blob: fa33c50b0e5a00cef1e560b0aa105034dd30e816 [file] [log] [blame]
Thomas Petazzonif6e916b2012-11-20 23:00:52 +01001config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -06005config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08008 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -06009 select MULTI_IRQ_HANDLER
10
Linus Walleija27d21e2015-12-18 10:44:53 +010011config ARM_GIC_MAX_NR
12 int
13 default 2 if ARCH_REALVIEW
14 default 1
15
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000016config ARM_GIC_V2M
17 bool
18 depends on ARM_GIC
19 depends on PCI && PCI_MSI
20 select PCI_MSI_IRQ_DOMAIN
21
Rob Herring81243e42012-11-20 21:21:40 -060022config GIC_NON_BANKED
23 bool
24
Marc Zyngier021f6532014-06-30 16:01:31 +010025config ARM_GIC_V3
26 bool
27 select IRQ_DOMAIN
28 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000029 select IRQ_DOMAIN_HIERARCHY
Marc Zyngiere3825ba2016-04-11 09:57:54 +010030 select PARTITION_PERCPU
Marc Zyngier021f6532014-06-30 16:01:31 +010031
Marc Zyngier19812722014-11-24 14:35:19 +000032config ARM_GIC_V3_ITS
33 bool
34 select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König292ec082013-06-26 09:18:48 +020035
Rob Herring44430ec2012-10-27 17:25:26 -050036config ARM_NVIC
37 bool
38 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020039 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050040 select GENERIC_IRQ_CHIP
41
42config ARM_VIC
43 bool
44 select IRQ_DOMAIN
45 select MULTI_IRQ_HANDLER
46
47config ARM_VIC_NR
48 int
49 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050050 default 2
51 depends on ARM_VIC
52 help
53 The maximum number of VICs available in the system, for
54 power management.
55
Thomas Petazzonifed6d332016-02-10 15:46:56 +010056config ARMADA_370_XP_IRQ
57 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +010058 select GENERIC_IRQ_CHIP
Thomas Petazzonifcc392d2016-02-10 15:46:57 +010059 select PCI_MSI_IRQ_DOMAIN if PCI_MSI
Thomas Petazzonifed6d332016-02-10 15:46:56 +010060
Antoine Tenarte6b78f22016-02-19 16:22:44 +010061config ALPINE_MSI
62 bool
63 depends on PCI && PCI_MSI
64 select GENERIC_IRQ_CHIP
65 select PCI_MSI_IRQ_DOMAIN
66
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020067config ATMEL_AIC_IRQ
68 bool
69 select GENERIC_IRQ_CHIP
70 select IRQ_DOMAIN
71 select MULTI_IRQ_HANDLER
72 select SPARSE_IRQ
73
74config ATMEL_AIC5_IRQ
75 bool
76 select GENERIC_IRQ_CHIP
77 select IRQ_DOMAIN
78 select MULTI_IRQ_HANDLER
79 select SPARSE_IRQ
80
Ralf Baechle0509cfd2015-07-08 14:46:08 +020081config I8259
82 bool
83 select IRQ_DOMAIN
84
Simon Arlottc7c42ec2015-11-22 14:30:14 +000085config BCM6345_L1_IRQ
86 bool
87 select GENERIC_IRQ_CHIP
88 select IRQ_DOMAIN
89
Kevin Cernekee5f7f0312014-12-25 09:49:06 -080090config BCM7038_L1_IRQ
91 bool
92 select GENERIC_IRQ_CHIP
93 select IRQ_DOMAIN
94
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -080095config BCM7120_L2_IRQ
96 bool
97 select GENERIC_IRQ_CHIP
98 select IRQ_DOMAIN
99
Florian Fainelli7f646e92014-05-23 17:40:53 -0700100config BRCMSTB_L2_IRQ
101 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700102 select GENERIC_IRQ_CHIP
103 select IRQ_DOMAIN
104
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200105config DW_APB_ICTL
106 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800107 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200108 select IRQ_DOMAIN
109
MaJun9a7c4ab2016-03-23 17:06:33 +0800110config HISILICON_IRQ_MBIGEN
111 bool
112 select ARM_GIC_V3
113 select ARM_GIC_V3_ITS
114 select GENERIC_MSI_IRQ_DOMAIN
115
James Hoganb6ef9162013-04-22 15:43:50 +0100116config IMGPDC_IRQ
117 bool
118 select GENERIC_IRQ_CHIP
119 select IRQ_DOMAIN
120
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200121config IRQ_MIPS_CPU
122 bool
123 select GENERIC_IRQ_CHIP
124 select IRQ_DOMAIN
125
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400126config CLPS711X_IRQCHIP
127 bool
128 depends on ARCH_CLPS711X
129 select IRQ_DOMAIN
130 select MULTI_IRQ_HANDLER
131 select SPARSE_IRQ
132 default y
133
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300134config OR1K_PIC
135 bool
136 select IRQ_DOMAIN
137
Felipe Balbi85980662014-09-15 16:15:02 -0500138config OMAP_IRQCHIP
139 bool
140 select GENERIC_IRQ_CHIP
141 select IRQ_DOMAIN
142
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200143config ORION_IRQCHIP
144 bool
145 select IRQ_DOMAIN
146 select MULTI_IRQ_HANDLER
147
Cristian Birsanaaa86662016-01-13 18:15:35 -0700148config PIC32_EVIC
149 bool
150 select GENERIC_IRQ_CHIP
151 select IRQ_DOMAIN
152
Magnus Damm44358042013-02-18 23:28:34 +0900153config RENESAS_INTC_IRQPIN
154 bool
155 select IRQ_DOMAIN
156
Magnus Dammfbc83b72013-02-27 17:15:01 +0900157config RENESAS_IRQC
158 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900159 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900160 select IRQ_DOMAIN
161
Lee Jones07088482015-02-18 15:13:58 +0000162config ST_IRQCHIP
163 bool
164 select REGMAP
165 select MFD_SYSCON
166 help
167 Enables SysCfg Controlled IRQs on STi based platforms.
168
Mans Rullgard4bba6682016-01-20 18:07:17 +0000169config TANGO_IRQ
170 bool
171 select IRQ_DOMAIN
172 select GENERIC_IRQ_CHIP
173
Christian Ruppertb06eb012013-06-25 18:29:57 +0200174config TB10X_IRQC
175 bool
176 select IRQ_DOMAIN
177 select GENERIC_IRQ_CHIP
178
Damien Riegeld01f8632015-12-21 15:11:23 -0500179config TS4800_IRQ
180 tristate "TS-4800 IRQ controller"
181 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100182 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100183 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500184 help
185 Support for the TS-4800 FPGA IRQ controller
186
Linus Walleij2389d502012-10-31 22:04:31 +0100187config VERSATILE_FPGA_IRQ
188 bool
189 select IRQ_DOMAIN
190
191config VERSATILE_FPGA_IRQ_NR
192 int
193 default 4
194 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400195
196config XTENSA_MX
197 bool
198 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530199
200config IRQ_CROSSBAR
201 bool
202 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900203 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530204 The primary irqchip invokes the crossbar's callback which inturn allocates
205 a free irq and configures the IP. Thus the peripheral interrupts are
206 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300207
208config KEYSTONE_IRQ
209 tristate "Keystone 2 IRQ controller IP"
210 depends on ARCH_KEYSTONE
211 help
212 Support for Texas Instruments Keystone 2 IRQ controller IP which
213 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700214
215config MIPS_GIC
216 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000217 select GENERIC_IRQ_IPI
Qais Yousef2af70a92015-12-08 13:20:23 +0000218 select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700219 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900220
Paul Burton44e08e72015-05-24 16:11:31 +0100221config INGENIC_IRQ
222 bool
223 depends on MACH_INGENIC
224 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700225
Yoshinori Sato8a764482015-05-10 02:30:47 +0900226config RENESAS_H8300H_INTC
227 bool
228 select IRQ_DOMAIN
229
230config RENESAS_H8S_INTC
231 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700232 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500233
234config IMX_GPCV2
235 bool
236 select IRQ_DOMAIN
237 help
238 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200239
240config IRQ_MXS
241 def_bool y if MACH_ASM9260 || ARCH_MXS
242 select IRQ_DOMAIN
243 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100244
245config MVEBU_ODMI
246 bool
247 select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100248
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800249config LS_SCFG_MSI
250 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
251 depends on PCI && PCI_MSI
252 select PCI_MSI_IRQ_DOMAIN
253
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100254config PARTITION_PERCPU
255 bool
Linus Torvalds0efacbb2016-05-19 09:46:18 -0700256
Noam Camus44df427c2015-10-29 00:26:22 +0200257config EZNPS_GIC
258 bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmannffd565e2016-05-12 23:03:35 +0200259 depends on ARC || (COMPILE_TEST && !64BIT)
Noam Camus44df427c2015-10-29 00:26:22 +0200260 select IRQ_DOMAIN
261 help
262 Support the EZchip NPS400 global interrupt controller