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gerrit-public.fairphone.software / kernel / msm-4.9 / 6fb11131ef3400364381661186a55a73b782c3be / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: b245e6cf633823879ff10af11439c235038bc85b [file] [log] [blame]
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]1/include/ "tegra30.dtsi"
2
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
30 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]31 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]32 };
33
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]34 pinmux {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]35 pinctrl-names = "default";
36 pinctrl-0 = <&state_default>;
37
38 state_default: pinmux {
39 sdmmc1_clk_pz0 {
40 nvidia,pins = "sdmmc1_clk_pz0";
41 nvidia,function = "sdmmc1";
42 nvidia,pull = <0>;
43 nvidia,tristate = <0>;
44 };
45 sdmmc1_cmd_pz1 {
46 nvidia,pins = "sdmmc1_cmd_pz1",
47 "sdmmc1_dat0_py7",
48 "sdmmc1_dat1_py6",
49 "sdmmc1_dat2_py5",
50 "sdmmc1_dat3_py4";
51 nvidia,function = "sdmmc1";
52 nvidia,pull = <2>;
53 nvidia,tristate = <0>;
54 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame^]55 sdmmc3_clk_pa6 {
56 nvidia,pins = "sdmmc3_clk_pa6";
57 nvidia,function = "sdmmc3";
58 nvidia,pull = <0>;
59 nvidia,tristate = <0>;
60 };
61 sdmmc3_cmd_pa7 {
62 nvidia,pins = "sdmmc3_cmd_pa7",
63 "sdmmc3_dat0_pb7",
64 "sdmmc3_dat1_pb6",
65 "sdmmc3_dat2_pb5",
66 "sdmmc3_dat3_pb4";
67 nvidia,function = "sdmmc3";
68 nvidia,pull = <2>;
69 nvidia,tristate = <0>;
70 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]71 sdmmc4_clk_pcc4 {
72 nvidia,pins = "sdmmc4_clk_pcc4",
73 "sdmmc4_rst_n_pcc3";
74 nvidia,function = "sdmmc4";
75 nvidia,pull = <0>;
76 nvidia,tristate = <0>;
77 };
78 sdmmc4_dat0_paa0 {
79 nvidia,pins = "sdmmc4_dat0_paa0",
80 "sdmmc4_dat1_paa1",
81 "sdmmc4_dat2_paa2",
82 "sdmmc4_dat3_paa3",
83 "sdmmc4_dat4_paa4",
84 "sdmmc4_dat5_paa5",
85 "sdmmc4_dat6_paa6",
86 "sdmmc4_dat7_paa7";
87 nvidia,function = "sdmmc4";
88 nvidia,pull = <2>;
89 nvidia,tristate = <0>;
90 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]91 dap2_fs_pa2 {
92 nvidia,pins = "dap2_fs_pa2",
93 "dap2_sclk_pa3",
94 "dap2_din_pa4",
95 "dap2_dout_pa5";
96 nvidia,function = "i2s1";
97 nvidia,pull = <0>;
98 nvidia,tristate = <0>;
99 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame^]100 sdio3 {
101 nvidia,pins = "drive_sdio3";
102 nvidia,high-speed-mode = <0>;
103 nvidia,schmitt = <0>;
104 nvidia,pull-down-strength = <46>;
105 nvidia,pull-up-strength = <42>;
106 nvidia,slew-rate-rising = <1>;
107 nvidia,slew-rate-falling = <1>;
108 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]109 };
110 };
111
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]112 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]113 status = "okay";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]114 clock-frequency = <408000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]115 };
116
117 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]118 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]119 clock-frequency = <100000>;
120 };
121
122 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]123 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]124 clock-frequency = <100000>;
125 };
126
127 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]128 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]129 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]130
131 /* ALS and Proximity sensor */
132 isl29028@44 {
133 compatible = "isil,isl29028";
134 reg = <0x44>;
135 interrupt-parent = <&gpio>;
136 interrupts = <88 0x04>; /*gpio PL0 */
137 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]138 };
139
140 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]141 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]142 clock-frequency = <100000>;
143 };
144
145 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]146 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]147 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]148
149 wm8903: wm8903@1a {
150 compatible = "wlf,wm8903";
151 reg = <0x1a>;
152 interrupt-parent = <&gpio>;
153 interrupts = <179 0x04>; /* gpio PW3 */
154
155 gpio-controller;
156 #gpio-cells = <2>;
157
158 micdet-cfg = <0>;
159 micdet-delay = <100>;
160 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
161 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]162
163 tps62361 {
164 compatible = "ti,tps62361";
165 reg = <0x60>;
166
167 regulator-name = "tps62361-vout";
168 regulator-min-microvolt = <500000>;
169 regulator-max-microvolt = <1500000>;
170 regulator-boot-on;
171 regulator-always-on;
172 ti,vsel0-state-high;
173 ti,vsel1-state-high;
174 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]175
176 pmic: tps65911@2d {
177 compatible = "ti,tps65911";
178 reg = <0x2d>;
179
180 interrupts = <0 86 0x4>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
183
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]184 ti,system-power-controller;
185
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]186 #gpio-cells = <2>;
187 gpio-controller;
188
189 vcc1-supply = <&vdd_ac_bat_reg>;
190 vcc2-supply = <&vdd_ac_bat_reg>;
191 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]192 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]193 vcc5-supply = <&vdd_ac_bat_reg>;
194 vcc6-supply = <&vdd2_reg>;
195 vcc7-supply = <&vdd_ac_bat_reg>;
196 vccio-supply = <&vdd_ac_bat_reg>;
197
198 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]199 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]200 regulator-name = "vddio_ddr_1v2";
201 regulator-min-microvolt = <1200000>;
202 regulator-max-microvolt = <1200000>;
203 regulator-always-on;
204 };
205
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]206 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]207 regulator-name = "vdd_1v5_gen";
208 regulator-min-microvolt = <1500000>;
209 regulator-max-microvolt = <1500000>;
210 regulator-always-on;
211 };
212
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]213 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]214 regulator-name = "vdd_cpu,vdd_sys";
215 regulator-min-microvolt = <1000000>;
216 regulator-max-microvolt = <1000000>;
217 regulator-always-on;
218 };
219
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]220 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]221 regulator-name = "vdd_1v8_gen";
222 regulator-min-microvolt = <1800000>;
223 regulator-max-microvolt = <1800000>;
224 regulator-always-on;
225 };
226
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]227 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]228 regulator-name = "vdd_pexa,vdd_pexb";
229 regulator-min-microvolt = <1050000>;
230 regulator-max-microvolt = <1050000>;
231 };
232
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]233 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]234 regulator-name = "vdd_sata,avdd_plle";
235 regulator-min-microvolt = <1050000>;
236 regulator-max-microvolt = <1050000>;
237 };
238
239 /* LDO3 is not connected to anything */
240
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]241 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]242 regulator-name = "vdd_rtc";
243 regulator-min-microvolt = <1200000>;
244 regulator-max-microvolt = <1200000>;
245 regulator-always-on;
246 };
247
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]248 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]249 regulator-name = "vddio_sdmmc,avdd_vdac";
250 regulator-min-microvolt = <3300000>;
251 regulator-max-microvolt = <3300000>;
252 regulator-always-on;
253 };
254
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]255 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]256 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
257 regulator-min-microvolt = <1200000>;
258 regulator-max-microvolt = <1200000>;
259 };
260
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]261 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]262 regulator-name = "vdd_pllm,x,u,a_p_c_s";
263 regulator-min-microvolt = <1200000>;
264 regulator-max-microvolt = <1200000>;
265 regulator-always-on;
266 };
267
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]268 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]269 regulator-name = "vdd_ddr_hs";
270 regulator-min-microvolt = <1000000>;
271 regulator-max-microvolt = <1000000>;
272 regulator-always-on;
273 };
274 };
275 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]276 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]277
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]278 ahub {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]279 i2s@70080400 {
280 status = "okay";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]281 };
282 };
283
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]284 pmc {
285 status = "okay";
286 nvidia,invert-interrupt;
287 };
288
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]289 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]290 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]291 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
292 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
293 power-gpios = <&gpio 31 0>; /* gpio PD7 */
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]294 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]295 };
296
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]297 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]298 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]299 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]300 };
301
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]302 regulators {
303 compatible = "simple-bus";
304 #address-cells = <1>;
305 #size-cells = <0>;
306
307 vdd_ac_bat_reg: regulator@0 {
308 compatible = "regulator-fixed";
309 reg = <0>;
310 regulator-name = "vdd_ac_bat";
311 regulator-min-microvolt = <5000000>;
312 regulator-max-microvolt = <5000000>;
313 regulator-always-on;
314 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]315
316 cam_1v8_reg: regulator@1 {
317 compatible = "regulator-fixed";
318 reg = <1>;
319 regulator-name = "cam_1v8";
320 regulator-min-microvolt = <1800000>;
321 regulator-max-microvolt = <1800000>;
322 enable-active-high;
323 gpio = <&gpio 220 0>; /* gpio PBB4 */
324 vin-supply = <&vio_reg>;
325 };
326
327 cp_5v_reg: regulator@2 {
328 compatible = "regulator-fixed";
329 reg = <2>;
330 regulator-name = "cp_5v";
331 regulator-min-microvolt = <5000000>;
332 regulator-max-microvolt = <5000000>;
333 regulator-boot-on;
334 regulator-always-on;
335 enable-active-high;
336 gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
337 };
338
339 emmc_3v3_reg: regulator@3 {
340 compatible = "regulator-fixed";
341 reg = <3>;
342 regulator-name = "emmc_3v3";
343 regulator-min-microvolt = <3300000>;
344 regulator-max-microvolt = <3300000>;
345 regulator-always-on;
346 regulator-boot-on;
347 enable-active-high;
348 gpio = <&gpio 25 0>; /* gpio PD1 */
349 vin-supply = <&sys_3v3_reg>;
350 };
351
352 modem_3v3_reg: regulator@4 {
353 compatible = "regulator-fixed";
354 reg = <4>;
355 regulator-name = "modem_3v3";
356 regulator-min-microvolt = <3300000>;
357 regulator-max-microvolt = <3300000>;
358 enable-active-high;
359 gpio = <&gpio 30 0>; /* gpio PD6 */
360 };
361
362 pex_hvdd_3v3_reg: regulator@5 {
363 compatible = "regulator-fixed";
364 reg = <5>;
365 regulator-name = "pex_hvdd_3v3";
366 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>;
368 enable-active-high;
369 gpio = <&gpio 95 0>; /* gpio PL7 */
370 vin-supply = <&sys_3v3_reg>;
371 };
372
373 vdd_cam1_ldo_reg: regulator@6 {
374 compatible = "regulator-fixed";
375 reg = <6>;
376 regulator-name = "vdd_cam1_ldo";
377 regulator-min-microvolt = <2800000>;
378 regulator-max-microvolt = <2800000>;
379 enable-active-high;
380 gpio = <&gpio 142 0>; /* gpio PR6 */
381 vin-supply = <&sys_3v3_reg>;
382 };
383
384 vdd_cam2_ldo_reg: regulator@7 {
385 compatible = "regulator-fixed";
386 reg = <7>;
387 regulator-name = "vdd_cam2_ldo";
388 regulator-min-microvolt = <2800000>;
389 regulator-max-microvolt = <2800000>;
390 enable-active-high;
391 gpio = <&gpio 143 0>; /* gpio PR7 */
392 vin-supply = <&sys_3v3_reg>;
393 };
394
395 vdd_cam3_ldo_reg: regulator@8 {
396 compatible = "regulator-fixed";
397 reg = <8>;
398 regulator-name = "vdd_cam3_ldo";
399 regulator-min-microvolt = <3300000>;
400 regulator-max-microvolt = <3300000>;
401 enable-active-high;
402 gpio = <&gpio 144 0>; /* gpio PS0 */
403 vin-supply = <&sys_3v3_reg>;
404 };
405
406 vdd_com_reg: regulator@9 {
407 compatible = "regulator-fixed";
408 reg = <9>;
409 regulator-name = "vdd_com";
410 regulator-min-microvolt = <3300000>;
411 regulator-max-microvolt = <3300000>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame^]412 regulator-always-on;
413 regulator-boot-on;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]414 enable-active-high;
415 gpio = <&gpio 24 0>; /* gpio PD0 */
416 vin-supply = <&sys_3v3_reg>;
417 };
418
419 vdd_fuse_3v3_reg: regulator@10 {
420 compatible = "regulator-fixed";
421 reg = <10>;
422 regulator-name = "vdd_fuse_3v3";
423 regulator-min-microvolt = <3300000>;
424 regulator-max-microvolt = <3300000>;
425 enable-active-high;
426 gpio = <&gpio 94 0>; /* gpio PL6 */
427 vin-supply = <&sys_3v3_reg>;
428 };
429
430 vdd_pnl1_reg: regulator@11 {
431 compatible = "regulator-fixed";
432 reg = <11>;
433 regulator-name = "vdd_pnl1";
434 regulator-min-microvolt = <3300000>;
435 regulator-max-microvolt = <3300000>;
436 regulator-always-on;
437 regulator-boot-on;
438 enable-active-high;
439 gpio = <&gpio 92 0>; /* gpio PL4 */
440 vin-supply = <&sys_3v3_reg>;
441 };
442
443 vdd_vid_reg: regulator@12 {
444 compatible = "regulator-fixed";
445 reg = <12>;
446 regulator-name = "vddio_vid";
447 regulator-min-microvolt = <5000000>;
448 regulator-max-microvolt = <5000000>;
449 enable-active-high;
450 gpio = <&gpio 152 0>; /* GPIO PT0 */
451 gpio-open-drain;
452 vin-supply = <&vdd_5v0_reg>;
453 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]454 };
455
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]456 sound {
457 compatible = "nvidia,tegra-audio-wm8903-cardhu",
458 "nvidia,tegra-audio-wm8903";
459 nvidia,model = "NVIDIA Tegra Cardhu";
460
461 nvidia,audio-routing =
462 "Headphone Jack", "HPOUTR",
463 "Headphone Jack", "HPOUTL",
464 "Int Spk", "ROP",
465 "Int Spk", "RON",
466 "Int Spk", "LOP",
467 "Int Spk", "LON",
468 "Mic Jack", "MICBIAS",
469 "IN1L", "Mic Jack";
470
471 nvidia,i2s-controller = <&tegra_i2s1>;
472 nvidia,audio-codec = <&wm8903>;
473
474 nvidia,spkr-en-gpios = <&wm8903 2 0>;
475 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
476 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]477};