R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | #include <dt-bindings/pinctrl/dra.h> |
| 12 | |
| 13 | #include "skeleton.dtsi" |
| 14 | |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 15 | #define MAX_SOURCES 400 |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 16 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 17 | / { |
| 18 | #address-cells = <1>; |
| 19 | #size-cells = <1>; |
| 20 | |
| 21 | compatible = "ti,dra7xx"; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 22 | interrupt-parent = <&crossbar_mpu>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 23 | |
| 24 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 25 | i2c0 = &i2c1; |
| 26 | i2c1 = &i2c2; |
| 27 | i2c2 = &i2c3; |
| 28 | i2c3 = &i2c4; |
| 29 | i2c4 = &i2c5; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 30 | serial0 = &uart1; |
| 31 | serial1 = &uart2; |
| 32 | serial2 = &uart3; |
| 33 | serial3 = &uart4; |
| 34 | serial4 = &uart5; |
| 35 | serial5 = &uart6; |
Nishanth Menon | 065bd7f | 2014-10-21 11:18:15 -0500 | [diff] [blame] | 36 | serial6 = &uart7; |
| 37 | serial7 = &uart8; |
| 38 | serial8 = &uart9; |
| 39 | serial9 = &uart10; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 40 | ethernet0 = &cpsw_emac0; |
| 41 | ethernet1 = &cpsw_emac1; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 42 | d_can0 = &dcan1; |
| 43 | d_can1 = &dcan2; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 44 | }; |
| 45 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 46 | timer { |
| 47 | compatible = "arm,armv7-timer"; |
| 48 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 49 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 50 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 51 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 52 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 53 | }; |
| 54 | |
| 55 | gic: interrupt-controller@48211000 { |
| 56 | compatible = "arm,cortex-a15-gic"; |
| 57 | interrupt-controller; |
| 58 | #interrupt-cells = <3>; |
| 59 | reg = <0x48211000 0x1000>, |
| 60 | <0x48212000 0x1000>, |
| 61 | <0x48214000 0x2000>, |
| 62 | <0x48216000 0x2000>; |
| 63 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 64 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 65 | }; |
| 66 | |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame^] | 67 | wakeupgen: interrupt-controller@48281000 { |
| 68 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; |
| 69 | interrupt-controller; |
| 70 | #interrupt-cells = <3>; |
| 71 | reg = <0x48281000 0x1000>; |
| 72 | interrupt-parent = <&gic>; |
| 73 | }; |
| 74 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 75 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 76 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 77 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 78 | */ |
| 79 | soc { |
| 80 | compatible = "ti,omap-infra"; |
| 81 | mpu { |
| 82 | compatible = "ti,omap5-mpu"; |
| 83 | ti,hwmods = "mpu"; |
| 84 | }; |
| 85 | }; |
| 86 | |
| 87 | /* |
| 88 | * XXX: Use a flat representation of the SOC interconnect. |
| 89 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 90 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 91 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 92 | * hierarchy. |
| 93 | */ |
| 94 | ocp { |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 95 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 96 | #address-cells = <1>; |
| 97 | #size-cells = <1>; |
| 98 | ranges; |
| 99 | ti,hwmods = "l3_main_1", "l3_main_2"; |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 100 | reg = <0x44000000 0x1000000>, |
| 101 | <0x45000000 0x1000>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 102 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame^] | 103 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 104 | |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 105 | prm: prm@4ae06000 { |
| 106 | compatible = "ti,dra7-prm"; |
| 107 | reg = <0x4ae06000 0x3000>; |
Nishanth Menon | 5081ce6 | 2014-08-22 09:03:50 -0500 | [diff] [blame] | 108 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 109 | |
| 110 | prm_clocks: clocks { |
| 111 | #address-cells = <1>; |
| 112 | #size-cells = <0>; |
| 113 | }; |
| 114 | |
| 115 | prm_clockdomains: clockdomains { |
| 116 | }; |
| 117 | }; |
| 118 | |
Kishon Vijay Abraham I | 18dcd79 | 2014-07-14 16:12:23 +0530 | [diff] [blame] | 119 | axi@0 { |
| 120 | compatible = "simple-bus"; |
| 121 | #size-cells = <1>; |
| 122 | #address-cells = <1>; |
| 123 | ranges = <0x51000000 0x51000000 0x3000 |
| 124 | 0x0 0x20000000 0x10000000>; |
| 125 | pcie@51000000 { |
| 126 | compatible = "ti,dra7-pcie"; |
| 127 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; |
| 128 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 129 | interrupts = <0 232 0x4>, <0 233 0x4>; |
| 130 | #address-cells = <3>; |
| 131 | #size-cells = <2>; |
| 132 | device_type = "pci"; |
| 133 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 134 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; |
| 135 | #interrupt-cells = <1>; |
| 136 | num-lanes = <1>; |
| 137 | ti,hwmods = "pcie1"; |
| 138 | phys = <&pcie1_phy>; |
| 139 | phy-names = "pcie-phy0"; |
| 140 | interrupt-map-mask = <0 0 0 7>; |
| 141 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, |
| 142 | <0 0 0 2 &pcie1_intc 2>, |
| 143 | <0 0 0 3 &pcie1_intc 3>, |
| 144 | <0 0 0 4 &pcie1_intc 4>; |
| 145 | pcie1_intc: interrupt-controller { |
| 146 | interrupt-controller; |
| 147 | #address-cells = <0>; |
| 148 | #interrupt-cells = <1>; |
| 149 | }; |
| 150 | }; |
| 151 | }; |
| 152 | |
| 153 | axi@1 { |
| 154 | compatible = "simple-bus"; |
| 155 | #size-cells = <1>; |
| 156 | #address-cells = <1>; |
| 157 | ranges = <0x51800000 0x51800000 0x3000 |
| 158 | 0x0 0x30000000 0x10000000>; |
| 159 | status = "disabled"; |
| 160 | pcie@51000000 { |
| 161 | compatible = "ti,dra7-pcie"; |
| 162 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; |
| 163 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 164 | interrupts = <0 355 0x4>, <0 356 0x4>; |
| 165 | #address-cells = <3>; |
| 166 | #size-cells = <2>; |
| 167 | device_type = "pci"; |
| 168 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 169 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; |
| 170 | #interrupt-cells = <1>; |
| 171 | num-lanes = <1>; |
| 172 | ti,hwmods = "pcie2"; |
| 173 | phys = <&pcie2_phy>; |
| 174 | phy-names = "pcie-phy0"; |
| 175 | interrupt-map-mask = <0 0 0 7>; |
| 176 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, |
| 177 | <0 0 0 2 &pcie2_intc 2>, |
| 178 | <0 0 0 3 &pcie2_intc 3>, |
| 179 | <0 0 0 4 &pcie2_intc 4>; |
| 180 | pcie2_intc: interrupt-controller { |
| 181 | interrupt-controller; |
| 182 | #address-cells = <0>; |
| 183 | #interrupt-cells = <1>; |
| 184 | }; |
| 185 | }; |
| 186 | }; |
| 187 | |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 188 | cm_core_aon: cm_core_aon@4a005000 { |
| 189 | compatible = "ti,dra7-cm-core-aon"; |
| 190 | reg = <0x4a005000 0x2000>; |
| 191 | |
| 192 | cm_core_aon_clocks: clocks { |
| 193 | #address-cells = <1>; |
| 194 | #size-cells = <0>; |
| 195 | }; |
| 196 | |
| 197 | cm_core_aon_clockdomains: clockdomains { |
| 198 | }; |
| 199 | }; |
| 200 | |
| 201 | cm_core: cm_core@4a008000 { |
| 202 | compatible = "ti,dra7-cm-core"; |
| 203 | reg = <0x4a008000 0x3000>; |
| 204 | |
| 205 | cm_core_clocks: clocks { |
| 206 | #address-cells = <1>; |
| 207 | #size-cells = <0>; |
| 208 | }; |
| 209 | |
| 210 | cm_core_clockdomains: clockdomains { |
| 211 | }; |
| 212 | }; |
| 213 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 214 | counter32k: counter@4ae04000 { |
| 215 | compatible = "ti,omap-counter32k"; |
| 216 | reg = <0x4ae04000 0x40>; |
| 217 | ti,hwmods = "counter_32k"; |
| 218 | }; |
| 219 | |
Roger Quadros | ae3c0f7 | 2014-09-03 17:21:45 +0300 | [diff] [blame] | 220 | dra7_ctrl_core: ctrl_core@4a002000 { |
| 221 | compatible = "syscon"; |
| 222 | reg = <0x4a002000 0x6d0>; |
| 223 | }; |
| 224 | |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 225 | dra7_ctrl_general: tisyscon@4a002e00 { |
| 226 | compatible = "syscon"; |
| 227 | reg = <0x4a002e00 0x7c>; |
| 228 | }; |
| 229 | |
| 230 | pbias_regulator: pbias_regulator { |
| 231 | compatible = "ti,pbias-omap"; |
| 232 | reg = <0 0x4>; |
| 233 | syscon = <&dra7_ctrl_general>; |
| 234 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 235 | regulator-name = "pbias_mmc_omap5"; |
| 236 | regulator-min-microvolt = <1800000>; |
| 237 | regulator-max-microvolt = <3000000>; |
| 238 | }; |
| 239 | }; |
| 240 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 241 | dra7_pmx_core: pinmux@4a003400 { |
Nishanth Menon | 817c037 | 2014-05-22 23:47:46 -0500 | [diff] [blame] | 242 | compatible = "ti,dra7-padconf", "pinctrl-single"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 243 | reg = <0x4a003400 0x0464>; |
| 244 | #address-cells = <1>; |
| 245 | #size-cells = <0>; |
Nishanth Menon | 817c037 | 2014-05-22 23:47:46 -0500 | [diff] [blame] | 246 | #interrupt-cells = <1>; |
| 247 | interrupt-controller; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 248 | pinctrl-single,register-width = <32>; |
| 249 | pinctrl-single,function-mask = <0x3fffffff>; |
| 250 | }; |
| 251 | |
| 252 | sdma: dma-controller@4a056000 { |
| 253 | compatible = "ti,omap4430-sdma"; |
| 254 | reg = <0x4a056000 0x1000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 255 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 256 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 257 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 258 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 259 | #dma-cells = <1>; |
| 260 | #dma-channels = <32>; |
| 261 | #dma-requests = <127>; |
| 262 | }; |
| 263 | |
| 264 | gpio1: gpio@4ae10000 { |
| 265 | compatible = "ti,omap4-gpio"; |
| 266 | reg = <0x4ae10000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 267 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 268 | ti,hwmods = "gpio1"; |
| 269 | gpio-controller; |
| 270 | #gpio-cells = <2>; |
| 271 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 272 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 273 | }; |
| 274 | |
| 275 | gpio2: gpio@48055000 { |
| 276 | compatible = "ti,omap4-gpio"; |
| 277 | reg = <0x48055000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 278 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 279 | ti,hwmods = "gpio2"; |
| 280 | gpio-controller; |
| 281 | #gpio-cells = <2>; |
| 282 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 283 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 284 | }; |
| 285 | |
| 286 | gpio3: gpio@48057000 { |
| 287 | compatible = "ti,omap4-gpio"; |
| 288 | reg = <0x48057000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 289 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 290 | ti,hwmods = "gpio3"; |
| 291 | gpio-controller; |
| 292 | #gpio-cells = <2>; |
| 293 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 294 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 295 | }; |
| 296 | |
| 297 | gpio4: gpio@48059000 { |
| 298 | compatible = "ti,omap4-gpio"; |
| 299 | reg = <0x48059000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 300 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 301 | ti,hwmods = "gpio4"; |
| 302 | gpio-controller; |
| 303 | #gpio-cells = <2>; |
| 304 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 305 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 306 | }; |
| 307 | |
| 308 | gpio5: gpio@4805b000 { |
| 309 | compatible = "ti,omap4-gpio"; |
| 310 | reg = <0x4805b000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 311 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 312 | ti,hwmods = "gpio5"; |
| 313 | gpio-controller; |
| 314 | #gpio-cells = <2>; |
| 315 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 316 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 317 | }; |
| 318 | |
| 319 | gpio6: gpio@4805d000 { |
| 320 | compatible = "ti,omap4-gpio"; |
| 321 | reg = <0x4805d000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 322 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 323 | ti,hwmods = "gpio6"; |
| 324 | gpio-controller; |
| 325 | #gpio-cells = <2>; |
| 326 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 327 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | gpio7: gpio@48051000 { |
| 331 | compatible = "ti,omap4-gpio"; |
| 332 | reg = <0x48051000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 333 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 334 | ti,hwmods = "gpio7"; |
| 335 | gpio-controller; |
| 336 | #gpio-cells = <2>; |
| 337 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 338 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 339 | }; |
| 340 | |
| 341 | gpio8: gpio@48053000 { |
| 342 | compatible = "ti,omap4-gpio"; |
| 343 | reg = <0x48053000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 344 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 345 | ti,hwmods = "gpio8"; |
| 346 | gpio-controller; |
| 347 | #gpio-cells = <2>; |
| 348 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 349 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 350 | }; |
| 351 | |
| 352 | uart1: serial@4806a000 { |
| 353 | compatible = "ti,omap4-uart"; |
| 354 | reg = <0x4806a000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 355 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 356 | ti,hwmods = "uart1"; |
| 357 | clock-frequency = <48000000>; |
| 358 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 359 | dmas = <&sdma 49>, <&sdma 50>; |
| 360 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 361 | }; |
| 362 | |
| 363 | uart2: serial@4806c000 { |
| 364 | compatible = "ti,omap4-uart"; |
| 365 | reg = <0x4806c000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 366 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 367 | ti,hwmods = "uart2"; |
| 368 | clock-frequency = <48000000>; |
| 369 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 370 | dmas = <&sdma 51>, <&sdma 52>; |
| 371 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 372 | }; |
| 373 | |
| 374 | uart3: serial@48020000 { |
| 375 | compatible = "ti,omap4-uart"; |
| 376 | reg = <0x48020000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 377 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 378 | ti,hwmods = "uart3"; |
| 379 | clock-frequency = <48000000>; |
| 380 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 381 | dmas = <&sdma 53>, <&sdma 54>; |
| 382 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 383 | }; |
| 384 | |
| 385 | uart4: serial@4806e000 { |
| 386 | compatible = "ti,omap4-uart"; |
| 387 | reg = <0x4806e000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 388 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 389 | ti,hwmods = "uart4"; |
| 390 | clock-frequency = <48000000>; |
| 391 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 392 | dmas = <&sdma 55>, <&sdma 56>; |
| 393 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 394 | }; |
| 395 | |
| 396 | uart5: serial@48066000 { |
| 397 | compatible = "ti,omap4-uart"; |
| 398 | reg = <0x48066000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 399 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 400 | ti,hwmods = "uart5"; |
| 401 | clock-frequency = <48000000>; |
| 402 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 403 | dmas = <&sdma 63>, <&sdma 64>; |
| 404 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 405 | }; |
| 406 | |
| 407 | uart6: serial@48068000 { |
| 408 | compatible = "ti,omap4-uart"; |
| 409 | reg = <0x48068000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 410 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 411 | ti,hwmods = "uart6"; |
| 412 | clock-frequency = <48000000>; |
| 413 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 414 | dmas = <&sdma 79>, <&sdma 80>; |
| 415 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 416 | }; |
| 417 | |
| 418 | uart7: serial@48420000 { |
| 419 | compatible = "ti,omap4-uart"; |
| 420 | reg = <0x48420000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 421 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 422 | ti,hwmods = "uart7"; |
| 423 | clock-frequency = <48000000>; |
| 424 | status = "disabled"; |
| 425 | }; |
| 426 | |
| 427 | uart8: serial@48422000 { |
| 428 | compatible = "ti,omap4-uart"; |
| 429 | reg = <0x48422000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 430 | interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 431 | ti,hwmods = "uart8"; |
| 432 | clock-frequency = <48000000>; |
| 433 | status = "disabled"; |
| 434 | }; |
| 435 | |
| 436 | uart9: serial@48424000 { |
| 437 | compatible = "ti,omap4-uart"; |
| 438 | reg = <0x48424000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 439 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 440 | ti,hwmods = "uart9"; |
| 441 | clock-frequency = <48000000>; |
| 442 | status = "disabled"; |
| 443 | }; |
| 444 | |
| 445 | uart10: serial@4ae2b000 { |
| 446 | compatible = "ti,omap4-uart"; |
| 447 | reg = <0x4ae2b000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 448 | interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 449 | ti,hwmods = "uart10"; |
| 450 | clock-frequency = <48000000>; |
| 451 | status = "disabled"; |
| 452 | }; |
| 453 | |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 454 | mailbox1: mailbox@4a0f4000 { |
| 455 | compatible = "ti,omap4-mailbox"; |
| 456 | reg = <0x4a0f4000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 457 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| 458 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 459 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 460 | ti,hwmods = "mailbox1"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 461 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 462 | ti,mbox-num-users = <3>; |
| 463 | ti,mbox-num-fifos = <8>; |
| 464 | status = "disabled"; |
| 465 | }; |
| 466 | |
| 467 | mailbox2: mailbox@4883a000 { |
| 468 | compatible = "ti,omap4-mailbox"; |
| 469 | reg = <0x4883a000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 470 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| 471 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
| 472 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, |
| 473 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 474 | ti,hwmods = "mailbox2"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 475 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 476 | ti,mbox-num-users = <4>; |
| 477 | ti,mbox-num-fifos = <12>; |
| 478 | status = "disabled"; |
| 479 | }; |
| 480 | |
| 481 | mailbox3: mailbox@4883c000 { |
| 482 | compatible = "ti,omap4-mailbox"; |
| 483 | reg = <0x4883c000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 484 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
| 485 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, |
| 486 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, |
| 487 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 488 | ti,hwmods = "mailbox3"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 489 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 490 | ti,mbox-num-users = <4>; |
| 491 | ti,mbox-num-fifos = <12>; |
| 492 | status = "disabled"; |
| 493 | }; |
| 494 | |
| 495 | mailbox4: mailbox@4883e000 { |
| 496 | compatible = "ti,omap4-mailbox"; |
| 497 | reg = <0x4883e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 498 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| 499 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| 500 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| 501 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 502 | ti,hwmods = "mailbox4"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 503 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 504 | ti,mbox-num-users = <4>; |
| 505 | ti,mbox-num-fifos = <12>; |
| 506 | status = "disabled"; |
| 507 | }; |
| 508 | |
| 509 | mailbox5: mailbox@48840000 { |
| 510 | compatible = "ti,omap4-mailbox"; |
| 511 | reg = <0x48840000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 512 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| 513 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| 514 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| 515 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 516 | ti,hwmods = "mailbox5"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 517 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 518 | ti,mbox-num-users = <4>; |
| 519 | ti,mbox-num-fifos = <12>; |
| 520 | status = "disabled"; |
| 521 | }; |
| 522 | |
| 523 | mailbox6: mailbox@48842000 { |
| 524 | compatible = "ti,omap4-mailbox"; |
| 525 | reg = <0x48842000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 526 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 527 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| 528 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| 529 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 530 | ti,hwmods = "mailbox6"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 531 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 532 | ti,mbox-num-users = <4>; |
| 533 | ti,mbox-num-fifos = <12>; |
| 534 | status = "disabled"; |
| 535 | }; |
| 536 | |
| 537 | mailbox7: mailbox@48844000 { |
| 538 | compatible = "ti,omap4-mailbox"; |
| 539 | reg = <0x48844000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 540 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| 541 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| 542 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, |
| 543 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 544 | ti,hwmods = "mailbox7"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 545 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 546 | ti,mbox-num-users = <4>; |
| 547 | ti,mbox-num-fifos = <12>; |
| 548 | status = "disabled"; |
| 549 | }; |
| 550 | |
| 551 | mailbox8: mailbox@48846000 { |
| 552 | compatible = "ti,omap4-mailbox"; |
| 553 | reg = <0x48846000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 554 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| 555 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| 556 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, |
| 557 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 558 | ti,hwmods = "mailbox8"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 559 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 560 | ti,mbox-num-users = <4>; |
| 561 | ti,mbox-num-fifos = <12>; |
| 562 | status = "disabled"; |
| 563 | }; |
| 564 | |
| 565 | mailbox9: mailbox@4885e000 { |
| 566 | compatible = "ti,omap4-mailbox"; |
| 567 | reg = <0x4885e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 568 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| 569 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| 570 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, |
| 571 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 572 | ti,hwmods = "mailbox9"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 573 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 574 | ti,mbox-num-users = <4>; |
| 575 | ti,mbox-num-fifos = <12>; |
| 576 | status = "disabled"; |
| 577 | }; |
| 578 | |
| 579 | mailbox10: mailbox@48860000 { |
| 580 | compatible = "ti,omap4-mailbox"; |
| 581 | reg = <0x48860000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 582 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| 583 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, |
| 584 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, |
| 585 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 586 | ti,hwmods = "mailbox10"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 587 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 588 | ti,mbox-num-users = <4>; |
| 589 | ti,mbox-num-fifos = <12>; |
| 590 | status = "disabled"; |
| 591 | }; |
| 592 | |
| 593 | mailbox11: mailbox@48862000 { |
| 594 | compatible = "ti,omap4-mailbox"; |
| 595 | reg = <0x48862000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 596 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
| 597 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| 598 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, |
| 599 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 600 | ti,hwmods = "mailbox11"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 601 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 602 | ti,mbox-num-users = <4>; |
| 603 | ti,mbox-num-fifos = <12>; |
| 604 | status = "disabled"; |
| 605 | }; |
| 606 | |
| 607 | mailbox12: mailbox@48864000 { |
| 608 | compatible = "ti,omap4-mailbox"; |
| 609 | reg = <0x48864000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 610 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
| 611 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, |
| 612 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| 613 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 614 | ti,hwmods = "mailbox12"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 615 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 616 | ti,mbox-num-users = <4>; |
| 617 | ti,mbox-num-fifos = <12>; |
| 618 | status = "disabled"; |
| 619 | }; |
| 620 | |
| 621 | mailbox13: mailbox@48802000 { |
| 622 | compatible = "ti,omap4-mailbox"; |
| 623 | reg = <0x48802000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 624 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| 625 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
| 626 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, |
| 627 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 628 | ti,hwmods = "mailbox13"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 629 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 630 | ti,mbox-num-users = <4>; |
| 631 | ti,mbox-num-fifos = <12>; |
| 632 | status = "disabled"; |
| 633 | }; |
| 634 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 635 | timer1: timer@4ae18000 { |
| 636 | compatible = "ti,omap5430-timer"; |
| 637 | reg = <0x4ae18000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 638 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 639 | ti,hwmods = "timer1"; |
| 640 | ti,timer-alwon; |
| 641 | }; |
| 642 | |
| 643 | timer2: timer@48032000 { |
| 644 | compatible = "ti,omap5430-timer"; |
| 645 | reg = <0x48032000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 646 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 647 | ti,hwmods = "timer2"; |
| 648 | }; |
| 649 | |
| 650 | timer3: timer@48034000 { |
| 651 | compatible = "ti,omap5430-timer"; |
| 652 | reg = <0x48034000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 653 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 654 | ti,hwmods = "timer3"; |
| 655 | }; |
| 656 | |
| 657 | timer4: timer@48036000 { |
| 658 | compatible = "ti,omap5430-timer"; |
| 659 | reg = <0x48036000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 660 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 661 | ti,hwmods = "timer4"; |
| 662 | }; |
| 663 | |
| 664 | timer5: timer@48820000 { |
| 665 | compatible = "ti,omap5430-timer"; |
| 666 | reg = <0x48820000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 667 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 668 | ti,hwmods = "timer5"; |
| 669 | ti,timer-dsp; |
| 670 | }; |
| 671 | |
| 672 | timer6: timer@48822000 { |
| 673 | compatible = "ti,omap5430-timer"; |
| 674 | reg = <0x48822000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 675 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 676 | ti,hwmods = "timer6"; |
| 677 | ti,timer-dsp; |
| 678 | ti,timer-pwm; |
| 679 | }; |
| 680 | |
| 681 | timer7: timer@48824000 { |
| 682 | compatible = "ti,omap5430-timer"; |
| 683 | reg = <0x48824000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 684 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 685 | ti,hwmods = "timer7"; |
| 686 | ti,timer-dsp; |
| 687 | }; |
| 688 | |
| 689 | timer8: timer@48826000 { |
| 690 | compatible = "ti,omap5430-timer"; |
| 691 | reg = <0x48826000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 692 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 693 | ti,hwmods = "timer8"; |
| 694 | ti,timer-dsp; |
| 695 | ti,timer-pwm; |
| 696 | }; |
| 697 | |
| 698 | timer9: timer@4803e000 { |
| 699 | compatible = "ti,omap5430-timer"; |
| 700 | reg = <0x4803e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 701 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 702 | ti,hwmods = "timer9"; |
| 703 | }; |
| 704 | |
| 705 | timer10: timer@48086000 { |
| 706 | compatible = "ti,omap5430-timer"; |
| 707 | reg = <0x48086000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 708 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 709 | ti,hwmods = "timer10"; |
| 710 | }; |
| 711 | |
| 712 | timer11: timer@48088000 { |
| 713 | compatible = "ti,omap5430-timer"; |
| 714 | reg = <0x48088000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 715 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 716 | ti,hwmods = "timer11"; |
| 717 | ti,timer-pwm; |
| 718 | }; |
| 719 | |
| 720 | timer13: timer@48828000 { |
| 721 | compatible = "ti,omap5430-timer"; |
| 722 | reg = <0x48828000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 723 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 724 | ti,hwmods = "timer13"; |
| 725 | status = "disabled"; |
| 726 | }; |
| 727 | |
| 728 | timer14: timer@4882a000 { |
| 729 | compatible = "ti,omap5430-timer"; |
| 730 | reg = <0x4882a000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 731 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 732 | ti,hwmods = "timer14"; |
| 733 | status = "disabled"; |
| 734 | }; |
| 735 | |
| 736 | timer15: timer@4882c000 { |
| 737 | compatible = "ti,omap5430-timer"; |
| 738 | reg = <0x4882c000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 739 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 740 | ti,hwmods = "timer15"; |
| 741 | status = "disabled"; |
| 742 | }; |
| 743 | |
| 744 | timer16: timer@4882e000 { |
| 745 | compatible = "ti,omap5430-timer"; |
| 746 | reg = <0x4882e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 747 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 748 | ti,hwmods = "timer16"; |
| 749 | status = "disabled"; |
| 750 | }; |
| 751 | |
| 752 | wdt2: wdt@4ae14000 { |
Lokesh Vutla | be66883 | 2014-11-12 10:54:15 +0530 | [diff] [blame] | 753 | compatible = "ti,omap3-wdt"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 754 | reg = <0x4ae14000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 755 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 756 | ti,hwmods = "wd_timer2"; |
| 757 | }; |
| 758 | |
Suman Anna | dbd7c19 | 2014-01-13 18:26:46 -0600 | [diff] [blame] | 759 | hwspinlock: spinlock@4a0f6000 { |
| 760 | compatible = "ti,omap4-hwspinlock"; |
| 761 | reg = <0x4a0f6000 0x1000>; |
| 762 | ti,hwmods = "spinlock"; |
| 763 | #hwlock-cells = <1>; |
| 764 | }; |
| 765 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 766 | dmm@4e000000 { |
| 767 | compatible = "ti,omap5-dmm"; |
| 768 | reg = <0x4e000000 0x800>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 769 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 770 | ti,hwmods = "dmm"; |
| 771 | }; |
| 772 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 773 | i2c1: i2c@48070000 { |
| 774 | compatible = "ti,omap4-i2c"; |
| 775 | reg = <0x48070000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 776 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 777 | #address-cells = <1>; |
| 778 | #size-cells = <0>; |
| 779 | ti,hwmods = "i2c1"; |
| 780 | status = "disabled"; |
| 781 | }; |
| 782 | |
| 783 | i2c2: i2c@48072000 { |
| 784 | compatible = "ti,omap4-i2c"; |
| 785 | reg = <0x48072000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 786 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 787 | #address-cells = <1>; |
| 788 | #size-cells = <0>; |
| 789 | ti,hwmods = "i2c2"; |
| 790 | status = "disabled"; |
| 791 | }; |
| 792 | |
| 793 | i2c3: i2c@48060000 { |
| 794 | compatible = "ti,omap4-i2c"; |
| 795 | reg = <0x48060000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 796 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 797 | #address-cells = <1>; |
| 798 | #size-cells = <0>; |
| 799 | ti,hwmods = "i2c3"; |
| 800 | status = "disabled"; |
| 801 | }; |
| 802 | |
| 803 | i2c4: i2c@4807a000 { |
| 804 | compatible = "ti,omap4-i2c"; |
| 805 | reg = <0x4807a000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 806 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 807 | #address-cells = <1>; |
| 808 | #size-cells = <0>; |
| 809 | ti,hwmods = "i2c4"; |
| 810 | status = "disabled"; |
| 811 | }; |
| 812 | |
| 813 | i2c5: i2c@4807c000 { |
| 814 | compatible = "ti,omap4-i2c"; |
| 815 | reg = <0x4807c000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 816 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 817 | #address-cells = <1>; |
| 818 | #size-cells = <0>; |
| 819 | ti,hwmods = "i2c5"; |
| 820 | status = "disabled"; |
| 821 | }; |
| 822 | |
| 823 | mmc1: mmc@4809c000 { |
| 824 | compatible = "ti,omap4-hsmmc"; |
| 825 | reg = <0x4809c000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 826 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 827 | ti,hwmods = "mmc1"; |
| 828 | ti,dual-volt; |
| 829 | ti,needs-special-reset; |
| 830 | dmas = <&sdma 61>, <&sdma 62>; |
| 831 | dma-names = "tx", "rx"; |
| 832 | status = "disabled"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 833 | pbias-supply = <&pbias_mmc_reg>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 834 | }; |
| 835 | |
| 836 | mmc2: mmc@480b4000 { |
| 837 | compatible = "ti,omap4-hsmmc"; |
| 838 | reg = <0x480b4000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 839 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 840 | ti,hwmods = "mmc2"; |
| 841 | ti,needs-special-reset; |
| 842 | dmas = <&sdma 47>, <&sdma 48>; |
| 843 | dma-names = "tx", "rx"; |
| 844 | status = "disabled"; |
| 845 | }; |
| 846 | |
| 847 | mmc3: mmc@480ad000 { |
| 848 | compatible = "ti,omap4-hsmmc"; |
| 849 | reg = <0x480ad000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 850 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 851 | ti,hwmods = "mmc3"; |
| 852 | ti,needs-special-reset; |
| 853 | dmas = <&sdma 77>, <&sdma 78>; |
| 854 | dma-names = "tx", "rx"; |
| 855 | status = "disabled"; |
| 856 | }; |
| 857 | |
| 858 | mmc4: mmc@480d1000 { |
| 859 | compatible = "ti,omap4-hsmmc"; |
| 860 | reg = <0x480d1000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 861 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 862 | ti,hwmods = "mmc4"; |
| 863 | ti,needs-special-reset; |
| 864 | dmas = <&sdma 57>, <&sdma 58>; |
| 865 | dma-names = "tx", "rx"; |
| 866 | status = "disabled"; |
| 867 | }; |
| 868 | |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 869 | abb_mpu: regulator-abb-mpu { |
| 870 | compatible = "ti,abb-v3"; |
| 871 | regulator-name = "abb_mpu"; |
| 872 | #address-cells = <0>; |
| 873 | #size-cells = <0>; |
| 874 | clocks = <&sys_clkin1>; |
| 875 | ti,settling-time = <50>; |
| 876 | ti,clock-cycles = <16>; |
| 877 | |
| 878 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
| 879 | <0x4ae06014 0x4>, <0x4a003b20 0x8>, |
| 880 | <0x4ae0c158 0x4>; |
| 881 | reg-names = "setup-address", "control-address", |
| 882 | "int-address", "efuse-address", |
| 883 | "ldo-address"; |
| 884 | ti,tranxdone-status-mask = <0x80>; |
| 885 | /* LDOVBBMPU_FBB_MUX_CTRL */ |
| 886 | ti,ldovbb-override-mask = <0x400>; |
| 887 | /* LDOVBBMPU_FBB_VSET_OUT */ |
| 888 | ti,ldovbb-vset-mask = <0x1F>; |
| 889 | |
| 890 | /* |
| 891 | * NOTE: only FBB mode used but actual vset will |
| 892 | * determine final biasing |
| 893 | */ |
| 894 | ti,abb_info = < |
| 895 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 896 | 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 897 | 1160000 0 0x4 0 0x02000000 0x01F00000 |
| 898 | 1210000 0 0x8 0 0x02000000 0x01F00000 |
| 899 | >; |
| 900 | }; |
| 901 | |
| 902 | abb_ivahd: regulator-abb-ivahd { |
| 903 | compatible = "ti,abb-v3"; |
| 904 | regulator-name = "abb_ivahd"; |
| 905 | #address-cells = <0>; |
| 906 | #size-cells = <0>; |
| 907 | clocks = <&sys_clkin1>; |
| 908 | ti,settling-time = <50>; |
| 909 | ti,clock-cycles = <16>; |
| 910 | |
| 911 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
| 912 | <0x4ae06010 0x4>, <0x4a0025cc 0x8>, |
| 913 | <0x4a002470 0x4>; |
| 914 | reg-names = "setup-address", "control-address", |
| 915 | "int-address", "efuse-address", |
| 916 | "ldo-address"; |
| 917 | ti,tranxdone-status-mask = <0x40000000>; |
| 918 | /* LDOVBBIVA_FBB_MUX_CTRL */ |
| 919 | ti,ldovbb-override-mask = <0x400>; |
| 920 | /* LDOVBBIVA_FBB_VSET_OUT */ |
| 921 | ti,ldovbb-vset-mask = <0x1F>; |
| 922 | |
| 923 | /* |
| 924 | * NOTE: only FBB mode used but actual vset will |
| 925 | * determine final biasing |
| 926 | */ |
| 927 | ti,abb_info = < |
| 928 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 929 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 930 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 931 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 932 | >; |
| 933 | }; |
| 934 | |
| 935 | abb_dspeve: regulator-abb-dspeve { |
| 936 | compatible = "ti,abb-v3"; |
| 937 | regulator-name = "abb_dspeve"; |
| 938 | #address-cells = <0>; |
| 939 | #size-cells = <0>; |
| 940 | clocks = <&sys_clkin1>; |
| 941 | ti,settling-time = <50>; |
| 942 | ti,clock-cycles = <16>; |
| 943 | |
| 944 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
| 945 | <0x4ae06010 0x4>, <0x4a0025e0 0x8>, |
| 946 | <0x4a00246c 0x4>; |
| 947 | reg-names = "setup-address", "control-address", |
| 948 | "int-address", "efuse-address", |
| 949 | "ldo-address"; |
| 950 | ti,tranxdone-status-mask = <0x20000000>; |
| 951 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ |
| 952 | ti,ldovbb-override-mask = <0x400>; |
| 953 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ |
| 954 | ti,ldovbb-vset-mask = <0x1F>; |
| 955 | |
| 956 | /* |
| 957 | * NOTE: only FBB mode used but actual vset will |
| 958 | * determine final biasing |
| 959 | */ |
| 960 | ti,abb_info = < |
| 961 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 962 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 963 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 964 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 965 | >; |
| 966 | }; |
| 967 | |
| 968 | abb_gpu: regulator-abb-gpu { |
| 969 | compatible = "ti,abb-v3"; |
| 970 | regulator-name = "abb_gpu"; |
| 971 | #address-cells = <0>; |
| 972 | #size-cells = <0>; |
| 973 | clocks = <&sys_clkin1>; |
| 974 | ti,settling-time = <50>; |
| 975 | ti,clock-cycles = <16>; |
| 976 | |
| 977 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
| 978 | <0x4ae06010 0x4>, <0x4a003b08 0x8>, |
| 979 | <0x4ae0c154 0x4>; |
| 980 | reg-names = "setup-address", "control-address", |
| 981 | "int-address", "efuse-address", |
| 982 | "ldo-address"; |
| 983 | ti,tranxdone-status-mask = <0x10000000>; |
| 984 | /* LDOVBBGPU_FBB_MUX_CTRL */ |
| 985 | ti,ldovbb-override-mask = <0x400>; |
| 986 | /* LDOVBBGPU_FBB_VSET_OUT */ |
| 987 | ti,ldovbb-vset-mask = <0x1F>; |
| 988 | |
| 989 | /* |
| 990 | * NOTE: only FBB mode used but actual vset will |
| 991 | * determine final biasing |
| 992 | */ |
| 993 | ti,abb_info = < |
| 994 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 995 | 1090000 0 0x0 0 0x02000000 0x01F00000 |
| 996 | 1210000 0 0x4 0 0x02000000 0x01F00000 |
| 997 | 1280000 0 0x8 0 0x02000000 0x01F00000 |
| 998 | >; |
| 999 | }; |
| 1000 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1001 | mcspi1: spi@48098000 { |
| 1002 | compatible = "ti,omap4-mcspi"; |
| 1003 | reg = <0x48098000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1004 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1005 | #address-cells = <1>; |
| 1006 | #size-cells = <0>; |
| 1007 | ti,hwmods = "mcspi1"; |
| 1008 | ti,spi-num-cs = <4>; |
| 1009 | dmas = <&sdma 35>, |
| 1010 | <&sdma 36>, |
| 1011 | <&sdma 37>, |
| 1012 | <&sdma 38>, |
| 1013 | <&sdma 39>, |
| 1014 | <&sdma 40>, |
| 1015 | <&sdma 41>, |
| 1016 | <&sdma 42>; |
| 1017 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 1018 | "tx2", "rx2", "tx3", "rx3"; |
| 1019 | status = "disabled"; |
| 1020 | }; |
| 1021 | |
| 1022 | mcspi2: spi@4809a000 { |
| 1023 | compatible = "ti,omap4-mcspi"; |
| 1024 | reg = <0x4809a000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1025 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1026 | #address-cells = <1>; |
| 1027 | #size-cells = <0>; |
| 1028 | ti,hwmods = "mcspi2"; |
| 1029 | ti,spi-num-cs = <2>; |
| 1030 | dmas = <&sdma 43>, |
| 1031 | <&sdma 44>, |
| 1032 | <&sdma 45>, |
| 1033 | <&sdma 46>; |
| 1034 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 1035 | status = "disabled"; |
| 1036 | }; |
| 1037 | |
| 1038 | mcspi3: spi@480b8000 { |
| 1039 | compatible = "ti,omap4-mcspi"; |
| 1040 | reg = <0x480b8000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1041 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1042 | #address-cells = <1>; |
| 1043 | #size-cells = <0>; |
| 1044 | ti,hwmods = "mcspi3"; |
| 1045 | ti,spi-num-cs = <2>; |
| 1046 | dmas = <&sdma 15>, <&sdma 16>; |
| 1047 | dma-names = "tx0", "rx0"; |
| 1048 | status = "disabled"; |
| 1049 | }; |
| 1050 | |
| 1051 | mcspi4: spi@480ba000 { |
| 1052 | compatible = "ti,omap4-mcspi"; |
| 1053 | reg = <0x480ba000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1054 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1055 | #address-cells = <1>; |
| 1056 | #size-cells = <0>; |
| 1057 | ti,hwmods = "mcspi4"; |
| 1058 | ti,spi-num-cs = <1>; |
| 1059 | dmas = <&sdma 70>, <&sdma 71>; |
| 1060 | dma-names = "tx0", "rx0"; |
| 1061 | status = "disabled"; |
| 1062 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1063 | |
| 1064 | qspi: qspi@4b300000 { |
| 1065 | compatible = "ti,dra7xxx-qspi"; |
| 1066 | reg = <0x4b300000 0x100>; |
| 1067 | reg-names = "qspi_base"; |
| 1068 | #address-cells = <1>; |
| 1069 | #size-cells = <0>; |
| 1070 | ti,hwmods = "qspi"; |
| 1071 | clocks = <&qspi_gfclk_div>; |
| 1072 | clock-names = "fck"; |
| 1073 | num-cs = <4>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1074 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1075 | status = "disabled"; |
| 1076 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1077 | |
| 1078 | omap_control_sata: control-phy@4a002374 { |
| 1079 | compatible = "ti,control-phy-pipe3"; |
| 1080 | reg = <0x4a002374 0x4>; |
| 1081 | reg-names = "power"; |
| 1082 | clocks = <&sys_clkin1>; |
| 1083 | clock-names = "sysclk"; |
| 1084 | }; |
| 1085 | |
| 1086 | /* OCP2SCP3 */ |
| 1087 | ocp2scp@4a090000 { |
| 1088 | compatible = "ti,omap-ocp2scp"; |
| 1089 | #address-cells = <1>; |
| 1090 | #size-cells = <1>; |
| 1091 | ranges; |
| 1092 | reg = <0x4a090000 0x20>; |
| 1093 | ti,hwmods = "ocp2scp3"; |
| 1094 | sata_phy: phy@4A096000 { |
| 1095 | compatible = "ti,phy-pipe3-sata"; |
| 1096 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 1097 | <0x4A096400 0x64>, /* phy_tx */ |
| 1098 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 1099 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1100 | ctrl-module = <&omap_control_sata>; |
| 1101 | clocks = <&sys_clkin1>; |
| 1102 | clock-names = "sysclk"; |
| 1103 | #phy-cells = <0>; |
| 1104 | }; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1105 | |
| 1106 | pcie1_phy: pciephy@4a094000 { |
| 1107 | compatible = "ti,phy-pipe3-pcie"; |
| 1108 | reg = <0x4a094000 0x80>, /* phy_rx */ |
| 1109 | <0x4a094400 0x64>; /* phy_tx */ |
| 1110 | reg-names = "phy_rx", "phy_tx"; |
| 1111 | ctrl-module = <&omap_control_pcie1phy>; |
| 1112 | clocks = <&dpll_pcie_ref_ck>, |
| 1113 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1114 | <&optfclk_pciephy1_32khz>, |
| 1115 | <&optfclk_pciephy1_clk>, |
| 1116 | <&optfclk_pciephy1_div_clk>, |
| 1117 | <&optfclk_pciephy_div>; |
| 1118 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1119 | "wkupclk", "refclk", |
| 1120 | "div-clk", "phy-div"; |
| 1121 | #phy-cells = <0>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1122 | ti,hwmods = "pcie1-phy"; |
| 1123 | }; |
| 1124 | |
| 1125 | pcie2_phy: pciephy@4a095000 { |
| 1126 | compatible = "ti,phy-pipe3-pcie"; |
| 1127 | reg = <0x4a095000 0x80>, /* phy_rx */ |
| 1128 | <0x4a095400 0x64>; /* phy_tx */ |
| 1129 | reg-names = "phy_rx", "phy_tx"; |
| 1130 | ctrl-module = <&omap_control_pcie2phy>; |
| 1131 | clocks = <&dpll_pcie_ref_ck>, |
| 1132 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1133 | <&optfclk_pciephy2_32khz>, |
| 1134 | <&optfclk_pciephy2_clk>, |
| 1135 | <&optfclk_pciephy2_div_clk>, |
| 1136 | <&optfclk_pciephy_div>; |
| 1137 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1138 | "wkupclk", "refclk", |
| 1139 | "div-clk", "phy-div"; |
| 1140 | #phy-cells = <0>; |
| 1141 | ti,hwmods = "pcie2-phy"; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1142 | status = "disabled"; |
| 1143 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1144 | }; |
| 1145 | |
| 1146 | sata: sata@4a141100 { |
| 1147 | compatible = "snps,dwc-ahci"; |
| 1148 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1149 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1150 | phys = <&sata_phy>; |
| 1151 | phy-names = "sata-phy"; |
| 1152 | clocks = <&sata_ref_clk>; |
| 1153 | ti,hwmods = "sata"; |
| 1154 | }; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1155 | |
Kishon Vijay Abraham I | d1ff66b | 2014-07-14 16:12:21 +0530 | [diff] [blame] | 1156 | omap_control_pcie1phy: control-phy@0x4a003c40 { |
| 1157 | compatible = "ti,control-phy-pcie"; |
| 1158 | reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1159 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1160 | clocks = <&sys_clkin1>; |
| 1161 | clock-names = "sysclk"; |
| 1162 | }; |
| 1163 | |
| 1164 | omap_control_pcie2phy: control-pcie@0x4a003c44 { |
| 1165 | compatible = "ti,control-phy-pcie"; |
| 1166 | reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1167 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1168 | clocks = <&sys_clkin1>; |
| 1169 | clock-names = "sysclk"; |
| 1170 | status = "disabled"; |
| 1171 | }; |
| 1172 | |
Lokesh Vutla | bc07831 | 2014-11-19 17:53:08 +0530 | [diff] [blame] | 1173 | rtc@48838000 { |
| 1174 | compatible = "ti,am3352-rtc"; |
| 1175 | reg = <0x48838000 0x100>; |
| 1176 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, |
| 1177 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; |
| 1178 | ti,hwmods = "rtcss"; |
| 1179 | clocks = <&sys_32k_ck>; |
| 1180 | }; |
| 1181 | |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1182 | omap_control_usb2phy1: control-phy@4a002300 { |
| 1183 | compatible = "ti,control-phy-usb2"; |
| 1184 | reg = <0x4a002300 0x4>; |
| 1185 | reg-names = "power"; |
| 1186 | }; |
| 1187 | |
| 1188 | omap_control_usb3phy1: control-phy@4a002370 { |
| 1189 | compatible = "ti,control-phy-pipe3"; |
| 1190 | reg = <0x4a002370 0x4>; |
| 1191 | reg-names = "power"; |
| 1192 | }; |
| 1193 | |
| 1194 | omap_control_usb2phy2: control-phy@0x4a002e74 { |
| 1195 | compatible = "ti,control-phy-usb2-dra7"; |
| 1196 | reg = <0x4a002e74 0x4>; |
| 1197 | reg-names = "power"; |
| 1198 | }; |
| 1199 | |
| 1200 | /* OCP2SCP1 */ |
| 1201 | ocp2scp@4a080000 { |
| 1202 | compatible = "ti,omap-ocp2scp"; |
| 1203 | #address-cells = <1>; |
| 1204 | #size-cells = <1>; |
| 1205 | ranges; |
| 1206 | reg = <0x4a080000 0x20>; |
| 1207 | ti,hwmods = "ocp2scp1"; |
| 1208 | |
| 1209 | usb2_phy1: phy@4a084000 { |
| 1210 | compatible = "ti,omap-usb2"; |
| 1211 | reg = <0x4a084000 0x400>; |
| 1212 | ctrl-module = <&omap_control_usb2phy1>; |
| 1213 | clocks = <&usb_phy1_always_on_clk32k>, |
| 1214 | <&usb_otg_ss1_refclk960m>; |
| 1215 | clock-names = "wkupclk", |
| 1216 | "refclk"; |
| 1217 | #phy-cells = <0>; |
| 1218 | }; |
| 1219 | |
| 1220 | usb2_phy2: phy@4a085000 { |
| 1221 | compatible = "ti,omap-usb2"; |
| 1222 | reg = <0x4a085000 0x400>; |
| 1223 | ctrl-module = <&omap_control_usb2phy2>; |
| 1224 | clocks = <&usb_phy2_always_on_clk32k>, |
| 1225 | <&usb_otg_ss2_refclk960m>; |
| 1226 | clock-names = "wkupclk", |
| 1227 | "refclk"; |
| 1228 | #phy-cells = <0>; |
| 1229 | }; |
| 1230 | |
| 1231 | usb3_phy1: phy@4a084400 { |
| 1232 | compatible = "ti,omap-usb3"; |
| 1233 | reg = <0x4a084400 0x80>, |
| 1234 | <0x4a084800 0x64>, |
| 1235 | <0x4a084c00 0x40>; |
| 1236 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1237 | ctrl-module = <&omap_control_usb3phy1>; |
| 1238 | clocks = <&usb_phy3_always_on_clk32k>, |
| 1239 | <&sys_clkin1>, |
| 1240 | <&usb_otg_ss1_refclk960m>; |
| 1241 | clock-names = "wkupclk", |
| 1242 | "sysclk", |
| 1243 | "refclk"; |
| 1244 | #phy-cells = <0>; |
| 1245 | }; |
| 1246 | }; |
| 1247 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1248 | omap_dwc3_1: omap_dwc3_1@48880000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1249 | compatible = "ti,dwc3"; |
| 1250 | ti,hwmods = "usb_otg_ss1"; |
| 1251 | reg = <0x48880000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1252 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1253 | #address-cells = <1>; |
| 1254 | #size-cells = <1>; |
| 1255 | utmi-mode = <2>; |
| 1256 | ranges; |
| 1257 | usb1: usb@48890000 { |
| 1258 | compatible = "snps,dwc3"; |
| 1259 | reg = <0x48890000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1260 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1261 | phys = <&usb2_phy1>, <&usb3_phy1>; |
| 1262 | phy-names = "usb2-phy", "usb3-phy"; |
| 1263 | tx-fifo-resize; |
| 1264 | maximum-speed = "super-speed"; |
| 1265 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1266 | snps,dis_u3_susphy_quirk; |
| 1267 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1268 | }; |
| 1269 | }; |
| 1270 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1271 | omap_dwc3_2: omap_dwc3_2@488c0000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1272 | compatible = "ti,dwc3"; |
| 1273 | ti,hwmods = "usb_otg_ss2"; |
| 1274 | reg = <0x488c0000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1275 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1276 | #address-cells = <1>; |
| 1277 | #size-cells = <1>; |
| 1278 | utmi-mode = <2>; |
| 1279 | ranges; |
| 1280 | usb2: usb@488d0000 { |
| 1281 | compatible = "snps,dwc3"; |
| 1282 | reg = <0x488d0000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1283 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1284 | phys = <&usb2_phy2>; |
| 1285 | phy-names = "usb2-phy"; |
| 1286 | tx-fifo-resize; |
| 1287 | maximum-speed = "high-speed"; |
| 1288 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1289 | snps,dis_u3_susphy_quirk; |
| 1290 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1291 | }; |
| 1292 | }; |
| 1293 | |
| 1294 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1295 | omap_dwc3_3: omap_dwc3_3@48900000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1296 | compatible = "ti,dwc3"; |
| 1297 | ti,hwmods = "usb_otg_ss3"; |
| 1298 | reg = <0x48900000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1299 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1300 | #address-cells = <1>; |
| 1301 | #size-cells = <1>; |
| 1302 | utmi-mode = <2>; |
| 1303 | ranges; |
| 1304 | status = "disabled"; |
| 1305 | usb3: usb@48910000 { |
| 1306 | compatible = "snps,dwc3"; |
| 1307 | reg = <0x48910000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1308 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1309 | tx-fifo-resize; |
| 1310 | maximum-speed = "high-speed"; |
| 1311 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1312 | snps,dis_u3_susphy_quirk; |
| 1313 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1314 | }; |
| 1315 | }; |
| 1316 | |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1317 | elm: elm@48078000 { |
| 1318 | compatible = "ti,am3352-elm"; |
| 1319 | reg = <0x48078000 0xfc0>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1320 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1321 | ti,hwmods = "elm"; |
| 1322 | status = "disabled"; |
| 1323 | }; |
| 1324 | |
| 1325 | gpmc: gpmc@50000000 { |
| 1326 | compatible = "ti,am3352-gpmc"; |
| 1327 | ti,hwmods = "gpmc"; |
| 1328 | reg = <0x50000000 0x37c>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1329 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1330 | gpmc,num-cs = <8>; |
| 1331 | gpmc,num-waitpins = <2>; |
| 1332 | #address-cells = <2>; |
| 1333 | #size-cells = <1>; |
| 1334 | status = "disabled"; |
| 1335 | }; |
Peter Ujfalusi | 2ca0945 | 2014-05-07 13:20:48 +0300 | [diff] [blame] | 1336 | |
| 1337 | atl: atl@4843c000 { |
| 1338 | compatible = "ti,dra7-atl"; |
| 1339 | reg = <0x4843c000 0x3ff>; |
| 1340 | ti,hwmods = "atl"; |
| 1341 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, |
| 1342 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; |
| 1343 | clocks = <&atl_gfclk_mux>; |
| 1344 | clock-names = "fck"; |
| 1345 | status = "disabled"; |
| 1346 | }; |
Olof Johansson | 412a9bb | 2014-07-18 22:16:15 -0700 | [diff] [blame] | 1347 | |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1348 | crossbar_mpu: crossbar@4a002a48 { |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1349 | compatible = "ti,irq-crossbar"; |
| 1350 | reg = <0x4a002a48 0x130>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1351 | interrupt-controller; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame^] | 1352 | interrupt-parent = <&wakeupgen>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1353 | #interrupt-cells = <3>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1354 | ti,max-irqs = <160>; |
| 1355 | ti,max-crossbar-sources = <MAX_SOURCES>; |
| 1356 | ti,reg-size = <2>; |
| 1357 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; |
| 1358 | ti,irqs-skip = <10 133 139 140>; |
| 1359 | ti,irqs-safe-map = <0>; |
| 1360 | }; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1361 | |
| 1362 | mac: ethernet@4a100000 { |
| 1363 | compatible = "ti,cpsw"; |
| 1364 | ti,hwmods = "gmac"; |
| 1365 | clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; |
| 1366 | clock-names = "fck", "cpts"; |
| 1367 | cpdma_channels = <8>; |
| 1368 | ale_entries = <1024>; |
| 1369 | bd_ram_size = <0x2000>; |
| 1370 | no_bd_ram = <0>; |
| 1371 | rx_descs = <64>; |
| 1372 | mac_control = <0x20>; |
| 1373 | slaves = <2>; |
| 1374 | active_slave = <0>; |
| 1375 | cpts_clock_mult = <0x80000000>; |
| 1376 | cpts_clock_shift = <29>; |
| 1377 | reg = <0x48484000 0x1000 |
| 1378 | 0x48485200 0x2E00>; |
| 1379 | #address-cells = <1>; |
| 1380 | #size-cells = <1>; |
| 1381 | /* |
| 1382 | * rx_thresh_pend |
| 1383 | * rx_pend |
| 1384 | * tx_pend |
| 1385 | * misc_pend |
| 1386 | */ |
| 1387 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| 1388 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| 1389 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| 1390 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; |
| 1391 | ranges; |
| 1392 | status = "disabled"; |
| 1393 | |
| 1394 | davinci_mdio: mdio@48485000 { |
| 1395 | compatible = "ti,davinci_mdio"; |
| 1396 | #address-cells = <1>; |
| 1397 | #size-cells = <0>; |
| 1398 | ti,hwmods = "davinci_mdio"; |
| 1399 | bus_freq = <1000000>; |
| 1400 | reg = <0x48485000 0x100>; |
| 1401 | }; |
| 1402 | |
| 1403 | cpsw_emac0: slave@48480200 { |
| 1404 | /* Filled in by U-Boot */ |
| 1405 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1406 | }; |
| 1407 | |
| 1408 | cpsw_emac1: slave@48480300 { |
| 1409 | /* Filled in by U-Boot */ |
| 1410 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1411 | }; |
| 1412 | |
| 1413 | phy_sel: cpsw-phy-sel@4a002554 { |
| 1414 | compatible = "ti,dra7xx-cpsw-phy-sel"; |
| 1415 | reg= <0x4a002554 0x4>; |
| 1416 | reg-names = "gmii-sel"; |
| 1417 | }; |
| 1418 | }; |
| 1419 | |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1420 | dcan1: can@481cc000 { |
| 1421 | compatible = "ti,dra7-d_can"; |
| 1422 | ti,hwmods = "dcan1"; |
| 1423 | reg = <0x4ae3c000 0x2000>; |
| 1424 | syscon-raminit = <&dra7_ctrl_core 0x558 0>; |
| 1425 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| 1426 | clocks = <&dcan1_sys_clk_mux>; |
| 1427 | status = "disabled"; |
| 1428 | }; |
| 1429 | |
| 1430 | dcan2: can@481d0000 { |
| 1431 | compatible = "ti,dra7-d_can"; |
| 1432 | ti,hwmods = "dcan2"; |
| 1433 | reg = <0x48480000 0x2000>; |
| 1434 | syscon-raminit = <&dra7_ctrl_core 0x558 1>; |
| 1435 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| 1436 | clocks = <&sys_clkin1>; |
| 1437 | status = "disabled"; |
| 1438 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1439 | }; |
| 1440 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 1441 | |
| 1442 | /include/ "dra7xx-clocks.dtsi" |