blob: 5a532224cb476b9db272b1acf1792f303476d1bb [file] [log] [blame]
Jeeja KPa40e6932015-07-09 15:20:08 +05301/*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22#include <linux/pci.h>
23#include <linux/pm_runtime.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include "skl.h"
Jeeja KPb663a8c2015-10-07 11:31:57 +010027#include "skl-topology.h"
Dharageswari.R721c3e32015-12-18 15:12:04 +053028#include "skl-sst-dsp.h"
29#include "skl-sst-ipc.h"
Jeeja KPa40e6932015-07-09 15:20:08 +053030
31#define HDA_MONO 1
32#define HDA_STEREO 2
Jeeja KP8f35bf32015-11-28 15:01:46 +053033#define HDA_QUAD 4
Jeeja KPa40e6932015-07-09 15:20:08 +053034
35static struct snd_pcm_hardware azx_pcm_hw = {
36 .info = (SNDRV_PCM_INFO_MMAP |
37 SNDRV_PCM_INFO_INTERLEAVED |
38 SNDRV_PCM_INFO_BLOCK_TRANSFER |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_PAUSE |
41 SNDRV_PCM_INFO_SYNC_START |
42 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
43 SNDRV_PCM_INFO_HAS_LINK_ATIME |
44 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
Jeeja KP06b23d92015-11-23 22:26:26 +053045 .formats = SNDRV_PCM_FMTBIT_S16_LE |
46 SNDRV_PCM_FMTBIT_S32_LE |
47 SNDRV_PCM_FMTBIT_S24_LE,
48 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
49 SNDRV_PCM_RATE_8000,
50 .rate_min = 8000,
Jeeja KPa40e6932015-07-09 15:20:08 +053051 .rate_max = 48000,
Jeeja KP8f35bf32015-11-28 15:01:46 +053052 .channels_min = 1,
53 .channels_max = HDA_QUAD,
Jeeja KPa40e6932015-07-09 15:20:08 +053054 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
55 .period_bytes_min = 128,
56 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
57 .periods_min = 2,
58 .periods_max = AZX_MAX_FRAG,
59 .fifo_size = 0,
60};
61
62static inline
63struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
64{
65 return substream->runtime->private_data;
66}
67
68static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
69{
70 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
71 struct hdac_stream *hstream = hdac_stream(stream);
72 struct hdac_bus *bus = hstream->bus;
73
74 return hbus_to_ebus(bus);
75}
76
77static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
78 struct snd_pcm_substream *substream,
79 size_t size)
80{
81 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
82
83 hdac_stream(stream)->bufsize = 0;
84 hdac_stream(stream)->period_bytes = 0;
85 hdac_stream(stream)->format_val = 0;
86
87 return snd_pcm_lib_malloc_pages(substream, size);
88}
89
90static int skl_substream_free_pages(struct hdac_bus *bus,
91 struct snd_pcm_substream *substream)
92{
93 return snd_pcm_lib_free_pages(substream);
94}
95
96static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
97 struct snd_pcm_runtime *runtime)
98{
99 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
100
101 /* avoid wrap-around with wall-clock */
102 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
103 20, 178000000);
104}
105
Jeeja KP05057002015-07-09 15:20:11 +0530106static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
107{
108 if (ebus->ppcap)
109 return HDAC_EXT_STREAM_TYPE_HOST;
110 else
111 return HDAC_EXT_STREAM_TYPE_COUPLED;
112}
113
Jeeja KP4557c302015-12-03 23:30:00 +0530114/*
115 * check if the stream opened is marked as ignore_suspend by machine, if so
116 * then enable suspend_active refcount
117 *
118 * The count supend_active does not need lock as it is used in open/close
119 * and suspend context
120 */
121static void skl_set_suspend_active(struct snd_pcm_substream *substream,
122 struct snd_soc_dai *dai, bool enable)
123{
124 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
125 struct snd_soc_dapm_widget *w;
126 struct skl *skl = ebus_to_skl(ebus);
127
128 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
129 w = dai->playback_widget;
130 else
131 w = dai->capture_widget;
132
133 if (w->ignore_suspend && enable)
134 skl->supend_active++;
135 else if (w->ignore_suspend && !enable)
136 skl->supend_active--;
137}
138
Jeeja KPa40e6932015-07-09 15:20:08 +0530139static int skl_pcm_open(struct snd_pcm_substream *substream,
140 struct snd_soc_dai *dai)
141{
142 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
143 struct hdac_ext_stream *stream;
144 struct snd_pcm_runtime *runtime = substream->runtime;
145 struct skl_dma_params *dma_params;
Jeeja KPa40e6932015-07-09 15:20:08 +0530146
147 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530148
149 stream = snd_hdac_ext_stream_assign(ebus, substream,
Jeeja KP05057002015-07-09 15:20:11 +0530150 skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530151 if (stream == NULL)
152 return -EBUSY;
153
154 skl_set_pcm_constrains(ebus, runtime);
155
156 /*
157 * disable WALLCLOCK timestamps for capture streams
158 * until we figure out how to handle digital inputs
159 */
160 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
161 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
162 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
163 }
164
165 runtime->private_data = stream;
166
167 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
168 if (!dma_params)
169 return -ENOMEM;
170
171 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
172 snd_soc_dai_set_dma_data(dai, substream, dma_params);
173
174 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
175 dma_params->stream_tag);
Jeeja KP4557c302015-12-03 23:30:00 +0530176 skl_set_suspend_active(substream, dai, true);
Jeeja KPa40e6932015-07-09 15:20:08 +0530177 snd_pcm_set_sync(substream);
178
179 return 0;
180}
181
182static int skl_get_format(struct snd_pcm_substream *substream,
183 struct snd_soc_dai *dai)
184{
185 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
186 struct skl_dma_params *dma_params;
Jeeja KP05057002015-07-09 15:20:11 +0530187 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530188 int format_val = 0;
Jeeja KPa40e6932015-07-09 15:20:08 +0530189
Jeeja KP05057002015-07-09 15:20:11 +0530190 if (ebus->ppcap) {
191 struct snd_pcm_runtime *runtime = substream->runtime;
192
193 format_val = snd_hdac_calc_stream_format(runtime->rate,
194 runtime->channels,
195 runtime->format,
196 32, 0);
197 } else {
198 struct snd_soc_dai *codec_dai = rtd->codec_dai;
199
200 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
201 if (dma_params)
202 format_val = dma_params->format;
203 }
Jeeja KPa40e6932015-07-09 15:20:08 +0530204
205 return format_val;
206}
207
208static int skl_pcm_prepare(struct snd_pcm_substream *substream,
209 struct snd_soc_dai *dai)
210{
211 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
212 unsigned int format_val;
213 int err;
214
215 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530216
217 format_val = skl_get_format(substream, dai);
218 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
219 hdac_stream(stream)->stream_tag, format_val);
220 snd_hdac_stream_reset(hdac_stream(stream));
221
222 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
223 if (err < 0)
224 return err;
225
226 err = snd_hdac_stream_setup(hdac_stream(stream));
227 if (err < 0)
228 return err;
229
230 hdac_stream(stream)->prepared = 1;
231
232 return err;
233}
234
235static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
236 struct snd_pcm_hw_params *params,
237 struct snd_soc_dai *dai)
238{
239 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KP05057002015-07-09 15:20:11 +0530240 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530241 struct snd_pcm_runtime *runtime = substream->runtime;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100242 struct skl_pipe_params p_params = {0};
243 struct skl_module_cfg *m_cfg;
Jeeja KP05057002015-07-09 15:20:11 +0530244 int ret, dma_id;
Jeeja KPa40e6932015-07-09 15:20:08 +0530245
246 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
247 ret = skl_substream_alloc_pages(ebus, substream,
248 params_buffer_bytes(params));
249 if (ret < 0)
250 return ret;
251
252 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
253 runtime->rate, runtime->channels, runtime->format);
254
Jeeja KP05057002015-07-09 15:20:11 +0530255 dma_id = hdac_stream(stream)->stream_tag - 1;
256 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
257
Jeeja KPb663a8c2015-10-07 11:31:57 +0100258 p_params.s_fmt = snd_pcm_format_width(params_format(params));
259 p_params.ch = params_channels(params);
260 p_params.s_freq = params_rate(params);
261 p_params.host_dma_id = dma_id;
262 p_params.stream = substream->stream;
263
264 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
265 if (m_cfg)
266 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
267
Jeeja KPa40e6932015-07-09 15:20:08 +0530268 return 0;
269}
270
271static void skl_pcm_close(struct snd_pcm_substream *substream,
272 struct snd_soc_dai *dai)
273{
274 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KP05057002015-07-09 15:20:11 +0530275 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530276 struct skl_dma_params *dma_params = NULL;
Dharageswari.R721c3e32015-12-18 15:12:04 +0530277 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPa40e6932015-07-09 15:20:08 +0530278
279 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KP05057002015-07-09 15:20:11 +0530280
281 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530282
283 dma_params = snd_soc_dai_get_dma_data(dai, substream);
284 /*
285 * now we should set this to NULL as we are freeing by the
286 * dma_params
287 */
288 snd_soc_dai_set_dma_data(dai, substream, NULL);
Jeeja KP4557c302015-12-03 23:30:00 +0530289 skl_set_suspend_active(substream, dai, false);
Jeeja KPa40e6932015-07-09 15:20:08 +0530290
Dharageswari.R721c3e32015-12-18 15:12:04 +0530291 /*
292 * check if close is for "Reference Pin" and set back the
293 * CGCTL.MISCBDCGE if disabled by driver
294 */
295 if (!strncmp(dai->name, "Reference Pin", 13) &&
296 skl->skl_sst->miscbdcg_disabled) {
297 skl->skl_sst->enable_miscbdcge(dai->dev, true);
298 skl->skl_sst->miscbdcg_disabled = false;
299 }
300
Jeeja KPa40e6932015-07-09 15:20:08 +0530301 kfree(dma_params);
302}
303
304static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
305 struct snd_soc_dai *dai)
306{
307 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
308 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
309
310 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
311
312 snd_hdac_stream_cleanup(hdac_stream(stream));
313 hdac_stream(stream)->prepared = 0;
314
315 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
316}
317
Jeeja KPb663a8c2015-10-07 11:31:57 +0100318static int skl_be_hw_params(struct snd_pcm_substream *substream,
319 struct snd_pcm_hw_params *params,
320 struct snd_soc_dai *dai)
321{
322 struct skl_pipe_params p_params = {0};
323
324 p_params.s_fmt = snd_pcm_format_width(params_format(params));
325 p_params.ch = params_channels(params);
326 p_params.s_freq = params_rate(params);
327 p_params.stream = substream->stream;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100328
Jeeja KP4bd073f2015-10-27 09:22:45 +0900329 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100330}
331
Jeeja KPd1730c32015-10-27 09:22:53 +0900332static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
333 int cmd)
334{
335 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
336 struct hdac_bus *bus = ebus_to_hbus(ebus);
337 struct hdac_ext_stream *stream;
338 int start;
339 unsigned long cookie;
340 struct hdac_stream *hstr;
341
342 stream = get_hdac_ext_stream(substream);
343 hstr = hdac_stream(stream);
344
345 if (!hstr->prepared)
346 return -EPIPE;
347
348 switch (cmd) {
349 case SNDRV_PCM_TRIGGER_START:
350 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
351 case SNDRV_PCM_TRIGGER_RESUME:
352 start = 1;
353 break;
354
355 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
356 case SNDRV_PCM_TRIGGER_SUSPEND:
357 case SNDRV_PCM_TRIGGER_STOP:
358 start = 0;
359 break;
360
361 default:
362 return -EINVAL;
363 }
364
365 spin_lock_irqsave(&bus->reg_lock, cookie);
366
367 if (start) {
368 snd_hdac_stream_start(hdac_stream(stream), true);
369 snd_hdac_stream_timecounter_init(hstr, 0);
370 } else {
371 snd_hdac_stream_stop(hdac_stream(stream));
372 }
373
374 spin_unlock_irqrestore(&bus->reg_lock, cookie);
375
376 return 0;
377}
378
Jeeja KPb663a8c2015-10-07 11:31:57 +0100379static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
380 struct snd_soc_dai *dai)
381{
382 struct skl *skl = get_skl_ctx(dai->dev);
383 struct skl_sst *ctx = skl->skl_sst;
384 struct skl_module_cfg *mconfig;
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530385 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
386 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPd1730c32015-10-27 09:22:53 +0900387 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100388
389 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
390 if (!mconfig)
391 return -EIO;
392
393 switch (cmd) {
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530394 case SNDRV_PCM_TRIGGER_RESUME:
395 skl_pcm_prepare(substream, dai);
Jeeja KP748a1d52015-12-18 15:12:07 +0530396 /*
397 * enable DMA Resume enable bit for the stream, set the dpib
398 * & lpib position to resune before starting the DMA
399 */
400 snd_hdac_ext_stream_drsm_enable(ebus, true,
401 hdac_stream(stream)->index);
402 snd_hdac_ext_stream_set_dpibr(ebus, stream, stream->dpib);
403 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
404
Jeeja KPd1730c32015-10-27 09:22:53 +0900405 case SNDRV_PCM_TRIGGER_START:
Jeeja KPb663a8c2015-10-07 11:31:57 +0100406 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Jeeja KPd1730c32015-10-27 09:22:53 +0900407 /*
408 * Start HOST DMA and Start FE Pipe.This is to make sure that
409 * there are no underrun/overrun in the case when the FE
410 * pipeline is started but there is a delay in starting the
411 * DMA channel on the host.
412 */
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530413 snd_hdac_ext_stream_decouple(ebus, stream, true);
Jeeja KPd1730c32015-10-27 09:22:53 +0900414 ret = skl_decoupled_trigger(substream, cmd);
415 if (ret < 0)
416 return ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100417 return skl_run_pipe(ctx, mconfig->pipe);
Jeeja KPd1730c32015-10-27 09:22:53 +0900418 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100419
420 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
421 case SNDRV_PCM_TRIGGER_SUSPEND:
Jeeja KPd1730c32015-10-27 09:22:53 +0900422 case SNDRV_PCM_TRIGGER_STOP:
423 /*
424 * Stop FE Pipe first and stop DMA. This is to make sure that
425 * there are no underrun/overrun in the case if there is a delay
426 * between the two operations.
427 */
428 ret = skl_stop_pipe(ctx, mconfig->pipe);
429 if (ret < 0)
430 return ret;
431
432 ret = skl_decoupled_trigger(substream, cmd);
Jeeja KP748a1d52015-12-18 15:12:07 +0530433 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) {
434 /* save the dpib and lpib positions */
435 stream->dpib = readl(ebus->bus.remap_addr +
436 AZX_REG_VS_SDXDPIB_XBASE +
437 (AZX_REG_VS_SDXDPIB_XINTERVAL *
438 hdac_stream(stream)->index));
439
440 stream->lpib = snd_hdac_stream_get_pos_lpib(
441 hdac_stream(stream));
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530442 snd_hdac_ext_stream_decouple(ebus, stream, false);
Jeeja KP748a1d52015-12-18 15:12:07 +0530443 }
Jeeja KPd1730c32015-10-27 09:22:53 +0900444 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100445
446 default:
Jeeja KPd1730c32015-10-27 09:22:53 +0900447 return -EINVAL;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100448 }
Jeeja KPd1730c32015-10-27 09:22:53 +0900449
450 return 0;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100451}
452
Jeeja KP05057002015-07-09 15:20:11 +0530453static int skl_link_hw_params(struct snd_pcm_substream *substream,
454 struct snd_pcm_hw_params *params,
455 struct snd_soc_dai *dai)
456{
457 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
458 struct hdac_ext_stream *link_dev;
459 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
460 struct skl_dma_params *dma_params;
461 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100462 struct skl_pipe_params p_params = {0};
Jeeja KP05057002015-07-09 15:20:11 +0530463
Jeeja KP05057002015-07-09 15:20:11 +0530464 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
465 HDAC_EXT_STREAM_TYPE_LINK);
466 if (!link_dev)
467 return -EBUSY;
468
469 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
470
471 /* set the stream tag in the codec dai dma params */
472 dma_params = (struct skl_dma_params *)
473 snd_soc_dai_get_dma_data(codec_dai, substream);
474 if (dma_params)
475 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
476 snd_soc_dai_set_dma_data(codec_dai, substream, (void *)dma_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100477
478 p_params.s_fmt = snd_pcm_format_width(params_format(params));
479 p_params.ch = params_channels(params);
480 p_params.s_freq = params_rate(params);
481 p_params.stream = substream->stream;
482 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
483
Jeeja KP4bd073f2015-10-27 09:22:45 +0900484 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KP05057002015-07-09 15:20:11 +0530485}
486
487static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
488 struct snd_soc_dai *dai)
489{
490 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
491 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
492 struct hdac_ext_stream *link_dev =
493 snd_soc_dai_get_dma_data(dai, substream);
494 unsigned int format_val = 0;
495 struct skl_dma_params *dma_params;
496 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KP05057002015-07-09 15:20:11 +0530497 struct hdac_ext_link *link;
498
Jeeja KP05057002015-07-09 15:20:11 +0530499 if (link_dev->link_prepared) {
500 dev_dbg(dai->dev, "already stream is prepared - returning\n");
501 return 0;
502 }
Jeeja KP05057002015-07-09 15:20:11 +0530503
504 dma_params = (struct skl_dma_params *)
505 snd_soc_dai_get_dma_data(codec_dai, substream);
506 if (dma_params)
507 format_val = dma_params->format;
508 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
509 hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
510
511 snd_hdac_ext_link_stream_reset(link_dev);
512
513 snd_hdac_ext_link_stream_setup(link_dev, format_val);
514
515 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
516 if (!link)
517 return -EINVAL;
518
519 snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
520 link_dev->link_prepared = 1;
521
522 return 0;
523}
524
525static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
526 int cmd, struct snd_soc_dai *dai)
527{
528 struct hdac_ext_stream *link_dev =
529 snd_soc_dai_get_dma_data(dai, substream);
530
531 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
532 switch (cmd) {
533 case SNDRV_PCM_TRIGGER_START:
534 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
535 case SNDRV_PCM_TRIGGER_RESUME:
536 snd_hdac_ext_link_stream_start(link_dev);
537 break;
538
539 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
540 case SNDRV_PCM_TRIGGER_SUSPEND:
541 case SNDRV_PCM_TRIGGER_STOP:
542 snd_hdac_ext_link_stream_clear(link_dev);
543 break;
544
545 default:
546 return -EINVAL;
547 }
548 return 0;
549}
550
551static int skl_link_hw_free(struct snd_pcm_substream *substream,
552 struct snd_soc_dai *dai)
553{
554 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
555 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
556 struct hdac_ext_stream *link_dev =
557 snd_soc_dai_get_dma_data(dai, substream);
558 struct hdac_ext_link *link;
559
560 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
561
562 link_dev->link_prepared = 0;
563
564 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
565 if (!link)
566 return -EINVAL;
567
568 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
569 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
570 return 0;
571}
572
Jeeja KPa40e6932015-07-09 15:20:08 +0530573static struct snd_soc_dai_ops skl_pcm_dai_ops = {
574 .startup = skl_pcm_open,
575 .shutdown = skl_pcm_close,
576 .prepare = skl_pcm_prepare,
577 .hw_params = skl_pcm_hw_params,
578 .hw_free = skl_pcm_hw_free,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100579 .trigger = skl_pcm_trigger,
Jeeja KPa40e6932015-07-09 15:20:08 +0530580};
581
Jeeja KP05057002015-07-09 15:20:11 +0530582static struct snd_soc_dai_ops skl_dmic_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100583 .hw_params = skl_be_hw_params,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100584};
585
586static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100587 .hw_params = skl_be_hw_params,
Jeeja KP05057002015-07-09 15:20:11 +0530588};
589
590static struct snd_soc_dai_ops skl_link_dai_ops = {
Jeeja KP05057002015-07-09 15:20:11 +0530591 .prepare = skl_link_pcm_prepare,
592 .hw_params = skl_link_hw_params,
593 .hw_free = skl_link_hw_free,
594 .trigger = skl_link_pcm_trigger,
Jeeja KP05057002015-07-09 15:20:11 +0530595};
596
Jeeja KPa40e6932015-07-09 15:20:08 +0530597static struct snd_soc_dai_driver skl_platform_dai[] = {
598{
599 .name = "System Pin",
600 .ops = &skl_pcm_dai_ops,
601 .playback = {
602 .stream_name = "System Playback",
603 .channels_min = HDA_MONO,
604 .channels_max = HDA_STEREO,
605 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
606 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
607 },
608 .capture = {
609 .stream_name = "System Capture",
610 .channels_min = HDA_MONO,
611 .channels_max = HDA_STEREO,
612 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
613 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
614 },
615},
616{
Jeeja KP05057002015-07-09 15:20:11 +0530617 .name = "Reference Pin",
618 .ops = &skl_pcm_dai_ops,
619 .capture = {
620 .stream_name = "Reference Capture",
621 .channels_min = HDA_MONO,
Jeeja KP8f35bf32015-11-28 15:01:46 +0530622 .channels_max = HDA_QUAD,
Jeeja KP05057002015-07-09 15:20:11 +0530623 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
624 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
625 },
626},
627{
Jeeja KPa40e6932015-07-09 15:20:08 +0530628 .name = "Deepbuffer Pin",
629 .ops = &skl_pcm_dai_ops,
630 .playback = {
631 .stream_name = "Deepbuffer Playback",
632 .channels_min = HDA_STEREO,
633 .channels_max = HDA_STEREO,
634 .rates = SNDRV_PCM_RATE_48000,
635 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
636 },
637},
638{
639 .name = "LowLatency Pin",
640 .ops = &skl_pcm_dai_ops,
641 .playback = {
642 .stream_name = "Low Latency Playback",
643 .channels_min = HDA_STEREO,
644 .channels_max = HDA_STEREO,
645 .rates = SNDRV_PCM_RATE_48000,
646 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
647 },
648},
Jeeja KP8f35bf32015-11-28 15:01:46 +0530649{
650 .name = "DMIC Pin",
651 .ops = &skl_pcm_dai_ops,
652 .capture = {
653 .stream_name = "DMIC Capture",
654 .channels_min = HDA_MONO,
655 .channels_max = HDA_QUAD,
656 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
657 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
658 },
659},
660
Jeeja KP05057002015-07-09 15:20:11 +0530661/* BE CPU Dais */
662{
Jeeja KPb663a8c2015-10-07 11:31:57 +0100663 .name = "SSP0 Pin",
664 .ops = &skl_be_ssp_dai_ops,
665 .playback = {
666 .stream_name = "ssp0 Tx",
667 .channels_min = HDA_STEREO,
668 .channels_max = HDA_STEREO,
669 .rates = SNDRV_PCM_RATE_48000,
670 .formats = SNDRV_PCM_FMTBIT_S16_LE,
671 },
672 .capture = {
673 .stream_name = "ssp0 Rx",
674 .channels_min = HDA_STEREO,
675 .channels_max = HDA_STEREO,
676 .rates = SNDRV_PCM_RATE_48000,
677 .formats = SNDRV_PCM_FMTBIT_S16_LE,
678 },
679},
680{
Jeeja KPc80fd4d2015-11-05 22:53:06 +0530681 .name = "SSP1 Pin",
682 .ops = &skl_be_ssp_dai_ops,
683 .playback = {
684 .stream_name = "ssp1 Tx",
685 .channels_min = HDA_STEREO,
686 .channels_max = HDA_STEREO,
687 .rates = SNDRV_PCM_RATE_48000,
688 .formats = SNDRV_PCM_FMTBIT_S16_LE,
689 },
690 .capture = {
691 .stream_name = "ssp1 Rx",
692 .channels_min = HDA_STEREO,
693 .channels_max = HDA_STEREO,
694 .rates = SNDRV_PCM_RATE_48000,
695 .formats = SNDRV_PCM_FMTBIT_S16_LE,
696 },
697},
698{
Jeeja KP05057002015-07-09 15:20:11 +0530699 .name = "iDisp Pin",
700 .ops = &skl_link_dai_ops,
701 .playback = {
702 .stream_name = "iDisp Tx",
703 .channels_min = HDA_STEREO,
704 .channels_max = HDA_STEREO,
705 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
706 .formats = SNDRV_PCM_FMTBIT_S16_LE,
707 },
708},
709{
710 .name = "DMIC01 Pin",
711 .ops = &skl_dmic_dai_ops,
712 .capture = {
713 .stream_name = "DMIC01 Rx",
Jeeja KP8f35bf32015-11-28 15:01:46 +0530714 .channels_min = HDA_MONO,
715 .channels_max = HDA_QUAD,
Jeeja KP05057002015-07-09 15:20:11 +0530716 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
717 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
718 },
719},
720{
Jeeja KP05057002015-07-09 15:20:11 +0530721 .name = "HD-Codec Pin",
722 .ops = &skl_link_dai_ops,
723 .playback = {
724 .stream_name = "HD-Codec Tx",
725 .channels_min = HDA_STEREO,
726 .channels_max = HDA_STEREO,
727 .rates = SNDRV_PCM_RATE_48000,
728 .formats = SNDRV_PCM_FMTBIT_S16_LE,
729 },
730 .capture = {
731 .stream_name = "HD-Codec Rx",
732 .channels_min = HDA_STEREO,
733 .channels_max = HDA_STEREO,
734 .rates = SNDRV_PCM_RATE_48000,
735 .formats = SNDRV_PCM_FMTBIT_S16_LE,
736 },
737},
Jeeja KPa40e6932015-07-09 15:20:08 +0530738};
739
740static int skl_platform_open(struct snd_pcm_substream *substream)
741{
742 struct snd_pcm_runtime *runtime;
743 struct snd_soc_pcm_runtime *rtd = substream->private_data;
744 struct snd_soc_dai_link *dai_link = rtd->dai_link;
745
746 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
747 dai_link->cpu_dai_name);
748
749 runtime = substream->runtime;
750 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
751
752 return 0;
753}
754
Jeeja KPb663a8c2015-10-07 11:31:57 +0100755static int skl_coupled_trigger(struct snd_pcm_substream *substream,
Jeeja KPa40e6932015-07-09 15:20:08 +0530756 int cmd)
757{
758 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
759 struct hdac_bus *bus = ebus_to_hbus(ebus);
760 struct hdac_ext_stream *stream;
761 struct snd_pcm_substream *s;
762 bool start;
763 int sbits = 0;
764 unsigned long cookie;
765 struct hdac_stream *hstr;
766
767 stream = get_hdac_ext_stream(substream);
768 hstr = hdac_stream(stream);
769
770 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
771
772 if (!hstr->prepared)
773 return -EPIPE;
774
775 switch (cmd) {
776 case SNDRV_PCM_TRIGGER_START:
777 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
778 case SNDRV_PCM_TRIGGER_RESUME:
779 start = true;
780 break;
781
782 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
783 case SNDRV_PCM_TRIGGER_SUSPEND:
784 case SNDRV_PCM_TRIGGER_STOP:
785 start = false;
786 break;
787
788 default:
789 return -EINVAL;
790 }
791
792 snd_pcm_group_for_each_entry(s, substream) {
793 if (s->pcm->card != substream->pcm->card)
794 continue;
795 stream = get_hdac_ext_stream(s);
796 sbits |= 1 << hdac_stream(stream)->index;
797 snd_pcm_trigger_done(s, substream);
798 }
799
800 spin_lock_irqsave(&bus->reg_lock, cookie);
801
802 /* first, set SYNC bits of corresponding streams */
803 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
804
805 snd_pcm_group_for_each_entry(s, substream) {
806 if (s->pcm->card != substream->pcm->card)
807 continue;
808 stream = get_hdac_ext_stream(s);
809 if (start)
810 snd_hdac_stream_start(hdac_stream(stream), true);
811 else
812 snd_hdac_stream_stop(hdac_stream(stream));
813 }
814 spin_unlock_irqrestore(&bus->reg_lock, cookie);
815
816 snd_hdac_stream_sync(hstr, start, sbits);
817
818 spin_lock_irqsave(&bus->reg_lock, cookie);
819
820 /* reset SYNC bits */
821 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
822 if (start)
823 snd_hdac_stream_timecounter_init(hstr, sbits);
824 spin_unlock_irqrestore(&bus->reg_lock, cookie);
825
826 return 0;
827}
828
Jeeja KP05057002015-07-09 15:20:11 +0530829static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
830 int cmd)
831{
832 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
833
Jeeja KPd1730c32015-10-27 09:22:53 +0900834 if (!ebus->ppcap)
Jeeja KPb663a8c2015-10-07 11:31:57 +0100835 return skl_coupled_trigger(substream, cmd);
Jeeja KPd1730c32015-10-27 09:22:53 +0900836
837 return 0;
Jeeja KP05057002015-07-09 15:20:11 +0530838}
839
Jeeja KPa40e6932015-07-09 15:20:08 +0530840/* calculate runtime delay from LPIB */
841static int skl_get_delay_from_lpib(struct hdac_ext_bus *ebus,
842 struct hdac_ext_stream *sstream,
843 unsigned int pos)
844{
845 struct hdac_bus *bus = ebus_to_hbus(ebus);
846 struct hdac_stream *hstream = hdac_stream(sstream);
847 struct snd_pcm_substream *substream = hstream->substream;
848 int stream = substream->stream;
849 unsigned int lpib_pos = snd_hdac_stream_get_pos_lpib(hstream);
850 int delay;
851
852 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
853 delay = pos - lpib_pos;
854 else
855 delay = lpib_pos - pos;
856
857 if (delay < 0) {
858 if (delay >= hstream->delay_negative_threshold)
859 delay = 0;
860 else
861 delay += hstream->bufsize;
862 }
863
864 if (delay >= hstream->period_bytes) {
865 dev_info(bus->dev,
866 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
867 delay, hstream->period_bytes);
868 delay = 0;
869 }
870
871 return bytes_to_frames(substream->runtime, delay);
872}
873
874static unsigned int skl_get_position(struct hdac_ext_stream *hstream,
875 int codec_delay)
876{
877 struct hdac_stream *hstr = hdac_stream(hstream);
878 struct snd_pcm_substream *substream = hstr->substream;
Vinod Koulc7b2a442015-10-30 20:34:20 +0530879 struct hdac_ext_bus *ebus;
Jeeja KPa40e6932015-07-09 15:20:08 +0530880 unsigned int pos;
881 int delay;
882
883 /* use the position buffer as default */
884 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
885
886 if (pos >= hdac_stream(hstream)->bufsize)
887 pos = 0;
888
889 if (substream->runtime) {
Vinod Koulc7b2a442015-10-30 20:34:20 +0530890 ebus = get_bus_ctx(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530891 delay = skl_get_delay_from_lpib(ebus, hstream, pos)
892 + codec_delay;
893 substream->runtime->delay += delay;
894 }
895
896 return pos;
897}
898
899static snd_pcm_uframes_t skl_platform_pcm_pointer
900 (struct snd_pcm_substream *substream)
901{
902 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
903
904 return bytes_to_frames(substream->runtime,
905 skl_get_position(hstream, 0));
906}
907
908static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
909 u64 nsec)
910{
911 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
912 struct snd_soc_dai *codec_dai = rtd->codec_dai;
913 u64 codec_frames, codec_nsecs;
914
915 if (!codec_dai->driver->ops->delay)
916 return nsec;
917
918 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
919 codec_nsecs = div_u64(codec_frames * 1000000000LL,
920 substream->runtime->rate);
921
922 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
923 return nsec + codec_nsecs;
924
925 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
926}
927
928static int skl_get_time_info(struct snd_pcm_substream *substream,
929 struct timespec *system_ts, struct timespec *audio_ts,
930 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
931 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
932{
933 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
934 struct hdac_stream *hstr = hdac_stream(sstream);
935 u64 nsec;
936
937 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
938 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
939
940 snd_pcm_gettime(substream->runtime, system_ts);
941
942 nsec = timecounter_read(&hstr->tc);
943 nsec = div_u64(nsec, 3); /* can be optimized */
944 if (audio_tstamp_config->report_delay)
945 nsec = skl_adjust_codec_delay(substream, nsec);
946
947 *audio_ts = ns_to_timespec(nsec);
948
949 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
950 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
951 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
952
953 } else {
954 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
955 }
956
957 return 0;
958}
959
960static struct snd_pcm_ops skl_platform_ops = {
961 .open = skl_platform_open,
962 .ioctl = snd_pcm_lib_ioctl,
963 .trigger = skl_platform_pcm_trigger,
964 .pointer = skl_platform_pcm_pointer,
965 .get_time_info = skl_get_time_info,
966 .mmap = snd_pcm_lib_default_mmap,
967 .page = snd_pcm_sgbuf_ops_page,
968};
969
970static void skl_pcm_free(struct snd_pcm *pcm)
971{
972 snd_pcm_lib_preallocate_free_for_all(pcm);
973}
974
975#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
976
977static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
978{
979 struct snd_soc_dai *dai = rtd->cpu_dai;
980 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
981 struct snd_pcm *pcm = rtd->pcm;
982 unsigned int size;
983 int retval = 0;
984 struct skl *skl = ebus_to_skl(ebus);
985
986 if (dai->driver->playback.channels_min ||
987 dai->driver->capture.channels_min) {
988 /* buffer pre-allocation */
989 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
990 if (size > MAX_PREALLOC_SIZE)
991 size = MAX_PREALLOC_SIZE;
992 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
993 SNDRV_DMA_TYPE_DEV_SG,
994 snd_dma_pci_data(skl->pci),
995 size, MAX_PREALLOC_SIZE);
996 if (retval) {
997 dev_err(dai->dev, "dma buffer allocationf fail\n");
998 return retval;
999 }
1000 }
1001
1002 return retval;
1003}
1004
Jeeja KPb663a8c2015-10-07 11:31:57 +01001005static int skl_platform_soc_probe(struct snd_soc_platform *platform)
1006{
1007 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
1008
1009 if (ebus->ppcap)
1010 return skl_tplg_init(platform, ebus);
1011
1012 return 0;
1013}
Jeeja KPa40e6932015-07-09 15:20:08 +05301014static struct snd_soc_platform_driver skl_platform_drv = {
Jeeja KPb663a8c2015-10-07 11:31:57 +01001015 .probe = skl_platform_soc_probe,
Jeeja KPa40e6932015-07-09 15:20:08 +05301016 .ops = &skl_platform_ops,
1017 .pcm_new = skl_pcm_new,
1018 .pcm_free = skl_pcm_free,
1019};
1020
1021static const struct snd_soc_component_driver skl_component = {
1022 .name = "pcm",
1023};
1024
1025int skl_platform_register(struct device *dev)
1026{
1027 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +01001028 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1029 struct skl *skl = ebus_to_skl(ebus);
1030
1031 INIT_LIST_HEAD(&skl->ppl_list);
Jeeja KPa40e6932015-07-09 15:20:08 +05301032
1033 ret = snd_soc_register_platform(dev, &skl_platform_drv);
1034 if (ret) {
1035 dev_err(dev, "soc platform registration failed %d\n", ret);
1036 return ret;
1037 }
1038 ret = snd_soc_register_component(dev, &skl_component,
1039 skl_platform_dai,
1040 ARRAY_SIZE(skl_platform_dai));
1041 if (ret) {
1042 dev_err(dev, "soc component registration failed %d\n", ret);
1043 snd_soc_unregister_platform(dev);
1044 }
1045
1046 return ret;
1047
1048}
1049
1050int skl_platform_unregister(struct device *dev)
1051{
1052 snd_soc_unregister_component(dev);
1053 snd_soc_unregister_platform(dev);
1054 return 0;
1055}