Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
| 3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
| 10 | #include <linux/clk.h> |
Thierry Reding | 9eb9b22 | 2013-09-24 16:32:47 +0200 | [diff] [blame] | 11 | #include <linux/debugfs.h> |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 12 | #include <linux/iommu.h> |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 13 | #include <linux/reset.h> |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 14 | |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 15 | #include <soc/tegra/pmc.h> |
| 16 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 17 | #include "dc.h" |
| 18 | #include "drm.h" |
| 19 | #include "gem.h" |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 20 | |
Thierry Reding | 9d44189 | 2014-11-24 17:02:53 +0100 | [diff] [blame] | 21 | #include <drm/drm_atomic.h> |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 22 | #include <drm/drm_atomic_helper.h> |
Daniel Vetter | 3cb9ae4 | 2014-10-29 10:03:57 +0100 | [diff] [blame] | 23 | #include <drm/drm_plane_helper.h> |
| 24 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 25 | struct tegra_dc_soc_info { |
Thierry Reding | 42d0659 | 2014-12-08 15:45:39 +0100 | [diff] [blame] | 26 | bool supports_border_color; |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 27 | bool supports_interlacing; |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 28 | bool supports_cursor; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 29 | bool supports_block_linear; |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 30 | unsigned int pitch_align; |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 31 | bool has_powergate; |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 32 | }; |
| 33 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 34 | struct tegra_plane { |
| 35 | struct drm_plane base; |
| 36 | unsigned int index; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 37 | }; |
| 38 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 39 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
| 40 | { |
| 41 | return container_of(plane, struct tegra_plane, base); |
| 42 | } |
| 43 | |
Thierry Reding | ca915b1 | 2014-12-08 16:14:45 +0100 | [diff] [blame] | 44 | struct tegra_dc_state { |
| 45 | struct drm_crtc_state base; |
| 46 | |
| 47 | struct clk *clk; |
| 48 | unsigned long pclk; |
| 49 | unsigned int div; |
| 50 | }; |
| 51 | |
| 52 | static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) |
| 53 | { |
| 54 | if (state) |
| 55 | return container_of(state, struct tegra_dc_state, base); |
| 56 | |
| 57 | return NULL; |
| 58 | } |
| 59 | |
Thierry Reding | 205d48e | 2014-10-21 13:41:46 +0200 | [diff] [blame] | 60 | static void tegra_dc_window_commit(struct tegra_dc *dc, unsigned int index) |
| 61 | { |
| 62 | u32 value = WIN_A_ACT_REQ << index; |
| 63 | |
| 64 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); |
| 65 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
| 66 | } |
| 67 | |
| 68 | static void tegra_dc_cursor_commit(struct tegra_dc *dc) |
| 69 | { |
| 70 | tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 71 | tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 72 | } |
| 73 | |
Thierry Reding | d700ba7 | 2014-12-08 15:50:04 +0100 | [diff] [blame] | 74 | /* |
Thierry Reding | 86df256 | 2014-12-08 16:03:53 +0100 | [diff] [blame] | 75 | * Reads the active copy of a register. This takes the dc->lock spinlock to |
| 76 | * prevent races with the VBLANK processing which also needs access to the |
| 77 | * active copy of some registers. |
| 78 | */ |
| 79 | static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) |
| 80 | { |
| 81 | unsigned long flags; |
| 82 | u32 value; |
| 83 | |
| 84 | spin_lock_irqsave(&dc->lock, flags); |
| 85 | |
| 86 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); |
| 87 | value = tegra_dc_readl(dc, offset); |
| 88 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); |
| 89 | |
| 90 | spin_unlock_irqrestore(&dc->lock, flags); |
| 91 | return value; |
| 92 | } |
| 93 | |
| 94 | /* |
Thierry Reding | d700ba7 | 2014-12-08 15:50:04 +0100 | [diff] [blame] | 95 | * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the |
| 96 | * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. |
| 97 | * Latching happens mmediately if the display controller is in STOP mode or |
| 98 | * on the next frame boundary otherwise. |
| 99 | * |
| 100 | * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The |
| 101 | * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits |
| 102 | * are written. When the *_ACT_REQ bits are written, the ARM copy is latched |
| 103 | * into the ACTIVE copy, either immediately if the display controller is in |
| 104 | * STOP mode, or at the next frame boundary otherwise. |
| 105 | */ |
Thierry Reding | 62b9e06 | 2014-11-21 17:33:33 +0100 | [diff] [blame] | 106 | void tegra_dc_commit(struct tegra_dc *dc) |
Thierry Reding | 205d48e | 2014-10-21 13:41:46 +0200 | [diff] [blame] | 107 | { |
| 108 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 109 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 110 | } |
| 111 | |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 112 | static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap) |
| 113 | { |
| 114 | /* assume no swapping of fetched data */ |
| 115 | if (swap) |
| 116 | *swap = BYTE_SWAP_NOSWAP; |
| 117 | |
| 118 | switch (format) { |
| 119 | case DRM_FORMAT_XBGR8888: |
| 120 | return WIN_COLOR_DEPTH_R8G8B8A8; |
| 121 | |
| 122 | case DRM_FORMAT_XRGB8888: |
| 123 | return WIN_COLOR_DEPTH_B8G8R8A8; |
| 124 | |
| 125 | case DRM_FORMAT_RGB565: |
| 126 | return WIN_COLOR_DEPTH_B5G6R5; |
| 127 | |
| 128 | case DRM_FORMAT_UYVY: |
| 129 | return WIN_COLOR_DEPTH_YCbCr422; |
| 130 | |
| 131 | case DRM_FORMAT_YUYV: |
| 132 | if (swap) |
| 133 | *swap = BYTE_SWAP_SWAP2; |
| 134 | |
| 135 | return WIN_COLOR_DEPTH_YCbCr422; |
| 136 | |
| 137 | case DRM_FORMAT_YUV420: |
| 138 | return WIN_COLOR_DEPTH_YCbCr420P; |
| 139 | |
| 140 | case DRM_FORMAT_YUV422: |
| 141 | return WIN_COLOR_DEPTH_YCbCr422P; |
| 142 | |
| 143 | default: |
| 144 | break; |
| 145 | } |
| 146 | |
| 147 | WARN(1, "unsupported pixel format %u, using default\n", format); |
| 148 | return WIN_COLOR_DEPTH_B8G8R8A8; |
| 149 | } |
| 150 | |
| 151 | static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) |
| 152 | { |
| 153 | switch (format) { |
| 154 | case WIN_COLOR_DEPTH_YCbCr422: |
| 155 | case WIN_COLOR_DEPTH_YUV422: |
| 156 | if (planar) |
| 157 | *planar = false; |
| 158 | |
| 159 | return true; |
| 160 | |
| 161 | case WIN_COLOR_DEPTH_YCbCr420P: |
| 162 | case WIN_COLOR_DEPTH_YUV420P: |
| 163 | case WIN_COLOR_DEPTH_YCbCr422P: |
| 164 | case WIN_COLOR_DEPTH_YUV422P: |
| 165 | case WIN_COLOR_DEPTH_YCbCr422R: |
| 166 | case WIN_COLOR_DEPTH_YUV422R: |
| 167 | case WIN_COLOR_DEPTH_YCbCr422RA: |
| 168 | case WIN_COLOR_DEPTH_YUV422RA: |
| 169 | if (planar) |
| 170 | *planar = true; |
| 171 | |
| 172 | return true; |
| 173 | } |
| 174 | |
Thierry Reding | fb35c6b | 2014-12-08 15:55:28 +0100 | [diff] [blame] | 175 | if (planar) |
| 176 | *planar = false; |
| 177 | |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 178 | return false; |
| 179 | } |
| 180 | |
| 181 | static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, |
| 182 | unsigned int bpp) |
| 183 | { |
| 184 | fixed20_12 outf = dfixed_init(out); |
| 185 | fixed20_12 inf = dfixed_init(in); |
| 186 | u32 dda_inc; |
| 187 | int max; |
| 188 | |
| 189 | if (v) |
| 190 | max = 15; |
| 191 | else { |
| 192 | switch (bpp) { |
| 193 | case 2: |
| 194 | max = 8; |
| 195 | break; |
| 196 | |
| 197 | default: |
| 198 | WARN_ON_ONCE(1); |
| 199 | /* fallthrough */ |
| 200 | case 4: |
| 201 | max = 4; |
| 202 | break; |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); |
| 207 | inf.full -= dfixed_const(1); |
| 208 | |
| 209 | dda_inc = dfixed_div(inf, outf); |
| 210 | dda_inc = min_t(u32, dda_inc, dfixed_const(max)); |
| 211 | |
| 212 | return dda_inc; |
| 213 | } |
| 214 | |
| 215 | static inline u32 compute_initial_dda(unsigned int in) |
| 216 | { |
| 217 | fixed20_12 inf = dfixed_init(in); |
| 218 | return dfixed_frac(inf); |
| 219 | } |
| 220 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 221 | static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, |
| 222 | const struct tegra_dc_window *window) |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 223 | { |
| 224 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 225 | unsigned long value, flags; |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 226 | bool yuv, planar; |
| 227 | |
| 228 | /* |
| 229 | * For YUV planar modes, the number of bytes per pixel takes into |
| 230 | * account only the luma component and therefore is 1. |
| 231 | */ |
| 232 | yuv = tegra_dc_format_is_yuv(window->format, &planar); |
| 233 | if (!yuv) |
| 234 | bpp = window->bits_per_pixel / 8; |
| 235 | else |
| 236 | bpp = planar ? 1 : 2; |
| 237 | |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 238 | spin_lock_irqsave(&dc->lock, flags); |
| 239 | |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 240 | value = WINDOW_A_SELECT << index; |
| 241 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); |
| 242 | |
| 243 | tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); |
| 244 | tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); |
| 245 | |
| 246 | value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); |
| 247 | tegra_dc_writel(dc, value, DC_WIN_POSITION); |
| 248 | |
| 249 | value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); |
| 250 | tegra_dc_writel(dc, value, DC_WIN_SIZE); |
| 251 | |
| 252 | h_offset = window->src.x * bpp; |
| 253 | v_offset = window->src.y; |
| 254 | h_size = window->src.w * bpp; |
| 255 | v_size = window->src.h; |
| 256 | |
| 257 | value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); |
| 258 | tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); |
| 259 | |
| 260 | /* |
| 261 | * For DDA computations the number of bytes per pixel for YUV planar |
| 262 | * modes needs to take into account all Y, U and V components. |
| 263 | */ |
| 264 | if (yuv && planar) |
| 265 | bpp = 2; |
| 266 | |
| 267 | h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); |
| 268 | v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); |
| 269 | |
| 270 | value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); |
| 271 | tegra_dc_writel(dc, value, DC_WIN_DDA_INC); |
| 272 | |
| 273 | h_dda = compute_initial_dda(window->src.x); |
| 274 | v_dda = compute_initial_dda(window->src.y); |
| 275 | |
| 276 | tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); |
| 277 | tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); |
| 278 | |
| 279 | tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); |
| 280 | tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); |
| 281 | |
| 282 | tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); |
| 283 | |
| 284 | if (yuv && planar) { |
| 285 | tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); |
| 286 | tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); |
| 287 | value = window->stride[1] << 16 | window->stride[0]; |
| 288 | tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); |
| 289 | } else { |
| 290 | tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); |
| 291 | } |
| 292 | |
| 293 | if (window->bottom_up) |
| 294 | v_offset += window->src.h - 1; |
| 295 | |
| 296 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); |
| 297 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); |
| 298 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 299 | if (dc->soc->supports_block_linear) { |
| 300 | unsigned long height = window->tiling.value; |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 301 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 302 | switch (window->tiling.mode) { |
| 303 | case TEGRA_BO_TILING_MODE_PITCH: |
| 304 | value = DC_WINBUF_SURFACE_KIND_PITCH; |
| 305 | break; |
| 306 | |
| 307 | case TEGRA_BO_TILING_MODE_TILED: |
| 308 | value = DC_WINBUF_SURFACE_KIND_TILED; |
| 309 | break; |
| 310 | |
| 311 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 312 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | |
| 313 | DC_WINBUF_SURFACE_KIND_BLOCK; |
| 314 | break; |
| 315 | } |
| 316 | |
| 317 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); |
| 318 | } else { |
| 319 | switch (window->tiling.mode) { |
| 320 | case TEGRA_BO_TILING_MODE_PITCH: |
| 321 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | |
| 322 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; |
| 323 | break; |
| 324 | |
| 325 | case TEGRA_BO_TILING_MODE_TILED: |
| 326 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | |
| 327 | DC_WIN_BUFFER_ADDR_MODE_TILE; |
| 328 | break; |
| 329 | |
| 330 | case TEGRA_BO_TILING_MODE_BLOCK: |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 331 | /* |
| 332 | * No need to handle this here because ->atomic_check |
| 333 | * will already have filtered it out. |
| 334 | */ |
| 335 | break; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 336 | } |
| 337 | |
| 338 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); |
| 339 | } |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 340 | |
| 341 | value = WIN_ENABLE; |
| 342 | |
| 343 | if (yuv) { |
| 344 | /* setup default colorspace conversion coefficients */ |
| 345 | tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); |
| 346 | tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); |
| 347 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); |
| 348 | tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); |
| 349 | tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); |
| 350 | tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); |
| 351 | tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); |
| 352 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); |
| 353 | |
| 354 | value |= CSC_ENABLE; |
| 355 | } else if (window->bits_per_pixel < 24) { |
| 356 | value |= COLOR_EXPAND; |
| 357 | } |
| 358 | |
| 359 | if (window->bottom_up) |
| 360 | value |= V_DIRECTION; |
| 361 | |
| 362 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
| 363 | |
| 364 | /* |
| 365 | * Disable blending and assume Window A is the bottom-most window, |
| 366 | * Window C is the top-most window and Window B is in the middle. |
| 367 | */ |
| 368 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); |
| 369 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); |
| 370 | |
| 371 | switch (index) { |
| 372 | case 0: |
| 373 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); |
| 374 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); |
| 375 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); |
| 376 | break; |
| 377 | |
| 378 | case 1: |
| 379 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); |
| 380 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); |
| 381 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); |
| 382 | break; |
| 383 | |
| 384 | case 2: |
| 385 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); |
| 386 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); |
| 387 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); |
| 388 | break; |
| 389 | } |
| 390 | |
Thierry Reding | 205d48e | 2014-10-21 13:41:46 +0200 | [diff] [blame] | 391 | tegra_dc_window_commit(dc, index); |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 392 | |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 393 | spin_unlock_irqrestore(&dc->lock, flags); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 394 | } |
| 395 | |
| 396 | static void tegra_plane_destroy(struct drm_plane *plane) |
| 397 | { |
| 398 | struct tegra_plane *p = to_tegra_plane(plane); |
| 399 | |
| 400 | drm_plane_cleanup(plane); |
| 401 | kfree(p); |
| 402 | } |
| 403 | |
| 404 | static const u32 tegra_primary_plane_formats[] = { |
| 405 | DRM_FORMAT_XBGR8888, |
| 406 | DRM_FORMAT_XRGB8888, |
| 407 | DRM_FORMAT_RGB565, |
| 408 | }; |
| 409 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 410 | static void tegra_primary_plane_destroy(struct drm_plane *plane) |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 411 | { |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 412 | tegra_plane_destroy(plane); |
| 413 | } |
| 414 | |
| 415 | static const struct drm_plane_funcs tegra_primary_plane_funcs = { |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 416 | .update_plane = drm_atomic_helper_update_plane, |
| 417 | .disable_plane = drm_atomic_helper_disable_plane, |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 418 | .destroy = tegra_primary_plane_destroy, |
Thierry Reding | 9d44189 | 2014-11-24 17:02:53 +0100 | [diff] [blame] | 419 | .reset = drm_atomic_helper_plane_reset, |
| 420 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 421 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
| 422 | }; |
| 423 | |
| 424 | static int tegra_plane_prepare_fb(struct drm_plane *plane, |
| 425 | struct drm_framebuffer *fb) |
| 426 | { |
| 427 | return 0; |
| 428 | } |
| 429 | |
| 430 | static void tegra_plane_cleanup_fb(struct drm_plane *plane, |
| 431 | struct drm_framebuffer *fb) |
| 432 | { |
| 433 | } |
| 434 | |
| 435 | static int tegra_plane_atomic_check(struct drm_plane *plane, |
| 436 | struct drm_plane_state *state) |
| 437 | { |
| 438 | struct tegra_dc *dc = to_tegra_dc(state->crtc); |
| 439 | struct tegra_bo_tiling tiling; |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 440 | int err; |
| 441 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 442 | /* no need for further checks if the plane is being disabled */ |
| 443 | if (!state->crtc) |
| 444 | return 0; |
| 445 | |
| 446 | err = tegra_fb_get_tiling(state->fb, &tiling); |
| 447 | if (err < 0) |
| 448 | return err; |
| 449 | |
| 450 | if (tiling.mode == TEGRA_BO_TILING_MODE_BLOCK && |
| 451 | !dc->soc->supports_block_linear) { |
| 452 | DRM_ERROR("hardware doesn't support block linear mode\n"); |
| 453 | return -EINVAL; |
| 454 | } |
| 455 | |
| 456 | /* |
| 457 | * Tegra doesn't support different strides for U and V planes so we |
| 458 | * error out if the user tries to display a framebuffer with such a |
| 459 | * configuration. |
| 460 | */ |
| 461 | if (drm_format_num_planes(state->fb->pixel_format) > 2) { |
| 462 | if (state->fb->pitches[2] != state->fb->pitches[1]) { |
| 463 | DRM_ERROR("unsupported UV-plane configuration\n"); |
| 464 | return -EINVAL; |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | return 0; |
| 469 | } |
| 470 | |
| 471 | static void tegra_plane_atomic_update(struct drm_plane *plane, |
| 472 | struct drm_plane_state *old_state) |
| 473 | { |
| 474 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); |
| 475 | struct drm_framebuffer *fb = plane->state->fb; |
| 476 | struct tegra_plane *p = to_tegra_plane(plane); |
| 477 | struct tegra_dc_window window; |
| 478 | unsigned int i; |
| 479 | int err; |
| 480 | |
| 481 | /* rien ne va plus */ |
| 482 | if (!plane->state->crtc || !plane->state->fb) |
| 483 | return; |
| 484 | |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 485 | memset(&window, 0, sizeof(window)); |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 486 | window.src.x = plane->state->src_x >> 16; |
| 487 | window.src.y = plane->state->src_y >> 16; |
| 488 | window.src.w = plane->state->src_w >> 16; |
| 489 | window.src.h = plane->state->src_h >> 16; |
| 490 | window.dst.x = plane->state->crtc_x; |
| 491 | window.dst.y = plane->state->crtc_y; |
| 492 | window.dst.w = plane->state->crtc_w; |
| 493 | window.dst.h = plane->state->crtc_h; |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 494 | window.format = tegra_dc_format(fb->pixel_format, &window.swap); |
| 495 | window.bits_per_pixel = fb->bits_per_pixel; |
| 496 | window.bottom_up = tegra_fb_is_bottom_up(fb); |
| 497 | |
| 498 | err = tegra_fb_get_tiling(fb, &window.tiling); |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 499 | WARN_ON(err < 0); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 500 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 501 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { |
| 502 | struct tegra_bo *bo = tegra_fb_get_plane(fb, i); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 503 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 504 | window.base[i] = bo->paddr + fb->offsets[i]; |
| 505 | window.stride[i] = fb->pitches[i]; |
| 506 | } |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 507 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 508 | tegra_dc_setup_window(dc, p->index, &window); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 509 | } |
| 510 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 511 | static void tegra_plane_atomic_disable(struct drm_plane *plane, |
| 512 | struct drm_plane_state *old_state) |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 513 | { |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 514 | struct tegra_plane *p = to_tegra_plane(plane); |
| 515 | struct tegra_dc *dc; |
| 516 | unsigned long flags; |
| 517 | u32 value; |
| 518 | |
| 519 | /* rien ne va plus */ |
| 520 | if (!old_state || !old_state->crtc) |
| 521 | return; |
| 522 | |
| 523 | dc = to_tegra_dc(old_state->crtc); |
| 524 | |
| 525 | spin_lock_irqsave(&dc->lock, flags); |
| 526 | |
| 527 | value = WINDOW_A_SELECT << p->index; |
| 528 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); |
| 529 | |
| 530 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); |
| 531 | value &= ~WIN_ENABLE; |
| 532 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
| 533 | |
| 534 | tegra_dc_window_commit(dc, p->index); |
| 535 | |
| 536 | spin_unlock_irqrestore(&dc->lock, flags); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 537 | } |
| 538 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 539 | static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = { |
| 540 | .prepare_fb = tegra_plane_prepare_fb, |
| 541 | .cleanup_fb = tegra_plane_cleanup_fb, |
| 542 | .atomic_check = tegra_plane_atomic_check, |
| 543 | .atomic_update = tegra_plane_atomic_update, |
| 544 | .atomic_disable = tegra_plane_atomic_disable, |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 545 | }; |
| 546 | |
| 547 | static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, |
| 548 | struct tegra_dc *dc) |
| 549 | { |
Thierry Reding | 518e622 | 2014-12-16 18:04:08 +0100 | [diff] [blame] | 550 | /* |
| 551 | * Ideally this would use drm_crtc_mask(), but that would require the |
| 552 | * CRTC to already be in the mode_config's list of CRTCs. However, it |
| 553 | * will only be added to that list in the drm_crtc_init_with_planes() |
| 554 | * (in tegra_dc_init()), which in turn requires registration of these |
| 555 | * planes. So we have ourselves a nice little chicken and egg problem |
| 556 | * here. |
| 557 | * |
| 558 | * We work around this by manually creating the mask from the number |
| 559 | * of CRTCs that have been registered, and should therefore always be |
| 560 | * the same as drm_crtc_index() after registration. |
| 561 | */ |
| 562 | unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc; |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 563 | struct tegra_plane *plane; |
| 564 | unsigned int num_formats; |
| 565 | const u32 *formats; |
| 566 | int err; |
| 567 | |
| 568 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
| 569 | if (!plane) |
| 570 | return ERR_PTR(-ENOMEM); |
| 571 | |
| 572 | num_formats = ARRAY_SIZE(tegra_primary_plane_formats); |
| 573 | formats = tegra_primary_plane_formats; |
| 574 | |
Thierry Reding | 518e622 | 2014-12-16 18:04:08 +0100 | [diff] [blame] | 575 | err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 576 | &tegra_primary_plane_funcs, formats, |
| 577 | num_formats, DRM_PLANE_TYPE_PRIMARY); |
| 578 | if (err < 0) { |
| 579 | kfree(plane); |
| 580 | return ERR_PTR(err); |
| 581 | } |
| 582 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 583 | drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs); |
| 584 | |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 585 | return &plane->base; |
| 586 | } |
| 587 | |
| 588 | static const u32 tegra_cursor_plane_formats[] = { |
| 589 | DRM_FORMAT_RGBA8888, |
| 590 | }; |
| 591 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 592 | static int tegra_cursor_atomic_check(struct drm_plane *plane, |
| 593 | struct drm_plane_state *state) |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 594 | { |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 595 | /* no need for further checks if the plane is being disabled */ |
| 596 | if (!state->crtc) |
| 597 | return 0; |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 598 | |
| 599 | /* scaling not supported for cursor */ |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 600 | if ((state->src_w >> 16 != state->crtc_w) || |
| 601 | (state->src_h >> 16 != state->crtc_h)) |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 602 | return -EINVAL; |
| 603 | |
| 604 | /* only square cursors supported */ |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 605 | if (state->src_w != state->src_h) |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 606 | return -EINVAL; |
| 607 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 608 | if (state->crtc_w != 32 && state->crtc_w != 64 && |
| 609 | state->crtc_w != 128 && state->crtc_w != 256) |
| 610 | return -EINVAL; |
| 611 | |
| 612 | return 0; |
| 613 | } |
| 614 | |
| 615 | static void tegra_cursor_atomic_update(struct drm_plane *plane, |
| 616 | struct drm_plane_state *old_state) |
| 617 | { |
| 618 | struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0); |
| 619 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); |
| 620 | struct drm_plane_state *state = plane->state; |
| 621 | u32 value = CURSOR_CLIP_DISPLAY; |
| 622 | |
| 623 | /* rien ne va plus */ |
| 624 | if (!plane->state->crtc || !plane->state->fb) |
| 625 | return; |
| 626 | |
| 627 | switch (state->crtc_w) { |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 628 | case 32: |
| 629 | value |= CURSOR_SIZE_32x32; |
| 630 | break; |
| 631 | |
| 632 | case 64: |
| 633 | value |= CURSOR_SIZE_64x64; |
| 634 | break; |
| 635 | |
| 636 | case 128: |
| 637 | value |= CURSOR_SIZE_128x128; |
| 638 | break; |
| 639 | |
| 640 | case 256: |
| 641 | value |= CURSOR_SIZE_256x256; |
| 642 | break; |
| 643 | |
| 644 | default: |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 645 | WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, |
| 646 | state->crtc_h); |
| 647 | return; |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 648 | } |
| 649 | |
| 650 | value |= (bo->paddr >> 10) & 0x3fffff; |
| 651 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); |
| 652 | |
| 653 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
| 654 | value = (bo->paddr >> 32) & 0x3; |
| 655 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); |
| 656 | #endif |
| 657 | |
| 658 | /* enable cursor and set blend mode */ |
| 659 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 660 | value |= CURSOR_ENABLE; |
| 661 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 662 | |
| 663 | value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); |
| 664 | value &= ~CURSOR_DST_BLEND_MASK; |
| 665 | value &= ~CURSOR_SRC_BLEND_MASK; |
| 666 | value |= CURSOR_MODE_NORMAL; |
| 667 | value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; |
| 668 | value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; |
| 669 | value |= CURSOR_ALPHA; |
| 670 | tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); |
| 671 | |
| 672 | /* position the cursor */ |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 673 | value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 674 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); |
| 675 | |
| 676 | /* apply changes */ |
| 677 | tegra_dc_cursor_commit(dc); |
| 678 | tegra_dc_commit(dc); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 679 | } |
| 680 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 681 | static void tegra_cursor_atomic_disable(struct drm_plane *plane, |
| 682 | struct drm_plane_state *old_state) |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 683 | { |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 684 | struct tegra_dc *dc; |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 685 | u32 value; |
| 686 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 687 | /* rien ne va plus */ |
| 688 | if (!old_state || !old_state->crtc) |
| 689 | return; |
| 690 | |
| 691 | dc = to_tegra_dc(old_state->crtc); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 692 | |
| 693 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 694 | value &= ~CURSOR_ENABLE; |
| 695 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 696 | |
| 697 | tegra_dc_cursor_commit(dc); |
| 698 | tegra_dc_commit(dc); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 699 | } |
| 700 | |
| 701 | static const struct drm_plane_funcs tegra_cursor_plane_funcs = { |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 702 | .update_plane = drm_atomic_helper_update_plane, |
| 703 | .disable_plane = drm_atomic_helper_disable_plane, |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 704 | .destroy = tegra_plane_destroy, |
Thierry Reding | 9d44189 | 2014-11-24 17:02:53 +0100 | [diff] [blame] | 705 | .reset = drm_atomic_helper_plane_reset, |
| 706 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 707 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
| 708 | }; |
| 709 | |
| 710 | static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { |
| 711 | .prepare_fb = tegra_plane_prepare_fb, |
| 712 | .cleanup_fb = tegra_plane_cleanup_fb, |
| 713 | .atomic_check = tegra_cursor_atomic_check, |
| 714 | .atomic_update = tegra_cursor_atomic_update, |
| 715 | .atomic_disable = tegra_cursor_atomic_disable, |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 716 | }; |
| 717 | |
| 718 | static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, |
| 719 | struct tegra_dc *dc) |
| 720 | { |
| 721 | struct tegra_plane *plane; |
| 722 | unsigned int num_formats; |
| 723 | const u32 *formats; |
| 724 | int err; |
| 725 | |
| 726 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
| 727 | if (!plane) |
| 728 | return ERR_PTR(-ENOMEM); |
| 729 | |
| 730 | num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); |
| 731 | formats = tegra_cursor_plane_formats; |
| 732 | |
| 733 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, |
| 734 | &tegra_cursor_plane_funcs, formats, |
| 735 | num_formats, DRM_PLANE_TYPE_CURSOR); |
| 736 | if (err < 0) { |
| 737 | kfree(plane); |
| 738 | return ERR_PTR(err); |
| 739 | } |
| 740 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 741 | drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); |
| 742 | |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 743 | return &plane->base; |
| 744 | } |
| 745 | |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 746 | static void tegra_overlay_plane_destroy(struct drm_plane *plane) |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 747 | { |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 748 | tegra_plane_destroy(plane); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 749 | } |
| 750 | |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 751 | static const struct drm_plane_funcs tegra_overlay_plane_funcs = { |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 752 | .update_plane = drm_atomic_helper_update_plane, |
| 753 | .disable_plane = drm_atomic_helper_disable_plane, |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 754 | .destroy = tegra_overlay_plane_destroy, |
Thierry Reding | 9d44189 | 2014-11-24 17:02:53 +0100 | [diff] [blame] | 755 | .reset = drm_atomic_helper_plane_reset, |
| 756 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 757 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 758 | }; |
| 759 | |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 760 | static const uint32_t tegra_overlay_plane_formats[] = { |
Thierry Reding | dbe4d9a | 2013-03-22 15:37:30 +0100 | [diff] [blame] | 761 | DRM_FORMAT_XBGR8888, |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 762 | DRM_FORMAT_XRGB8888, |
Thierry Reding | dbe4d9a | 2013-03-22 15:37:30 +0100 | [diff] [blame] | 763 | DRM_FORMAT_RGB565, |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 764 | DRM_FORMAT_UYVY, |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 765 | DRM_FORMAT_YUYV, |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 766 | DRM_FORMAT_YUV420, |
| 767 | DRM_FORMAT_YUV422, |
| 768 | }; |
| 769 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 770 | static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = { |
| 771 | .prepare_fb = tegra_plane_prepare_fb, |
| 772 | .cleanup_fb = tegra_plane_cleanup_fb, |
| 773 | .atomic_check = tegra_plane_atomic_check, |
| 774 | .atomic_update = tegra_plane_atomic_update, |
| 775 | .atomic_disable = tegra_plane_atomic_disable, |
| 776 | }; |
| 777 | |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 778 | static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, |
| 779 | struct tegra_dc *dc, |
| 780 | unsigned int index) |
| 781 | { |
| 782 | struct tegra_plane *plane; |
| 783 | unsigned int num_formats; |
| 784 | const u32 *formats; |
| 785 | int err; |
| 786 | |
| 787 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
| 788 | if (!plane) |
| 789 | return ERR_PTR(-ENOMEM); |
| 790 | |
| 791 | plane->index = index; |
| 792 | |
| 793 | num_formats = ARRAY_SIZE(tegra_overlay_plane_formats); |
| 794 | formats = tegra_overlay_plane_formats; |
| 795 | |
| 796 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, |
| 797 | &tegra_overlay_plane_funcs, formats, |
| 798 | num_formats, DRM_PLANE_TYPE_OVERLAY); |
| 799 | if (err < 0) { |
| 800 | kfree(plane); |
| 801 | return ERR_PTR(err); |
| 802 | } |
| 803 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 804 | drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs); |
| 805 | |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 806 | return &plane->base; |
| 807 | } |
| 808 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 809 | static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) |
| 810 | { |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 811 | struct drm_plane *plane; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 812 | unsigned int i; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 813 | |
| 814 | for (i = 0; i < 2; i++) { |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 815 | plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); |
| 816 | if (IS_ERR(plane)) |
| 817 | return PTR_ERR(plane); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 818 | } |
| 819 | |
| 820 | return 0; |
| 821 | } |
| 822 | |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 823 | static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, |
| 824 | struct drm_framebuffer *fb) |
| 825 | { |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 826 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 827 | unsigned int h_offset = 0, v_offset = 0; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 828 | struct tegra_bo_tiling tiling; |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 829 | unsigned long value, flags; |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 830 | unsigned int format, swap; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 831 | int err; |
| 832 | |
| 833 | err = tegra_fb_get_tiling(fb, &tiling); |
| 834 | if (err < 0) |
| 835 | return err; |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 836 | |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 837 | spin_lock_irqsave(&dc->lock, flags); |
| 838 | |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 839 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
| 840 | |
| 841 | value = fb->offsets[0] + y * fb->pitches[0] + |
| 842 | x * fb->bits_per_pixel / 8; |
| 843 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 844 | tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 845 | tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 846 | |
| 847 | format = tegra_dc_format(fb->pixel_format, &swap); |
Thierry Reding | ed683ae | 2013-04-22 21:31:15 +0200 | [diff] [blame] | 848 | tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH); |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 849 | tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP); |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 850 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 851 | if (dc->soc->supports_block_linear) { |
| 852 | unsigned long height = tiling.value; |
Thierry Reding | 773af77 | 2013-10-04 22:34:01 +0200 | [diff] [blame] | 853 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 854 | switch (tiling.mode) { |
| 855 | case TEGRA_BO_TILING_MODE_PITCH: |
| 856 | value = DC_WINBUF_SURFACE_KIND_PITCH; |
| 857 | break; |
| 858 | |
| 859 | case TEGRA_BO_TILING_MODE_TILED: |
| 860 | value = DC_WINBUF_SURFACE_KIND_TILED; |
| 861 | break; |
| 862 | |
| 863 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 864 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | |
| 865 | DC_WINBUF_SURFACE_KIND_BLOCK; |
| 866 | break; |
| 867 | } |
| 868 | |
| 869 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); |
| 870 | } else { |
| 871 | switch (tiling.mode) { |
| 872 | case TEGRA_BO_TILING_MODE_PITCH: |
| 873 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | |
| 874 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; |
| 875 | break; |
| 876 | |
| 877 | case TEGRA_BO_TILING_MODE_TILED: |
| 878 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | |
| 879 | DC_WIN_BUFFER_ADDR_MODE_TILE; |
| 880 | break; |
| 881 | |
| 882 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 883 | DRM_ERROR("hardware doesn't support block linear mode\n"); |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 884 | spin_unlock_irqrestore(&dc->lock, flags); |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 885 | return -EINVAL; |
| 886 | } |
| 887 | |
| 888 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); |
| 889 | } |
Thierry Reding | 773af77 | 2013-10-04 22:34:01 +0200 | [diff] [blame] | 890 | |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 891 | /* make sure bottom-up buffers are properly displayed */ |
| 892 | if (tegra_fb_is_bottom_up(fb)) { |
| 893 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); |
Thierry Reding | eba6650 | 2014-02-25 12:04:06 +0100 | [diff] [blame] | 894 | value |= V_DIRECTION; |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 895 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
| 896 | |
| 897 | v_offset += fb->height - 1; |
| 898 | } else { |
| 899 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); |
Thierry Reding | eba6650 | 2014-02-25 12:04:06 +0100 | [diff] [blame] | 900 | value &= ~V_DIRECTION; |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 901 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
| 902 | } |
| 903 | |
| 904 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); |
| 905 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); |
| 906 | |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 907 | value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
Thierry Reding | 205d48e | 2014-10-21 13:41:46 +0200 | [diff] [blame] | 908 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 909 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
| 910 | |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 911 | spin_unlock_irqrestore(&dc->lock, flags); |
| 912 | |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 913 | return 0; |
| 914 | } |
| 915 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 916 | void tegra_dc_enable_vblank(struct tegra_dc *dc) |
| 917 | { |
| 918 | unsigned long value, flags; |
| 919 | |
| 920 | spin_lock_irqsave(&dc->lock, flags); |
| 921 | |
| 922 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); |
| 923 | value |= VBLANK_INT; |
| 924 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); |
| 925 | |
| 926 | spin_unlock_irqrestore(&dc->lock, flags); |
| 927 | } |
| 928 | |
| 929 | void tegra_dc_disable_vblank(struct tegra_dc *dc) |
| 930 | { |
| 931 | unsigned long value, flags; |
| 932 | |
| 933 | spin_lock_irqsave(&dc->lock, flags); |
| 934 | |
| 935 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); |
| 936 | value &= ~VBLANK_INT; |
| 937 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); |
| 938 | |
| 939 | spin_unlock_irqrestore(&dc->lock, flags); |
| 940 | } |
| 941 | |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 942 | static void tegra_dc_finish_page_flip(struct tegra_dc *dc) |
| 943 | { |
| 944 | struct drm_device *drm = dc->base.dev; |
| 945 | struct drm_crtc *crtc = &dc->base; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 946 | unsigned long flags, base; |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 947 | struct tegra_bo *bo; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 948 | |
Thierry Reding | 6b59cc1 | 2014-12-16 16:33:27 +0100 | [diff] [blame] | 949 | spin_lock_irqsave(&drm->event_lock, flags); |
| 950 | |
| 951 | if (!dc->event) { |
| 952 | spin_unlock_irqrestore(&drm->event_lock, flags); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 953 | return; |
Thierry Reding | 6b59cc1 | 2014-12-16 16:33:27 +0100 | [diff] [blame] | 954 | } |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 955 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 956 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 957 | |
Dan Carpenter | 8643bc6 | 2015-01-07 14:01:26 +0300 | [diff] [blame] | 958 | spin_lock(&dc->lock); |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 959 | |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 960 | /* check if new start address has been latched */ |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 961 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 962 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); |
| 963 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); |
| 964 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); |
| 965 | |
Dan Carpenter | 8643bc6 | 2015-01-07 14:01:26 +0300 | [diff] [blame] | 966 | spin_unlock(&dc->lock); |
Sean Paul | 93396d0 | 2014-11-19 13:04:49 -0500 | [diff] [blame] | 967 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 968 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
Thierry Reding | ed7dae5 | 2014-12-16 16:03:13 +0100 | [diff] [blame] | 969 | drm_crtc_send_vblank_event(crtc, dc->event); |
| 970 | drm_crtc_vblank_put(crtc); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 971 | dc->event = NULL; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 972 | } |
Thierry Reding | 6b59cc1 | 2014-12-16 16:33:27 +0100 | [diff] [blame] | 973 | |
| 974 | spin_unlock_irqrestore(&drm->event_lock, flags); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 975 | } |
| 976 | |
| 977 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) |
| 978 | { |
| 979 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 980 | struct drm_device *drm = crtc->dev; |
| 981 | unsigned long flags; |
| 982 | |
| 983 | spin_lock_irqsave(&drm->event_lock, flags); |
| 984 | |
| 985 | if (dc->event && dc->event->base.file_priv == file) { |
| 986 | dc->event->base.destroy(&dc->event->base); |
Thierry Reding | ed7dae5 | 2014-12-16 16:03:13 +0100 | [diff] [blame] | 987 | drm_crtc_vblank_put(crtc); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 988 | dc->event = NULL; |
| 989 | } |
| 990 | |
| 991 | spin_unlock_irqrestore(&drm->event_lock, flags); |
| 992 | } |
| 993 | |
| 994 | static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
Dave Airlie | a5b6f74 | 2013-09-02 09:47:56 +1000 | [diff] [blame] | 995 | struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 996 | { |
Thierry Reding | ed7dae5 | 2014-12-16 16:03:13 +0100 | [diff] [blame] | 997 | unsigned int pipe = drm_crtc_index(crtc); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 998 | struct tegra_dc *dc = to_tegra_dc(crtc); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 999 | |
| 1000 | if (dc->event) |
| 1001 | return -EBUSY; |
| 1002 | |
| 1003 | if (event) { |
Thierry Reding | ed7dae5 | 2014-12-16 16:03:13 +0100 | [diff] [blame] | 1004 | event->pipe = pipe; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 1005 | dc->event = event; |
Thierry Reding | ed7dae5 | 2014-12-16 16:03:13 +0100 | [diff] [blame] | 1006 | drm_crtc_vblank_get(crtc); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 1007 | } |
| 1008 | |
Thierry Reding | 9d44189 | 2014-11-24 17:02:53 +0100 | [diff] [blame] | 1009 | if (crtc->primary->state) |
| 1010 | drm_atomic_set_fb_for_plane(crtc->primary->state, fb); |
| 1011 | |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 1012 | tegra_dc_set_base(dc, 0, 0, fb); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1013 | crtc->primary->fb = fb; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 1014 | |
| 1015 | return 0; |
| 1016 | } |
| 1017 | |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 1018 | static void tegra_dc_destroy(struct drm_crtc *crtc) |
| 1019 | { |
| 1020 | drm_crtc_cleanup(crtc); |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 1021 | } |
| 1022 | |
Thierry Reding | ca915b1 | 2014-12-08 16:14:45 +0100 | [diff] [blame] | 1023 | static void tegra_crtc_reset(struct drm_crtc *crtc) |
| 1024 | { |
| 1025 | struct tegra_dc_state *state; |
| 1026 | |
| 1027 | kfree(crtc->state); |
| 1028 | crtc->state = NULL; |
| 1029 | |
| 1030 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
| 1031 | if (state) |
| 1032 | crtc->state = &state->base; |
| 1033 | } |
| 1034 | |
| 1035 | static struct drm_crtc_state * |
| 1036 | tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) |
| 1037 | { |
| 1038 | struct tegra_dc_state *state = to_dc_state(crtc->state); |
| 1039 | struct tegra_dc_state *copy; |
| 1040 | |
| 1041 | copy = kmemdup(state, sizeof(*state), GFP_KERNEL); |
| 1042 | if (!copy) |
| 1043 | return NULL; |
| 1044 | |
| 1045 | copy->base.mode_changed = false; |
| 1046 | copy->base.planes_changed = false; |
| 1047 | copy->base.event = NULL; |
| 1048 | |
| 1049 | return ©->base; |
| 1050 | } |
| 1051 | |
| 1052 | static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, |
| 1053 | struct drm_crtc_state *state) |
| 1054 | { |
| 1055 | kfree(state); |
| 1056 | } |
| 1057 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1058 | static const struct drm_crtc_funcs tegra_crtc_funcs = { |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 1059 | .page_flip = tegra_dc_page_flip, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1060 | .set_config = drm_crtc_helper_set_config, |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 1061 | .destroy = tegra_dc_destroy, |
Thierry Reding | ca915b1 | 2014-12-08 16:14:45 +0100 | [diff] [blame] | 1062 | .reset = tegra_crtc_reset, |
| 1063 | .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, |
| 1064 | .atomic_destroy_state = tegra_crtc_atomic_destroy_state, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1065 | }; |
| 1066 | |
Thierry Reding | 86df256 | 2014-12-08 16:03:53 +0100 | [diff] [blame] | 1067 | static void tegra_dc_stop(struct tegra_dc *dc) |
| 1068 | { |
| 1069 | u32 value; |
| 1070 | |
| 1071 | /* stop the display controller */ |
| 1072 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); |
| 1073 | value &= ~DISP_CTRL_MODE_MASK; |
| 1074 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); |
| 1075 | |
| 1076 | tegra_dc_commit(dc); |
| 1077 | } |
| 1078 | |
| 1079 | static bool tegra_dc_idle(struct tegra_dc *dc) |
| 1080 | { |
| 1081 | u32 value; |
| 1082 | |
| 1083 | value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); |
| 1084 | |
| 1085 | return (value & DISP_CTRL_MODE_MASK) == 0; |
| 1086 | } |
| 1087 | |
| 1088 | static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) |
| 1089 | { |
| 1090 | timeout = jiffies + msecs_to_jiffies(timeout); |
| 1091 | |
| 1092 | while (time_before(jiffies, timeout)) { |
| 1093 | if (tegra_dc_idle(dc)) |
| 1094 | return 0; |
| 1095 | |
| 1096 | usleep_range(1000, 2000); |
| 1097 | } |
| 1098 | |
| 1099 | dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); |
| 1100 | return -ETIMEDOUT; |
| 1101 | } |
| 1102 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 1103 | static void tegra_crtc_disable(struct drm_crtc *crtc) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1104 | { |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 1105 | struct tegra_dc *dc = to_tegra_dc(crtc); |
Thierry Reding | 3b0e585 | 2014-12-16 18:30:16 +0100 | [diff] [blame] | 1106 | u32 value; |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 1107 | |
Thierry Reding | 86df256 | 2014-12-08 16:03:53 +0100 | [diff] [blame] | 1108 | if (!tegra_dc_idle(dc)) { |
| 1109 | tegra_dc_stop(dc); |
| 1110 | |
| 1111 | /* |
| 1112 | * Ignore the return value, there isn't anything useful to do |
| 1113 | * in case this fails. |
| 1114 | */ |
| 1115 | tegra_dc_wait_idle(dc, 100); |
| 1116 | } |
Thierry Reding | 36904ad | 2014-11-21 17:35:54 +0100 | [diff] [blame] | 1117 | |
Thierry Reding | 3b0e585 | 2014-12-16 18:30:16 +0100 | [diff] [blame] | 1118 | /* |
| 1119 | * This should really be part of the RGB encoder driver, but clearing |
| 1120 | * these bits has the side-effect of stopping the display controller. |
| 1121 | * When that happens no VBLANK interrupts will be raised. At the same |
| 1122 | * time the encoder is disabled before the display controller, so the |
| 1123 | * above code is always going to timeout waiting for the controller |
| 1124 | * to go idle. |
| 1125 | * |
| 1126 | * Given the close coupling between the RGB encoder and the display |
| 1127 | * controller doing it here is still kind of okay. None of the other |
| 1128 | * encoder drivers require these bits to be cleared. |
| 1129 | * |
| 1130 | * XXX: Perhaps given that the display controller is switched off at |
| 1131 | * this point anyway maybe clearing these bits isn't even useful for |
| 1132 | * the RGB encoder? |
| 1133 | */ |
| 1134 | if (dc->rgb) { |
| 1135 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); |
| 1136 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | |
| 1137 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); |
| 1138 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); |
| 1139 | } |
| 1140 | |
Thierry Reding | 8ff64c1 | 2014-10-08 14:48:51 +0200 | [diff] [blame] | 1141 | drm_crtc_vblank_off(crtc); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 1142 | tegra_dc_commit(dc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1143 | } |
| 1144 | |
| 1145 | static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, |
| 1146 | const struct drm_display_mode *mode, |
| 1147 | struct drm_display_mode *adjusted) |
| 1148 | { |
| 1149 | return true; |
| 1150 | } |
| 1151 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1152 | static int tegra_dc_set_timings(struct tegra_dc *dc, |
| 1153 | struct drm_display_mode *mode) |
| 1154 | { |
Thierry Reding | 0444c0f | 2014-04-16 09:22:38 +0200 | [diff] [blame] | 1155 | unsigned int h_ref_to_sync = 1; |
| 1156 | unsigned int v_ref_to_sync = 1; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1157 | unsigned long value; |
| 1158 | |
| 1159 | tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); |
| 1160 | |
| 1161 | value = (v_ref_to_sync << 16) | h_ref_to_sync; |
| 1162 | tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); |
| 1163 | |
| 1164 | value = ((mode->vsync_end - mode->vsync_start) << 16) | |
| 1165 | ((mode->hsync_end - mode->hsync_start) << 0); |
| 1166 | tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); |
| 1167 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1168 | value = ((mode->vtotal - mode->vsync_end) << 16) | |
| 1169 | ((mode->htotal - mode->hsync_end) << 0); |
Lucas Stach | 4049508 | 2012-12-19 21:38:52 +0000 | [diff] [blame] | 1170 | tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); |
| 1171 | |
| 1172 | value = ((mode->vsync_start - mode->vdisplay) << 16) | |
| 1173 | ((mode->hsync_start - mode->hdisplay) << 0); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1174 | tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); |
| 1175 | |
| 1176 | value = (mode->vdisplay << 16) | mode->hdisplay; |
| 1177 | tegra_dc_writel(dc, value, DC_DISP_ACTIVE); |
| 1178 | |
| 1179 | return 0; |
| 1180 | } |
| 1181 | |
Thierry Reding | c5a107d | 2014-12-02 15:15:06 +0100 | [diff] [blame] | 1182 | int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent, |
| 1183 | unsigned long pclk, unsigned int div) |
| 1184 | { |
| 1185 | u32 value; |
| 1186 | int err; |
| 1187 | |
| 1188 | err = clk_set_parent(dc->clk, parent); |
| 1189 | if (err < 0) { |
| 1190 | dev_err(dc->dev, "failed to set parent clock: %d\n", err); |
| 1191 | return err; |
| 1192 | } |
| 1193 | |
| 1194 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div); |
| 1195 | |
| 1196 | value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; |
| 1197 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); |
| 1198 | |
| 1199 | return 0; |
| 1200 | } |
| 1201 | |
Thierry Reding | ca915b1 | 2014-12-08 16:14:45 +0100 | [diff] [blame] | 1202 | int tegra_dc_state_setup_clock(struct tegra_dc *dc, |
| 1203 | struct drm_crtc_state *crtc_state, |
| 1204 | struct clk *clk, unsigned long pclk, |
| 1205 | unsigned int div) |
| 1206 | { |
| 1207 | struct tegra_dc_state *state = to_dc_state(crtc_state); |
| 1208 | |
| 1209 | state->clk = clk; |
| 1210 | state->pclk = pclk; |
| 1211 | state->div = div; |
| 1212 | |
| 1213 | return 0; |
| 1214 | } |
| 1215 | |
Thierry Reding | 76d59ed | 2014-12-19 15:09:16 +0100 | [diff] [blame^] | 1216 | static void tegra_dc_commit_state(struct tegra_dc *dc, |
| 1217 | struct tegra_dc_state *state) |
| 1218 | { |
| 1219 | u32 value; |
| 1220 | int err; |
| 1221 | |
| 1222 | err = clk_set_parent(dc->clk, state->clk); |
| 1223 | if (err < 0) |
| 1224 | dev_err(dc->dev, "failed to set parent clock: %d\n", err); |
| 1225 | |
| 1226 | /* |
| 1227 | * Outputs may not want to change the parent clock rate. This is only |
| 1228 | * relevant to Tegra20 where only a single display PLL is available. |
| 1229 | * Since that PLL would typically be used for HDMI, an internal LVDS |
| 1230 | * panel would need to be driven by some other clock such as PLL_P |
| 1231 | * which is shared with other peripherals. Changing the clock rate |
| 1232 | * should therefore be avoided. |
| 1233 | */ |
| 1234 | if (state->pclk > 0) { |
| 1235 | err = clk_set_rate(state->clk, state->pclk); |
| 1236 | if (err < 0) |
| 1237 | dev_err(dc->dev, |
| 1238 | "failed to set clock rate to %lu Hz\n", |
| 1239 | state->pclk); |
| 1240 | } |
| 1241 | |
| 1242 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), |
| 1243 | state->div); |
| 1244 | DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); |
| 1245 | |
| 1246 | value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; |
| 1247 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); |
| 1248 | } |
| 1249 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 1250 | static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1251 | { |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 1252 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
Thierry Reding | 76d59ed | 2014-12-19 15:09:16 +0100 | [diff] [blame^] | 1253 | struct tegra_dc_state *state = to_dc_state(crtc->state); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1254 | struct tegra_dc *dc = to_tegra_dc(crtc); |
Thierry Reding | dbb3f2f | 2014-03-26 12:32:14 +0100 | [diff] [blame] | 1255 | u32 value; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1256 | |
Thierry Reding | 76d59ed | 2014-12-19 15:09:16 +0100 | [diff] [blame^] | 1257 | tegra_dc_commit_state(dc, state); |
| 1258 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1259 | /* program display mode */ |
| 1260 | tegra_dc_set_timings(dc, mode); |
| 1261 | |
Thierry Reding | 42d0659 | 2014-12-08 15:45:39 +0100 | [diff] [blame] | 1262 | if (dc->soc->supports_border_color) |
| 1263 | tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); |
| 1264 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1265 | /* interlacing isn't supported yet, so disable it */ |
| 1266 | if (dc->soc->supports_interlacing) { |
| 1267 | value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); |
| 1268 | value &= ~INTERLACE_ENABLE; |
| 1269 | tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); |
| 1270 | } |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 1271 | } |
| 1272 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1273 | static void tegra_crtc_prepare(struct drm_crtc *crtc) |
| 1274 | { |
| 1275 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 1276 | unsigned int syncpt; |
| 1277 | unsigned long value; |
| 1278 | |
Thierry Reding | 8ff64c1 | 2014-10-08 14:48:51 +0200 | [diff] [blame] | 1279 | drm_crtc_vblank_off(crtc); |
| 1280 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1281 | if (dc->pipe) |
| 1282 | syncpt = SYNCPT_VBLANK1; |
| 1283 | else |
| 1284 | syncpt = SYNCPT_VBLANK0; |
| 1285 | |
| 1286 | /* initialize display controller */ |
| 1287 | tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); |
| 1288 | tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); |
| 1289 | |
| 1290 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; |
| 1291 | tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); |
| 1292 | |
| 1293 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | |
| 1294 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; |
| 1295 | tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); |
| 1296 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1297 | /* initialize timer */ |
| 1298 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | |
| 1299 | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); |
| 1300 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); |
| 1301 | |
| 1302 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | |
| 1303 | WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); |
| 1304 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); |
| 1305 | |
| 1306 | value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1307 | tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 1308 | |
| 1309 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; |
| 1310 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1311 | } |
| 1312 | |
| 1313 | static void tegra_crtc_commit(struct drm_crtc *crtc) |
| 1314 | { |
| 1315 | struct tegra_dc *dc = to_tegra_dc(crtc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1316 | |
Thierry Reding | 8ff64c1 | 2014-10-08 14:48:51 +0200 | [diff] [blame] | 1317 | drm_crtc_vblank_on(crtc); |
Thierry Reding | 205d48e | 2014-10-21 13:41:46 +0200 | [diff] [blame] | 1318 | tegra_dc_commit(dc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1319 | } |
| 1320 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 1321 | static int tegra_crtc_atomic_check(struct drm_crtc *crtc, |
| 1322 | struct drm_crtc_state *state) |
| 1323 | { |
| 1324 | return 0; |
| 1325 | } |
| 1326 | |
| 1327 | static void tegra_crtc_atomic_begin(struct drm_crtc *crtc) |
| 1328 | { |
| 1329 | } |
| 1330 | |
| 1331 | static void tegra_crtc_atomic_flush(struct drm_crtc *crtc) |
| 1332 | { |
| 1333 | } |
| 1334 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1335 | static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 1336 | .disable = tegra_crtc_disable, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1337 | .mode_fixup = tegra_crtc_mode_fixup, |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 1338 | .mode_set = drm_helper_crtc_mode_set, |
| 1339 | .mode_set_nofb = tegra_crtc_mode_set_nofb, |
| 1340 | .mode_set_base = drm_helper_crtc_mode_set_base, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1341 | .prepare = tegra_crtc_prepare, |
| 1342 | .commit = tegra_crtc_commit, |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 1343 | .atomic_check = tegra_crtc_atomic_check, |
| 1344 | .atomic_begin = tegra_crtc_atomic_begin, |
| 1345 | .atomic_flush = tegra_crtc_atomic_flush, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1346 | }; |
| 1347 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 1348 | static irqreturn_t tegra_dc_irq(int irq, void *data) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1349 | { |
| 1350 | struct tegra_dc *dc = data; |
| 1351 | unsigned long status; |
| 1352 | |
| 1353 | status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); |
| 1354 | tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); |
| 1355 | |
| 1356 | if (status & FRAME_END_INT) { |
| 1357 | /* |
| 1358 | dev_dbg(dc->dev, "%s(): frame end\n", __func__); |
| 1359 | */ |
| 1360 | } |
| 1361 | |
| 1362 | if (status & VBLANK_INT) { |
| 1363 | /* |
| 1364 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); |
| 1365 | */ |
Thierry Reding | ed7dae5 | 2014-12-16 16:03:13 +0100 | [diff] [blame] | 1366 | drm_crtc_handle_vblank(&dc->base); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 1367 | tegra_dc_finish_page_flip(dc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1368 | } |
| 1369 | |
| 1370 | if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { |
| 1371 | /* |
| 1372 | dev_dbg(dc->dev, "%s(): underflow\n", __func__); |
| 1373 | */ |
| 1374 | } |
| 1375 | |
| 1376 | return IRQ_HANDLED; |
| 1377 | } |
| 1378 | |
| 1379 | static int tegra_dc_show_regs(struct seq_file *s, void *data) |
| 1380 | { |
| 1381 | struct drm_info_node *node = s->private; |
| 1382 | struct tegra_dc *dc = node->info_ent->data; |
| 1383 | |
| 1384 | #define DUMP_REG(name) \ |
Thierry Reding | 03a6056 | 2014-10-21 13:48:48 +0200 | [diff] [blame] | 1385 | seq_printf(s, "%-40s %#05x %08x\n", #name, name, \ |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1386 | tegra_dc_readl(dc, name)) |
| 1387 | |
| 1388 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); |
| 1389 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); |
| 1390 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); |
| 1391 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); |
| 1392 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); |
| 1393 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); |
| 1394 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); |
| 1395 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); |
| 1396 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); |
| 1397 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); |
| 1398 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); |
| 1399 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); |
| 1400 | DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); |
| 1401 | DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); |
| 1402 | DUMP_REG(DC_CMD_DISPLAY_COMMAND); |
| 1403 | DUMP_REG(DC_CMD_SIGNAL_RAISE); |
| 1404 | DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); |
| 1405 | DUMP_REG(DC_CMD_INT_STATUS); |
| 1406 | DUMP_REG(DC_CMD_INT_MASK); |
| 1407 | DUMP_REG(DC_CMD_INT_ENABLE); |
| 1408 | DUMP_REG(DC_CMD_INT_TYPE); |
| 1409 | DUMP_REG(DC_CMD_INT_POLARITY); |
| 1410 | DUMP_REG(DC_CMD_SIGNAL_RAISE1); |
| 1411 | DUMP_REG(DC_CMD_SIGNAL_RAISE2); |
| 1412 | DUMP_REG(DC_CMD_SIGNAL_RAISE3); |
| 1413 | DUMP_REG(DC_CMD_STATE_ACCESS); |
| 1414 | DUMP_REG(DC_CMD_STATE_CONTROL); |
| 1415 | DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); |
| 1416 | DUMP_REG(DC_CMD_REG_ACT_CONTROL); |
| 1417 | DUMP_REG(DC_COM_CRC_CONTROL); |
| 1418 | DUMP_REG(DC_COM_CRC_CHECKSUM); |
| 1419 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); |
| 1420 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); |
| 1421 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); |
| 1422 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); |
| 1423 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); |
| 1424 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); |
| 1425 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); |
| 1426 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); |
| 1427 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); |
| 1428 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); |
| 1429 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); |
| 1430 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); |
| 1431 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); |
| 1432 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); |
| 1433 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); |
| 1434 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); |
| 1435 | DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); |
| 1436 | DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); |
| 1437 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); |
| 1438 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); |
| 1439 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); |
| 1440 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); |
| 1441 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); |
| 1442 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); |
| 1443 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); |
| 1444 | DUMP_REG(DC_COM_PIN_MISC_CONTROL); |
| 1445 | DUMP_REG(DC_COM_PIN_PM0_CONTROL); |
| 1446 | DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); |
| 1447 | DUMP_REG(DC_COM_PIN_PM1_CONTROL); |
| 1448 | DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); |
| 1449 | DUMP_REG(DC_COM_SPI_CONTROL); |
| 1450 | DUMP_REG(DC_COM_SPI_START_BYTE); |
| 1451 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); |
| 1452 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); |
| 1453 | DUMP_REG(DC_COM_HSPI_CS_DC); |
| 1454 | DUMP_REG(DC_COM_SCRATCH_REGISTER_A); |
| 1455 | DUMP_REG(DC_COM_SCRATCH_REGISTER_B); |
| 1456 | DUMP_REG(DC_COM_GPIO_CTRL); |
| 1457 | DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); |
| 1458 | DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); |
| 1459 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); |
| 1460 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); |
| 1461 | DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); |
| 1462 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); |
| 1463 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); |
| 1464 | DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); |
| 1465 | DUMP_REG(DC_DISP_REF_TO_SYNC); |
| 1466 | DUMP_REG(DC_DISP_SYNC_WIDTH); |
| 1467 | DUMP_REG(DC_DISP_BACK_PORCH); |
| 1468 | DUMP_REG(DC_DISP_ACTIVE); |
| 1469 | DUMP_REG(DC_DISP_FRONT_PORCH); |
| 1470 | DUMP_REG(DC_DISP_H_PULSE0_CONTROL); |
| 1471 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); |
| 1472 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); |
| 1473 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); |
| 1474 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); |
| 1475 | DUMP_REG(DC_DISP_H_PULSE1_CONTROL); |
| 1476 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); |
| 1477 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); |
| 1478 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); |
| 1479 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); |
| 1480 | DUMP_REG(DC_DISP_H_PULSE2_CONTROL); |
| 1481 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); |
| 1482 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); |
| 1483 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); |
| 1484 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); |
| 1485 | DUMP_REG(DC_DISP_V_PULSE0_CONTROL); |
| 1486 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); |
| 1487 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); |
| 1488 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); |
| 1489 | DUMP_REG(DC_DISP_V_PULSE1_CONTROL); |
| 1490 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); |
| 1491 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); |
| 1492 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); |
| 1493 | DUMP_REG(DC_DISP_V_PULSE2_CONTROL); |
| 1494 | DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); |
| 1495 | DUMP_REG(DC_DISP_V_PULSE3_CONTROL); |
| 1496 | DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); |
| 1497 | DUMP_REG(DC_DISP_M0_CONTROL); |
| 1498 | DUMP_REG(DC_DISP_M1_CONTROL); |
| 1499 | DUMP_REG(DC_DISP_DI_CONTROL); |
| 1500 | DUMP_REG(DC_DISP_PP_CONTROL); |
| 1501 | DUMP_REG(DC_DISP_PP_SELECT_A); |
| 1502 | DUMP_REG(DC_DISP_PP_SELECT_B); |
| 1503 | DUMP_REG(DC_DISP_PP_SELECT_C); |
| 1504 | DUMP_REG(DC_DISP_PP_SELECT_D); |
| 1505 | DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); |
| 1506 | DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); |
| 1507 | DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); |
| 1508 | DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); |
| 1509 | DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); |
| 1510 | DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); |
| 1511 | DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); |
| 1512 | DUMP_REG(DC_DISP_BORDER_COLOR); |
| 1513 | DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); |
| 1514 | DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); |
| 1515 | DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); |
| 1516 | DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); |
| 1517 | DUMP_REG(DC_DISP_CURSOR_FOREGROUND); |
| 1518 | DUMP_REG(DC_DISP_CURSOR_BACKGROUND); |
| 1519 | DUMP_REG(DC_DISP_CURSOR_START_ADDR); |
| 1520 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); |
| 1521 | DUMP_REG(DC_DISP_CURSOR_POSITION); |
| 1522 | DUMP_REG(DC_DISP_CURSOR_POSITION_NS); |
| 1523 | DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); |
| 1524 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); |
| 1525 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); |
| 1526 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); |
| 1527 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); |
| 1528 | DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); |
| 1529 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); |
| 1530 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); |
| 1531 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); |
| 1532 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); |
| 1533 | DUMP_REG(DC_DISP_DAC_CRT_CTRL); |
| 1534 | DUMP_REG(DC_DISP_DISP_MISC_CONTROL); |
| 1535 | DUMP_REG(DC_DISP_SD_CONTROL); |
| 1536 | DUMP_REG(DC_DISP_SD_CSC_COEFF); |
| 1537 | DUMP_REG(DC_DISP_SD_LUT(0)); |
| 1538 | DUMP_REG(DC_DISP_SD_LUT(1)); |
| 1539 | DUMP_REG(DC_DISP_SD_LUT(2)); |
| 1540 | DUMP_REG(DC_DISP_SD_LUT(3)); |
| 1541 | DUMP_REG(DC_DISP_SD_LUT(4)); |
| 1542 | DUMP_REG(DC_DISP_SD_LUT(5)); |
| 1543 | DUMP_REG(DC_DISP_SD_LUT(6)); |
| 1544 | DUMP_REG(DC_DISP_SD_LUT(7)); |
| 1545 | DUMP_REG(DC_DISP_SD_LUT(8)); |
| 1546 | DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); |
| 1547 | DUMP_REG(DC_DISP_DC_PIXEL_COUNT); |
| 1548 | DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); |
| 1549 | DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); |
| 1550 | DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); |
| 1551 | DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); |
| 1552 | DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); |
| 1553 | DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); |
| 1554 | DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); |
| 1555 | DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); |
| 1556 | DUMP_REG(DC_DISP_SD_BL_TF(0)); |
| 1557 | DUMP_REG(DC_DISP_SD_BL_TF(1)); |
| 1558 | DUMP_REG(DC_DISP_SD_BL_TF(2)); |
| 1559 | DUMP_REG(DC_DISP_SD_BL_TF(3)); |
| 1560 | DUMP_REG(DC_DISP_SD_BL_CONTROL); |
| 1561 | DUMP_REG(DC_DISP_SD_HW_K_VALUES); |
| 1562 | DUMP_REG(DC_DISP_SD_MAN_K_VALUES); |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 1563 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); |
| 1564 | DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1565 | DUMP_REG(DC_WIN_WIN_OPTIONS); |
| 1566 | DUMP_REG(DC_WIN_BYTE_SWAP); |
| 1567 | DUMP_REG(DC_WIN_BUFFER_CONTROL); |
| 1568 | DUMP_REG(DC_WIN_COLOR_DEPTH); |
| 1569 | DUMP_REG(DC_WIN_POSITION); |
| 1570 | DUMP_REG(DC_WIN_SIZE); |
| 1571 | DUMP_REG(DC_WIN_PRESCALED_SIZE); |
| 1572 | DUMP_REG(DC_WIN_H_INITIAL_DDA); |
| 1573 | DUMP_REG(DC_WIN_V_INITIAL_DDA); |
| 1574 | DUMP_REG(DC_WIN_DDA_INC); |
| 1575 | DUMP_REG(DC_WIN_LINE_STRIDE); |
| 1576 | DUMP_REG(DC_WIN_BUF_STRIDE); |
| 1577 | DUMP_REG(DC_WIN_UV_BUF_STRIDE); |
| 1578 | DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); |
| 1579 | DUMP_REG(DC_WIN_DV_CONTROL); |
| 1580 | DUMP_REG(DC_WIN_BLEND_NOKEY); |
| 1581 | DUMP_REG(DC_WIN_BLEND_1WIN); |
| 1582 | DUMP_REG(DC_WIN_BLEND_2WIN_X); |
| 1583 | DUMP_REG(DC_WIN_BLEND_2WIN_Y); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 1584 | DUMP_REG(DC_WIN_BLEND_3WIN_XY); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1585 | DUMP_REG(DC_WIN_HP_FETCH_CONTROL); |
| 1586 | DUMP_REG(DC_WINBUF_START_ADDR); |
| 1587 | DUMP_REG(DC_WINBUF_START_ADDR_NS); |
| 1588 | DUMP_REG(DC_WINBUF_START_ADDR_U); |
| 1589 | DUMP_REG(DC_WINBUF_START_ADDR_U_NS); |
| 1590 | DUMP_REG(DC_WINBUF_START_ADDR_V); |
| 1591 | DUMP_REG(DC_WINBUF_START_ADDR_V_NS); |
| 1592 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); |
| 1593 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); |
| 1594 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); |
| 1595 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); |
| 1596 | DUMP_REG(DC_WINBUF_UFLOW_STATUS); |
| 1597 | DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); |
| 1598 | DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); |
| 1599 | DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); |
| 1600 | |
| 1601 | #undef DUMP_REG |
| 1602 | |
| 1603 | return 0; |
| 1604 | } |
| 1605 | |
| 1606 | static struct drm_info_list debugfs_files[] = { |
| 1607 | { "regs", tegra_dc_show_regs, 0, NULL }, |
| 1608 | }; |
| 1609 | |
| 1610 | static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) |
| 1611 | { |
| 1612 | unsigned int i; |
| 1613 | char *name; |
| 1614 | int err; |
| 1615 | |
| 1616 | name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); |
| 1617 | dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); |
| 1618 | kfree(name); |
| 1619 | |
| 1620 | if (!dc->debugfs) |
| 1621 | return -ENOMEM; |
| 1622 | |
| 1623 | dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), |
| 1624 | GFP_KERNEL); |
| 1625 | if (!dc->debugfs_files) { |
| 1626 | err = -ENOMEM; |
| 1627 | goto remove; |
| 1628 | } |
| 1629 | |
| 1630 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) |
| 1631 | dc->debugfs_files[i].data = dc; |
| 1632 | |
| 1633 | err = drm_debugfs_create_files(dc->debugfs_files, |
| 1634 | ARRAY_SIZE(debugfs_files), |
| 1635 | dc->debugfs, minor); |
| 1636 | if (err < 0) |
| 1637 | goto free; |
| 1638 | |
| 1639 | dc->minor = minor; |
| 1640 | |
| 1641 | return 0; |
| 1642 | |
| 1643 | free: |
| 1644 | kfree(dc->debugfs_files); |
| 1645 | dc->debugfs_files = NULL; |
| 1646 | remove: |
| 1647 | debugfs_remove(dc->debugfs); |
| 1648 | dc->debugfs = NULL; |
| 1649 | |
| 1650 | return err; |
| 1651 | } |
| 1652 | |
| 1653 | static int tegra_dc_debugfs_exit(struct tegra_dc *dc) |
| 1654 | { |
| 1655 | drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), |
| 1656 | dc->minor); |
| 1657 | dc->minor = NULL; |
| 1658 | |
| 1659 | kfree(dc->debugfs_files); |
| 1660 | dc->debugfs_files = NULL; |
| 1661 | |
| 1662 | debugfs_remove(dc->debugfs); |
| 1663 | dc->debugfs = NULL; |
| 1664 | |
| 1665 | return 0; |
| 1666 | } |
| 1667 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 1668 | static int tegra_dc_init(struct host1x_client *client) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1669 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1670 | struct drm_device *drm = dev_get_drvdata(client->parent); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1671 | struct tegra_dc *dc = host1x_client_to_dc(client); |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1672 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 1673 | struct drm_plane *primary = NULL; |
| 1674 | struct drm_plane *cursor = NULL; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1675 | int err; |
| 1676 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 1677 | if (tegra->domain) { |
| 1678 | err = iommu_attach_device(tegra->domain, dc->dev); |
| 1679 | if (err < 0) { |
| 1680 | dev_err(dc->dev, "failed to attach to domain: %d\n", |
| 1681 | err); |
| 1682 | return err; |
| 1683 | } |
| 1684 | |
| 1685 | dc->domain = tegra->domain; |
| 1686 | } |
| 1687 | |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 1688 | primary = tegra_dc_primary_plane_create(drm, dc); |
| 1689 | if (IS_ERR(primary)) { |
| 1690 | err = PTR_ERR(primary); |
| 1691 | goto cleanup; |
| 1692 | } |
| 1693 | |
| 1694 | if (dc->soc->supports_cursor) { |
| 1695 | cursor = tegra_dc_cursor_plane_create(drm, dc); |
| 1696 | if (IS_ERR(cursor)) { |
| 1697 | err = PTR_ERR(cursor); |
| 1698 | goto cleanup; |
| 1699 | } |
| 1700 | } |
| 1701 | |
| 1702 | err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, |
| 1703 | &tegra_crtc_funcs); |
| 1704 | if (err < 0) |
| 1705 | goto cleanup; |
| 1706 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1707 | drm_mode_crtc_set_gamma_size(&dc->base, 256); |
| 1708 | drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); |
| 1709 | |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1710 | /* |
| 1711 | * Keep track of the minimum pitch alignment across all display |
| 1712 | * controllers. |
| 1713 | */ |
| 1714 | if (dc->soc->pitch_align > tegra->pitch_align) |
| 1715 | tegra->pitch_align = dc->soc->pitch_align; |
| 1716 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1717 | err = tegra_dc_rgb_init(drm, dc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1718 | if (err < 0 && err != -ENODEV) { |
| 1719 | dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 1720 | goto cleanup; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1721 | } |
| 1722 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1723 | err = tegra_dc_add_planes(drm, dc); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 1724 | if (err < 0) |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 1725 | goto cleanup; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 1726 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1727 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1728 | err = tegra_dc_debugfs_init(dc, drm->primary); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1729 | if (err < 0) |
| 1730 | dev_err(dc->dev, "debugfs setup failed: %d\n", err); |
| 1731 | } |
| 1732 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 1733 | err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1734 | dev_name(dc->dev), dc); |
| 1735 | if (err < 0) { |
| 1736 | dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, |
| 1737 | err); |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 1738 | goto cleanup; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1739 | } |
| 1740 | |
| 1741 | return 0; |
Thierry Reding | c767930 | 2014-10-21 13:51:53 +0200 | [diff] [blame] | 1742 | |
| 1743 | cleanup: |
| 1744 | if (cursor) |
| 1745 | drm_plane_cleanup(cursor); |
| 1746 | |
| 1747 | if (primary) |
| 1748 | drm_plane_cleanup(primary); |
| 1749 | |
| 1750 | if (tegra->domain) { |
| 1751 | iommu_detach_device(tegra->domain, dc->dev); |
| 1752 | dc->domain = NULL; |
| 1753 | } |
| 1754 | |
| 1755 | return err; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1756 | } |
| 1757 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 1758 | static int tegra_dc_exit(struct host1x_client *client) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1759 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1760 | struct tegra_dc *dc = host1x_client_to_dc(client); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1761 | int err; |
| 1762 | |
| 1763 | devm_free_irq(dc->dev, dc->irq, dc); |
| 1764 | |
| 1765 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
| 1766 | err = tegra_dc_debugfs_exit(dc); |
| 1767 | if (err < 0) |
| 1768 | dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); |
| 1769 | } |
| 1770 | |
| 1771 | err = tegra_dc_rgb_exit(dc); |
| 1772 | if (err) { |
| 1773 | dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); |
| 1774 | return err; |
| 1775 | } |
| 1776 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 1777 | if (dc->domain) { |
| 1778 | iommu_detach_device(dc->domain, dc->dev); |
| 1779 | dc->domain = NULL; |
| 1780 | } |
| 1781 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1782 | return 0; |
| 1783 | } |
| 1784 | |
| 1785 | static const struct host1x_client_ops dc_client_ops = { |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 1786 | .init = tegra_dc_init, |
| 1787 | .exit = tegra_dc_exit, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1788 | }; |
| 1789 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1790 | static const struct tegra_dc_soc_info tegra20_dc_soc_info = { |
Thierry Reding | 42d0659 | 2014-12-08 15:45:39 +0100 | [diff] [blame] | 1791 | .supports_border_color = true, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1792 | .supports_interlacing = false, |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 1793 | .supports_cursor = false, |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 1794 | .supports_block_linear = false, |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1795 | .pitch_align = 8, |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1796 | .has_powergate = false, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1797 | }; |
| 1798 | |
| 1799 | static const struct tegra_dc_soc_info tegra30_dc_soc_info = { |
Thierry Reding | 42d0659 | 2014-12-08 15:45:39 +0100 | [diff] [blame] | 1800 | .supports_border_color = true, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1801 | .supports_interlacing = false, |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 1802 | .supports_cursor = false, |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 1803 | .supports_block_linear = false, |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1804 | .pitch_align = 8, |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1805 | .has_powergate = false, |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1806 | }; |
| 1807 | |
| 1808 | static const struct tegra_dc_soc_info tegra114_dc_soc_info = { |
Thierry Reding | 42d0659 | 2014-12-08 15:45:39 +0100 | [diff] [blame] | 1809 | .supports_border_color = true, |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1810 | .supports_interlacing = false, |
| 1811 | .supports_cursor = false, |
| 1812 | .supports_block_linear = false, |
| 1813 | .pitch_align = 64, |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1814 | .has_powergate = true, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1815 | }; |
| 1816 | |
| 1817 | static const struct tegra_dc_soc_info tegra124_dc_soc_info = { |
Thierry Reding | 42d0659 | 2014-12-08 15:45:39 +0100 | [diff] [blame] | 1818 | .supports_border_color = false, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1819 | .supports_interlacing = true, |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 1820 | .supports_cursor = true, |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 1821 | .supports_block_linear = true, |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1822 | .pitch_align = 64, |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1823 | .has_powergate = true, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1824 | }; |
| 1825 | |
| 1826 | static const struct of_device_id tegra_dc_of_match[] = { |
| 1827 | { |
| 1828 | .compatible = "nvidia,tegra124-dc", |
| 1829 | .data = &tegra124_dc_soc_info, |
| 1830 | }, { |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1831 | .compatible = "nvidia,tegra114-dc", |
| 1832 | .data = &tegra114_dc_soc_info, |
| 1833 | }, { |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1834 | .compatible = "nvidia,tegra30-dc", |
| 1835 | .data = &tegra30_dc_soc_info, |
| 1836 | }, { |
| 1837 | .compatible = "nvidia,tegra20-dc", |
| 1838 | .data = &tegra20_dc_soc_info, |
| 1839 | }, { |
| 1840 | /* sentinel */ |
| 1841 | } |
| 1842 | }; |
Stephen Warren | ef70728 | 2014-06-18 16:21:55 -0600 | [diff] [blame] | 1843 | MODULE_DEVICE_TABLE(of, tegra_dc_of_match); |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1844 | |
Thierry Reding | 13411dd | 2014-01-09 17:08:36 +0100 | [diff] [blame] | 1845 | static int tegra_dc_parse_dt(struct tegra_dc *dc) |
| 1846 | { |
| 1847 | struct device_node *np; |
| 1848 | u32 value = 0; |
| 1849 | int err; |
| 1850 | |
| 1851 | err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); |
| 1852 | if (err < 0) { |
| 1853 | dev_err(dc->dev, "missing \"nvidia,head\" property\n"); |
| 1854 | |
| 1855 | /* |
| 1856 | * If the nvidia,head property isn't present, try to find the |
| 1857 | * correct head number by looking up the position of this |
| 1858 | * display controller's node within the device tree. Assuming |
| 1859 | * that the nodes are ordered properly in the DTS file and |
| 1860 | * that the translation into a flattened device tree blob |
| 1861 | * preserves that ordering this will actually yield the right |
| 1862 | * head number. |
| 1863 | * |
| 1864 | * If those assumptions don't hold, this will still work for |
| 1865 | * cases where only a single display controller is used. |
| 1866 | */ |
| 1867 | for_each_matching_node(np, tegra_dc_of_match) { |
| 1868 | if (np == dc->dev->of_node) |
| 1869 | break; |
| 1870 | |
| 1871 | value++; |
| 1872 | } |
| 1873 | } |
| 1874 | |
| 1875 | dc->pipe = value; |
| 1876 | |
| 1877 | return 0; |
| 1878 | } |
| 1879 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1880 | static int tegra_dc_probe(struct platform_device *pdev) |
| 1881 | { |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1882 | const struct of_device_id *id; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1883 | struct resource *regs; |
| 1884 | struct tegra_dc *dc; |
| 1885 | int err; |
| 1886 | |
| 1887 | dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); |
| 1888 | if (!dc) |
| 1889 | return -ENOMEM; |
| 1890 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1891 | id = of_match_node(tegra_dc_of_match, pdev->dev.of_node); |
| 1892 | if (!id) |
| 1893 | return -ENODEV; |
| 1894 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 1895 | spin_lock_init(&dc->lock); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1896 | INIT_LIST_HEAD(&dc->list); |
| 1897 | dc->dev = &pdev->dev; |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1898 | dc->soc = id->data; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1899 | |
Thierry Reding | 13411dd | 2014-01-09 17:08:36 +0100 | [diff] [blame] | 1900 | err = tegra_dc_parse_dt(dc); |
| 1901 | if (err < 0) |
| 1902 | return err; |
| 1903 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1904 | dc->clk = devm_clk_get(&pdev->dev, NULL); |
| 1905 | if (IS_ERR(dc->clk)) { |
| 1906 | dev_err(&pdev->dev, "failed to get clock\n"); |
| 1907 | return PTR_ERR(dc->clk); |
| 1908 | } |
| 1909 | |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 1910 | dc->rst = devm_reset_control_get(&pdev->dev, "dc"); |
| 1911 | if (IS_ERR(dc->rst)) { |
| 1912 | dev_err(&pdev->dev, "failed to get reset\n"); |
| 1913 | return PTR_ERR(dc->rst); |
| 1914 | } |
| 1915 | |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1916 | if (dc->soc->has_powergate) { |
| 1917 | if (dc->pipe == 0) |
| 1918 | dc->powergate = TEGRA_POWERGATE_DIS; |
| 1919 | else |
| 1920 | dc->powergate = TEGRA_POWERGATE_DISB; |
| 1921 | |
| 1922 | err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, |
| 1923 | dc->rst); |
| 1924 | if (err < 0) { |
| 1925 | dev_err(&pdev->dev, "failed to power partition: %d\n", |
| 1926 | err); |
| 1927 | return err; |
| 1928 | } |
| 1929 | } else { |
| 1930 | err = clk_prepare_enable(dc->clk); |
| 1931 | if (err < 0) { |
| 1932 | dev_err(&pdev->dev, "failed to enable clock: %d\n", |
| 1933 | err); |
| 1934 | return err; |
| 1935 | } |
| 1936 | |
| 1937 | err = reset_control_deassert(dc->rst); |
| 1938 | if (err < 0) { |
| 1939 | dev_err(&pdev->dev, "failed to deassert reset: %d\n", |
| 1940 | err); |
| 1941 | return err; |
| 1942 | } |
| 1943 | } |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1944 | |
| 1945 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Thierry Reding | d4ed602 | 2013-01-21 11:09:02 +0100 | [diff] [blame] | 1946 | dc->regs = devm_ioremap_resource(&pdev->dev, regs); |
| 1947 | if (IS_ERR(dc->regs)) |
| 1948 | return PTR_ERR(dc->regs); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1949 | |
| 1950 | dc->irq = platform_get_irq(pdev, 0); |
| 1951 | if (dc->irq < 0) { |
| 1952 | dev_err(&pdev->dev, "failed to get IRQ\n"); |
| 1953 | return -ENXIO; |
| 1954 | } |
| 1955 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1956 | INIT_LIST_HEAD(&dc->client.list); |
| 1957 | dc->client.ops = &dc_client_ops; |
| 1958 | dc->client.dev = &pdev->dev; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1959 | |
| 1960 | err = tegra_dc_rgb_probe(dc); |
| 1961 | if (err < 0 && err != -ENODEV) { |
| 1962 | dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); |
| 1963 | return err; |
| 1964 | } |
| 1965 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1966 | err = host1x_client_register(&dc->client); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1967 | if (err < 0) { |
| 1968 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", |
| 1969 | err); |
| 1970 | return err; |
| 1971 | } |
| 1972 | |
| 1973 | platform_set_drvdata(pdev, dc); |
| 1974 | |
| 1975 | return 0; |
| 1976 | } |
| 1977 | |
| 1978 | static int tegra_dc_remove(struct platform_device *pdev) |
| 1979 | { |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1980 | struct tegra_dc *dc = platform_get_drvdata(pdev); |
| 1981 | int err; |
| 1982 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1983 | err = host1x_client_unregister(&dc->client); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1984 | if (err < 0) { |
| 1985 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", |
| 1986 | err); |
| 1987 | return err; |
| 1988 | } |
| 1989 | |
Thierry Reding | 59d29c0 | 2013-10-14 14:26:42 +0200 | [diff] [blame] | 1990 | err = tegra_dc_rgb_remove(dc); |
| 1991 | if (err < 0) { |
| 1992 | dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); |
| 1993 | return err; |
| 1994 | } |
| 1995 | |
Thierry Reding | 5482d75 | 2014-07-11 08:39:03 +0200 | [diff] [blame] | 1996 | reset_control_assert(dc->rst); |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1997 | |
| 1998 | if (dc->soc->has_powergate) |
| 1999 | tegra_powergate_power_off(dc->powergate); |
| 2000 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 2001 | clk_disable_unprepare(dc->clk); |
| 2002 | |
| 2003 | return 0; |
| 2004 | } |
| 2005 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 2006 | struct platform_driver tegra_dc_driver = { |
| 2007 | .driver = { |
| 2008 | .name = "tegra-dc", |
| 2009 | .owner = THIS_MODULE, |
| 2010 | .of_match_table = tegra_dc_of_match, |
| 2011 | }, |
| 2012 | .probe = tegra_dc_probe, |
| 2013 | .remove = tegra_dc_remove, |
| 2014 | }; |