blob: 191e76da23f72d277a9fb709604ed2c1ffd190dd [file] [log] [blame]
Banajit Goswamib016de92017-02-15 21:02:30 -08001/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Kyle Yan679cbee2016-07-27 16:55:20 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070014 tlmm: pinctrl@03400000 {
Kyle Yan6a20fae2017-02-14 13:34:41 -080015 compatible = "qcom,sdm845-pinctrl";
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070016 reg = <0x03400000 0xc00000>;
Kyle Yan679cbee2016-07-27 16:55:20 -070017 interrupts = <0 208 0>;
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
Archana Sathyakumar00a36ab2017-03-03 14:38:26 -070022 interrupt-parent = <&pdc>;
Banajit Goswamib016de92017-02-15 21:02:30 -080023
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070024 ufs_dev_reset_assert: ufs_dev_reset_assert {
25 config {
26 pins = "ufs_reset";
27 bias-pull-down; /* default: pull down */
28 /*
29 * UFS_RESET driver strengths are having
30 * different values/steps compared to typical
31 * GPIO drive strengths.
32 *
33 * Following table clarifies:
34 *
35 * HDRV value | UFS_RESET | Typical GPIO
36 * (dec) | (mA) | (mA)
37 * 0 | 0.8 | 2
38 * 1 | 1.55 | 4
39 * 2 | 2.35 | 6
40 * 3 | 3.1 | 8
41 * 4 | 3.9 | 10
42 * 5 | 4.65 | 12
43 * 6 | 5.4 | 14
44 * 7 | 6.15 | 16
45 *
46 * POR value for UFS_RESET HDRV is 3 which means
47 * 3.1mA and we want to use that. Hence just
48 * specify 8mA to "drive-strength" binding and
49 * that should result into writing 3 to HDRV
50 * field.
51 */
52 drive-strength = <8>; /* default: 3.1 mA */
53 output-low; /* active low reset */
54 };
55 };
56
57 ufs_dev_reset_deassert: ufs_dev_reset_deassert {
58 config {
59 pins = "ufs_reset";
60 bias-pull-down; /* default: pull down */
61 /*
62 * default: 3.1 mA
63 * check comments under ufs_dev_reset_assert
64 */
65 drive-strength = <8>;
66 output-high; /* active low reset */
67 };
68 };
69
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070070 flash_led3_front {
71 flash_led3_front_en: flash_led3_front_en {
72 mux {
73 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070074 function = "gpio";
75 };
76
77 config {
78 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070079 drive_strength = <2>;
80 output-high;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070081 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070082 };
83 };
84
85 flash_led3_front_dis: flash_led3_front_dis {
86 mux {
87 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070088 function = "gpio";
89 };
90
91 config {
92 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070093 drive_strength = <2>;
94 output-low;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070095 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070096 };
97 };
98 };
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070099
Jilai Wangf4d78a22017-11-10 17:05:47 -0500100 flash_led3_iris {
101 flash_led3_iris_en: flash_led3_iris_en {
102 mux {
103 pins = "gpio23";
104 function = "gpio";
105 };
106
107 config {
108 pins = "gpio23";
109 drive_strength = <2>;
110 output-high;
111 bias-disable;
112 };
113 };
114
115 flash_led3_iris_dis: flash_led3_iris_dis {
116 mux {
117 pins = "gpio23";
118 function = "gpio";
119 };
120
121 config {
122 pins = "gpio23";
123 drive_strength = <2>;
124 output-low;
125 bias-disable;
126 };
127 };
128 };
129
130
Banajit Goswamib016de92017-02-15 21:02:30 -0800131 wcd9xxx_intr {
132 wcd_intr_default: wcd_intr_default{
133 mux {
134 pins = "gpio54";
135 function = "gpio";
136 };
137
138 config {
139 pins = "gpio54";
140 drive-strength = <2>; /* 2 mA */
141 bias-pull-down; /* pull down */
142 input-enable;
143 };
144 };
145 };
146
Subhash Jadavanidd416c42017-05-15 11:54:10 -0700147 storage_cd: storage_cd {
148 mux {
149 pins = "gpio126";
150 function = "gpio";
151 };
152
153 config {
154 pins = "gpio126";
155 bias-pull-up; /* pull up */
156 drive-strength = <2>; /* 2 MA */
157 };
158 };
159
Xiaonian Wang898e0902017-04-08 06:46:29 +0800160 sdc2_clk_on: sdc2_clk_on {
161 config {
162 pins = "sdc2_clk";
163 bias-disable; /* NO pull */
164 drive-strength = <16>; /* 16 MA */
165 };
166 };
167
168 sdc2_clk_off: sdc2_clk_off {
169 config {
170 pins = "sdc2_clk";
171 bias-disable; /* NO pull */
172 drive-strength = <2>; /* 2 MA */
173 };
174 };
175
Can Guo45ebef02017-10-17 13:21:37 +0800176 sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz {
177 config {
178 pins = "sdc2_clk";
179 bias-disable; /* NO pull */
180 drive-strength = <16>; /* 16 MA */
181 };
182 };
183
184 sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz {
185 config {
186 pins = "sdc2_clk";
187 bias-disable; /* NO pull */
188 drive-strength = <16>; /* 16 MA */
189 };
190 };
191
192 sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz {
193 config {
194 pins = "sdc2_clk";
195 bias-disable; /* NO pull */
196 drive-strength = <16>; /* 16 MA */
197 };
198 };
199
200 sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz {
201 config {
202 pins = "sdc2_clk";
203 bias-disable; /* NO pull */
204 drive-strength = <16>; /* 16 MA */
205 };
206 };
207
Xiaonian Wang898e0902017-04-08 06:46:29 +0800208 sdc2_cmd_on: sdc2_cmd_on {
209 config {
210 pins = "sdc2_cmd";
211 bias-pull-up; /* pull up */
212 drive-strength = <10>; /* 10 MA */
213 };
214 };
215
216 sdc2_cmd_off: sdc2_cmd_off {
217 config {
218 pins = "sdc2_cmd";
219 bias-pull-up; /* pull up */
220 drive-strength = <2>; /* 2 MA */
221 };
222 };
223
Can Guo45ebef02017-10-17 13:21:37 +0800224 sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz {
225 config {
226 pins = "sdc2_cmd";
227 bias-pull-up; /* pull up */
228 drive-strength = <10>; /* 10 MA */
229 };
230 };
231
232 sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz {
233 config {
234 pins = "sdc2_cmd";
235 bias-pull-up; /* pull up */
236 drive-strength = <10>; /* 10 MA */
237 };
238 };
239
240 sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz {
241 config {
242 pins = "sdc2_cmd";
243 bias-pull-up; /* pull up */
244 drive-strength = <10>; /* 10 MA */
245 };
246 };
247
248 sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz {
249 config {
250 pins = "sdc2_cmd";
251 bias-pull-up; /* pull up */
252 drive-strength = <10>; /* 10 MA */
253 };
254 };
255
Xiaonian Wang898e0902017-04-08 06:46:29 +0800256 sdc2_data_on: sdc2_data_on {
257 config {
258 pins = "sdc2_data";
259 bias-pull-up; /* pull up */
260 drive-strength = <10>; /* 10 MA */
261 };
262 };
263
264 sdc2_data_off: sdc2_data_off {
265 config {
266 pins = "sdc2_data";
267 bias-pull-up; /* pull up */
268 drive-strength = <2>; /* 2 MA */
269 };
270 };
271
Can Guo45ebef02017-10-17 13:21:37 +0800272 sdc2_data_ds_400KHz: sdc2_data_ds_400KHz {
273 config {
274 pins = "sdc2_data";
275 bias-pull-up; /* pull up */
276 drive-strength = <10>; /* 10 MA */
277 };
278 };
279
280 sdc2_data_ds_50MHz: sdc2_data_ds_50MHz {
281 config {
282 pins = "sdc2_data";
283 bias-pull-up; /* pull up */
284 drive-strength = <10>; /* 10 MA */
285 };
286 };
287
288 sdc2_data_ds_100MHz: sdc2_data_ds_100MHz {
289 config {
290 pins = "sdc2_data";
291 bias-pull-up; /* pull up */
292 drive-strength = <10>; /* 10 MA */
293 };
294 };
295
296 sdc2_data_ds_200MHz: sdc2_data_ds_200MHz {
297 config {
298 pins = "sdc2_data";
299 bias-pull-up; /* pull up */
300 drive-strength = <10>; /* 10 MA */
301 };
302 };
303
Tony Truongc0e0a5f02017-03-15 11:57:40 -0700304 pcie0 {
305 pcie0_clkreq_default: pcie0_clkreq_default {
306 mux {
307 pins = "gpio36";
308 function = "pci_e0";
309 };
310
311 config {
312 pins = "gpio36";
313 drive-strength = <2>;
314 bias-pull-up;
315 };
316 };
317
318 pcie0_perst_default: pcie0_perst_default {
319 mux {
320 pins = "gpio35";
321 function = "gpio";
322 };
323
324 config {
325 pins = "gpio35";
326 drive-strength = <2>;
327 bias-pull-down;
328 };
329 };
330
331 pcie0_wake_default: pcie0_wake_default {
332 mux {
333 pins = "gpio37";
334 function = "gpio";
335 };
336
337 config {
338 pins = "gpio37";
339 drive-strength = <2>;
Tony Truong299dda12017-09-12 14:32:44 -0700340 bias-pull-up;
Tony Truongc0e0a5f02017-03-15 11:57:40 -0700341 };
342 };
343 };
344
Tony Truong16938352017-05-04 13:39:24 -0700345 pcie1 {
346 pcie1_clkreq_default: pcie1_clkreq_default {
347 mux {
348 pins = "gpio103";
349 function = "pci_e1";
350 };
351
352 config {
353 pins = "gpio103";
354 drive-strength = <2>;
355 bias-pull-up;
356 };
357 };
358
359 pcie1_perst_default: pcie1_perst_default {
360 mux {
361 pins = "gpio102";
362 function = "gpio";
363 };
364
365 config {
366 pins = "gpio102";
367 drive-strength = <2>;
368 bias-pull-down;
369 };
370 };
371
372 pcie1_wake_default: pcie1_wake_default {
373 mux {
374 pins = "gpio104";
375 function = "gpio";
376 };
377
378 config {
379 pins = "gpio104";
380 drive-strength = <2>;
381 bias-pull-down;
382 };
383 };
384 };
385
Banajit Goswamib016de92017-02-15 21:02:30 -0800386 cdc_reset_ctrl {
387 cdc_reset_sleep: cdc_reset_sleep {
388 mux {
389 pins = "gpio64";
390 function = "gpio";
391 };
392 config {
393 pins = "gpio64";
394 drive-strength = <2>;
395 bias-disable;
396 output-low;
397 };
398 };
399
400 cdc_reset_active:cdc_reset_active {
401 mux {
402 pins = "gpio64";
403 function = "gpio";
404 };
405 config {
406 pins = "gpio64";
407 drive-strength = <8>;
408 bias-pull-down;
409 output-high;
410 };
411 };
412 };
413
414 spkr_i2s_clk_pin {
415 spkr_i2s_clk_sleep: spkr_i2s_clk_sleep {
416 mux {
417 pins = "gpio69";
418 function = "spkr_i2s";
419 };
420
421 config {
422 pins = "gpio69";
423 drive-strength = <2>; /* 2 mA */
424 bias-pull-down; /* PULL DOWN */
425 };
426 };
427
428 spkr_i2s_clk_active: spkr_i2s_clk_active {
429 mux {
430 pins = "gpio69";
431 function = "spkr_i2s";
432 };
433
434 config {
435 pins = "gpio69";
436 drive-strength = <8>; /* 8 mA */
437 bias-disable; /* NO PULL */
438 };
439 };
440 };
441
442 wcd_gnd_mic_swap {
443 wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
444 mux {
445 pins = "gpio51";
446 function = "gpio";
447 };
448 config {
449 pins = "gpio51";
450 drive-strength = <2>;
451 bias-pull-down;
452 output-low;
453 };
454 };
455
456 wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
457 mux {
458 pins = "gpio51";
459 function = "gpio";
460 };
461 config {
462 pins = "gpio51";
463 drive-strength = <2>;
464 bias-disable;
465 output-high;
466 };
467 };
468 };
469
Karthikeyan Mani5bce47c2017-05-26 15:19:04 -0700470 /* USB C analog configuration */
471 wcd_usbc_analog_en1 {
472 wcd_usbc_analog_en1_idle: wcd_usbc_ana_en1_idle {
473 mux {
474 pins = "gpio49";
475 function = "gpio";
476 };
477 config {
478 pins = "gpio49";
479 drive-strength = <2>;
480 bias-pull-down;
481 output-low;
482 };
483 };
484
485 wcd_usbc_analog_en1_active: wcd_usbc_ana_en1_active {
486 mux {
487 pins = "gpio49";
488 function = "gpio";
489 };
490 config {
491 pins = "gpio49";
492 drive-strength = <2>;
493 bias-disable;
494 output-high;
495 };
496 };
497 };
498
499 wcd_usbc_analog_en2 {
500 wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle {
501 mux {
502 pins = "gpio51";
503 function = "gpio";
504 };
505 config {
506 pins = "gpio51";
507 drive-strength = <2>;
508 bias-pull-down;
509 output-low;
510 };
511 };
512
513 wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active {
514 mux {
515 pins = "gpio51";
516 function = "gpio";
517 };
518 config {
519 pins = "gpio51";
520 drive-strength = <2>;
521 bias-disable;
522 output-high;
523 };
524 };
525 };
526
Banajit Goswamib016de92017-02-15 21:02:30 -0800527 pri_aux_pcm_clk {
528 pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
529 mux {
530 pins = "gpio65";
531 function = "gpio";
532 };
533
534 config {
535 pins = "gpio65";
536 drive-strength = <2>; /* 2 mA */
537 bias-pull-down; /* PULL DOWN */
538 input-enable;
539 };
540 };
541
542 pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
543 mux {
544 pins = "gpio65";
545 function = "pri_mi2s";
546 };
547
548 config {
549 pins = "gpio65";
550 drive-strength = <8>; /* 8 mA */
551 bias-disable; /* NO PULL */
552 output-high;
553 };
554 };
555 };
556
557 pri_aux_pcm_sync {
558 pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
559 mux {
560 pins = "gpio66";
561 function = "gpio";
562 };
563
564 config {
565 pins = "gpio66";
566 drive-strength = <2>; /* 2 mA */
567 bias-pull-down; /* PULL DOWN */
568 input-enable;
569 };
570 };
571
572 pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
573 mux {
574 pins = "gpio66";
575 function = "pri_mi2s_ws";
576 };
577
578 config {
579 pins = "gpio66";
580 drive-strength = <8>; /* 8 mA */
581 bias-disable; /* NO PULL */
582 output-high;
583 };
584 };
585 };
586
587 pri_aux_pcm_din {
588 pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
589 mux {
590 pins = "gpio67";
591 function = "gpio";
592 };
593
594 config {
595 pins = "gpio67";
596 drive-strength = <2>; /* 2 mA */
597 bias-pull-down; /* PULL DOWN */
598 input-enable;
599 };
600 };
601
602 pri_aux_pcm_din_active: pri_aux_pcm_din_active {
603 mux {
604 pins = "gpio67";
605 function = "pri_mi2s";
606 };
607
608 config {
609 pins = "gpio67";
610 drive-strength = <8>; /* 8 mA */
611 bias-disable; /* NO PULL */
612 };
613 };
614 };
615
616 pri_aux_pcm_dout {
617 pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
618 mux {
619 pins = "gpio68";
620 function = "gpio";
621 };
622
623 config {
624 pins = "gpio68";
625 drive-strength = <2>; /* 2 mA */
626 bias-pull-down; /* PULL DOWN */
627 input-enable;
628 };
629 };
630
631 pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
632 mux {
633 pins = "gpio68";
634 function = "pri_mi2s";
635 };
636
637 config {
638 pins = "gpio68";
639 drive-strength = <8>; /* 8 mA */
640 bias-disable; /* NO PULL */
641 };
642 };
643 };
644
Shashank Babu Chinta Venkata2f40bc72017-03-21 15:31:38 -0700645 pmx_sde: pmx_sde {
646 sde_dsi_active: sde_dsi_active {
647 mux {
648 pins = "gpio6", "gpio52";
649 function = "gpio";
650 };
651
652 config {
653 pins = "gpio6", "gpio52";
654 drive-strength = <8>; /* 8 mA */
655 bias-disable = <0>; /* no pull */
656 };
657 };
658 sde_dsi_suspend: sde_dsi_suspend {
659 mux {
660 pins = "gpio6", "gpio52";
661 function = "gpio";
662 };
663
664 config {
665 pins = "gpio6", "gpio52";
666 drive-strength = <2>; /* 2 mA */
667 bias-pull-down; /* PULL DOWN */
668 };
669 };
670 };
671
672 pmx_sde_te {
673 sde_te_active: sde_te_active {
674 mux {
675 pins = "gpio10";
676 function = "mdp_vsync";
677 };
678
679 config {
680 pins = "gpio10";
681 drive-strength = <2>; /* 2 mA */
682 bias-pull-down; /* PULL DOWN */
683 };
684 };
685
686 sde_te_suspend: sde_te_suspend {
687 mux {
688 pins = "gpio10";
689 function = "mdp_vsync";
690 };
691
692 config {
693 pins = "gpio10";
694 drive-strength = <2>; /* 2 mA */
695 bias-pull-down; /* PULL DOWN */
696 };
697 };
698 };
699
Padmanabhan Komanduru887085e2017-05-02 14:57:12 -0700700 sde_dp_aux_active: sde_dp_aux_active {
701 mux {
702 pins = "gpio43", "gpio51";
703 function = "gpio";
704 };
705
706 config {
707 pins = "gpio43", "gpio51";
708 bias-disable = <0>; /* no pull */
709 drive-strength = <8>;
710 };
711 };
712
713 sde_dp_aux_suspend: sde_dp_aux_suspend {
714 mux {
715 pins = "gpio43", "gpio51";
716 function = "gpio";
717 };
718
719 config {
720 pins = "gpio43", "gpio51";
721 bias-pull-down;
722 drive-strength = <2>;
723 };
724 };
725
726 sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
727 mux {
728 pins = "gpio38";
729 function = "gpio";
730 };
731
732 config {
733 pins = "gpio38";
734 bias-disable;
735 drive-strength = <16>;
736 };
737 };
738
739 sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {
740 mux {
741 pins = "gpio38";
742 function = "gpio";
743 };
744
745 config {
746 pins = "gpio38";
747 bias-pull-down;
748 drive-strength = <2>;
749 };
750 };
751
Banajit Goswamib016de92017-02-15 21:02:30 -0800752 sec_aux_pcm {
753 sec_aux_pcm_sleep: sec_aux_pcm_sleep {
754 mux {
755 pins = "gpio80", "gpio81";
756 function = "gpio";
757 };
758
759 config {
760 pins = "gpio80", "gpio81";
761 drive-strength = <2>; /* 2 mA */
762 bias-pull-down; /* PULL DOWN */
763 input-enable;
764 };
765 };
766
767 sec_aux_pcm_active: sec_aux_pcm_active {
768 mux {
769 pins = "gpio80", "gpio81";
770 function = "sec_mi2s";
771 };
772
773 config {
774 pins = "gpio80", "gpio81";
775 drive-strength = <8>; /* 8 mA */
776 bias-disable; /* NO PULL */
777 };
778 };
779 };
780
781 sec_aux_pcm_din {
782 sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
783 mux {
784 pins = "gpio82";
785 function = "gpio";
786 };
787
788 config {
789 pins = "gpio82";
790 drive-strength = <2>; /* 2 mA */
791 bias-pull-down; /* PULL DOWN */
792 input-enable;
793 };
794 };
795
796 sec_aux_pcm_din_active: sec_aux_pcm_din_active {
797 mux {
798 pins = "gpio82";
799 function = "sec_mi2s";
800 };
801
802 config {
803 pins = "gpio82";
804 drive-strength = <8>; /* 8 mA */
805 bias-disable; /* NO PULL */
806 };
807 };
808 };
809
810 sec_aux_pcm_dout {
811 sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
812 mux {
813 pins = "gpio83";
814 function = "gpio";
815 };
816
817 config {
818 pins = "gpio83";
819 drive-strength = <2>; /* 2 mA */
820 bias-pull-down; /* PULL DOWN */
821 input-enable;
822 };
823 };
824
825 sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
826 mux {
827 pins = "gpio83";
828 function = "sec_mi2s";
829 };
830
831 config {
832 pins = "gpio83";
833 drive-strength = <8>; /* 8 mA */
834 bias-disable; /* NO PULL */
835 };
836 };
837 };
838
839 tert_aux_pcm {
840 tert_aux_pcm_sleep: tert_aux_pcm_sleep {
841 mux {
842 pins = "gpio75", "gpio76";
843 function = "gpio";
844 };
845
846 config {
847 pins = "gpio75", "gpio76";
848 drive-strength = <2>; /* 2 mA */
849 bias-pull-down; /* PULL DOWN */
850 input-enable;
851 };
852 };
853
854 tert_aux_pcm_active: tert_aux_pcm_active {
855 mux {
856 pins = "gpio75", "gpio76";
857 function = "ter_mi2s";
858 };
859
860 config {
861 pins = "gpio75", "gpio76";
862 drive-strength = <8>; /* 8 mA */
863 bias-disable; /* NO PULL */
864 output-high;
865 };
866 };
867 };
868
869 tert_aux_pcm_din {
870 tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
871 mux {
872 pins = "gpio77";
873 function = "gpio";
874 };
875
876 config {
877 pins = "gpio77";
878 drive-strength = <2>; /* 2 mA */
879 bias-pull-down; /* PULL DOWN */
880 input-enable;
881 };
882 };
883
884 tert_aux_pcm_din_active: tert_aux_pcm_din_active {
885 mux {
886 pins = "gpio77";
887 function = "ter_mi2s";
888 };
889
890 config {
891 pins = "gpio77";
892 drive-strength = <8>; /* 8 mA */
893 bias-disable; /* NO PULL */
894 };
895 };
896 };
897
898 tert_aux_pcm_dout {
899 tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
900 mux {
901 pins = "gpio78";
902 function = "gpio";
903 };
904
905 config {
906 pins = "gpio78";
907 drive-strength = <2>; /* 2 mA */
908 bias-pull-down; /* PULL DOWN */
909 input-enable;
910 };
911 };
912
913 tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
914 mux {
915 pins = "gpio78";
916 function = "ter_mi2s";
917 };
918
919 config {
920 pins = "gpio78";
921 drive-strength = <8>; /* 8 mA */
922 bias-disable; /* NO PULL */
923 };
924 };
925 };
926
927 quat_aux_pcm {
928 quat_aux_pcm_sleep: quat_aux_pcm_sleep {
929 mux {
930 pins = "gpio58", "gpio59";
931 function = "gpio";
932 };
933
934 config {
935 pins = "gpio58", "gpio59";
936 drive-strength = <2>; /* 2 mA */
937 bias-pull-down; /* PULL DOWN */
938 input-enable;
939 };
940 };
941
942 quat_aux_pcm_active: quat_aux_pcm_active {
943 mux {
944 pins = "gpio58", "gpio59";
945 function = "qua_mi2s";
946 };
947
948 config {
949 pins = "gpio58", "gpio59";
950 drive-strength = <8>; /* 8 mA */
951 bias-disable; /* NO PULL */
952 output-high;
953 };
954 };
955 };
956
957 quat_aux_pcm_din {
958 quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep {
959 mux {
960 pins = "gpio60";
961 function = "gpio";
962 };
963
964 config {
965 pins = "gpio60";
966 drive-strength = <2>; /* 2 mA */
967 bias-pull-down; /* PULL DOWN */
968 input-enable;
969 };
970 };
971
972 quat_aux_pcm_din_active: quat_aux_pcm_din_active {
973 mux {
974 pins = "gpio60";
975 function = "qua_mi2s";
976 };
977
978 config {
979 pins = "gpio60";
980 drive-strength = <8>; /* 8 mA */
981 bias-disable; /* NO PULL */
982 };
983 };
984 };
985
986 quat_aux_pcm_dout {
987 quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep {
988 mux {
989 pins = "gpio61";
990 function = "gpio";
991 };
992
993 config {
994 pins = "gpio61";
995 drive-strength = <2>; /* 2 mA */
996 bias-pull-down; /* PULL DOWN */
997 input-enable;
998 };
999 };
1000
1001 quat_aux_pcm_dout_active: quat_aux_pcm_dout_active {
1002 mux {
1003 pins = "gpio61";
1004 function = "qua_mi2s";
1005 };
1006
1007 config {
1008 pins = "gpio61";
1009 drive-strength = <8>; /* 8 mA */
1010 bias-disable; /* NO PULL */
1011 };
1012 };
1013 };
1014
1015 pri_mi2s_mclk {
1016 pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
1017 mux {
1018 pins = "gpio64";
1019 function = "gpio";
1020 };
1021
1022 config {
1023 pins = "gpio64";
1024 drive-strength = <2>; /* 2 mA */
1025 bias-pull-down; /* PULL DOWN */
1026 input-enable;
1027 };
1028 };
1029
1030 pri_mi2s_mclk_active: pri_mi2s_mclk_active {
1031 mux {
1032 pins = "gpio64";
1033 function = "pri_mi2s";
1034 };
1035
1036 config {
1037 pins = "gpio64";
1038 drive-strength = <8>; /* 8 mA */
1039 bias-disable; /* NO PULL */
1040 output-high;
1041 };
1042 };
1043 };
1044
1045 pri_mi2s_sck {
1046 pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
1047 mux {
1048 pins = "gpio65";
1049 function = "gpio";
1050 };
1051
1052 config {
1053 pins = "gpio65";
1054 drive-strength = <2>; /* 2 mA */
1055 bias-pull-down; /* PULL DOWN */
1056 input-enable;
1057 };
1058 };
1059
1060 pri_mi2s_sck_active: pri_mi2s_sck_active {
1061 mux {
1062 pins = "gpio65";
1063 function = "pri_mi2s";
1064 };
1065
1066 config {
1067 pins = "gpio65";
1068 drive-strength = <8>; /* 8 mA */
1069 bias-disable; /* NO PULL */
1070 output-high;
1071 };
1072 };
1073 };
1074
1075 pri_mi2s_ws {
1076 pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
1077 mux {
1078 pins = "gpio66";
1079 function = "gpio";
1080 };
1081
1082 config {
1083 pins = "gpio66";
1084 drive-strength = <2>; /* 2 mA */
1085 bias-pull-down; /* PULL DOWN */
1086 input-enable;
1087 };
1088 };
1089
1090 pri_mi2s_ws_active: pri_mi2s_ws_active {
1091 mux {
1092 pins = "gpio66";
1093 function = "pri_mi2s_ws";
1094 };
1095
1096 config {
1097 pins = "gpio66";
1098 drive-strength = <8>; /* 8 mA */
1099 bias-disable; /* NO PULL */
1100 output-high;
1101 };
1102 };
1103 };
1104
1105 pri_mi2s_sd0 {
1106 pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
1107 mux {
1108 pins = "gpio67";
1109 function = "gpio";
1110 };
1111
1112 config {
1113 pins = "gpio67";
1114 drive-strength = <2>; /* 2 mA */
1115 bias-pull-down; /* PULL DOWN */
1116 input-enable;
1117 };
1118 };
1119
1120 pri_mi2s_sd0_active: pri_mi2s_sd0_active {
1121 mux {
1122 pins = "gpio67";
1123 function = "pri_mi2s";
1124 };
1125
1126 config {
1127 pins = "gpio67";
1128 drive-strength = <8>; /* 8 mA */
1129 bias-disable; /* NO PULL */
1130 };
1131 };
1132 };
1133
1134 pri_mi2s_sd1 {
1135 pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
1136 mux {
1137 pins = "gpio68";
1138 function = "gpio";
1139 };
1140
1141 config {
1142 pins = "gpio68";
1143 drive-strength = <2>; /* 2 mA */
1144 bias-pull-down; /* PULL DOWN */
1145 input-enable;
1146 };
1147 };
1148
1149 pri_mi2s_sd1_active: pri_mi2s_sd1_active {
1150 mux {
1151 pins = "gpio68";
1152 function = "pri_mi2s";
1153 };
1154
1155 config {
1156 pins = "gpio68";
1157 drive-strength = <8>; /* 8 mA */
1158 bias-disable; /* NO PULL */
1159 };
1160 };
1161 };
1162
1163 sec_mi2s_mclk {
1164 sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
1165 mux {
1166 pins = "gpio79";
1167 function = "gpio";
1168 };
1169
1170 config {
1171 pins = "gpio79";
1172 drive-strength = <2>; /* 2 mA */
1173 bias-pull-down; /* PULL DOWN */
1174 input-enable;
1175 };
1176 };
1177
1178 sec_mi2s_mclk_active: sec_mi2s_mclk_active {
1179 mux {
1180 pins = "gpio79";
1181 function = "sec_mi2s";
1182 };
1183
1184 config {
1185 pins = "gpio79";
1186 drive-strength = <8>; /* 8 mA */
1187 bias-disable; /* NO PULL */
1188 };
1189 };
1190 };
1191
1192 sec_mi2s {
1193 sec_mi2s_sleep: sec_mi2s_sleep {
1194 mux {
1195 pins = "gpio80", "gpio81";
1196 function = "gpio";
1197 };
1198
1199 config {
1200 pins = "gpio80", "gpio81";
1201 drive-strength = <2>; /* 2 mA */
1202 bias-disable; /* NO PULL */
1203 input-enable;
1204 };
1205 };
1206
1207 sec_mi2s_active: sec_mi2s_active {
1208 mux {
1209 pins = "gpio80", "gpio81";
1210 function = "sec_mi2s";
1211 };
1212
1213 config {
1214 pins = "gpio80", "gpio81";
1215 drive-strength = <8>; /* 8 mA */
1216 bias-disable; /* NO PULL */
1217 };
1218 };
1219 };
1220
1221 sec_mi2s_sd0 {
1222 sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
1223 mux {
1224 pins = "gpio82";
1225 function = "gpio";
1226 };
1227
1228 config {
1229 pins = "gpio82";
1230 drive-strength = <2>; /* 2 mA */
1231 bias-pull-down; /* PULL DOWN */
1232 input-enable;
1233 };
1234 };
1235
1236 sec_mi2s_sd0_active: sec_mi2s_sd0_active {
1237 mux {
1238 pins = "gpio82";
1239 function = "sec_mi2s";
1240 };
1241
1242 config {
1243 pins = "gpio82";
1244 drive-strength = <8>; /* 8 mA */
1245 bias-disable; /* NO PULL */
1246 };
1247 };
1248 };
1249
1250 sec_mi2s_sd1 {
1251 sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
1252 mux {
1253 pins = "gpio83";
1254 function = "gpio";
1255 };
1256
1257 config {
1258 pins = "gpio83";
1259 drive-strength = <2>; /* 2 mA */
1260 bias-pull-down; /* PULL DOWN */
1261 input-enable;
1262 };
1263 };
1264
1265 sec_mi2s_sd1_active: sec_mi2s_sd1_active {
1266 mux {
1267 pins = "gpio83";
1268 function = "sec_mi2s";
1269 };
1270
1271 config {
1272 pins = "gpio83";
1273 drive-strength = <8>; /* 8 mA */
1274 bias-disable; /* NO PULL */
1275 };
1276 };
1277 };
1278
1279 tert_mi2s_mclk {
1280 tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep {
1281 mux {
1282 pins = "gpio74";
1283 function = "gpio";
1284 };
1285
1286 config {
1287 pins = "gpio74";
1288 drive-strength = <2>; /* 2 mA */
1289 bias-pull-down; /* PULL DOWN */
1290 input-enable;
1291 };
1292 };
1293
1294 tert_mi2s_mclk_active: tert_mi2s_mclk_active {
1295 mux {
1296 pins = "gpio74";
1297 function = "ter_mi2s";
1298 };
1299
1300 config {
1301 pins = "gpio74";
1302 drive-strength = <8>; /* 8 mA */
1303 bias-disable; /* NO PULL */
1304 };
1305 };
1306 };
1307
1308 tert_mi2s {
1309 tert_mi2s_sleep: tert_mi2s_sleep {
1310 mux {
1311 pins = "gpio75", "gpio76";
1312 function = "gpio";
1313 };
1314
1315 config {
1316 pins = "gpio75", "gpio76";
1317 drive-strength = <2>; /* 2 mA */
1318 bias-pull-down; /* PULL DOWN */
1319 input-enable;
1320 };
1321 };
1322
1323 tert_mi2s_active: tert_mi2s_active {
1324 mux {
1325 pins = "gpio75", "gpio76";
1326 function = "ter_mi2s";
1327 };
1328
1329 config {
1330 pins = "gpio75", "gpio76";
1331 drive-strength = <8>; /* 8 mA */
1332 bias-disable; /* NO PULL */
1333 output-high;
1334 };
1335 };
1336 };
1337
1338 tert_mi2s_sd0 {
1339 tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
1340 mux {
1341 pins = "gpio77";
1342 function = "gpio";
1343 };
1344
1345 config {
1346 pins = "gpio77";
1347 drive-strength = <2>; /* 2 mA */
1348 bias-pull-down; /* PULL DOWN */
1349 input-enable;
1350 };
1351 };
1352
1353 tert_mi2s_sd0_active: tert_mi2s_sd0_active {
1354 mux {
1355 pins = "gpio77";
1356 function = "ter_mi2s";
1357 };
1358
1359 config {
1360 pins = "gpio77";
1361 drive-strength = <8>; /* 8 mA */
1362 bias-disable; /* NO PULL */
1363 };
1364 };
1365 };
1366
1367 tert_mi2s_sd1 {
1368 tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
1369 mux {
1370 pins = "gpio78";
1371 function = "gpio";
1372 };
1373
1374 config {
1375 pins = "gpio78";
1376 drive-strength = <2>; /* 2 mA */
1377 bias-pull-down; /* PULL DOWN */
1378 input-enable;
1379 };
1380 };
1381
1382 tert_mi2s_sd1_active: tert_mi2s_sd1_active {
1383 mux {
1384 pins = "gpio78";
1385 function = "ter_mi2s";
1386 };
1387
1388 config {
1389 pins = "gpio78";
1390 drive-strength = <8>; /* 8 mA */
1391 bias-disable; /* NO PULL */
1392 };
1393 };
1394 };
1395
1396 quat_mi2s_mclk {
1397 quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep {
1398 mux {
1399 pins = "gpio57";
1400 function = "gpio";
1401 };
1402
1403 config {
1404 pins = "gpio57";
1405 drive-strength = <2>; /* 2 mA */
1406 bias-pull-down; /* PULL DOWN */
1407 input-enable;
1408 };
1409 };
1410
1411 quat_mi2s_mclk_active: quat_mi2s_mclk_active {
1412 mux {
1413 pins = "gpio57";
1414 function = "qua_mi2s";
1415 };
1416
1417 config {
1418 pins = "gpio57";
1419 drive-strength = <8>; /* 8 mA */
1420 bias-disable; /* NO PULL */
1421 };
1422 };
1423 };
1424
1425 quat_mi2s {
1426 quat_mi2s_sleep: quat_mi2s_sleep {
1427 mux {
1428 pins = "gpio58", "gpio59";
1429 function = "gpio";
1430 };
1431
1432 config {
1433 pins = "gpio58", "gpio59";
1434 drive-strength = <2>; /* 2 mA */
1435 bias-pull-down; /* PULL DOWN */
1436 input-enable;
1437 };
1438 };
1439
1440 quat_mi2s_active: quat_mi2s_active {
1441 mux {
1442 pins = "gpio58", "gpio59";
1443 function = "qua_mi2s";
1444 };
1445
1446 config {
1447 pins = "gpio58", "gpio59";
1448 drive-strength = <8>; /* 8 mA */
1449 bias-disable; /* NO PULL */
1450 output-high;
1451 };
1452 };
1453 };
1454
1455 quat_mi2s_sd0 {
1456 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
1457 mux {
1458 pins = "gpio60";
1459 function = "gpio";
1460 };
1461
1462 config {
1463 pins = "gpio60";
1464 drive-strength = <2>; /* 2 mA */
1465 bias-pull-down; /* PULL DOWN */
1466 input-enable;
1467 };
1468 };
1469
1470 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
1471 mux {
1472 pins = "gpio60";
1473 function = "qua_mi2s";
1474 };
1475
1476 config {
1477 pins = "gpio60";
1478 drive-strength = <8>; /* 8 mA */
1479 bias-disable; /* NO PULL */
1480 };
1481 };
1482 };
1483
1484 quat_mi2s_sd1 {
1485 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
1486 mux {
1487 pins = "gpio61";
1488 function = "gpio";
1489 };
1490
1491 config {
1492 pins = "gpio61";
1493 drive-strength = <2>; /* 2 mA */
1494 bias-pull-down; /* PULL DOWN */
1495 input-enable;
1496 };
1497 };
1498
1499 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
1500 mux {
1501 pins = "gpio61";
1502 function = "qua_mi2s";
1503 };
1504
1505 config {
1506 pins = "gpio61";
1507 drive-strength = <8>; /* 8 mA */
1508 bias-disable; /* NO PULL */
1509 };
1510 };
1511 };
1512
1513 quat_mi2s_sd2 {
1514 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
1515 mux {
1516 pins = "gpio62";
1517 function = "gpio";
1518 };
1519
1520 config {
1521 pins = "gpio62";
1522 drive-strength = <2>; /* 2 mA */
1523 bias-pull-down; /* PULL DOWN */
1524 input-enable;
1525 };
1526 };
1527
1528 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
1529 mux {
1530 pins = "gpio62";
1531 function = "qua_mi2s";
1532 };
1533
1534 config {
1535 pins = "gpio62";
1536 drive-strength = <8>; /* 8 mA */
1537 bias-disable; /* NO PULL */
1538 };
1539 };
1540 };
1541
1542 quat_mi2s_sd3 {
1543 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
1544 mux {
1545 pins = "gpio63";
1546 function = "gpio";
1547 };
1548
1549 config {
1550 pins = "gpio63";
1551 drive-strength = <2>; /* 2 mA */
1552 bias-pull-down; /* PULL DOWN */
1553 input-enable;
1554 };
1555 };
1556
1557 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
1558 mux {
1559 pins = "gpio63";
1560 function = "qua_mi2s";
1561 };
1562
1563 config {
1564 pins = "gpio63";
1565 drive-strength = <8>; /* 8 mA */
1566 bias-disable; /* NO PULL */
1567 };
1568 };
1569 };
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001570
Xiaoyu Yee1bd1c62017-07-31 16:36:25 -07001571 quat_tdm {
1572 quat_tdm_sleep: quat_tdm_sleep {
1573 mux {
1574 pins = "gpio58", "gpio59";
1575 function = "qua_mi2s";
1576 };
1577
1578 config {
1579 pins = "gpio58", "gpio59";
1580 drive-strength = <2>; /* 2 mA */
1581 bias-pull-down; /* PULL DOWN */
1582 };
1583 };
1584
1585 quat_tdm_active: quat_tdm_active {
1586 mux {
1587 pins = "gpio58", "gpio59";
1588 function = "qua_mi2s";
1589 };
1590
1591 config {
1592 pins = "gpio58", "gpio59";
1593 drive-strength = <8>; /* 8 mA */
1594 bias-disable; /* NO PULL */
1595 };
1596 };
1597 };
1598
1599 quat_tdm_dout {
1600 quat_tdm_dout_sleep: quat_tdm_dout_sleep {
1601 mux {
1602 pins = "gpio61";
1603 function = "qua_mi2s";
1604 };
1605
1606 config {
1607 pins = "gpio61";
1608 drive-strength = <2>; /* 2 mA */
1609 bias-pull-down; /* PULL DOWN */
1610 };
1611 };
1612
1613 quat_tdm_dout_active: quat_tdm_dout_active {
1614 mux {
1615 pins = "gpio61";
1616 function = "qua_mi2s";
1617 };
1618
1619 config {
1620 pins = "gpio61";
1621 drive-strength = <2>; /* 2 mA */
1622 bias-disable; /* NO PULL */
1623 };
1624 };
1625 };
1626
1627 quat_tdm_din {
1628 quat_tdm_din_sleep: quat_tdm_din_sleep {
1629 mux {
1630 pins = "gpio60";
1631 function = "qua_mi2s";
1632 };
1633
1634 config {
1635 pins = "gpio60";
1636 drive-strength = <2>; /* 2 mA */
1637 bias-pull-down; /* PULL DOWN */
1638 };
1639 };
1640
1641 quat_tdm_din_active: quat_tdm_din_active {
1642 mux {
1643 pins = "gpio60";
1644 function = "qua_mi2s";
1645 };
1646
1647 config {
1648 pins = "gpio60";
1649 drive-strength = <2>; /* 2 mA */
1650 bias-disable; /* NO PULL */
1651 };
1652 };
1653 };
1654
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001655 /* QUPv3 South SE mappings */
1656 /* SE 0 pin mappings */
1657 qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
1658 qupv3_se0_i2c_active: qupv3_se0_i2c_active {
1659 mux {
1660 pins = "gpio0", "gpio1";
1661 function = "qup0";
1662 };
1663
1664 config {
1665 pins = "gpio0", "gpio1";
1666 drive-strength = <2>;
1667 bias-disable;
1668 };
1669 };
1670
1671 qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
1672 mux {
1673 pins = "gpio0", "gpio1";
1674 function = "gpio";
1675 };
1676
1677 config {
1678 pins = "gpio0", "gpio1";
1679 drive-strength = <2>;
1680 bias-pull-up;
1681 };
1682 };
1683 };
1684
1685 qupv3_se0_spi_pins: qupv3_se0_spi_pins {
1686 qupv3_se0_spi_active: qupv3_se0_spi_active {
1687 mux {
1688 pins = "gpio0", "gpio1", "gpio2",
1689 "gpio3";
1690 function = "qup0";
1691 };
1692
1693 config {
1694 pins = "gpio0", "gpio1", "gpio2",
1695 "gpio3";
1696 drive-strength = <6>;
1697 bias-disable;
1698 };
1699 };
1700
1701 qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
1702 mux {
1703 pins = "gpio0", "gpio1", "gpio2",
1704 "gpio3";
1705 function = "gpio";
1706 };
1707
1708 config {
1709 pins = "gpio0", "gpio1", "gpio2",
1710 "gpio3";
1711 drive-strength = <6>;
1712 bias-disable;
1713 };
1714 };
1715 };
1716
1717 /* SE 1 pin mappings */
1718 qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
1719 qupv3_se1_i2c_active: qupv3_se1_i2c_active {
1720 mux {
1721 pins = "gpio17", "gpio18";
1722 function = "qup1";
1723 };
1724
1725 config {
1726 pins = "gpio17", "gpio18";
1727 drive-strength = <2>;
1728 bias-disable;
1729 };
1730 };
1731
1732 qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
1733 mux {
1734 pins = "gpio17", "gpio18";
1735 function = "gpio";
1736 };
1737
1738 config {
1739 pins = "gpio17", "gpio18";
1740 drive-strength = <2>;
1741 bias-pull-up;
1742 };
1743 };
1744 };
1745
1746 qupv3_se1_spi_pins: qupv3_se1_spi_pins {
1747 qupv3_se1_spi_active: qupv3_se1_spi_active {
1748 mux {
1749 pins = "gpio17", "gpio18", "gpio19",
1750 "gpio20";
1751 function = "qup1";
1752 };
1753
1754 config {
1755 pins = "gpio17", "gpio18", "gpio19",
1756 "gpio20";
1757 drive-strength = <6>;
1758 bias-disable;
1759 };
1760 };
1761
1762 qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
1763 mux {
1764 pins = "gpio17", "gpio18", "gpio19",
1765 "gpio20";
1766 function = "gpio";
1767 };
1768
1769 config {
1770 pins = "gpio17", "gpio18", "gpio19",
1771 "gpio20";
1772 drive-strength = <6>;
1773 bias-disable;
1774 };
1775 };
1776 };
1777
1778 /* SE 2 pin mappings */
1779 qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
1780 qupv3_se2_i2c_active: qupv3_se2_i2c_active {
1781 mux {
1782 pins = "gpio27", "gpio28";
1783 function = "qup2";
1784 };
1785
1786 config {
1787 pins = "gpio27", "gpio28";
1788 drive-strength = <2>;
1789 bias-disable;
1790 };
1791 };
1792
1793 qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
1794 mux {
1795 pins = "gpio27", "gpio28";
1796 function = "gpio";
1797 };
1798
1799 config {
1800 pins = "gpio27", "gpio28";
1801 drive-strength = <2>;
1802 bias-pull-up;
1803 };
1804 };
1805 };
1806
1807 qupv3_se2_spi_pins: qupv3_se2_spi_pins {
1808 qupv3_se2_spi_active: qupv3_se2_spi_active {
1809 mux {
1810 pins = "gpio27", "gpio28", "gpio29",
1811 "gpio30";
1812 function = "qup2";
1813 };
1814
1815 config {
1816 pins = "gpio27", "gpio28", "gpio29",
1817 "gpio30";
1818 drive-strength = <6>;
1819 bias-disable;
1820 };
1821 };
1822
1823 qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
1824 mux {
1825 pins = "gpio27", "gpio28", "gpio29",
1826 "gpio30";
1827 function = "gpio";
1828 };
1829
1830 config {
1831 pins = "gpio27", "gpio28", "gpio29",
1832 "gpio30";
1833 drive-strength = <6>;
1834 bias-disable;
1835 };
1836 };
1837 };
1838
1839 /* SE 3 pin mappings */
1840 qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
1841 qupv3_se3_i2c_active: qupv3_se3_i2c_active {
1842 mux {
1843 pins = "gpio41", "gpio42";
1844 function = "qup3";
1845 };
1846
1847 config {
1848 pins = "gpio41", "gpio42";
1849 drive-strength = <2>;
1850 bias-disable;
1851 };
1852 };
1853
1854 qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
1855 mux {
1856 pins = "gpio41", "gpio42";
1857 function = "gpio";
1858 };
1859
1860 config {
1861 pins = "gpio41", "gpio42";
1862 drive-strength = <2>;
1863 bias-pull-up;
1864 };
1865 };
1866 };
1867
Gaurav Singhalf6d253d2017-05-11 08:24:40 +05301868 nfc {
1869 nfc_int_active: nfc_int_active {
1870 /* active state */
1871 mux {
1872 /* GPIO 63 NFC Read Interrupt */
1873 pins = "gpio63";
1874 function = "gpio";
1875 };
1876
1877 config {
1878 pins = "gpio63";
1879 drive-strength = <2>; /* 2 MA */
1880 bias-pull-up;
1881 };
1882 };
1883
1884 nfc_int_suspend: nfc_int_suspend {
1885 /* sleep state */
1886 mux {
1887 /* GPIO 63 NFC Read Interrupt */
1888 pins = "gpio63";
1889 function = "gpio";
1890 };
1891
1892 config {
1893 pins = "gpio63";
1894 drive-strength = <2>; /* 2 MA */
1895 bias-pull-up;
1896 };
1897 };
1898
1899 nfc_enable_active: nfc_enable_active {
1900 /* active state */
1901 mux {
1902 /* 12: NFC ENABLE 116:ESE Enable */
1903 pins = "gpio12", "gpio62", "gpio116";
1904 function = "gpio";
1905 };
1906
1907 config {
1908 pins = "gpio12", "gpio62", "gpio116";
1909 drive-strength = <2>; /* 2 MA */
1910 bias-pull-up;
1911 };
1912 };
1913
1914 nfc_enable_suspend: nfc_enable_suspend {
1915 /* sleep state */
1916 mux {
1917 /* 12: NFC ENABLE 116:ESE Enable */
1918 pins = "gpio12", "gpio62", "gpio116";
1919 function = "gpio";
1920 };
1921
1922 config {
1923 pins = "gpio12", "gpio62", "gpio116";
1924 drive-strength = <2>; /* 2 MA */
1925 bias-disable;
1926 };
1927 };
1928 };
1929
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001930 qupv3_se3_spi_pins: qupv3_se3_spi_pins {
1931 qupv3_se3_spi_active: qupv3_se3_spi_active {
1932 mux {
1933 pins = "gpio41", "gpio42", "gpio43",
1934 "gpio44";
1935 function = "qup3";
1936 };
1937
1938 config {
1939 pins = "gpio41", "gpio42", "gpio43",
1940 "gpio44";
1941 drive-strength = <6>;
1942 bias-disable;
1943 };
1944 };
1945
1946 qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
1947 mux {
1948 pins = "gpio41", "gpio42", "gpio43",
1949 "gpio44";
1950 function = "gpio";
1951 };
1952
1953 config {
1954 pins = "gpio41", "gpio42", "gpio43",
1955 "gpio44";
1956 drive-strength = <6>;
1957 bias-disable;
1958 };
1959 };
1960 };
1961
1962 /* SE 4 pin mappings */
1963 qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
1964 qupv3_se4_i2c_active: qupv3_se4_i2c_active {
1965 mux {
1966 pins = "gpio89", "gpio90";
1967 function = "qup4";
1968 };
1969
1970 config {
1971 pins = "gpio89", "gpio90";
1972 drive-strength = <2>;
1973 bias-disable;
1974 };
1975 };
1976
1977 qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
1978 mux {
1979 pins = "gpio89", "gpio90";
1980 function = "gpio";
1981 };
1982
1983 config {
1984 pins = "gpio89", "gpio90";
1985 drive-strength = <2>;
1986 bias-pull-up;
1987 };
1988 };
1989 };
1990
1991 qupv3_se4_spi_pins: qupv3_se4_spi_pins {
1992 qupv3_se4_spi_active: qupv3_se4_spi_active {
1993 mux {
1994 pins = "gpio89", "gpio90", "gpio91",
1995 "gpio92";
1996 function = "qup4";
1997 };
1998
1999 config {
2000 pins = "gpio89", "gpio90", "gpio91",
2001 "gpio92";
2002 drive-strength = <6>;
2003 bias-disable;
2004 };
2005 };
2006
2007 qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
2008 mux {
2009 pins = "gpio89", "gpio90", "gpio91",
2010 "gpio92";
2011 function = "gpio";
2012 };
2013
2014 config {
2015 pins = "gpio89", "gpio90", "gpio91",
2016 "gpio92";
2017 drive-strength = <6>;
2018 bias-disable;
2019 };
2020 };
2021 };
2022
2023 /* SE 5 pin mappings */
2024 qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
2025 qupv3_se5_i2c_active: qupv3_se5_i2c_active {
2026 mux {
2027 pins = "gpio85", "gpio86";
2028 function = "qup5";
2029 };
2030
2031 config {
2032 pins = "gpio85", "gpio86";
2033 drive-strength = <2>;
2034 bias-disable;
2035 };
2036 };
2037
2038 qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
2039 mux {
2040 pins = "gpio85", "gpio86";
2041 function = "gpio";
2042 };
2043
2044 config {
2045 pins = "gpio85", "gpio86";
2046 drive-strength = <2>;
2047 bias-pull-up;
2048 };
2049 };
2050 };
2051
2052 qupv3_se5_spi_pins: qupv3_se5_spi_pins {
2053 qupv3_se5_spi_active: qupv3_se5_spi_active {
2054 mux {
2055 pins = "gpio85", "gpio86", "gpio87",
2056 "gpio88";
2057 function = "qup5";
2058 };
2059
2060 config {
2061 pins = "gpio85", "gpio86", "gpio87",
2062 "gpio88";
2063 drive-strength = <6>;
2064 bias-disable;
2065 };
2066 };
2067
2068 qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
2069 mux {
2070 pins = "gpio85", "gpio86", "gpio87",
2071 "gpio88";
2072 function = "gpio";
2073 };
2074
2075 config {
2076 pins = "gpio85", "gpio86", "gpio87",
2077 "gpio88";
2078 drive-strength = <6>;
2079 bias-disable;
2080 };
2081 };
2082 };
2083
2084 /* SE 6 pin mappings */
2085 qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
2086 qupv3_se6_i2c_active: qupv3_se6_i2c_active {
2087 mux {
2088 pins = "gpio45", "gpio46";
2089 function = "qup6";
2090 };
2091
2092 config {
2093 pins = "gpio45", "gpio46";
2094 drive-strength = <2>;
2095 bias-disable;
2096 };
2097 };
2098
2099 qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
2100 mux {
2101 pins = "gpio45", "gpio46";
2102 function = "gpio";
2103 };
2104
2105 config {
2106 pins = "gpio45", "gpio46";
2107 drive-strength = <2>;
2108 bias-pull-up;
2109 };
2110 };
2111 };
2112
2113 qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
2114 qupv3_se6_4uart_active: qupv3_se6_4uart_active {
2115 mux {
2116 pins = "gpio45", "gpio46", "gpio47",
2117 "gpio48";
2118 function = "qup6";
2119 };
2120
2121 config {
2122 pins = "gpio45", "gpio46", "gpio47",
2123 "gpio48";
2124 drive-strength = <2>;
2125 bias-disable;
2126 };
2127 };
2128
2129 qupv3_se6_4uart_sleep: qupv3_se6_4uart_sleep {
2130 mux {
2131 pins = "gpio45", "gpio46", "gpio47",
2132 "gpio48";
2133 function = "gpio";
2134 };
2135
2136 config {
2137 pins = "gpio45", "gpio46", "gpio47",
2138 "gpio48";
2139 drive-strength = <2>;
2140 bias-disable;
2141 };
2142 };
2143 };
2144
2145 qupv3_se6_spi_pins: qupv3_se6_spi_pins {
2146 qupv3_se6_spi_active: qupv3_se6_spi_active {
2147 mux {
2148 pins = "gpio45", "gpio46", "gpio47",
2149 "gpio48";
2150 function = "qup6";
2151 };
2152
2153 config {
2154 pins = "gpio45", "gpio46", "gpio47",
2155 "gpio48";
2156 drive-strength = <6>;
2157 bias-disable;
2158 };
2159 };
2160
2161 qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
2162 mux {
2163 pins = "gpio45", "gpio46", "gpio47",
2164 "gpio48";
2165 function = "gpio";
2166 };
2167
2168 config {
2169 pins = "gpio45", "gpio46", "gpio47",
2170 "gpio48";
2171 drive-strength = <6>;
2172 bias-disable;
2173 };
2174 };
2175 };
2176
2177 /* SE 7 pin mappings */
2178 qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
2179 qupv3_se7_i2c_active: qupv3_se7_i2c_active {
2180 mux {
2181 pins = "gpio93", "gpio94";
2182 function = "qup7";
2183 };
2184
2185 config {
2186 pins = "gpio93", "gpio94";
2187 drive-strength = <2>;
2188 bias-disable;
2189 };
2190 };
2191
2192 qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
2193 mux {
2194 pins = "gpio93", "gpio94";
2195 function = "gpio";
2196 };
2197
2198 config {
2199 pins = "gpio93", "gpio94";
2200 drive-strength = <2>;
2201 bias-pull-up;
2202 };
2203 };
2204 };
2205
2206 qupv3_se7_4uart_pins: qupv3_se7_4uart_pins {
2207 qupv3_se7_4uart_active: qupv3_se7_4uart_active {
2208 mux {
2209 pins = "gpio93", "gpio94", "gpio95",
2210 "gpio96";
2211 function = "qup7";
2212 };
2213
2214 config {
2215 pins = "gpio93", "gpio94", "gpio95",
2216 "gpio96";
2217 drive-strength = <2>;
2218 bias-disable;
2219 };
2220 };
2221
2222 qupv3_se7_4uart_sleep: qupv3_se7_4uart_sleep {
2223 mux {
2224 pins = "gpio93", "gpio94", "gpio95",
2225 "gpio96";
2226 function = "gpio";
2227 };
2228
2229 config {
2230 pins = "gpio93", "gpio94", "gpio95",
2231 "gpio96";
2232 drive-strength = <2>;
2233 bias-disable;
2234 };
2235 };
2236 };
2237
2238 qupv3_se7_spi_pins: qupv3_se7_spi_pins {
2239 qupv3_se7_spi_active: qupv3_se7_spi_active {
2240 mux {
2241 pins = "gpio93", "gpio94", "gpio95",
2242 "gpio96";
2243 function = "qup7";
2244 };
2245
2246 config {
2247 pins = "gpio93", "gpio94", "gpio95",
2248 "gpio96";
2249 drive-strength = <6>;
2250 bias-disable;
2251 };
2252 };
2253
2254 qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
2255 mux {
2256 pins = "gpio93", "gpio94", "gpio95",
2257 "gpio96";
2258 function = "gpio";
2259 };
2260
2261 config {
2262 pins = "gpio93", "gpio94", "gpio95",
2263 "gpio96";
2264 drive-strength = <6>;
2265 bias-disable;
2266 };
2267 };
2268 };
2269
2270 /* QUPv3 North instances */
2271 /* SE 8 pin mappings */
2272 qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
2273 qupv3_se8_i2c_active: qupv3_se8_i2c_active {
2274 mux {
2275 pins = "gpio65", "gpio66";
2276 function = "qup8";
2277 };
2278
2279 config {
2280 pins = "gpio65", "gpio66";
2281 drive-strength = <2>;
2282 bias-disable;
2283 };
2284 };
2285
2286 qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
2287 mux {
2288 pins = "gpio65", "gpio66";
2289 function = "gpio";
2290 };
2291
2292 config {
2293 pins = "gpio65", "gpio66";
2294 drive-strength = <2>;
2295 bias-pull-up;
2296 };
2297 };
2298 };
2299
2300 qupv3_se8_spi_pins: qupv3_se8_spi_pins {
2301 qupv3_se8_spi_active: qupv3_se8_spi_active {
2302 mux {
2303 pins = "gpio65", "gpio66", "gpio67",
2304 "gpio68";
2305 function = "qup8";
2306 };
2307
2308 config {
2309 pins = "gpio65", "gpio66", "gpio67",
2310 "gpio68";
2311 drive-strength = <6>;
2312 bias-disable;
2313 };
2314 };
2315
2316 qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
2317 mux {
2318 pins = "gpio65", "gpio66", "gpio67",
2319 "gpio68";
2320 function = "gpio";
2321 };
2322
2323 config {
2324 pins = "gpio65", "gpio66", "gpio67",
2325 "gpio68";
2326 drive-strength = <6>;
2327 bias-disable;
2328 };
2329 };
2330 };
2331
2332 /* SE 9 pin mappings */
2333 qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
2334 qupv3_se9_i2c_active: qupv3_se9_i2c_active {
2335 mux {
2336 pins = "gpio6", "gpio7";
2337 function = "qup9";
2338 };
2339
2340 config {
2341 pins = "gpio6", "gpio7";
2342 drive-strength = <2>;
2343 bias-disable;
2344 };
2345 };
2346
2347 qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
2348 mux {
2349 pins = "gpio6", "gpio7";
2350 function = "gpio";
2351 };
2352
2353 config {
2354 pins = "gpio6", "gpio7";
2355 drive-strength = <2>;
2356 bias-pull-up;
2357 };
2358 };
2359 };
2360
2361 qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
2362 qupv3_se9_2uart_active: qupv3_se9_2uart_active {
2363 mux {
2364 pins = "gpio4", "gpio5";
2365 function = "qup9";
2366 };
2367
2368 config {
2369 pins = "gpio4", "gpio5";
2370 drive-strength = <2>;
2371 bias-disable;
2372 };
2373 };
2374
2375 qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
2376 mux {
2377 pins = "gpio4", "gpio5";
2378 function = "gpio";
2379 };
2380
2381 config {
2382 pins = "gpio4", "gpio5";
2383 drive-strength = <2>;
2384 bias-disable;
2385 };
2386 };
2387 };
2388
2389 qupv3_se9_spi_pins: qupv3_se9_spi_pins {
2390 qupv3_se9_spi_active: qupv3_se9_spi_active {
2391 mux {
2392 pins = "gpio4", "gpio5", "gpio6",
2393 "gpio7";
2394 function = "qup9";
2395 };
2396
2397 config {
2398 pins = "gpio4", "gpio5", "gpio6",
2399 "gpio7";
2400 drive-strength = <6>;
2401 bias-disable;
2402 };
2403 };
2404
2405 qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
2406 mux {
2407 pins = "gpio4", "gpio5", "gpio6",
2408 "gpio7";
2409 function = "gpio";
2410 };
2411
2412 config {
2413 pins = "gpio4", "gpio5", "gpio6",
2414 "gpio7";
2415 drive-strength = <6>;
2416 bias-disable;
2417 };
2418 };
2419 };
2420
2421 /* SE 10 pin mappings */
2422 qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
2423 qupv3_se10_i2c_active: qupv3_se10_i2c_active {
2424 mux {
2425 pins = "gpio55", "gpio56";
2426 function = "qup10";
2427 };
2428
2429 config {
2430 pins = "gpio55", "gpio56";
2431 drive-strength = <2>;
2432 bias-disable;
2433 };
2434 };
2435
2436 qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
2437 mux {
2438 pins = "gpio55", "gpio56";
2439 function = "gpio";
2440 };
2441
2442 config {
2443 pins = "gpio55", "gpio56";
2444 drive-strength = <2>;
2445 bias-pull-up;
2446 };
2447 };
2448 };
2449
2450 qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {
2451 qupv3_se10_2uart_active: qupv3_se10_2uart_active {
2452 mux {
2453 pins = "gpio53", "gpio54";
2454 function = "qup10";
2455 };
2456
2457 config {
2458 pins = "gpio53", "gpio54";
2459 drive-strength = <2>;
2460 bias-disable;
2461 };
2462 };
2463
2464 qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep {
2465 mux {
2466 pins = "gpio53", "gpio54";
2467 function = "gpio";
2468 };
2469
2470 config {
2471 pins = "gpio53", "gpio54";
2472 drive-strength = <2>;
2473 bias-disable;
2474 };
2475 };
2476 };
2477
2478 qupv3_se10_spi_pins: qupv3_se10_spi_pins {
2479 qupv3_se10_spi_active: qupv3_se10_spi_active {
2480 mux {
2481 pins = "gpio53", "gpio54", "gpio55",
2482 "gpio56";
2483 function = "qup10";
2484 };
2485
2486 config {
2487 pins = "gpio53", "gpio54", "gpio55",
2488 "gpio56";
2489 drive-strength = <6>;
2490 bias-disable;
2491 };
2492 };
2493
2494 qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
2495 mux {
2496 pins = "gpio53", "gpio54", "gpio55",
2497 "gpio56";
2498 function = "gpio";
2499 };
2500
2501 config {
2502 pins = "gpio53", "gpio54", "gpio55",
2503 "gpio56";
2504 drive-strength = <6>;
2505 bias-disable;
2506 };
2507 };
2508 };
2509
2510 /* SE 11 pin mappings */
2511 qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
2512 qupv3_se11_i2c_active: qupv3_se11_i2c_active {
2513 mux {
2514 pins = "gpio31", "gpio32";
2515 function = "qup11";
2516 };
2517
2518 config {
2519 pins = "gpio31", "gpio32";
2520 drive-strength = <2>;
2521 bias-disable;
2522 };
2523 };
2524
2525 qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
2526 mux {
2527 pins = "gpio31", "gpio32";
2528 function = "gpio";
2529 };
2530
2531 config {
2532 pins = "gpio31", "gpio32";
2533 drive-strength = <2>;
2534 bias-pull-up;
2535 };
2536 };
2537 };
2538
2539 qupv3_se11_spi_pins: qupv3_se11_spi_pins {
2540 qupv3_se11_spi_active: qupv3_se11_spi_active {
2541 mux {
2542 pins = "gpio31", "gpio32", "gpio33",
2543 "gpio34";
2544 function = "qup11";
2545 };
2546
2547 config {
2548 pins = "gpio31", "gpio32", "gpio33",
2549 "gpio34";
2550 drive-strength = <6>;
2551 bias-disable;
2552 };
2553 };
2554
2555 qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
2556 mux {
2557 pins = "gpio31", "gpio32", "gpio33",
2558 "gpio34";
2559 function = "gpio";
2560 };
2561
2562 config {
2563 pins = "gpio31", "gpio32", "gpio33",
2564 "gpio34";
2565 drive-strength = <6>;
2566 bias-disable;
2567 };
2568 };
2569 };
2570
2571 /* SE 12 pin mappings */
2572 qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
2573 qupv3_se12_i2c_active: qupv3_se12_i2c_active {
2574 mux {
2575 pins = "gpio49", "gpio50";
2576 function = "qup12";
2577 };
2578
2579 config {
2580 pins = "gpio49", "gpio50";
2581 drive-strength = <2>;
2582 bias-disable;
2583 };
2584 };
2585
2586 qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
2587 mux {
2588 pins = "gpio49", "gpio50";
2589 function = "gpio";
2590 };
2591
2592 config {
2593 pins = "gpio49", "gpio50";
2594 drive-strength = <2>;
2595 bias-pull-up;
2596 };
2597 };
2598 };
2599
2600 qupv3_se12_spi_pins: qupv3_se12_spi_pins {
2601 qupv3_se12_spi_active: qupv3_se12_spi_active {
2602 mux {
2603 pins = "gpio49", "gpio50", "gpio51",
2604 "gpio52";
2605 function = "qup12";
2606 };
2607
2608 config {
2609 pins = "gpio49", "gpio50", "gpio51",
2610 "gpio52";
2611 drive-strength = <6>;
2612 bias-disable;
2613 };
2614 };
2615
2616 qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
2617 mux {
2618 pins = "gpio49", "gpio50", "gpio51",
2619 "gpio52";
2620 function = "gpio";
2621 };
2622
2623 config {
2624 pins = "gpio49", "gpio50", "gpio51",
2625 "gpio52";
2626 drive-strength = <6>;
2627 bias-disable;
2628 };
2629 };
2630 };
2631
2632 /* SE 13 pin mappings */
2633 qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
2634 qupv3_se13_i2c_active: qupv3_se13_i2c_active {
2635 mux {
2636 pins = "gpio105", "gpio106";
2637 function = "qup13";
2638 };
2639
2640 config {
2641 pins = "gpio105", "gpio106";
2642 drive-strength = <2>;
2643 bias-disable;
2644 };
2645 };
2646
2647 qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
2648 mux {
2649 pins = "gpio105", "gpio106";
2650 function = "gpio";
2651 };
2652
2653 config {
2654 pins = "gpio105", "gpio106";
2655 drive-strength = <2>;
2656 bias-pull-up;
2657 };
2658 };
2659 };
2660
2661 qupv3_se13_spi_pins: qupv3_se13_spi_pins {
2662 qupv3_se13_spi_active: qupv3_se13_spi_active {
2663 mux {
2664 pins = "gpio105", "gpio106", "gpio107",
2665 "gpio108";
2666 function = "qup13";
2667 };
2668
2669 config {
2670 pins = "gpio105", "gpio106", "gpio107",
2671 "gpio108";
2672 drive-strength = <6>;
2673 bias-disable;
2674 };
2675 };
2676
2677 qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
2678 mux {
2679 pins = "gpio105", "gpio106", "gpio107",
2680 "gpio108";
2681 function = "gpio";
2682 };
2683
2684 config {
2685 pins = "gpio105", "gpio106", "gpio107",
2686 "gpio108";
2687 drive-strength = <6>;
2688 bias-disable;
2689 };
2690 };
2691 };
2692
2693 /* SE 14 pin mappings */
2694 qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
2695 qupv3_se14_i2c_active: qupv3_se14_i2c_active {
2696 mux {
2697 pins = "gpio33", "gpio34";
2698 function = "qup14";
2699 };
2700
2701 config {
2702 pins = "gpio33", "gpio34";
2703 drive-strength = <2>;
2704 bias-disable;
2705 };
2706 };
2707
2708 qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
2709 mux {
2710 pins = "gpio33", "gpio34";
2711 function = "gpio";
2712 };
2713
2714 config {
2715 pins = "gpio33", "gpio34";
2716 drive-strength = <2>;
2717 bias-pull-up;
2718 };
2719 };
2720 };
2721
2722 qupv3_se14_spi_pins: qupv3_se14_spi_pins {
2723 qupv3_se14_spi_active: qupv3_se14_spi_active {
2724 mux {
2725 pins = "gpio31", "gpio32", "gpio33",
2726 "gpio34";
2727 function = "qup14";
2728 };
2729
2730 config {
2731 pins = "gpio31", "gpio32", "gpio33",
2732 "gpio34";
2733 drive-strength = <6>;
2734 bias-disable;
2735 };
2736 };
2737
2738 qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
2739 mux {
2740 pins = "gpio31", "gpio32", "gpio33",
2741 "gpio34";
2742 function = "gpio";
2743 };
2744
2745 config {
2746 pins = "gpio31", "gpio32", "gpio33",
2747 "gpio34";
2748 drive-strength = <6>;
2749 bias-disable;
2750 };
2751 };
2752 };
2753
2754 /* SE 15 pin mappings */
2755 qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
2756 qupv3_se15_i2c_active: qupv3_se15_i2c_active {
2757 mux {
2758 pins = "gpio81", "gpio82";
2759 function = "qup15";
2760 };
2761
2762 config {
2763 pins = "gpio81", "gpio82";
2764 drive-strength = <2>;
2765 bias-disable;
2766 };
2767 };
2768
2769 qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
2770 mux {
2771 pins = "gpio81", "gpio82";
2772 function = "gpio";
2773 };
2774
2775 config {
2776 pins = "gpio81", "gpio82";
2777 drive-strength = <2>;
2778 bias-pull-up;
2779 };
2780 };
2781 };
2782
2783 qupv3_se15_spi_pins: qupv3_se15_spi_pins {
2784 qupv3_se15_spi_active: qupv3_se15_spi_active {
2785 mux {
2786 pins = "gpio81", "gpio82", "gpio83",
2787 "gpio84";
2788 function = "qup15";
2789 };
2790
2791 config {
2792 pins = "gpio81", "gpio82", "gpio83",
2793 "gpio84";
2794 drive-strength = <6>;
2795 bias-disable;
2796 };
2797 };
2798
2799 qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
2800 mux {
2801 pins = "gpio81", "gpio82", "gpio83",
2802 "gpio84";
2803 function = "gpio";
2804 };
2805
2806 config {
2807 pins = "gpio81", "gpio82", "gpio83",
2808 "gpio84";
2809 drive-strength = <6>;
2810 bias-disable;
2811 };
2812 };
2813 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002814
2815 cci0_active: cci0_active {
2816 mux {
2817 /* CLK, DATA */
2818 pins = "gpio17","gpio18"; // Only 2
2819 function = "cci_i2c";
2820 };
2821
2822 config {
2823 pins = "gpio17","gpio18";
2824 bias-pull-up; /* PULL UP*/
2825 drive-strength = <2>; /* 2 MA */
2826 };
2827 };
2828
2829 cci0_suspend: cci0_suspend {
2830 mux {
2831 /* CLK, DATA */
2832 pins = "gpio17","gpio18";
2833 function = "cci_i2c";
2834 };
2835
2836 config {
2837 pins = "gpio17","gpio18";
2838 bias-pull-down; /* PULL DOWN */
2839 drive-strength = <2>; /* 2 MA */
2840 };
2841 };
2842
2843 cci1_active: cci1_active {
2844 mux {
2845 /* CLK, DATA */
2846 pins = "gpio19","gpio20";
2847 function = "cci_i2c";
2848 };
2849
2850 config {
2851 pins = "gpio19","gpio20";
2852 bias-pull-up; /* PULL UP*/
2853 drive-strength = <2>; /* 2 MA */
2854 };
2855 };
2856
2857 cci1_suspend: cci1_suspend {
2858 mux {
2859 /* CLK, DATA */
2860 pins = "gpio19","gpio20";
2861 function = "cci_i2c";
2862 };
2863
2864 config {
2865 pins = "gpio19","gpio20";
2866 bias-pull-down; /* PULL DOWN */
2867 drive-strength = <2>; /* 2 MA */
2868 };
2869 };
2870
2871 cam_sensor_mclk0_active: cam_sensor_mclk0_active {
2872 /* MCLK0 */
2873 mux {
2874 pins = "gpio13";
2875 function = "cam_mclk";
2876 };
2877
2878 config {
2879 pins = "gpio13";
2880 bias-disable; /* No PULL */
2881 drive-strength = <2>; /* 2 MA */
2882 };
2883 };
2884
2885 cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
2886 /* MCLK0 */
2887 mux {
2888 pins = "gpio13";
2889 function = "cam_mclk";
2890 };
2891
2892 config {
2893 pins = "gpio13";
2894 bias-pull-down; /* PULL DOWN */
2895 drive-strength = <2>; /* 2 MA */
2896 };
2897 };
2898
2899 cam_sensor_rear_active: cam_sensor_rear_active {
2900 /* RESET, AVDD LDO */
2901 mux {
2902 pins = "gpio80","gpio79";
2903 function = "gpio";
2904 };
2905
2906 config {
2907 pins = "gpio80","gpio79";
2908 bias-disable; /* No PULL */
2909 drive-strength = <2>; /* 2 MA */
2910 };
2911 };
2912
2913 cam_sensor_rear_suspend: cam_sensor_rear_suspend {
2914 /* RESET, AVDD LDO */
2915 mux {
2916 pins = "gpio80","gpio79";
2917 function = "gpio";
2918 };
2919
2920 config {
2921 pins = "gpio80","gpio79";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07002922 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08002923 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07002924 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08002925 };
2926 };
2927
2928 cam_sensor_mclk1_active: cam_sensor_mclk1_active {
2929 /* MCLK1 */
2930 mux {
2931 pins = "gpio14";
2932 function = "cam_mclk";
2933 };
2934
2935 config {
2936 pins = "gpio14";
2937 bias-disable; /* No PULL */
2938 drive-strength = <2>; /* 2 MA */
2939 };
2940 };
2941
2942 cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
2943 /* MCLK1 */
2944 mux {
2945 pins = "gpio14";
2946 function = "cam_mclk";
2947 };
2948
2949 config {
2950 pins = "gpio14";
2951 bias-pull-down; /* PULL DOWN */
2952 drive-strength = <2>; /* 2 MA */
2953 };
2954 };
2955
Jigarkumar Zala9e214912017-09-14 16:40:03 -07002956 cam_sensor_mclk3_active: cam_sensor_mclk3_active {
2957 /* MCLK3 */
2958 mux {
2959 pins = "gpio16";
2960 function = "cam_mclk";
2961 };
2962
2963 config {
2964 pins = "gpio16";
2965 bias-disable; /* No PULL */
2966 drive-strength = <2>; /* 2 MA */
2967 };
2968 };
2969
2970 cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
2971 /* MCLK3 */
2972 mux {
2973 pins = "gpio16";
2974 function = "cam_mclk";
2975 };
2976
2977 config {
2978 pins = "gpio16";
2979 bias-pull-down; /* PULL DOWN */
2980 drive-strength = <2>; /* 2 MA */
2981 };
2982 };
2983
2984
Jigarkumar Zala861231152017-02-28 14:05:11 -08002985 cam_sensor_front_active: cam_sensor_front_active {
2986 /* RESET AVDD_LDO*/
2987 mux {
Jilai Wange0297632017-11-15 18:15:10 -05002988 pins = "gpio28";
Jigarkumar Zala861231152017-02-28 14:05:11 -08002989 function = "gpio";
2990 };
2991
2992 config {
Jilai Wange0297632017-11-15 18:15:10 -05002993 pins = "gpio28";
Jigarkumar Zala861231152017-02-28 14:05:11 -08002994 bias-disable; /* No PULL */
2995 drive-strength = <2>; /* 2 MA */
2996 };
2997 };
2998
2999 cam_sensor_front_suspend: cam_sensor_front_suspend {
3000 /* RESET */
3001 mux {
3002 pins = "gpio28";
3003 function = "gpio";
3004 };
3005
3006 config {
3007 pins = "gpio28";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07003008 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08003009 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07003010 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08003011 };
3012 };
3013
Jigarkumar Zala9e214912017-09-14 16:40:03 -07003014 cam_sensor_iris_active: cam_sensor_iris_active {
3015 /* RESET AVDD_LDO*/
3016 mux {
Jilai Wange0297632017-11-15 18:15:10 -05003017 pins = "gpio9";
Jigarkumar Zala9e214912017-09-14 16:40:03 -07003018 function = "gpio";
3019 };
3020
3021 config {
Jilai Wange0297632017-11-15 18:15:10 -05003022 pins = "gpio9";
Jigarkumar Zala9e214912017-09-14 16:40:03 -07003023 bias-disable; /* No PULL */
3024 drive-strength = <2>; /* 2 MA */
3025 };
3026 };
3027
3028 cam_sensor_iris_suspend: cam_sensor_iris_suspend {
3029 /* RESET */
3030 mux {
3031 pins = "gpio9";
3032 function = "gpio";
3033 };
3034
3035 config {
3036 pins = "gpio9";
3037 bias-disable; /* No PULL */
3038 drive-strength = <2>; /* 2 MA */
3039 output-low;
3040 };
3041 };
3042
3043
Jigarkumar Zala861231152017-02-28 14:05:11 -08003044 cam_sensor_mclk2_active: cam_sensor_mclk2_active {
3045 /* MCLK1 */
3046 mux {
3047 /* CLK, DATA */
3048 pins = "gpio15";
3049 function = "cam_mclk";
3050 };
3051
3052 config {
3053 pins = "gpio15";
3054 bias-disable; /* No PULL */
3055 drive-strength = <2>; /* 2 MA */
3056 };
3057 };
3058
3059 cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
3060 /* MCLK1 */
3061 mux {
3062 /* CLK, DATA */
3063 pins = "gpio15";
3064 function = "cam_mclk";
3065 };
3066
3067 config {
3068 pins = "gpio15";
3069 bias-pull-down; /* PULL DOWN */
3070 drive-strength = <2>; /* 2 MA */
3071 };
3072 };
3073
3074 cam_sensor_rear2_active: cam_sensor_rear2_active {
3075 /* RESET, STANDBY */
3076 mux {
Jilai Wange0297632017-11-15 18:15:10 -05003077 pins = "gpio9";
Jigarkumar Zala861231152017-02-28 14:05:11 -08003078 function = "gpio";
3079 };
3080
3081 config {
Jilai Wange0297632017-11-15 18:15:10 -05003082 pins = "gpio9";
Jigarkumar Zala861231152017-02-28 14:05:11 -08003083 bias-disable; /* No PULL */
3084 drive-strength = <2>; /* 2 MA */
3085 };
3086 };
3087
3088 cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
3089 /* RESET, STANDBY */
3090 mux {
Jilai Wange0297632017-11-15 18:15:10 -05003091 pins = "gpio9";
Jigarkumar Zala861231152017-02-28 14:05:11 -08003092 function = "gpio";
3093 };
3094 config {
Jilai Wange0297632017-11-15 18:15:10 -05003095 pins = "gpio9";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07003096 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08003097 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07003098 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08003099 };
3100 };
Satyajit Desaie4508132017-04-05 17:15:22 -07003101
Jilai Wange0297632017-11-15 18:15:10 -05003102 cam_res_mgr_active: cam_res_mgr_active {
3103 /* AVDD_LDO*/
3104 mux {
3105 pins = "gpio8";
3106 function = "gpio";
3107 };
3108
3109 config {
3110 pins = "gpio8";
3111 bias-disable; /* No PULL */
3112 drive-strength = <2>; /* 2 MA */
3113 };
3114 };
3115
3116 cam_res_mgr_suspend: cam_res_mgr_suspend {
3117 /* AVDD_LDO */
3118 mux {
3119 pins = "gpio8";
3120 function = "gpio";
3121 };
3122
3123 config {
3124 pins = "gpio8";
3125 bias-disable; /* No PULL */
3126 drive-strength = <2>; /* 2 MA */
3127 output-low;
3128 };
3129 };
3130
3131
Satyajit Desaie4508132017-04-05 17:15:22 -07003132 trigout_a: trigout_a {
3133 mux {
Satyajit Desai602a6712017-05-09 14:45:16 -07003134 pins = "gpio90";
Satyajit Desaie4508132017-04-05 17:15:22 -07003135 function = "qdss_cti";
3136 };
3137 config {
Satyajit Desai602a6712017-05-09 14:45:16 -07003138 pins = "gpio90";
Satyajit Desaie4508132017-04-05 17:15:22 -07003139 drive-strength = <2>;
3140 bias-disable;
3141 };
3142 };
Udaya Bhaskara Reddy Mallavarapu55ef0cb2017-06-12 14:45:28 +05303143
3144 tsif0_signals_active: tsif0_signals_active {
3145 tsif1_clk {
3146 pins = "gpio89"; /* TSIF0 CLK */
3147 function = "tsif1_clk";
3148 };
3149 tsif1_en {
3150 pins = "gpio90"; /* TSIF0 Enable */
3151 function = "tsif1_en";
3152 };
3153 tsif1_data {
3154 pins = "gpio91"; /* TSIF0 DATA */
3155 function = "tsif1_data";
3156 };
3157 signals_cfg {
3158 pins = "gpio89", "gpio90", "gpio91";
3159 drive_strength = <2>; /* 2 mA */
3160 bias-pull-down; /* pull down */
3161 };
3162 };
3163
3164 /* sync signal is only used if configured to mode-2 */
3165 tsif0_sync_active: tsif0_sync_active {
3166 tsif1_sync {
3167 pins = "gpio12"; /* TSIF0 SYNC */
3168 function = "tsif1_sync";
3169 drive_strength = <2>; /* 2 mA */
3170 bias-pull-down; /* pull down */
3171 };
3172 };
3173
3174 tsif1_signals_active: tsif1_signals_active {
3175 tsif2_clk {
3176 pins = "gpio93"; /* TSIF1 CLK */
3177 function = "tsif2_clk";
3178 };
3179 tsif2_en {
3180 pins = "gpio94"; /* TSIF1 Enable */
3181 function = "tsif2_en";
3182 };
3183 tsif2_data {
3184 pins = "gpio95"; /* TSIF1 DATA */
3185 function = "tsif2_data";
3186 };
3187 signals_cfg {
3188 pins = "gpio93", "gpio94", "gpio95";
3189 drive_strength = <2>; /* 2 mA */
3190 bias-pull-down; /* pull down */
3191 };
3192 };
3193
3194 /* sync signal is only used if configured to mode-2 */
3195 tsif1_sync_active: tsif1_sync_active {
3196 tsif2_sync {
3197 pins = "gpio96"; /* TSIF1 SYNC */
3198 function = "tsif2_sync";
3199 drive_strength = <2>; /* 2 mA */
3200 bias-pull-down; /* pull down */
3201 };
3202 };
Kyle Yan679cbee2016-07-27 16:55:20 -07003203 };
3204};
David Collinsc6686252017-03-31 14:23:09 -07003205
3206&pm8998_gpios {
3207 key_home {
3208 key_home_default: key_home_default {
3209 pins = "gpio5";
3210 function = "normal";
3211 input-enable;
3212 bias-pull-up;
3213 power-source = <0>;
3214 };
3215 };
3216
3217 key_vol_up {
3218 key_vol_up_default: key_vol_up_default {
3219 pins = "gpio6";
3220 function = "normal";
3221 input-enable;
3222 bias-pull-up;
3223 power-source = <0>;
3224 };
3225 };
3226
3227 key_cam_snapshot {
3228 key_cam_snapshot_default: key_cam_snapshot_default {
3229 pins = "gpio7";
3230 function = "normal";
3231 input-enable;
3232 bias-pull-up;
3233 power-source = <0>;
3234 };
3235 };
3236
3237 key_cam_focus {
3238 key_cam_focus_default: key_cam_focus_default {
3239 pins = "gpio8";
3240 function = "normal";
3241 input-enable;
3242 bias-pull-up;
3243 power-source = <0>;
3244 };
3245 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08003246
3247 camera_dvdd_en {
3248 camera_dvdd_en_default: camera_dvdd_en_default {
3249 pins = "gpio9";
3250 function = "normal";
3251 power-source = <0>;
3252 output-low;
3253 };
3254 };
3255
3256 camera_rear_dvdd_en {
3257 camera_rear_dvdd_en_default: camera_rear_dvdd_en_default {
3258 pins = "gpio12";
3259 function = "normal";
3260 power-source = <0>;
3261 output-low;
3262 };
3263 };
Gaurav Singhal243b94b2017-06-20 14:16:59 +05303264
3265 nfc_clk {
3266 nfc_clk_default: nfc_clk_default {
3267 pins = "gpio21";
3268 function = "normal";
3269 input-enable;
3270 power-source = <1>;
3271 };
3272 };
David Collinsc6686252017-03-31 14:23:09 -07003273};