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gerrit-public.fairphone.software / kernel / msm-4.9 / 87f04358c2fe1bbf8b25790748db095c5f72906e / . / drivers / clk / msm / clock-gcc-8952.c
blob: ed39a8ba777feabc65b32b02df1d12111bc2add1 [file] [log] [blame]
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]1/*
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]2 * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/ctype.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/clk.h>
21#include <linux/regulator/consumer.h>
22#include <linux/platform_device.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <soc/qcom/clock-local2.h>
27#include <soc/qcom/clock-pll.h>
28#include <soc/qcom/clock-alpha-pll.h>
29#include <soc/qcom/clock-voter.h>
30#include <soc/qcom/rpm-smd.h>
31#include <soc/qcom/clock-rpm.h>
32
33#include <linux/clk/msm-clock-generic.h>
34#include <linux/regulator/rpm-smd-regulator.h>
35
36#include <dt-bindings/clock/msm-clocks-8952.h>
37#include <dt-bindings/clock/msm-clocks-hwio-8952.h>
38
39#include "clock.h"
40#include "reset.h"
41
42enum {
43 GCC_BASE,
44 APCS_C1_PLL_BASE,
45 APCS_C0_PLL_BASE,
46 APCS_CCI_PLL_BASE,
47 N_BASES,
48};
49
50static void __iomem *virt_bases[N_BASES];
51#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
52
53static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
54
55/* SMD clocks */
56DEFINE_CLK_RPM_SMD_BRANCH(xo_clk_src, xo_a_clk_src, RPM_MISC_CLK_TYPE,
57 CXO_CLK_SRC_ID, 19200000);
58DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
59DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL);
60DEFINE_CLK_RPM_SMD(bimc_gpu_clk, bimc_gpu_a_clk, RPM_MEM_CLK_TYPE,
61 BIMC_GPU_CLK_ID, NULL);
62DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL);
63DEFINE_CLK_RPM_SMD(sysmmnoc_clk, sysmmnoc_a_clk, RPM_BUS_CLK_TYPE,
64 SYSMMNOC_CLK_ID, NULL);
65DEFINE_CLK_RPM_SMD(ipa_clk, ipa_a_clk, RPM_IPA_CLK_TYPE, IPA_CLK_ID, NULL);
66DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_CLK_ID);
67
68/* SMD_XO_BUFFER */
69DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID);
70DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID);
71DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID);
72DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_a, DIV_CLK2_ID);
73
74DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID);
75DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID);
76
77/* Voter clocks */
78static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
79static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
80static DEFINE_CLK_VOTER(sysmmnoc_msmbus_clk, &sysmmnoc_clk.c, LONG_MAX);
81static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
82
83static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
84static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
85static DEFINE_CLK_VOTER(sysmmnoc_msmbus_a_clk, &sysmmnoc_a_clk.c, LONG_MAX);
86static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
87static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, &pnoc_a_clk.c, LONG_MAX);
88
89static DEFINE_CLK_VOTER(pnoc_usb_a_clk, &pnoc_a_clk.c, LONG_MAX);
90static DEFINE_CLK_VOTER(snoc_usb_a_clk, &snoc_a_clk.c, LONG_MAX);
91static DEFINE_CLK_VOTER(bimc_usb_a_clk, &bimc_a_clk.c, LONG_MAX);
92
93static DEFINE_CLK_VOTER(pnoc_usb_clk, &pnoc_clk.c, LONG_MAX);
94static DEFINE_CLK_VOTER(snoc_usb_clk, &snoc_clk.c, LONG_MAX);
95static DEFINE_CLK_VOTER(bimc_usb_clk, &bimc_clk.c, LONG_MAX);
96
97static DEFINE_CLK_VOTER(snoc_wcnss_a_clk, &snoc_a_clk.c, LONG_MAX);
98static DEFINE_CLK_VOTER(bimc_wcnss_a_clk, &bimc_a_clk.c, LONG_MAX);
99
100/* Branch Voter clocks */
101static DEFINE_CLK_BRANCH_VOTER(xo_gcc, &xo_clk_src.c);
102static DEFINE_CLK_BRANCH_VOTER(xo_otg_clk, &xo_clk_src.c);
103static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo_clk_src.c);
104static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo_clk_src.c);
105static DEFINE_CLK_BRANCH_VOTER(xo_pil_mss_clk, &xo_clk_src.c);
106static DEFINE_CLK_BRANCH_VOTER(xo_wlan_clk, &xo_clk_src.c);
107static DEFINE_CLK_BRANCH_VOTER(xo_pil_lpass_clk, &xo_clk_src.c);
108
109DEFINE_CLK_DUMMY(wcnss_m_clk, 0);
110
111enum vdd_sr2_pll_levels {
112 VDD_SR2_PLL_OFF,
113 VDD_SR2_PLL_SVS,
114 VDD_SR2_PLL_NOM,
115 VDD_SR2_PLL_TUR,
116 VDD_SR2_PLL_SUPER_TUR,
117 VDD_SR2_PLL_NUM,
118};
119
120static int vdd_sr2_levels[] = {
121 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_SR2_PLL_OFF */
122 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_SR2_PLL_SVS */
123 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_SR2_PLL_NOM */
124 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_SR2_PLL_TUR */
125 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_SR2_PLL_SUPER_TUR */
126};
127
128static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
129 vdd_sr2_levels, NULL);
130
131enum vdd_hf_pll_levels {
132 VDD_HF_PLL_OFF,
133 VDD_HF_PLL_SVS,
134 VDD_HF_PLL_NOM,
135 VDD_HF_PLL_TUR,
136 VDD_HF_PLL_SUPER_TUR,
137 VDD_HF_PLL_NUM,
138};
139
140static int vdd_hf_levels[] = {
141 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_HF_PLL_OFF */
142 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_HF_PLL_SVS */
143 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_HF_PLL_NOM */
144 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_HF_PLL_TUR */
145 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_HF_PLL_SUPER_TUR */
146};
147static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2,
148 vdd_hf_levels, NULL);
149
150static struct pll_freq_tbl apcs_cci_pll_freq[] = {
151 F_APCS_PLL(307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
152 F_APCS_PLL(600000000, 31, 0x1, 0x4, 0x0, 0x0, 0x0),
153};
154
155static struct pll_clk a53ss_cci_pll = {
156 .mode_reg = (void __iomem *)APCS_CCI_PLL_MODE,
157 .l_reg = (void __iomem *)APCS_CCI_PLL_L_VAL,
158 .m_reg = (void __iomem *)APCS_CCI_PLL_M_VAL,
159 .n_reg = (void __iomem *)APCS_CCI_PLL_N_VAL,
160 .config_reg = (void __iomem *)APCS_CCI_PLL_USER_CTL,
161 .status_reg = (void __iomem *)APCS_CCI_PLL_STATUS,
162 .freq_tbl = apcs_cci_pll_freq,
163 .masks = {
164 .vco_mask = BM(29, 28),
165 .pre_div_mask = BIT(12),
166 .post_div_mask = BM(9, 8),
167 .mn_en_mask = BIT(24),
168 .main_output_mask = BIT(0),
169 },
170 .base = &virt_bases[APCS_CCI_PLL_BASE],
171 .spm_ctrl = {
172 .offset = 0x40,
173 .event_bit = 0x0,
174 },
175 .c = {
176 .parent = &xo_a_clk_src.c,
177 .dbg_name = "a53ss_cci_pll",
178 .ops = &clk_ops_sr2_pll,
179 .vdd_class = &vdd_sr2_pll,
180 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
181 [VDD_SR2_PLL_SVS] = 1000000000,
182 [VDD_SR2_PLL_NOM] = 1900000000,
183 },
184 .num_fmax = VDD_SR2_PLL_NUM,
185 CLK_INIT(a53ss_cci_pll.c),
186 },
187};
188
189static struct pll_freq_tbl apcs_c0_pll_freq[] = {
190 F_APCS_PLL( 249600000, 13, 0x0, 0x1, 0x0, 0x0, 0x0),
191 F_APCS_PLL( 307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
192 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
193 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
194 F_APCS_PLL( 460800000, 24, 0x0, 0x1, 0x0, 0x0, 0x0),
195 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
196 F_APCS_PLL( 518400000, 27, 0x0, 0x1, 0x0, 0x0, 0x0),
197 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
198 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
199 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
200 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
201 F_APCS_PLL( 902400000, 47, 0x0, 0x1, 0x0, 0x0, 0x0),
202 F_APCS_PLL( 921600000, 48, 0x0, 0x1, 0x0, 0x0, 0x0),
203 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
204 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]205 F_APCS_PLL(1171200000, 61, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]206 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]207 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
208 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]209};
210
211static struct pll_clk a53ss_c0_pll = {
212 .mode_reg = (void __iomem *)APCS_C0_PLL_MODE,
213 .l_reg = (void __iomem *)APCS_C0_PLL_L_VAL,
214 .m_reg = (void __iomem *)APCS_C0_PLL_M_VAL,
215 .n_reg = (void __iomem *)APCS_C0_PLL_N_VAL,
216 .config_reg = (void __iomem *)APCS_C0_PLL_USER_CTL,
217 .status_reg = (void __iomem *)APCS_C0_PLL_STATUS,
218 .freq_tbl = apcs_c0_pll_freq,
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]219 .config_ctl_reg = (void __iomem *)APCS_C0_PLL_CONFIG_CTL,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]220 .masks = {
221 .vco_mask = BM(29, 28),
222 .pre_div_mask = BIT(12),
223 .post_div_mask = BM(9, 8),
224 .mn_en_mask = BIT(24),
225 .main_output_mask = BIT(0),
226 },
227 .base = &virt_bases[APCS_C0_PLL_BASE],
228 .spm_ctrl = {
229 .offset = 0x50,
230 .event_bit = 0x4,
231 },
232 .c = {
233 .parent = &xo_a_clk_src.c,
234 .dbg_name = "a53ss_c0_pll",
235 .ops = &clk_ops_sr2_pll,
236 .vdd_class = &vdd_sr2_pll,
237 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
238 [VDD_SR2_PLL_SVS] = 1000000000,
239 [VDD_SR2_PLL_NOM] = 1900000000,
240 },
241 .num_fmax = VDD_SR2_PLL_NUM,
242 CLK_INIT(a53ss_c0_pll.c),
243 },
244};
245
246static struct pll_freq_tbl apcs_c1_pll_freq[] = {
247 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
248 F_APCS_PLL( 422400000, 22, 0x0, 0x1, 0x0, 0x0, 0x0),
249 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
250 F_APCS_PLL( 652800000, 34, 0x0, 0x1, 0x0, 0x0, 0x0),
251 F_APCS_PLL( 729600000, 38, 0x0, 0x1, 0x0, 0x0, 0x0),
252 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
253 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
254 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
255 F_APCS_PLL( 960000000, 50, 0x0, 0x1, 0x0, 0x0, 0x0),
256 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
257 F_APCS_PLL(1036800000, 54, 0x0, 0x1, 0x0, 0x0, 0x0),
258 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
259 F_APCS_PLL(1113600000, 58, 0x0, 0x1, 0x0, 0x0, 0x0),
260 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
261 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
262 F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
263 F_APCS_PLL(1267200000, 66, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]264 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]265 F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
266 F_APCS_PLL(1401000000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
267 F_APCS_PLL(1420800000, 74, 0x0, 0x1, 0x0, 0x0, 0x0),
268 F_APCS_PLL(1440000000, 75, 0x0, 0x1, 0x0, 0x0, 0x0),
269 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
270 F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
271 F_APCS_PLL(1516800000, 79, 0x0, 0x1, 0x0, 0x0, 0x0),
272 F_APCS_PLL(1536000000, 80, 0x0, 0x1, 0x0, 0x0, 0x0),
273 F_APCS_PLL(1651200000, 86, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]274 F_APCS_PLL(1708800000, 89, 0x0, 0x1, 0x0, 0x0, 0x0),
275 F_APCS_PLL(1804800000, 94, 0x0, 0x1, 0x0, 0x0, 0x0),
276 F_APCS_PLL(1958400000, 102, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatladb8f4672018-11-02 10:48:42 +0530[diff] [blame]277 F_APCS_PLL(2016000000, 105, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]278};
279
280static struct pll_clk a53ss_c1_pll = {
281 .mode_reg = (void __iomem *)APCS_C1_PLL_MODE,
282 .l_reg = (void __iomem *)APCS_C1_PLL_L_VAL,
283 .m_reg = (void __iomem *)APCS_C1_PLL_M_VAL,
284 .n_reg = (void __iomem *)APCS_C1_PLL_N_VAL,
285 .config_reg = (void __iomem *)APCS_C1_PLL_USER_CTL,
286 .status_reg = (void __iomem *)APCS_C1_PLL_STATUS,
287 .freq_tbl = apcs_c1_pll_freq,
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]288 .config_ctl_reg = (void __iomem *)APCS_C1_PLL_CONFIG_CTL,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]289 .masks = {
290 .vco_mask = BM(29, 28),
291 .pre_div_mask = BIT(12),
292 .post_div_mask = BM(9, 8),
293 .mn_en_mask = BIT(24),
294 .main_output_mask = BIT(0),
295 },
296 .base = &virt_bases[APCS_C1_PLL_BASE],
297 .spm_ctrl = {
298 .offset = 0x50,
299 .event_bit = 0x4,
300 },
301 .c = {
302 .parent = &xo_a_clk_src.c,
303 .dbg_name = "a53ss_c1_pll",
304 .ops = &clk_ops_sr2_pll,
305 .vdd_class = &vdd_hf_pll,
306 .fmax = (unsigned long [VDD_HF_PLL_NUM]) {
307 [VDD_HF_PLL_SVS] = 1000000000,
Odelu Kukatladb8f4672018-11-02 10:48:42 +0530[diff] [blame]308 [VDD_HF_PLL_NOM] = 2020000000,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]309 },
310 .num_fmax = VDD_HF_PLL_NUM,
311 CLK_INIT(a53ss_c1_pll.c),
312 },
313};
314
315static struct pll_vote_clk gpll0_sleep_clk_src = {
316 .en_reg = (void __iomem *)APCS_CLOCK_SLEEP_ENA_VOTE,
317 .en_mask = BIT(23),
318 .status_reg = (void __iomem *)GPLL0_MODE,
319 .status_mask = BIT(30),
320 .base = &virt_bases[GCC_BASE],
321 .c = {
322 .parent = &xo_clk_src.c,
323 .rate = 800000000,
324 .dbg_name = "gpll0_sleep_clk_src",
325 .ops = &clk_ops_pll_sleep_vote,
326 CLK_INIT(gpll0_sleep_clk_src.c),
327 },
328};
329
330static unsigned int soft_vote_gpll0;
331
332/* PLL_ACTIVE_FLAG bit of GCC_GPLL0_MODE register
333 * gets set from PLL voting FSM.It indicates when
334 * FSM has enabled the PLL and PLL should be locked.
335 */
336static struct pll_vote_clk gpll0_clk_src_8952 = {
337 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
338 .en_mask = BIT(0),
339 .status_reg = (void __iomem *)GPLL0_STATUS,
340 .status_mask = BIT(17),
341 .soft_vote = &soft_vote_gpll0,
342 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
343 .base = &virt_bases[GCC_BASE],
344 .c = {
345 .parent = &xo_clk_src.c,
346 .rate = 800000000,
347 .dbg_name = "gpll0_clk_src_8952",
348 .ops = &clk_ops_pll_acpu_vote,
349 CLK_INIT(gpll0_clk_src_8952.c),
350 },
351};
352
353static struct pll_vote_clk gpll0_clk_src_8937 = {
354 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
355 .en_mask = BIT(0),
356 .status_reg = (void __iomem *)GPLL0_MODE,
357 .status_mask = BIT(30),
358 .soft_vote = &soft_vote_gpll0,
359 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
360 .base = &virt_bases[GCC_BASE],
361 .c = {
362 .parent = &gpll0_sleep_clk_src.c,
363 .rate = 800000000,
364 .dbg_name = "gpll0_clk_src_8937",
365 .ops = &clk_ops_pll_acpu_vote,
366 CLK_INIT(gpll0_clk_src_8937.c),
367 },
368};
369
370DEFINE_EXT_CLK(gpll0_clk_src, NULL);
371DEFINE_EXT_CLK(gpll0_ao_clk_src, NULL);
372DEFINE_EXT_CLK(gpll0_out_aux_clk_src, &gpll0_clk_src.c);
373DEFINE_EXT_CLK(gpll0_out_main_clk_src, &gpll0_clk_src.c);
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]374DEFINE_EXT_CLK(gpll0_gfx_clk_src, &gpll0_clk_src.c);
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]375DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
376DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);
377DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);
378DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);
379
380/* Don't vote for xo if using this clock to allow xo shutdown */
381static struct pll_vote_clk gpll0_ao_clk_src_8952 = {
382 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
383 .en_mask = BIT(0),
384 .status_reg = (void __iomem *)GPLL0_STATUS,
385 .status_mask = BIT(17),
386 .soft_vote = &soft_vote_gpll0,
387 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
388 .base = &virt_bases[GCC_BASE],
389 .c = {
390 .parent = &xo_a_clk_src.c,
391 .rate = 800000000,
392 .dbg_name = "gpll0_ao_clk_src_8952",
393 .ops = &clk_ops_pll_acpu_vote,
394 CLK_INIT(gpll0_ao_clk_src_8952.c),
395 },
396};
397
398static struct pll_vote_clk gpll0_ao_clk_src_8937 = {
399 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
400 .en_mask = BIT(0),
401 .status_reg = (void __iomem *)GPLL0_MODE,
402 .status_mask = BIT(30),
403 .soft_vote = &soft_vote_gpll0,
404 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
405 .base = &virt_bases[GCC_BASE],
406 .c = {
407 .parent = &xo_a_clk_src.c,
408 .rate = 800000000,
409 .dbg_name = "gpll0_ao_clk_src_8937",
410 .ops = &clk_ops_pll_acpu_vote,
411 CLK_INIT(gpll0_ao_clk_src_8937.c),
412 },
413};
414
415static struct pll_vote_clk gpll6_clk_src = {
416 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
417 .en_mask = BIT(7),
418 .status_reg = (void __iomem *)GPLL6_STATUS,
419 .status_mask = BIT(17),
420 .base = &virt_bases[GCC_BASE],
421 .c = {
422 .parent = &xo_clk_src.c,
423 .rate = 1080000000,
424 .dbg_name = "gpll6_clk_src",
425 .ops = &clk_ops_pll_vote,
426 CLK_INIT(gpll6_clk_src.c),
427 },
428};
429
430DEFINE_EXT_CLK(gpll6_aux_clk_src, &gpll6_clk_src.c);
431DEFINE_EXT_CLK(gpll6_out_main_clk_src, &gpll6_clk_src.c);
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]432DEFINE_EXT_CLK(gpll6_gfx_clk_src, &gpll6_clk_src.c);
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]433
434static struct alpha_pll_masks pll_masks_p = {
435 .lock_mask = BIT(31),
436 .active_mask = BIT(30),
437 .vco_mask = BM(21, 20) >> 20,
438 .vco_shift = 20,
439 .alpha_en_mask = BIT(24),
440 .output_mask = 0xf,
441 .update_mask = BIT(22),
442 .post_div_mask = BM(11, 8),
443 .test_ctl_lo_mask = BM(31, 0),
444 .test_ctl_hi_mask = BM(31, 0),
445};
446
447/* Slewing plls won't allow to change vco_sel.
448 * Hence will have only one vco table entry
449 */
450static struct alpha_pll_vco_tbl p_vco[] = {
451 VCO(0, 700000000, 1400000000),
452};
453
454/* Slewing plls won't allow to change vco_sel.
455 * Hence will have only one vco table entry
456 */
457static struct alpha_pll_vco_tbl p_vco_8937[] = {
458 VCO(1, 525000000, 1066000000),
459};
460
461static struct alpha_pll_clk gpll3_clk_src = {
462 .masks = &pll_masks_p,
463 .base = &virt_bases[GCC_BASE],
464 .offset = GPLL3_MODE,
465 .vco_tbl = p_vco,
466 .num_vco = ARRAY_SIZE(p_vco),
467 .enable_config = 1,
468 /*
469 * gpll3 is dedicated to oxili and has a fuse implementation for
470 * post divider to limit frequency. HW with fuse blown has a divider
471 * value set to 2. So lets stick to divide by 2 in software to avoid
472 * conflicts.
473 */
474 .post_div_config = 1 << 8,
475 .slew = true,
476 .config_ctl_val = 0x4001055b,
477 .test_ctl_hi_val = 0x40000600,
478 .c = {
479 .rate = 1050000000,
480 .parent = &xo_clk_src.c,
481 .dbg_name = "gpll3_clk_src",
482 .ops = &clk_ops_dyna_alpha_pll,
483 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
484 CLK_INIT(gpll3_clk_src.c),
485 },
486};
487
488static struct pll_vote_clk gpll4_clk_src = {
489 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
490 .en_mask = BIT(5),
491 .status_reg = (void __iomem *)GPLL4_MODE,
492 .status_mask = BIT(30),
493 .base = &virt_bases[GCC_BASE],
494 .c = {
495 .rate = 1152000000,
496 .parent = &xo_clk_src.c,
497 .dbg_name = "gpll4_clk_src",
498 .ops = &clk_ops_pll_vote,
499 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
500 CLK_INIT(gpll4_clk_src.c),
501 },
502};
503DEFINE_EXT_CLK(gpll4_out_clk_src, &gpll4_clk_src.c);
504
505static struct clk_freq_tbl ftbl_gcc_camss_top_ahb_clk[] = {
506 F( 40000000, gpll0, 10, 1, 2),
507 F( 61540000, gpll0, 13, 0, 0),
508 F( 80000000, gpll0, 10, 0, 0),
509 F_END
510};
511
512static struct rcg_clk camss_top_ahb_clk_src = {
513 .cmd_rcgr_reg = CAMSS_TOP_AHB_CMD_RCGR,
514 .set_rate = set_rate_mnd,
515 .freq_tbl = ftbl_gcc_camss_top_ahb_clk,
516 .current_freq = &rcg_dummy_freq,
517 .base = &virt_bases[GCC_BASE],
518 .c = {
519 .dbg_name = "camss_top_ahb_clk_src",
520 .ops = &clk_ops_rcg_mnd,
521 VDD_DIG_FMAX_MAP3(LOWER, 40000000, LOW, 61540000,
522 NOMINAL, 80000000),
523 CLK_INIT(camss_top_ahb_clk_src.c),
524 },
525};
526
527static struct clk_freq_tbl ftbl_gcc_apss_ahb_clk[] = {
528 F( 19200000, xo_a, 1, 0, 0),
529 F( 50000000, gpll0, 16, 0, 0),
530 F( 100000000, gpll0, 8, 0, 0),
531 F( 133330000, gpll0, 6, 0, 0),
532 F_END
533};
534
535static struct rcg_clk apss_ahb_clk_src = {
536 .cmd_rcgr_reg = APSS_AHB_CMD_RCGR,
537 .set_rate = set_rate_hid,
538 .freq_tbl = ftbl_gcc_apss_ahb_clk,
539 .current_freq = &rcg_dummy_freq,
540 .base = &virt_bases[GCC_BASE],
541 .c = {
542 .dbg_name = "apss_ahb_clk_src",
543 .ops = &clk_ops_rcg,
544 CLK_INIT(apss_ahb_clk_src.c),
545 },
546};
547
548static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk[] = {
549 F( 100000000, gpll0, 8, 0, 0),
550 F( 160000000, gpll0, 5, 0, 0),
551 F( 200000000, gpll0, 4, 0, 0),
552 F_END
553};
554
555static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk_8937[] = {
556 F( 100000000, gpll0, 8, 0, 0),
557 F( 160000000, gpll0, 5, 0, 0),
558 F( 200000000, gpll0, 4, 0, 0),
559 F( 266670000, gpll0, 3, 0, 0),
560 F_END
561};
562
563
564static struct rcg_clk csi0_clk_src = {
565 .cmd_rcgr_reg = CSI0_CMD_RCGR,
566 .set_rate = set_rate_hid,
567 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
568 .current_freq = &rcg_dummy_freq,
569 .base = &virt_bases[GCC_BASE],
570 .c = {
571 .dbg_name = "csi0_clk_src",
572 .ops = &clk_ops_rcg,
573 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
574 NOMINAL, 200000000),
575 CLK_INIT(csi0_clk_src.c),
576 },
577};
578
579static struct rcg_clk csi1_clk_src = {
580 .cmd_rcgr_reg = CSI1_CMD_RCGR,
581 .set_rate = set_rate_hid,
582 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
583 .current_freq = &rcg_dummy_freq,
584 .base = &virt_bases[GCC_BASE],
585 .c = {
586 .dbg_name = "csi1_clk_src",
587 .ops = &clk_ops_rcg,
588 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
589 NOMINAL, 200000000),
590 CLK_INIT(csi1_clk_src.c),
591 },
592};
593
594static struct rcg_clk csi2_clk_src = {
595 .cmd_rcgr_reg = CSI2_CMD_RCGR,
596 .set_rate = set_rate_hid,
597 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
598 .current_freq = &rcg_dummy_freq,
599 .base = &virt_bases[GCC_BASE],
600 .c = {
601 .dbg_name = "csi2_clk_src",
602 .ops = &clk_ops_rcg,
603 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
604 NOMINAL, 200000000),
605 CLK_INIT(csi2_clk_src.c),
606 },
607};
608
609static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
610 F( 133330000, gpll0, 6, 0, 0),
611 F( 180000000, gpll6, 6, 0, 0),
612 F( 228570000, gpll0, 3.5, 0, 0),
613 F( 266670000, gpll0, 3, 0, 0),
614 F( 308570000, gpll6, 3.5, 0, 0),
615 F_END
616};
617
618static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8937[] = {
619 F( 166150000, gpll6, 6.5, 0, 0),
620 F( 240000000, gpll6, 4.5, 0, 0),
621 F( 308570000, gpll6, 3.5, 0, 0),
622 F( 320000000, gpll0, 2.5, 0, 0),
623 F( 360000000, gpll6, 3, 0, 0),
624 F_END
625};
626
627static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8917[] = {
628 F( 160000000, gpll0, 5, 0, 0),
629 F( 200000000, gpll0, 4, 0, 0),
630 F( 270000000, gpll6, 4, 0, 0),
631 F( 308570000, gpll6, 3.5, 0, 0),
632 F( 329140000, gpll4_out, 3.5, 0, 0),
633 F( 360000000, gpll6, 3, 0, 0),
634 F_END
635};
636
637static struct rcg_clk vcodec0_clk_src = {
638 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
639 .set_rate = set_rate_mnd,
640 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
641 .current_freq = &rcg_dummy_freq,
642 .base = &virt_bases[GCC_BASE],
643 .c = {
644 .dbg_name = "vcodec0_clk_src",
645 .ops = &clk_ops_rcg_mnd,
646 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
647 NOMINAL, 228570000, NOM_PLUS, 266670000,
648 HIGH, 308570000),
649 CLK_INIT(vcodec0_clk_src.c),
650 },
651};
652
653static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk[] = {
654 F( 50000000, gpll0, 16, 0, 0),
655 F( 80000000, gpll0, 10, 0, 0),
656 F( 100000000, gpll0, 8, 0, 0),
657 F( 133330000, gpll0, 6, 0, 0),
658 F( 160000000, gpll0, 5, 0, 0),
659 F( 177780000, gpll0, 4.5, 0, 0),
660 F( 200000000, gpll0, 4, 0, 0),
661 F( 266670000, gpll0, 3, 0, 0),
662 F( 308570000, gpll6, 3.5, 0, 0),
663 F( 320000000, gpll0, 2.5, 0, 0),
664 F( 360000000, gpll6, 3, 0, 0),
665 F_END
666};
667
668static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8937[] = {
669 F( 50000000, gpll0, 16, 0, 0),
670 F( 80000000, gpll0, 10, 0, 0),
671 F( 100000000, gpll0, 8, 0, 0),
672 F( 133333333, gpll0, 6, 0, 0),
673 F( 160000000, gpll0, 5, 0, 0),
674 F( 177780000, gpll0, 4.5, 0, 0),
675 F( 200000000, gpll0, 4, 0, 0),
676 F( 266670000, gpll0, 3, 0, 0),
677 F( 308570000, gpll6, 3.5, 0, 0),
678 F( 320000000, gpll0, 2.5, 0, 0),
679 F( 360000000, gpll6, 3, 0, 0),
680 F( 400000000, gpll0, 2, 0, 0),
681 F( 432000000, gpll6, 2.5, 0, 0),
682 F_END
683};
684
685static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8917[] = {
686 F( 50000000, gpll0, 16, 0, 0),
687 F( 80000000, gpll0, 10, 0, 0),
688 F( 100000000, gpll0, 8, 0, 0),
689 F( 133333333, gpll0, 6, 0, 0),
690 F( 160000000, gpll0, 5, 0, 0),
691 F( 177780000, gpll0, 4.5, 0, 0),
692 F( 200000000, gpll0, 4, 0, 0),
693 F( 266670000, gpll0, 3, 0, 0),
694 F( 308570000, gpll6, 3.5, 0, 0),
695 F( 320000000, gpll0, 2.5, 0, 0),
696 F( 329140000, gpll4_out, 3.5, 0, 0),
697 F( 360000000, gpll6, 3, 0, 0),
698 F_END
699};
700
701static struct rcg_clk vfe0_clk_src = {
702 .cmd_rcgr_reg = VFE0_CMD_RCGR,
703 .set_rate = set_rate_hid,
704 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
705 .current_freq = &rcg_dummy_freq,
706 .base = &virt_bases[GCC_BASE],
707 .c = {
708 .dbg_name = "vfe0_clk_src",
709 .ops = &clk_ops_rcg,
710 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
711 NOMINAL, 308570000, NOM_PLUS, 320000000,
712 HIGH, 360000000),
713 CLK_INIT(vfe0_clk_src.c),
714 },
715};
716
717static struct rcg_clk vfe1_clk_src = {
718 .cmd_rcgr_reg = VFE1_CMD_RCGR,
719 .set_rate = set_rate_hid,
720 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
721 .current_freq = &rcg_dummy_freq,
722 .base = &virt_bases[GCC_BASE],
723 .c = {
724 .dbg_name = "vfe1_clk_src",
725 .ops = &clk_ops_rcg,
726 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
727 NOMINAL, 308570000, NOM_PLUS, 320000000,
728 HIGH, 360000000),
729 CLK_INIT(vfe1_clk_src.c),
730 },
731};
732
733static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
734 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
735 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
736 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
737 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
738 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
739 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
740 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
741 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
742 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
743 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
744 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
745 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
746 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
747 F_END
748};
749
750static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937[] = {
751 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
752 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
753 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
754 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
755 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
756 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
757 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
758 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
759 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
760 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
761 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
762 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
763 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
764 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
765 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
766 F_END
767};
768
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]769static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_sdm439[] = {
770 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
771 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
772 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
773 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
774 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
775 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
776 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
777 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
778 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
779 F_SLEW( 259200000, 1296000000, gpll3, 2.5, 0, 0),
780 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
781 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
782 F_SLEW( 355200000, 710400000, gpll3, 1, 0, 0),
783 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
784 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
785 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
786 F_SLEW( 510000000, 1020000000, gpll3, 1, 0, 0),
787 F_SLEW( 560000000, 1120000000, gpll3, 1, 0, 0),
788 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
789 F_END
790};
791
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]792static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937_475MHz[] = {
793 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
794 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
795 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
796 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
797 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
798 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
799 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
800 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
801 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
802 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
803 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
804 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
805 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
806 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
807 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
808 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
809 F_END
810};
811
812static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8940_500MHz[] = {
813 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
814 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
815 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
816 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
817 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
818 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
819 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
820 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
821 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
822 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
823 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
824 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
825 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
826 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
827 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
828 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
829 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
830 F_END
831};
832
833static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917[] = {
834 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
835 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
836 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
837 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
838 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
839 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
840 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
841 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
842 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
843 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
844 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
845 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
Odelu Kukatla9c000582018-09-25 18:55:09 +0530[diff] [blame]846 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]847 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
Odelu Kukatla6110fc32018-12-11 16:48:03 +0530[diff] [blame]848 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]849 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
850 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
851 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
852 F_END
853};
854
855static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917_650MHz[] = {
856 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
857 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
858 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
859 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
860 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
861 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
862 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
863 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
864 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
865 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
866 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
867 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
Odelu Kukatla9c000582018-09-25 18:55:09 +0530[diff] [blame]868 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]869 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
Odelu Kukatla6110fc32018-12-11 16:48:03 +0530[diff] [blame]870 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]871 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
872 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
873 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
874 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
875 F_END
876};
877
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]878static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_qm215[] = {
879 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
880 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0_gfx, 16, 0, 0),
881 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0_gfx, 10, 0, 0),
882 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0_gfx, 8, 0, 0),
883 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0_gfx, 5, 0, 0),
884 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0_gfx, 4, 0, 0),
885 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0_gfx, 3.5, 0, 0),
886 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_gfx, 4.5, 0, 0),
887 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0_gfx, 3, 0, 0),
888 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_gfx, 4, 0, 0),
889 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0_gfx, 2.5, 0, 0),
890 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0_gfx, 2, 0, 0),
891 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
892 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
893 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
894 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
895 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
896 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
897 F_END
898};
899
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]900static struct rcg_clk gfx3d_clk_src = {
901 .cmd_rcgr_reg = GFX3D_CMD_RCGR,
902 .set_rate = set_rate_hid,
903 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
904 .current_freq = &rcg_dummy_freq,
905 .base = &virt_bases[GCC_BASE],
906 .c = {
907 .dbg_name = "gfx3d_clk_src",
908 .ops = &clk_ops_rcg,
909 VDD_DIG_FMAX_MAP5(LOWER, 240000000, LOW, 400000000,
910 NOMINAL, 465000000, NOM_PLUS, 500000000,
911 HIGH, 550000000),
912 CLK_INIT(gfx3d_clk_src.c),
913 },
914};
915
916static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk[] = {
917 F( 19200000, xo, 1, 0, 0),
918 F( 50000000, gpll0, 16, 0, 0),
919 F_END
920};
921
922static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
923 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
924 .set_rate = set_rate_hid,
925 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
926 .current_freq = &rcg_dummy_freq,
927 .base = &virt_bases[GCC_BASE],
928 .c = {
929 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
930 .ops = &clk_ops_rcg,
931 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
932 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
933 },
934};
935
936static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk[] = {
937 F( 960000, xo, 10, 1, 2),
938 F( 4800000, xo, 4, 0, 0),
939 F( 9600000, xo, 2, 0, 0),
940 F( 16000000, gpll0, 10, 1, 5),
941 F( 19200000, xo, 1, 0, 0),
942 F( 25000000, gpll0, 16, 1, 2),
943 F( 50000000, gpll0, 16, 0, 0),
944 F_END
945};
946
947static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917[] = {
948 F( 960000, xo, 10, 1, 2),
949 F( 4800000, xo, 4, 0, 0),
950 F( 9600000, xo, 2, 0, 0),
951 F( 16000000, gpll0, 10, 1, 5),
952 F( 19200000, xo, 1, 0, 0),
953 F( 25000000, gpll0, 16, 1, 2),
954 F( 40000000, gpll0, 10, 1, 2),
955 F( 50000000, gpll0, 16, 0, 0),
956 F_END
957};
958
959static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
960 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
961 .set_rate = set_rate_mnd,
962 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
963 .current_freq = &rcg_dummy_freq,
964 .base = &virt_bases[GCC_BASE],
965 .c = {
966 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
967 .ops = &clk_ops_rcg_mnd,
968 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
969 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
970 },
971};
972
973static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
974 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
975 .set_rate = set_rate_hid,
976 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
977 .current_freq = &rcg_dummy_freq,
978 .base = &virt_bases[GCC_BASE],
979 .c = {
980 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
981 .ops = &clk_ops_rcg,
982 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
983 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
984 },
985};
986
987static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
988 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
989 .set_rate = set_rate_mnd,
990 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
991 .current_freq = &rcg_dummy_freq,
992 .base = &virt_bases[GCC_BASE],
993 .c = {
994 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
995 .ops = &clk_ops_rcg_mnd,
996 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
997 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
998 },
999};
1000
1001static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
1002 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
1003 .set_rate = set_rate_hid,
1004 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1005 .current_freq = &rcg_dummy_freq,
1006 .base = &virt_bases[GCC_BASE],
1007 .c = {
1008 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
1009 .ops = &clk_ops_rcg,
1010 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1011 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
1012 },
1013};
1014
1015static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
1016 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
1017 .set_rate = set_rate_mnd,
1018 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1019 .current_freq = &rcg_dummy_freq,
1020 .base = &virt_bases[GCC_BASE],
1021 .c = {
1022 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
1023 .ops = &clk_ops_rcg_mnd,
1024 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1025 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
1026 },
1027};
1028
1029static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
1030 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
1031 .set_rate = set_rate_hid,
1032 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1033 .current_freq = &rcg_dummy_freq,
1034 .base = &virt_bases[GCC_BASE],
1035 .c = {
1036 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
1037 .ops = &clk_ops_rcg,
1038 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1039 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
1040 },
1041};
1042
1043static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
1044 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
1045 .set_rate = set_rate_mnd,
1046 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1047 .current_freq = &rcg_dummy_freq,
1048 .base = &virt_bases[GCC_BASE],
1049 .c = {
1050 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
1051 .ops = &clk_ops_rcg_mnd,
1052 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1053 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
1054 },
1055};
1056
1057static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = {
1058 F( 3686400, gpll0, 1, 72, 15625),
1059 F( 7372800, gpll0, 1, 144, 15625),
1060 F( 14745600, gpll0, 1, 288, 15625),
1061 F( 16000000, gpll0, 10, 1, 5),
1062 F( 19200000, xo, 1, 0, 0),
1063 F( 24000000, gpll0, 1, 3, 100),
1064 F( 25000000, gpll0, 16, 1, 2),
1065 F( 32000000, gpll0, 1, 1, 25),
1066 F( 40000000, gpll0, 1, 1, 20),
1067 F( 46400000, gpll0, 1, 29, 500),
1068 F( 48000000, gpll0, 1, 3, 50),
1069 F( 51200000, gpll0, 1, 8, 125),
1070 F( 56000000, gpll0, 1, 7, 100),
1071 F( 58982400, gpll0, 1, 1152, 15625),
1072 F( 60000000, gpll0, 1, 3, 40),
1073 F( 64000000, gpll0, 1, 2, 25),
1074 F_END
1075};
1076
1077static struct rcg_clk blsp1_uart1_apps_clk_src = {
1078 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
1079 .set_rate = set_rate_mnd,
1080 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1081 .current_freq = &rcg_dummy_freq,
1082 .base = &virt_bases[GCC_BASE],
1083 .c = {
1084 .dbg_name = "blsp1_uart1_apps_clk_src",
1085 .ops = &clk_ops_rcg_mnd,
1086 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1087 CLK_INIT(blsp1_uart1_apps_clk_src.c),
1088 },
1089};
1090
1091static struct rcg_clk blsp1_uart2_apps_clk_src = {
1092 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
1093 .set_rate = set_rate_mnd,
1094 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1095 .current_freq = &rcg_dummy_freq,
1096 .base = &virt_bases[GCC_BASE],
1097 .c = {
1098 .dbg_name = "blsp1_uart2_apps_clk_src",
1099 .ops = &clk_ops_rcg_mnd,
1100 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1101 CLK_INIT(blsp1_uart2_apps_clk_src.c),
1102 },
1103};
1104
1105static struct rcg_clk blsp2_qup1_i2c_apps_clk_src = {
1106 .cmd_rcgr_reg = BLSP2_QUP1_I2C_APPS_CMD_RCGR,
1107 .set_rate = set_rate_hid,
1108 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1109 .current_freq = &rcg_dummy_freq,
1110 .base = &virt_bases[GCC_BASE],
1111 .c = {
1112 .dbg_name = "blsp2_qup1_i2c_apps_clk_src",
1113 .ops = &clk_ops_rcg,
1114 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1115 CLK_INIT(blsp2_qup1_i2c_apps_clk_src.c),
1116 },
1117};
1118
1119static struct rcg_clk blsp2_qup1_spi_apps_clk_src = {
1120 .cmd_rcgr_reg = BLSP2_QUP1_SPI_APPS_CMD_RCGR,
1121 .set_rate = set_rate_mnd,
1122 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1123 .current_freq = &rcg_dummy_freq,
1124 .base = &virt_bases[GCC_BASE],
1125 .c = {
1126 .dbg_name = "blsp2_qup1_spi_apps_clk_src",
1127 .ops = &clk_ops_rcg_mnd,
1128 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1129 CLK_INIT(blsp2_qup1_spi_apps_clk_src.c),
1130 },
1131};
1132
1133static struct rcg_clk blsp2_qup2_i2c_apps_clk_src = {
1134 .cmd_rcgr_reg = BLSP2_QUP2_I2C_APPS_CMD_RCGR,
1135 .set_rate = set_rate_hid,
1136 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1137 .current_freq = &rcg_dummy_freq,
1138 .base = &virt_bases[GCC_BASE],
1139 .c = {
1140 .dbg_name = "blsp2_qup2_i2c_apps_clk_src",
1141 .ops = &clk_ops_rcg,
1142 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1143 CLK_INIT(blsp2_qup2_i2c_apps_clk_src.c),
1144 },
1145};
1146
1147static struct rcg_clk blsp2_qup2_spi_apps_clk_src = {
1148 .cmd_rcgr_reg = BLSP2_QUP2_SPI_APPS_CMD_RCGR,
1149 .set_rate = set_rate_mnd,
1150 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1151 .current_freq = &rcg_dummy_freq,
1152 .base = &virt_bases[GCC_BASE],
1153 .c = {
1154 .dbg_name = "blsp2_qup2_spi_apps_clk_src",
1155 .ops = &clk_ops_rcg_mnd,
1156 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1157 CLK_INIT(blsp2_qup2_spi_apps_clk_src.c),
1158 },
1159};
1160
1161static struct rcg_clk blsp2_qup3_i2c_apps_clk_src = {
1162 .cmd_rcgr_reg = BLSP2_QUP3_I2C_APPS_CMD_RCGR,
1163 .set_rate = set_rate_hid,
1164 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1165 .current_freq = &rcg_dummy_freq,
1166 .base = &virt_bases[GCC_BASE],
1167 .c = {
1168 .dbg_name = "blsp2_qup3_i2c_apps_clk_src",
1169 .ops = &clk_ops_rcg,
1170 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1171 CLK_INIT(blsp2_qup3_i2c_apps_clk_src.c),
1172 },
1173};
1174
1175static struct rcg_clk blsp2_qup3_spi_apps_clk_src = {
1176 .cmd_rcgr_reg = BLSP2_QUP3_SPI_APPS_CMD_RCGR,
1177 .set_rate = set_rate_mnd,
1178 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1179 .current_freq = &rcg_dummy_freq,
1180 .base = &virt_bases[GCC_BASE],
1181 .c = {
1182 .dbg_name = "blsp2_qup3_spi_apps_clk_src",
1183 .ops = &clk_ops_rcg_mnd,
1184 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1185 CLK_INIT(blsp2_qup3_spi_apps_clk_src.c),
1186 },
1187};
1188
1189static struct rcg_clk blsp2_qup4_i2c_apps_clk_src = {
1190 .cmd_rcgr_reg = BLSP2_QUP4_I2C_APPS_CMD_RCGR,
1191 .set_rate = set_rate_hid,
1192 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1193 .current_freq = &rcg_dummy_freq,
1194 .base = &virt_bases[GCC_BASE],
1195 .c = {
1196 .dbg_name = "blsp2_qup4_i2c_apps_clk_src",
1197 .ops = &clk_ops_rcg,
1198 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1199 CLK_INIT(blsp2_qup4_i2c_apps_clk_src.c),
1200 },
1201};
1202
1203static struct rcg_clk blsp2_qup4_spi_apps_clk_src = {
1204 .cmd_rcgr_reg = BLSP2_QUP4_SPI_APPS_CMD_RCGR,
1205 .set_rate = set_rate_mnd,
1206 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1207 .current_freq = &rcg_dummy_freq,
1208 .base = &virt_bases[GCC_BASE],
1209 .c = {
1210 .dbg_name = "blsp2_qup4_spi_apps_clk_src",
1211 .ops = &clk_ops_rcg_mnd,
1212 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1213 CLK_INIT(blsp2_qup4_spi_apps_clk_src.c),
1214 },
1215};
1216
1217static struct rcg_clk blsp2_uart1_apps_clk_src = {
1218 .cmd_rcgr_reg = BLSP2_UART1_APPS_CMD_RCGR,
1219 .set_rate = set_rate_mnd,
1220 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1221 .current_freq = &rcg_dummy_freq,
1222 .base = &virt_bases[GCC_BASE],
1223 .c = {
1224 .dbg_name = "blsp2_uart1_apps_clk_src",
1225 .ops = &clk_ops_rcg_mnd,
1226 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1227 CLK_INIT(blsp2_uart1_apps_clk_src.c),
1228 },
1229};
1230
1231static struct rcg_clk blsp2_uart2_apps_clk_src = {
1232 .cmd_rcgr_reg = BLSP2_UART2_APPS_CMD_RCGR,
1233 .set_rate = set_rate_mnd,
1234 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1235 .current_freq = &rcg_dummy_freq,
1236 .base = &virt_bases[GCC_BASE],
1237 .c = {
1238 .dbg_name = "blsp2_uart2_apps_clk_src",
1239 .ops = &clk_ops_rcg_mnd,
1240 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1241 CLK_INIT(blsp2_uart2_apps_clk_src.c),
1242 },
1243};
1244
1245static struct clk_freq_tbl ftbl_gcc_camss_cci_clk[] = {
1246 F( 19200000, xo, 1, 0, 0),
1247 F( 37500000, gpll0_out_aux, 1, 3, 64),
1248 F_END
1249};
1250
1251static struct rcg_clk cci_clk_src = {
1252 .cmd_rcgr_reg = CCI_CMD_RCGR,
1253 .set_rate = set_rate_mnd,
1254 .freq_tbl = ftbl_gcc_camss_cci_clk,
1255 .current_freq = &rcg_dummy_freq,
1256 .base = &virt_bases[GCC_BASE],
1257 .c = {
1258 .dbg_name = "cci_clk_src",
1259 .ops = &clk_ops_rcg_mnd,
1260 VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 37500000),
1261 CLK_INIT(cci_clk_src.c),
1262 },
1263};
1264
1265static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1266 F( 133330000, gpll0, 6, 0, 0),
1267 F( 180000000, gpll6, 6, 0, 0),
1268 F( 266670000, gpll0, 3, 0, 0),
1269 F( 308570000, gpll6, 3.5, 0, 0),
1270 F( 320000000, gpll0, 2.5, 0, 0),
1271 F_END
1272};
1273
1274static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8937[] = {
1275 F( 133333333, gpll0, 6, 0, 0),
1276 F( 160000000, gpll0, 5, 0, 0),
1277 F( 200000000, gpll0, 4, 0, 0),
1278 F( 266666667, gpll0, 3, 0, 0),
1279 F( 308570000, gpll6, 3.5, 0, 0),
1280 F( 320000000, gpll0, 2.5, 0, 0),
1281 F( 360000000, gpll6, 3, 0, 0),
1282 F_END
1283};
1284
1285static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8917[] = {
1286 F( 133330000, gpll0, 6, 0, 0),
1287 F( 160000000, gpll0, 5, 0, 0),
1288 F( 266670000, gpll0, 3, 0, 0),
1289 F( 308570000, gpll6, 3.5, 0, 0),
1290 F( 320000000, gpll0, 2.5, 0, 0),
1291 F( 360000000, gpll6, 3, 0, 0),
1292 F_END
1293};
1294
1295static struct rcg_clk cpp_clk_src = {
1296 .cmd_rcgr_reg = CPP_CMD_RCGR,
1297 .set_rate = set_rate_hid,
1298 .freq_tbl = ftbl_gcc_camss_cpp_clk,
1299 .current_freq = &rcg_dummy_freq,
1300 .base = &virt_bases[GCC_BASE],
1301 .c = {
1302 .dbg_name = "cpp_clk_src",
1303 .ops = &clk_ops_rcg,
1304 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
1305 NOMINAL, 266670000, NOM_PLUS, 308570000,
1306 HIGH, 320000000),
1307 CLK_INIT(cpp_clk_src.c),
1308 },
1309};
1310
1311static struct clk_freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1312 F( 100000000, gpll0, 8, 0, 0),
1313 F( 160000000, gpll0, 5, 0, 0),
1314 F( 200000000, gpll0, 4, 0, 0),
1315 F_END
1316};
1317
1318static struct rcg_clk camss_gp0_clk_src = {
1319 .cmd_rcgr_reg = MM_GP0_CMD_RCGR,
1320 .set_rate = set_rate_mnd,
1321 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1322 .current_freq = &rcg_dummy_freq,
1323 .base = &virt_bases[GCC_BASE],
1324 .c = {
1325 .dbg_name = "camss_gp0_clk_src",
1326 .ops = &clk_ops_rcg_mnd,
1327 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1328 NOMINAL, 200000000),
1329 CLK_INIT(camss_gp0_clk_src.c),
1330 },
1331};
1332
1333static struct rcg_clk camss_gp1_clk_src = {
1334 .cmd_rcgr_reg = MM_GP1_CMD_RCGR,
1335 .set_rate = set_rate_mnd,
1336 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1337 .current_freq = &rcg_dummy_freq,
1338 .base = &virt_bases[GCC_BASE],
1339 .c = {
1340 .dbg_name = "camss_gp1_clk_src",
1341 .ops = &clk_ops_rcg_mnd,
1342 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1343 NOMINAL, 200000000),
1344 CLK_INIT(camss_gp1_clk_src.c),
1345 },
1346};
1347
1348static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1349 F( 133330000, gpll0, 6, 0, 0),
1350 F( 266670000, gpll0, 3, 0, 0),
1351 F( 320000000, gpll0, 2.5, 0, 0),
1352 F_END
1353};
1354
1355static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk_8937[] = {
1356 F( 133333333, gpll0, 6, 0, 0),
1357 F( 200000000, gpll0, 4, 0, 0),
1358 F( 266666667, gpll0, 3, 0, 0),
1359 F( 308570000, gpll6, 3.5, 0, 0),
1360 F( 320000000, gpll0, 2.5, 0, 0),
1361 F_END
1362};
1363
1364static struct rcg_clk jpeg0_clk_src = {
1365 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1366 .set_rate = set_rate_hid,
1367 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1368 .current_freq = &rcg_dummy_freq,
1369 .base = &virt_bases[GCC_BASE],
1370 .c = {
1371 .dbg_name = "jpeg0_clk_src",
1372 .ops = &clk_ops_rcg,
1373 VDD_DIG_FMAX_MAP3(LOWER, 133330000, NOMINAL, 266670000,
1374 HIGH, 320000000),
1375 CLK_INIT(jpeg0_clk_src.c),
1376 },
1377};
1378
1379static struct clk_freq_tbl ftbl_gcc_camss_mclk0_2_clk[] = {
1380 F( 19200000, xo, 1, 0, 0),
1381 F( 24000000, gpll6, 1, 1, 45),
1382 F( 66670000, gpll0, 12, 0, 0),
1383 F_END
1384};
1385
1386static struct rcg_clk mclk0_clk_src = {
1387 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1388 .set_rate = set_rate_mnd,
1389 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1390 .current_freq = &rcg_dummy_freq,
1391 .base = &virt_bases[GCC_BASE],
1392 .c = {
1393 .dbg_name = "mclk0_clk_src",
1394 .ops = &clk_ops_rcg_mnd,
1395 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1396 CLK_INIT(mclk0_clk_src.c),
1397 },
1398};
1399
1400static struct rcg_clk mclk1_clk_src = {
1401 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1402 .set_rate = set_rate_mnd,
1403 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1404 .current_freq = &rcg_dummy_freq,
1405 .base = &virt_bases[GCC_BASE],
1406 .c = {
1407 .dbg_name = "mclk1_clk_src",
1408 .ops = &clk_ops_rcg_mnd,
1409 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1410 CLK_INIT(mclk1_clk_src.c),
1411 },
1412};
1413
1414static struct rcg_clk mclk2_clk_src = {
1415 .cmd_rcgr_reg = MCLK2_CMD_RCGR,
1416 .set_rate = set_rate_mnd,
1417 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1418 .current_freq = &rcg_dummy_freq,
1419 .base = &virt_bases[GCC_BASE],
1420 .c = {
1421 .dbg_name = "mclk2_clk_src",
1422 .ops = &clk_ops_rcg_mnd,
1423 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1424 CLK_INIT(mclk2_clk_src.c),
1425 },
1426};
1427
1428static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1429 F( 100000000, gpll0, 8, 0, 0),
1430 F( 160000000, gpll0, 5, 0, 0),
1431 F( 200000000, gpll0, 4, 0, 0),
1432 F_END
1433};
1434
1435static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk_8917[] = {
1436 F( 100000000, gpll0, 8, 0, 0),
1437 F( 160000000, gpll0, 5, 0, 0),
1438 F( 200000000, gpll0, 4, 0, 0),
1439 F( 266670000, gpll0, 3, 0, 0),
1440 F_END
1441};
1442
1443static struct rcg_clk csi0phytimer_clk_src = {
1444 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1445 .set_rate = set_rate_hid,
1446 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1447 .current_freq = &rcg_dummy_freq,
1448 .base = &virt_bases[GCC_BASE],
1449 .c = {
1450 .dbg_name = "csi0phytimer_clk_src",
1451 .ops = &clk_ops_rcg,
1452 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1453 NOMINAL, 200000000),
1454 CLK_INIT(csi0phytimer_clk_src.c),
1455 },
1456};
1457
1458static struct rcg_clk csi1phytimer_clk_src = {
1459 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1460 .set_rate = set_rate_hid,
1461 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1462 .current_freq = &rcg_dummy_freq,
1463 .base = &virt_bases[GCC_BASE],
1464 .c = {
1465 .dbg_name = "csi1phytimer_clk_src",
1466 .ops = &clk_ops_rcg,
1467 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1468 NOMINAL, 200000000),
1469 CLK_INIT(csi1phytimer_clk_src.c),
1470 },
1471};
1472
1473static struct clk_freq_tbl ftbl_gcc_crypto_clk[] = {
1474 F( 50000000, gpll0, 16, 0, 0),
1475 F( 80000000, gpll0, 10, 0, 0),
1476 F( 100000000, gpll0, 8, 0, 0),
1477 F( 160000000, gpll0, 5, 0, 0),
1478 F_END
1479};
1480
1481static struct rcg_clk crypto_clk_src = {
1482 .cmd_rcgr_reg = CRYPTO_CMD_RCGR,
1483 .set_rate = set_rate_hid,
1484 .freq_tbl = ftbl_gcc_crypto_clk,
1485 .current_freq = &rcg_dummy_freq,
1486 .base = &virt_bases[GCC_BASE],
1487 .c = {
1488 .dbg_name = "crypto_clk_src",
1489 .ops = &clk_ops_rcg,
1490 VDD_DIG_FMAX_MAP2(LOWER, 80000000, NOMINAL, 160000000),
1491 CLK_INIT(crypto_clk_src.c),
1492 },
1493};
1494
1495static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
1496 F( 19200000, xo, 1, 0, 0),
1497 F_END
1498};
1499
1500static struct rcg_clk gp1_clk_src = {
1501 .cmd_rcgr_reg = GP1_CMD_RCGR,
1502 .set_rate = set_rate_mnd,
1503 .freq_tbl = ftbl_gcc_gp1_3_clk,
1504 .current_freq = &rcg_dummy_freq,
1505 .base = &virt_bases[GCC_BASE],
1506 .c = {
1507 .dbg_name = "gp1_clk_src",
1508 .ops = &clk_ops_rcg_mnd,
1509 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1510 CLK_INIT(gp1_clk_src.c),
1511 },
1512};
1513
1514static struct rcg_clk gp2_clk_src = {
1515 .cmd_rcgr_reg = GP2_CMD_RCGR,
1516 .set_rate = set_rate_mnd,
1517 .freq_tbl = ftbl_gcc_gp1_3_clk,
1518 .current_freq = &rcg_dummy_freq,
1519 .base = &virt_bases[GCC_BASE],
1520 .c = {
1521 .dbg_name = "gp2_clk_src",
1522 .ops = &clk_ops_rcg_mnd,
1523 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1524 CLK_INIT(gp2_clk_src.c),
1525 },
1526};
1527
1528static struct rcg_clk gp3_clk_src = {
1529 .cmd_rcgr_reg = GP3_CMD_RCGR,
1530 .set_rate = set_rate_mnd,
1531 .freq_tbl = ftbl_gcc_gp1_3_clk,
1532 .current_freq = &rcg_dummy_freq,
1533 .base = &virt_bases[GCC_BASE],
1534 .c = {
1535 .dbg_name = "gp3_clk_src",
1536 .ops = &clk_ops_rcg_mnd,
1537 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1538 CLK_INIT(gp3_clk_src.c),
1539 },
1540};
1541
1542static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
1543 {
1544 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1545 | BVAL(4, 0, 0),
1546 .src_clk = &ext_byte0_clk_src.c,
1547 .freq_hz = 0,
1548 },
1549 F_END
1550};
1551
1552static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk_8937[] = {
1553 {
1554 .div_src_val = BVAL(10, 8, xo_source_val)
1555 | BVAL(4, 0, 0),
1556 .src_clk = &xo_clk_src.c,
1557 .freq_hz = 0,
1558 },
1559 {
1560 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1561 | BVAL(4, 0, 0),
1562 .src_clk = &ext_byte0_clk_src.c,
1563 .freq_hz = 0,
1564 },
1565 {
1566 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1567 | BVAL(4, 0, 0),
1568 .src_clk = &ext_byte1_clk_src.c,
1569 .freq_hz = 0,
1570 },
1571 F_END
1572};
1573
1574static struct rcg_clk byte0_clk_src = {
1575 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
1576 .set_rate = set_rate_hid,
1577 .current_freq = ftbl_gcc_mdss_byte0_clk,
1578 .freq_tbl = ftbl_gcc_mdss_byte0_clk,
1579 .base = &virt_bases[GCC_BASE],
1580 .c = {
1581 .dbg_name = "byte0_clk_src",
1582 .ops = &clk_ops_byte_multiparent,
1583 .flags = CLKFLAG_NO_RATE_CACHE,
1584 VDD_DIG_FMAX_MAP2(LOWER, 120000000, NOMINAL, 187500000),
1585 CLK_INIT(byte0_clk_src.c),
1586 },
1587};
1588
1589static struct clk_freq_tbl ftbl_gcc_mdss_byte1_clk[] = {
1590 {
1591 .div_src_val = BVAL(10, 8, xo_source_val)
1592 | BVAL(4, 0, 0),
1593 .src_clk = &xo_clk_src.c,
1594 .freq_hz = 0,
1595 },
1596 {
1597 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1598 | BVAL(4, 0, 0),
1599 .src_clk = &ext_byte1_clk_src.c,
1600 .freq_hz = 0,
1601 },
1602 {
1603 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1604 | BVAL(4, 0, 0),
1605 .src_clk = &ext_byte0_clk_src.c,
1606 .freq_hz = 0,
1607 },
1608 F_END
1609};
1610
1611static struct rcg_clk byte1_clk_src = {
1612 .cmd_rcgr_reg = BYTE1_CMD_RCGR,
1613 .set_rate = set_rate_hid,
1614 .current_freq = ftbl_gcc_mdss_byte1_clk,
1615 .freq_tbl = ftbl_gcc_mdss_byte1_clk,
1616 .base = &virt_bases[GCC_BASE],
1617 .c = {
1618 .dbg_name = "byte1_clk_src",
1619 .ops = &clk_ops_byte_multiparent,
1620 .flags = CLKFLAG_NO_RATE_CACHE,
1621 VDD_DIG_FMAX_MAP2(LOWER, 125000000, NOMINAL, 187500000),
1622 CLK_INIT(byte1_clk_src.c),
1623 },
1624};
1625
1626static struct clk_freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
1627 F( 19200000, xo, 1, 0, 0),
1628 F_END
1629};
1630
1631static struct rcg_clk esc0_clk_src = {
1632 .cmd_rcgr_reg = ESC0_CMD_RCGR,
1633 .set_rate = set_rate_hid,
1634 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
1635 .current_freq = &rcg_dummy_freq,
1636 .base = &virt_bases[GCC_BASE],
1637 .c = {
1638 .dbg_name = "esc0_clk_src",
1639 .ops = &clk_ops_rcg,
1640 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1641 CLK_INIT(esc0_clk_src.c),
1642 },
1643};
1644
1645static struct clk_freq_tbl ftbl_esc1_clk_src[] = {
1646 F( 19200000, xo, 1, 0, 0),
1647 F_END
1648};
1649
1650static struct rcg_clk esc1_clk_src = {
1651 .cmd_rcgr_reg = ESC1_CMD_RCGR,
1652 .set_rate = set_rate_hid,
1653 .freq_tbl = ftbl_esc1_clk_src,
1654 .current_freq = &rcg_dummy_freq,
1655 .base = &virt_bases[GCC_BASE],
1656 .c = {
1657 .dbg_name = "esc1_clk_src",
1658 .ops = &clk_ops_rcg,
1659 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1660 CLK_INIT(esc1_clk_src.c),
1661 },
1662};
1663
1664static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1665 F( 50000000, gpll0, 16, 0, 0),
1666 F( 80000000, gpll0, 10, 0, 0),
1667 F( 100000000, gpll0, 8, 0, 0),
1668 F( 145450000, gpll0, 5.5, 0, 0),
1669 F( 160000000, gpll0, 5, 0, 0),
1670 F( 177780000, gpll0, 4.5, 0, 0),
1671 F( 200000000, gpll0, 4, 0, 0),
1672 F( 266670000, gpll0, 3, 0, 0),
1673 F( 320000000, gpll0, 2.5, 0, 0),
1674 F_END
1675};
1676
1677static struct rcg_clk mdp_clk_src = {
1678 .cmd_rcgr_reg = MDP_CMD_RCGR,
1679 .set_rate = set_rate_hid,
1680 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1681 .current_freq = &rcg_dummy_freq,
1682 .base = &virt_bases[GCC_BASE],
1683 .c = {
1684 .dbg_name = "mdp_clk_src",
1685 .ops = &clk_ops_rcg,
1686 VDD_DIG_FMAX_MAP3(LOWER, 160000000, NOMINAL, 266670000,
1687 HIGH, 320000000),
1688 CLK_INIT(mdp_clk_src.c),
1689 },
1690};
1691
1692static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk[] = {
1693 {
1694 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1695 | BVAL(4, 0, 0),
1696 .src_clk = &ext_pclk0_clk_src.c,
1697 .freq_hz = 0,
1698 },
1699 F_END
1700};
1701
1702static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk_8937[] = {
1703 {
1704 .div_src_val = BVAL(10, 8, xo_source_val)
1705 | BVAL(4, 0, 0),
1706 .src_clk = &xo_clk_src.c,
1707 .freq_hz = 0,
1708 },
1709 {
1710 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1711 | BVAL(4, 0, 0),
1712 .src_clk = &ext_pclk0_clk_src.c,
1713 .freq_hz = 0,
1714 },
1715 {
1716 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1717 | BVAL(4, 0, 0),
1718 .src_clk = &ext_pclk1_clk_src.c,
1719 .freq_hz = 0,
1720 },
1721 F_END
1722};
1723
1724static struct rcg_clk pclk0_clk_src = {
1725 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
1726 .set_rate = set_rate_mnd,
1727 .current_freq = ftbl_gcc_mdss_pclk0_clk,
1728 .freq_tbl = ftbl_gcc_mdss_pclk0_clk,
1729 .base = &virt_bases[GCC_BASE],
1730 .c = {
1731 .dbg_name = "pclk0_clk_src",
1732 .ops = &clk_ops_pixel_multiparent,
1733 VDD_DIG_FMAX_MAP2(LOWER, 160000000, NOMINAL, 250000000),
1734 .flags = CLKFLAG_NO_RATE_CACHE,
1735 CLK_INIT(pclk0_clk_src.c),
1736 },
1737};
1738
1739static struct clk_freq_tbl ftbl_gcc_mdss_pclk1_clk[] = {
1740 {
1741 .div_src_val = BVAL(10, 8, xo_source_val)
1742 | BVAL(4, 0, 0),
1743 .src_clk = &xo_clk_src.c,
1744 .freq_hz = 0,
1745 },
1746 {
1747 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1748 | BVAL(4, 0, 0),
1749 .src_clk = &ext_pclk1_clk_src.c,
1750 .freq_hz = 0,
1751 },
1752 {
1753 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1754 | BVAL(4, 0, 0),
1755 .src_clk = &ext_pclk0_clk_src.c,
1756 .freq_hz = 0,
1757 },
1758 F_END
1759};
1760
1761static struct rcg_clk pclk1_clk_src = {
1762 .cmd_rcgr_reg = PCLK1_CMD_RCGR,
1763 .set_rate = set_rate_mnd,
1764 .current_freq = ftbl_gcc_mdss_pclk1_clk,
1765 .freq_tbl = ftbl_gcc_mdss_pclk1_clk,
1766 .base = &virt_bases[GCC_BASE],
1767 .c = {
1768 .dbg_name = "pclk1_clk_src",
1769 .ops = &clk_ops_pixel_multiparent,
1770 .flags = CLKFLAG_NO_RATE_CACHE,
1771 VDD_DIG_FMAX_MAP2(LOWER, 166670000, NOMINAL, 250000000),
1772 CLK_INIT(pclk1_clk_src.c),
1773 },
1774};
1775
1776static struct clk_freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1777 F( 19200000, xo, 1, 0, 0),
1778 F_END
1779};
1780
1781static struct rcg_clk vsync_clk_src = {
1782 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
1783 .set_rate = set_rate_hid,
1784 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1785 .current_freq = &rcg_dummy_freq,
1786 .base = &virt_bases[GCC_BASE],
1787 .c = {
1788 .dbg_name = "vsync_clk_src",
1789 .ops = &clk_ops_rcg,
1790 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1791 CLK_INIT(vsync_clk_src.c),
1792 },
1793};
1794
1795static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
1796 F( 64000000, gpll0, 12.5, 0, 0),
1797 F_END
1798};
1799
1800static struct rcg_clk pdm2_clk_src = {
1801 .cmd_rcgr_reg = PDM2_CMD_RCGR,
1802 .set_rate = set_rate_hid,
1803 .freq_tbl = ftbl_gcc_pdm2_clk,
1804 .current_freq = &rcg_dummy_freq,
1805 .base = &virt_bases[GCC_BASE],
1806 .c = {
1807 .dbg_name = "pdm2_clk_src",
1808 .ops = &clk_ops_rcg,
1809 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1810 CLK_INIT(pdm2_clk_src.c),
1811 },
1812};
1813
1814static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1815 F( 144000, xo, 16, 3, 25),
1816 F( 400000, xo, 12, 1, 4),
1817 F( 20000000, gpll0, 10, 1, 4),
1818 F( 25000000, gpll0, 16, 1, 2),
1819 F( 50000000, gpll0, 16, 0, 0),
1820 F( 100000000, gpll0, 8, 0, 0),
1821 F( 177770000, gpll0, 4.5, 0, 0),
1822 F( 192000000, gpll4, 6, 0, 0),
1823 F( 200000000, gpll0, 4, 0, 0),
1824 F( 384000000, gpll4, 3, 0, 0),
1825 F_END
1826};
1827
1828static struct rcg_clk sdcc1_apps_clk_src = {
1829 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
1830 .set_rate = set_rate_mnd,
1831 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1832 .current_freq = &rcg_dummy_freq,
1833 .base = &virt_bases[GCC_BASE],
1834 .c = {
1835 .dbg_name = "sdcc1_apps_clk_src",
1836 .ops = &clk_ops_rcg_mnd,
1837 VDD_DIG_FMAX_MAP2(LOWER, 50000000, NOMINAL, 384000000),
1838 CLK_INIT(sdcc1_apps_clk_src.c),
1839 },
1840};
1841
1842static struct clk_freq_tbl ftbl_gcc_sdcc1_ice_core_clk[] = {
1843 F( 100000000, gpll0_out_main, 8, 0, 0),
1844 F( 200000000, gpll0_out_main, 4, 0, 0),
1845 F_END
1846};
1847
1848static struct rcg_clk sdcc1_ice_core_clk_src = {
1849 .cmd_rcgr_reg = SDCC1_ICE_CORE_CMD_RCGR,
1850 .set_rate = set_rate_mnd,
1851 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk,
1852 .current_freq = &rcg_dummy_freq,
1853 .base = &virt_bases[GCC_BASE],
1854 .c = {
1855 .dbg_name = "sdcc1_ice_core_clk_src",
1856 .ops = &clk_ops_rcg_mnd,
1857 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1858 CLK_INIT(sdcc1_ice_core_clk_src.c),
1859 },
1860};
1861
1862static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1863 F( 144000, xo, 16, 3, 25),
1864 F( 400000, xo, 12, 1, 4),
1865 F( 20000000, gpll0, 10, 1, 4),
1866 F( 25000000, gpll0, 16, 1, 2),
1867 F( 50000000, gpll0, 16, 0, 0),
1868 F( 100000000, gpll0, 8, 0, 0),
1869 F( 177770000, gpll0, 4.5, 0, 0),
1870 F( 200000000, gpll0, 4, 0, 0),
1871 F_END
1872};
1873
1874static struct rcg_clk sdcc2_apps_clk_src = {
1875 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
1876 .set_rate = set_rate_mnd,
1877 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1878 .current_freq = &rcg_dummy_freq,
1879 .base = &virt_bases[GCC_BASE],
1880 .c = {
1881 .dbg_name = "sdcc2_apps_clk_src",
1882 .ops = &clk_ops_rcg_mnd,
1883 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1884 CLK_INIT(sdcc2_apps_clk_src.c),
1885 },
1886};
1887
1888static struct clk_freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1889 F( 60000000, gpll6_out_main, 9, 1, 2),
1890 F_END
1891};
1892
1893static struct rcg_clk usb_fs_ic_clk_src = {
1894 .cmd_rcgr_reg = USB_FS_IC_CMD_RCGR,
1895 .set_rate = set_rate_mnd,
1896 .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1897 .current_freq = &rcg_dummy_freq,
1898 .base = &virt_bases[GCC_BASE],
1899 .c = {
1900 .dbg_name = "usb_fs_ic_clk_src",
1901 .ops = &clk_ops_rcg_mnd,
1902 VDD_DIG_FMAX_MAP1(LOWER, 60000000),
1903 CLK_INIT(usb_fs_ic_clk_src.c),
1904 },
1905};
1906
1907static struct clk_freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1908 F( 64000000, gpll0_out_aux, 12.5, 0, 0),
1909 F_END
1910};
1911
1912static struct rcg_clk usb_fs_system_clk_src = {
1913 .cmd_rcgr_reg = USB_FS_SYSTEM_CMD_RCGR,
1914 .set_rate = set_rate_mnd,
1915 .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1916 .current_freq = &rcg_dummy_freq,
1917 .base = &virt_bases[GCC_BASE],
1918 .c = {
1919 .dbg_name = "usb_fs_system_clk_src",
1920 .ops = &clk_ops_rcg_mnd,
1921 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1922 CLK_INIT(usb_fs_system_clk_src.c),
1923 },
1924};
1925
1926static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1927 F( 57140000, gpll0, 14, 0, 0),
1928 F( 100000000, gpll0, 8, 0, 0),
1929 F( 133330000, gpll0, 6, 0, 0),
1930 F( 177780000, gpll0, 4.5, 0, 0),
1931 F_END
1932};
1933
1934static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk_8917[] = {
1935 F( 80000000, gpll0, 10, 0, 0),
1936 F( 100000000, gpll0, 8, 0, 0),
1937 F( 133330000, gpll0, 6, 0, 0),
1938 F( 177780000, gpll0, 4.5, 0, 0),
1939 F_END
1940};
1941
1942static struct rcg_clk usb_hs_system_clk_src = {
1943 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
1944 .set_rate = set_rate_hid,
1945 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1946 .current_freq = &rcg_dummy_freq,
1947 .base = &virt_bases[GCC_BASE],
1948 .c = {
1949 .dbg_name = "usb_hs_system_clk_src",
1950 .ops = &clk_ops_rcg,
1951 VDD_DIG_FMAX_MAP3(LOWER, 57140000, NOMINAL, 133330000,
1952 HIGH, 177780000),
1953 CLK_INIT(usb_hs_system_clk_src.c),
1954 },
1955};
1956
1957static struct branch_clk gcc_bimc_gpu_clk = {
1958 .cbcr_reg = BIMC_GPU_CBCR,
1959 .has_sibling = 1,
1960 .base = &virt_bases[GCC_BASE],
1961 .c = {
1962 .dbg_name = "gcc_bimc_gpu_clk",
1963 .ops = &clk_ops_branch,
1964 CLK_INIT(gcc_bimc_gpu_clk.c),
1965 },
1966};
1967
1968static struct branch_clk gcc_dcc_clk = {
1969 .cbcr_reg = DCC_CBCR,
1970 .has_sibling = 1,
1971 .base = &virt_bases[GCC_BASE],
1972 .c = {
1973 .dbg_name = "gcc_dcc_clk",
1974 .ops = &clk_ops_branch,
1975 CLK_INIT(gcc_dcc_clk.c),
1976 },
1977};
1978
1979static struct local_vote_clk gcc_blsp1_ahb_clk = {
1980 .cbcr_reg = BLSP1_AHB_CBCR,
1981 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1982 .en_mask = BIT(10),
1983 .base = &virt_bases[GCC_BASE],
1984 .c = {
1985 .dbg_name = "gcc_blsp1_ahb_clk",
1986 .ops = &clk_ops_vote,
1987 CLK_INIT(gcc_blsp1_ahb_clk.c),
1988 },
1989};
1990
1991static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1992 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1993 .has_sibling = 0,
1994 .base = &virt_bases[GCC_BASE],
1995 .c = {
1996 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1997 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1998 .ops = &clk_ops_branch,
1999 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
2000 },
2001};
2002
2003static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
2004 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
2005 .has_sibling = 0,
2006 .base = &virt_bases[GCC_BASE],
2007 .c = {
2008 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
2009 .parent = &blsp1_qup1_spi_apps_clk_src.c,
2010 .ops = &clk_ops_branch,
2011 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
2012 },
2013};
2014
2015static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
2016 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
2017 .has_sibling = 0,
2018 .base = &virt_bases[GCC_BASE],
2019 .c = {
2020 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
2021 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
2022 .ops = &clk_ops_branch,
2023 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
2024 },
2025};
2026
2027static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
2028 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
2029 .has_sibling = 0,
2030 .base = &virt_bases[GCC_BASE],
2031 .c = {
2032 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
2033 .parent = &blsp1_qup2_spi_apps_clk_src.c,
2034 .ops = &clk_ops_branch,
2035 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
2036 },
2037};
2038
2039static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
2040 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
2041 .has_sibling = 0,
2042 .base = &virt_bases[GCC_BASE],
2043 .c = {
2044 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
2045 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
2046 .ops = &clk_ops_branch,
2047 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
2048 },
2049};
2050
2051static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
2052 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
2053 .has_sibling = 0,
2054 .base = &virt_bases[GCC_BASE],
2055 .c = {
2056 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
2057 .parent = &blsp1_qup3_spi_apps_clk_src.c,
2058 .ops = &clk_ops_branch,
2059 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
2060 },
2061};
2062
2063static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
2064 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
2065 .has_sibling = 0,
2066 .base = &virt_bases[GCC_BASE],
2067 .c = {
2068 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
2069 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
2070 .ops = &clk_ops_branch,
2071 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
2072 },
2073};
2074
2075static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
2076 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
2077 .has_sibling = 0,
2078 .base = &virt_bases[GCC_BASE],
2079 .c = {
2080 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
2081 .parent = &blsp1_qup4_spi_apps_clk_src.c,
2082 .ops = &clk_ops_branch,
2083 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
2084 },
2085};
2086
2087static struct branch_clk gcc_blsp1_uart1_apps_clk = {
2088 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
2089 .has_sibling = 0,
2090 .base = &virt_bases[GCC_BASE],
2091 .c = {
2092 .dbg_name = "gcc_blsp1_uart1_apps_clk",
2093 .parent = &blsp1_uart1_apps_clk_src.c,
2094 .ops = &clk_ops_branch,
2095 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
2096 },
2097};
2098
2099static struct branch_clk gcc_blsp1_uart2_apps_clk = {
2100 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
2101 .has_sibling = 0,
2102 .base = &virt_bases[GCC_BASE],
2103 .c = {
2104 .dbg_name = "gcc_blsp1_uart2_apps_clk",
2105 .parent = &blsp1_uart2_apps_clk_src.c,
2106 .ops = &clk_ops_branch,
2107 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
2108 },
2109};
2110
2111static struct local_vote_clk gcc_blsp2_ahb_clk = {
2112 .cbcr_reg = BLSP2_AHB_CBCR,
2113 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2114 .en_mask = BIT(20),
2115 .base = &virt_bases[GCC_BASE],
2116 .c = {
2117 .dbg_name = "gcc_blsp2_ahb_clk",
2118 .ops = &clk_ops_vote,
2119 CLK_INIT(gcc_blsp2_ahb_clk.c),
2120 },
2121};
2122
2123static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = {
2124 .cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR,
2125 .has_sibling = 0,
2126 .base = &virt_bases[GCC_BASE],
2127 .c = {
2128 .dbg_name = "gcc_blsp2_qup1_i2c_apps_clk",
2129 .parent = &blsp2_qup1_i2c_apps_clk_src.c,
2130 .ops = &clk_ops_branch,
2131 CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c),
2132 },
2133};
2134
2135static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = {
2136 .cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR,
2137 .has_sibling = 0,
2138 .base = &virt_bases[GCC_BASE],
2139 .c = {
2140 .dbg_name = "gcc_blsp2_qup1_spi_apps_clk",
2141 .parent = &blsp2_qup1_spi_apps_clk_src.c,
2142 .ops = &clk_ops_branch,
2143 CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c),
2144 },
2145};
2146
2147static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = {
2148 .cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR,
2149 .has_sibling = 0,
2150 .base = &virt_bases[GCC_BASE],
2151 .c = {
2152 .dbg_name = "gcc_blsp2_qup2_i2c_apps_clk",
2153 .parent = &blsp2_qup2_i2c_apps_clk_src.c,
2154 .ops = &clk_ops_branch,
2155 CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c),
2156 },
2157};
2158
2159static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
2160 .cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR,
2161 .has_sibling = 0,
2162 .base = &virt_bases[GCC_BASE],
2163 .c = {
2164 .dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
2165 .parent = &blsp2_qup2_spi_apps_clk_src.c,
2166 .ops = &clk_ops_branch,
2167 CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c),
2168 },
2169};
2170
2171static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = {
2172 .cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR,
2173 .has_sibling = 0,
2174 .base = &virt_bases[GCC_BASE],
2175 .c = {
2176 .dbg_name = "gcc_blsp2_qup3_i2c_apps_clk",
2177 .parent = &blsp2_qup3_i2c_apps_clk_src.c,
2178 .ops = &clk_ops_branch,
2179 CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c),
2180 },
2181};
2182
2183static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
2184 .cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR,
2185 .has_sibling = 0,
2186 .base = &virt_bases[GCC_BASE],
2187 .c = {
2188 .dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
2189 .parent = &blsp2_qup3_spi_apps_clk_src.c,
2190 .ops = &clk_ops_branch,
2191 CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c),
2192 },
2193};
2194
2195static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = {
2196 .cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR,
2197 .has_sibling = 0,
2198 .base = &virt_bases[GCC_BASE],
2199 .c = {
2200 .dbg_name = "gcc_blsp2_qup4_i2c_apps_clk",
2201 .parent = &blsp2_qup4_i2c_apps_clk_src.c,
2202 .ops = &clk_ops_branch,
2203 CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c),
2204 },
2205};
2206
2207static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = {
2208 .cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR,
2209 .has_sibling = 0,
2210 .base = &virt_bases[GCC_BASE],
2211 .c = {
2212 .dbg_name = "gcc_blsp2_qup4_spi_apps_clk",
2213 .parent = &blsp2_qup4_spi_apps_clk_src.c,
2214 .ops = &clk_ops_branch,
2215 CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c),
2216 },
2217};
2218
2219static struct branch_clk gcc_blsp2_uart1_apps_clk = {
2220 .cbcr_reg = BLSP2_UART1_APPS_CBCR,
2221 .has_sibling = 0,
2222 .base = &virt_bases[GCC_BASE],
2223 .c = {
2224 .dbg_name = "gcc_blsp2_uart1_apps_clk",
2225 .parent = &blsp2_uart1_apps_clk_src.c,
2226 .ops = &clk_ops_branch,
2227 CLK_INIT(gcc_blsp2_uart1_apps_clk.c),
2228 },
2229};
2230
2231static struct branch_clk gcc_blsp2_uart2_apps_clk = {
2232 .cbcr_reg = BLSP2_UART2_APPS_CBCR,
2233 .has_sibling = 0,
2234 .base = &virt_bases[GCC_BASE],
2235 .c = {
2236 .dbg_name = "gcc_blsp2_uart2_apps_clk",
2237 .parent = &blsp2_uart2_apps_clk_src.c,
2238 .ops = &clk_ops_branch,
2239 CLK_INIT(gcc_blsp2_uart2_apps_clk.c),
2240 },
2241};
2242
2243static struct local_vote_clk gcc_boot_rom_ahb_clk = {
2244 .cbcr_reg = BOOT_ROM_AHB_CBCR,
2245 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2246 .en_mask = BIT(7),
2247 .base = &virt_bases[GCC_BASE],
2248 .c = {
2249 .dbg_name = "gcc_boot_rom_ahb_clk",
2250 .ops = &clk_ops_vote,
2251 CLK_INIT(gcc_boot_rom_ahb_clk.c),
2252 },
2253};
2254
2255static struct branch_clk gcc_camss_cci_ahb_clk = {
2256 .cbcr_reg = CAMSS_CCI_AHB_CBCR,
2257 .has_sibling = 1,
2258 .base = &virt_bases[GCC_BASE],
2259 .c = {
2260 .dbg_name = "gcc_camss_cci_ahb_clk",
2261 .parent = &camss_top_ahb_clk_src.c,
2262 .ops = &clk_ops_branch,
2263 CLK_INIT(gcc_camss_cci_ahb_clk.c),
2264 },
2265};
2266
2267static struct branch_clk gcc_camss_cci_clk = {
2268 .cbcr_reg = CAMSS_CCI_CBCR,
2269 .has_sibling = 0,
2270 .base = &virt_bases[GCC_BASE],
2271 .c = {
2272 .dbg_name = "gcc_camss_cci_clk",
2273 .parent = &cci_clk_src.c,
2274 .ops = &clk_ops_branch,
2275 CLK_INIT(gcc_camss_cci_clk.c),
2276 },
2277};
2278
2279static struct branch_clk gcc_camss_cpp_ahb_clk = {
2280 .cbcr_reg = CAMSS_CPP_AHB_CBCR,
2281 .has_sibling = 1,
2282 .base = &virt_bases[GCC_BASE],
2283 .c = {
2284 .dbg_name = "gcc_camss_cpp_ahb_clk",
2285 .parent = &camss_top_ahb_clk_src.c,
2286 .ops = &clk_ops_branch,
2287 CLK_INIT(gcc_camss_cpp_ahb_clk.c),
2288 },
2289};
2290
2291static struct branch_clk gcc_camss_cpp_axi_clk = {
2292 .cbcr_reg = CAMSS_CPP_AXI_CBCR,
2293 .has_sibling = 1,
2294 .base = &virt_bases[GCC_BASE],
2295 .c = {
2296 .dbg_name = "gcc_camss_cpp_axi_clk",
2297 .ops = &clk_ops_branch,
2298 CLK_INIT(gcc_camss_cpp_axi_clk.c),
2299 },
2300};
2301
2302static struct branch_clk gcc_camss_cpp_clk = {
2303 .cbcr_reg = CAMSS_CPP_CBCR,
2304 .has_sibling = 0,
2305 .base = &virt_bases[GCC_BASE],
2306 .c = {
2307 .dbg_name = "gcc_camss_cpp_clk",
2308 .parent = &cpp_clk_src.c,
2309 .ops = &clk_ops_branch,
2310 CLK_INIT(gcc_camss_cpp_clk.c),
2311 },
2312};
2313
2314static struct branch_clk gcc_camss_csi0_ahb_clk = {
2315 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2316 .has_sibling = 1,
2317 .base = &virt_bases[GCC_BASE],
2318 .c = {
2319 .dbg_name = "gcc_camss_csi0_ahb_clk",
2320 .parent = &camss_top_ahb_clk_src.c,
2321 .ops = &clk_ops_branch,
2322 CLK_INIT(gcc_camss_csi0_ahb_clk.c),
2323 },
2324};
2325
2326static struct branch_clk gcc_camss_csi0_clk = {
2327 .cbcr_reg = CAMSS_CSI0_CBCR,
2328 .has_sibling = 1,
2329 .base = &virt_bases[GCC_BASE],
2330 .c = {
2331 .dbg_name = "gcc_camss_csi0_clk",
2332 .parent = &csi0_clk_src.c,
2333 .ops = &clk_ops_branch,
2334 CLK_INIT(gcc_camss_csi0_clk.c),
2335 },
2336};
2337
2338static struct branch_clk gcc_camss_csi0phy_clk = {
2339 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2340 .has_sibling = 1,
2341 .base = &virt_bases[GCC_BASE],
2342 .c = {
2343 .dbg_name = "gcc_camss_csi0phy_clk",
2344 .parent = &csi0_clk_src.c,
2345 .ops = &clk_ops_branch,
2346 CLK_INIT(gcc_camss_csi0phy_clk.c),
2347 },
2348};
2349
2350static struct branch_clk gcc_camss_csi0pix_clk = {
2351 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2352 .has_sibling = 1,
2353 .base = &virt_bases[GCC_BASE],
2354 .c = {
2355 .dbg_name = "gcc_camss_csi0pix_clk",
2356 .parent = &csi0_clk_src.c,
2357 .ops = &clk_ops_branch,
2358 CLK_INIT(gcc_camss_csi0pix_clk.c),
2359 },
2360};
2361
2362static struct branch_clk gcc_camss_csi0rdi_clk = {
2363 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2364 .has_sibling = 1,
2365 .base = &virt_bases[GCC_BASE],
2366 .c = {
2367 .dbg_name = "gcc_camss_csi0rdi_clk",
2368 .parent = &csi0_clk_src.c,
2369 .ops = &clk_ops_branch,
2370 CLK_INIT(gcc_camss_csi0rdi_clk.c),
2371 },
2372};
2373
2374static struct branch_clk gcc_camss_csi1_ahb_clk = {
2375 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2376 .has_sibling = 1,
2377 .base = &virt_bases[GCC_BASE],
2378 .c = {
2379 .dbg_name = "gcc_camss_csi1_ahb_clk",
2380 .parent = &camss_top_ahb_clk_src.c,
2381 .ops = &clk_ops_branch,
2382 CLK_INIT(gcc_camss_csi1_ahb_clk.c),
2383 },
2384};
2385
2386static struct branch_clk gcc_camss_csi1_clk = {
2387 .cbcr_reg = CAMSS_CSI1_CBCR,
2388 .has_sibling = 1,
2389 .base = &virt_bases[GCC_BASE],
2390 .c = {
2391 .dbg_name = "gcc_camss_csi1_clk",
2392 .parent = &csi1_clk_src.c,
2393 .ops = &clk_ops_branch,
2394 CLK_INIT(gcc_camss_csi1_clk.c),
2395 },
2396};
2397
2398static struct branch_clk gcc_camss_csi1phy_clk = {
2399 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2400 .has_sibling = 1,
2401 .base = &virt_bases[GCC_BASE],
2402 .c = {
2403 .dbg_name = "gcc_camss_csi1phy_clk",
2404 .parent = &csi1_clk_src.c,
2405 .ops = &clk_ops_branch,
2406 CLK_INIT(gcc_camss_csi1phy_clk.c),
2407 },
2408};
2409
2410static struct branch_clk gcc_camss_csi1pix_clk = {
2411 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2412 .has_sibling = 1,
2413 .base = &virt_bases[GCC_BASE],
2414 .c = {
2415 .dbg_name = "gcc_camss_csi1pix_clk",
2416 .parent = &csi1_clk_src.c,
2417 .ops = &clk_ops_branch,
2418 CLK_INIT(gcc_camss_csi1pix_clk.c),
2419 },
2420};
2421
2422static struct branch_clk gcc_camss_csi1rdi_clk = {
2423 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2424 .has_sibling = 1,
2425 .base = &virt_bases[GCC_BASE],
2426 .c = {
2427 .dbg_name = "gcc_camss_csi1rdi_clk",
2428 .parent = &csi1_clk_src.c,
2429 .ops = &clk_ops_branch,
2430 CLK_INIT(gcc_camss_csi1rdi_clk.c),
2431 },
2432};
2433
2434static struct branch_clk gcc_camss_csi2_ahb_clk = {
2435 .cbcr_reg = CAMSS_CSI2_AHB_CBCR,
2436 .has_sibling = 1,
2437 .base = &virt_bases[GCC_BASE],
2438 .c = {
2439 .dbg_name = "gcc_camss_csi2_ahb_clk",
2440 .parent = &camss_top_ahb_clk_src.c,
2441 .ops = &clk_ops_branch,
2442 CLK_INIT(gcc_camss_csi2_ahb_clk.c),
2443 },
2444};
2445
2446static struct branch_clk gcc_camss_csi2_clk = {
2447 .cbcr_reg = CAMSS_CSI2_CBCR,
2448 .has_sibling = 1,
2449 .base = &virt_bases[GCC_BASE],
2450 .c = {
2451 .dbg_name = "gcc_camss_csi2_clk",
2452 .parent = &csi2_clk_src.c,
2453 .ops = &clk_ops_branch,
2454 CLK_INIT(gcc_camss_csi2_clk.c),
2455 },
2456};
2457
2458static struct branch_clk gcc_camss_csi2phy_clk = {
2459 .cbcr_reg = CAMSS_CSI2PHY_CBCR,
2460 .has_sibling = 1,
2461 .base = &virt_bases[GCC_BASE],
2462 .c = {
2463 .dbg_name = "gcc_camss_csi2phy_clk",
2464 .parent = &csi2_clk_src.c,
2465 .ops = &clk_ops_branch,
2466 CLK_INIT(gcc_camss_csi2phy_clk.c),
2467 },
2468};
2469
2470static struct branch_clk gcc_camss_csi2pix_clk = {
2471 .cbcr_reg = CAMSS_CSI2PIX_CBCR,
2472 .has_sibling = 1,
2473 .base = &virt_bases[GCC_BASE],
2474 .c = {
2475 .dbg_name = "gcc_camss_csi2pix_clk",
2476 .parent = &csi2_clk_src.c,
2477 .ops = &clk_ops_branch,
2478 CLK_INIT(gcc_camss_csi2pix_clk.c),
2479 },
2480};
2481
2482static struct branch_clk gcc_camss_csi2rdi_clk = {
2483 .cbcr_reg = CAMSS_CSI2RDI_CBCR,
2484 .has_sibling = 1,
2485 .base = &virt_bases[GCC_BASE],
2486 .c = {
2487 .dbg_name = "gcc_camss_csi2rdi_clk",
2488 .parent = &csi2_clk_src.c,
2489 .ops = &clk_ops_branch,
2490 CLK_INIT(gcc_camss_csi2rdi_clk.c),
2491 },
2492};
2493
2494static struct branch_clk gcc_camss_csi_vfe0_clk = {
2495 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2496 .has_sibling = 1,
2497 .base = &virt_bases[GCC_BASE],
2498 .c = {
2499 .dbg_name = "gcc_camss_csi_vfe0_clk",
2500 .parent = &vfe0_clk_src.c,
2501 .ops = &clk_ops_branch,
2502 CLK_INIT(gcc_camss_csi_vfe0_clk.c),
2503 },
2504};
2505
2506static struct branch_clk gcc_camss_csi_vfe1_clk = {
2507 .cbcr_reg = CAMSS_CSI_VFE1_CBCR,
2508 .has_sibling = 1,
2509 .base = &virt_bases[GCC_BASE],
2510 .c = {
2511 .dbg_name = "gcc_camss_csi_vfe1_clk",
2512 .parent = &vfe1_clk_src.c,
2513 .ops = &clk_ops_branch,
2514 CLK_INIT(gcc_camss_csi_vfe1_clk.c),
2515 },
2516};
2517
2518static struct branch_clk gcc_camss_gp0_clk = {
2519 .cbcr_reg = CAMSS_GP0_CBCR,
2520 .has_sibling = 0,
2521 .base = &virt_bases[GCC_BASE],
2522 .c = {
2523 .dbg_name = "gcc_camss_gp0_clk",
2524 .parent = &camss_gp0_clk_src.c,
2525 .ops = &clk_ops_branch,
2526 CLK_INIT(gcc_camss_gp0_clk.c),
2527 },
2528};
2529
2530static struct branch_clk gcc_camss_gp1_clk = {
2531 .cbcr_reg = CAMSS_GP1_CBCR,
2532 .has_sibling = 0,
2533 .base = &virt_bases[GCC_BASE],
2534 .c = {
2535 .dbg_name = "gcc_camss_gp1_clk",
2536 .parent = &camss_gp1_clk_src.c,
2537 .ops = &clk_ops_branch,
2538 CLK_INIT(gcc_camss_gp1_clk.c),
2539 },
2540};
2541
2542static struct branch_clk gcc_camss_ispif_ahb_clk = {
2543 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2544 .has_sibling = 0,
2545 .base = &virt_bases[GCC_BASE],
2546 .c = {
2547 .dbg_name = "gcc_camss_ispif_ahb_clk",
2548 .parent = &camss_top_ahb_clk_src.c,
2549 .ops = &clk_ops_branch,
2550 CLK_INIT(gcc_camss_ispif_ahb_clk.c),
2551 },
2552};
2553
2554static struct branch_clk gcc_camss_jpeg0_clk = {
2555 .cbcr_reg = CAMSS_JPEG0_CBCR,
2556 .has_sibling = 0,
2557 .base = &virt_bases[GCC_BASE],
2558 .c = {
2559 .dbg_name = "gcc_camss_jpeg0_clk",
2560 .parent = &jpeg0_clk_src.c,
2561 .ops = &clk_ops_branch,
2562 CLK_INIT(gcc_camss_jpeg0_clk.c),
2563 },
2564};
2565
2566static struct branch_clk gcc_camss_jpeg_ahb_clk = {
2567 .cbcr_reg = CAMSS_JPEG_AHB_CBCR,
2568 .has_sibling = 1,
2569 .base = &virt_bases[GCC_BASE],
2570 .c = {
2571 .dbg_name = "gcc_camss_jpeg_ahb_clk",
2572 .parent = &camss_top_ahb_clk_src.c,
2573 .ops = &clk_ops_branch,
2574 CLK_INIT(gcc_camss_jpeg_ahb_clk.c),
2575 },
2576};
2577
2578static struct branch_clk gcc_camss_jpeg_axi_clk = {
2579 .cbcr_reg = CAMSS_JPEG_AXI_CBCR,
2580 .has_sibling = 1,
2581 .base = &virt_bases[GCC_BASE],
2582 .c = {
2583 .dbg_name = "gcc_camss_jpeg_axi_clk",
2584 .ops = &clk_ops_branch,
2585 CLK_INIT(gcc_camss_jpeg_axi_clk.c),
2586 },
2587};
2588
2589static struct branch_clk gcc_camss_mclk0_clk = {
2590 .cbcr_reg = CAMSS_MCLK0_CBCR,
2591 .has_sibling = 0,
2592 .base = &virt_bases[GCC_BASE],
2593 .c = {
2594 .dbg_name = "gcc_camss_mclk0_clk",
2595 .parent = &mclk0_clk_src.c,
2596 .ops = &clk_ops_branch,
2597 CLK_INIT(gcc_camss_mclk0_clk.c),
2598 },
2599};
2600
2601static struct branch_clk gcc_camss_mclk1_clk = {
2602 .cbcr_reg = CAMSS_MCLK1_CBCR,
2603 .has_sibling = 0,
2604 .base = &virt_bases[GCC_BASE],
2605 .c = {
2606 .dbg_name = "gcc_camss_mclk1_clk",
2607 .parent = &mclk1_clk_src.c,
2608 .ops = &clk_ops_branch,
2609 CLK_INIT(gcc_camss_mclk1_clk.c),
2610 },
2611};
2612
2613static struct branch_clk gcc_camss_mclk2_clk = {
2614 .cbcr_reg = CAMSS_MCLK2_CBCR,
2615 .has_sibling = 0,
2616 .base = &virt_bases[GCC_BASE],
2617 .c = {
2618 .dbg_name = "gcc_camss_mclk2_clk",
2619 .parent = &mclk2_clk_src.c,
2620 .ops = &clk_ops_branch,
2621 CLK_INIT(gcc_camss_mclk2_clk.c),
2622 },
2623};
2624
2625static struct branch_clk gcc_camss_micro_ahb_clk = {
2626 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2627 .bcr_reg = CAMSS_MICRO_BCR,
2628 .has_sibling = 1,
2629 .base = &virt_bases[GCC_BASE],
2630 .c = {
2631 .dbg_name = "gcc_camss_micro_ahb_clk",
2632 .parent = &camss_top_ahb_clk_src.c,
2633 .ops = &clk_ops_branch,
2634 CLK_INIT(gcc_camss_micro_ahb_clk.c),
2635 },
2636};
2637
2638static struct branch_clk gcc_camss_csi0phytimer_clk = {
2639 .cbcr_reg = CAMSS_CSI0PHYTIMER_CBCR,
2640 .has_sibling = 0,
2641 .base = &virt_bases[GCC_BASE],
2642 .c = {
2643 .dbg_name = "gcc_camss_csi0phytimer_clk",
2644 .parent = &csi0phytimer_clk_src.c,
2645 .ops = &clk_ops_branch,
2646 CLK_INIT(gcc_camss_csi0phytimer_clk.c),
2647 },
2648};
2649
2650static struct branch_clk gcc_camss_csi1phytimer_clk = {
2651 .cbcr_reg = CAMSS_CSI1PHYTIMER_CBCR,
2652 .has_sibling = 0,
2653 .base = &virt_bases[GCC_BASE],
2654 .c = {
2655 .dbg_name = "gcc_camss_csi1phytimer_clk",
2656 .parent = &csi1phytimer_clk_src.c,
2657 .ops = &clk_ops_branch,
2658 CLK_INIT(gcc_camss_csi1phytimer_clk.c),
2659 },
2660};
2661
2662static struct branch_clk gcc_camss_ahb_clk = {
2663 .cbcr_reg = CAMSS_AHB_CBCR,
2664 .has_sibling = 1,
2665 .base = &virt_bases[GCC_BASE],
2666 .c = {
2667 .dbg_name = "gcc_camss_ahb_clk",
2668 .ops = &clk_ops_branch,
2669 CLK_INIT(gcc_camss_ahb_clk.c),
2670 },
2671};
2672
2673static struct branch_clk gcc_camss_top_ahb_clk = {
2674 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2675 .has_sibling = 1,
2676 .base = &virt_bases[GCC_BASE],
2677 .c = {
2678 .dbg_name = "gcc_camss_top_ahb_clk",
2679 .parent = &camss_top_ahb_clk_src.c,
2680 .ops = &clk_ops_branch,
2681 CLK_INIT(gcc_camss_top_ahb_clk.c),
2682 },
2683};
2684
2685static struct branch_clk gcc_camss_vfe0_clk = {
2686 .cbcr_reg = CAMSS_VFE0_CBCR,
2687 .has_sibling = 1,
2688 .base = &virt_bases[GCC_BASE],
2689 .c = {
2690 .dbg_name = "gcc_camss_vfe0_clk",
2691 .parent = &vfe0_clk_src.c,
2692 .ops = &clk_ops_branch,
2693 CLK_INIT(gcc_camss_vfe0_clk.c),
2694 },
2695};
2696
2697static struct branch_clk gcc_camss_vfe_ahb_clk = {
2698 .cbcr_reg = CAMSS_VFE_AHB_CBCR,
2699 .has_sibling = 1,
2700 .base = &virt_bases[GCC_BASE],
2701 .c = {
2702 .dbg_name = "gcc_camss_vfe_ahb_clk",
2703 .ops = &clk_ops_branch,
2704 CLK_INIT(gcc_camss_vfe_ahb_clk.c),
2705 },
2706};
2707
2708static struct branch_clk gcc_camss_vfe_axi_clk = {
2709 .cbcr_reg = CAMSS_VFE_AXI_CBCR,
2710 .has_sibling = 1,
2711 .base = &virt_bases[GCC_BASE],
2712 .c = {
2713 .dbg_name = "gcc_camss_vfe_axi_clk",
2714 .ops = &clk_ops_branch,
2715 CLK_INIT(gcc_camss_vfe_axi_clk.c),
2716 },
2717};
2718
2719static struct branch_clk gcc_camss_vfe1_ahb_clk = {
2720 .cbcr_reg = CAMSS_VFE1_AHB_CBCR,
2721 .has_sibling = 1,
2722 .base = &virt_bases[GCC_BASE],
2723 .c = {
2724 .dbg_name = "gcc_camss_vfe1_ahb_clk",
2725 .parent = &camss_top_ahb_clk_src.c,
2726 .ops = &clk_ops_branch,
2727 CLK_INIT(gcc_camss_vfe1_ahb_clk.c),
2728 },
2729};
2730
2731static struct branch_clk gcc_camss_vfe1_axi_clk = {
2732 .cbcr_reg = CAMSS_VFE1_AXI_CBCR,
2733 .has_sibling = 1,
2734 .base = &virt_bases[GCC_BASE],
2735 .c = {
2736 .dbg_name = "gcc_camss_vfe1_axi_clk",
2737 .ops = &clk_ops_branch,
2738 CLK_INIT(gcc_camss_vfe1_axi_clk.c),
2739 },
2740};
2741
2742static struct branch_clk gcc_camss_vfe1_clk = {
2743 .cbcr_reg = CAMSS_VFE1_CBCR,
2744 .has_sibling = 1,
2745 .base = &virt_bases[GCC_BASE],
2746 .c = {
2747 .dbg_name = "gcc_camss_vfe1_clk",
2748 .parent = &vfe1_clk_src.c,
2749 .ops = &clk_ops_branch,
2750 CLK_INIT(gcc_camss_vfe1_clk.c),
2751 },
2752};
2753
2754static struct local_vote_clk gcc_crypto_ahb_clk = {
2755 .cbcr_reg = CRYPTO_AHB_CBCR,
2756 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2757 .en_mask = BIT(0),
2758 .base = &virt_bases[GCC_BASE],
2759 .c = {
2760 .dbg_name = "gcc_crypto_ahb_clk",
2761 .parent = &crypto_clk_src.c,
2762 .ops = &clk_ops_vote,
2763 CLK_INIT(gcc_crypto_ahb_clk.c),
2764 },
2765};
2766
2767static struct local_vote_clk gcc_crypto_axi_clk = {
2768 .cbcr_reg = CRYPTO_AXI_CBCR,
2769 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2770 .en_mask = BIT(1),
2771 .base = &virt_bases[GCC_BASE],
2772 .c = {
2773 .dbg_name = "gcc_crypto_axi_clk",
2774 .ops = &clk_ops_vote,
2775 CLK_INIT(gcc_crypto_axi_clk.c),
2776 },
2777};
2778
2779static struct local_vote_clk gcc_crypto_clk = {
2780 .cbcr_reg = CRYPTO_CBCR,
2781 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2782 .en_mask = BIT(2),
2783 .base = &virt_bases[GCC_BASE],
2784 .c = {
2785 .dbg_name = "gcc_crypto_clk",
2786 .parent = &crypto_clk_src.c,
2787 .ops = &clk_ops_vote,
2788 CLK_INIT(gcc_crypto_clk.c),
2789 },
2790};
2791
2792static struct gate_clk gcc_oxili_gmem_clk = {
2793 .en_reg = OXILI_GMEM_CBCR,
2794 .en_mask = BIT(0),
2795 .delay_us = 50,
2796 .base = &virt_bases[GCC_BASE],
2797 .c = {
2798 .dbg_name = "gcc_oxili_gmem_clk",
2799 .parent = &gfx3d_clk_src.c,
2800 .ops = &clk_ops_gate,
2801 CLK_INIT(gcc_oxili_gmem_clk.c),
2802 },
2803};
2804
2805static struct branch_clk gcc_gp1_clk = {
2806 .cbcr_reg = GP1_CBCR,
2807 .has_sibling = 0,
2808 .base = &virt_bases[GCC_BASE],
2809 .c = {
2810 .dbg_name = "gcc_gp1_clk",
2811 .parent = &gp1_clk_src.c,
2812 .ops = &clk_ops_branch,
2813 CLK_INIT(gcc_gp1_clk.c),
2814 },
2815};
2816
2817static struct branch_clk gcc_gp2_clk = {
2818 .cbcr_reg = GP2_CBCR,
2819 .has_sibling = 0,
2820 .base = &virt_bases[GCC_BASE],
2821 .c = {
2822 .dbg_name = "gcc_gp2_clk",
2823 .parent = &gp2_clk_src.c,
2824 .ops = &clk_ops_branch,
2825 CLK_INIT(gcc_gp2_clk.c),
2826 },
2827};
2828
2829static struct branch_clk gcc_gp3_clk = {
2830 .cbcr_reg = GP3_CBCR,
2831 .has_sibling = 0,
2832 .base = &virt_bases[GCC_BASE],
2833 .c = {
2834 .dbg_name = "gcc_gp3_clk",
2835 .parent = &gp3_clk_src.c,
2836 .ops = &clk_ops_branch,
2837 CLK_INIT(gcc_gp3_clk.c),
2838 },
2839};
2840
2841static struct branch_clk gcc_mdss_ahb_clk = {
2842 .cbcr_reg = MDSS_AHB_CBCR,
2843 .has_sibling = 1,
2844 .base = &virt_bases[GCC_BASE],
2845 .c = {
2846 .dbg_name = "gcc_mdss_ahb_clk",
2847 .ops = &clk_ops_branch,
2848 CLK_INIT(gcc_mdss_ahb_clk.c),
2849 },
2850};
2851
2852static struct branch_clk gcc_mdss_axi_clk = {
2853 .cbcr_reg = MDSS_AXI_CBCR,
2854 .has_sibling = 1,
2855 .base = &virt_bases[GCC_BASE],
2856 .c = {
2857 .dbg_name = "gcc_mdss_axi_clk",
2858 .ops = &clk_ops_branch,
2859 CLK_INIT(gcc_mdss_axi_clk.c),
2860 },
2861};
2862
2863static struct branch_clk gcc_mdss_byte0_clk = {
2864 .cbcr_reg = MDSS_BYTE0_CBCR,
2865 .has_sibling = 0,
2866 .base = &virt_bases[GCC_BASE],
2867 .c = {
2868 .dbg_name = "gcc_mdss_byte0_clk",
2869 .parent = &byte0_clk_src.c,
2870 .ops = &clk_ops_branch,
2871 .flags = CLKFLAG_NO_RATE_CACHE,
2872 CLK_INIT(gcc_mdss_byte0_clk.c),
2873 },
2874};
2875
2876static struct branch_clk gcc_mdss_byte1_clk = {
2877 .cbcr_reg = MDSS_BYTE1_CBCR,
2878 .has_sibling = 0,
2879 .base = &virt_bases[GCC_BASE],
2880 .c = {
2881 .dbg_name = "gcc_mdss_byte1_clk",
2882 .parent = &byte1_clk_src.c,
2883 .ops = &clk_ops_branch,
2884 .flags = CLKFLAG_NO_RATE_CACHE,
2885 CLK_INIT(gcc_mdss_byte1_clk.c),
2886 },
2887};
2888
2889static struct branch_clk gcc_mdss_esc0_clk = {
2890 .cbcr_reg = MDSS_ESC0_CBCR,
2891 .has_sibling = 0,
2892 .base = &virt_bases[GCC_BASE],
2893 .c = {
2894 .dbg_name = "gcc_mdss_esc0_clk",
2895 .parent = &esc0_clk_src.c,
2896 .ops = &clk_ops_branch,
2897 CLK_INIT(gcc_mdss_esc0_clk.c),
2898 },
2899};
2900
2901static struct branch_clk gcc_mdss_esc1_clk = {
2902 .cbcr_reg = MDSS_ESC1_CBCR,
2903 .has_sibling = 0,
2904 .base = &virt_bases[GCC_BASE],
2905 .c = {
2906 .dbg_name = "gcc_mdss_esc1_clk",
2907 .parent = &esc1_clk_src.c,
2908 .ops = &clk_ops_branch,
2909 CLK_INIT(gcc_mdss_esc1_clk.c),
2910 },
2911};
2912
2913static struct branch_clk gcc_mdss_mdp_clk = {
2914 .cbcr_reg = MDSS_MDP_CBCR,
2915 .has_sibling = 0,
2916 .base = &virt_bases[GCC_BASE],
2917 .c = {
2918 .dbg_name = "gcc_mdss_mdp_clk",
2919 .parent = &mdp_clk_src.c,
2920 .ops = &clk_ops_branch,
2921 CLK_INIT(gcc_mdss_mdp_clk.c),
2922 },
2923};
2924
2925static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2926static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2927
2928static struct branch_clk gcc_mdss_pclk0_clk = {
2929 .cbcr_reg = MDSS_PCLK0_CBCR,
2930 .has_sibling = 0,
2931 .base = &virt_bases[GCC_BASE],
2932 .c = {
2933 .dbg_name = "gcc_mdss_pclk0_clk",
2934 .parent = &pclk0_clk_src.c,
2935 .ops = &clk_ops_branch,
2936 .flags = CLKFLAG_NO_RATE_CACHE,
2937 CLK_INIT(gcc_mdss_pclk0_clk.c),
2938 },
2939};
2940
2941static struct branch_clk gcc_mdss_pclk1_clk = {
2942 .cbcr_reg = MDSS_PCLK1_CBCR,
2943 .has_sibling = 0,
2944 .base = &virt_bases[GCC_BASE],
2945 .c = {
2946 .dbg_name = "gcc_mdss_pclk1_clk",
2947 .parent = &pclk1_clk_src.c,
2948 .ops = &clk_ops_branch,
2949 .flags = CLKFLAG_NO_RATE_CACHE,
2950 CLK_INIT(gcc_mdss_pclk1_clk.c),
2951 },
2952};
2953
2954static struct branch_clk gcc_mdss_vsync_clk = {
2955 .cbcr_reg = MDSS_VSYNC_CBCR,
2956 .has_sibling = 0,
2957 .base = &virt_bases[GCC_BASE],
2958 .c = {
2959 .dbg_name = "gcc_mdss_vsync_clk",
2960 .parent = &vsync_clk_src.c,
2961 .ops = &clk_ops_branch,
2962 CLK_INIT(gcc_mdss_vsync_clk.c),
2963 },
2964};
2965
2966static struct branch_clk gcc_mss_cfg_ahb_clk = {
2967 .cbcr_reg = MSS_CFG_AHB_CBCR,
2968 .has_sibling = 1,
2969 .base = &virt_bases[GCC_BASE],
2970 .c = {
2971 .dbg_name = "gcc_mss_cfg_ahb_clk",
2972 .ops = &clk_ops_branch,
2973 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
2974 },
2975};
2976
2977static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
2978 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
2979 .has_sibling = 1,
2980 .base = &virt_bases[GCC_BASE],
2981 .c = {
2982 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
2983 .ops = &clk_ops_branch,
2984 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
2985 },
2986};
2987
2988static struct local_vote_clk gcc_apss_tcu_clk;
2989static struct branch_clk gcc_bimc_gfx_clk = {
2990 .cbcr_reg = BIMC_GFX_CBCR,
2991 .has_sibling = 1,
2992 .base = &virt_bases[GCC_BASE],
2993 .c = {
2994 .dbg_name = "gcc_bimc_gfx_clk",
2995 .ops = &clk_ops_branch,
2996 CLK_INIT(gcc_bimc_gfx_clk.c),
2997 .depends = &gcc_apss_tcu_clk.c,
2998 },
2999};
3000
3001static struct branch_clk gcc_oxili_ahb_clk = {
3002 .cbcr_reg = OXILI_AHB_CBCR,
3003 .has_sibling = 1,
3004 .base = &virt_bases[GCC_BASE],
3005 .c = {
3006 .dbg_name = "gcc_oxili_ahb_clk",
3007 .ops = &clk_ops_branch,
3008 CLK_INIT(gcc_oxili_ahb_clk.c),
3009 },
3010};
3011
3012static struct branch_clk gcc_oxili_gfx3d_clk = {
3013 .cbcr_reg = OXILI_GFX3D_CBCR,
3014 .has_sibling = 0,
3015 .base = &virt_bases[GCC_BASE],
3016 .c = {
3017 .dbg_name = "gcc_oxili_gfx3d_clk",
3018 .parent = &gfx3d_clk_src.c,
3019 .ops = &clk_ops_branch,
3020 CLK_INIT(gcc_oxili_gfx3d_clk.c),
3021 },
3022};
3023
3024static struct branch_clk gcc_oxili_timer_clk = {
3025 .cbcr_reg = OXILI_TIMER_CBCR,
3026 .has_sibling = 0,
3027 .base = &virt_bases[GCC_BASE],
3028 .c = {
3029 .dbg_name = "gcc_oxili_timer_clk",
3030 .parent = &xo_clk_src.c,
3031 .ops = &clk_ops_branch,
3032 CLK_INIT(gcc_oxili_timer_clk.c),
3033 },
3034};
3035
3036static struct branch_clk gcc_oxili_aon_clk = {
3037 .cbcr_reg = OXILI_AON_CBCR,
3038 .has_sibling = 0,
3039 .base = &virt_bases[GCC_BASE],
3040 .c = {
3041 .dbg_name = "gcc_oxili_aon_clk",
3042 .parent = &gfx3d_clk_src.c,
3043 .ops = &clk_ops_branch,
3044 CLK_INIT(gcc_oxili_aon_clk.c),
3045 },
3046};
3047
3048static struct branch_clk gcc_pdm2_clk = {
3049 .cbcr_reg = PDM2_CBCR,
3050 .has_sibling = 0,
3051 .base = &virt_bases[GCC_BASE],
3052 .c = {
3053 .dbg_name = "gcc_pdm2_clk",
3054 .parent = &pdm2_clk_src.c,
3055 .ops = &clk_ops_branch,
3056 CLK_INIT(gcc_pdm2_clk.c),
3057 },
3058};
3059
3060static struct branch_clk gcc_pdm_ahb_clk = {
3061 .cbcr_reg = PDM_AHB_CBCR,
3062 .has_sibling = 1,
3063 .base = &virt_bases[GCC_BASE],
3064 .c = {
3065 .dbg_name = "gcc_pdm_ahb_clk",
3066 .ops = &clk_ops_branch,
3067 CLK_INIT(gcc_pdm_ahb_clk.c),
3068 },
3069};
3070
3071static struct local_vote_clk gcc_prng_ahb_clk = {
3072 .cbcr_reg = PRNG_AHB_CBCR,
3073 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3074 .en_mask = BIT(8),
3075 .base = &virt_bases[GCC_BASE],
3076 .c = {
3077 .dbg_name = "gcc_prng_ahb_clk",
3078 .ops = &clk_ops_vote,
3079 CLK_INIT(gcc_prng_ahb_clk.c),
3080 },
3081};
3082
3083static struct local_vote_clk gcc_qdss_dap_clk = {
3084 .cbcr_reg = QDSS_DAP_CBCR,
3085 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3086 .en_mask = BIT(21),
3087 .base = &virt_bases[GCC_BASE],
3088 .c = {
3089 .dbg_name = "gcc_qdss_dap_clk",
3090 .ops = &clk_ops_vote,
3091 CLK_INIT(gcc_qdss_dap_clk.c),
3092 },
3093};
3094
3095static struct branch_clk gcc_sdcc1_ahb_clk = {
3096 .cbcr_reg = SDCC1_AHB_CBCR,
3097 .has_sibling = 1,
3098 .base = &virt_bases[GCC_BASE],
3099 .c = {
3100 .dbg_name = "gcc_sdcc1_ahb_clk",
3101 .ops = &clk_ops_branch,
3102 CLK_INIT(gcc_sdcc1_ahb_clk.c),
3103 },
3104};
3105
3106static struct branch_clk gcc_sdcc1_apps_clk = {
3107 .cbcr_reg = SDCC1_APPS_CBCR,
3108 .has_sibling = 0,
3109 .base = &virt_bases[GCC_BASE],
3110 .c = {
3111 .dbg_name = "gcc_sdcc1_apps_clk",
3112 .parent = &sdcc1_apps_clk_src.c,
3113 .ops = &clk_ops_branch,
3114 CLK_INIT(gcc_sdcc1_apps_clk.c),
3115 },
3116};
3117
3118static struct branch_clk gcc_sdcc1_ice_core_clk = {
3119 .cbcr_reg = SDCC1_ICE_CORE_CBCR,
3120 .has_sibling = 0,
3121 .base = &virt_bases[GCC_BASE],
3122 .c = {
3123 .dbg_name = "gcc_sdcc1_ice_core_clk",
3124 .parent = &sdcc1_ice_core_clk_src.c,
3125 .ops = &clk_ops_branch,
3126 CLK_INIT(gcc_sdcc1_ice_core_clk.c),
3127 }
3128};
3129
3130static struct branch_clk gcc_sdcc2_ahb_clk = {
3131 .cbcr_reg = SDCC2_AHB_CBCR,
3132 .has_sibling = 1,
3133 .base = &virt_bases[GCC_BASE],
3134 .c = {
3135 .dbg_name = "gcc_sdcc2_ahb_clk",
3136 .ops = &clk_ops_branch,
3137 CLK_INIT(gcc_sdcc2_ahb_clk.c),
3138 },
3139};
3140
3141static struct branch_clk gcc_sdcc2_apps_clk = {
3142 .cbcr_reg = SDCC2_APPS_CBCR,
3143 .has_sibling = 0,
3144 .base = &virt_bases[GCC_BASE],
3145 .c = {
3146 .dbg_name = "gcc_sdcc2_apps_clk",
3147 .parent = &sdcc2_apps_clk_src.c,
3148 .ops = &clk_ops_branch,
3149 CLK_INIT(gcc_sdcc2_apps_clk.c),
3150 },
3151};
3152
3153static struct local_vote_clk gcc_cpp_tbu_clk = {
3154 .cbcr_reg = CPP_TBU_CBCR,
3155 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3156 .en_mask = BIT(14),
3157 .base = &virt_bases[GCC_BASE],
3158 .c = {
3159 .dbg_name = "gcc_cpp_tbu_clk",
3160 .ops = &clk_ops_vote,
3161 CLK_INIT(gcc_cpp_tbu_clk.c),
3162 },
3163};
3164
3165static struct local_vote_clk gcc_gfx_tbu_clk = {
3166 .cbcr_reg = GFX_TBU_CBCR,
3167 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3168 .en_mask = BIT(3),
3169 .base = &virt_bases[GCC_BASE],
3170 .c = {
3171 .dbg_name = "gcc_gfx_tbu_clk",
3172 .ops = &clk_ops_vote,
3173 CLK_INIT(gcc_gfx_tbu_clk.c),
3174 },
3175};
3176
3177static struct local_vote_clk gcc_gfx_tcu_clk = {
3178 .cbcr_reg = GFX_TCU_CBCR,
3179 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3180 .en_mask = BIT(2),
3181 .base = &virt_bases[GCC_BASE],
3182 .c = {
3183 .dbg_name = "gcc_gfx_tcu_clk",
3184 .ops = &clk_ops_vote,
3185 CLK_INIT(gcc_gfx_tcu_clk.c),
3186 },
3187};
3188
3189static struct local_vote_clk gcc_apss_tcu_clk = {
3190 .cbcr_reg = APSS_TCU_CBCR,
3191 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3192 .en_mask = BIT(1),
3193 .base = &virt_bases[GCC_BASE],
3194 .c = {
3195 .dbg_name = "gcc_apss_tcu_clk",
3196 .ops = &clk_ops_vote,
3197 CLK_INIT(gcc_apss_tcu_clk.c),
3198 },
3199};
3200
3201static struct local_vote_clk gcc_gtcu_ahb_clk = {
3202 .cbcr_reg = GTCU_AHB_CBCR,
3203 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3204 .en_mask = BIT(13),
3205 .base = &virt_bases[GCC_BASE],
3206 .c = {
3207 .dbg_name = "gcc_gtcu_ahb_clk",
3208 .ops = &clk_ops_vote,
3209 CLK_INIT(gcc_gtcu_ahb_clk.c),
3210 },
3211};
3212
3213static struct local_vote_clk gcc_ipa_tbu_clk = {
3214 .cbcr_reg = IPA_TBU_CBCR,
3215 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3216 .en_mask = BIT(16),
3217 .base = &virt_bases[GCC_BASE],
3218 .c = {
3219 .dbg_name = "gcc_ipa_tbu_clk",
3220 .ops = &clk_ops_vote,
3221 CLK_INIT(gcc_ipa_tbu_clk.c),
3222 },
3223};
3224
3225static struct local_vote_clk gcc_jpeg_tbu_clk = {
3226 .cbcr_reg = JPEG_TBU_CBCR,
3227 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3228 .en_mask = BIT(10),
3229 .base = &virt_bases[GCC_BASE],
3230 .c = {
3231 .dbg_name = "gcc_jpeg_tbu_clk",
3232 .ops = &clk_ops_vote,
3233 CLK_INIT(gcc_jpeg_tbu_clk.c),
3234 },
3235};
3236
3237static struct local_vote_clk gcc_mdp_tbu_clk = {
3238 .cbcr_reg = MDP_TBU_CBCR,
3239 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3240 .en_mask = BIT(4),
3241 .base = &virt_bases[GCC_BASE],
3242 .c = {
3243 .dbg_name = "gcc_mdp_tbu_clk",
3244 .ops = &clk_ops_vote,
3245 CLK_INIT(gcc_mdp_tbu_clk.c),
3246 },
3247};
3248
3249static struct local_vote_clk gcc_smmu_cfg_clk = {
3250 .cbcr_reg = SMMU_CFG_CBCR,
3251 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3252 .en_mask = BIT(12),
3253 .base = &virt_bases[GCC_BASE],
3254 .c = {
3255 .dbg_name = "gcc_smmu_cfg_clk",
3256 .ops = &clk_ops_vote,
3257 CLK_INIT(gcc_smmu_cfg_clk.c),
3258 },
3259};
3260
3261static struct local_vote_clk gcc_venus_tbu_clk = {
3262 .cbcr_reg = VENUS_TBU_CBCR,
3263 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3264 .en_mask = BIT(5),
3265 .base = &virt_bases[GCC_BASE],
3266 .c = {
3267 .dbg_name = "gcc_venus_tbu_clk",
3268 .ops = &clk_ops_vote,
3269 CLK_INIT(gcc_venus_tbu_clk.c),
3270 },
3271};
3272
3273static struct local_vote_clk gcc_vfe1_tbu_clk = {
3274 .cbcr_reg = VFE1_TBU_CBCR,
3275 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3276 .en_mask = BIT(17),
3277 .base = &virt_bases[GCC_BASE],
3278 .c = {
3279 .dbg_name = "gcc_vfe1_tbu_clk",
3280 .ops = &clk_ops_vote,
3281 CLK_INIT(gcc_vfe1_tbu_clk.c),
3282 },
3283};
3284
3285static struct local_vote_clk gcc_vfe_tbu_clk = {
3286 .cbcr_reg = VFE_TBU_CBCR,
3287 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3288 .en_mask = BIT(9),
3289 .base = &virt_bases[GCC_BASE],
3290 .c = {
3291 .dbg_name = "gcc_vfe_tbu_clk",
3292 .ops = &clk_ops_vote,
3293 CLK_INIT(gcc_vfe_tbu_clk.c),
3294 },
3295};
3296
3297static struct branch_clk gcc_usb2a_phy_sleep_clk = {
3298 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
3299 .has_sibling = 1,
3300 .base = &virt_bases[GCC_BASE],
3301 .c = {
3302 .dbg_name = "gcc_usb2a_phy_sleep_clk",
3303 .ops = &clk_ops_branch,
3304 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
3305 },
3306};
3307
3308static struct branch_clk gcc_usb_hs_phy_cfg_ahb_clk = {
3309 .cbcr_reg = USB_HS_PHY_CFG_AHB_CBCR,
3310 .has_sibling = 1,
3311 .base = &virt_bases[GCC_BASE],
3312 .c = {
3313 .dbg_name = "gcc_usb_hs_phy_cfg_ahb_clk",
3314 .ops = &clk_ops_branch,
3315 CLK_INIT(gcc_usb_hs_phy_cfg_ahb_clk.c),
3316 },
3317};
3318
3319static struct branch_clk gcc_usb_fs_ahb_clk = {
3320 .cbcr_reg = USB_FS_AHB_CBCR,
3321 .has_sibling = 1,
3322 .base = &virt_bases[GCC_BASE],
3323 .c = {
3324 .dbg_name = "gcc_usb_fs_ahb_clk",
3325 .ops = &clk_ops_branch,
3326 CLK_INIT(gcc_usb_fs_ahb_clk.c),
3327 },
3328};
3329
3330static struct branch_clk gcc_usb_fs_ic_clk = {
3331 .cbcr_reg = USB_FS_IC_CBCR,
3332 .has_sibling = 0,
3333 .base = &virt_bases[GCC_BASE],
3334 .c = {
3335 .dbg_name = "gcc_usb_fs_ic_clk",
3336 .parent = &usb_fs_ic_clk_src.c,
3337 .ops = &clk_ops_branch,
3338 CLK_INIT(gcc_usb_fs_ic_clk.c),
3339 },
3340};
3341
3342static struct branch_clk gcc_usb_fs_system_clk = {
3343 .cbcr_reg = USB_FS_SYSTEM_CBCR,
3344 .bcr_reg = USB_FS_BCR,
3345 .has_sibling = 0,
3346 .base = &virt_bases[GCC_BASE],
3347 .c = {
3348 .dbg_name = "gcc_usb_fs_system_clk",
3349 .parent = &usb_fs_system_clk_src.c,
3350 .ops = &clk_ops_branch,
3351 CLK_INIT(gcc_usb_fs_system_clk.c),
3352 },
3353};
3354
3355static struct branch_clk gcc_usb_hs_ahb_clk = {
3356 .cbcr_reg = USB_HS_AHB_CBCR,
3357 .has_sibling = 1,
3358 .base = &virt_bases[GCC_BASE],
3359 .c = {
3360 .dbg_name = "gcc_usb_hs_ahb_clk",
3361 .ops = &clk_ops_branch,
3362 CLK_INIT(gcc_usb_hs_ahb_clk.c),
3363 },
3364};
3365
3366static struct branch_clk gcc_usb_hs_system_clk = {
3367 .cbcr_reg = USB_HS_SYSTEM_CBCR,
3368 .bcr_reg = USB_HS_BCR,
3369 .has_sibling = 0,
3370 .base = &virt_bases[GCC_BASE],
3371 .c = {
3372 .dbg_name = "gcc_usb_hs_system_clk",
3373 .parent = &usb_hs_system_clk_src.c,
3374 .ops = &clk_ops_branch,
3375 CLK_INIT(gcc_usb_hs_system_clk.c),
3376 },
3377};
3378
3379static struct reset_clk gcc_usb2_hs_phy_only_clk = {
3380 .reset_reg = USB2_HS_PHY_ONLY_BCR,
3381 .base = &virt_bases[GCC_BASE],
3382 .c = {
3383 .dbg_name = "gcc_usb2_hs_phy_only_clk",
3384 .ops = &clk_ops_rst,
3385 CLK_INIT(gcc_usb2_hs_phy_only_clk.c),
3386 },
3387};
3388
3389static struct reset_clk gcc_qusb2_phy_clk = {
3390 .reset_reg = QUSB2_PHY_BCR,
3391 .base = &virt_bases[GCC_BASE],
3392 .c = {
3393 .dbg_name = "gcc_qusb2_phy_clk",
3394 .ops = &clk_ops_rst,
3395 CLK_INIT(gcc_qusb2_phy_clk.c),
3396 },
3397};
3398
3399static struct branch_clk gcc_venus0_ahb_clk = {
3400 .cbcr_reg = VENUS0_AHB_CBCR,
3401 .has_sibling = 1,
3402 .base = &virt_bases[GCC_BASE],
3403 .c = {
3404 .dbg_name = "gcc_venus0_ahb_clk",
3405 .ops = &clk_ops_branch,
3406 CLK_INIT(gcc_venus0_ahb_clk.c),
3407 },
3408};
3409
3410static struct branch_clk gcc_venus0_axi_clk = {
3411 .cbcr_reg = VENUS0_AXI_CBCR,
3412 .has_sibling = 1,
3413 .base = &virt_bases[GCC_BASE],
3414 .c = {
3415 .dbg_name = "gcc_venus0_axi_clk",
3416 .ops = &clk_ops_branch,
3417 CLK_INIT(gcc_venus0_axi_clk.c),
3418 },
3419};
3420
3421static struct branch_clk gcc_venus0_core0_vcodec0_clk = {
3422 .cbcr_reg = VENUS0_CORE0_VCODEC0_CBCR,
3423 .has_sibling = 1,
3424 .base = &virt_bases[GCC_BASE],
3425 .c = {
3426 .dbg_name = "gcc_venus0_core0_vcodec0_clk",
3427 .parent = &vcodec0_clk_src.c,
3428 .ops = &clk_ops_branch,
3429 CLK_INIT(gcc_venus0_core0_vcodec0_clk.c),
3430 },
3431};
3432
3433static struct branch_clk gcc_venus0_core1_vcodec0_clk = {
3434 .cbcr_reg = VENUS0_CORE1_VCODEC0_CBCR,
3435 .has_sibling = 1,
3436 .base = &virt_bases[GCC_BASE],
3437 .c = {
3438 .dbg_name = "gcc_venus0_core1_vcodec0_clk",
3439 .parent = &vcodec0_clk_src.c,
3440 .ops = &clk_ops_branch,
3441 CLK_INIT(gcc_venus0_core1_vcodec0_clk.c),
3442 },
3443};
3444
3445static struct branch_clk gcc_venus0_vcodec0_clk = {
3446 .cbcr_reg = VENUS0_VCODEC0_CBCR,
3447 .has_sibling = 0,
3448 .base = &virt_bases[GCC_BASE],
3449 .c = {
3450 .dbg_name = "gcc_venus0_vcodec0_clk",
3451 .parent = &vcodec0_clk_src.c,
3452 .ops = &clk_ops_branch,
3453 CLK_INIT(gcc_venus0_vcodec0_clk.c),
3454 },
3455};
3456
3457static struct clk_ops clk_ops_debug_mux;
3458
3459static void __iomem *meas_base;
3460
3461static struct measure_clk apc0_m_clk = {
3462 .c = {
3463 .ops = &clk_ops_empty,
3464 .dbg_name = "apc0_m_clk",
3465 CLK_INIT(apc0_m_clk.c),
3466 },
3467};
3468
3469static struct measure_clk apc1_m_clk = {
3470 .c = {
3471 .ops = &clk_ops_empty,
3472 .dbg_name = "apc1_m_clk",
3473 CLK_INIT(apc1_m_clk.c),
3474 },
3475};
3476
3477static struct measure_clk cci_m_clk = {
3478 .c = {
3479 .ops = &clk_ops_empty,
3480 .dbg_name = "cci_m_clk",
3481 CLK_INIT(cci_m_clk.c),
3482 },
3483};
3484
3485static struct mux_clk apss_debug_ter_mux = {
3486 .ops = &mux_reg_ops,
3487 .mask = 0x3,
3488 .shift = 8,
3489 MUX_SRC_LIST(
3490 {&apc0_m_clk.c, 0},
3491 {&apc1_m_clk.c, 1},
3492 {&cci_m_clk.c, 2},
3493 ),
3494 .base = &meas_base,
3495 .c = {
3496 .dbg_name = "apss_debug_ter_mux",
3497 .ops = &clk_ops_gen_mux,
3498 CLK_INIT(apss_debug_ter_mux.c),
3499 },
3500};
3501
3502static struct mux_clk apss_debug_sec_mux = {
3503 .ops = &mux_reg_ops,
3504 .mask = 0x7,
3505 .shift = 12,
3506 MUX_SRC_LIST(
3507 {&apss_debug_ter_mux.c, 0},
3508 ),
3509 MUX_REC_SRC_LIST(
3510 &apss_debug_ter_mux.c,
3511 ),
3512 .base = &meas_base,
3513 .c = {
3514 .dbg_name = "apss_debug_sec_mux",
3515 .ops = &clk_ops_gen_mux,
3516 CLK_INIT(apss_debug_sec_mux.c),
3517 },
3518};
3519
3520static struct mux_clk apss_debug_pri_mux = {
3521 .ops = &mux_reg_ops,
3522 .mask = 0x3,
3523 .shift = 16,
3524 MUX_SRC_LIST(
3525 {&apss_debug_sec_mux.c, 0},
3526 ),
3527 MUX_REC_SRC_LIST(
3528 &apss_debug_sec_mux.c,
3529 ),
3530 .base = &meas_base,
3531 .c = {
3532 .dbg_name = "apss_debug_pri_mux",
3533 .ops = &clk_ops_gen_mux,
3534 CLK_INIT(apss_debug_pri_mux.c),
3535 },
3536};
3537
3538static struct measure_clk_data debug_mux_priv = {
3539 .cxo = &xo_clk_src.c,
3540 .plltest_reg = GCC_PLLTEST_PAD_CFG,
3541 .plltest_val = 0x51A00,
3542 .xo_div4_cbcr = GCC_XO_DIV4_CBCR,
3543 .ctl_reg = CLOCK_FRQ_MEASURE_CTL,
3544 .status_reg = CLOCK_FRQ_MEASURE_STATUS,
3545 .base = &virt_bases[GCC_BASE],
3546};
3547
3548static struct mux_clk gcc_debug_mux = {
3549 .priv = &debug_mux_priv,
3550 .ops = &mux_reg_ops,
3551 .offset = GCC_DEBUG_CLK_CTL,
3552 .mask = 0x1FF,
3553 .en_offset = GCC_DEBUG_CLK_CTL,
3554 .en_mask = BIT(16),
3555 .base = &virt_bases[GCC_BASE],
3556 MUX_REC_SRC_LIST(
3557 &apss_debug_pri_mux.c,
3558 ),
3559 MUX_SRC_LIST(
3560 { &apss_debug_pri_mux.c, 0x016A},
3561 { &snoc_clk.c, 0x0000 },
3562 { &sysmmnoc_clk.c, 0x0001 },
3563 { &pnoc_clk.c, 0x0008 },
3564 { &bimc_clk.c, 0x0154 },
3565 { &gcc_gp1_clk.c, 0x0010 },
3566 { &gcc_gp2_clk.c, 0x0011 },
3567 { &gcc_gp3_clk.c, 0x0012 },
3568 { &gcc_bimc_gfx_clk.c, 0x002d },
3569 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3570 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3571 { &gcc_apss_tcu_clk.c, 0x0050 },
3572 { &gcc_mdp_tbu_clk.c, 0x0051 },
3573 { &gcc_gfx_tbu_clk.c, 0x0052 },
3574 { &gcc_gfx_tcu_clk.c, 0x0053 },
3575 { &gcc_venus_tbu_clk.c, 0x0054 },
3576 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3577 { &gcc_vfe_tbu_clk.c, 0x005a },
3578 { &gcc_smmu_cfg_clk.c, 0x005b },
3579 { &gcc_jpeg_tbu_clk.c, 0x005c },
3580 { &gcc_usb_hs_system_clk.c, 0x0060 },
3581 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3582 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3583 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3584 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3585 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3586 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3587 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3588 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3589 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3590 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3591 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3592 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3593 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3594 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3595 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3596 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3597 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3598 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3599 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3600 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3601 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3602 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3603 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3604 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3605 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3606 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3607 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3608 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3609 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3610 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3611 { &gcc_camss_ahb_clk.c, 0x00a8 },
3612 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3613 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3614 { &gcc_camss_gp0_clk.c, 0x00ab },
3615 { &gcc_camss_gp1_clk.c, 0x00ac },
3616 { &gcc_camss_mclk0_clk.c, 0x00ad },
3617 { &gcc_camss_mclk1_clk.c, 0x00ae },
3618 { &gcc_camss_cci_clk.c, 0x00af },
3619 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3620 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3621 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3622 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3623 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3624 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3625 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3626 { &gcc_camss_cpp_clk.c, 0x00b9 },
3627 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3628 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3629 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3630 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3631 { &gcc_camss_csi0_clk.c, 0x00c0 },
3632 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3633 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3634 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3635 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3636 { &gcc_camss_csi1_clk.c, 0x00c5 },
3637 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3638 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3639 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3640 { &gcc_pdm2_clk.c, 0x00d2 },
3641 { &gcc_prng_ahb_clk.c, 0x00d8 },
3642 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3643 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3644 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3645 { &gcc_camss_csi2_clk.c, 0x00e3 },
3646 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3647 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3648 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3649 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3650 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3651 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3652 { &gcc_usb_fs_ahb_clk.c, 0x00f1 },
3653 { &gcc_usb_fs_ic_clk.c, 0x00f4 },
3654 { &gcc_crypto_clk.c, 0x0138 },
3655 { &gcc_crypto_axi_clk.c, 0x0139 },
3656 { &gcc_crypto_ahb_clk.c, 0x013a },
3657 { &gcc_bimc_gpu_clk.c, 0x0157 },
3658 { &gcc_ipa_tbu_clk.c, 0x0198 },
3659 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3660 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3661 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3662 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3663 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3664 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3665 { &gcc_venus0_core1_vcodec0_clk.c, 0x01b9 },
3666 { &gcc_camss_mclk2_clk.c, 0x01bd },
3667 { &gcc_oxili_timer_clk.c, 0x01e9 },
3668 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3669 { &gcc_oxili_ahb_clk.c, 0x01eb },
3670 { &gcc_oxili_gmem_clk.c, 0x01f0 },
3671 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3672 { &gcc_venus0_axi_clk.c, 0x01f2 },
3673 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3674 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3675 { &gcc_mdss_axi_clk.c, 0x01f7 },
3676 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3677 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3678 { &gcc_mdss_vsync_clk.c, 0x01fb },
3679 { &gcc_mdss_byte0_clk.c, 0x01fc },
3680 { &gcc_mdss_esc0_clk.c, 0x01fd },
3681 { &wcnss_m_clk.c, 0x0ec },
3682 ),
3683 .c = {
3684 .dbg_name = "gcc_debug_mux",
3685 .ops = &clk_ops_debug_mux,
3686 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3687 CLK_INIT(gcc_debug_mux.c),
3688 },
3689};
3690
3691static struct mux_clk gcc_debug_mux_8937 = {
3692 .priv = &debug_mux_priv,
3693 .ops = &mux_reg_ops,
3694 .offset = GCC_DEBUG_CLK_CTL,
3695 .mask = 0x1FF,
3696 .en_offset = GCC_DEBUG_CLK_CTL,
3697 .en_mask = BIT(16),
3698 .base = &virt_bases[GCC_BASE],
3699 MUX_REC_SRC_LIST(
3700 &apss_debug_pri_mux.c,
3701 ),
3702 MUX_SRC_LIST(
3703 { &apss_debug_pri_mux.c, 0x016A},
3704 { &snoc_clk.c, 0x0000 },
3705 { &sysmmnoc_clk.c, 0x0001 },
3706 { &pnoc_clk.c, 0x0008 },
3707 { &bimc_clk.c, 0x015A },
3708 { &ipa_clk.c, 0x1B0 },
3709 { &gcc_gp1_clk.c, 0x0010 },
3710 { &gcc_gp2_clk.c, 0x0011 },
3711 { &gcc_gp3_clk.c, 0x0012 },
3712 { &gcc_bimc_gfx_clk.c, 0x002d },
3713 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3714 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3715 { &gcc_qdss_dap_clk.c, 0x0049 },
3716 { &gcc_apss_tcu_clk.c, 0x0050 },
3717 { &gcc_mdp_tbu_clk.c, 0x0051 },
3718 { &gcc_gfx_tbu_clk.c, 0x0052 },
3719 { &gcc_gfx_tcu_clk.c, 0x0053 },
3720 { &gcc_venus_tbu_clk.c, 0x0054 },
3721 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3722 { &gcc_vfe_tbu_clk.c, 0x005a },
3723 { &gcc_smmu_cfg_clk.c, 0x005b },
3724 { &gcc_jpeg_tbu_clk.c, 0x005c },
3725 { &gcc_usb_hs_system_clk.c, 0x0060 },
3726 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3727 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3728 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3729 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3730 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3731 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3732 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3733 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3734 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3735 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3736 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3737 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3738 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3739 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3740 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3741 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3742 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3743 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3744 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3745 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3746 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3747 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3748 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3749 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3750 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3751 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3752 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3753 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3754 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3755 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3756 { &gcc_camss_ahb_clk.c, 0x00a8 },
3757 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3758 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3759 { &gcc_camss_gp0_clk.c, 0x00ab },
3760 { &gcc_camss_gp1_clk.c, 0x00ac },
3761 { &gcc_camss_mclk0_clk.c, 0x00ad },
3762 { &gcc_camss_mclk1_clk.c, 0x00ae },
3763 { &gcc_camss_cci_clk.c, 0x00af },
3764 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3765 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3766 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3767 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3768 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3769 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3770 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3771 { &gcc_camss_cpp_clk.c, 0x00b9 },
3772 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3773 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3774 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3775 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3776 { &gcc_camss_csi0_clk.c, 0x00c0 },
3777 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3778 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3779 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3780 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3781 { &gcc_camss_csi1_clk.c, 0x00c5 },
3782 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3783 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3784 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3785 { &gcc_pdm2_clk.c, 0x00d2 },
3786 { &gcc_prng_ahb_clk.c, 0x00d8 },
3787 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3788 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3789 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3790 { &gcc_camss_csi2_clk.c, 0x00e3 },
3791 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3792 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3793 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3794 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3795 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3796 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3797 { &gcc_crypto_clk.c, 0x0138 },
3798 { &gcc_crypto_axi_clk.c, 0x0139 },
3799 { &gcc_crypto_ahb_clk.c, 0x013a },
3800 { &gcc_bimc_gpu_clk.c, 0x0157 },
3801 { &gcc_ipa_tbu_clk.c, 0x0198 },
3802 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3803 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3804 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3805 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3806 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3807 { &gcc_camss_cpp_axi_clk.c, 0x01a4 },
3808 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3809 { &gcc_dcc_clk.c, 0x01b9 },
3810 { &gcc_camss_mclk2_clk.c, 0x01bd },
3811 { &gcc_oxili_timer_clk.c, 0x01e9 },
3812 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3813 { &gcc_oxili_aon_clk.c, 0x00ee },
3814 { &gcc_oxili_ahb_clk.c, 0x01eb },
3815 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3816 { &gcc_venus0_axi_clk.c, 0x01f2 },
3817 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3818 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3819 { &gcc_mdss_axi_clk.c, 0x01f7 },
3820 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3821 { &gcc_mdss_pclk1_clk.c, 0x01e3 },
3822 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3823 { &gcc_mdss_vsync_clk.c, 0x01fb },
3824 { &gcc_mdss_byte0_clk.c, 0x01fc },
3825 { &gcc_mdss_byte1_clk.c, 0x01e4 },
3826 { &gcc_mdss_esc0_clk.c, 0x01fd },
3827 { &gcc_mdss_esc1_clk.c, 0x01e5 },
3828 { &wcnss_m_clk.c, 0x0ec },
3829 ),
3830 .c = {
3831 .dbg_name = "gcc_debug_mux_8937",
3832 .ops = &clk_ops_debug_mux,
3833 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3834 CLK_INIT(gcc_debug_mux_8937.c),
3835 },
3836};
3837
3838/* Clock lookup */
3839static struct clk_lookup msm_clocks_lookup_common[] = {
3840 /* RPM clocks */
3841 CLK_LIST(xo_clk_src),
3842 CLK_LIST(xo_a_clk_src),
3843 CLK_LIST(xo_otg_clk),
3844 CLK_LIST(xo_lpm_clk),
3845 CLK_LIST(xo_pil_mss_clk),
3846 CLK_LIST(xo_pil_pronto_clk),
3847 CLK_LIST(xo_wlan_clk),
3848 CLK_LIST(xo_pil_lpass_clk),
3849
3850 CLK_LIST(sysmmnoc_msmbus_clk),
3851 CLK_LIST(snoc_msmbus_clk),
3852 CLK_LIST(snoc_msmbus_a_clk),
3853 CLK_LIST(sysmmnoc_msmbus_a_clk),
3854 CLK_LIST(pnoc_msmbus_clk),
3855 CLK_LIST(pnoc_msmbus_a_clk),
3856 CLK_LIST(bimc_msmbus_clk),
3857 CLK_LIST(bimc_msmbus_a_clk),
3858 CLK_LIST(pnoc_keepalive_a_clk),
3859
3860 CLK_LIST(pnoc_usb_a_clk),
3861 CLK_LIST(snoc_usb_a_clk),
3862 CLK_LIST(bimc_usb_a_clk),
3863 CLK_LIST(pnoc_usb_clk),
3864 CLK_LIST(snoc_usb_clk),
3865 CLK_LIST(bimc_usb_clk),
3866
3867 CLK_LIST(snoc_wcnss_a_clk),
3868 CLK_LIST(bimc_wcnss_a_clk),
3869
3870 CLK_LIST(qdss_clk),
3871 CLK_LIST(qdss_a_clk),
3872
3873 CLK_LIST(snoc_clk),
3874 CLK_LIST(sysmmnoc_clk),
3875 CLK_LIST(pnoc_clk),
3876 CLK_LIST(bimc_clk),
3877 CLK_LIST(snoc_a_clk),
3878 CLK_LIST(sysmmnoc_a_clk),
3879 CLK_LIST(pnoc_a_clk),
3880 CLK_LIST(bimc_a_clk),
3881
3882 CLK_LIST(bb_clk1),
3883 CLK_LIST(bb_clk1_a),
3884 CLK_LIST(bb_clk2),
3885 CLK_LIST(bb_clk2_a),
3886 CLK_LIST(rf_clk2),
3887 CLK_LIST(rf_clk2_a),
3888 CLK_LIST(div_clk2),
3889 CLK_LIST(div_clk2_a),
3890
3891 CLK_LIST(bb_clk1_pin),
3892 CLK_LIST(bb_clk1_a_pin),
3893 CLK_LIST(bb_clk2_pin),
3894 CLK_LIST(bb_clk2_a_pin),
3895
3896 CLK_LIST(gpll0_clk_src),
3897 CLK_LIST(gpll0_ao_clk_src),
3898 CLK_LIST(gpll6_clk_src),
3899 CLK_LIST(gpll4_clk_src),
3900 CLK_LIST(gpll3_clk_src),
3901 CLK_LIST(a53ss_c1_pll),
3902 CLK_LIST(gcc_blsp1_ahb_clk),
3903 CLK_LIST(gcc_blsp2_ahb_clk),
3904 CLK_LIST(gcc_boot_rom_ahb_clk),
3905 CLK_LIST(gcc_crypto_ahb_clk),
3906 CLK_LIST(gcc_crypto_axi_clk),
3907 CLK_LIST(gcc_crypto_clk),
3908 CLK_LIST(gcc_prng_ahb_clk),
3909 CLK_LIST(gcc_cpp_tbu_clk),
3910 CLK_LIST(gcc_apss_tcu_clk),
3911 CLK_LIST(gcc_jpeg_tbu_clk),
3912 CLK_LIST(gcc_mdp_tbu_clk),
3913 CLK_LIST(gcc_smmu_cfg_clk),
3914 CLK_LIST(gcc_venus_tbu_clk),
3915 CLK_LIST(gcc_vfe1_tbu_clk),
3916 CLK_LIST(gcc_vfe_tbu_clk),
3917 CLK_LIST(camss_top_ahb_clk_src),
3918 CLK_LIST(apss_ahb_clk_src),
3919 CLK_LIST(csi0_clk_src),
3920 CLK_LIST(csi1_clk_src),
3921 CLK_LIST(csi2_clk_src),
3922 CLK_LIST(vcodec0_clk_src),
3923 CLK_LIST(vfe0_clk_src),
3924 CLK_LIST(vfe1_clk_src),
3925 CLK_LIST(gfx3d_clk_src),
3926 CLK_LIST(blsp1_qup2_i2c_apps_clk_src),
3927 CLK_LIST(blsp1_qup2_spi_apps_clk_src),
3928 CLK_LIST(blsp1_qup3_i2c_apps_clk_src),
3929 CLK_LIST(blsp1_qup3_spi_apps_clk_src),
3930 CLK_LIST(blsp1_qup4_i2c_apps_clk_src),
3931 CLK_LIST(blsp1_qup4_spi_apps_clk_src),
3932 CLK_LIST(blsp1_uart1_apps_clk_src),
3933 CLK_LIST(blsp1_uart2_apps_clk_src),
3934 CLK_LIST(blsp2_qup1_i2c_apps_clk_src),
3935 CLK_LIST(blsp2_qup1_spi_apps_clk_src),
3936 CLK_LIST(blsp2_qup2_i2c_apps_clk_src),
3937 CLK_LIST(blsp2_qup2_spi_apps_clk_src),
3938 CLK_LIST(blsp2_qup3_i2c_apps_clk_src),
3939 CLK_LIST(blsp2_qup3_spi_apps_clk_src),
3940 CLK_LIST(blsp2_uart1_apps_clk_src),
3941 CLK_LIST(blsp2_uart2_apps_clk_src),
3942 CLK_LIST(cci_clk_src),
3943 CLK_LIST(cpp_clk_src),
3944 CLK_LIST(camss_gp0_clk_src),
3945 CLK_LIST(camss_gp1_clk_src),
3946 CLK_LIST(jpeg0_clk_src),
3947 CLK_LIST(mclk0_clk_src),
3948 CLK_LIST(mclk1_clk_src),
3949 CLK_LIST(mclk2_clk_src),
3950 CLK_LIST(csi0phytimer_clk_src),
3951 CLK_LIST(csi1phytimer_clk_src),
3952 CLK_LIST(crypto_clk_src),
3953 CLK_LIST(gp1_clk_src),
3954 CLK_LIST(gp2_clk_src),
3955 CLK_LIST(gp3_clk_src),
3956 CLK_LIST(esc0_clk_src),
3957 CLK_LIST(mdp_clk_src),
3958 CLK_LIST(vsync_clk_src),
3959 CLK_LIST(pdm2_clk_src),
3960 CLK_LIST(sdcc1_apps_clk_src),
3961 CLK_LIST(sdcc1_ice_core_clk_src),
3962 CLK_LIST(sdcc2_apps_clk_src),
3963 CLK_LIST(usb_hs_system_clk_src),
3964 CLK_LIST(gcc_bimc_gpu_clk),
3965 CLK_LIST(gcc_blsp1_qup2_i2c_apps_clk),
3966 CLK_LIST(gcc_blsp1_qup2_spi_apps_clk),
3967 CLK_LIST(gcc_blsp1_qup3_i2c_apps_clk),
3968 CLK_LIST(gcc_blsp1_qup3_spi_apps_clk),
3969 CLK_LIST(gcc_blsp1_qup4_i2c_apps_clk),
3970 CLK_LIST(gcc_blsp1_qup4_spi_apps_clk),
3971 CLK_LIST(gcc_blsp1_uart1_apps_clk),
3972 CLK_LIST(gcc_blsp1_uart2_apps_clk),
3973 CLK_LIST(gcc_blsp2_qup1_i2c_apps_clk),
3974 CLK_LIST(gcc_blsp2_qup1_spi_apps_clk),
3975 CLK_LIST(gcc_blsp2_qup2_i2c_apps_clk),
3976 CLK_LIST(gcc_blsp2_qup2_spi_apps_clk),
3977 CLK_LIST(gcc_blsp2_qup3_i2c_apps_clk),
3978 CLK_LIST(gcc_blsp2_qup3_spi_apps_clk),
3979 CLK_LIST(gcc_blsp2_uart1_apps_clk),
3980 CLK_LIST(gcc_blsp2_uart2_apps_clk),
3981 CLK_LIST(gcc_camss_cci_ahb_clk),
3982 CLK_LIST(gcc_camss_cci_clk),
3983 CLK_LIST(gcc_camss_cpp_ahb_clk),
3984 CLK_LIST(gcc_camss_cpp_axi_clk),
3985 CLK_LIST(gcc_camss_cpp_clk),
3986 CLK_LIST(gcc_camss_csi0_ahb_clk),
3987 CLK_LIST(gcc_camss_csi0_clk),
3988 CLK_LIST(gcc_camss_csi0phy_clk),
3989 CLK_LIST(gcc_camss_csi0pix_clk),
3990 CLK_LIST(gcc_camss_csi0rdi_clk),
3991 CLK_LIST(gcc_camss_csi1_ahb_clk),
3992 CLK_LIST(gcc_camss_csi1_clk),
3993 CLK_LIST(gcc_camss_csi1phy_clk),
3994 CLK_LIST(gcc_camss_csi1pix_clk),
3995 CLK_LIST(gcc_camss_csi1rdi_clk),
3996 CLK_LIST(gcc_camss_csi2_ahb_clk),
3997 CLK_LIST(gcc_camss_csi2_clk),
3998 CLK_LIST(gcc_camss_csi2phy_clk),
3999 CLK_LIST(gcc_camss_csi2pix_clk),
4000 CLK_LIST(gcc_camss_csi2rdi_clk),
4001 CLK_LIST(gcc_camss_csi_vfe0_clk),
4002 CLK_LIST(gcc_camss_csi_vfe1_clk),
4003 CLK_LIST(gcc_camss_gp0_clk),
4004 CLK_LIST(gcc_camss_gp1_clk),
4005 CLK_LIST(gcc_camss_ispif_ahb_clk),
4006 CLK_LIST(gcc_camss_jpeg0_clk),
4007 CLK_LIST(gcc_camss_jpeg_ahb_clk),
4008 CLK_LIST(gcc_camss_jpeg_axi_clk),
4009 CLK_LIST(gcc_camss_mclk0_clk),
4010 CLK_LIST(gcc_camss_mclk1_clk),
4011 CLK_LIST(gcc_camss_mclk2_clk),
4012 CLK_LIST(gcc_camss_micro_ahb_clk),
4013 CLK_LIST(gcc_camss_csi0phytimer_clk),
4014 CLK_LIST(gcc_camss_csi1phytimer_clk),
4015 CLK_LIST(gcc_camss_ahb_clk),
4016 CLK_LIST(gcc_camss_top_ahb_clk),
4017 CLK_LIST(gcc_camss_vfe0_clk),
4018 CLK_LIST(gcc_camss_vfe_ahb_clk),
4019 CLK_LIST(gcc_camss_vfe_axi_clk),
4020 CLK_LIST(gcc_camss_vfe1_ahb_clk),
4021 CLK_LIST(gcc_camss_vfe1_axi_clk),
4022 CLK_LIST(gcc_camss_vfe1_clk),
4023 CLK_LIST(gcc_gp1_clk),
4024 CLK_LIST(gcc_gp2_clk),
4025 CLK_LIST(gcc_gp3_clk),
4026 CLK_LIST(gcc_mdss_ahb_clk),
4027 CLK_LIST(gcc_mdss_axi_clk),
4028 CLK_LIST(gcc_mdss_esc0_clk),
4029 CLK_LIST(gcc_mdss_mdp_clk),
4030 CLK_LIST(gcc_mdss_vsync_clk),
4031 CLK_LIST(gcc_mss_cfg_ahb_clk),
4032 CLK_LIST(gcc_mss_q6_bimc_axi_clk),
4033 CLK_LIST(gcc_bimc_gfx_clk),
4034 CLK_LIST(gcc_oxili_ahb_clk),
4035 CLK_LIST(gcc_oxili_gfx3d_clk),
4036 CLK_LIST(gcc_pdm2_clk),
4037 CLK_LIST(gcc_pdm_ahb_clk),
4038 CLK_LIST(gcc_sdcc1_ahb_clk),
4039 CLK_LIST(gcc_sdcc1_apps_clk),
4040 CLK_LIST(gcc_sdcc1_ice_core_clk),
4041 CLK_LIST(gcc_sdcc2_ahb_clk),
4042 CLK_LIST(gcc_sdcc2_apps_clk),
4043 CLK_LIST(gcc_usb2a_phy_sleep_clk),
4044 CLK_LIST(gcc_usb_hs_phy_cfg_ahb_clk),
4045 CLK_LIST(gcc_usb_hs_ahb_clk),
4046 CLK_LIST(gcc_usb_hs_system_clk),
4047 CLK_LIST(gcc_venus0_ahb_clk),
4048 CLK_LIST(gcc_venus0_axi_clk),
4049 CLK_LIST(gcc_venus0_core0_vcodec0_clk),
4050 CLK_LIST(gcc_venus0_vcodec0_clk),
4051
4052 /* Reset clks */
4053 CLK_LIST(gcc_usb2_hs_phy_only_clk),
4054 CLK_LIST(gcc_qusb2_phy_clk),
4055
4056 /* WCNSS Debug */
4057 CLK_LIST(wcnss_m_clk),
4058};
4059
4060static struct clk_lookup msm_clocks_lookup_8952[] = {
4061 CLK_LIST(a53ss_c0_pll),
4062 CLK_LIST(a53ss_cci_pll),
4063 CLK_LIST(ipa_clk),
4064 CLK_LIST(ipa_a_clk),
4065 CLK_LIST(gpll0_clk_src_8952),
4066 CLK_LIST(gpll0_ao_clk_src_8952),
4067 CLK_LIST(gcc_oxili_gmem_clk),
4068 CLK_LIST(usb_fs_ic_clk_src),
4069 CLK_LIST(gcc_usb_fs_ic_clk),
4070 CLK_LIST(usb_fs_system_clk_src),
4071 CLK_LIST(gcc_usb_fs_system_clk),
4072 CLK_LIST(gcc_gfx_tcu_clk),
4073 CLK_LIST(gcc_gfx_tbu_clk),
4074 CLK_LIST(gcc_gtcu_ahb_clk),
4075 CLK_LIST(gcc_ipa_tbu_clk),
4076 CLK_LIST(gcc_usb_fs_ahb_clk),
4077 CLK_LIST(gcc_venus0_core1_vcodec0_clk),
4078 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4079 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4080 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4081 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4082 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4083 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4084 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4085 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4086 CLK_LIST(gcc_oxili_timer_clk),
4087};
4088
4089static struct clk_lookup msm_clocks_lookup_8937[] = {
4090 CLK_LIST(gpll0_clk_src_8937),
4091 CLK_LIST(gpll0_ao_clk_src_8937),
4092 CLK_LIST(gpll0_sleep_clk_src),
4093 CLK_LIST(a53ss_c0_pll),
4094 CLK_LIST(esc1_clk_src),
4095 CLK_LIST(gcc_mdss_esc1_clk),
4096 CLK_LIST(gcc_dcc_clk),
4097 CLK_LIST(gcc_oxili_aon_clk),
4098 CLK_LIST(gcc_qdss_dap_clk),
4099 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4100 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4101 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4102 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4103 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4104 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4105 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4106 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4107 CLK_LIST(gcc_oxili_timer_clk),
4108};
4109
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4110static struct clk_lookup msm_clocks_lookup_sdm429[] = {
4111 CLK_LIST(gpll0_clk_src_8937),
4112 CLK_LIST(gpll0_ao_clk_src_8937),
4113 CLK_LIST(gpll0_sleep_clk_src),
4114 CLK_LIST(esc1_clk_src),
4115 CLK_LIST(gcc_mdss_esc1_clk),
4116 CLK_LIST(gcc_dcc_clk),
4117 CLK_LIST(gcc_oxili_aon_clk),
4118 CLK_LIST(gcc_qdss_dap_clk),
4119 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4120 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4121 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4122 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4123 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4124 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4125 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4126 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4127 CLK_LIST(gcc_oxili_timer_clk),
4128};
4129
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4130static struct clk_lookup msm_clocks_lookup_8917[] = {
4131 CLK_LIST(gpll0_clk_src_8937),
4132 CLK_LIST(gpll0_ao_clk_src_8937),
4133 CLK_LIST(gpll0_sleep_clk_src),
4134 CLK_LIST(bimc_gpu_clk),
4135 CLK_LIST(bimc_gpu_a_clk),
4136 CLK_LIST(gcc_dcc_clk),
4137 CLK_LIST(gcc_qdss_dap_clk),
4138 CLK_LIST(gcc_gfx_tcu_clk),
4139 CLK_LIST(gcc_gfx_tbu_clk),
4140 CLK_LIST(gcc_gtcu_ahb_clk),
4141};
4142
4143static struct clk_lookup msm_clocks_lookup_8920[] = {
4144 CLK_LIST(gpll0_clk_src_8937),
4145 CLK_LIST(gpll0_ao_clk_src_8937),
4146 CLK_LIST(gpll0_sleep_clk_src),
4147 CLK_LIST(bimc_gpu_clk),
4148 CLK_LIST(bimc_gpu_a_clk),
4149 CLK_LIST(gcc_dcc_clk),
4150 CLK_LIST(gcc_qdss_dap_clk),
4151 CLK_LIST(gcc_gfx_tcu_clk),
4152 CLK_LIST(gcc_gfx_tbu_clk),
4153 CLK_LIST(gcc_gtcu_ahb_clk),
4154 CLK_LIST(ipa_clk),
4155 CLK_LIST(ipa_a_clk),
4156 CLK_LIST(gcc_ipa_tbu_clk),
4157};
4158
4159static struct clk_lookup msm_clocks_lookup_8940[] = {
4160 CLK_LIST(gpll0_clk_src_8937),
4161 CLK_LIST(gpll0_ao_clk_src_8937),
4162 CLK_LIST(gpll0_sleep_clk_src),
4163 CLK_LIST(a53ss_c0_pll),
4164 CLK_LIST(esc1_clk_src),
4165 CLK_LIST(gcc_mdss_esc1_clk),
4166 CLK_LIST(gcc_dcc_clk),
4167 CLK_LIST(gcc_oxili_aon_clk),
4168 CLK_LIST(gcc_qdss_dap_clk),
4169 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4170 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4171 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4172 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4173 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4174 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4175 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4176 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4177 CLK_LIST(gcc_oxili_timer_clk),
4178 CLK_LIST(ipa_clk),
4179 CLK_LIST(ipa_a_clk),
4180 CLK_LIST(gcc_ipa_tbu_clk),
4181};
4182
4183/* Please note that the order of reg-names is important */
4184static int get_mmio_addr(struct platform_device *pdev, u32 nbases)
4185{
4186 int i, count;
4187 const char *str;
4188 struct resource *res;
4189 struct device *dev = &pdev->dev;
4190
4191 count = of_property_count_strings(dev->of_node, "reg-names");
4192 if (count < nbases) {
4193 dev_err(dev, "missing reg-names property, expected %d strings\n",
4194 nbases);
4195 return -EINVAL;
4196 }
4197
4198 for (i = 0; i < nbases; i++) {
4199 of_property_read_string_index(dev->of_node, "reg-names", i,
4200 &str);
4201 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, str);
4202 if (!res) {
4203 dev_err(dev, "Unable to retrieve register base.\n");
4204 return -ENOMEM;
4205 }
4206
4207 virt_bases[i] = devm_ioremap(dev, res->start,
4208 resource_size(res));
4209 if (!virt_bases[i]) {
4210 dev_err(dev, "Failed to map in CC registers.\n");
4211 return -ENOMEM;
4212 }
4213 }
4214
4215 return 0;
4216}
4217
4218static const struct msm_reset_map gcc_8952_resets[] = {
4219 [GCC_CAMSS_MICRO_BCR] = {0x56008},
4220 [GCC_USB_FS_BCR] = {0x3F000},
4221 [GCC_USB_HS_BCR] = {0x41000},
4222 [GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034},
4223 [GCC_QUSB2_PHY_BCR] = {0x4103C},
4224};
4225
4226static void override_for_8917(int speed_bin)
4227{
4228 gpll3_clk_src.c.rate = 930000000;
4229
4230 OVERRIDE_FMAX3(csi0,
4231 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4232 /* Frequency Table same as 8937 */
4233 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4234 OVERRIDE_FMAX3(csi1,
4235 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4236 /* Frequency Table same as 8937 */
4237 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4238 OVERRIDE_FMAX3(csi2,
4239 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4240 /* Frequency Table same as 8937 */
4241 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4242
4243 OVERRIDE_FMAX5(vfe0,
4244 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4245 NOM_PLUS, 329140000, HIGH, 360000000);
4246 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8917);
4247 OVERRIDE_FMAX5(vfe1,
4248 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4249 NOM_PLUS, 329140000, HIGH, 360000000);
4250 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8917);
4251 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8917);
4252 OVERRIDE_FMAX5(vcodec0,
4253 LOWER, 200000000, LOW, 270000000, NOMINAL, 308570000,
4254 NOM_PLUS, 329140000, HIGH, 360000000);
4255 OVERRIDE_FMAX4(cpp,
4256 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4257 NOM_PLUS, 360000000);
4258 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8917);
4259 OVERRIDE_FMAX5(jpeg0,
4260 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4261 NOM_PLUS, 308570000, HIGH, 320000000);
4262 /* Frequency Table same as 8937 */
4263 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4264
4265 if (speed_bin) {
4266 OVERRIDE_FMAX5(gfx3d,
4267 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4268 NOM_PLUS, 523200000, HIGH, 650000000);
4269 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917_650MHz);
4270 } else {
4271 OVERRIDE_FMAX5(gfx3d,
4272 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4273 NOM_PLUS, 523200000, HIGH, 598000000);
4274 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917);
4275 }
4276
4277 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4278
4279 OVERRIDE_FTABLE(csi0phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4280 OVERRIDE_FMAX3(csi0phytimer, LOWER, 100000000, LOW, 200000000,
4281 NOMINAL, 266670000);
4282 OVERRIDE_FTABLE(csi1phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4283 OVERRIDE_FMAX3(csi1phytimer, LOWER, 100000000, LOW, 200000000,
4284 NOMINAL, 266670000);
4285 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4286 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4287 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4288
4289 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4290 /* Frequency Table same as 8937 */
4291 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4292 byte0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4293
4294 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4295 /* Frequency Table same as 8937 */
4296 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4297 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4298
4299 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 200000000, NOMINAL, 400000000);
4300 OVERRIDE_FTABLE(usb_hs_system, ftbl_gcc_usb_hs_system_clk, 8917);
4301 OVERRIDE_FMAX3(usb_hs_system, LOWER, 800000000, NOMINAL, 133333000,
4302 HIGH, 177780000);
4303}
4304
4305static void override_for_8937(int speed_bin)
4306{
4307 gpll3_clk_src.c.rate = 900000000;
4308 gpll3_clk_src.vco_tbl = p_vco_8937;
4309 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco_8937);
4310 OVERRIDE_FMAX2(gpll3, LOW, 800000000, NOMINAL, 1066000000);
4311
4312 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4313 OVERRIDE_FMAX3(csi0,
4314 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4315 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4316 OVERRIDE_FMAX3(csi1,
4317 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4318 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4319 OVERRIDE_FMAX3(csi2,
4320 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4321 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4322 OVERRIDE_FMAX4(vfe0,
4323 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4324 NOM_PLUS, 432000000);
4325 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8937);
4326 OVERRIDE_FMAX4(vfe1,
4327 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4328 NOM_PLUS, 432000000);
4329 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8937);
4330
4331 if (speed_bin) {
4332 OVERRIDE_FMAX6(gfx3d,
4333 LOWER, 216000000, LOW, 300000000,
4334 NOMINAL, 375000000, NOM_PLUS, 400000000,
4335 HIGH, 450000000, SUPER_TUR, 475000000);
4336 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937_475MHz);
4337 } else {
4338 OVERRIDE_FMAX5(gfx3d,
4339 LOWER, 216000000, LOW, 300000000,
4340 NOMINAL, 375000000, NOM_PLUS, 400000000,
4341 HIGH, 450000000);
4342 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937);
4343 }
4344
4345 OVERRIDE_FMAX5(cpp,
4346 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4347 NOM_PLUS, 342860000, HIGH, 360000000);
4348 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8937);
4349 OVERRIDE_FMAX5(jpeg0,
4350 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4351 NOM_PLUS, 308570000, HIGH, 320000000);
4352 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4353 OVERRIDE_FMAX2(csi0phytimer, LOWER, 100000000, LOW, 200000000);
4354 OVERRIDE_FMAX2(csi1phytimer, LOWER, 100000000, LOW, 200000000);
4355 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4356 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4357 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4358 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4359 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4360 OVERRIDE_FMAX2(byte1, LOWER, 125000000, NOMINAL, 187500000);
4361 byte0_clk_src.current_freq = ftbl_gcc_mdss_byte0_clk_8937;
4362 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4363 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4364 OVERRIDE_FMAX2(pclk1, LOWER, 166670000, NOMINAL, 250000000);
4365 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4366 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8937);
4367 OVERRIDE_FMAX5(vcodec0,
4368 LOWER, 166150000, LOW, 240000000, NOMINAL, 308570000,
4369 NOM_PLUS, 320000000, HIGH, 360000000);
4370 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 100000000,
4371 NOMINAL, 400000000);
4372}
4373
4374static void get_speed_bin(struct platform_device *pdev, int *bin)
4375{
4376 struct resource *res;
4377 void __iomem *base;
4378 u32 config_efuse;
4379
4380 *bin = 0;
4381
4382 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
4383 if (!res) {
4384 dev_info(&pdev->dev,
4385 "No GPU speed binning available. Defaulting to 0.\n");
4386 return;
4387 }
4388
4389 base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4390 if (!base) {
4391 dev_warn(&pdev->dev,
4392 "Unable to ioremap efuse reg address. Defaulting to 0.\n");
4393 return;
4394 }
4395
4396 config_efuse = readl_relaxed(base);
4397 devm_iounmap(&pdev->dev, base);
4398 *bin = (config_efuse >> 31) & 0x1;
4399
4400 dev_info(&pdev->dev, "GPU speed bin: %d\n", *bin);
4401}
4402
4403static int msm_gcc_probe(struct platform_device *pdev)
4404{
4405 struct resource *res;
4406 int ret;
4407 int speed_bin;
4408 u32 regval, nbases = N_BASES;
4409 bool compat_bin = false;
4410 bool compat_bin2 = false;
4411 bool compat_bin3 = false;
4412 bool compat_bin4 = false;
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4413 bool compat_bin5 = false;
4414 bool compat_bin6 = false;
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]4415 bool compat_bin7 = false;
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4416
4417 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4418 "qcom,gcc-8937");
4419
4420 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4421 "qcom,gcc-8917");
4422
4423 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4424 "qcom,gcc-8940");
4425
4426 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4427 "qcom,gcc-8920");
4428
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4429 compat_bin5 = of_device_is_compatible(pdev->dev.of_node,
4430 "qcom,gcc-sdm429");
4431
4432 compat_bin6 = of_device_is_compatible(pdev->dev.of_node,
4433 "qcom,gcc-sdm439");
4434
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]4435 compat_bin7 = of_device_is_compatible(pdev->dev.of_node,
4436 "qcom,gcc-qm215");
4437
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4438 ret = vote_bimc(&bimc_clk, INT_MAX);
4439 if (ret < 0)
4440 return ret;
4441
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]4442 if (compat_bin2 || compat_bin4 || compat_bin5 || compat_bin7)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4443 nbases = APCS_C0_PLL_BASE;
4444
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]4445 if (compat_bin5 || compat_bin6) {
4446 a53ss_c0_pll.c.ops = &clk_ops_acpu_pll;
4447 a53ss_c1_pll.c.ops = &clk_ops_acpu_pll;
4448 }
4449
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4450 ret = get_mmio_addr(pdev, nbases);
4451 if (ret)
4452 return ret;
4453
4454 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
4455 if (!res) {
4456 dev_err(&pdev->dev, "Register base not defined\n");
4457 return -ENOMEM;
4458 }
4459
4460 virt_bases[GCC_BASE] = devm_ioremap(&pdev->dev, res->start,
4461 resource_size(res));
4462 if (!virt_bases[GCC_BASE]) {
4463 dev_err(&pdev->dev, "Failed to ioremap CC registers\n");
4464 return -ENOMEM;
4465 }
4466
4467 vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");
4468 if (IS_ERR(vdd_dig.regulator[0])) {
4469 if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER))
4470 dev_err(&pdev->dev,
4471 "Unable to get vdd_dig regulator!!!\n");
4472 return PTR_ERR(vdd_dig.regulator[0]);
4473 }
4474
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]4475 if (!compat_bin2 && !compat_bin4 && !compat_bin5 && !compat_bin7) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4476 vdd_sr2_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4477 "vdd_sr2_pll");
4478 if (IS_ERR(vdd_sr2_pll.regulator[0])) {
4479 if (PTR_ERR(vdd_sr2_pll.regulator[0]) != -EPROBE_DEFER)
4480 dev_err(&pdev->dev,
4481 "Unable to get vdd_sr2_pll regulator!!!\n");
4482 return PTR_ERR(vdd_sr2_pll.regulator[0]);
4483 }
4484
4485 vdd_sr2_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4486 "vdd_sr2_dig");
4487 if (IS_ERR(vdd_sr2_pll.regulator[1])) {
4488 if (PTR_ERR(vdd_sr2_pll.regulator[1]) != -EPROBE_DEFER)
4489 dev_err(&pdev->dev,
4490 "Unable to get vdd_sr2_dig regulator!!!\n");
4491 return PTR_ERR(vdd_sr2_pll.regulator[1]);
4492 }
4493 }
4494
4495 vdd_hf_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4496 "vdd_hf_pll");
4497 if (IS_ERR(vdd_hf_pll.regulator[0])) {
4498 if (PTR_ERR(vdd_hf_pll.regulator[0]) != -EPROBE_DEFER)
4499 dev_err(&pdev->dev,
4500 "Unable to get vdd_sr2_pll regulator!!!\n");
4501 return PTR_ERR(vdd_hf_pll.regulator[0]);
4502 }
4503
4504 vdd_hf_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4505 "vdd_hf_dig");
4506 if (IS_ERR(vdd_hf_pll.regulator[1])) {
4507 if (PTR_ERR(vdd_hf_pll.regulator[1]) != -EPROBE_DEFER)
4508 dev_err(&pdev->dev,
4509 "Unable to get vdd_hf_dig regulator!!!\n");
4510 return PTR_ERR(vdd_hf_pll.regulator[1]);
4511 }
4512
4513 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
4514 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4515 regval |= BIT(0);
4516 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4517
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4518 if (compat_bin || compat_bin3 || compat_bin5 || compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4519 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4520 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4521 /* Oxili Ocmem in GX rail: OXILI_GMEM_CLAMP_IO */
4522 regval = readl_relaxed(GCC_REG_BASE(GX_DOMAIN_MISC));
4523 regval &= ~BIT(0);
4524 writel_relaxed(regval, GCC_REG_BASE(GX_DOMAIN_MISC));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4525
4526 if (compat_bin5 || compat_bin6)
4527 speed_bin = 0;
4528 else
4529 get_speed_bin(pdev, &speed_bin);
4530
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4531 override_for_8937(speed_bin);
4532
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4533 if (compat_bin5 || compat_bin6) {
4534 vdd_dig.num_levels = VDD_DIG_NUM_439;
4535 vdd_dig.cur_level = VDD_DIG_NUM_439;
4536 vdd_sr2_pll.num_levels = VDD_SR2_PLL_NUM_439;
4537 vdd_sr2_pll.cur_level = VDD_SR2_PLL_NUM_439;
4538 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_439;
4539 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_439;
4540
Odelu Kukatlaff4c6a02018-06-28 12:45:16 +0530[diff] [blame]4541 gpll3_clk_src.test_ctl_hi_val = 0x400000;
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4542 gpll3_clk_src.vco_tbl = p_vco;
4543 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco);
4544 gpll3_clk_src.c.fmax[VDD_DIG_LOW] = 800000000;
4545 gpll3_clk_src.c.fmax[VDD_DIG_NOMINAL] = 1400000000;
4546 gfx3d_clk_src.freq_tbl =
4547 ftbl_gcc_oxili_gfx3d_clk_sdm439;
4548
4549 gfx3d_clk_src.c.fmax[VDD_DIG_LOWER] = 320000000;
4550 gfx3d_clk_src.c.fmax[VDD_DIG_LOW] = 400000000;
4551 gfx3d_clk_src.c.fmax[VDD_DIG_NOMINAL] = 510000000;
4552 gfx3d_clk_src.c.fmax[VDD_DIG_NOM_PLUS] = 560000000;
4553 gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 650000000;
4554 }
4555
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4556 if (compat_bin3) {
4557 if (speed_bin) {
4558 gfx3d_clk_src.freq_tbl =
4559 ftbl_gcc_oxili_gfx3d_clk_8940_500MHz;
4560 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4561 500000000;
4562 } else {
4563 gfx3d_clk_src.freq_tbl =
4564 ftbl_gcc_oxili_gfx3d_clk_8937_475MHz;
4565 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4566 475000000;
4567 }
4568 }
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]4569 } else if (compat_bin2 || compat_bin4 || compat_bin7) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4570 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4571 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4572 vdd_dig.num_levels = VDD_DIG_NUM_8917;
4573 vdd_dig.cur_level = VDD_DIG_NUM_8917;
4574 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_8917;
4575 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_8917;
4576 get_speed_bin(pdev, &speed_bin);
4577 override_for_8917(speed_bin);
4578
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]4579 if (compat_bin7)
4580 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, qm215);
4581
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4582 if (compat_bin2) {
4583 blsp1_qup2_spi_apps_clk_src.freq_tbl =
4584 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4585 blsp1_qup3_spi_apps_clk_src.freq_tbl =
4586 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4587 blsp1_qup4_spi_apps_clk_src.freq_tbl =
4588 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4589 blsp2_qup1_spi_apps_clk_src.freq_tbl =
4590 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4591 blsp2_qup2_spi_apps_clk_src.freq_tbl =
4592 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4593 blsp2_qup3_spi_apps_clk_src.freq_tbl =
4594 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4595 }
4596 } else {
4597 gpll0_clk_src.c.parent = &gpll0_clk_src_8952.c;
4598 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8952.c;
4599 }
4600
4601 ret = of_msm_clock_register(pdev->dev.of_node,
4602 msm_clocks_lookup_common,
4603 ARRAY_SIZE(msm_clocks_lookup_common));
4604 if (ret)
4605 return ret;
4606
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4607 if (compat_bin || compat_bin6)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4608 ret = of_msm_clock_register(pdev->dev.of_node,
4609 msm_clocks_lookup_8937,
4610 ARRAY_SIZE(msm_clocks_lookup_8937));
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]4611 else if (compat_bin2 || compat_bin7)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4612 ret = of_msm_clock_register(pdev->dev.of_node,
4613 msm_clocks_lookup_8917,
4614 ARRAY_SIZE(msm_clocks_lookup_8917));
4615 else if (compat_bin3)
4616 ret = of_msm_clock_register(pdev->dev.of_node,
4617 msm_clocks_lookup_8940,
4618 ARRAY_SIZE(msm_clocks_lookup_8940));
4619 else if (compat_bin4)
4620 ret = of_msm_clock_register(pdev->dev.of_node,
4621 msm_clocks_lookup_8920,
4622 ARRAY_SIZE(msm_clocks_lookup_8920));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4623 else if (compat_bin5)
4624 ret = of_msm_clock_register(pdev->dev.of_node,
4625 msm_clocks_lookup_sdm429,
4626 ARRAY_SIZE(msm_clocks_lookup_sdm429));
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4627 else
4628 ret = of_msm_clock_register(pdev->dev.of_node,
4629 msm_clocks_lookup_8952,
4630 ARRAY_SIZE(msm_clocks_lookup_8952));
4631 if (ret)
4632 return ret;
4633
4634 ret = enable_rpm_scaling();
4635 if (ret)
4636 return ret;
4637
4638 clk_set_rate(&apss_ahb_clk_src.c, 19200000);
4639 clk_prepare_enable(&apss_ahb_clk_src.c);
4640
4641 /*
4642 * Hold an active set vote for PCNOC AHB source. Sleep set vote is 0.
4643 */
4644 clk_set_rate(&pnoc_keepalive_a_clk.c, 19200000);
4645 clk_prepare_enable(&pnoc_keepalive_a_clk.c);
4646
4647 clk_prepare_enable(&xo_a_clk_src.c);
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4648
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4649 if (!compat_bin && !compat_bin3 && !compat_bin5 && !compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4650 /* Configure Sleep and Wakeup cycles for GMEM clock */
4651 regval = readl_relaxed(GCC_REG_BASE(OXILI_GMEM_CBCR));
4652 regval ^= 0xFF0;
4653 regval |= CLKFLAG_WAKEUP_CYCLES << 8;
4654 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4655 writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));
4656 } else {
4657 /* Configure Sleep and Wakeup cycles for OXILI clock */
4658 regval = readl_relaxed(GCC_REG_BASE(OXILI_GFX3D_CBCR));
4659 regval &= ~0xF0;
4660 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4661 writel_relaxed(regval, GCC_REG_BASE(OXILI_GFX3D_CBCR));
4662 }
4663
4664 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
4665 if (ret)
4666 return ret;
4667
4668 msm_reset_controller_register(pdev, gcc_8952_resets,
4669 ARRAY_SIZE(gcc_8952_resets), virt_bases[GCC_BASE]);
4670
4671 dev_info(&pdev->dev, "Registered GCC clocks\n");
4672
4673 return 0;
4674}
4675
4676static const struct of_device_id msm_clock_gcc_match_table[] = {
4677 { .compatible = "qcom,gcc-8952" },
4678 { .compatible = "qcom,gcc-8937" },
4679 { .compatible = "qcom,gcc-8917" },
4680 { .compatible = "qcom,gcc-8940" },
4681 { .compatible = "qcom,gcc-8920" },
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4682 { .compatible = "qcom,gcc-sdm439" },
4683 { .compatible = "qcom,gcc-sdm429" },
Taniya Dasca059ac2019-01-18 14:45:24 +0530[diff] [blame]4684 { .compatible = "qcom,gcc-qm215" },
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4685 {}
4686};
4687
4688static struct platform_driver msm_clock_gcc_driver = {
4689 .probe = msm_gcc_probe,
4690 .driver = {
4691 .name = "qcom,gcc-8952",
4692 .of_match_table = msm_clock_gcc_match_table,
4693 .owner = THIS_MODULE,
4694 },
4695};
4696
4697static int msm_gcc_spm_probe(struct platform_device *pdev)
4698{
4699 struct resource *res = NULL;
4700 bool compat_bin = false;
4701
4702 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4703 "qcom,spm-8952");
4704
4705 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c0_base");
4706 if (!res) {
4707 dev_err(&pdev->dev, "SPM register base not defined for c0\n");
4708 return -ENOMEM;
4709 }
4710
4711 a53ss_c0_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4712 resource_size(res));
4713 if (!a53ss_c0_pll.spm_ctrl.spm_base) {
4714 dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");
4715 return -ENOMEM;
4716 }
4717
4718 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c1_base");
4719 if (!res) {
4720 dev_err(&pdev->dev, "SPM register base not defined for c1\n");
4721 return -ENOMEM;
4722 }
4723
4724 a53ss_c1_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4725 resource_size(res));
4726 if (!a53ss_c1_pll.spm_ctrl.spm_base) {
4727 dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");
4728 return -ENOMEM;
4729 }
4730
4731 if (compat_bin) {
4732 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4733 "spm_cci_base");
4734 if (!res) {
4735 dev_err(&pdev->dev, "SPM register base not defined for cci\n");
4736 return -ENOMEM;
4737 }
4738
4739 a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev,
4740 res->start, resource_size(res));
4741 if (!a53ss_cci_pll.spm_ctrl.spm_base) {
4742 dev_err(&pdev->dev, "Failed to ioremap cci spm registers\n");
4743 return -ENOMEM;
4744 }
4745 }
4746
4747 dev_info(&pdev->dev, "Registered GCC SPM clocks\n");
4748
4749 return 0;
4750}
4751
4752static const struct of_device_id msm_clock_spm_match_table[] = {
4753 { .compatible = "qcom,gcc-spm-8952" },
4754 { .compatible = "qcom,gcc-spm-8937" },
4755 {}
4756};
4757
4758static struct platform_driver msm_clock_spm_driver = {
4759 .probe = msm_gcc_spm_probe,
4760 .driver = {
4761 .name = "qcom,gcc-spm-8952",
4762 .of_match_table = msm_clock_spm_match_table,
4763 .owner = THIS_MODULE,
4764 },
4765};
4766
4767static int __init msm_gcc_init(void)
4768{
4769 int ret;
4770
4771 ret = platform_driver_register(&msm_clock_gcc_driver);
4772 if (!ret)
4773 ret = platform_driver_register(&msm_clock_spm_driver);
4774
4775 return ret;
4776}
4777
4778static struct clk_lookup msm_clocks_measure[] = {
4779 CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),
4780 CLK_LIST(apss_debug_pri_mux),
4781 CLK_LIST(apc0_m_clk),
4782 CLK_LIST(apc1_m_clk),
4783 CLK_LIST(cci_m_clk),
4784};
4785
4786static struct clk_lookup msm_clocks_measure_8937[] = {
4787 CLK_LOOKUP_OF("measure", gcc_debug_mux_8937, "debug"),
4788 CLK_LIST(apss_debug_pri_mux),
4789 CLK_LIST(apc0_m_clk),
4790 CLK_LIST(apc1_m_clk),
4791 CLK_LIST(cci_m_clk),
4792};
4793
4794static int msm_clock_debug_probe(struct platform_device *pdev)
4795{
4796 int ret;
4797 struct resource *res;
4798 bool compat_bin = false, compat_bin2 = false;
4799 bool compat_bin3 = false;
4800 bool compat_bin4 = false;
4801
4802 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4803 "qcom,cc-debug-8937");
4804
4805 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4806 "qcom,cc-debug-8917");
4807
4808 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4809 "qcom,cc-debug-8940");
4810
4811 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4812 "qcom,cc-debug-8920");
4813
4814 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "meas");
4815 if (!res) {
4816 dev_err(&pdev->dev, "GLB clock diag base not defined.\n");
4817 return -EINVAL;
4818 }
4819
4820 meas_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4821 if (!meas_base) {
4822 dev_err(&pdev->dev, "Unable to map GLB clock diag base.\n");
4823 return -ENOMEM;
4824 }
4825
4826 clk_ops_debug_mux = clk_ops_gen_mux;
4827 clk_ops_debug_mux.get_rate = measure_get_rate;
4828
4829 if (compat_bin2)
4830 gcc_debug_mux_8937.post_div = 0x3;
4831
4832 if (!compat_bin && !compat_bin2 && !compat_bin3 && !compat_bin4)
4833 ret = of_msm_clock_register(pdev->dev.of_node,
4834 msm_clocks_measure, ARRAY_SIZE(msm_clocks_measure));
4835 else
4836 ret = of_msm_clock_register(pdev->dev.of_node,
4837 msm_clocks_measure_8937,
4838 ARRAY_SIZE(msm_clocks_measure_8937));
4839 if (ret) {
4840 dev_err(&pdev->dev, "Failed to register debug Mux\n");
4841 return ret;
4842 }
4843
4844 dev_info(&pdev->dev, "Registered Debug Mux successfully\n");
4845 return ret;
4846}
4847
4848static const struct of_device_id msm_clock_debug_match_table[] = {
4849 { .compatible = "qcom,cc-debug-8952" },
4850 { .compatible = "qcom,cc-debug-8937" },
4851 { .compatible = "qcom,cc-debug-8917" },
4852 { .compatible = "qcom,cc-debug-8940" },
4853 { .compatible = "qcom,cc-debug-8920" },
4854 {}
4855};
4856
4857static struct platform_driver msm_clock_debug_driver = {
4858 .probe = msm_clock_debug_probe,
4859 .driver = {
4860 .name = "qcom,cc-debug-8952",
4861 .of_match_table = msm_clock_debug_match_table,
4862 .owner = THIS_MODULE,
4863 },
4864};
4865
4866static int __init msm_clock_debug_init(void)
4867{
4868 return platform_driver_register(&msm_clock_debug_driver);
4869}
4870
4871/* MDSS DSI_PHY_PLL */
4872static struct clk_lookup msm_clocks_gcc_mdss_common[] = {
4873 CLK_LIST(ext_pclk0_clk_src),
4874 CLK_LIST(ext_byte0_clk_src),
4875 CLK_LIST(byte0_clk_src),
4876 CLK_LIST(pclk0_clk_src),
4877 CLK_LIST(gcc_mdss_pclk0_clk),
4878 CLK_LIST(gcc_mdss_byte0_clk),
4879 CLK_LIST(mdss_mdp_vote_clk),
4880 CLK_LIST(mdss_rotator_vote_clk),
4881};
4882
4883static struct clk_lookup msm_clocks_gcc_mdss_8937[] = {
4884 CLK_LIST(ext_pclk1_clk_src),
4885 CLK_LIST(ext_byte1_clk_src),
4886 CLK_LIST(byte1_clk_src),
4887 CLK_LIST(pclk1_clk_src),
4888 CLK_LIST(gcc_mdss_pclk1_clk),
4889 CLK_LIST(gcc_mdss_byte1_clk),
4890};
4891
4892static int msm_gcc_mdss_probe(struct platform_device *pdev)
4893{
4894 int ret = 0;
4895 struct clk *curr_p;
4896 bool compat_bin = false;
4897
4898 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4899 "qcom,gcc-mdss-8937");
4900 if (!compat_bin)
4901 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4902 "qcom,gcc-mdss-8940");
4903
Padmanabhan Komanduru1853d7f2018-04-09 21:50:30 +0530[diff] [blame]4904 if (!compat_bin)
4905 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4906 "qcom,gcc-mdss-sdm439");
4907
4908 if (!compat_bin)
4909 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4910 "qcom,gcc-mdss-sdm429");
4911
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4912 curr_p = ext_pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4913 "pclk0_src");
4914 if (IS_ERR(curr_p)) {
4915 dev_err(&pdev->dev, "Failed to get pclk0 source.\n");
4916 return PTR_ERR(curr_p);
4917 }
4918
4919 curr_p = ext_byte0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4920 "byte0_src");
4921 if (IS_ERR(curr_p)) {
4922 dev_err(&pdev->dev, "Failed to get byte source.\n");
4923 ret = PTR_ERR(curr_p);
4924 goto byte0_fail;
4925 }
4926
4927 ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4928 ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4929
4930 if (compat_bin) {
4931 curr_p = ext_pclk1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4932 "pclk1_src");
4933 if (IS_ERR(curr_p)) {
4934 dev_err(&pdev->dev, "Failed to get pclk1 source.\n");
4935 ret = PTR_ERR(curr_p);
4936 goto fail;
4937 }
4938
4939 curr_p = ext_byte1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4940 "byte1_src");
4941 if (IS_ERR(curr_p)) {
4942 dev_err(&pdev->dev, "Failed to get byte1 source.\n");
4943 ret = PTR_ERR(curr_p);
4944 goto byte1_fail;
4945 }
4946
4947 ext_pclk1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4948 ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4949 }
4950
4951 ret = of_msm_clock_register(pdev->dev.of_node,
4952 msm_clocks_gcc_mdss_common,
4953 ARRAY_SIZE(msm_clocks_gcc_mdss_common));
4954 if (ret)
4955 goto fail;
4956
4957 if (compat_bin) {
4958 ret = of_msm_clock_register(pdev->dev.of_node,
4959 msm_clocks_gcc_mdss_8937,
4960 ARRAY_SIZE(msm_clocks_gcc_mdss_8937));
4961 if (ret)
4962 goto fail_8937;
4963 }
4964
4965 dev_info(&pdev->dev, "Registered GCC MDSS clocks.\n");
4966
4967 return ret;
4968fail_8937:
4969 devm_clk_put(&pdev->dev, ext_byte1_clk_src.c.parent);
4970byte1_fail:
4971 devm_clk_put(&pdev->dev, ext_pclk1_clk_src.c.parent);
4972fail:
4973 devm_clk_put(&pdev->dev, ext_byte0_clk_src.c.parent);
4974byte0_fail:
4975 devm_clk_put(&pdev->dev, ext_pclk0_clk_src.c.parent);
4976 return ret;
4977
4978}
4979
4980static const struct of_device_id msm_clock_mdss_match_table[] = {
4981 { .compatible = "qcom,gcc-mdss-8952" },
4982 { .compatible = "qcom,gcc-mdss-8937" },
4983 { .compatible = "qcom,gcc-mdss-8917" },
4984 { .compatible = "qcom,gcc-mdss-8940" },
4985 { .compatible = "qcom,gcc-mdss-8920" },
Padmanabhan Komanduru1853d7f2018-04-09 21:50:30 +0530[diff] [blame]4986 { .compatible = "qcom,gcc-mdss-sdm439" },
4987 { .compatible = "qcom,gcc-mdss-sdm429" },
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4988 {}
4989};
4990
4991static struct platform_driver msm_clock_gcc_mdss_driver = {
4992 .probe = msm_gcc_mdss_probe,
4993 .driver = {
4994 .name = "gcc-mdss-8952",
4995 .of_match_table = msm_clock_mdss_match_table,
4996 .owner = THIS_MODULE,
4997 },
4998};
4999
5000static int __init msm_gcc_mdss_init(void)
5001{
5002 return platform_driver_register(&msm_clock_gcc_mdss_driver);
5003}
5004arch_initcall(msm_gcc_init);
5005fs_initcall_sync(msm_gcc_mdss_init);
5006late_initcall(msm_clock_debug_init);