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Wu, Bryana5f6abd2007-05-06 14:50:34 -07001/*
Mike Frysinger26fdc1f2008-02-06 01:38:21 -08002 * Blackfin On-Chip SPI Driver
Wu, Bryana5f6abd2007-05-06 14:50:34 -07003 *
Mike Frysinger9c0a7882010-10-18 02:45:22 -04004 * Copyright 2004-2010 Analog Devices Inc.
Wu, Bryana5f6abd2007-05-06 14:50:34 -07005 *
Mike Frysinger26fdc1f2008-02-06 01:38:21 -08006 * Enter bugs at http://blackfin.uclinux.org/
Wu, Bryana5f6abd2007-05-06 14:50:34 -07007 *
Mike Frysinger26fdc1f2008-02-06 01:38:21 -08008 * Licensed under the GPL-2 or later.
Wu, Bryana5f6abd2007-05-06 14:50:34 -07009 */
10
11#include <linux/init.h>
12#include <linux/module.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080013#include <linux/delay.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070014#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080016#include <linux/io.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070017#include <linux/ioport.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080018#include <linux/irq.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070019#include <linux/errno.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/spi/spi.h>
24#include <linux/workqueue.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070025
Wu, Bryana5f6abd2007-05-06 14:50:34 -070026#include <asm/dma.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080027#include <asm/portmux.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070028#include <asm/bfin5xx_spi.h>
Vitja Makarov8cf58582009-04-06 19:00:31 -070029#include <asm/cacheflush.h>
30
Bryan Wua32c6912007-12-04 23:45:15 -080031#define DRV_NAME "bfin-spi"
32#define DRV_AUTHOR "Bryan Wu, Luke Yang"
Mike Frysinger138f97c2009-04-06 19:00:50 -070033#define DRV_DESC "Blackfin on-chip SPI Controller Driver"
Bryan Wua32c6912007-12-04 23:45:15 -080034#define DRV_VERSION "1.0"
35
36MODULE_AUTHOR(DRV_AUTHOR);
37MODULE_DESCRIPTION(DRV_DESC);
Wu, Bryana5f6abd2007-05-06 14:50:34 -070038MODULE_LICENSE("GPL");
39
Bryan Wubb90eb02007-12-04 23:45:18 -080040#define START_STATE ((void *)0)
41#define RUNNING_STATE ((void *)1)
42#define DONE_STATE ((void *)2)
43#define ERROR_STATE ((void *)-1)
Wu, Bryana5f6abd2007-05-06 14:50:34 -070044
Mike Frysinger9c0a7882010-10-18 02:45:22 -040045struct bfin_spi_master_data;
Mike Frysinger9c4542c2009-09-24 01:04:04 +000046
Mike Frysinger9c0a7882010-10-18 02:45:22 -040047struct bfin_spi_transfer_ops {
48 void (*write) (struct bfin_spi_master_data *);
49 void (*read) (struct bfin_spi_master_data *);
50 void (*duplex) (struct bfin_spi_master_data *);
Mike Frysinger9c4542c2009-09-24 01:04:04 +000051};
52
Mike Frysinger9c0a7882010-10-18 02:45:22 -040053struct bfin_spi_master_data {
Wu, Bryana5f6abd2007-05-06 14:50:34 -070054 /* Driver model hookup */
55 struct platform_device *pdev;
56
57 /* SPI framework hookup */
58 struct spi_master *master;
59
Bryan Wubb90eb02007-12-04 23:45:18 -080060 /* Regs base of SPI controller */
Mike Frysinger47885ce2011-06-17 04:16:56 -040061 struct bfin_spi_regs __iomem *regs;
Bryan Wubb90eb02007-12-04 23:45:18 -080062
Bryan Wu003d9222007-12-04 23:45:22 -080063 /* Pin request list */
64 u16 *pin_req;
65
Wu, Bryana5f6abd2007-05-06 14:50:34 -070066 /* BFIN hookup */
67 struct bfin5xx_spi_master *master_info;
68
69 /* Driver message queue */
70 struct workqueue_struct *workqueue;
71 struct work_struct pump_messages;
72 spinlock_t lock;
73 struct list_head queue;
74 int busy;
Mike Frysingerf4f50c32009-09-24 00:41:49 +000075 bool running;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070076
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers;
79
80 /* Current message transfer state info */
81 struct spi_message *cur_msg;
82 struct spi_transfer *cur_transfer;
Mike Frysinger9c0a7882010-10-18 02:45:22 -040083 struct bfin_spi_slave_data *cur_chip;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070084 size_t len_in_bytes;
85 size_t len;
86 void *tx;
87 void *tx_end;
88 void *rx;
89 void *rx_end;
Bryan Wubb90eb02007-12-04 23:45:18 -080090
91 /* DMA stuffs */
92 int dma_channel;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070093 int dma_mapped;
Bryan Wubb90eb02007-12-04 23:45:18 -080094 int dma_requested;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070095 dma_addr_t rx_dma;
96 dma_addr_t tx_dma;
Bryan Wubb90eb02007-12-04 23:45:18 -080097
Yi Lif6a6d962009-06-03 09:46:22 +000098 int irq_requested;
99 int spi_irq;
100
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700101 size_t rx_map_len;
102 size_t tx_map_len;
103 u8 n_bytes;
Barry Songb052fd02009-11-18 09:43:21 +0000104 u16 ctrl_reg;
105 u16 flag_reg;
106
Bryan Wufad91c82007-12-04 23:45:14 -0800107 int cs_change;
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400108 const struct bfin_spi_transfer_ops *ops;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700109};
110
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400111struct bfin_spi_slave_data {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700112 u16 ctl_reg;
113 u16 baud;
114 u16 flag;
115
116 u8 chip_select_num;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700117 u8 enable_dma;
Bryan Wu62310e52007-12-04 23:45:20 -0800118 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
Michael Hennerich42c78b22009-04-06 19:00:51 -0700119 u32 cs_gpio;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700120 u16 idle_tx_val;
Yi Lif6a6d962009-06-03 09:46:22 +0000121 u8 pio_interrupt; /* use spi data irq */
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400122 const struct bfin_spi_transfer_ops *ops;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700123};
124
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400125static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700126{
Mike Frysinger47885ce2011-06-17 04:16:56 -0400127 bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700128}
129
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400130static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700131{
Mike Frysinger47885ce2011-06-17 04:16:56 -0400132 bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700133}
134
135/* Caculate the SPI_BAUD register value based on input HZ */
136static u16 hz_to_spi_baud(u32 speed_hz)
137{
138 u_long sclk = get_sclk();
139 u16 spi_baud = (sclk / (2 * speed_hz));
140
141 if ((sclk % (2 * speed_hz)) > 0)
142 spi_baud++;
143
Michael Hennerich7513e002009-04-06 19:00:32 -0700144 if (spi_baud < MIN_SPI_BAUD_VAL)
145 spi_baud = MIN_SPI_BAUD_VAL;
146
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700147 return spi_baud;
148}
149
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400150static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700151{
152 unsigned long limit = loops_per_jiffy << 1;
153
154 /* wait for stop and clear stat */
Mike Frysinger47885ce2011-06-17 04:16:56 -0400155 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
Bryan Wud8c05002007-12-04 23:45:21 -0800156 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700157
Mike Frysinger47885ce2011-06-17 04:16:56 -0400158 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700159
160 return limit;
161}
162
Bryan Wufad91c82007-12-04 23:45:14 -0800163/* Chip select operation functions for cs_change flag */
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400164static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
Bryan Wufad91c82007-12-04 23:45:14 -0800165{
Mike Frysinger47885ce2011-06-17 04:16:56 -0400166 if (likely(chip->chip_select_num < MAX_CTRL_CS))
167 bfin_write_and(&drv_data->regs->flg, ~chip->flag);
168 else
Michael Hennerich42c78b22009-04-06 19:00:51 -0700169 gpio_set_value(chip->cs_gpio, 0);
Bryan Wufad91c82007-12-04 23:45:14 -0800170}
171
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400172static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
173 struct bfin_spi_slave_data *chip)
Bryan Wufad91c82007-12-04 23:45:14 -0800174{
Mike Frysinger47885ce2011-06-17 04:16:56 -0400175 if (likely(chip->chip_select_num < MAX_CTRL_CS))
176 bfin_write_or(&drv_data->regs->flg, chip->flag);
177 else
Michael Hennerich42c78b22009-04-06 19:00:51 -0700178 gpio_set_value(chip->cs_gpio, 1);
Bryan Wu62310e52007-12-04 23:45:20 -0800179
180 /* Move delay here for consistency */
181 if (chip->cs_chg_udelay)
182 udelay(chip->cs_chg_udelay);
Bryan Wufad91c82007-12-04 23:45:14 -0800183}
184
Barry Song82216102009-06-17 10:10:53 +0000185/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400186static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
187 struct bfin_spi_slave_data *chip)
Barry Song82216102009-06-17 10:10:53 +0000188{
Mike Frysinger47885ce2011-06-17 04:16:56 -0400189 if (chip->chip_select_num < MAX_CTRL_CS)
190 bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
Barry Song82216102009-06-17 10:10:53 +0000191}
192
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400193static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
194 struct bfin_spi_slave_data *chip)
Barry Song82216102009-06-17 10:10:53 +0000195{
Mike Frysinger47885ce2011-06-17 04:16:56 -0400196 if (chip->chip_select_num < MAX_CTRL_CS)
197 bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
Barry Song82216102009-06-17 10:10:53 +0000198}
199
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700200/* stop controller and re-config current chip*/
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400201static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700202{
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400203 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700204
205 /* Clear status and disable clock */
Mike Frysinger47885ce2011-06-17 04:16:56 -0400206 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700207 bfin_spi_disable(drv_data);
Bryan Wu88b40362007-05-21 18:32:16 +0800208 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700209
Barry Song9677b0de2009-11-30 03:49:41 +0000210 SSYNC();
211
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700212 /* Load the registers */
Mike Frysinger47885ce2011-06-17 04:16:56 -0400213 bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
214 bfin_write(&drv_data->regs->baud, chip->baud);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800215
216 bfin_spi_enable(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700217 bfin_spi_cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700218}
219
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700220/* used to kick off transfer in rx mode and read unwanted RX data */
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400221static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700222{
Mike Frysinger47885ce2011-06-17 04:16:56 -0400223 (void) bfin_read(&drv_data->regs->rdbr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700224}
225
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400226static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700227{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700228 /* clear RXS (we check for RXS inside the loop) */
229 bfin_spi_dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800230
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700231 while (drv_data->tx < drv_data->tx_end) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400232 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700233 /* wait until transfer finished.
234 checking SPIF or TXS may not guarantee transfer completion */
Mike Frysinger47885ce2011-06-17 04:16:56 -0400235 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800236 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700237 /* discard RX data and clear RXS */
238 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700239 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700240}
241
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400242static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700243{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700244 u16 tx_val = drv_data->cur_chip->idle_tx_val;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700245
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700246 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700247 bfin_spi_dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800248
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700249 while (drv_data->rx < drv_data->rx_end) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400250 bfin_write(&drv_data->regs->tdbr, tx_val);
251 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800252 cpu_relax();
Mike Frysinger47885ce2011-06-17 04:16:56 -0400253 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700254 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700255}
256
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400257static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700258{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700259 /* discard old RX data and clear RXS */
260 bfin_spi_dummy_read(drv_data);
261
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700262 while (drv_data->rx < drv_data->rx_end) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400263 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
264 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800265 cpu_relax();
Mike Frysinger47885ce2011-06-17 04:16:56 -0400266 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700267 }
268}
269
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400270static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
Mike Frysinger9c4542c2009-09-24 01:04:04 +0000271 .write = bfin_spi_u8_writer,
272 .read = bfin_spi_u8_reader,
273 .duplex = bfin_spi_u8_duplex,
274};
275
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400276static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700277{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700278 /* clear RXS (we check for RXS inside the loop) */
279 bfin_spi_dummy_read(drv_data);
Bryan Wu88b40362007-05-21 18:32:16 +0800280
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700281 while (drv_data->tx < drv_data->tx_end) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400282 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700283 drv_data->tx += 2;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700284 /* wait until transfer finished.
285 checking SPIF or TXS may not guarantee transfer completion */
Mike Frysinger47885ce2011-06-17 04:16:56 -0400286 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700287 cpu_relax();
288 /* discard RX data and clear RXS */
289 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700290 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700291}
292
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400293static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700294{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700295 u16 tx_val = drv_data->cur_chip->idle_tx_val;
Sonic Zhangcc487e72007-12-04 23:45:17 -0800296
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700297 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700298 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700299
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700300 while (drv_data->rx < drv_data->rx_end) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400301 bfin_write(&drv_data->regs->tdbr, tx_val);
302 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800303 cpu_relax();
Mike Frysinger47885ce2011-06-17 04:16:56 -0400304 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700305 drv_data->rx += 2;
306 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700307}
308
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400309static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700310{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700311 /* discard old RX data and clear RXS */
312 bfin_spi_dummy_read(drv_data);
313
314 while (drv_data->rx < drv_data->rx_end) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400315 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700316 drv_data->tx += 2;
Mike Frysinger47885ce2011-06-17 04:16:56 -0400317 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800318 cpu_relax();
Mike Frysinger47885ce2011-06-17 04:16:56 -0400319 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700320 drv_data->rx += 2;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700321 }
322}
323
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400324static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
Mike Frysinger9c4542c2009-09-24 01:04:04 +0000325 .write = bfin_spi_u16_writer,
326 .read = bfin_spi_u16_reader,
327 .duplex = bfin_spi_u16_duplex,
328};
329
Rob Marise3595402010-04-06 04:12:00 +0000330/* test if there is more transfer to be done */
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400331static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700332{
333 struct spi_message *msg = drv_data->cur_msg;
334 struct spi_transfer *trans = drv_data->cur_transfer;
335
336 /* Move to next transfer */
337 if (trans->transfer_list.next != &msg->transfers) {
338 drv_data->cur_transfer =
339 list_entry(trans->transfer_list.next,
340 struct spi_transfer, transfer_list);
341 return RUNNING_STATE;
342 } else
343 return DONE_STATE;
344}
345
346/*
347 * caller already set message->status;
348 * dma and pio irqs are blocked give finished message back
349 */
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400350static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700351{
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400352 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700353 struct spi_transfer *last_transfer;
354 unsigned long flags;
355 struct spi_message *msg;
356
357 spin_lock_irqsave(&drv_data->lock, flags);
358 msg = drv_data->cur_msg;
359 drv_data->cur_msg = NULL;
360 drv_data->cur_transfer = NULL;
361 drv_data->cur_chip = NULL;
362 queue_work(drv_data->workqueue, &drv_data->pump_messages);
363 spin_unlock_irqrestore(&drv_data->lock, flags);
364
365 last_transfer = list_entry(msg->transfers.prev,
366 struct spi_transfer, transfer_list);
367
368 msg->state = NULL;
369
Bryan Wufad91c82007-12-04 23:45:14 -0800370 if (!drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700371 bfin_spi_cs_deactive(drv_data, chip);
Bryan Wufad91c82007-12-04 23:45:14 -0800372
Yi Lib9b2a762009-04-06 19:00:49 -0700373 /* Not stop spi in autobuffer mode */
374 if (drv_data->tx_dma != 0xFFFF)
375 bfin_spi_disable(drv_data);
376
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700377 if (msg->complete)
378 msg->complete(msg->context);
379}
380
Yi Lif6a6d962009-06-03 09:46:22 +0000381/* spi data irq handler */
382static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
383{
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400384 struct bfin_spi_master_data *drv_data = dev_id;
385 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
Yi Lif6a6d962009-06-03 09:46:22 +0000386 struct spi_message *msg = drv_data->cur_msg;
387 int n_bytes = drv_data->n_bytes;
Bob Liu4d676fc2011-01-11 11:19:07 -0500388 int loop = 0;
Yi Lif6a6d962009-06-03 09:46:22 +0000389
390 /* wait until transfer finished. */
Mike Frysinger47885ce2011-06-17 04:16:56 -0400391 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
Yi Lif6a6d962009-06-03 09:46:22 +0000392 cpu_relax();
393
394 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
395 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
396 /* last read */
397 if (drv_data->rx) {
398 dev_dbg(&drv_data->pdev->dev, "last read\n");
Scott Jiang128465c2012-04-23 18:18:12 -0400399 if (!(n_bytes % 2)) {
Bob Liu4d676fc2011-01-11 11:19:07 -0500400 u16 *buf = (u16 *)drv_data->rx;
401 for (loop = 0; loop < n_bytes / 2; loop++)
Mike Frysinger47885ce2011-06-17 04:16:56 -0400402 *buf++ = bfin_read(&drv_data->regs->rdbr);
Bob Liu4d676fc2011-01-11 11:19:07 -0500403 } else {
404 u8 *buf = (u8 *)drv_data->rx;
405 for (loop = 0; loop < n_bytes; loop++)
Mike Frysinger47885ce2011-06-17 04:16:56 -0400406 *buf++ = bfin_read(&drv_data->regs->rdbr);
Bob Liu4d676fc2011-01-11 11:19:07 -0500407 }
Yi Lif6a6d962009-06-03 09:46:22 +0000408 drv_data->rx += n_bytes;
409 }
410
411 msg->actual_length += drv_data->len_in_bytes;
412 if (drv_data->cs_change)
413 bfin_spi_cs_deactive(drv_data, chip);
414 /* Move to next transfer */
415 msg->state = bfin_spi_next_transfer(drv_data);
416
Yi Li7370ed62009-12-07 08:07:01 +0000417 disable_irq_nosync(drv_data->spi_irq);
Yi Lif6a6d962009-06-03 09:46:22 +0000418
419 /* Schedule transfer tasklet */
420 tasklet_schedule(&drv_data->pump_transfers);
421 return IRQ_HANDLED;
422 }
423
424 if (drv_data->rx && drv_data->tx) {
425 /* duplex */
426 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
Scott Jiang128465c2012-04-23 18:18:12 -0400427 if (!(n_bytes % 2)) {
Bob Liu4d676fc2011-01-11 11:19:07 -0500428 u16 *buf = (u16 *)drv_data->rx;
429 u16 *buf2 = (u16 *)drv_data->tx;
430 for (loop = 0; loop < n_bytes / 2; loop++) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400431 *buf++ = bfin_read(&drv_data->regs->rdbr);
432 bfin_write(&drv_data->regs->tdbr, *buf2++);
Bob Liu4d676fc2011-01-11 11:19:07 -0500433 }
434 } else {
435 u8 *buf = (u8 *)drv_data->rx;
436 u8 *buf2 = (u8 *)drv_data->tx;
437 for (loop = 0; loop < n_bytes; loop++) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400438 *buf++ = bfin_read(&drv_data->regs->rdbr);
439 bfin_write(&drv_data->regs->tdbr, *buf2++);
Bob Liu4d676fc2011-01-11 11:19:07 -0500440 }
Yi Lif6a6d962009-06-03 09:46:22 +0000441 }
442 } else if (drv_data->rx) {
443 /* read */
444 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
Scott Jiang128465c2012-04-23 18:18:12 -0400445 if (!(n_bytes % 2)) {
Bob Liu4d676fc2011-01-11 11:19:07 -0500446 u16 *buf = (u16 *)drv_data->rx;
447 for (loop = 0; loop < n_bytes / 2; loop++) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400448 *buf++ = bfin_read(&drv_data->regs->rdbr);
449 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
Bob Liu4d676fc2011-01-11 11:19:07 -0500450 }
451 } else {
452 u8 *buf = (u8 *)drv_data->rx;
453 for (loop = 0; loop < n_bytes; loop++) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400454 *buf++ = bfin_read(&drv_data->regs->rdbr);
455 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
Bob Liu4d676fc2011-01-11 11:19:07 -0500456 }
457 }
Yi Lif6a6d962009-06-03 09:46:22 +0000458 } else if (drv_data->tx) {
459 /* write */
460 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
Scott Jiang128465c2012-04-23 18:18:12 -0400461 if (!(n_bytes % 2)) {
Bob Liu4d676fc2011-01-11 11:19:07 -0500462 u16 *buf = (u16 *)drv_data->tx;
463 for (loop = 0; loop < n_bytes / 2; loop++) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400464 bfin_read(&drv_data->regs->rdbr);
465 bfin_write(&drv_data->regs->tdbr, *buf++);
Bob Liu4d676fc2011-01-11 11:19:07 -0500466 }
467 } else {
468 u8 *buf = (u8 *)drv_data->tx;
469 for (loop = 0; loop < n_bytes; loop++) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400470 bfin_read(&drv_data->regs->rdbr);
471 bfin_write(&drv_data->regs->tdbr, *buf++);
Bob Liu4d676fc2011-01-11 11:19:07 -0500472 }
473 }
Yi Lif6a6d962009-06-03 09:46:22 +0000474 }
475
476 if (drv_data->tx)
477 drv_data->tx += n_bytes;
478 if (drv_data->rx)
479 drv_data->rx += n_bytes;
480
481 return IRQ_HANDLED;
482}
483
Mike Frysinger138f97c2009-04-06 19:00:50 -0700484static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700485{
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400486 struct bfin_spi_master_data *drv_data = dev_id;
487 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
Bryan Wubb90eb02007-12-04 23:45:18 -0800488 struct spi_message *msg = drv_data->cur_msg;
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700489 unsigned long timeout;
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700490 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
Mike Frysinger47885ce2011-06-17 04:16:56 -0400491 u16 spistat = bfin_read(&drv_data->regs->stat);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700492
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700493 dev_dbg(&drv_data->pdev->dev,
494 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
495 dmastat, spistat);
496
Michael Hennerich782a8952010-10-22 02:01:48 -0400497 if (drv_data->rx != NULL) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400498 u16 cr = bfin_read(&drv_data->regs->ctl);
Michael Hennerich782a8952010-10-22 02:01:48 -0400499 /* discard old RX data and clear RXS */
500 bfin_spi_dummy_read(drv_data);
Mike Frysinger47885ce2011-06-17 04:16:56 -0400501 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
502 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */
503 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */
Michael Hennerich782a8952010-10-22 02:01:48 -0400504 }
505
Bryan Wubb90eb02007-12-04 23:45:18 -0800506 clear_dma_irqstat(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700507
508 /*
Bryan Wud6fe89b2007-06-11 17:34:17 +0800509 * wait for the last transaction shifted out. HRM states:
510 * at this point there may still be data in the SPI DMA FIFO waiting
511 * to be transmitted ... software needs to poll TXS in the SPI_STAT
512 * register until it goes low for 2 successive reads
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700513 */
514 if (drv_data->tx != NULL) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400515 while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
516 (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800517 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700518 }
519
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700520 dev_dbg(&drv_data->pdev->dev,
521 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
Mike Frysinger47885ce2011-06-17 04:16:56 -0400522 dmastat, bfin_read(&drv_data->regs->stat));
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700523
524 timeout = jiffies + HZ;
Mike Frysinger47885ce2011-06-17 04:16:56 -0400525 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700526 if (!time_before(jiffies, timeout)) {
527 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
528 break;
529 } else
530 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700531
Mike Frysinger90008a62009-10-15 04:13:29 +0000532 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
Mike Frysinger04b95d22009-04-06 19:00:35 -0700533 msg->state = ERROR_STATE;
534 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
535 } else {
536 msg->actual_length += drv_data->len_in_bytes;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700537
Mike Frysinger04b95d22009-04-06 19:00:35 -0700538 if (drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700539 bfin_spi_cs_deactive(drv_data, chip);
Bryan Wufad91c82007-12-04 23:45:14 -0800540
Mike Frysinger04b95d22009-04-06 19:00:35 -0700541 /* Move to next transfer */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700542 msg->state = bfin_spi_next_transfer(drv_data);
Mike Frysinger04b95d22009-04-06 19:00:35 -0700543 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700544
545 /* Schedule transfer tasklet */
546 tasklet_schedule(&drv_data->pump_transfers);
547
548 /* free the irq handler before next transfer */
Bryan Wu88b40362007-05-21 18:32:16 +0800549 dev_dbg(&drv_data->pdev->dev,
550 "disable dma channel irq%d\n",
Bryan Wubb90eb02007-12-04 23:45:18 -0800551 drv_data->dma_channel);
Barry Songa75bd65b2010-01-22 10:07:30 +0000552 dma_disable_irq_nosync(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700553
554 return IRQ_HANDLED;
555}
556
Mike Frysinger138f97c2009-04-06 19:00:50 -0700557static void bfin_spi_pump_transfers(unsigned long data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700558{
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400559 struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700560 struct spi_message *message = NULL;
561 struct spi_transfer *transfer = NULL;
562 struct spi_transfer *previous = NULL;
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400563 struct bfin_spi_slave_data *chip = NULL;
Mike Frysinger033f44b2009-12-18 17:38:04 +0000564 unsigned int bits_per_word;
Mike Frysinger5e8592d2009-12-18 18:00:10 +0000565 u16 cr, cr_width, dma_width, dma_config;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700566 u32 tranf_success = 1;
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700567 u8 full_duplex = 0;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700568
569 /* Get current state information */
570 message = drv_data->cur_msg;
571 transfer = drv_data->cur_transfer;
572 chip = drv_data->cur_chip;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800573
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700574 /*
575 * if msg is error or done, report it back using complete() callback
576 */
577
578 /* Handle for abort */
579 if (message->state == ERROR_STATE) {
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700580 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700581 message->status = -EIO;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700582 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700583 return;
584 }
585
586 /* Handle end of message */
587 if (message->state == DONE_STATE) {
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700588 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700589 message->status = 0;
Scott Jiang2431a812012-04-23 18:18:13 -0400590 bfin_spi_flush(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700591 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700592 return;
593 }
594
595 /* Delay if requested at end of transfer */
596 if (message->state == RUNNING_STATE) {
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700597 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700598 previous = list_entry(transfer->transfer_list.prev,
599 struct spi_transfer, transfer_list);
600 if (previous->delay_usecs)
601 udelay(previous->delay_usecs);
602 }
603
Mike Frysingerab09e042009-09-23 23:32:34 +0000604 /* Flush any existing transfers that may be sitting in the hardware */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700605 if (bfin_spi_flush(drv_data) == 0) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700606 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
607 message->status = -EIO;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700608 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700609 return;
610 }
611
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700612 if (transfer->len == 0) {
613 /* Move to next transfer of this msg */
614 message->state = bfin_spi_next_transfer(drv_data);
615 /* Schedule next transfer tasklet */
616 tasklet_schedule(&drv_data->pump_transfers);
Sonic Zhang1974eba2011-01-11 11:19:08 -0500617 return;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700618 }
619
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700620 if (transfer->tx_buf != NULL) {
621 drv_data->tx = (void *)transfer->tx_buf;
622 drv_data->tx_end = drv_data->tx + transfer->len;
Bryan Wu88b40362007-05-21 18:32:16 +0800623 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
624 transfer->tx_buf, drv_data->tx_end);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700625 } else {
626 drv_data->tx = NULL;
627 }
628
629 if (transfer->rx_buf != NULL) {
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700630 full_duplex = transfer->tx_buf != NULL;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700631 drv_data->rx = transfer->rx_buf;
632 drv_data->rx_end = drv_data->rx + transfer->len;
Bryan Wu88b40362007-05-21 18:32:16 +0800633 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
634 transfer->rx_buf, drv_data->rx_end);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700635 } else {
636 drv_data->rx = NULL;
637 }
638
639 drv_data->rx_dma = transfer->rx_dma;
640 drv_data->tx_dma = transfer->tx_dma;
641 drv_data->len_in_bytes = transfer->len;
Bryan Wufad91c82007-12-04 23:45:14 -0800642 drv_data->cs_change = transfer->cs_change;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700643
Bryan Wu092e1fd2007-12-04 23:45:23 -0800644 /* Bits per word setup */
Laxman Dewangan766ed702012-12-18 14:25:43 +0530645 bits_per_word = transfer->bits_per_word;
Stephen Warren24778be2013-05-21 20:36:35 -0600646 if (bits_per_word == 16) {
Bob Liu4d676fc2011-01-11 11:19:07 -0500647 drv_data->n_bytes = bits_per_word/8;
Mike Frysinger5e8592d2009-12-18 18:00:10 +0000648 drv_data->len = (transfer->len) >> 1;
649 cr_width = BIT_CTL_WORDSIZE;
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400650 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
Stephen Warren24778be2013-05-21 20:36:35 -0600651 } else if (bits_per_word == 8) {
Bob Liu4d676fc2011-01-11 11:19:07 -0500652 drv_data->n_bytes = bits_per_word/8;
653 drv_data->len = transfer->len;
654 cr_width = 0;
655 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800656 }
Mike Frysinger47885ce2011-06-17 04:16:56 -0400657 cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
Mike Frysinger5e8592d2009-12-18 18:00:10 +0000658 cr |= cr_width;
Mike Frysinger47885ce2011-06-17 04:16:56 -0400659 bfin_write(&drv_data->regs->ctl, cr);
Bryan Wu092e1fd2007-12-04 23:45:23 -0800660
Mike Frysinger4fb98ef2008-04-08 17:41:57 -0700661 dev_dbg(&drv_data->pdev->dev,
Mike Frysinger9c4542c2009-09-24 01:04:04 +0000662 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400663 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700664
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700665 message->state = RUNNING_STATE;
666 dma_config = 0;
667
Bryan Wu092e1fd2007-12-04 23:45:23 -0800668 /* Speed setup (surely valid because already checked) */
669 if (transfer->speed_hz)
Mike Frysinger47885ce2011-06-17 04:16:56 -0400670 bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
Bryan Wu092e1fd2007-12-04 23:45:23 -0800671 else
Mike Frysinger47885ce2011-06-17 04:16:56 -0400672 bfin_write(&drv_data->regs->baud, chip->baud);
Bryan Wu092e1fd2007-12-04 23:45:23 -0800673
Mike Frysinger47885ce2011-06-17 04:16:56 -0400674 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
Rob Marise72dcde2010-04-06 04:17:08 +0000675 bfin_spi_cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700676
Bryan Wu88b40362007-05-21 18:32:16 +0800677 dev_dbg(&drv_data->pdev->dev,
678 "now pumping a transfer: width is %d, len is %d\n",
Mike Frysinger5e8592d2009-12-18 18:00:10 +0000679 cr_width, transfer->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700680
681 /*
Vitja Makarov8cf58582009-04-06 19:00:31 -0700682 * Try to map dma buffer and do a dma transfer. If successful use,
683 * different way to r/w according to the enable_dma settings and if
684 * we are not doing a full duplex transfer (since the hardware does
685 * not support full duplex DMA transfers).
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700686 */
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700687 if (!full_duplex && drv_data->cur_chip->enable_dma
688 && drv_data->len > 6) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700689
Mike Frysinger11d6f592009-04-06 19:00:41 -0700690 unsigned long dma_start_addr, flags;
Mike Frysinger7aec3562009-04-06 19:00:36 -0700691
Bryan Wubb90eb02007-12-04 23:45:18 -0800692 disable_dma(drv_data->dma_channel);
693 clear_dma_irqstat(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700694
695 /* config dma channel */
Bryan Wu88b40362007-05-21 18:32:16 +0800696 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
Mike Frysinger7aec3562009-04-06 19:00:36 -0700697 set_dma_x_count(drv_data->dma_channel, drv_data->len);
Mike Frysinger5e8592d2009-12-18 18:00:10 +0000698 if (cr_width == BIT_CTL_WORDSIZE) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800699 set_dma_x_modify(drv_data->dma_channel, 2);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700700 dma_width = WDSIZE_16;
701 } else {
Bryan Wubb90eb02007-12-04 23:45:18 -0800702 set_dma_x_modify(drv_data->dma_channel, 1);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700703 dma_width = WDSIZE_8;
704 }
705
Sonic Zhang3f479a62007-12-04 23:45:18 -0800706 /* poll for SPI completion before start */
Mike Frysinger47885ce2011-06-17 04:16:56 -0400707 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800708 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800709
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700710 /* dirty hack for autobuffer DMA mode */
711 if (drv_data->tx_dma == 0xFFFF) {
Bryan Wu88b40362007-05-21 18:32:16 +0800712 dev_dbg(&drv_data->pdev->dev,
713 "doing autobuffer DMA out.\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700714
715 /* no irq in autobuffer mode */
716 dma_config =
717 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
Bryan Wubb90eb02007-12-04 23:45:18 -0800718 set_dma_config(drv_data->dma_channel, dma_config);
719 set_dma_start_addr(drv_data->dma_channel,
Bryan Wua32c6912007-12-04 23:45:15 -0800720 (unsigned long)drv_data->tx);
Bryan Wubb90eb02007-12-04 23:45:18 -0800721 enable_dma(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700722
Sonic Zhang07612e52007-12-04 23:45:21 -0800723 /* start SPI transfer */
Mike Frysinger47885ce2011-06-17 04:16:56 -0400724 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
Sonic Zhang07612e52007-12-04 23:45:21 -0800725
726 /* just return here, there can only be one transfer
727 * in this mode
728 */
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700729 message->status = 0;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700730 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700731 return;
732 }
733
734 /* In dma mode, rx or tx must be NULL in one transfer */
Mike Frysinger7aec3562009-04-06 19:00:36 -0700735 dma_config = (RESTART | dma_width | DI_EN);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700736 if (drv_data->rx != NULL) {
737 /* set transfer mode, and enable SPI */
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700738 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
739 drv_data->rx, drv_data->len_in_bytes);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700740
Vitja Makarov8cf58582009-04-06 19:00:31 -0700741 /* invalidate caches, if needed */
Jie Zhang67834fa2009-06-10 06:26:26 +0000742 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
Vitja Makarov8cf58582009-04-06 19:00:31 -0700743 invalidate_dcache_range((unsigned long) drv_data->rx,
744 (unsigned long) (drv_data->rx +
Mike Frysingerace32862009-04-06 19:00:34 -0700745 drv_data->len_in_bytes));
Vitja Makarov8cf58582009-04-06 19:00:31 -0700746
Mike Frysinger7aec3562009-04-06 19:00:36 -0700747 dma_config |= WNR;
748 dma_start_addr = (unsigned long)drv_data->rx;
Mike Frysingerb31e27a2009-04-06 19:00:39 -0700749 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
Sonic Zhang07612e52007-12-04 23:45:21 -0800750
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700751 } else if (drv_data->tx != NULL) {
Bryan Wu88b40362007-05-21 18:32:16 +0800752 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700753
Vitja Makarov8cf58582009-04-06 19:00:31 -0700754 /* flush caches, if needed */
Jie Zhang67834fa2009-06-10 06:26:26 +0000755 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
Vitja Makarov8cf58582009-04-06 19:00:31 -0700756 flush_dcache_range((unsigned long) drv_data->tx,
757 (unsigned long) (drv_data->tx +
Mike Frysingerace32862009-04-06 19:00:34 -0700758 drv_data->len_in_bytes));
Vitja Makarov8cf58582009-04-06 19:00:31 -0700759
Mike Frysinger7aec3562009-04-06 19:00:36 -0700760 dma_start_addr = (unsigned long)drv_data->tx;
Mike Frysingerb31e27a2009-04-06 19:00:39 -0700761 cr |= BIT_CTL_TIMOD_DMA_TX;
Sonic Zhang07612e52007-12-04 23:45:21 -0800762
Mike Frysinger7aec3562009-04-06 19:00:36 -0700763 } else
764 BUG();
765
Mike Frysinger11d6f592009-04-06 19:00:41 -0700766 /* oh man, here there be monsters ... and i dont mean the
767 * fluffy cute ones from pixar, i mean the kind that'll eat
768 * your data, kick your dog, and love it all. do *not* try
769 * and change these lines unless you (1) heavily test DMA
770 * with SPI flashes on a loaded system (e.g. ping floods),
771 * (2) know just how broken the DMA engine interaction with
772 * the SPI peripheral is, and (3) have someone else to blame
773 * when you screw it all up anyways.
774 */
Mike Frysinger7aec3562009-04-06 19:00:36 -0700775 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
Mike Frysinger11d6f592009-04-06 19:00:41 -0700776 set_dma_config(drv_data->dma_channel, dma_config);
777 local_irq_save(flags);
Mike Frysingera963ea82009-04-06 19:00:43 -0700778 SSYNC();
Mike Frysinger47885ce2011-06-17 04:16:56 -0400779 bfin_write(&drv_data->regs->ctl, cr);
Mike Frysingera963ea82009-04-06 19:00:43 -0700780 enable_dma(drv_data->dma_channel);
Mike Frysinger11d6f592009-04-06 19:00:41 -0700781 dma_enable_irq(drv_data->dma_channel);
782 local_irq_restore(flags);
Mike Frysinger7aec3562009-04-06 19:00:36 -0700783
Yi Lif6a6d962009-06-03 09:46:22 +0000784 return;
785 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700786
Mike Frysinger5e8592d2009-12-18 18:00:10 +0000787 /*
788 * We always use SPI_WRITE mode (transfer starts with TDBR write).
789 * SPI_READ mode (transfer starts with RDBR read) seems to have
790 * problems with setting up the output value in TDBR prior to the
791 * start of the transfer.
792 */
Mike Frysinger47885ce2011-06-17 04:16:56 -0400793 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
Mike Frysinger5e8592d2009-12-18 18:00:10 +0000794
Yi Lif6a6d962009-06-03 09:46:22 +0000795 if (chip->pio_interrupt) {
Mike Frysinger5e8592d2009-12-18 18:00:10 +0000796 /* SPI irq should have been disabled by now */
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700797
Yi Lif6a6d962009-06-03 09:46:22 +0000798 /* discard old RX data and clear RXS */
799 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700800
Yi Lif6a6d962009-06-03 09:46:22 +0000801 /* start transfer */
802 if (drv_data->tx == NULL)
Mike Frysinger47885ce2011-06-17 04:16:56 -0400803 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
Yi Lif6a6d962009-06-03 09:46:22 +0000804 else {
Bob Liu4d676fc2011-01-11 11:19:07 -0500805 int loop;
Stephen Warren24778be2013-05-21 20:36:35 -0600806 if (bits_per_word == 16) {
Bob Liu4d676fc2011-01-11 11:19:07 -0500807 u16 *buf = (u16 *)drv_data->tx;
808 for (loop = 0; loop < bits_per_word / 16;
809 loop++) {
Mike Frysinger47885ce2011-06-17 04:16:56 -0400810 bfin_write(&drv_data->regs->tdbr, *buf++);
Bob Liu4d676fc2011-01-11 11:19:07 -0500811 }
Stephen Warren24778be2013-05-21 20:36:35 -0600812 } else if (bits_per_word == 8) {
Bob Liu4d676fc2011-01-11 11:19:07 -0500813 u8 *buf = (u8 *)drv_data->tx;
814 for (loop = 0; loop < bits_per_word / 8; loop++)
Mike Frysinger47885ce2011-06-17 04:16:56 -0400815 bfin_write(&drv_data->regs->tdbr, *buf++);
Bob Liu4d676fc2011-01-11 11:19:07 -0500816 }
817
Yi Lif6a6d962009-06-03 09:46:22 +0000818 drv_data->tx += drv_data->n_bytes;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700819 }
820
Yi Lif6a6d962009-06-03 09:46:22 +0000821 /* once TDBR is empty, interrupt is triggered */
822 enable_irq(drv_data->spi_irq);
823 return;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700824 }
Yi Lif6a6d962009-06-03 09:46:22 +0000825
826 /* IO mode */
827 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
828
Yi Lif6a6d962009-06-03 09:46:22 +0000829 if (full_duplex) {
830 /* full duplex mode */
831 BUG_ON((drv_data->tx_end - drv_data->tx) !=
832 (drv_data->rx_end - drv_data->rx));
833 dev_dbg(&drv_data->pdev->dev,
834 "IO duplex: cr is 0x%x\n", cr);
835
Mike Frysinger9c4542c2009-09-24 01:04:04 +0000836 drv_data->ops->duplex(drv_data);
Yi Lif6a6d962009-06-03 09:46:22 +0000837
838 if (drv_data->tx != drv_data->tx_end)
839 tranf_success = 0;
840 } else if (drv_data->tx != NULL) {
841 /* write only half duplex */
842 dev_dbg(&drv_data->pdev->dev,
843 "IO write: cr is 0x%x\n", cr);
844
Mike Frysinger9c4542c2009-09-24 01:04:04 +0000845 drv_data->ops->write(drv_data);
Yi Lif6a6d962009-06-03 09:46:22 +0000846
847 if (drv_data->tx != drv_data->tx_end)
848 tranf_success = 0;
849 } else if (drv_data->rx != NULL) {
850 /* read only half duplex */
851 dev_dbg(&drv_data->pdev->dev,
852 "IO read: cr is 0x%x\n", cr);
853
Mike Frysinger9c4542c2009-09-24 01:04:04 +0000854 drv_data->ops->read(drv_data);
Yi Lif6a6d962009-06-03 09:46:22 +0000855 if (drv_data->rx != drv_data->rx_end)
856 tranf_success = 0;
857 }
858
859 if (!tranf_success) {
860 dev_dbg(&drv_data->pdev->dev,
861 "IO write error!\n");
862 message->state = ERROR_STATE;
863 } else {
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300864 /* Update total byte transferred */
Yi Lif6a6d962009-06-03 09:46:22 +0000865 message->actual_length += drv_data->len_in_bytes;
866 /* Move to next transfer of this msg */
867 message->state = bfin_spi_next_transfer(drv_data);
Scott Jiang2431a812012-04-23 18:18:13 -0400868 if (drv_data->cs_change && message->state != DONE_STATE) {
869 bfin_spi_flush(drv_data);
Yi Lif6a6d962009-06-03 09:46:22 +0000870 bfin_spi_cs_deactive(drv_data, chip);
Scott Jiang2431a812012-04-23 18:18:13 -0400871 }
Yi Lif6a6d962009-06-03 09:46:22 +0000872 }
873
874 /* Schedule next transfer tasklet */
875 tasklet_schedule(&drv_data->pump_transfers);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700876}
877
878/* pop a msg from queue and kick off real transfer */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700879static void bfin_spi_pump_messages(struct work_struct *work)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700880{
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400881 struct bfin_spi_master_data *drv_data;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700882 unsigned long flags;
883
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400884 drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
Bryan Wu131b17d2007-12-04 23:45:12 -0800885
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700886 /* Lock queue and check for queue work */
887 spin_lock_irqsave(&drv_data->lock, flags);
Mike Frysingerf4f50c32009-09-24 00:41:49 +0000888 if (list_empty(&drv_data->queue) || !drv_data->running) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700889 /* pumper kicked off but no work to do */
890 drv_data->busy = 0;
891 spin_unlock_irqrestore(&drv_data->lock, flags);
892 return;
893 }
894
895 /* Make sure we are not already running a message */
896 if (drv_data->cur_msg) {
897 spin_unlock_irqrestore(&drv_data->lock, flags);
898 return;
899 }
900
901 /* Extract head of queue */
902 drv_data->cur_msg = list_entry(drv_data->queue.next,
903 struct spi_message, queue);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800904
905 /* Setup the SSP using the per chip configuration */
906 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700907 bfin_spi_restore_state(drv_data);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800908
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700909 list_del_init(&drv_data->cur_msg->queue);
910
911 /* Initial message state */
912 drv_data->cur_msg->state = START_STATE;
913 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
914 struct spi_transfer, transfer_list);
915
Bryan Wu5fec5b52007-12-04 23:45:13 -0800916 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
917 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
918 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
919 drv_data->cur_chip->ctl_reg);
Bryan Wu131b17d2007-12-04 23:45:12 -0800920
921 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800922 "the first transfer len is %d\n",
923 drv_data->cur_transfer->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700924
925 /* Mark as busy and launch transfers */
926 tasklet_schedule(&drv_data->pump_transfers);
927
928 drv_data->busy = 1;
929 spin_unlock_irqrestore(&drv_data->lock, flags);
930}
931
932/*
933 * got a msg to transfer, queue it in drv_data->queue.
934 * And kick off message pumper
935 */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700936static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700937{
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400938 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700939 unsigned long flags;
940
941 spin_lock_irqsave(&drv_data->lock, flags);
942
Mike Frysingerf4f50c32009-09-24 00:41:49 +0000943 if (!drv_data->running) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700944 spin_unlock_irqrestore(&drv_data->lock, flags);
945 return -ESHUTDOWN;
946 }
947
948 msg->actual_length = 0;
949 msg->status = -EINPROGRESS;
950 msg->state = START_STATE;
951
Bryan Wu88b40362007-05-21 18:32:16 +0800952 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700953 list_add_tail(&msg->queue, &drv_data->queue);
954
Mike Frysingerf4f50c32009-09-24 00:41:49 +0000955 if (drv_data->running && !drv_data->busy)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700956 queue_work(drv_data->workqueue, &drv_data->pump_messages);
957
958 spin_unlock_irqrestore(&drv_data->lock, flags);
959
960 return 0;
961}
962
Sonic Zhang12e17c42007-12-04 23:45:16 -0800963#define MAX_SPI_SSEL 7
964
Mike Frysingerddc0bf12011-06-17 04:16:57 -0400965static const u16 ssel[][MAX_SPI_SSEL] = {
Sonic Zhang12e17c42007-12-04 23:45:16 -0800966 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
967 P_SPI0_SSEL4, P_SPI0_SSEL5,
968 P_SPI0_SSEL6, P_SPI0_SSEL7},
969
970 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
971 P_SPI1_SSEL4, P_SPI1_SSEL5,
972 P_SPI1_SSEL6, P_SPI1_SSEL7},
973
974 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
975 P_SPI2_SSEL4, P_SPI2_SSEL5,
976 P_SPI2_SSEL6, P_SPI2_SSEL7},
977};
978
Mike Frysingerab09e042009-09-23 23:32:34 +0000979/* setup for devices (may be called multiple times -- not just first setup) */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700980static int bfin_spi_setup(struct spi_device *spi)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700981{
Daniel Mackac01e972009-03-25 00:18:35 +0000982 struct bfin5xx_spi_chip *chip_info;
Mike Frysinger9c0a7882010-10-18 02:45:22 -0400983 struct bfin_spi_slave_data *chip = NULL;
984 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
Mike Frysinger5b47bcd2009-12-18 17:43:31 +0000985 u16 bfin_ctl_reg;
Daniel Mackac01e972009-03-25 00:18:35 +0000986 int ret = -EINVAL;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700987
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700988 /* Only alloc (or use chip_info) on first setup */
Daniel Mackac01e972009-03-25 00:18:35 +0000989 chip_info = NULL;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700990 chip = spi_get_ctldata(spi);
991 if (chip == NULL) {
Daniel Mackac01e972009-03-25 00:18:35 +0000992 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
993 if (!chip) {
994 dev_err(&spi->dev, "cannot allocate chip data\n");
995 ret = -ENOMEM;
996 goto error;
997 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700998
999 chip->enable_dma = 0;
1000 chip_info = spi->controller_data;
1001 }
1002
Mike Frysinger5b47bcd2009-12-18 17:43:31 +00001003 /* Let people set non-standard bits directly */
1004 bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
1005 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
1006
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001007 /* chip_info isn't always needed */
1008 if (chip_info) {
Mike Frysinger2ed35512007-12-04 23:45:14 -08001009 /* Make sure people stop trying to set fields via ctl_reg
1010 * when they should actually be using common SPI framework.
Mike Frysinger90008a62009-10-15 04:13:29 +00001011 * Currently we let through: WOM EMISO PSSE GM SZ.
Mike Frysinger2ed35512007-12-04 23:45:14 -08001012 * Not sure if a user actually needs/uses any of these,
1013 * but let's assume (for now) they do.
1014 */
Mike Frysinger5b47bcd2009-12-18 17:43:31 +00001015 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
Mike Frysinger2ed35512007-12-04 23:45:14 -08001016 dev_err(&spi->dev, "do not set bits in ctl_reg "
1017 "that the SPI framework manages\n");
Daniel Mackac01e972009-03-25 00:18:35 +00001018 goto error;
Mike Frysinger2ed35512007-12-04 23:45:14 -08001019 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001020 chip->enable_dma = chip_info->enable_dma != 0
1021 && drv_data->master_info->enable_dma;
1022 chip->ctl_reg = chip_info->ctl_reg;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001023 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -07001024 chip->idle_tx_val = chip_info->idle_tx_val;
Yi Lif6a6d962009-06-03 09:46:22 +00001025 chip->pio_interrupt = chip_info->pio_interrupt;
Mike Frysinger5b47bcd2009-12-18 17:43:31 +00001026 } else {
1027 /* force a default base state */
1028 chip->ctl_reg &= bfin_ctl_reg;
Mike Frysinger033f44b2009-12-18 17:38:04 +00001029 }
1030
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001031 /* translate common spi framework into our register */
Mike Frysinger7715aad2010-02-25 10:00:55 +00001032 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1033 dev_err(&spi->dev, "unsupported spi modes detected\n");
1034 goto error;
1035 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001036 if (spi->mode & SPI_CPOL)
Mike Frysinger90008a62009-10-15 04:13:29 +00001037 chip->ctl_reg |= BIT_CTL_CPOL;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001038 if (spi->mode & SPI_CPHA)
Mike Frysinger90008a62009-10-15 04:13:29 +00001039 chip->ctl_reg |= BIT_CTL_CPHA;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001040 if (spi->mode & SPI_LSB_FIRST)
Mike Frysinger90008a62009-10-15 04:13:29 +00001041 chip->ctl_reg |= BIT_CTL_LSBF;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001042 /* we dont support running in slave mode (yet?) */
Mike Frysinger90008a62009-10-15 04:13:29 +00001043 chip->ctl_reg |= BIT_CTL_MASTER;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001044
1045 /*
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001046 * Notice: for blackfin, the speed_hz is the value of register
1047 * SPI_BAUD, not the real baudrate
1048 */
1049 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001050 chip->chip_select_num = spi->chip_select;
Barry Song4190f6a2010-04-06 03:36:24 +00001051 if (chip->chip_select_num < MAX_CTRL_CS) {
1052 if (!(spi->mode & SPI_CPHA))
1053 dev_warn(&spi->dev, "Warning: SPI CPHA not set:"
1054 " Slave Select not under software control!\n"
1055 " See Documentation/blackfin/bfin-spi-notes.txt");
1056
Barry Songd3cc71f2009-11-17 09:45:59 +00001057 chip->flag = (1 << spi->chip_select) << 8;
Barry Song4190f6a2010-04-06 03:36:24 +00001058 } else
Barry Songd3cc71f2009-11-17 09:45:59 +00001059 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001060
Yi Lif6a6d962009-06-03 09:46:22 +00001061 if (chip->enable_dma && chip->pio_interrupt) {
1062 dev_err(&spi->dev, "enable_dma is set, "
1063 "do not set pio_interrupt\n");
1064 goto error;
1065 }
Daniel Mackac01e972009-03-25 00:18:35 +00001066 /*
1067 * if any one SPI chip is registered and wants DMA, request the
1068 * DMA channel for it
1069 */
1070 if (chip->enable_dma && !drv_data->dma_requested) {
1071 /* register dma irq handler */
1072 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1073 if (ret) {
1074 dev_err(&spi->dev,
1075 "Unable to request BlackFin SPI DMA channel\n");
1076 goto error;
1077 }
1078 drv_data->dma_requested = 1;
1079
1080 ret = set_dma_callback(drv_data->dma_channel,
1081 bfin_spi_dma_irq_handler, drv_data);
1082 if (ret) {
1083 dev_err(&spi->dev, "Unable to set dma callback\n");
1084 goto error;
1085 }
1086 dma_disable_irq(drv_data->dma_channel);
1087 }
1088
Yi Lif6a6d962009-06-03 09:46:22 +00001089 if (chip->pio_interrupt && !drv_data->irq_requested) {
1090 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
Yong Zhang38ada212011-10-22 17:56:55 +08001091 0, "BFIN_SPI", drv_data);
Yi Lif6a6d962009-06-03 09:46:22 +00001092 if (ret) {
1093 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1094 goto error;
1095 }
1096 drv_data->irq_requested = 1;
1097 /* we use write mode, spi irq has to be disabled here */
1098 disable_irq(drv_data->spi_irq);
1099 }
1100
Barry Songd3cc71f2009-11-17 09:45:59 +00001101 if (chip->chip_select_num >= MAX_CTRL_CS) {
Michael Hennerich73e1ac12010-10-22 02:01:47 -04001102 /* Only request on first setup */
1103 if (spi_get_ctldata(spi) == NULL) {
1104 ret = gpio_request(chip->cs_gpio, spi->modalias);
1105 if (ret) {
1106 dev_err(&spi->dev, "gpio_request() error\n");
1107 goto pin_error;
1108 }
1109 gpio_direction_output(chip->cs_gpio, 1);
Daniel Mackac01e972009-03-25 00:18:35 +00001110 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001111 }
1112
Joe Perches898eb712007-10-18 03:06:30 -07001113 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
Mike Frysinger033f44b2009-12-18 17:38:04 +00001114 spi->modalias, spi->bits_per_word, chip->enable_dma);
Bryan Wu88b40362007-05-21 18:32:16 +08001115 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001116 chip->ctl_reg, chip->flag);
1117
1118 spi_set_ctldata(spi, chip);
1119
Sonic Zhang12e17c42007-12-04 23:45:16 -08001120 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
Barry Songd3cc71f2009-11-17 09:45:59 +00001121 if (chip->chip_select_num < MAX_CTRL_CS) {
Daniel Mackac01e972009-03-25 00:18:35 +00001122 ret = peripheral_request(ssel[spi->master->bus_num]
1123 [chip->chip_select_num-1], spi->modalias);
1124 if (ret) {
1125 dev_err(&spi->dev, "peripheral_request() error\n");
1126 goto pin_error;
1127 }
1128 }
Sonic Zhang12e17c42007-12-04 23:45:16 -08001129
Barry Song82216102009-06-17 10:10:53 +00001130 bfin_spi_cs_enable(drv_data, chip);
Mike Frysinger138f97c2009-04-06 19:00:50 -07001131 bfin_spi_cs_deactive(drv_data, chip);
Sonic Zhang07612e52007-12-04 23:45:21 -08001132
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001133 return 0;
Daniel Mackac01e972009-03-25 00:18:35 +00001134
1135 pin_error:
Barry Songd3cc71f2009-11-17 09:45:59 +00001136 if (chip->chip_select_num >= MAX_CTRL_CS)
Daniel Mackac01e972009-03-25 00:18:35 +00001137 gpio_free(chip->cs_gpio);
1138 else
1139 peripheral_free(ssel[spi->master->bus_num]
1140 [chip->chip_select_num - 1]);
1141 error:
1142 if (chip) {
1143 if (drv_data->dma_requested)
1144 free_dma(drv_data->dma_channel);
1145 drv_data->dma_requested = 0;
1146
1147 kfree(chip);
1148 /* prevent free 'chip' twice */
1149 spi_set_ctldata(spi, NULL);
1150 }
1151
1152 return ret;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001153}
1154
1155/*
1156 * callback for spi framework.
1157 * clean driver specific data
1158 */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001159static void bfin_spi_cleanup(struct spi_device *spi)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001160{
Mike Frysinger9c0a7882010-10-18 02:45:22 -04001161 struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1162 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001163
Mike Frysingere7d02e32009-04-06 19:00:51 -07001164 if (!chip)
1165 return;
1166
Barry Songd3cc71f2009-11-17 09:45:59 +00001167 if (chip->chip_select_num < MAX_CTRL_CS) {
Sonic Zhang12e17c42007-12-04 23:45:16 -08001168 peripheral_free(ssel[spi->master->bus_num]
1169 [chip->chip_select_num-1]);
Barry Song82216102009-06-17 10:10:53 +00001170 bfin_spi_cs_disable(drv_data, chip);
Barry Songd3cc71f2009-11-17 09:45:59 +00001171 } else
Michael Hennerich42c78b22009-04-06 19:00:51 -07001172 gpio_free(chip->cs_gpio);
1173
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001174 kfree(chip);
Daniel Mackac01e972009-03-25 00:18:35 +00001175 /* prevent free 'chip' twice */
1176 spi_set_ctldata(spi, NULL);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001177}
1178
Mike Frysingerc52d4e52011-06-17 04:16:58 -04001179static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001180{
1181 INIT_LIST_HEAD(&drv_data->queue);
1182 spin_lock_init(&drv_data->lock);
1183
Mike Frysingerf4f50c32009-09-24 00:41:49 +00001184 drv_data->running = false;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001185 drv_data->busy = 0;
1186
1187 /* init transfer tasklet */
1188 tasklet_init(&drv_data->pump_transfers,
Mike Frysinger138f97c2009-04-06 19:00:50 -07001189 bfin_spi_pump_transfers, (unsigned long)drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001190
1191 /* init messages workqueue */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001192 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
Kay Sievers6c7377a2009-03-24 16:38:21 -07001193 drv_data->workqueue = create_singlethread_workqueue(
1194 dev_name(drv_data->master->dev.parent));
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001195 if (drv_data->workqueue == NULL)
1196 return -EBUSY;
1197
1198 return 0;
1199}
1200
Mike Frysingerc52d4e52011-06-17 04:16:58 -04001201static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001202{
1203 unsigned long flags;
1204
1205 spin_lock_irqsave(&drv_data->lock, flags);
1206
Mike Frysingerf4f50c32009-09-24 00:41:49 +00001207 if (drv_data->running || drv_data->busy) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001208 spin_unlock_irqrestore(&drv_data->lock, flags);
1209 return -EBUSY;
1210 }
1211
Mike Frysingerf4f50c32009-09-24 00:41:49 +00001212 drv_data->running = true;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001213 drv_data->cur_msg = NULL;
1214 drv_data->cur_transfer = NULL;
1215 drv_data->cur_chip = NULL;
1216 spin_unlock_irqrestore(&drv_data->lock, flags);
1217
1218 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1219
1220 return 0;
1221}
1222
Mike Frysingerc52d4e52011-06-17 04:16:58 -04001223static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001224{
1225 unsigned long flags;
1226 unsigned limit = 500;
1227 int status = 0;
1228
1229 spin_lock_irqsave(&drv_data->lock, flags);
1230
1231 /*
1232 * This is a bit lame, but is optimized for the common execution path.
1233 * A wait_queue on the drv_data->busy could be used, but then the common
1234 * execution path (pump_messages) would be required to call wake_up or
1235 * friends on every SPI message. Do this instead
1236 */
Mike Frysingerf4f50c32009-09-24 00:41:49 +00001237 drv_data->running = false;
Vasily Khoruzhick850a28e2011-04-06 17:49:15 +03001238 while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001239 spin_unlock_irqrestore(&drv_data->lock, flags);
1240 msleep(10);
1241 spin_lock_irqsave(&drv_data->lock, flags);
1242 }
1243
1244 if (!list_empty(&drv_data->queue) || drv_data->busy)
1245 status = -EBUSY;
1246
1247 spin_unlock_irqrestore(&drv_data->lock, flags);
1248
1249 return status;
1250}
1251
Mike Frysingerc52d4e52011-06-17 04:16:58 -04001252static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001253{
1254 int status;
1255
Mike Frysinger138f97c2009-04-06 19:00:50 -07001256 status = bfin_spi_stop_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001257 if (status != 0)
1258 return status;
1259
1260 destroy_workqueue(drv_data->workqueue);
1261
1262 return 0;
1263}
1264
Grant Likely2deff8d2013-02-05 13:27:35 +00001265static int bfin_spi_probe(struct platform_device *pdev)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001266{
1267 struct device *dev = &pdev->dev;
1268 struct bfin5xx_spi_master *platform_info;
1269 struct spi_master *master;
Mike Frysinger9c0a7882010-10-18 02:45:22 -04001270 struct bfin_spi_master_data *drv_data;
Bryan Wua32c6912007-12-04 23:45:15 -08001271 struct resource *res;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001272 int status = 0;
1273
Jingoo Han8074cf02013-07-30 16:58:59 +09001274 platform_info = dev_get_platdata(dev);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001275
1276 /* Allocate master with space for drv_data */
Mike Frysinger2a045132009-09-24 01:28:54 +00001277 master = spi_alloc_master(dev, sizeof(*drv_data));
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001278 if (!master) {
1279 dev_err(&pdev->dev, "can not alloc spi_master\n");
1280 return -ENOMEM;
1281 }
Bryan Wu131b17d2007-12-04 23:45:12 -08001282
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001283 drv_data = spi_master_get_devdata(master);
1284 drv_data->master = master;
1285 drv_data->master_info = platform_info;
1286 drv_data->pdev = pdev;
Bryan Wu003d9222007-12-04 23:45:22 -08001287 drv_data->pin_req = platform_info->pin_req;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001288
David Brownelle7db06b2009-06-17 16:26:04 -07001289 /* the spi->mode bits supported by this driver: */
1290 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
Stephen Warren24778be2013-05-21 20:36:35 -06001291 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001292 master->bus_num = pdev->id;
1293 master->num_chipselect = platform_info->num_chipselect;
Mike Frysinger138f97c2009-04-06 19:00:50 -07001294 master->cleanup = bfin_spi_cleanup;
1295 master->setup = bfin_spi_setup;
1296 master->transfer = bfin_spi_transfer;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001297
Bryan Wua32c6912007-12-04 23:45:15 -08001298 /* Find and map our resources */
1299 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300 if (res == NULL) {
1301 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1302 status = -ENOENT;
1303 goto out_error_get_res;
1304 }
1305
Mike Frysinger47885ce2011-06-17 04:16:56 -04001306 drv_data->regs = ioremap(res->start, resource_size(res));
1307 if (drv_data->regs == NULL) {
Bryan Wua32c6912007-12-04 23:45:15 -08001308 dev_err(dev, "Cannot map IO\n");
1309 status = -ENXIO;
1310 goto out_error_ioremap;
1311 }
1312
Yi Lif6a6d962009-06-03 09:46:22 +00001313 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1314 if (res == NULL) {
Bryan Wua32c6912007-12-04 23:45:15 -08001315 dev_err(dev, "No DMA channel specified\n");
1316 status = -ENOENT;
Yi Lif6a6d962009-06-03 09:46:22 +00001317 goto out_error_free_io;
1318 }
1319 drv_data->dma_channel = res->start;
1320
1321 drv_data->spi_irq = platform_get_irq(pdev, 0);
1322 if (drv_data->spi_irq < 0) {
1323 dev_err(dev, "No spi pio irq specified\n");
1324 status = -ENOENT;
1325 goto out_error_free_io;
Bryan Wua32c6912007-12-04 23:45:15 -08001326 }
1327
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001328 /* Initial and start queue */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001329 status = bfin_spi_init_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001330 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001331 dev_err(dev, "problem initializing queue\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001332 goto out_error_queue_alloc;
1333 }
Bryan Wua32c6912007-12-04 23:45:15 -08001334
Mike Frysinger138f97c2009-04-06 19:00:50 -07001335 status = bfin_spi_start_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001336 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001337 dev_err(dev, "problem starting queue\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001338 goto out_error_queue_alloc;
1339 }
1340
Vitja Makarovf9e522c2008-04-08 17:41:57 -07001341 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1342 if (status != 0) {
1343 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1344 goto out_error_queue_alloc;
1345 }
1346
Wolfgang Mueesbb8beecd2009-05-22 01:11:02 +00001347 /* Reset SPI registers. If these registers were used by the boot loader,
1348 * the sky may fall on your head if you enable the dma controller.
1349 */
Mike Frysinger47885ce2011-06-17 04:16:56 -04001350 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1351 bfin_write(&drv_data->regs->flg, 0xFF00);
Wolfgang Mueesbb8beecd2009-05-22 01:11:02 +00001352
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001353 /* Register with the SPI framework */
1354 platform_set_drvdata(pdev, drv_data);
1355 status = spi_register_master(master);
1356 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001357 dev_err(dev, "problem registering spi master\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001358 goto out_error_queue_alloc;
1359 }
Bryan Wua32c6912007-12-04 23:45:15 -08001360
Mike Frysinger47885ce2011-06-17 04:16:56 -04001361 dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
1362 DRV_DESC, DRV_VERSION, drv_data->regs,
Bryan Wubb90eb02007-12-04 23:45:18 -08001363 drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001364 return status;
1365
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001366out_error_queue_alloc:
Mike Frysinger138f97c2009-04-06 19:00:50 -07001367 bfin_spi_destroy_queue(drv_data);
Yi Lif6a6d962009-06-03 09:46:22 +00001368out_error_free_io:
Mike Frysinger47885ce2011-06-17 04:16:56 -04001369 iounmap(drv_data->regs);
Bryan Wua32c6912007-12-04 23:45:15 -08001370out_error_ioremap:
1371out_error_get_res:
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001372 spi_master_put(master);
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001373
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001374 return status;
1375}
1376
1377/* stop hardware and remove the driver */
Grant Likelyfd4a3192012-12-07 16:57:14 +00001378static int bfin_spi_remove(struct platform_device *pdev)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001379{
Mike Frysinger9c0a7882010-10-18 02:45:22 -04001380 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001381 int status = 0;
1382
1383 if (!drv_data)
1384 return 0;
1385
1386 /* Remove the queue */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001387 status = bfin_spi_destroy_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001388 if (status != 0)
1389 return status;
1390
1391 /* Disable the SSP at the peripheral and SOC level */
1392 bfin_spi_disable(drv_data);
1393
1394 /* Release DMA */
1395 if (drv_data->master_info->enable_dma) {
Bryan Wubb90eb02007-12-04 23:45:18 -08001396 if (dma_channel_active(drv_data->dma_channel))
1397 free_dma(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001398 }
1399
Yi Lif6a6d962009-06-03 09:46:22 +00001400 if (drv_data->irq_requested) {
1401 free_irq(drv_data->spi_irq, drv_data);
1402 drv_data->irq_requested = 0;
1403 }
1404
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001405 /* Disconnect from the SPI framework */
1406 spi_unregister_master(drv_data->master);
1407
Bryan Wu003d9222007-12-04 23:45:22 -08001408 peripheral_free_list(drv_data->pin_req);
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001409
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001410 return 0;
1411}
1412
1413#ifdef CONFIG_PM
Mike Frysinger138f97c2009-04-06 19:00:50 -07001414static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001415{
Mike Frysinger9c0a7882010-10-18 02:45:22 -04001416 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001417 int status = 0;
1418
Mike Frysinger138f97c2009-04-06 19:00:50 -07001419 status = bfin_spi_stop_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001420 if (status != 0)
1421 return status;
1422
Mike Frysinger47885ce2011-06-17 04:16:56 -04001423 drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
1424 drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
Barry Songb052fd02009-11-18 09:43:21 +00001425
1426 /*
1427 * reset SPI_CTL and SPI_FLG registers
1428 */
Mike Frysinger47885ce2011-06-17 04:16:56 -04001429 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1430 bfin_write(&drv_data->regs->flg, 0xFF00);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001431
1432 return 0;
1433}
1434
Mike Frysinger138f97c2009-04-06 19:00:50 -07001435static int bfin_spi_resume(struct platform_device *pdev)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001436{
Mike Frysinger9c0a7882010-10-18 02:45:22 -04001437 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001438 int status = 0;
1439
Mike Frysinger47885ce2011-06-17 04:16:56 -04001440 bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
1441 bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001442
1443 /* Start the queue running */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001444 status = bfin_spi_start_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001445 if (status != 0) {
1446 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1447 return status;
1448 }
1449
1450 return 0;
1451}
1452#else
Mike Frysinger138f97c2009-04-06 19:00:50 -07001453#define bfin_spi_suspend NULL
1454#define bfin_spi_resume NULL
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001455#endif /* CONFIG_PM */
1456
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001457MODULE_ALIAS("platform:bfin-spi");
Mike Frysinger138f97c2009-04-06 19:00:50 -07001458static struct platform_driver bfin_spi_driver = {
David Brownellfc3ba952007-08-30 23:56:24 -07001459 .driver = {
Bryan Wua32c6912007-12-04 23:45:15 -08001460 .name = DRV_NAME,
Bryan Wu88b40362007-05-21 18:32:16 +08001461 .owner = THIS_MODULE,
1462 },
Mike Frysinger138f97c2009-04-06 19:00:50 -07001463 .suspend = bfin_spi_suspend,
1464 .resume = bfin_spi_resume,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001465 .remove = bfin_spi_remove,
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001466};
1467
Mike Frysinger138f97c2009-04-06 19:00:50 -07001468static int __init bfin_spi_init(void)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001469{
Mike Frysinger138f97c2009-04-06 19:00:50 -07001470 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001471}
Michael Hennerich6f7c17f2010-07-01 14:34:10 +00001472subsys_initcall(bfin_spi_init);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001473
Mike Frysinger138f97c2009-04-06 19:00:50 -07001474static void __exit bfin_spi_exit(void)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001475{
Mike Frysinger138f97c2009-04-06 19:00:50 -07001476 platform_driver_unregister(&bfin_spi_driver);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001477}
Mike Frysinger138f97c2009-04-06 19:00:50 -07001478module_exit(bfin_spi_exit);