Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 1 | config ARM64 |
| 2 | def_bool y |
Lorenzo Pieralisi | d8f4f16 | 2015-03-24 17:58:51 +0000 | [diff] [blame] | 3 | select ACPI_GENERIC_GSI if ACPI |
Al Stone | 6933de0 | 2015-03-24 14:02:51 +0000 | [diff] [blame] | 4 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
Kees Cook | 2b68f6c | 2015-04-14 15:48:00 -0700 | [diff] [blame] | 6 | select ARCH_HAS_ELF_RANDOMIZE |
Riku Voipio | 957e3fa | 2014-12-12 16:57:44 -0800 | [diff] [blame] | 7 | select ARCH_HAS_GCOV_PROFILE_ALL |
Laura Abbott | 308c09f | 2014-08-08 14:23:25 -0700 | [diff] [blame] | 8 | select ARCH_HAS_SG_CHAIN |
Lorenzo Pieralisi | 1f85008 | 2013-09-04 10:55:17 +0100 | [diff] [blame] | 9 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
Sudeep Holla | c63c870 | 2014-05-09 10:33:01 +0100 | [diff] [blame] | 10 | select ARCH_USE_CMPXCHG_LOCKREF |
Peter Zijlstra | 4badad3 | 2014-06-06 19:53:16 +0200 | [diff] [blame] | 11 | select ARCH_SUPPORTS_ATOMIC_RMW |
Arnd Bergmann | 9170100 | 2013-02-21 11:42:57 +0100 | [diff] [blame] | 12 | select ARCH_WANT_OPTIONAL_GPIOLIB |
Will Deacon | 6212a51 | 2012-11-07 14:16:28 +0000 | [diff] [blame] | 13 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
Catalin Marinas | b6f3598 | 2013-01-29 18:25:41 +0000 | [diff] [blame] | 14 | select ARCH_WANT_FRAME_POINTERS |
Catalin Marinas | 25c92a3 | 2012-12-18 15:26:13 +0000 | [diff] [blame] | 15 | select ARM_AMBA |
Mark Rutland | 1aee5d7 | 2012-11-20 10:06:00 +0000 | [diff] [blame] | 16 | select ARM_ARCH_TIMER |
Catalin Marinas | c4188ed | 2013-01-14 12:39:31 +0000 | [diff] [blame] | 17 | select ARM_GIC |
AKASHI Takahiro | 875cbf3 | 2014-07-04 08:28:30 +0100 | [diff] [blame] | 18 | select AUDIT_ARCH_COMPAT_GENERIC |
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 19 | select ARM_GIC_V2M if PCI_MSI |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 20 | select ARM_GIC_V3 |
Marc Zyngier | 1981272 | 2014-11-24 14:35:19 +0000 | [diff] [blame] | 21 | select ARM_GIC_V3_ITS if PCI_MSI |
Will Deacon | adace89 | 2013-05-08 17:29:24 +0100 | [diff] [blame] | 22 | select BUILDTIME_EXTABLE_SORT |
Catalin Marinas | db2789b | 2012-12-18 15:27:25 +0000 | [diff] [blame] | 23 | select CLONE_BACKWARDS |
Deepak Saxena | 7ca2ef3 | 2012-09-22 10:33:36 -0700 | [diff] [blame] | 24 | select COMMON_CLK |
Lorenzo Pieralisi | 166936b | 2013-11-07 18:37:14 +0000 | [diff] [blame] | 25 | select CPU_PM if (SUSPEND || CPU_IDLE) |
Will Deacon | 7bc13fd | 2013-11-06 19:32:13 +0000 | [diff] [blame] | 26 | select DCACHE_WORD_ACCESS |
Laura Abbott | d4932f9 | 2014-10-09 15:26:44 -0700 | [diff] [blame] | 27 | select GENERIC_ALLOCATOR |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 28 | select GENERIC_CLOCKEVENTS |
Lorenzo Pieralisi | 1f85008 | 2013-09-04 10:55:17 +0100 | [diff] [blame] | 29 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
Ard Biesheuvel | 3be1a5c | 2014-03-04 01:10:04 +0000 | [diff] [blame] | 30 | select GENERIC_CPU_AUTOPROBE |
Mark Salter | bf4b558 | 2014-04-07 15:39:52 -0700 | [diff] [blame] | 31 | select GENERIC_EARLY_IOREMAP |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 32 | select GENERIC_IRQ_PROBE |
| 33 | select GENERIC_IRQ_SHOW |
Sudeep Holla | 6544e67 | 2015-04-22 18:16:33 +0100 | [diff] [blame] | 34 | select GENERIC_IRQ_SHOW_LEVEL |
Arnd Bergmann | cb61f67 | 2014-11-19 14:09:07 +0100 | [diff] [blame] | 35 | select GENERIC_PCI_IOMAP |
Stephen Boyd | 65cd4f6 | 2013-07-18 16:21:18 -0700 | [diff] [blame] | 36 | select GENERIC_SCHED_CLOCK |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 37 | select GENERIC_SMP_IDLE_THREAD |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 38 | select GENERIC_STRNCPY_FROM_USER |
| 39 | select GENERIC_STRNLEN_USER |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 40 | select GENERIC_TIME_VSYSCALL |
Marc Zyngier | a1ddc74 | 2014-08-26 11:03:17 +0100 | [diff] [blame] | 41 | select HANDLE_DOMAIN_IRQ |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 42 | select HARDIRQS_SW_RESEND |
Steve Capper | 5284e1b | 2014-10-24 13:22:20 +0100 | [diff] [blame] | 43 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
AKASHI Takahiro | 875cbf3 | 2014-07-04 08:28:30 +0100 | [diff] [blame] | 44 | select HAVE_ARCH_AUDITSYSCALL |
Yalin Wang | 8e7a4ce | 2014-11-03 03:02:23 +0100 | [diff] [blame] | 45 | select HAVE_ARCH_BITREVERSE |
Jiang Liu | 9732caf | 2014-01-07 22:17:13 +0800 | [diff] [blame] | 46 | select HAVE_ARCH_JUMP_LABEL |
Vijaya Kumar K | 9529247 | 2014-01-28 11:20:22 +0000 | [diff] [blame] | 47 | select HAVE_ARCH_KGDB |
AKASHI Takahiro | a1ae65b | 2014-11-28 05:26:39 +0000 | [diff] [blame] | 48 | select HAVE_ARCH_SECCOMP_FILTER |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 49 | select HAVE_ARCH_TRACEHOOK |
Zi Shen Lim | e54bcde | 2014-08-26 21:15:30 -0700 | [diff] [blame] | 50 | select HAVE_BPF_JIT |
AKASHI Takahiro | af64d2a | 2014-04-30 10:54:32 +0100 | [diff] [blame] | 51 | select HAVE_C_RECORDMCOUNT |
Laura Abbott | c0c264a | 2014-06-25 23:55:03 +0100 | [diff] [blame] | 52 | select HAVE_CC_STACKPROTECTOR |
Steve Capper | 5284e1b | 2014-10-24 13:22:20 +0100 | [diff] [blame] | 53 | select HAVE_CMPXCHG_DOUBLE |
Catalin Marinas | 9b2a60c | 2012-10-08 16:28:13 -0700 | [diff] [blame] | 54 | select HAVE_DEBUG_BUGVERBOSE |
Catalin Marinas | b69ec42 | 2012-10-08 16:28:11 -0700 | [diff] [blame] | 55 | select HAVE_DEBUG_KMEMLEAK |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 56 | select HAVE_DMA_API_DEBUG |
| 57 | select HAVE_DMA_ATTRS |
Laura Abbott | 6ac2104 | 2013-12-12 19:28:33 +0000 | [diff] [blame] | 58 | select HAVE_DMA_CONTIGUOUS |
AKASHI Takahiro | bd7d38d | 2014-04-30 10:54:34 +0100 | [diff] [blame] | 59 | select HAVE_DYNAMIC_FTRACE |
Will Deacon | 50afc33 | 2013-12-16 17:50:08 +0000 | [diff] [blame] | 60 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
AKASHI Takahiro | af64d2a | 2014-04-30 10:54:32 +0100 | [diff] [blame] | 61 | select HAVE_FTRACE_MCOUNT_RECORD |
AKASHI Takahiro | 819e50e | 2014-04-30 18:54:33 +0900 | [diff] [blame] | 62 | select HAVE_FUNCTION_TRACER |
| 63 | select HAVE_FUNCTION_GRAPH_TRACER |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 64 | select HAVE_GENERIC_DMA_COHERENT |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 65 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 66 | select HAVE_MEMBLOCK |
Mark Rutland | 55834a7 | 2014-02-07 17:12:45 +0000 | [diff] [blame] | 67 | select HAVE_PATA_PLATFORM |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 68 | select HAVE_PERF_EVENTS |
Jean Pihet | 2ee0d7f | 2014-02-03 19:18:27 +0100 | [diff] [blame] | 69 | select HAVE_PERF_REGS |
| 70 | select HAVE_PERF_USER_STACK_DUMP |
Steve Capper | 5e5f6dc | 2014-10-09 15:29:23 -0700 | [diff] [blame] | 71 | select HAVE_RCU_TABLE_FREE |
AKASHI Takahiro | 055b121 | 2014-04-30 10:54:36 +0100 | [diff] [blame] | 72 | select HAVE_SYSCALL_TRACEPOINTS |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 73 | select IRQ_DOMAIN |
Catalin Marinas | fea2aca | 2012-10-16 11:26:57 +0100 | [diff] [blame] | 74 | select MODULES_USE_ELF_RELA |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 75 | select NO_BOOTMEM |
| 76 | select OF |
| 77 | select OF_EARLY_FLATTREE |
Marek Szyprowski | 9bf14b7 | 2014-02-28 14:42:55 +0100 | [diff] [blame] | 78 | select OF_RESERVED_MEM |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 79 | select PERF_USE_VMALLOC |
Catalin Marinas | aa1e8ec | 2013-02-28 18:14:37 +0000 | [diff] [blame] | 80 | select POWER_RESET |
| 81 | select POWER_SUPPLY |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 82 | select RTC_LIB |
| 83 | select SPARSE_IRQ |
Catalin Marinas | 7ac57a8 | 2012-10-08 16:28:16 -0700 | [diff] [blame] | 84 | select SYSCTL_EXCEPTION_TRACE |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 85 | select HAVE_CONTEXT_TRACKING |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 86 | help |
| 87 | ARM 64-bit (AArch64) Linux support. |
| 88 | |
| 89 | config 64BIT |
| 90 | def_bool y |
| 91 | |
| 92 | config ARCH_PHYS_ADDR_T_64BIT |
| 93 | def_bool y |
| 94 | |
| 95 | config MMU |
| 96 | def_bool y |
| 97 | |
Uwe Kleine-König | ce816fa | 2014-04-07 15:39:19 -0700 | [diff] [blame] | 98 | config NO_IOPORT_MAP |
Liviu Dudau | d1e6dc9 | 2014-09-29 15:29:31 +0100 | [diff] [blame] | 99 | def_bool y if !PCI |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 100 | |
| 101 | config STACKTRACE_SUPPORT |
| 102 | def_bool y |
| 103 | |
| 104 | config LOCKDEP_SUPPORT |
| 105 | def_bool y |
| 106 | |
| 107 | config TRACE_IRQFLAGS_SUPPORT |
| 108 | def_bool y |
| 109 | |
Will Deacon | c209f79 | 2014-03-14 17:47:05 +0000 | [diff] [blame] | 110 | config RWSEM_XCHGADD_ALGORITHM |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 111 | def_bool y |
| 112 | |
| 113 | config GENERIC_HWEIGHT |
| 114 | def_bool y |
| 115 | |
| 116 | config GENERIC_CSUM |
| 117 | def_bool y |
| 118 | |
| 119 | config GENERIC_CALIBRATE_DELAY |
| 120 | def_bool y |
| 121 | |
Catalin Marinas | 19e7640 | 2014-02-27 12:09:22 +0000 | [diff] [blame] | 122 | config ZONE_DMA |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 123 | def_bool y |
| 124 | |
Steve Capper | 29e5694 | 2014-10-09 15:29:25 -0700 | [diff] [blame] | 125 | config HAVE_GENERIC_RCU_GUP |
| 126 | def_bool y |
| 127 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 128 | config ARCH_DMA_ADDR_T_64BIT |
| 129 | def_bool y |
| 130 | |
| 131 | config NEED_DMA_MAP_STATE |
| 132 | def_bool y |
| 133 | |
| 134 | config NEED_SG_DMA_LENGTH |
| 135 | def_bool y |
| 136 | |
| 137 | config SWIOTLB |
| 138 | def_bool y |
| 139 | |
| 140 | config IOMMU_HELPER |
| 141 | def_bool SWIOTLB |
| 142 | |
Ard Biesheuvel | 4cfb361 | 2013-07-09 14:18:12 +0100 | [diff] [blame] | 143 | config KERNEL_MODE_NEON |
| 144 | def_bool y |
| 145 | |
Rob Herring | 92cc15f | 2014-04-18 17:19:59 -0500 | [diff] [blame] | 146 | config FIX_EARLYCON_MEM |
| 147 | def_bool y |
| 148 | |
Kirill A. Shutemov | 9f25e6a | 2015-04-14 15:45:39 -0700 | [diff] [blame] | 149 | config PGTABLE_LEVELS |
| 150 | int |
| 151 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
| 152 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 |
| 153 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 |
| 154 | default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 |
| 155 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 156 | source "init/Kconfig" |
| 157 | |
| 158 | source "kernel/Kconfig.freezer" |
| 159 | |
Catalin Marinas | 1ae90e7 | 2012-09-05 17:47:44 +0100 | [diff] [blame] | 160 | menu "Platform selection" |
| 161 | |
Alim Akhtar | 6f56eef | 2014-11-22 22:41:52 +0900 | [diff] [blame] | 162 | config ARCH_EXYNOS |
| 163 | bool |
| 164 | help |
| 165 | This enables support for Samsung Exynos SoC family |
| 166 | |
| 167 | config ARCH_EXYNOS7 |
| 168 | bool "ARMv8 based Samsung Exynos7" |
| 169 | select ARCH_EXYNOS |
| 170 | select COMMON_CLK_SAMSUNG |
| 171 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
| 172 | select HAVE_S3C_RTC if RTC_CLASS |
| 173 | select PINCTRL |
| 174 | select PINCTRL_EXYNOS |
| 175 | |
| 176 | help |
| 177 | This enables support for Samsung Exynos7 SoC family |
| 178 | |
Olof Johansson | 5118a6a | 2015-01-27 16:19:11 -0800 | [diff] [blame] | 179 | config ARCH_FSL_LS2085A |
| 180 | bool "Freescale LS2085A SOC" |
| 181 | help |
| 182 | This enables support for Freescale LS2085A SOC. |
| 183 | |
Eddie Huang | 4727a6f | 2015-12-01 10:14:00 +0100 | [diff] [blame] | 184 | config ARCH_MEDIATEK |
| 185 | bool "Mediatek MT65xx & MT81xx ARMv8 SoC" |
| 186 | select ARM_GIC |
Yingjoe Chen | 0a233cd | 2015-03-06 14:24:50 +0800 | [diff] [blame] | 187 | select PINCTRL |
Eddie Huang | 4727a6f | 2015-12-01 10:14:00 +0100 | [diff] [blame] | 188 | help |
| 189 | Support for Mediatek MT65xx & MT81xx ARMv8 SoCs |
| 190 | |
Abhimanyu Kapur | d7f64a4 | 2013-10-15 21:11:09 -0700 | [diff] [blame] | 191 | config ARCH_QCOM |
| 192 | bool "Qualcomm Platforms" |
| 193 | select PINCTRL |
| 194 | help |
| 195 | This enables support for the ARMv8 based Qualcomm chipsets. |
| 196 | |
Suravee Suthikulpanit | 4190436 | 2014-11-26 11:51:09 +0700 | [diff] [blame] | 197 | config ARCH_SEATTLE |
| 198 | bool "AMD Seattle SoC Family" |
| 199 | help |
| 200 | This enables support for AMD Seattle SOC Family |
| 201 | |
Paul Walmsley | d035fdf | 2015-01-07 01:17:33 -0700 | [diff] [blame] | 202 | config ARCH_TEGRA |
| 203 | bool "NVIDIA Tegra SoC Family" |
| 204 | select ARCH_HAS_RESET_CONTROLLER |
| 205 | select ARCH_REQUIRE_GPIOLIB |
| 206 | select CLKDEV_LOOKUP |
| 207 | select CLKSRC_MMIO |
| 208 | select CLKSRC_OF |
| 209 | select GENERIC_CLOCKEVENTS |
| 210 | select HAVE_CLK |
Paul Walmsley | d035fdf | 2015-01-07 01:17:33 -0700 | [diff] [blame] | 211 | select PINCTRL |
| 212 | select RESET_CONTROLLER |
| 213 | help |
| 214 | This enables support for the NVIDIA Tegra SoC family. |
| 215 | |
| 216 | config ARCH_TEGRA_132_SOC |
| 217 | bool "NVIDIA Tegra132 SoC" |
| 218 | depends on ARCH_TEGRA |
| 219 | select PINCTRL_TEGRA124 |
Paul Walmsley | d035fdf | 2015-01-07 01:17:33 -0700 | [diff] [blame] | 220 | select USB_ULPI if USB_PHY |
| 221 | select USB_ULPI_VIEWPORT if USB_PHY |
| 222 | help |
| 223 | Enable support for NVIDIA Tegra132 SoC, based on the Denver |
| 224 | ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, |
| 225 | but contains an NVIDIA Denver CPU complex in place of |
| 226 | Tegra124's "4+1" Cortex-A15 CPU complex. |
| 227 | |
Zhizhou Zhang | c4bb799 | 2015-03-11 02:27:08 +0000 | [diff] [blame] | 228 | config ARCH_SPRD |
| 229 | bool "Spreadtrum SoC platform" |
| 230 | help |
| 231 | Support for Spreadtrum ARM based SoCs |
| 232 | |
Radha Mohan Chintakuntla | 28f7420 | 2014-04-08 18:47:51 +0530 | [diff] [blame] | 233 | config ARCH_THUNDER |
| 234 | bool "Cavium Inc. Thunder SoC Family" |
| 235 | help |
| 236 | This enables support for Cavium's Thunder Family of SoCs. |
| 237 | |
Catalin Marinas | 1ae90e7 | 2012-09-05 17:47:44 +0100 | [diff] [blame] | 238 | config ARCH_VEXPRESS |
| 239 | bool "ARMv8 software model (Versatile Express)" |
| 240 | select ARCH_REQUIRE_GPIOLIB |
| 241 | select COMMON_CLK_VERSATILE |
Catalin Marinas | aa1e8ec | 2013-02-28 18:14:37 +0000 | [diff] [blame] | 242 | select POWER_RESET_VEXPRESS |
Catalin Marinas | 1ae90e7 | 2012-09-05 17:47:44 +0100 | [diff] [blame] | 243 | select VEXPRESS_CONFIG |
| 244 | help |
| 245 | This enables support for the ARMv8 software model (Versatile |
| 246 | Express). |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 247 | |
Vinayak Kale | 1594285 | 2013-04-24 10:06:57 +0100 | [diff] [blame] | 248 | config ARCH_XGENE |
| 249 | bool "AppliedMicro X-Gene SOC Family" |
| 250 | help |
| 251 | This enables support for AppliedMicro X-Gene SOC Family |
| 252 | |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 253 | config ARCH_ZYNQMP |
| 254 | bool "Xilinx ZynqMP Family" |
| 255 | help |
| 256 | This enables support for Xilinx ZynqMP Family |
| 257 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 258 | endmenu |
| 259 | |
| 260 | menu "Bus support" |
| 261 | |
Liviu Dudau | d1e6dc9 | 2014-09-29 15:29:31 +0100 | [diff] [blame] | 262 | config PCI |
| 263 | bool "PCI support" |
| 264 | help |
| 265 | This feature enables support for PCI bus system. If you say Y |
| 266 | here, the kernel will include drivers and infrastructure code |
| 267 | to support PCI bus devices. |
| 268 | |
| 269 | config PCI_DOMAINS |
| 270 | def_bool PCI |
| 271 | |
| 272 | config PCI_DOMAINS_GENERIC |
| 273 | def_bool PCI |
| 274 | |
| 275 | config PCI_SYSCALL |
| 276 | def_bool PCI |
| 277 | |
| 278 | source "drivers/pci/Kconfig" |
| 279 | source "drivers/pci/pcie/Kconfig" |
| 280 | source "drivers/pci/hotplug/Kconfig" |
| 281 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 282 | endmenu |
| 283 | |
| 284 | menu "Kernel Features" |
| 285 | |
Andre Przywara | c0a01b8 | 2014-11-14 15:54:12 +0000 | [diff] [blame] | 286 | menu "ARM errata workarounds via the alternatives framework" |
| 287 | |
| 288 | config ARM64_ERRATUM_826319 |
| 289 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" |
| 290 | default y |
| 291 | help |
| 292 | This option adds an alternative code sequence to work around ARM |
| 293 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or |
| 294 | AXI master interface and an L2 cache. |
| 295 | |
| 296 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors |
| 297 | and is unable to accept a certain write via this interface, it will |
| 298 | not progress on read data presented on the read data channel and the |
| 299 | system can deadlock. |
| 300 | |
| 301 | The workaround promotes data cache clean instructions to |
| 302 | data cache clean-and-invalidate. |
| 303 | Please note that this does not necessarily enable the workaround, |
| 304 | as it depends on the alternative framework, which will only patch |
| 305 | the kernel if an affected CPU is detected. |
| 306 | |
| 307 | If unsure, say Y. |
| 308 | |
| 309 | config ARM64_ERRATUM_827319 |
| 310 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" |
| 311 | default y |
| 312 | help |
| 313 | This option adds an alternative code sequence to work around ARM |
| 314 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI |
| 315 | master interface and an L2 cache. |
| 316 | |
| 317 | Under certain conditions this erratum can cause a clean line eviction |
| 318 | to occur at the same time as another transaction to the same address |
| 319 | on the AMBA 5 CHI interface, which can cause data corruption if the |
| 320 | interconnect reorders the two transactions. |
| 321 | |
| 322 | The workaround promotes data cache clean instructions to |
| 323 | data cache clean-and-invalidate. |
| 324 | Please note that this does not necessarily enable the workaround, |
| 325 | as it depends on the alternative framework, which will only patch |
| 326 | the kernel if an affected CPU is detected. |
| 327 | |
| 328 | If unsure, say Y. |
| 329 | |
| 330 | config ARM64_ERRATUM_824069 |
| 331 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" |
| 332 | default y |
| 333 | help |
| 334 | This option adds an alternative code sequence to work around ARM |
| 335 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected |
| 336 | to a coherent interconnect. |
| 337 | |
| 338 | If a Cortex-A53 processor is executing a store or prefetch for |
| 339 | write instruction at the same time as a processor in another |
| 340 | cluster is executing a cache maintenance operation to the same |
| 341 | address, then this erratum might cause a clean cache line to be |
| 342 | incorrectly marked as dirty. |
| 343 | |
| 344 | The workaround promotes data cache clean instructions to |
| 345 | data cache clean-and-invalidate. |
| 346 | Please note that this option does not necessarily enable the |
| 347 | workaround, as it depends on the alternative framework, which will |
| 348 | only patch the kernel if an affected CPU is detected. |
| 349 | |
| 350 | If unsure, say Y. |
| 351 | |
| 352 | config ARM64_ERRATUM_819472 |
| 353 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" |
| 354 | default y |
| 355 | help |
| 356 | This option adds an alternative code sequence to work around ARM |
| 357 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache |
| 358 | present when it is connected to a coherent interconnect. |
| 359 | |
| 360 | If the processor is executing a load and store exclusive sequence at |
| 361 | the same time as a processor in another cluster is executing a cache |
| 362 | maintenance operation to the same address, then this erratum might |
| 363 | cause data corruption. |
| 364 | |
| 365 | The workaround promotes data cache clean instructions to |
| 366 | data cache clean-and-invalidate. |
| 367 | Please note that this does not necessarily enable the workaround, |
| 368 | as it depends on the alternative framework, which will only patch |
| 369 | the kernel if an affected CPU is detected. |
| 370 | |
| 371 | If unsure, say Y. |
| 372 | |
| 373 | config ARM64_ERRATUM_832075 |
| 374 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" |
| 375 | default y |
| 376 | help |
| 377 | This option adds an alternative code sequence to work around ARM |
| 378 | erratum 832075 on Cortex-A57 parts up to r1p2. |
| 379 | |
| 380 | Affected Cortex-A57 parts might deadlock when exclusive load/store |
| 381 | instructions to Write-Back memory are mixed with Device loads. |
| 382 | |
| 383 | The workaround is to promote device loads to use Load-Acquire |
| 384 | semantics. |
| 385 | Please note that this does not necessarily enable the workaround, |
| 386 | as it depends on the alternative framework, which will only patch |
| 387 | the kernel if an affected CPU is detected. |
| 388 | |
| 389 | If unsure, say Y. |
| 390 | |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 391 | config ARM64_ERRATUM_845719 |
| 392 | bool "Cortex-A53: 845719: a load might read incorrect data" |
| 393 | depends on COMPAT |
| 394 | default y |
| 395 | help |
| 396 | This option adds an alternative code sequence to work around ARM |
| 397 | erratum 845719 on Cortex-A53 parts up to r0p4. |
| 398 | |
| 399 | When running a compat (AArch32) userspace on an affected Cortex-A53 |
| 400 | part, a load at EL0 from a virtual address that matches the bottom 32 |
| 401 | bits of the virtual address used by a recent load at (AArch64) EL1 |
| 402 | might return incorrect data. |
| 403 | |
| 404 | The workaround is to write the contextidr_el1 register on exception |
| 405 | return to a 32-bit task. |
| 406 | Please note that this does not necessarily enable the workaround, |
| 407 | as it depends on the alternative framework, which will only patch |
| 408 | the kernel if an affected CPU is detected. |
| 409 | |
| 410 | If unsure, say Y. |
| 411 | |
Andre Przywara | c0a01b8 | 2014-11-14 15:54:12 +0000 | [diff] [blame] | 412 | endmenu |
| 413 | |
| 414 | |
Jungseok Lee | e41ceed | 2014-05-12 10:40:38 +0100 | [diff] [blame] | 415 | choice |
| 416 | prompt "Page size" |
| 417 | default ARM64_4K_PAGES |
| 418 | help |
| 419 | Page size (translation granule) configuration. |
| 420 | |
| 421 | config ARM64_4K_PAGES |
| 422 | bool "4KB" |
| 423 | help |
| 424 | This feature enables 4KB pages support. |
| 425 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 426 | config ARM64_64K_PAGES |
Jungseok Lee | e41ceed | 2014-05-12 10:40:38 +0100 | [diff] [blame] | 427 | bool "64KB" |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 428 | help |
| 429 | This feature enables 64KB pages support (4KB by default) |
| 430 | allowing only two levels of page tables and faster TLB |
| 431 | look-up. AArch32 emulation is not available when this feature |
| 432 | is enabled. |
| 433 | |
Jungseok Lee | e41ceed | 2014-05-12 10:40:38 +0100 | [diff] [blame] | 434 | endchoice |
| 435 | |
| 436 | choice |
| 437 | prompt "Virtual address space size" |
| 438 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES |
| 439 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
| 440 | help |
| 441 | Allows choosing one of multiple possible virtual address |
| 442 | space sizes. The level of translation table is determined by |
| 443 | a combination of page size and virtual address space size. |
| 444 | |
| 445 | config ARM64_VA_BITS_39 |
| 446 | bool "39-bit" |
| 447 | depends on ARM64_4K_PAGES |
| 448 | |
| 449 | config ARM64_VA_BITS_42 |
| 450 | bool "42-bit" |
| 451 | depends on ARM64_64K_PAGES |
| 452 | |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 453 | config ARM64_VA_BITS_48 |
| 454 | bool "48-bit" |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 455 | |
Jungseok Lee | e41ceed | 2014-05-12 10:40:38 +0100 | [diff] [blame] | 456 | endchoice |
| 457 | |
| 458 | config ARM64_VA_BITS |
| 459 | int |
| 460 | default 39 if ARM64_VA_BITS_39 |
| 461 | default 42 if ARM64_VA_BITS_42 |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 462 | default 48 if ARM64_VA_BITS_48 |
Jungseok Lee | e41ceed | 2014-05-12 10:40:38 +0100 | [diff] [blame] | 463 | |
Will Deacon | a872013 | 2013-10-11 14:52:19 +0100 | [diff] [blame] | 464 | config CPU_BIG_ENDIAN |
| 465 | bool "Build big-endian kernel" |
| 466 | help |
| 467 | Say Y if you plan on running a kernel in big-endian mode. |
| 468 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 469 | config SMP |
| 470 | bool "Symmetric Multi-Processing" |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 471 | help |
| 472 | This enables support for systems with more than one CPU. If |
| 473 | you say N here, the kernel will run on single and |
| 474 | multiprocessor machines, but will use only one CPU of a |
| 475 | multiprocessor machine. If you say Y here, the kernel will run |
| 476 | on many, but not all, single processor machines. On a single |
| 477 | processor machine, the kernel will run faster if you say N |
| 478 | here. |
| 479 | |
| 480 | If you don't know what to do here, say N. |
| 481 | |
Mark Brown | f6e763b | 2014-03-04 07:51:17 +0000 | [diff] [blame] | 482 | config SCHED_MC |
| 483 | bool "Multi-core scheduler support" |
| 484 | depends on SMP |
| 485 | help |
| 486 | Multi-core scheduler support improves the CPU scheduler's decision |
| 487 | making when dealing with multi-core CPU chips at a cost of slightly |
| 488 | increased overhead in some places. If unsure say N here. |
| 489 | |
| 490 | config SCHED_SMT |
| 491 | bool "SMT scheduler support" |
| 492 | depends on SMP |
| 493 | help |
| 494 | Improves the CPU scheduler's decision making when dealing with |
| 495 | MultiThreading at a cost of slightly increased overhead in some |
| 496 | places. If unsure say N here. |
| 497 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 498 | config NR_CPUS |
Ganapatrao Kulkarni | 62aa965 | 2015-03-18 11:01:18 +0000 | [diff] [blame] | 499 | int "Maximum number of CPUs (2-4096)" |
| 500 | range 2 4096 |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 501 | depends on SMP |
Vinayak Kale | 1594285 | 2013-04-24 10:06:57 +0100 | [diff] [blame] | 502 | # These have to remain sorted largest to smallest |
Robert Richter | e367264 | 2014-09-08 12:44:48 +0100 | [diff] [blame] | 503 | default "64" |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 504 | |
Mark Rutland | 9327e2c | 2013-10-24 20:30:18 +0100 | [diff] [blame] | 505 | config HOTPLUG_CPU |
| 506 | bool "Support for hot-pluggable CPUs" |
| 507 | depends on SMP |
| 508 | help |
| 509 | Say Y here to experiment with turning CPUs off and on. CPUs |
| 510 | can be controlled through /sys/devices/system/cpu. |
| 511 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 512 | source kernel/Kconfig.preempt |
| 513 | |
Mark Rutland | 137650aa | 2015-03-13 16:14:34 +0000 | [diff] [blame] | 514 | config UP_LATE_INIT |
| 515 | def_bool y |
| 516 | depends on !SMP |
| 517 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 518 | config HZ |
| 519 | int |
| 520 | default 100 |
| 521 | |
| 522 | config ARCH_HAS_HOLES_MEMORYMODEL |
| 523 | def_bool y if SPARSEMEM |
| 524 | |
| 525 | config ARCH_SPARSEMEM_ENABLE |
| 526 | def_bool y |
| 527 | select SPARSEMEM_VMEMMAP_ENABLE |
| 528 | |
| 529 | config ARCH_SPARSEMEM_DEFAULT |
| 530 | def_bool ARCH_SPARSEMEM_ENABLE |
| 531 | |
| 532 | config ARCH_SELECT_MEMORY_MODEL |
| 533 | def_bool ARCH_SPARSEMEM_ENABLE |
| 534 | |
| 535 | config HAVE_ARCH_PFN_VALID |
| 536 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM |
| 537 | |
| 538 | config HW_PERF_EVENTS |
| 539 | bool "Enable hardware performance counter support for perf events" |
| 540 | depends on PERF_EVENTS |
| 541 | default y |
| 542 | help |
| 543 | Enable hardware performance counter support for perf events. If |
| 544 | disabled, perf events will use software events only. |
| 545 | |
Steve Capper | 084bd29 | 2013-04-10 13:48:00 +0100 | [diff] [blame] | 546 | config SYS_SUPPORTS_HUGETLBFS |
| 547 | def_bool y |
| 548 | |
| 549 | config ARCH_WANT_GENERAL_HUGETLB |
| 550 | def_bool y |
| 551 | |
| 552 | config ARCH_WANT_HUGE_PMD_SHARE |
| 553 | def_bool y if !ARM64_64K_PAGES |
| 554 | |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 555 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
| 556 | def_bool y |
| 557 | |
Catalin Marinas | a41dc0e | 2014-04-03 17:48:54 +0100 | [diff] [blame] | 558 | config ARCH_HAS_CACHE_LINE_SIZE |
| 559 | def_bool y |
| 560 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 561 | source "mm/Kconfig" |
| 562 | |
AKASHI Takahiro | a1ae65b | 2014-11-28 05:26:39 +0000 | [diff] [blame] | 563 | config SECCOMP |
| 564 | bool "Enable seccomp to safely compute untrusted bytecode" |
| 565 | ---help--- |
| 566 | This kernel feature is useful for number crunching applications |
| 567 | that may need to compute untrusted bytecode during their |
| 568 | execution. By using pipes or other transports made available to |
| 569 | the process as file descriptors supporting the read/write |
| 570 | syscalls, it's possible to isolate those applications in |
| 571 | their own address space using seccomp. Once seccomp is |
| 572 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled |
| 573 | and the task is only allowed to execute a few safe syscalls |
| 574 | defined by each seccomp mode. |
| 575 | |
Stefano Stabellini | aa42aa1 | 2013-06-03 17:05:43 +0000 | [diff] [blame] | 576 | config XEN_DOM0 |
| 577 | def_bool y |
| 578 | depends on XEN |
| 579 | |
| 580 | config XEN |
Julien Grall | c2ba1f7 | 2014-09-17 14:07:06 -0700 | [diff] [blame] | 581 | bool "Xen guest support on ARM64" |
Stefano Stabellini | aa42aa1 | 2013-06-03 17:05:43 +0000 | [diff] [blame] | 582 | depends on ARM64 && OF |
Stefano Stabellini | 83862cc | 2013-10-10 13:40:44 +0000 | [diff] [blame] | 583 | select SWIOTLB_XEN |
Stefano Stabellini | aa42aa1 | 2013-06-03 17:05:43 +0000 | [diff] [blame] | 584 | help |
| 585 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. |
| 586 | |
Steve Capper | d03bb14 | 2013-04-25 15:19:21 +0100 | [diff] [blame] | 587 | config FORCE_MAX_ZONEORDER |
| 588 | int |
| 589 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) |
| 590 | default "11" |
| 591 | |
Will Deacon | 1b907f4 | 2014-11-20 16:51:10 +0000 | [diff] [blame] | 592 | menuconfig ARMV8_DEPRECATED |
| 593 | bool "Emulate deprecated/obsolete ARMv8 instructions" |
| 594 | depends on COMPAT |
| 595 | help |
| 596 | Legacy software support may require certain instructions |
| 597 | that have been deprecated or obsoleted in the architecture. |
| 598 | |
| 599 | Enable this config to enable selective emulation of these |
| 600 | features. |
| 601 | |
| 602 | If unsure, say Y |
| 603 | |
| 604 | if ARMV8_DEPRECATED |
| 605 | |
| 606 | config SWP_EMULATION |
| 607 | bool "Emulate SWP/SWPB instructions" |
| 608 | help |
| 609 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that |
| 610 | they are always undefined. Say Y here to enable software |
| 611 | emulation of these instructions for userspace using LDXR/STXR. |
| 612 | |
| 613 | In some older versions of glibc [<=2.8] SWP is used during futex |
| 614 | trylock() operations with the assumption that the code will not |
| 615 | be preempted. This invalid assumption may be more likely to fail |
| 616 | with SWP emulation enabled, leading to deadlock of the user |
| 617 | application. |
| 618 | |
| 619 | NOTE: when accessing uncached shared regions, LDXR/STXR rely |
| 620 | on an external transaction monitoring block called a global |
| 621 | monitor to maintain update atomicity. If your system does not |
| 622 | implement a global monitor, this option can cause programs that |
| 623 | perform SWP operations to uncached memory to deadlock. |
| 624 | |
| 625 | If unsure, say Y |
| 626 | |
| 627 | config CP15_BARRIER_EMULATION |
| 628 | bool "Emulate CP15 Barrier instructions" |
| 629 | help |
| 630 | The CP15 barrier instructions - CP15ISB, CP15DSB, and |
| 631 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is |
| 632 | strongly recommended to use the ISB, DSB, and DMB |
| 633 | instructions instead. |
| 634 | |
| 635 | Say Y here to enable software emulation of these |
| 636 | instructions for AArch32 userspace code. When this option is |
| 637 | enabled, CP15 barrier usage is traced which can help |
| 638 | identify software that needs updating. |
| 639 | |
| 640 | If unsure, say Y |
| 641 | |
Suzuki K. Poulose | 2d888f4 | 2015-01-21 12:43:11 +0000 | [diff] [blame] | 642 | config SETEND_EMULATION |
| 643 | bool "Emulate SETEND instruction" |
| 644 | help |
| 645 | The SETEND instruction alters the data-endianness of the |
| 646 | AArch32 EL0, and is deprecated in ARMv8. |
| 647 | |
| 648 | Say Y here to enable software emulation of the instruction |
| 649 | for AArch32 userspace code. |
| 650 | |
| 651 | Note: All the cpus on the system must have mixed endian support at EL0 |
| 652 | for this feature to be enabled. If a new CPU - which doesn't support mixed |
| 653 | endian - is hotplugged in after this feature has been enabled, there could |
| 654 | be unexpected results in the applications. |
| 655 | |
| 656 | If unsure, say Y |
Will Deacon | 1b907f4 | 2014-11-20 16:51:10 +0000 | [diff] [blame] | 657 | endif |
| 658 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 659 | endmenu |
| 660 | |
| 661 | menu "Boot options" |
| 662 | |
| 663 | config CMDLINE |
| 664 | string "Default kernel command string" |
| 665 | default "" |
| 666 | help |
| 667 | Provide a set of default command-line options at build time by |
| 668 | entering them here. As a minimum, you should specify the the |
| 669 | root device (e.g. root=/dev/nfs). |
| 670 | |
| 671 | config CMDLINE_FORCE |
| 672 | bool "Always use the default kernel command string" |
| 673 | help |
| 674 | Always use the default kernel command string, even if the boot |
| 675 | loader passes other arguments to the kernel. |
| 676 | This is useful if you cannot or don't want to change the |
| 677 | command-line options your boot loader passes to the kernel. |
| 678 | |
Ard Biesheuvel | f4f75ad5 | 2014-07-02 14:54:43 +0200 | [diff] [blame] | 679 | config EFI_STUB |
| 680 | bool |
| 681 | |
Mark Salter | f84d027 | 2014-04-15 21:59:30 -0400 | [diff] [blame] | 682 | config EFI |
| 683 | bool "UEFI runtime support" |
| 684 | depends on OF && !CPU_BIG_ENDIAN |
| 685 | select LIBFDT |
| 686 | select UCS2_STRING |
| 687 | select EFI_PARAMS_FROM_FDT |
Ard Biesheuvel | e15dd49 | 2014-07-04 19:41:53 +0200 | [diff] [blame] | 688 | select EFI_RUNTIME_WRAPPERS |
Ard Biesheuvel | f4f75ad5 | 2014-07-02 14:54:43 +0200 | [diff] [blame] | 689 | select EFI_STUB |
| 690 | select EFI_ARMSTUB |
Mark Salter | f84d027 | 2014-04-15 21:59:30 -0400 | [diff] [blame] | 691 | default y |
| 692 | help |
| 693 | This option provides support for runtime services provided |
| 694 | by UEFI firmware (such as non-volatile variables, realtime |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 695 | clock, and platform reset). A UEFI stub is also provided to |
| 696 | allow the kernel to be booted as an EFI application. This |
| 697 | is only useful on systems that have UEFI firmware. |
Mark Salter | f84d027 | 2014-04-15 21:59:30 -0400 | [diff] [blame] | 698 | |
Yi Li | d1ae8c0 | 2014-10-04 23:46:43 +0800 | [diff] [blame] | 699 | config DMI |
| 700 | bool "Enable support for SMBIOS (DMI) tables" |
| 701 | depends on EFI |
| 702 | default y |
| 703 | help |
| 704 | This enables SMBIOS/DMI feature for systems. |
| 705 | |
| 706 | This option is only useful on systems that have UEFI firmware. |
| 707 | However, even with this option, the resultant kernel should |
| 708 | continue to boot on existing non-UEFI platforms. |
| 709 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 710 | endmenu |
| 711 | |
| 712 | menu "Userspace binary formats" |
| 713 | |
| 714 | source "fs/Kconfig.binfmt" |
| 715 | |
| 716 | config COMPAT |
| 717 | bool "Kernel support for 32-bit EL0" |
Alexander Graf | a8fcd8b | 2015-03-16 16:32:23 +0000 | [diff] [blame] | 718 | depends on !ARM64_64K_PAGES || EXPERT |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 719 | select COMPAT_BINFMT_ELF |
Catalin Marinas | af1839e | 2012-10-08 16:28:08 -0700 | [diff] [blame] | 720 | select HAVE_UID16 |
Al Viro | 84b9e9b | 2012-12-25 16:29:11 -0500 | [diff] [blame] | 721 | select OLD_SIGSUSPEND3 |
Al Viro | 5168203 | 2012-12-25 19:31:29 -0500 | [diff] [blame] | 722 | select COMPAT_OLD_SIGACTION |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 723 | help |
| 724 | This option enables support for a 32-bit EL0 running under a 64-bit |
| 725 | kernel at EL1. AArch32-specific components such as system calls, |
| 726 | the user helper functions, VFP support and the ptrace interface are |
| 727 | handled appropriately by the kernel. |
| 728 | |
Alexander Graf | a8fcd8b | 2015-03-16 16:32:23 +0000 | [diff] [blame] | 729 | If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you |
| 730 | will only be able to execute AArch32 binaries that were compiled with |
| 731 | 64k aligned segments. |
| 732 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 733 | If you want to execute 32-bit userspace applications, say Y. |
| 734 | |
| 735 | config SYSVIPC_COMPAT |
| 736 | def_bool y |
| 737 | depends on COMPAT && SYSVIPC |
| 738 | |
| 739 | endmenu |
| 740 | |
Lorenzo Pieralisi | 166936b | 2013-11-07 18:37:14 +0000 | [diff] [blame] | 741 | menu "Power management options" |
| 742 | |
| 743 | source "kernel/power/Kconfig" |
| 744 | |
| 745 | config ARCH_SUSPEND_POSSIBLE |
| 746 | def_bool y |
| 747 | |
Lorenzo Pieralisi | 166936b | 2013-11-07 18:37:14 +0000 | [diff] [blame] | 748 | endmenu |
| 749 | |
Lorenzo Pieralisi | 1307220 | 2013-07-17 14:54:21 +0100 | [diff] [blame] | 750 | menu "CPU Power Management" |
| 751 | |
| 752 | source "drivers/cpuidle/Kconfig" |
| 753 | |
Rob Herring | 52e7e81 | 2014-02-24 11:27:57 +0900 | [diff] [blame] | 754 | source "drivers/cpufreq/Kconfig" |
| 755 | |
| 756 | endmenu |
| 757 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 758 | source "net/Kconfig" |
| 759 | |
| 760 | source "drivers/Kconfig" |
| 761 | |
Mark Salter | f84d027 | 2014-04-15 21:59:30 -0400 | [diff] [blame] | 762 | source "drivers/firmware/Kconfig" |
| 763 | |
Graeme Gregory | b6a0217 | 2015-03-24 14:02:53 +0000 | [diff] [blame] | 764 | source "drivers/acpi/Kconfig" |
| 765 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 766 | source "fs/Kconfig" |
| 767 | |
Marc Zyngier | c3eb5b1 | 2013-07-04 13:34:32 +0100 | [diff] [blame] | 768 | source "arch/arm64/kvm/Kconfig" |
| 769 | |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 770 | source "arch/arm64/Kconfig.debug" |
| 771 | |
| 772 | source "security/Kconfig" |
| 773 | |
| 774 | source "crypto/Kconfig" |
Ard Biesheuvel | 2c98833 | 2014-03-06 16:23:33 +0800 | [diff] [blame] | 775 | if CRYPTO |
| 776 | source "arch/arm64/crypto/Kconfig" |
| 777 | endif |
Catalin Marinas | 8c2c3df | 2012-04-20 14:45:54 +0100 | [diff] [blame] | 778 | |
| 779 | source "lib/Kconfig" |