blob: 183fb8e07815a3c5e93aca5e62afa67f87fd5448 [file] [log] [blame]
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070017#include <linux/nl80211.h>
Sujith394cf0a2009-02-09 13:26:54 +053018#include "ath9k.h"
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070019
20#define ATH_PCI_VERSION "0.1"
21
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070022static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
Jouni Malinenb3bd89c2009-02-24 13:42:01 +020029static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -080033/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
Luis R. Rodriguezce111ba2008-12-23 15:58:39 -0800104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
Sujithff37e332008-11-24 12:07:55 +0530106{
Luis R. Rodriguez030bb492008-12-23 15:58:37 -0800107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
Luis R. Rodriguez96742252008-12-23 15:58:38 -0800118 else
Luis R. Rodriguez030bb492008-12-23 15:58:37 -0800119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
Luis R. Rodriguez030bb492008-12-23 15:58:37 -0800121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
Luis R. Rodriguez96742252008-12-23 15:58:38 -0800133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
Luis R. Rodriguez030bb492008-12-23 15:58:37 -0800135 break;
136 default:
Luis R. Rodriguezce111ba2008-12-23 15:58:39 -0800137 BUG_ON(1);
Luis R. Rodriguez030bb492008-12-23 15:58:37 -0800138 break;
139 }
Sujithff37e332008-11-24 12:07:55 +0530140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
Sujithcbe61d82009-02-09 13:27:12 +0530144 struct ath_hw *ah = sc->sc_ah;
Sujithff37e332008-11-24 12:07:55 +0530145 u32 txpow;
146
Sujith17d79042009-02-09 13:27:03 +0530147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
Sujithff37e332008-11-24 12:07:55 +0530149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
Sujith17d79042009-02-09 13:27:03 +0530151 sc->curtxpow = txpow;
Sujithff37e332008-11-24 12:07:55 +0530152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
Sujithf46730d2009-01-27 13:51:03 +0530222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
Sujithff37e332008-11-24 12:07:55 +0530227 sband->n_bitrates++;
Sujithf46730d2009-01-27 13:51:03 +0530228
Sujith04bd4632008-11-28 22:18:05 +0530229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
Sujithff37e332008-11-24 12:07:55 +0530231 }
232}
233
Sujithff37e332008-11-24 12:07:55 +0530234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
Jouni Malinen0e2dedf2009-03-03 19:23:32 +0200239int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
Sujithff37e332008-11-24 12:07:55 +0530241{
Sujithcbe61d82009-02-09 13:27:12 +0530242 struct ath_hw *ah = sc->sc_ah;
Sujithff37e332008-11-24 12:07:55 +0530243 bool fastcc = true, stopped;
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -0800244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
Sujithff37e332008-11-24 12:07:55 +0530246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +0530250 ath9k_ps_wakeup(sc);
251
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
Sujith043a0402009-01-16 21:38:47 +0530262 ath_drain_all_txq(sc, false);
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800263 stopped = ath_stoprecv(sc);
Sujithff37e332008-11-24 12:07:55 +0530264
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
Sujithff37e332008-11-24 12:07:55 +0530268
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
Sujithff37e332008-11-24 12:07:55 +0530271
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
Sujith2660b812009-02-09 13:27:26 +0530274 sc->sc_ah->curchan->channel,
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800275 channel->center_freq, sc->tx_chan_width);
Sujith99405f92008-11-24 12:08:35 +0530276
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800277 spin_lock_bh(&sc->sc_resetlock);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -0800278
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
Sujithff37e332008-11-24 12:07:55 +0530285 spin_unlock_bh(&sc->sc_resetlock);
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800286 return r;
Sujithff37e332008-11-24 12:07:55 +0530287 }
Luis R. Rodriguezc0d7c7a2008-12-23 15:58:50 -0800288 spin_unlock_bh(&sc->sc_resetlock);
289
290 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
291 sc->sc_flags &= ~SC_OP_FULL_RESET;
292
293 if (ath_startrecv(sc) != 0) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to restart recv logic\n");
296 return -EIO;
297 }
298
299 ath_cache_conf_rate(sc, &hw->conf);
300 ath_update_txpow(sc);
Sujith17d79042009-02-09 13:27:03 +0530301 ath9k_hw_set_interrupts(ah, sc->imask);
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +0530302 ath9k_ps_restore(sc);
Sujithff37e332008-11-24 12:07:55 +0530303 return 0;
304}
305
306/*
307 * This routine performs the periodic noise floor calibration function
308 * that is used to adjust and optimize the chip performance. This
309 * takes environmental changes (location, temperature) into account.
310 * When the task is complete, it reschedules itself depending on the
311 * appropriate interval that was calculated.
312 */
313static void ath_ani_calibrate(unsigned long data)
314{
Sujith20977d32009-02-20 15:13:28 +0530315 struct ath_softc *sc = (struct ath_softc *)data;
316 struct ath_hw *ah = sc->sc_ah;
Sujithff37e332008-11-24 12:07:55 +0530317 bool longcal = false;
318 bool shortcal = false;
319 bool aniflag = false;
320 unsigned int timestamp = jiffies_to_msecs(jiffies);
Sujith20977d32009-02-20 15:13:28 +0530321 u32 cal_interval, short_cal_interval;
Sujithff37e332008-11-24 12:07:55 +0530322
Sujith20977d32009-02-20 15:13:28 +0530323 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
324 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
Sujithff37e332008-11-24 12:07:55 +0530325
326 /*
327 * don't calibrate when we're scanning.
328 * we are most likely not on our home channel.
329 */
Sujith0c98de62009-03-03 10:16:45 +0530330 if (sc->sc_flags & SC_OP_SCANNING)
Sujith20977d32009-02-20 15:13:28 +0530331 goto set_timer;
Sujithff37e332008-11-24 12:07:55 +0530332
333 /* Long calibration runs independently of short calibration. */
Sujith17d79042009-02-09 13:27:03 +0530334 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
Sujithff37e332008-11-24 12:07:55 +0530335 longcal = true;
Sujith04bd4632008-11-28 22:18:05 +0530336 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
Sujith17d79042009-02-09 13:27:03 +0530337 sc->ani.longcal_timer = timestamp;
Sujithff37e332008-11-24 12:07:55 +0530338 }
339
Sujith17d79042009-02-09 13:27:03 +0530340 /* Short calibration applies only while caldone is false */
341 if (!sc->ani.caldone) {
Sujith20977d32009-02-20 15:13:28 +0530342 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
Sujithff37e332008-11-24 12:07:55 +0530343 shortcal = true;
Sujith04bd4632008-11-28 22:18:05 +0530344 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
Sujith17d79042009-02-09 13:27:03 +0530345 sc->ani.shortcal_timer = timestamp;
346 sc->ani.resetcal_timer = timestamp;
Sujithff37e332008-11-24 12:07:55 +0530347 }
348 } else {
Sujith17d79042009-02-09 13:27:03 +0530349 if ((timestamp - sc->ani.resetcal_timer) >=
Sujithff37e332008-11-24 12:07:55 +0530350 ATH_RESTART_CALINTERVAL) {
Sujith17d79042009-02-09 13:27:03 +0530351 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 if (sc->ani.caldone)
353 sc->ani.resetcal_timer = timestamp;
Sujithff37e332008-11-24 12:07:55 +0530354 }
355 }
356
357 /* Verify whether we must check ANI */
Sujith20977d32009-02-20 15:13:28 +0530358 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
Sujithff37e332008-11-24 12:07:55 +0530359 aniflag = true;
Sujith17d79042009-02-09 13:27:03 +0530360 sc->ani.checkani_timer = timestamp;
Sujithff37e332008-11-24 12:07:55 +0530361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
Sujith20977d32009-02-20 15:13:28 +0530367 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
Sujithff37e332008-11-24 12:07:55 +0530368
369 /* Perform calibration if necessary */
370 if (longcal || shortcal) {
371 bool iscaldone = false;
372
Sujith2660b812009-02-09 13:27:26 +0530373 if (ath9k_hw_calibrate(ah, ah->curchan,
Sujith17d79042009-02-09 13:27:03 +0530374 sc->rx_chainmask, longcal,
Sujithff37e332008-11-24 12:07:55 +0530375 &iscaldone)) {
376 if (longcal)
Sujith17d79042009-02-09 13:27:03 +0530377 sc->ani.noise_floor =
Sujithff37e332008-11-24 12:07:55 +0530378 ath9k_hw_getchan_noise(ah,
Sujith2660b812009-02-09 13:27:26 +0530379 ah->curchan);
Sujithff37e332008-11-24 12:07:55 +0530380
381 DPRINTF(sc, ATH_DBG_ANI,
Sujith04bd4632008-11-28 22:18:05 +0530382 "calibrate chan %u/%x nf: %d\n",
Sujith2660b812009-02-09 13:27:26 +0530383 ah->curchan->channel,
384 ah->curchan->channelFlags,
Sujith17d79042009-02-09 13:27:03 +0530385 sc->ani.noise_floor);
Sujithff37e332008-11-24 12:07:55 +0530386 } else {
387 DPRINTF(sc, ATH_DBG_ANY,
Sujith04bd4632008-11-28 22:18:05 +0530388 "calibrate chan %u/%x failed\n",
Sujith2660b812009-02-09 13:27:26 +0530389 ah->curchan->channel,
390 ah->curchan->channelFlags);
Sujithff37e332008-11-24 12:07:55 +0530391 }
Sujith17d79042009-02-09 13:27:03 +0530392 sc->ani.caldone = iscaldone;
Sujithff37e332008-11-24 12:07:55 +0530393 }
394 }
395
Sujith20977d32009-02-20 15:13:28 +0530396set_timer:
Sujithff37e332008-11-24 12:07:55 +0530397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
Sujithaac92072008-12-02 18:37:54 +0530402 cal_interval = ATH_LONG_CALINTERVAL;
Sujith2660b812009-02-09 13:27:26 +0530403 if (sc->sc_ah->config.enable_ani)
Sujithaac92072008-12-02 18:37:54 +0530404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
Sujith17d79042009-02-09 13:27:03 +0530405 if (!sc->ani.caldone)
Sujith20977d32009-02-20 15:13:28 +0530406 cal_interval = min(cal_interval, (u32)short_cal_interval);
Sujithff37e332008-11-24 12:07:55 +0530407
Sujith17d79042009-02-09 13:27:03 +0530408 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
Sujithff37e332008-11-24 12:07:55 +0530409}
410
411/*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
Vasanthakumar Thiagarajanc97c92d2009-01-02 15:35:46 +0530414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
Sujithff37e332008-11-24 12:07:55 +0530416 */
Jouni Malinen0e2dedf2009-03-03 19:23:32 +0200417void ath_update_chainmask(struct ath_softc *sc, int is_ht)
Sujithff37e332008-11-24 12:07:55 +0530418{
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
Vasanthakumar Thiagarajanc97c92d2009-01-02 15:35:46 +0530420 if (is_ht ||
Sujith2660b812009-02-09 13:27:26 +0530421 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
422 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
423 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
Sujithff37e332008-11-24 12:07:55 +0530424 } else {
Sujith17d79042009-02-09 13:27:03 +0530425 sc->tx_chainmask = 1;
426 sc->rx_chainmask = 1;
Sujithff37e332008-11-24 12:07:55 +0530427 }
428
Sujith04bd4632008-11-28 22:18:05 +0530429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
Sujith17d79042009-02-09 13:27:03 +0530430 sc->tx_chainmask, sc->rx_chainmask);
Sujithff37e332008-11-24 12:07:55 +0530431}
432
433static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434{
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445}
446
447static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448{
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453}
454
455static void ath9k_tasklet(unsigned long data)
456{
457 struct ath_softc *sc = (struct ath_softc *)data;
Sujith17d79042009-02-09 13:27:03 +0530458 u32 status = sc->intrstatus;
Sujithff37e332008-11-24 12:07:55 +0530459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
Sujithb77f4832008-12-07 21:44:03 +0530468 spin_lock_bh(&sc->rx.rxflushlock);
Sujithff37e332008-11-24 12:07:55 +0530469 ath_rx_tasklet(sc, 0);
Sujithb77f4832008-12-07 21:44:03 +0530470 spin_unlock_bh(&sc->rx.rxflushlock);
Sujithff37e332008-11-24 12:07:55 +0530471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
Sujith17d79042009-02-09 13:27:03 +0530478 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
Sujithff37e332008-11-24 12:07:55 +0530479}
480
Gabor Juhos6baff7f2009-01-14 20:17:06 +0100481irqreturn_t ath_isr(int irq, void *dev)
Sujithff37e332008-11-24 12:07:55 +0530482{
483 struct ath_softc *sc = dev;
Sujithcbe61d82009-02-09 13:27:12 +0530484 struct ath_hw *ah = sc->sc_ah;
Sujithff37e332008-11-24 12:07:55 +0530485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
Sujith17d79042009-02-09 13:27:03 +0530509 status &= sc->imask; /* discard unasked-for bits */
Sujithff37e332008-11-24 12:07:55 +0530510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
Sujith17d79042009-02-09 13:27:03 +0530518 sc->intrstatus = status;
Vivek Natarajan541d8dd2009-03-02 20:25:14 +0530519 ath9k_ps_wakeup(sc);
Sujithff37e332008-11-24 12:07:55 +0530520
521 if (status & ATH9K_INT_FATAL) {
522 /* need a chip reset */
523 sched = true;
524 } else if (status & ATH9K_INT_RXORN) {
525 /* need a chip reset */
526 sched = true;
527 } else {
528 if (status & ATH9K_INT_SWBA) {
529 /* schedule a tasklet for beacon handling */
530 tasklet_schedule(&sc->bcon_tasklet);
531 }
532 if (status & ATH9K_INT_RXEOL) {
533 /*
534 * NB: the hardware should re-read the link when
535 * RXE bit is written, but it doesn't work
536 * at least on older hardware revs.
537 */
538 sched = true;
539 }
540
541 if (status & ATH9K_INT_TXURN)
542 /* bump tx trigger level */
543 ath9k_hw_updatetxtriglevel(ah, true);
544 /* XXX: optimize this */
545 if (status & ATH9K_INT_RX)
546 sched = true;
547 if (status & ATH9K_INT_TX)
548 sched = true;
549 if (status & ATH9K_INT_BMISS)
550 sched = true;
551 /* carrier sense timeout */
552 if (status & ATH9K_INT_CST)
553 sched = true;
554 if (status & ATH9K_INT_MIB) {
555 /*
556 * Disable interrupts until we service the MIB
557 * interrupt; otherwise it will continue to
558 * fire.
559 */
560 ath9k_hw_set_interrupts(ah, 0);
561 /*
562 * Let the hal handle the event. We assume
563 * it will clear whatever condition caused
564 * the interrupt.
565 */
Sujith17d79042009-02-09 13:27:03 +0530566 ath9k_hw_procmibevent(ah, &sc->nodestats);
567 ath9k_hw_set_interrupts(ah, sc->imask);
Sujithff37e332008-11-24 12:07:55 +0530568 }
569 if (status & ATH9K_INT_TIM_TIMER) {
Sujith2660b812009-02-09 13:27:26 +0530570 if (!(ah->caps.hw_caps &
Sujithff37e332008-11-24 12:07:55 +0530571 ATH9K_HW_CAP_AUTOSLEEP)) {
572 /* Clear RxAbort bit so that we can
573 * receive frames */
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +0530574 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
Sujithff37e332008-11-24 12:07:55 +0530575 ath9k_hw_setrxabort(ah, 0);
576 sched = true;
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +0530577 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
Sujithff37e332008-11-24 12:07:55 +0530578 }
579 }
Sujith4af9cf42009-02-12 10:06:47 +0530580 if (status & ATH9K_INT_TSFOOR) {
581 /* FIXME: Handle this interrupt for power save */
582 sched = true;
583 }
Sujithff37e332008-11-24 12:07:55 +0530584 }
Vivek Natarajan541d8dd2009-03-02 20:25:14 +0530585 ath9k_ps_restore(sc);
Sujithff37e332008-11-24 12:07:55 +0530586 } while (0);
587
Sujith817e11d2008-12-07 21:42:44 +0530588 ath_debug_stat_interrupt(sc, status);
589
Sujithff37e332008-11-24 12:07:55 +0530590 if (sched) {
591 /* turn off every interrupt except SWBA */
Sujith17d79042009-02-09 13:27:03 +0530592 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
Sujithff37e332008-11-24 12:07:55 +0530593 tasklet_schedule(&sc->intr_tq);
594 }
595
596 return IRQ_HANDLED;
597}
598
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700599static u32 ath_get_extchanmode(struct ath_softc *sc,
Sujith99405f92008-11-24 12:08:35 +0530600 struct ieee80211_channel *chan,
Sujith094d05d2008-12-12 11:57:43 +0530601 enum nl80211_channel_type channel_type)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700602{
603 u32 chanmode = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700604
605 switch (chan->band) {
606 case IEEE80211_BAND_2GHZ:
Sujith094d05d2008-12-12 11:57:43 +0530607 switch(channel_type) {
608 case NL80211_CHAN_NO_HT:
609 case NL80211_CHAN_HT20:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700610 chanmode = CHANNEL_G_HT20;
Sujith094d05d2008-12-12 11:57:43 +0530611 break;
612 case NL80211_CHAN_HT40PLUS:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700613 chanmode = CHANNEL_G_HT40PLUS;
Sujith094d05d2008-12-12 11:57:43 +0530614 break;
615 case NL80211_CHAN_HT40MINUS:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700616 chanmode = CHANNEL_G_HT40MINUS;
Sujith094d05d2008-12-12 11:57:43 +0530617 break;
618 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700619 break;
620 case IEEE80211_BAND_5GHZ:
Sujith094d05d2008-12-12 11:57:43 +0530621 switch(channel_type) {
622 case NL80211_CHAN_NO_HT:
623 case NL80211_CHAN_HT20:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700624 chanmode = CHANNEL_A_HT20;
Sujith094d05d2008-12-12 11:57:43 +0530625 break;
626 case NL80211_CHAN_HT40PLUS:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700627 chanmode = CHANNEL_A_HT40PLUS;
Sujith094d05d2008-12-12 11:57:43 +0530628 break;
629 case NL80211_CHAN_HT40MINUS:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700630 chanmode = CHANNEL_A_HT40MINUS;
Sujith094d05d2008-12-12 11:57:43 +0530631 break;
632 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700633 break;
634 default:
635 break;
636 }
637
638 return chanmode;
639}
640
Jouni Malinen6ace2892008-12-17 13:32:17 +0200641static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
Jouni Malinen3f53dd62009-02-26 11:18:46 +0200642 struct ath9k_keyval *hk, const u8 *addr,
643 bool authenticator)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700644{
Jouni Malinen6ace2892008-12-17 13:32:17 +0200645 const u8 *key_rxmic;
646 const u8 *key_txmic;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700647
Jouni Malinen6ace2892008-12-17 13:32:17 +0200648 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
649 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700650
651 if (addr == NULL) {
Jouni Malinend216aaa2009-03-03 13:11:53 +0200652 /*
653 * Group key installation - only two key cache entries are used
654 * regardless of splitmic capability since group key is only
655 * used either for TX or RX.
656 */
Jouni Malinen3f53dd62009-02-26 11:18:46 +0200657 if (authenticator) {
658 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
659 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
660 } else {
661 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
662 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
663 }
Jouni Malinend216aaa2009-03-03 13:11:53 +0200664 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700665 }
Sujith17d79042009-02-09 13:27:03 +0530666 if (!sc->splitmic) {
Jouni Malinend216aaa2009-03-03 13:11:53 +0200667 /* TX and RX keys share the same key cache entry. */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700668 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
669 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
Jouni Malinend216aaa2009-03-03 13:11:53 +0200670 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700671 }
Jouni Malinend216aaa2009-03-03 13:11:53 +0200672
673 /* Separate key cache entries for TX and RX */
674
675 /* TX key goes at first index, RX key at +32. */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
Jouni Malinend216aaa2009-03-03 13:11:53 +0200677 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
678 /* TX MIC entry failed. No need to proceed further */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700679 DPRINTF(sc, ATH_DBG_KEYCACHE,
Sujith04bd4632008-11-28 22:18:05 +0530680 "Setting TX MIC Key Failed\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700681 return 0;
682 }
683
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 /* XXX delete tx key on failure? */
Jouni Malinend216aaa2009-03-03 13:11:53 +0200686 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
Jouni Malinen6ace2892008-12-17 13:32:17 +0200687}
688
689static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
690{
691 int i;
692
Sujith17d79042009-02-09 13:27:03 +0530693 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
694 if (test_bit(i, sc->keymap) ||
695 test_bit(i + 64, sc->keymap))
Jouni Malinen6ace2892008-12-17 13:32:17 +0200696 continue; /* At least one part of TKIP key allocated */
Sujith17d79042009-02-09 13:27:03 +0530697 if (sc->splitmic &&
698 (test_bit(i + 32, sc->keymap) ||
699 test_bit(i + 64 + 32, sc->keymap)))
Jouni Malinen6ace2892008-12-17 13:32:17 +0200700 continue; /* At least one part of TKIP key allocated */
701
702 /* Found a free slot for a TKIP key */
703 return i;
704 }
705 return -1;
706}
707
708static int ath_reserve_key_cache_slot(struct ath_softc *sc)
709{
710 int i;
711
712 /* First, try to find slots that would not be available for TKIP. */
Sujith17d79042009-02-09 13:27:03 +0530713 if (sc->splitmic) {
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
715 if (!test_bit(i, sc->keymap) &&
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64, sc->keymap) ||
718 test_bit(i + 64 + 32, sc->keymap)))
Jouni Malinen6ace2892008-12-17 13:32:17 +0200719 return i;
Sujith17d79042009-02-09 13:27:03 +0530720 if (!test_bit(i + 32, sc->keymap) &&
721 (test_bit(i, sc->keymap) ||
722 test_bit(i + 64, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
Jouni Malinen6ace2892008-12-17 13:32:17 +0200724 return i + 32;
Sujith17d79042009-02-09 13:27:03 +0530725 if (!test_bit(i + 64, sc->keymap) &&
726 (test_bit(i , sc->keymap) ||
727 test_bit(i + 32, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
Jouni Malinenea612132008-12-18 14:31:10 +0200729 return i + 64;
Sujith17d79042009-02-09 13:27:03 +0530730 if (!test_bit(i + 64 + 32, sc->keymap) &&
731 (test_bit(i, sc->keymap) ||
732 test_bit(i + 32, sc->keymap) ||
733 test_bit(i + 64, sc->keymap)))
Jouni Malinenea612132008-12-18 14:31:10 +0200734 return i + 64 + 32;
Jouni Malinen6ace2892008-12-17 13:32:17 +0200735 }
736 } else {
Sujith17d79042009-02-09 13:27:03 +0530737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 test_bit(i + 64, sc->keymap))
Jouni Malinen6ace2892008-12-17 13:32:17 +0200740 return i;
Sujith17d79042009-02-09 13:27:03 +0530741 if (test_bit(i, sc->keymap) &&
742 !test_bit(i + 64, sc->keymap))
Jouni Malinen6ace2892008-12-17 13:32:17 +0200743 return i + 64;
744 }
745 }
746
747 /* No partially used TKIP slots, pick any available slot */
Sujith17d79042009-02-09 13:27:03 +0530748 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
Jouni Malinenbe2864c2008-12-18 14:33:00 +0200749 /* Do not allow slots that could be needed for TKIP group keys
750 * to be used. This limitation could be removed if we know that
751 * TKIP will not be used. */
752 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 continue;
Sujith17d79042009-02-09 13:27:03 +0530754 if (sc->splitmic) {
Jouni Malinenbe2864c2008-12-18 14:33:00 +0200755 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
756 continue;
757 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
758 continue;
759 }
760
Sujith17d79042009-02-09 13:27:03 +0530761 if (!test_bit(i, sc->keymap))
Jouni Malinen6ace2892008-12-17 13:32:17 +0200762 return i; /* Found a free slot for a key */
763 }
764
765 /* No free slot found */
766 return -1;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700767}
768
769static int ath_key_config(struct ath_softc *sc,
Jouni Malinen3f53dd62009-02-26 11:18:46 +0200770 struct ieee80211_vif *vif,
Johannes Bergdc822b52008-12-29 12:55:09 +0100771 struct ieee80211_sta *sta,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700772 struct ieee80211_key_conf *key)
773{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700774 struct ath9k_keyval hk;
775 const u8 *mac = NULL;
776 int ret = 0;
Jouni Malinen6ace2892008-12-17 13:32:17 +0200777 int idx;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700778
779 memset(&hk, 0, sizeof(hk));
780
781 switch (key->alg) {
782 case ALG_WEP:
783 hk.kv_type = ATH9K_CIPHER_WEP;
784 break;
785 case ALG_TKIP:
786 hk.kv_type = ATH9K_CIPHER_TKIP;
787 break;
788 case ALG_CCMP:
789 hk.kv_type = ATH9K_CIPHER_AES_CCM;
790 break;
791 default:
Jouni Malinenca470b22009-01-08 13:32:12 +0200792 return -EOPNOTSUPP;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700793 }
794
Jouni Malinen6ace2892008-12-17 13:32:17 +0200795 hk.kv_len = key->keylen;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700796 memcpy(hk.kv_val, key->key, key->keylen);
797
Jouni Malinen6ace2892008-12-17 13:32:17 +0200798 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
799 /* For now, use the default keys for broadcast keys. This may
800 * need to change with virtual interfaces. */
801 idx = key->keyidx;
802 } else if (key->keyidx) {
Johannes Bergdc822b52008-12-29 12:55:09 +0100803 if (WARN_ON(!sta))
804 return -EOPNOTSUPP;
805 mac = sta->addr;
806
Jouni Malinen6ace2892008-12-17 13:32:17 +0200807 if (vif->type != NL80211_IFTYPE_AP) {
808 /* Only keyidx 0 should be used with unicast key, but
809 * allow this for client mode for now. */
810 idx = key->keyidx;
811 } else
812 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700813 } else {
Johannes Bergdc822b52008-12-29 12:55:09 +0100814 if (WARN_ON(!sta))
815 return -EOPNOTSUPP;
816 mac = sta->addr;
817
Jouni Malinen6ace2892008-12-17 13:32:17 +0200818 if (key->alg == ALG_TKIP)
819 idx = ath_reserve_key_cache_slot_tkip(sc);
820 else
821 idx = ath_reserve_key_cache_slot(sc);
822 if (idx < 0)
Jouni Malinenca470b22009-01-08 13:32:12 +0200823 return -ENOSPC; /* no free key cache entries */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700824 }
825
826 if (key->alg == ALG_TKIP)
Jouni Malinen3f53dd62009-02-26 11:18:46 +0200827 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
828 vif->type == NL80211_IFTYPE_AP);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700829 else
Jouni Malinend216aaa2009-03-03 13:11:53 +0200830 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700831
832 if (!ret)
833 return -EIO;
834
Sujith17d79042009-02-09 13:27:03 +0530835 set_bit(idx, sc->keymap);
Jouni Malinen6ace2892008-12-17 13:32:17 +0200836 if (key->alg == ALG_TKIP) {
Sujith17d79042009-02-09 13:27:03 +0530837 set_bit(idx + 64, sc->keymap);
838 if (sc->splitmic) {
839 set_bit(idx + 32, sc->keymap);
840 set_bit(idx + 64 + 32, sc->keymap);
Jouni Malinen6ace2892008-12-17 13:32:17 +0200841 }
842 }
843
844 return idx;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700845}
846
847static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
848{
Jouni Malinen6ace2892008-12-17 13:32:17 +0200849 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
850 if (key->hw_key_idx < IEEE80211_WEP_NKID)
851 return;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700852
Sujith17d79042009-02-09 13:27:03 +0530853 clear_bit(key->hw_key_idx, sc->keymap);
Jouni Malinen6ace2892008-12-17 13:32:17 +0200854 if (key->alg != ALG_TKIP)
855 return;
856
Sujith17d79042009-02-09 13:27:03 +0530857 clear_bit(key->hw_key_idx + 64, sc->keymap);
858 if (sc->splitmic) {
859 clear_bit(key->hw_key_idx + 32, sc->keymap);
860 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
Jouni Malinen6ace2892008-12-17 13:32:17 +0200861 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700862}
863
Sujitheb2599c2009-01-23 11:20:44 +0530864static void setup_ht_cap(struct ath_softc *sc,
865 struct ieee80211_sta_ht_cap *ht_info)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700866{
Sujith60653672008-08-14 13:28:02 +0530867#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
868#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700869
Johannes Bergd9fe60d2008-10-09 12:13:49 +0200870 ht_info->ht_supported = true;
871 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
872 IEEE80211_HT_CAP_SM_PS |
873 IEEE80211_HT_CAP_SGI_40 |
874 IEEE80211_HT_CAP_DSSSCCK40;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700875
Sujith60653672008-08-14 13:28:02 +0530876 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
877 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
Sujitheb2599c2009-01-23 11:20:44 +0530878
Johannes Bergd9fe60d2008-10-09 12:13:49 +0200879 /* set up supported mcs set */
880 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
Sujitheb2599c2009-01-23 11:20:44 +0530881
Sujith17d79042009-02-09 13:27:03 +0530882 switch(sc->rx_chainmask) {
Sujitheb2599c2009-01-23 11:20:44 +0530883 case 1:
884 ht_info->mcs.rx_mask[0] = 0xff;
885 break;
Sujith3c457262009-01-27 10:55:31 +0530886 case 3:
Sujitheb2599c2009-01-23 11:20:44 +0530887 case 5:
888 case 7:
889 default:
890 ht_info->mcs.rx_mask[0] = 0xff;
891 ht_info->mcs.rx_mask[1] = 0xff;
892 break;
893 }
894
Johannes Bergd9fe60d2008-10-09 12:13:49 +0200895 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700896}
897
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530898static void ath9k_bss_assoc_info(struct ath_softc *sc,
Sujith5640b082008-10-29 10:16:06 +0530899 struct ieee80211_vif *vif,
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530900 struct ieee80211_bss_conf *bss_conf)
901{
Sujith17d79042009-02-09 13:27:03 +0530902 struct ath_vif *avp = (void *)vif->drv_priv;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530903
904 if (bss_conf->assoc) {
Sujith094d05d2008-12-12 11:57:43 +0530905 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
Sujith17d79042009-02-09 13:27:03 +0530906 bss_conf->aid, sc->curbssid);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530907
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530908 /* New association, store aid */
Colin McCabed97809d2008-12-01 13:38:55 -0800909 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
Sujith17d79042009-02-09 13:27:03 +0530910 sc->curaid = bss_conf->aid;
Sujithba52da52009-02-09 13:27:10 +0530911 ath9k_hw_write_associd(sc);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530912 }
913
914 /* Configure the beacon */
Jouni Malinen2c3db3d2009-03-03 19:23:26 +0200915 ath_beacon_config(sc, vif);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530916
917 /* Reset rssi stats */
Sujith17d79042009-02-09 13:27:03 +0530918 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530922
Luis R. Rodriguez6f255422008-10-03 15:45:27 -0700923 /* Start ANI */
Sujith17d79042009-02-09 13:27:03 +0530924 mod_timer(&sc->ani.timer,
Sujith20977d32009-02-20 15:13:28 +0530925 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530926 } else {
Sujith04bd4632008-11-28 22:18:05 +0530927 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
Sujith17d79042009-02-09 13:27:03 +0530928 sc->curaid = 0;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530929 }
930}
931
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530932/********************************/
933/* LED functions */
934/********************************/
935
Vasanthakumar Thiagarajanf2bffa72009-01-29 17:52:19 +0530936static void ath_led_blink_work(struct work_struct *work)
937{
938 struct ath_softc *sc = container_of(work, struct ath_softc,
939 ath_led_blink_work.work);
940
941 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
942 return;
943 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
944 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
945
946 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
947 (sc->sc_flags & SC_OP_LED_ON) ?
948 msecs_to_jiffies(sc->led_off_duration) :
949 msecs_to_jiffies(sc->led_on_duration));
950
951 sc->led_on_duration =
952 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
953 sc->led_off_duration =
954 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
955 sc->led_on_cnt = sc->led_off_cnt = 0;
956 if (sc->sc_flags & SC_OP_LED_ON)
957 sc->sc_flags &= ~SC_OP_LED_ON;
958 else
959 sc->sc_flags |= SC_OP_LED_ON;
960}
961
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530962static void ath_led_brightness(struct led_classdev *led_cdev,
963 enum led_brightness brightness)
964{
965 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
966 struct ath_softc *sc = led->sc;
967
968 switch (brightness) {
969 case LED_OFF:
970 if (led->led_type == ATH_LED_ASSOC ||
Vasanthakumar Thiagarajanf2bffa72009-01-29 17:52:19 +0530971 led->led_type == ATH_LED_RADIO) {
972 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
973 (led->led_type == ATH_LED_RADIO));
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530974 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
Vasanthakumar Thiagarajanf2bffa72009-01-29 17:52:19 +0530975 if (led->led_type == ATH_LED_RADIO)
976 sc->sc_flags &= ~SC_OP_LED_ON;
977 } else {
978 sc->led_off_cnt++;
979 }
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530980 break;
981 case LED_FULL:
Vasanthakumar Thiagarajanf2bffa72009-01-29 17:52:19 +0530982 if (led->led_type == ATH_LED_ASSOC) {
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530983 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
Vasanthakumar Thiagarajanf2bffa72009-01-29 17:52:19 +0530984 queue_delayed_work(sc->hw->workqueue,
985 &sc->ath_led_blink_work, 0);
986 } else if (led->led_type == ATH_LED_RADIO) {
987 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
988 sc->sc_flags |= SC_OP_LED_ON;
989 } else {
990 sc->led_on_cnt++;
991 }
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530992 break;
993 default:
994 break;
995 }
996}
997
998static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
999 char *trigger)
1000{
1001 int ret;
1002
1003 led->sc = sc;
1004 led->led_cdev.name = led->name;
1005 led->led_cdev.default_trigger = trigger;
1006 led->led_cdev.brightness_set = ath_led_brightness;
1007
1008 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1009 if (ret)
1010 DPRINTF(sc, ATH_DBG_FATAL,
1011 "Failed to register led:%s", led->name);
1012 else
1013 led->registered = 1;
1014 return ret;
1015}
1016
1017static void ath_unregister_led(struct ath_led *led)
1018{
1019 if (led->registered) {
1020 led_classdev_unregister(&led->led_cdev);
1021 led->registered = 0;
1022 }
1023}
1024
1025static void ath_deinit_leds(struct ath_softc *sc)
1026{
Vasanthakumar Thiagarajanf2bffa72009-01-29 17:52:19 +05301027 cancel_delayed_work_sync(&sc->ath_led_blink_work);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301028 ath_unregister_led(&sc->assoc_led);
1029 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030 ath_unregister_led(&sc->tx_led);
1031 ath_unregister_led(&sc->rx_led);
1032 ath_unregister_led(&sc->radio_led);
1033 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1034}
1035
1036static void ath_init_leds(struct ath_softc *sc)
1037{
1038 char *trigger;
1039 int ret;
1040
1041 /* Configure gpio 1 for output */
1042 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044 /* LED off, active low */
1045 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1046
Vasanthakumar Thiagarajanf2bffa72009-01-29 17:52:19 +05301047 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1048
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301049 trigger = ieee80211_get_radio_led_name(sc->hw);
1050 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
Danny Kukawka0818cb82009-01-31 15:52:09 +01001051 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301052 ret = ath_register_led(sc, &sc->radio_led, trigger);
1053 sc->radio_led.led_type = ATH_LED_RADIO;
1054 if (ret)
1055 goto fail;
1056
1057 trigger = ieee80211_get_assoc_led_name(sc->hw);
1058 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
Danny Kukawka0818cb82009-01-31 15:52:09 +01001059 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301060 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061 sc->assoc_led.led_type = ATH_LED_ASSOC;
1062 if (ret)
1063 goto fail;
1064
1065 trigger = ieee80211_get_tx_led_name(sc->hw);
1066 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
Danny Kukawka0818cb82009-01-31 15:52:09 +01001067 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301068 ret = ath_register_led(sc, &sc->tx_led, trigger);
1069 sc->tx_led.led_type = ATH_LED_TX;
1070 if (ret)
1071 goto fail;
1072
1073 trigger = ieee80211_get_rx_led_name(sc->hw);
1074 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
Danny Kukawka0818cb82009-01-31 15:52:09 +01001075 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301076 ret = ath_register_led(sc, &sc->rx_led, trigger);
1077 sc->rx_led.led_type = ATH_LED_RX;
1078 if (ret)
1079 goto fail;
1080
1081 return;
1082
1083fail:
1084 ath_deinit_leds(sc);
1085}
1086
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05301087#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith9c84b792008-10-29 10:17:13 +05301088
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301089/*******************/
1090/* Rfkill */
1091/*******************/
1092
1093static void ath_radio_enable(struct ath_softc *sc)
1094{
Sujithcbe61d82009-02-09 13:27:12 +05301095 struct ath_hw *ah = sc->sc_ah;
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001096 struct ieee80211_channel *channel = sc->hw->conf.channel;
1097 int r;
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301098
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05301099 ath9k_ps_wakeup(sc);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301100 spin_lock_bh(&sc->sc_resetlock);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001101
Sujith2660b812009-02-09 13:27:26 +05301102 r = ath9k_hw_reset(ah, ah->curchan, false);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001103
1104 if (r) {
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301105 DPRINTF(sc, ATH_DBG_FATAL,
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001106 "Unable to reset channel %u (%uMhz) ",
1107 "reset status %u\n",
1108 channel->center_freq, r);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301109 }
1110 spin_unlock_bh(&sc->sc_resetlock);
1111
1112 ath_update_txpow(sc);
1113 if (ath_startrecv(sc) != 0) {
1114 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301115 "Unable to restart recv logic\n");
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301116 return;
1117 }
1118
1119 if (sc->sc_flags & SC_OP_BEACONS)
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02001120 ath_beacon_config(sc, NULL); /* restart beacons */
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301121
1122 /* Re-Enable interrupts */
Sujith17d79042009-02-09 13:27:03 +05301123 ath9k_hw_set_interrupts(ah, sc->imask);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301124
1125 /* Enable LED */
1126 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1127 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1128 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1129
1130 ieee80211_wake_queues(sc->hw);
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05301131 ath9k_ps_restore(sc);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301132}
1133
1134static void ath_radio_disable(struct ath_softc *sc)
1135{
Sujithcbe61d82009-02-09 13:27:12 +05301136 struct ath_hw *ah = sc->sc_ah;
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001137 struct ieee80211_channel *channel = sc->hw->conf.channel;
1138 int r;
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301139
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05301140 ath9k_ps_wakeup(sc);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301141 ieee80211_stop_queues(sc->hw);
1142
1143 /* Disable LED */
1144 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1145 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1146
1147 /* Disable interrupts */
1148 ath9k_hw_set_interrupts(ah, 0);
1149
Sujith043a0402009-01-16 21:38:47 +05301150 ath_drain_all_txq(sc, false); /* clear pending tx frames */
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301151 ath_stoprecv(sc); /* turn off frame recv */
1152 ath_flushrecv(sc); /* flush recv queue */
1153
1154 spin_lock_bh(&sc->sc_resetlock);
Sujith2660b812009-02-09 13:27:26 +05301155 r = ath9k_hw_reset(ah, ah->curchan, false);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001156 if (r) {
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301157 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301158 "Unable to reset channel %u (%uMhz) "
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001159 "reset status %u\n",
1160 channel->center_freq, r);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301161 }
1162 spin_unlock_bh(&sc->sc_resetlock);
1163
1164 ath9k_hw_phy_disable(ah);
1165 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05301166 ath9k_ps_restore(sc);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301167}
1168
1169static bool ath_is_rfkill_set(struct ath_softc *sc)
1170{
Sujithcbe61d82009-02-09 13:27:12 +05301171 struct ath_hw *ah = sc->sc_ah;
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301172
Sujith2660b812009-02-09 13:27:26 +05301173 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1174 ah->rfkill_polarity;
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301175}
1176
1177/* h/w rfkill poll function */
1178static void ath_rfkill_poll(struct work_struct *work)
1179{
1180 struct ath_softc *sc = container_of(work, struct ath_softc,
1181 rf_kill.rfkill_poll.work);
1182 bool radio_on;
1183
1184 if (sc->sc_flags & SC_OP_INVALID)
1185 return;
1186
1187 radio_on = !ath_is_rfkill_set(sc);
1188
1189 /*
1190 * enable/disable radio only when there is a
1191 * state change in RF switch
1192 */
1193 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1194 enum rfkill_state state;
1195
1196 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1197 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1198 : RFKILL_STATE_HARD_BLOCKED;
1199 } else if (radio_on) {
1200 ath_radio_enable(sc);
1201 state = RFKILL_STATE_UNBLOCKED;
1202 } else {
1203 ath_radio_disable(sc);
1204 state = RFKILL_STATE_HARD_BLOCKED;
1205 }
1206
1207 if (state == RFKILL_STATE_HARD_BLOCKED)
1208 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1209 else
1210 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1211
1212 rfkill_force_state(sc->rf_kill.rfkill, state);
1213 }
1214
1215 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1216 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1217}
1218
1219/* s/w rfkill handler */
1220static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1221{
1222 struct ath_softc *sc = data;
1223
1224 switch (state) {
1225 case RFKILL_STATE_SOFT_BLOCKED:
1226 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1227 SC_OP_RFKILL_SW_BLOCKED)))
1228 ath_radio_disable(sc);
1229 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1230 return 0;
1231 case RFKILL_STATE_UNBLOCKED:
1232 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1233 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1234 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1235 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
Sujith04bd4632008-11-28 22:18:05 +05301236 "radio as it is disabled by h/w\n");
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301237 return -EPERM;
1238 }
1239 ath_radio_enable(sc);
1240 }
1241 return 0;
1242 default:
1243 return -EINVAL;
1244 }
1245}
1246
1247/* Init s/w rfkill */
1248static int ath_init_sw_rfkill(struct ath_softc *sc)
1249{
1250 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1251 RFKILL_TYPE_WLAN);
1252 if (!sc->rf_kill.rfkill) {
1253 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1254 return -ENOMEM;
1255 }
1256
1257 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
Danny Kukawka0818cb82009-01-31 15:52:09 +01001258 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301259 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1260 sc->rf_kill.rfkill->data = sc;
1261 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1262 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1263 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1264
1265 return 0;
1266}
1267
1268/* Deinitialize rfkill */
1269static void ath_deinit_rfkill(struct ath_softc *sc)
1270{
Sujith2660b812009-02-09 13:27:26 +05301271 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301272 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1273
1274 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275 rfkill_unregister(sc->rf_kill.rfkill);
1276 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277 sc->rf_kill.rfkill = NULL;
1278 }
1279}
Sujith9c84b792008-10-29 10:17:13 +05301280
1281static int ath_start_rfkill_poll(struct ath_softc *sc)
1282{
Sujith2660b812009-02-09 13:27:26 +05301283 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Sujith9c84b792008-10-29 10:17:13 +05301284 queue_delayed_work(sc->hw->workqueue,
1285 &sc->rf_kill.rfkill_poll, 0);
1286
1287 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288 if (rfkill_register(sc->rf_kill.rfkill)) {
1289 DPRINTF(sc, ATH_DBG_FATAL,
1290 "Unable to register rfkill\n");
1291 rfkill_free(sc->rf_kill.rfkill);
1292
1293 /* Deinitialize the device */
Gabor Juhos39c3c2f2009-01-14 20:17:05 +01001294 ath_cleanup(sc);
Sujith9c84b792008-10-29 10:17:13 +05301295 return -EIO;
1296 } else {
1297 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1298 }
1299 }
1300
1301 return 0;
1302}
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301303#endif /* CONFIG_RFKILL */
1304
Gabor Juhos6baff7f2009-01-14 20:17:06 +01001305void ath_cleanup(struct ath_softc *sc)
Gabor Juhos39c3c2f2009-01-14 20:17:05 +01001306{
1307 ath_detach(sc);
1308 free_irq(sc->irq, sc);
1309 ath_bus_cleanup(sc);
Jouni Malinenc52f33d2009-03-03 19:23:29 +02001310 kfree(sc->sec_wiphy);
Gabor Juhos39c3c2f2009-01-14 20:17:05 +01001311 ieee80211_free_hw(sc->hw);
1312}
1313
Gabor Juhos6baff7f2009-01-14 20:17:06 +01001314void ath_detach(struct ath_softc *sc)
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301315{
1316 struct ieee80211_hw *hw = sc->hw;
Sujith9c84b792008-10-29 10:17:13 +05301317 int i = 0;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301318
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05301319 ath9k_ps_wakeup(sc);
1320
Sujith04bd4632008-11-28 22:18:05 +05301321 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301322
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05301323#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301324 ath_deinit_rfkill(sc);
1325#endif
Vasanthakumar Thiagarajan3fcdfb42008-11-18 01:19:56 +05301326 ath_deinit_leds(sc);
Jouni Malinen0e2dedf2009-03-03 19:23:32 +02001327 cancel_work_sync(&sc->chan_work);
Vasanthakumar Thiagarajan3fcdfb42008-11-18 01:19:56 +05301328
Jouni Malinenc52f33d2009-03-03 19:23:29 +02001329 for (i = 0; i < sc->num_sec_wiphy; i++) {
1330 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1331 if (aphy == NULL)
1332 continue;
1333 sc->sec_wiphy[i] = NULL;
1334 ieee80211_unregister_hw(aphy->hw);
1335 ieee80211_free_hw(aphy->hw);
1336 }
Vasanthakumar Thiagarajan3fcdfb42008-11-18 01:19:56 +05301337 ieee80211_unregister_hw(hw);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301338 ath_rx_cleanup(sc);
1339 ath_tx_cleanup(sc);
1340
Sujith9c84b792008-10-29 10:17:13 +05301341 tasklet_kill(&sc->intr_tq);
1342 tasklet_kill(&sc->bcon_tasklet);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301343
Sujith9c84b792008-10-29 10:17:13 +05301344 if (!(sc->sc_flags & SC_OP_INVALID))
1345 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301346
Sujith9c84b792008-10-29 10:17:13 +05301347 /* cleanup tx queues */
1348 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1349 if (ATH_TXQ_SETUP(sc, i))
Sujithb77f4832008-12-07 21:44:03 +05301350 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
Sujith9c84b792008-10-29 10:17:13 +05301351
1352 ath9k_hw_detach(sc->sc_ah);
Sujith826d2682008-11-28 22:20:23 +05301353 ath9k_exit_debug(sc);
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05301354 ath9k_ps_restore(sc);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301355}
1356
Sujithff37e332008-11-24 12:07:55 +05301357static int ath_init(u16 devid, struct ath_softc *sc)
1358{
Sujithcbe61d82009-02-09 13:27:12 +05301359 struct ath_hw *ah = NULL;
Sujithff37e332008-11-24 12:07:55 +05301360 int status;
1361 int error = 0, i;
1362 int csz = 0;
1363
1364 /* XXX: hardware will not be ready until ath_open() being called */
1365 sc->sc_flags |= SC_OP_INVALID;
Sujith88b126a2008-11-28 22:19:02 +05301366
Sujith826d2682008-11-28 22:20:23 +05301367 if (ath9k_init_debug(sc) < 0)
1368 printk(KERN_ERR "Unable to create debugfs files\n");
Sujithff37e332008-11-24 12:07:55 +05301369
Jouni Malinenc52f33d2009-03-03 19:23:29 +02001370 spin_lock_init(&sc->wiphy_lock);
Sujithff37e332008-11-24 12:07:55 +05301371 spin_lock_init(&sc->sc_resetlock);
Sujithaa33de02008-12-18 11:40:16 +05301372 mutex_init(&sc->mutex);
Sujithff37e332008-11-24 12:07:55 +05301373 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
Sujith9fc9ab02009-03-03 10:16:51 +05301374 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
Sujithff37e332008-11-24 12:07:55 +05301375 (unsigned long)sc);
1376
1377 /*
1378 * Cache line size is used to size and align various
1379 * structures used to communicate with the hardware.
1380 */
Gabor Juhos88d15702009-01-14 20:17:04 +01001381 ath_read_cachesize(sc, &csz);
Sujithff37e332008-11-24 12:07:55 +05301382 /* XXX assert csz is non-zero */
Sujith17d79042009-02-09 13:27:03 +05301383 sc->cachelsz = csz << 2; /* convert to bytes */
Sujithff37e332008-11-24 12:07:55 +05301384
Sujithcbe61d82009-02-09 13:27:12 +05301385 ah = ath9k_hw_attach(devid, sc, &status);
Sujithff37e332008-11-24 12:07:55 +05301386 if (ah == NULL) {
1387 DPRINTF(sc, ATH_DBG_FATAL,
Gabor Juhos295834f2008-12-29 21:07:42 +01001388 "Unable to attach hardware; HAL status %d\n", status);
Sujithff37e332008-11-24 12:07:55 +05301389 error = -ENXIO;
1390 goto bad;
1391 }
1392 sc->sc_ah = ah;
1393
1394 /* Get the hardware key cache size. */
Sujith2660b812009-02-09 13:27:26 +05301395 sc->keymax = ah->caps.keycache_size;
Sujith17d79042009-02-09 13:27:03 +05301396 if (sc->keymax > ATH_KEYMAX) {
Sujithff37e332008-11-24 12:07:55 +05301397 DPRINTF(sc, ATH_DBG_KEYCACHE,
Sujith04bd4632008-11-28 22:18:05 +05301398 "Warning, using only %u entries in %u key cache\n",
Sujith17d79042009-02-09 13:27:03 +05301399 ATH_KEYMAX, sc->keymax);
1400 sc->keymax = ATH_KEYMAX;
Sujithff37e332008-11-24 12:07:55 +05301401 }
1402
1403 /*
1404 * Reset the key cache since some parts do not
1405 * reset the contents on initial power up.
1406 */
Sujith17d79042009-02-09 13:27:03 +05301407 for (i = 0; i < sc->keymax; i++)
Sujithff37e332008-11-24 12:07:55 +05301408 ath9k_hw_keyreset(ah, (u16) i);
Sujithff37e332008-11-24 12:07:55 +05301409
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001410 if (ath9k_regd_init(sc->sc_ah))
Sujithff37e332008-11-24 12:07:55 +05301411 goto bad;
1412
1413 /* default to MONITOR mode */
Sujith2660b812009-02-09 13:27:26 +05301414 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
Colin McCabed97809d2008-12-01 13:38:55 -08001415
Sujithff37e332008-11-24 12:07:55 +05301416 /* Setup rate tables */
1417
1418 ath_rate_attach(sc);
1419 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1420 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1421
1422 /*
1423 * Allocate hardware transmit queues: one queue for
1424 * beacon frames and one data queue for each QoS
1425 * priority. Note that the hal handles reseting
1426 * these queues at the needed time.
1427 */
Sujithb77f4832008-12-07 21:44:03 +05301428 sc->beacon.beaconq = ath_beaconq_setup(ah);
1429 if (sc->beacon.beaconq == -1) {
Sujithff37e332008-11-24 12:07:55 +05301430 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301431 "Unable to setup a beacon xmit queue\n");
Sujithff37e332008-11-24 12:07:55 +05301432 error = -EIO;
1433 goto bad2;
1434 }
Sujithb77f4832008-12-07 21:44:03 +05301435 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1436 if (sc->beacon.cabq == NULL) {
Sujithff37e332008-11-24 12:07:55 +05301437 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301438 "Unable to setup CAB xmit queue\n");
Sujithff37e332008-11-24 12:07:55 +05301439 error = -EIO;
1440 goto bad2;
1441 }
1442
Sujith17d79042009-02-09 13:27:03 +05301443 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
Sujithff37e332008-11-24 12:07:55 +05301444 ath_cabq_update(sc);
1445
Sujithb77f4832008-12-07 21:44:03 +05301446 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1447 sc->tx.hwq_map[i] = -1;
Sujithff37e332008-11-24 12:07:55 +05301448
1449 /* Setup data queues */
1450 /* NB: ensure BK queue is the lowest priority h/w queue */
1451 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1452 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301453 "Unable to setup xmit queue for BK traffic\n");
Sujithff37e332008-11-24 12:07:55 +05301454 error = -EIO;
1455 goto bad2;
1456 }
1457
1458 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1459 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301460 "Unable to setup xmit queue for BE traffic\n");
Sujithff37e332008-11-24 12:07:55 +05301461 error = -EIO;
1462 goto bad2;
1463 }
1464 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1465 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301466 "Unable to setup xmit queue for VI traffic\n");
Sujithff37e332008-11-24 12:07:55 +05301467 error = -EIO;
1468 goto bad2;
1469 }
1470 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1471 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301472 "Unable to setup xmit queue for VO traffic\n");
Sujithff37e332008-11-24 12:07:55 +05301473 error = -EIO;
1474 goto bad2;
1475 }
1476
1477 /* Initializes the noise floor to a reasonable default value.
1478 * Later on this will be updated during ANI processing. */
1479
Sujith17d79042009-02-09 13:27:03 +05301480 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1481 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
Sujithff37e332008-11-24 12:07:55 +05301482
1483 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1484 ATH9K_CIPHER_TKIP, NULL)) {
1485 /*
1486 * Whether we should enable h/w TKIP MIC.
1487 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1488 * report WMM capable, so it's always safe to turn on
1489 * TKIP MIC in this case.
1490 */
1491 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1492 0, 1, NULL);
1493 }
1494
1495 /*
1496 * Check whether the separate key cache entries
1497 * are required to handle both tx+rx MIC keys.
1498 * With split mic keys the number of stations is limited
1499 * to 27 otherwise 59.
1500 */
1501 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1502 ATH9K_CIPHER_TKIP, NULL)
1503 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1504 ATH9K_CIPHER_MIC, NULL)
1505 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1506 0, NULL))
Sujith17d79042009-02-09 13:27:03 +05301507 sc->splitmic = 1;
Sujithff37e332008-11-24 12:07:55 +05301508
1509 /* turn on mcast key search if possible */
1510 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1511 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1512 1, NULL);
1513
Sujith17d79042009-02-09 13:27:03 +05301514 sc->config.txpowlimit = ATH_TXPOWER_MAX;
Sujithff37e332008-11-24 12:07:55 +05301515
1516 /* 11n Capabilities */
Sujith2660b812009-02-09 13:27:26 +05301517 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
Sujithff37e332008-11-24 12:07:55 +05301518 sc->sc_flags |= SC_OP_TXAGGR;
1519 sc->sc_flags |= SC_OP_RXAGGR;
1520 }
1521
Sujith2660b812009-02-09 13:27:26 +05301522 sc->tx_chainmask = ah->caps.tx_chainmask;
1523 sc->rx_chainmask = ah->caps.rx_chainmask;
Sujithff37e332008-11-24 12:07:55 +05301524
1525 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
Sujithb77f4832008-12-07 21:44:03 +05301526 sc->rx.defant = ath9k_hw_getdefantenna(ah);
Sujithff37e332008-11-24 12:07:55 +05301527
Jouni Malinen8ca21f02009-03-03 19:23:27 +02001528 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
Sujithba52da52009-02-09 13:27:10 +05301529 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
Sujithff37e332008-11-24 12:07:55 +05301530
Sujithb77f4832008-12-07 21:44:03 +05301531 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
Sujithff37e332008-11-24 12:07:55 +05301532
1533 /* initialize beacon slots */
Jouni Malinenc52f33d2009-03-03 19:23:29 +02001534 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02001535 sc->beacon.bslot[i] = NULL;
Jouni Malinenc52f33d2009-03-03 19:23:29 +02001536 sc->beacon.bslot_aphy[i] = NULL;
1537 }
Sujithff37e332008-11-24 12:07:55 +05301538
1539 /* save MISC configurations */
Sujith17d79042009-02-09 13:27:03 +05301540 sc->config.swBeaconProcess = 1;
Sujithff37e332008-11-24 12:07:55 +05301541
Sujithff37e332008-11-24 12:07:55 +05301542 /* setup channels and rates */
1543
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001544 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
Sujithff37e332008-11-24 12:07:55 +05301545 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1546 sc->rates[IEEE80211_BAND_2GHZ];
1547 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001548 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1549 ARRAY_SIZE(ath9k_2ghz_chantable);
Sujithff37e332008-11-24 12:07:55 +05301550
Sujith2660b812009-02-09 13:27:26 +05301551 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001552 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
Sujithff37e332008-11-24 12:07:55 +05301553 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1554 sc->rates[IEEE80211_BAND_5GHZ];
1555 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001556 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1557 ARRAY_SIZE(ath9k_5ghz_chantable);
Sujithff37e332008-11-24 12:07:55 +05301558 }
1559
Sujith2660b812009-02-09 13:27:26 +05301560 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
Vasanthakumar Thiagarajanc97c92d2009-01-02 15:35:46 +05301561 ath9k_hw_btcoex_enable(sc->sc_ah);
1562
Sujithff37e332008-11-24 12:07:55 +05301563 return 0;
1564bad2:
1565 /* cleanup tx queues */
1566 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1567 if (ATH_TXQ_SETUP(sc, i))
Sujithb77f4832008-12-07 21:44:03 +05301568 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
Sujithff37e332008-11-24 12:07:55 +05301569bad:
1570 if (ah)
1571 ath9k_hw_detach(ah);
Vasanthakumar Thiagarajan40b130a2009-02-16 13:55:07 +05301572 ath9k_exit_debug(sc);
Sujithff37e332008-11-24 12:07:55 +05301573
1574 return error;
1575}
1576
Jouni Malinenc52f33d2009-03-03 19:23:29 +02001577void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301578{
Sujith9c84b792008-10-29 10:17:13 +05301579 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1580 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1581 IEEE80211_HW_SIGNAL_DBM |
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05301582 IEEE80211_HW_AMPDU_AGGREGATION |
1583 IEEE80211_HW_SUPPORTS_PS |
1584 IEEE80211_HW_PS_NULLFUNC_STACK;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301585
Jouni Malinenb3bd89c2009-02-24 13:42:01 +02001586 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001587 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1588
Sujith9c84b792008-10-29 10:17:13 +05301589 hw->wiphy->interface_modes =
1590 BIT(NL80211_IFTYPE_AP) |
1591 BIT(NL80211_IFTYPE_STATION) |
1592 BIT(NL80211_IFTYPE_ADHOC);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301593
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001594 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1595 hw->wiphy->strict_regulatory = true;
1596
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301597 hw->queues = 4;
Sujithe63835b2008-11-18 09:07:53 +05301598 hw->max_rates = 4;
Sujith171387e2009-02-17 15:36:25 +05301599 hw->channel_change_time = 5000;
Sujithe63835b2008-11-18 09:07:53 +05301600 hw->max_rate_tries = ATH_11N_TXMAXTRY;
Sujith528f0c62008-10-29 10:14:26 +05301601 hw->sta_data_size = sizeof(struct ath_node);
Sujith17d79042009-02-09 13:27:03 +05301602 hw->vif_data_size = sizeof(struct ath_vif);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301603
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301604 hw->rate_control_algorithm = "ath9k_rate_control";
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301605
Jouni Malinenc52f33d2009-03-03 19:23:29 +02001606 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1607 &sc->sbands[IEEE80211_BAND_2GHZ];
1608 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1609 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1610 &sc->sbands[IEEE80211_BAND_5GHZ];
1611}
1612
1613int ath_attach(u16 devid, struct ath_softc *sc)
1614{
1615 struct ieee80211_hw *hw = sc->hw;
1616 const struct ieee80211_regdomain *regd;
1617 int error = 0, i;
1618
1619 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1620
1621 error = ath_init(devid, sc);
1622 if (error != 0)
1623 return error;
1624
1625 /* get mac address from hardware and set in mac80211 */
1626
1627 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1628
1629 ath_set_hw_capab(sc, hw);
1630
Sujith2660b812009-02-09 13:27:26 +05301631 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
Sujitheb2599c2009-01-23 11:20:44 +05301632 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
Sujith2660b812009-02-09 13:27:26 +05301633 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
Sujitheb2599c2009-01-23 11:20:44 +05301634 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
Sujith9c84b792008-10-29 10:17:13 +05301635 }
1636
Senthil Balasubramaniandb93e7b2008-11-13 18:01:08 +05301637 /* initialize tx/rx engine */
1638 error = ath_tx_init(sc, ATH_TXBUF);
1639 if (error != 0)
Vasanthakumar Thiagarajan40b130a2009-02-16 13:55:07 +05301640 goto error_attach;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301641
Senthil Balasubramaniandb93e7b2008-11-13 18:01:08 +05301642 error = ath_rx_init(sc, ATH_RXBUF);
1643 if (error != 0)
Vasanthakumar Thiagarajan40b130a2009-02-16 13:55:07 +05301644 goto error_attach;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301645
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05301646#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301647 /* Initialze h/w Rfkill */
Sujith2660b812009-02-09 13:27:26 +05301648 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301649 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1650
1651 /* Initialize s/w rfkill */
Vasanthakumar Thiagarajan40b130a2009-02-16 13:55:07 +05301652 error = ath_init_sw_rfkill(sc);
1653 if (error)
1654 goto error_attach;
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301655#endif
1656
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001657 if (ath9k_is_world_regd(sc->sc_ah)) {
Bob Copeland191a99b2009-02-12 13:38:58 -05001658 /* Anything applied here (prior to wiphy registration) gets
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001659 * saved on the wiphy orig_* parameters */
Bob Copeland191a99b2009-02-12 13:38:58 -05001660 regd = ath9k_world_regdomain(sc->sc_ah);
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001661 hw->wiphy->custom_regulatory = true;
1662 hw->wiphy->strict_regulatory = false;
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001663 } else {
1664 /* This gets applied in the case of the absense of CRDA,
Bob Copeland191a99b2009-02-12 13:38:58 -05001665 * it's our own custom world regulatory domain, similar to
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001666 * cfg80211's but we enable passive scanning */
Bob Copeland191a99b2009-02-12 13:38:58 -05001667 regd = ath9k_default_world_regdomain();
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001668 }
Bob Copeland191a99b2009-02-12 13:38:58 -05001669 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1670 ath9k_reg_apply_radar_flags(hw->wiphy);
1671 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001672
Jouni Malinen0e2dedf2009-03-03 19:23:32 +02001673 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1674
Senthil Balasubramaniandb93e7b2008-11-13 18:01:08 +05301675 error = ieee80211_register_hw(hw);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301676
Luis R. Rodriguezfe33eb32009-02-21 00:04:30 -05001677 if (!ath9k_is_world_regd(sc->sc_ah)) {
1678 error = regulatory_hint(hw->wiphy,
1679 sc->sc_ah->regulatory.alpha2);
1680 if (error)
1681 goto error_attach;
1682 }
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001683
Senthil Balasubramaniandb93e7b2008-11-13 18:01:08 +05301684 /* Initialize LED control */
1685 ath_init_leds(sc);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301686
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001687
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301688 return 0;
Vasanthakumar Thiagarajan40b130a2009-02-16 13:55:07 +05301689
1690error_attach:
1691 /* cleanup tx queues */
1692 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1693 if (ATH_TXQ_SETUP(sc, i))
1694 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1695
1696 ath9k_hw_detach(sc->sc_ah);
1697 ath9k_exit_debug(sc);
1698
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301699 return error;
1700}
1701
Sujithff37e332008-11-24 12:07:55 +05301702int ath_reset(struct ath_softc *sc, bool retry_tx)
1703{
Sujithcbe61d82009-02-09 13:27:12 +05301704 struct ath_hw *ah = sc->sc_ah;
Luis R. Rodriguez030bb492008-12-23 15:58:37 -08001705 struct ieee80211_hw *hw = sc->hw;
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001706 int r;
Sujithff37e332008-11-24 12:07:55 +05301707
1708 ath9k_hw_set_interrupts(ah, 0);
Sujith043a0402009-01-16 21:38:47 +05301709 ath_drain_all_txq(sc, retry_tx);
Sujithff37e332008-11-24 12:07:55 +05301710 ath_stoprecv(sc);
1711 ath_flushrecv(sc);
1712
1713 spin_lock_bh(&sc->sc_resetlock);
Sujith2660b812009-02-09 13:27:26 +05301714 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001715 if (r)
Sujithff37e332008-11-24 12:07:55 +05301716 DPRINTF(sc, ATH_DBG_FATAL,
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001717 "Unable to reset hardware; reset status %u\n", r);
Sujithff37e332008-11-24 12:07:55 +05301718 spin_unlock_bh(&sc->sc_resetlock);
1719
1720 if (ath_startrecv(sc) != 0)
Sujith04bd4632008-11-28 22:18:05 +05301721 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
Sujithff37e332008-11-24 12:07:55 +05301722
1723 /*
1724 * We may be doing a reset in response to a request
1725 * that changes the channel so update any state that
1726 * might change as a result.
1727 */
Luis R. Rodriguezce111ba2008-12-23 15:58:39 -08001728 ath_cache_conf_rate(sc, &hw->conf);
Sujithff37e332008-11-24 12:07:55 +05301729
1730 ath_update_txpow(sc);
1731
1732 if (sc->sc_flags & SC_OP_BEACONS)
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02001733 ath_beacon_config(sc, NULL); /* restart beacons */
Sujithff37e332008-11-24 12:07:55 +05301734
Sujith17d79042009-02-09 13:27:03 +05301735 ath9k_hw_set_interrupts(ah, sc->imask);
Sujithff37e332008-11-24 12:07:55 +05301736
1737 if (retry_tx) {
1738 int i;
1739 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1740 if (ATH_TXQ_SETUP(sc, i)) {
Sujithb77f4832008-12-07 21:44:03 +05301741 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1742 ath_txq_schedule(sc, &sc->tx.txq[i]);
1743 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
Sujithff37e332008-11-24 12:07:55 +05301744 }
1745 }
1746 }
1747
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001748 return r;
Sujithff37e332008-11-24 12:07:55 +05301749}
1750
1751/*
1752 * This function will allocate both the DMA descriptor structure, and the
1753 * buffers it contains. These are used to contain the descriptors used
1754 * by the system.
1755*/
1756int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1757 struct list_head *head, const char *name,
1758 int nbuf, int ndesc)
1759{
1760#define DS2PHYS(_dd, _ds) \
1761 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1762#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1763#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1764
1765 struct ath_desc *ds;
1766 struct ath_buf *bf;
1767 int i, bsize, error;
1768
Sujith04bd4632008-11-28 22:18:05 +05301769 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1770 name, nbuf, ndesc);
Sujithff37e332008-11-24 12:07:55 +05301771
1772 /* ath_desc must be a multiple of DWORDs */
1773 if ((sizeof(struct ath_desc) % 4) != 0) {
Sujith04bd4632008-11-28 22:18:05 +05301774 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
Sujithff37e332008-11-24 12:07:55 +05301775 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1776 error = -ENOMEM;
1777 goto fail;
1778 }
1779
1780 dd->dd_name = name;
1781 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1782
1783 /*
1784 * Need additional DMA memory because we can't use
1785 * descriptors that cross the 4K page boundary. Assume
1786 * one skipped descriptor per 4K page.
1787 */
Sujith2660b812009-02-09 13:27:26 +05301788 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
Sujithff37e332008-11-24 12:07:55 +05301789 u32 ndesc_skipped =
1790 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1791 u32 dma_len;
1792
1793 while (ndesc_skipped) {
1794 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1795 dd->dd_desc_len += dma_len;
1796
1797 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1798 };
1799 }
1800
1801 /* allocate descriptors */
Gabor Juhos7da3c552009-01-14 20:17:03 +01001802 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1803 &dd->dd_desc_paddr, GFP_ATOMIC);
Sujithff37e332008-11-24 12:07:55 +05301804 if (dd->dd_desc == NULL) {
1805 error = -ENOMEM;
1806 goto fail;
1807 }
1808 ds = dd->dd_desc;
Sujith04bd4632008-11-28 22:18:05 +05301809 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1810 dd->dd_name, ds, (u32) dd->dd_desc_len,
Sujithff37e332008-11-24 12:07:55 +05301811 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1812
1813 /* allocate buffers */
1814 bsize = sizeof(struct ath_buf) * nbuf;
1815 bf = kmalloc(bsize, GFP_KERNEL);
1816 if (bf == NULL) {
1817 error = -ENOMEM;
1818 goto fail2;
1819 }
1820 memset(bf, 0, bsize);
1821 dd->dd_bufptr = bf;
1822
1823 INIT_LIST_HEAD(head);
1824 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1825 bf->bf_desc = ds;
1826 bf->bf_daddr = DS2PHYS(dd, ds);
1827
Sujith2660b812009-02-09 13:27:26 +05301828 if (!(sc->sc_ah->caps.hw_caps &
Sujithff37e332008-11-24 12:07:55 +05301829 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1830 /*
1831 * Skip descriptor addresses which can cause 4KB
1832 * boundary crossing (addr + length) with a 32 dword
1833 * descriptor fetch.
1834 */
1835 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1836 ASSERT((caddr_t) bf->bf_desc <
1837 ((caddr_t) dd->dd_desc +
1838 dd->dd_desc_len));
1839
1840 ds += ndesc;
1841 bf->bf_desc = ds;
1842 bf->bf_daddr = DS2PHYS(dd, ds);
1843 }
1844 }
1845 list_add_tail(&bf->list, head);
1846 }
1847 return 0;
1848fail2:
Gabor Juhos7da3c552009-01-14 20:17:03 +01001849 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1850 dd->dd_desc_paddr);
Sujithff37e332008-11-24 12:07:55 +05301851fail:
1852 memset(dd, 0, sizeof(*dd));
1853 return error;
1854#undef ATH_DESC_4KB_BOUND_CHECK
1855#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1856#undef DS2PHYS
1857}
1858
1859void ath_descdma_cleanup(struct ath_softc *sc,
1860 struct ath_descdma *dd,
1861 struct list_head *head)
1862{
Gabor Juhos7da3c552009-01-14 20:17:03 +01001863 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1864 dd->dd_desc_paddr);
Sujithff37e332008-11-24 12:07:55 +05301865
1866 INIT_LIST_HEAD(head);
1867 kfree(dd->dd_bufptr);
1868 memset(dd, 0, sizeof(*dd));
1869}
1870
1871int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1872{
1873 int qnum;
1874
1875 switch (queue) {
1876 case 0:
Sujithb77f4832008-12-07 21:44:03 +05301877 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
Sujithff37e332008-11-24 12:07:55 +05301878 break;
1879 case 1:
Sujithb77f4832008-12-07 21:44:03 +05301880 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
Sujithff37e332008-11-24 12:07:55 +05301881 break;
1882 case 2:
Sujithb77f4832008-12-07 21:44:03 +05301883 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
Sujithff37e332008-11-24 12:07:55 +05301884 break;
1885 case 3:
Sujithb77f4832008-12-07 21:44:03 +05301886 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
Sujithff37e332008-11-24 12:07:55 +05301887 break;
1888 default:
Sujithb77f4832008-12-07 21:44:03 +05301889 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
Sujithff37e332008-11-24 12:07:55 +05301890 break;
1891 }
1892
1893 return qnum;
1894}
1895
1896int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1897{
1898 int qnum;
1899
1900 switch (queue) {
1901 case ATH9K_WME_AC_VO:
1902 qnum = 0;
1903 break;
1904 case ATH9K_WME_AC_VI:
1905 qnum = 1;
1906 break;
1907 case ATH9K_WME_AC_BE:
1908 qnum = 2;
1909 break;
1910 case ATH9K_WME_AC_BK:
1911 qnum = 3;
1912 break;
1913 default:
1914 qnum = -1;
1915 break;
1916 }
1917
1918 return qnum;
1919}
1920
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001921/* XXX: Remove me once we don't depend on ath9k_channel for all
1922 * this redundant data */
Jouni Malinen0e2dedf2009-03-03 19:23:32 +02001923void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1924 struct ath9k_channel *ichan)
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001925{
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001926 struct ieee80211_channel *chan = hw->conf.channel;
1927 struct ieee80211_conf *conf = &hw->conf;
1928
1929 ichan->channel = chan->center_freq;
1930 ichan->chan = chan;
1931
1932 if (chan->band == IEEE80211_BAND_2GHZ) {
1933 ichan->chanmode = CHANNEL_G;
1934 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1935 } else {
1936 ichan->chanmode = CHANNEL_A;
1937 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1938 }
1939
1940 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1941
1942 if (conf_is_ht(conf)) {
1943 if (conf_is_ht40(conf))
1944 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1945
1946 ichan->chanmode = ath_get_extchanmode(sc, chan,
1947 conf->channel_type);
1948 }
1949}
1950
Sujithff37e332008-11-24 12:07:55 +05301951/**********************/
1952/* mac80211 callbacks */
1953/**********************/
1954
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001955static int ath9k_start(struct ieee80211_hw *hw)
1956{
Jouni Malinenbce048d2009-03-03 19:23:28 +02001957 struct ath_wiphy *aphy = hw->priv;
1958 struct ath_softc *sc = aphy->sc;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001959 struct ieee80211_channel *curchan = hw->conf.channel;
Sujithff37e332008-11-24 12:07:55 +05301960 struct ath9k_channel *init_channel;
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001961 int r, pos;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001962
Sujith04bd4632008-11-28 22:18:05 +05301963 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1964 "initial channel: %d MHz\n", curchan->center_freq);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001965
Sujith141b38b2009-02-04 08:10:07 +05301966 mutex_lock(&sc->mutex);
1967
Jouni Malinen9580a222009-03-03 19:23:33 +02001968 if (ath9k_wiphy_started(sc)) {
1969 if (sc->chan_idx == curchan->hw_value) {
1970 /*
1971 * Already on the operational channel, the new wiphy
1972 * can be marked active.
1973 */
1974 aphy->state = ATH_WIPHY_ACTIVE;
1975 ieee80211_wake_queues(hw);
1976 } else {
1977 /*
1978 * Another wiphy is on another channel, start the new
1979 * wiphy in paused state.
1980 */
1981 aphy->state = ATH_WIPHY_PAUSED;
1982 ieee80211_stop_queues(hw);
1983 }
1984 mutex_unlock(&sc->mutex);
1985 return 0;
1986 }
1987 aphy->state = ATH_WIPHY_ACTIVE;
1988
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001989 /* setup initial channel */
1990
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001991 pos = curchan->hw_value;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001992
Jouni Malinen0e2dedf2009-03-03 19:23:32 +02001993 sc->chan_idx = pos;
Sujith2660b812009-02-09 13:27:26 +05301994 init_channel = &sc->sc_ah->channels[pos];
Jouni Malinen0e2dedf2009-03-03 19:23:32 +02001995 ath9k_update_ichannel(sc, hw, init_channel);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001996
Sujithff37e332008-11-24 12:07:55 +05301997 /* Reset SERDES registers */
1998 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1999
2000 /*
2001 * The basic interface to setting the hardware in a good
2002 * state is ``reset''. On return the hardware is known to
2003 * be powered up and with interrupts disabled. This must
2004 * be followed by initialization of the appropriate bits
2005 * and then setup of the interrupt mask.
2006 */
2007 spin_lock_bh(&sc->sc_resetlock);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08002008 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2009 if (r) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002010 DPRINTF(sc, ATH_DBG_FATAL,
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08002011 "Unable to reset hardware; reset status %u "
2012 "(freq %u MHz)\n", r,
2013 curchan->center_freq);
Sujithff37e332008-11-24 12:07:55 +05302014 spin_unlock_bh(&sc->sc_resetlock);
Sujith141b38b2009-02-04 08:10:07 +05302015 goto mutex_unlock;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002016 }
Sujithff37e332008-11-24 12:07:55 +05302017 spin_unlock_bh(&sc->sc_resetlock);
2018
2019 /*
2020 * This is needed only to setup initial state
2021 * but it's best done after a reset.
2022 */
2023 ath_update_txpow(sc);
2024
2025 /*
2026 * Setup the hardware after reset:
2027 * The receive engine is set going.
2028 * Frame transmit is handled entirely
2029 * in the frame output path; there's nothing to do
2030 * here except setup the interrupt mask.
2031 */
2032 if (ath_startrecv(sc) != 0) {
2033 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05302034 "Unable to start recv logic\n");
Sujith141b38b2009-02-04 08:10:07 +05302035 r = -EIO;
2036 goto mutex_unlock;
Sujithff37e332008-11-24 12:07:55 +05302037 }
2038
2039 /* Setup our intr mask. */
Sujith17d79042009-02-09 13:27:03 +05302040 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
Sujithff37e332008-11-24 12:07:55 +05302041 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2042 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2043
Sujith2660b812009-02-09 13:27:26 +05302044 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
Sujith17d79042009-02-09 13:27:03 +05302045 sc->imask |= ATH9K_INT_GTT;
Sujithff37e332008-11-24 12:07:55 +05302046
Sujith2660b812009-02-09 13:27:26 +05302047 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
Sujith17d79042009-02-09 13:27:03 +05302048 sc->imask |= ATH9K_INT_CST;
Sujithff37e332008-11-24 12:07:55 +05302049
Luis R. Rodriguezce111ba2008-12-23 15:58:39 -08002050 ath_cache_conf_rate(sc, &hw->conf);
Sujithff37e332008-11-24 12:07:55 +05302051
2052 sc->sc_flags &= ~SC_OP_INVALID;
2053
2054 /* Disable BMISS interrupt when we're not associated */
Sujith17d79042009-02-09 13:27:03 +05302055 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2056 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
Sujithff37e332008-11-24 12:07:55 +05302057
Jouni Malinenbce048d2009-03-03 19:23:28 +02002058 ieee80211_wake_queues(hw);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002059
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05302060#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08002061 r = ath_start_rfkill_poll(sc);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05302062#endif
Sujith141b38b2009-02-04 08:10:07 +05302063
2064mutex_unlock:
2065 mutex_unlock(&sc->mutex);
2066
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08002067 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002068}
2069
2070static int ath9k_tx(struct ieee80211_hw *hw,
2071 struct sk_buff *skb)
2072{
Jouni Malinen147583c2008-08-11 14:01:50 +03002073 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Jouni Malinenbce048d2009-03-03 19:23:28 +02002074 struct ath_wiphy *aphy = hw->priv;
2075 struct ath_softc *sc = aphy->sc;
Sujith528f0c62008-10-29 10:14:26 +05302076 struct ath_tx_control txctl;
2077 int hdrlen, padsize;
2078
2079 memset(&txctl, 0, sizeof(struct ath_tx_control));
Jouni Malinen147583c2008-08-11 14:01:50 +03002080
2081 /*
2082 * As a temporary workaround, assign seq# here; this will likely need
2083 * to be cleaned up to work better with Beacon transmission and virtual
2084 * BSSes.
2085 */
2086 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2087 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2088 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
Sujithb77f4832008-12-07 21:44:03 +05302089 sc->tx.seq_no += 0x10;
Jouni Malinen147583c2008-08-11 14:01:50 +03002090 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
Sujithb77f4832008-12-07 21:44:03 +05302091 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
Jouni Malinen147583c2008-08-11 14:01:50 +03002092 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002093
2094 /* Add the padding after the header if this is not already done */
2095 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2096 if (hdrlen & 3) {
2097 padsize = hdrlen % 4;
2098 if (skb_headroom(skb) < padsize)
2099 return -1;
2100 skb_push(skb, padsize);
2101 memmove(skb->data, skb->data + padsize, hdrlen);
2102 }
2103
Sujith528f0c62008-10-29 10:14:26 +05302104 /* Check if a tx queue is available */
2105
2106 txctl.txq = ath_test_get_txq(sc, skb);
2107 if (!txctl.txq)
2108 goto exit;
2109
Sujith04bd4632008-11-28 22:18:05 +05302110 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002111
Jouni Malinenc52f33d2009-03-03 19:23:29 +02002112 if (ath_tx_start(hw, skb, &txctl) != 0) {
Sujith04bd4632008-11-28 22:18:05 +05302113 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
Sujith528f0c62008-10-29 10:14:26 +05302114 goto exit;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002115 }
2116
2117 return 0;
Sujith528f0c62008-10-29 10:14:26 +05302118exit:
2119 dev_kfree_skb_any(skb);
2120 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002121}
2122
2123static void ath9k_stop(struct ieee80211_hw *hw)
2124{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002125 struct ath_wiphy *aphy = hw->priv;
2126 struct ath_softc *sc = aphy->sc;
Sujith9c84b792008-10-29 10:17:13 +05302127
Jouni Malinen9580a222009-03-03 19:23:33 +02002128 aphy->state = ATH_WIPHY_INACTIVE;
2129
Sujith9c84b792008-10-29 10:17:13 +05302130 if (sc->sc_flags & SC_OP_INVALID) {
Sujith04bd4632008-11-28 22:18:05 +05302131 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
Sujith9c84b792008-10-29 10:17:13 +05302132 return;
2133 }
2134
Sujith141b38b2009-02-04 08:10:07 +05302135 mutex_lock(&sc->mutex);
Sujithff37e332008-11-24 12:07:55 +05302136
Jouni Malinenbce048d2009-03-03 19:23:28 +02002137 ieee80211_stop_queues(hw);
Sujithff37e332008-11-24 12:07:55 +05302138
Jouni Malinen9580a222009-03-03 19:23:33 +02002139 if (ath9k_wiphy_started(sc)) {
2140 mutex_unlock(&sc->mutex);
2141 return; /* another wiphy still in use */
2142 }
2143
Sujithff37e332008-11-24 12:07:55 +05302144 /* make sure h/w will not generate any interrupt
2145 * before setting the invalid flag. */
2146 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2147
2148 if (!(sc->sc_flags & SC_OP_INVALID)) {
Sujith043a0402009-01-16 21:38:47 +05302149 ath_drain_all_txq(sc, false);
Sujithff37e332008-11-24 12:07:55 +05302150 ath_stoprecv(sc);
2151 ath9k_hw_phy_disable(sc->sc_ah);
2152 } else
Sujithb77f4832008-12-07 21:44:03 +05302153 sc->rx.rxlink = NULL;
Sujithff37e332008-11-24 12:07:55 +05302154
2155#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith2660b812009-02-09 13:27:26 +05302156 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Sujithff37e332008-11-24 12:07:55 +05302157 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2158#endif
2159 /* disable HAL and put h/w to sleep */
2160 ath9k_hw_disable(sc->sc_ah);
2161 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2162
2163 sc->sc_flags |= SC_OP_INVALID;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002164
Sujith141b38b2009-02-04 08:10:07 +05302165 mutex_unlock(&sc->mutex);
2166
Sujith04bd4632008-11-28 22:18:05 +05302167 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002168}
2169
2170static int ath9k_add_interface(struct ieee80211_hw *hw,
2171 struct ieee80211_if_init_conf *conf)
2172{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002173 struct ath_wiphy *aphy = hw->priv;
2174 struct ath_softc *sc = aphy->sc;
Sujith17d79042009-02-09 13:27:03 +05302175 struct ath_vif *avp = (void *)conf->vif->drv_priv;
Colin McCabed97809d2008-12-01 13:38:55 -08002176 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002177 int ret = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002178
Sujith141b38b2009-02-04 08:10:07 +05302179 mutex_lock(&sc->mutex);
2180
Jouni Malinen8ca21f02009-03-03 19:23:27 +02002181 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2182 sc->nvifs > 0) {
2183 ret = -ENOBUFS;
2184 goto out;
2185 }
2186
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002187 switch (conf->type) {
Johannes Berg05c914f2008-09-11 00:01:58 +02002188 case NL80211_IFTYPE_STATION:
Colin McCabed97809d2008-12-01 13:38:55 -08002189 ic_opmode = NL80211_IFTYPE_STATION;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002190 break;
Johannes Berg05c914f2008-09-11 00:01:58 +02002191 case NL80211_IFTYPE_ADHOC:
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002192 if (sc->nbcnvifs >= ATH_BCBUF) {
2193 ret = -ENOBUFS;
2194 goto out;
2195 }
Colin McCabed97809d2008-12-01 13:38:55 -08002196 ic_opmode = NL80211_IFTYPE_ADHOC;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002197 break;
Johannes Berg05c914f2008-09-11 00:01:58 +02002198 case NL80211_IFTYPE_AP:
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002199 if (sc->nbcnvifs >= ATH_BCBUF) {
2200 ret = -ENOBUFS;
2201 goto out;
2202 }
Colin McCabed97809d2008-12-01 13:38:55 -08002203 ic_opmode = NL80211_IFTYPE_AP;
Jouni Malinen2ad67de2008-08-11 14:01:47 +03002204 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002205 default:
2206 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05302207 "Interface type %d not yet supported\n", conf->type);
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002208 ret = -EOPNOTSUPP;
2209 goto out;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002210 }
2211
Sujith17d79042009-02-09 13:27:03 +05302212 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002213
Sujith17d79042009-02-09 13:27:03 +05302214 /* Set the VIF opmode */
Sujith5640b082008-10-29 10:16:06 +05302215 avp->av_opmode = ic_opmode;
2216 avp->av_bslot = -1;
2217
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002218 sc->nvifs++;
Jouni Malinen8ca21f02009-03-03 19:23:27 +02002219
2220 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2221 ath9k_set_bssid_mask(hw);
2222
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002223 if (sc->nvifs > 1)
2224 goto out; /* skip global settings for secondary vif */
2225
Sujithb238e902009-03-03 10:16:56 +05302226 if (ic_opmode == NL80211_IFTYPE_AP) {
Sujith5640b082008-10-29 10:16:06 +05302227 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
Sujithb238e902009-03-03 10:16:56 +05302228 sc->sc_flags |= SC_OP_TSF_RESET;
2229 }
Sujith5640b082008-10-29 10:16:06 +05302230
Sujith5640b082008-10-29 10:16:06 +05302231 /* Set the device opmode */
Sujith2660b812009-02-09 13:27:26 +05302232 sc->sc_ah->opmode = ic_opmode;
Sujith5640b082008-10-29 10:16:06 +05302233
Vivek Natarajan4e30ffa2009-01-28 20:53:27 +05302234 /*
2235 * Enable MIB interrupts when there are hardware phy counters.
2236 * Note we only do this (at the moment) for station mode.
2237 */
Sujith4af9cf42009-02-12 10:06:47 +05302238 if ((conf->type == NL80211_IFTYPE_STATION) ||
2239 (conf->type == NL80211_IFTYPE_ADHOC)) {
2240 if (ath9k_hw_phycounters(sc->sc_ah))
2241 sc->imask |= ATH9K_INT_MIB;
2242 sc->imask |= ATH9K_INT_TSFOOR;
2243 }
2244
Vivek Natarajan4e30ffa2009-01-28 20:53:27 +05302245 /*
2246 * Some hardware processes the TIM IE and fires an
2247 * interrupt when the TIM bit is set. For hardware
2248 * that does, if not overridden by configuration,
2249 * enable the TIM interrupt when operating as station.
2250 */
Sujith2660b812009-02-09 13:27:26 +05302251 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
Vivek Natarajan4e30ffa2009-01-28 20:53:27 +05302252 (conf->type == NL80211_IFTYPE_STATION) &&
Sujith17d79042009-02-09 13:27:03 +05302253 !sc->config.swBeaconProcess)
2254 sc->imask |= ATH9K_INT_TIM;
Vivek Natarajan4e30ffa2009-01-28 20:53:27 +05302255
Sujith17d79042009-02-09 13:27:03 +05302256 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
Vivek Natarajan4e30ffa2009-01-28 20:53:27 +05302257
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002258 if (conf->type == NL80211_IFTYPE_AP) {
2259 /* TODO: is this a suitable place to start ANI for AP mode? */
2260 /* Start ANI */
Sujith17d79042009-02-09 13:27:03 +05302261 mod_timer(&sc->ani.timer,
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002262 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2263 }
2264
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002265out:
Sujith141b38b2009-02-04 08:10:07 +05302266 mutex_unlock(&sc->mutex);
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002267 return ret;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002268}
2269
2270static void ath9k_remove_interface(struct ieee80211_hw *hw,
2271 struct ieee80211_if_init_conf *conf)
2272{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002273 struct ath_wiphy *aphy = hw->priv;
2274 struct ath_softc *sc = aphy->sc;
Sujith17d79042009-02-09 13:27:03 +05302275 struct ath_vif *avp = (void *)conf->vif->drv_priv;
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002276 int i;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002277
Sujith04bd4632008-11-28 22:18:05 +05302278 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002279
Sujith141b38b2009-02-04 08:10:07 +05302280 mutex_lock(&sc->mutex);
2281
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002282 /* Stop ANI */
Sujith17d79042009-02-09 13:27:03 +05302283 del_timer_sync(&sc->ani.timer);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002284
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002285 /* Reclaim beacon resources */
Sujith2660b812009-02-09 13:27:26 +05302286 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2287 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
Sujithb77f4832008-12-07 21:44:03 +05302288 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002289 ath_beacon_return(sc, avp);
2290 }
2291
Sujith672840a2008-08-11 14:05:08 +05302292 sc->sc_flags &= ~SC_OP_BEACONS;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002293
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002294 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2295 if (sc->beacon.bslot[i] == conf->vif) {
2296 printk(KERN_DEBUG "%s: vif had allocated beacon "
2297 "slot\n", __func__);
2298 sc->beacon.bslot[i] = NULL;
Jouni Malinenc52f33d2009-03-03 19:23:29 +02002299 sc->beacon.bslot_aphy[i] = NULL;
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002300 }
2301 }
2302
Sujith17d79042009-02-09 13:27:03 +05302303 sc->nvifs--;
Sujith141b38b2009-02-04 08:10:07 +05302304
2305 mutex_unlock(&sc->mutex);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002306}
2307
Johannes Berge8975582008-10-09 12:18:51 +02002308static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002309{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002310 struct ath_wiphy *aphy = hw->priv;
2311 struct ath_softc *sc = aphy->sc;
Johannes Berge8975582008-10-09 12:18:51 +02002312 struct ieee80211_conf *conf = &hw->conf;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002313
Sujithaa33de02008-12-18 11:40:16 +05302314 mutex_lock(&sc->mutex);
Sujith141b38b2009-02-04 08:10:07 +05302315
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05302316 if (changed & IEEE80211_CONF_CHANGE_PS) {
2317 if (conf->flags & IEEE80211_CONF_PS) {
Sujith17d79042009-02-09 13:27:03 +05302318 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2319 sc->imask |= ATH9K_INT_TIM_TIMER;
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05302320 ath9k_hw_set_interrupts(sc->sc_ah,
Sujith17d79042009-02-09 13:27:03 +05302321 sc->imask);
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05302322 }
2323 ath9k_hw_setrxabort(sc->sc_ah, 1);
2324 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2325 } else {
2326 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2327 ath9k_hw_setrxabort(sc->sc_ah, 0);
2328 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
Sujith17d79042009-02-09 13:27:03 +05302329 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2330 sc->imask &= ~ATH9K_INT_TIM_TIMER;
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05302331 ath9k_hw_set_interrupts(sc->sc_ah,
Sujith17d79042009-02-09 13:27:03 +05302332 sc->imask);
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05302333 }
2334 }
2335 }
2336
Johannes Berg47979382009-01-07 10:13:27 +01002337 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
Sujith99405f92008-11-24 12:08:35 +05302338 struct ieee80211_channel *curchan = hw->conf.channel;
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08002339 int pos = curchan->hw_value;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002340
Jouni Malinen0e2dedf2009-03-03 19:23:32 +02002341 aphy->chan_idx = pos;
2342 aphy->chan_is_ht = conf_is_ht(conf);
2343
2344 /* TODO: do not change operation channel immediately if there
2345 * are other virtual wiphys that use another channel */
2346
Sujith04bd4632008-11-28 22:18:05 +05302347 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2348 curchan->center_freq);
Johannes Bergae5eb022008-10-14 16:58:37 +02002349
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08002350 /* XXX: remove me eventualy */
Jouni Malinen0e2dedf2009-03-03 19:23:32 +02002351 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
Sujithe11602b2008-11-27 09:46:27 +05302352
Luis R. Rodriguezecf70442008-12-23 15:58:43 -08002353 ath_update_chainmask(sc, conf_is_ht(conf));
Sujith86060f02009-01-07 14:25:29 +05302354
Jouni Malinen0e2dedf2009-03-03 19:23:32 +02002355 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
Sujith04bd4632008-11-28 22:18:05 +05302356 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
Sujithaa33de02008-12-18 11:40:16 +05302357 mutex_unlock(&sc->mutex);
Sujithe11602b2008-11-27 09:46:27 +05302358 return -EINVAL;
2359 }
Sujith094d05d2008-12-12 11:57:43 +05302360 }
Sujith86b89ee2008-08-07 10:54:57 +05302361
Luis R. Rodriguez5c020dc2008-10-22 13:28:45 -07002362 if (changed & IEEE80211_CONF_CHANGE_POWER)
Sujith17d79042009-02-09 13:27:03 +05302363 sc->config.txpowlimit = 2 * conf->power_level;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002364
Sujithb238e902009-03-03 10:16:56 +05302365 /*
2366 * The HW TSF has to be reset when the beacon interval changes.
2367 * We set the flag here, and ath_beacon_config_ap() would take this
2368 * into account when it gets called through the subsequent
2369 * config_interface() call - with IFCC_BEACON in the changed field.
2370 */
2371
2372 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2373 sc->sc_flags |= SC_OP_TSF_RESET;
2374
Sujithaa33de02008-12-18 11:40:16 +05302375 mutex_unlock(&sc->mutex);
Sujith141b38b2009-02-04 08:10:07 +05302376
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002377 return 0;
2378}
2379
2380static int ath9k_config_interface(struct ieee80211_hw *hw,
2381 struct ieee80211_vif *vif,
2382 struct ieee80211_if_conf *conf)
2383{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002384 struct ath_wiphy *aphy = hw->priv;
2385 struct ath_softc *sc = aphy->sc;
Sujithcbe61d82009-02-09 13:27:12 +05302386 struct ath_hw *ah = sc->sc_ah;
Sujith17d79042009-02-09 13:27:03 +05302387 struct ath_vif *avp = (void *)vif->drv_priv;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002388 u32 rfilt = 0;
2389 int error, i;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002390
Sujith25549352009-03-03 10:16:57 +05302391 mutex_lock(&sc->mutex);
2392
Jouni Malinen2ad67de2008-08-11 14:01:47 +03002393 /* TODO: Need to decide which hw opmode to use for multi-interface
2394 * cases */
Johannes Berg05c914f2008-09-11 00:01:58 +02002395 if (vif->type == NL80211_IFTYPE_AP &&
Sujith2660b812009-02-09 13:27:26 +05302396 ah->opmode != NL80211_IFTYPE_AP) {
2397 ah->opmode = NL80211_IFTYPE_STATION;
Jouni Malinen2ad67de2008-08-11 14:01:47 +03002398 ath9k_hw_setopmode(ah);
Sujithba52da52009-02-09 13:27:10 +05302399 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2400 sc->curaid = 0;
2401 ath9k_hw_write_associd(sc);
Jouni Malinen2ad67de2008-08-11 14:01:47 +03002402 /* Request full reset to get hw opmode changed properly */
2403 sc->sc_flags |= SC_OP_FULL_RESET;
2404 }
2405
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002406 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2407 !is_zero_ether_addr(conf->bssid)) {
2408 switch (vif->type) {
Johannes Berg05c914f2008-09-11 00:01:58 +02002409 case NL80211_IFTYPE_STATION:
2410 case NL80211_IFTYPE_ADHOC:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002411 /* Set BSSID */
Sujith17d79042009-02-09 13:27:03 +05302412 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
Jouni Malinenf0ed85c2009-03-03 19:23:31 +02002413 memcpy(avp->bssid, conf->bssid, ETH_ALEN);
Sujith17d79042009-02-09 13:27:03 +05302414 sc->curaid = 0;
Sujithba52da52009-02-09 13:27:10 +05302415 ath9k_hw_write_associd(sc);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002416
2417 /* Set aggregation protection mode parameters */
Sujith17d79042009-02-09 13:27:03 +05302418 sc->config.ath_aggr_prot = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002419
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002420 DPRINTF(sc, ATH_DBG_CONFIG,
Sujith04bd4632008-11-28 22:18:05 +05302421 "RX filter 0x%x bssid %pM aid 0x%x\n",
Sujith17d79042009-02-09 13:27:03 +05302422 rfilt, sc->curbssid, sc->curaid);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002423
2424 /* need to reconfigure the beacon */
Sujith672840a2008-08-11 14:05:08 +05302425 sc->sc_flags &= ~SC_OP_BEACONS ;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002426
2427 break;
2428 default:
2429 break;
2430 }
2431 }
2432
Sujith1f7d6cb2009-01-27 10:55:54 +05302433 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2434 (vif->type == NL80211_IFTYPE_AP)) {
2435 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2436 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2437 conf->enable_beacon)) {
2438 /*
2439 * Allocate and setup the beacon frame.
2440 *
2441 * Stop any previous beacon DMA. This may be
2442 * necessary, for example, when an ibss merge
2443 * causes reconfiguration; we may be called
2444 * with beacon transmission active.
2445 */
2446 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002447
Jouni Malinenc52f33d2009-03-03 19:23:29 +02002448 error = ath_beacon_alloc(aphy, vif);
Sujith25549352009-03-03 10:16:57 +05302449 if (error != 0) {
2450 mutex_unlock(&sc->mutex);
Sujith1f7d6cb2009-01-27 10:55:54 +05302451 return error;
Sujith25549352009-03-03 10:16:57 +05302452 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002453
Jouni Malinen2c3db3d2009-03-03 19:23:26 +02002454 ath_beacon_config(sc, vif);
Sujith1f7d6cb2009-01-27 10:55:54 +05302455 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002456 }
2457
2458 /* Check for WLAN_CAPABILITY_PRIVACY ? */
Colin McCabed97809d2008-12-01 13:38:55 -08002459 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002460 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2461 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2462 ath9k_hw_keysetmac(sc->sc_ah,
2463 (u16)i,
Sujith17d79042009-02-09 13:27:03 +05302464 sc->curbssid);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002465 }
2466
2467 /* Only legacy IBSS for now */
Johannes Berg05c914f2008-09-11 00:01:58 +02002468 if (vif->type == NL80211_IFTYPE_ADHOC)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002469 ath_update_chainmask(sc, 0);
2470
Sujith25549352009-03-03 10:16:57 +05302471 mutex_unlock(&sc->mutex);
2472
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002473 return 0;
2474}
2475
2476#define SUPPORTED_FILTERS \
2477 (FIF_PROMISC_IN_BSS | \
2478 FIF_ALLMULTI | \
2479 FIF_CONTROL | \
2480 FIF_OTHER_BSS | \
2481 FIF_BCN_PRBRESP_PROMISC | \
2482 FIF_FCSFAIL)
2483
Sujith7dcfdcd2008-08-11 14:03:13 +05302484/* FIXME: sc->sc_full_reset ? */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002485static void ath9k_configure_filter(struct ieee80211_hw *hw,
2486 unsigned int changed_flags,
2487 unsigned int *total_flags,
2488 int mc_count,
2489 struct dev_mc_list *mclist)
2490{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002491 struct ath_wiphy *aphy = hw->priv;
2492 struct ath_softc *sc = aphy->sc;
Sujith7dcfdcd2008-08-11 14:03:13 +05302493 u32 rfilt;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002494
2495 changed_flags &= SUPPORTED_FILTERS;
2496 *total_flags &= SUPPORTED_FILTERS;
2497
Sujithb77f4832008-12-07 21:44:03 +05302498 sc->rx.rxfilter = *total_flags;
Sujith7dcfdcd2008-08-11 14:03:13 +05302499 rfilt = ath_calcrxfilter(sc);
2500 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2501
Sujithb77f4832008-12-07 21:44:03 +05302502 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002503}
2504
2505static void ath9k_sta_notify(struct ieee80211_hw *hw,
2506 struct ieee80211_vif *vif,
2507 enum sta_notify_cmd cmd,
Johannes Berg17741cd2008-09-11 00:02:02 +02002508 struct ieee80211_sta *sta)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002509{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002510 struct ath_wiphy *aphy = hw->priv;
2511 struct ath_softc *sc = aphy->sc;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002512
2513 switch (cmd) {
2514 case STA_NOTIFY_ADD:
Sujith5640b082008-10-29 10:16:06 +05302515 ath_node_attach(sc, sta);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002516 break;
2517 case STA_NOTIFY_REMOVE:
Sujithb5aa9bf2008-10-29 10:13:31 +05302518 ath_node_detach(sc, sta);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002519 break;
2520 default:
2521 break;
2522 }
2523}
2524
Sujith141b38b2009-02-04 08:10:07 +05302525static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002526 const struct ieee80211_tx_queue_params *params)
2527{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002528 struct ath_wiphy *aphy = hw->priv;
2529 struct ath_softc *sc = aphy->sc;
Sujithea9880f2008-08-07 10:53:10 +05302530 struct ath9k_tx_queue_info qi;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002531 int ret = 0, qnum;
2532
2533 if (queue >= WME_NUM_AC)
2534 return 0;
2535
Sujith141b38b2009-02-04 08:10:07 +05302536 mutex_lock(&sc->mutex);
2537
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002538 qi.tqi_aifs = params->aifs;
2539 qi.tqi_cwmin = params->cw_min;
2540 qi.tqi_cwmax = params->cw_max;
2541 qi.tqi_burstTime = params->txop;
2542 qnum = ath_get_hal_qnum(queue, sc);
2543
2544 DPRINTF(sc, ATH_DBG_CONFIG,
Sujith04bd4632008-11-28 22:18:05 +05302545 "Configure tx [queue/halq] [%d/%d], "
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002546 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
Sujith04bd4632008-11-28 22:18:05 +05302547 queue, qnum, params->aifs, params->cw_min,
2548 params->cw_max, params->txop);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002549
2550 ret = ath_txq_update(sc, qnum, &qi);
2551 if (ret)
Sujith04bd4632008-11-28 22:18:05 +05302552 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002553
Sujith141b38b2009-02-04 08:10:07 +05302554 mutex_unlock(&sc->mutex);
2555
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002556 return ret;
2557}
2558
2559static int ath9k_set_key(struct ieee80211_hw *hw,
2560 enum set_key_cmd cmd,
Johannes Bergdc822b52008-12-29 12:55:09 +01002561 struct ieee80211_vif *vif,
2562 struct ieee80211_sta *sta,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002563 struct ieee80211_key_conf *key)
2564{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002565 struct ath_wiphy *aphy = hw->priv;
2566 struct ath_softc *sc = aphy->sc;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002567 int ret = 0;
2568
Jouni Malinenb3bd89c2009-02-24 13:42:01 +02002569 if (modparam_nohwcrypt)
2570 return -ENOSPC;
2571
Sujith141b38b2009-02-04 08:10:07 +05302572 mutex_lock(&sc->mutex);
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05302573 ath9k_ps_wakeup(sc);
Sujith04bd4632008-11-28 22:18:05 +05302574 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002575
2576 switch (cmd) {
2577 case SET_KEY:
Jouni Malinen3f53dd62009-02-26 11:18:46 +02002578 ret = ath_key_config(sc, vif, sta, key);
Jouni Malinen6ace2892008-12-17 13:32:17 +02002579 if (ret >= 0) {
2580 key->hw_key_idx = ret;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002581 /* push IV and Michael MIC generation to stack */
2582 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
Senthil Balasubramanian1b961752008-09-01 19:45:21 +05302583 if (key->alg == ALG_TKIP)
2584 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
Jouni Malinen0ced0e12009-01-08 13:32:13 +02002585 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2586 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
Jouni Malinen6ace2892008-12-17 13:32:17 +02002587 ret = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002588 }
2589 break;
2590 case DISABLE_KEY:
2591 ath_key_delete(sc, key);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002592 break;
2593 default:
2594 ret = -EINVAL;
2595 }
2596
Vivek Natarajan3cbb5dd2009-01-20 11:17:08 +05302597 ath9k_ps_restore(sc);
Sujith141b38b2009-02-04 08:10:07 +05302598 mutex_unlock(&sc->mutex);
2599
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002600 return ret;
2601}
2602
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002603static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2604 struct ieee80211_vif *vif,
2605 struct ieee80211_bss_conf *bss_conf,
2606 u32 changed)
2607{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002608 struct ath_wiphy *aphy = hw->priv;
2609 struct ath_softc *sc = aphy->sc;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002610
Sujith141b38b2009-02-04 08:10:07 +05302611 mutex_lock(&sc->mutex);
2612
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002613 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
Sujith04bd4632008-11-28 22:18:05 +05302614 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002615 bss_conf->use_short_preamble);
2616 if (bss_conf->use_short_preamble)
Sujith672840a2008-08-11 14:05:08 +05302617 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002618 else
Sujith672840a2008-08-11 14:05:08 +05302619 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002620 }
2621
2622 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
Sujith04bd4632008-11-28 22:18:05 +05302623 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002624 bss_conf->use_cts_prot);
2625 if (bss_conf->use_cts_prot &&
2626 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
Sujith672840a2008-08-11 14:05:08 +05302627 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002628 else
Sujith672840a2008-08-11 14:05:08 +05302629 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002630 }
2631
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002632 if (changed & BSS_CHANGED_ASSOC) {
Sujith04bd4632008-11-28 22:18:05 +05302633 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002634 bss_conf->assoc);
Sujith5640b082008-10-29 10:16:06 +05302635 ath9k_bss_assoc_info(sc, vif, bss_conf);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002636 }
Sujith141b38b2009-02-04 08:10:07 +05302637
2638 mutex_unlock(&sc->mutex);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002639}
2640
2641static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2642{
2643 u64 tsf;
Jouni Malinenbce048d2009-03-03 19:23:28 +02002644 struct ath_wiphy *aphy = hw->priv;
2645 struct ath_softc *sc = aphy->sc;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002646
Sujith141b38b2009-02-04 08:10:07 +05302647 mutex_lock(&sc->mutex);
2648 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2649 mutex_unlock(&sc->mutex);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002650
2651 return tsf;
2652}
2653
Alina Friedrichsen3b5d6652009-01-24 07:09:59 +01002654static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2655{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002656 struct ath_wiphy *aphy = hw->priv;
2657 struct ath_softc *sc = aphy->sc;
Alina Friedrichsen3b5d6652009-01-24 07:09:59 +01002658
Sujith141b38b2009-02-04 08:10:07 +05302659 mutex_lock(&sc->mutex);
2660 ath9k_hw_settsf64(sc->sc_ah, tsf);
2661 mutex_unlock(&sc->mutex);
Alina Friedrichsen3b5d6652009-01-24 07:09:59 +01002662}
2663
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002664static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2665{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002666 struct ath_wiphy *aphy = hw->priv;
2667 struct ath_softc *sc = aphy->sc;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002668
Sujith141b38b2009-02-04 08:10:07 +05302669 mutex_lock(&sc->mutex);
2670 ath9k_hw_reset_tsf(sc->sc_ah);
2671 mutex_unlock(&sc->mutex);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002672}
2673
2674static int ath9k_ampdu_action(struct ieee80211_hw *hw,
Sujith141b38b2009-02-04 08:10:07 +05302675 enum ieee80211_ampdu_mlme_action action,
2676 struct ieee80211_sta *sta,
2677 u16 tid, u16 *ssn)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002678{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002679 struct ath_wiphy *aphy = hw->priv;
2680 struct ath_softc *sc = aphy->sc;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002681 int ret = 0;
2682
2683 switch (action) {
2684 case IEEE80211_AMPDU_RX_START:
Sujithdca3edb2008-10-29 10:19:01 +05302685 if (!(sc->sc_flags & SC_OP_RXAGGR))
2686 ret = -ENOTSUPP;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002687 break;
2688 case IEEE80211_AMPDU_RX_STOP:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002689 break;
2690 case IEEE80211_AMPDU_TX_START:
Sujithb5aa9bf2008-10-29 10:13:31 +05302691 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002692 if (ret < 0)
2693 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05302694 "Unable to start TX aggregation\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002695 else
Johannes Berg17741cd2008-09-11 00:02:02 +02002696 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002697 break;
2698 case IEEE80211_AMPDU_TX_STOP:
Sujithb5aa9bf2008-10-29 10:13:31 +05302699 ret = ath_tx_aggr_stop(sc, sta, tid);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002700 if (ret < 0)
2701 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05302702 "Unable to stop TX aggregation\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002703
Johannes Berg17741cd2008-09-11 00:02:02 +02002704 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002705 break;
Sujith8469cde2008-10-29 10:19:28 +05302706 case IEEE80211_AMPDU_TX_RESUME:
2707 ath_tx_aggr_resume(sc, sta, tid);
2708 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002709 default:
Sujith04bd4632008-11-28 22:18:05 +05302710 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002711 }
2712
2713 return ret;
2714}
2715
Sujith0c98de62009-03-03 10:16:45 +05302716static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2717{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002718 struct ath_wiphy *aphy = hw->priv;
2719 struct ath_softc *sc = aphy->sc;
Sujith0c98de62009-03-03 10:16:45 +05302720
2721 mutex_lock(&sc->mutex);
2722 sc->sc_flags |= SC_OP_SCANNING;
2723 mutex_unlock(&sc->mutex);
2724}
2725
2726static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2727{
Jouni Malinenbce048d2009-03-03 19:23:28 +02002728 struct ath_wiphy *aphy = hw->priv;
2729 struct ath_softc *sc = aphy->sc;
Sujith0c98de62009-03-03 10:16:45 +05302730
2731 mutex_lock(&sc->mutex);
2732 sc->sc_flags &= ~SC_OP_SCANNING;
2733 mutex_unlock(&sc->mutex);
2734}
2735
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002736struct ieee80211_ops ath9k_ops = {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002737 .tx = ath9k_tx,
2738 .start = ath9k_start,
2739 .stop = ath9k_stop,
2740 .add_interface = ath9k_add_interface,
2741 .remove_interface = ath9k_remove_interface,
2742 .config = ath9k_config,
2743 .config_interface = ath9k_config_interface,
2744 .configure_filter = ath9k_configure_filter,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002745 .sta_notify = ath9k_sta_notify,
2746 .conf_tx = ath9k_conf_tx,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002747 .bss_info_changed = ath9k_bss_info_changed,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002748 .set_key = ath9k_set_key,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002749 .get_tsf = ath9k_get_tsf,
Alina Friedrichsen3b5d6652009-01-24 07:09:59 +01002750 .set_tsf = ath9k_set_tsf,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002751 .reset_tsf = ath9k_reset_tsf,
Johannes Berg4233df62008-10-13 13:35:05 +02002752 .ampdu_action = ath9k_ampdu_action,
Sujith0c98de62009-03-03 10:16:45 +05302753 .sw_scan_start = ath9k_sw_scan_start,
2754 .sw_scan_complete = ath9k_sw_scan_complete,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002755};
2756
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +01002757static struct {
2758 u32 version;
2759 const char * name;
2760} ath_mac_bb_names[] = {
2761 { AR_SREV_VERSION_5416_PCI, "5416" },
2762 { AR_SREV_VERSION_5416_PCIE, "5418" },
2763 { AR_SREV_VERSION_9100, "9100" },
2764 { AR_SREV_VERSION_9160, "9160" },
2765 { AR_SREV_VERSION_9280, "9280" },
2766 { AR_SREV_VERSION_9285, "9285" }
2767};
2768
2769static struct {
2770 u16 version;
2771 const char * name;
2772} ath_rf_names[] = {
2773 { 0, "5133" },
2774 { AR_RAD5133_SREV_MAJOR, "5133" },
2775 { AR_RAD5122_SREV_MAJOR, "5122" },
2776 { AR_RAD2133_SREV_MAJOR, "2133" },
2777 { AR_RAD2122_SREV_MAJOR, "2122" }
2778};
2779
2780/*
2781 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2782 */
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002783const char *
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +01002784ath_mac_bb_name(u32 mac_bb_version)
2785{
2786 int i;
2787
2788 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2789 if (ath_mac_bb_names[i].version == mac_bb_version) {
2790 return ath_mac_bb_names[i].name;
2791 }
2792 }
2793
2794 return "????";
2795}
2796
2797/*
2798 * Return the RF name. "????" is returned if the RF is unknown.
2799 */
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002800const char *
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +01002801ath_rf_name(u16 rf_version)
2802{
2803 int i;
2804
2805 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2806 if (ath_rf_names[i].version == rf_version) {
2807 return ath_rf_names[i].name;
2808 }
2809 }
2810
2811 return "????";
2812}
2813
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002814static int __init ath9k_init(void)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002815{
Vasanthakumar Thiagarajanca8a8562008-12-16 12:37:38 +05302816 int error;
2817
Vasanthakumar Thiagarajanca8a8562008-12-16 12:37:38 +05302818 /* Register rate control algorithm */
2819 error = ath_rate_control_register();
2820 if (error != 0) {
2821 printk(KERN_ERR
Luis R. Rodriguezb51bb3c2009-01-26 07:30:03 -08002822 "ath9k: Unable to register rate control "
2823 "algorithm: %d\n",
Vasanthakumar Thiagarajanca8a8562008-12-16 12:37:38 +05302824 error);
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002825 goto err_out;
Vasanthakumar Thiagarajanca8a8562008-12-16 12:37:38 +05302826 }
2827
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002828 error = ath_pci_init();
2829 if (error < 0) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002830 printk(KERN_ERR
Luis R. Rodriguezb51bb3c2009-01-26 07:30:03 -08002831 "ath9k: No PCI devices found, driver not installed.\n");
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002832 error = -ENODEV;
2833 goto err_rate_unregister;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002834 }
2835
Gabor Juhos09329d32009-01-14 20:17:07 +01002836 error = ath_ahb_init();
2837 if (error < 0) {
2838 error = -ENODEV;
2839 goto err_pci_exit;
2840 }
2841
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002842 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002843
Gabor Juhos09329d32009-01-14 20:17:07 +01002844 err_pci_exit:
2845 ath_pci_exit();
2846
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002847 err_rate_unregister:
Vasanthakumar Thiagarajanca8a8562008-12-16 12:37:38 +05302848 ath_rate_control_unregister();
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002849 err_out:
2850 return error;
2851}
2852module_init(ath9k_init);
2853
2854static void __exit ath9k_exit(void)
2855{
Gabor Juhos09329d32009-01-14 20:17:07 +01002856 ath_ahb_exit();
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002857 ath_pci_exit();
2858 ath_rate_control_unregister();
Sujith04bd4632008-11-28 22:18:05 +05302859 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002860}
Gabor Juhos6baff7f2009-01-14 20:17:06 +01002861module_exit(ath9k_exit);