Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Emilio López |
| 3 | * |
| 4 | * Emilio López <emilio@elopez.com.ar> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/clk-provider.h> |
| 18 | #include <linux/clkdev.h> |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> |
| 21 | |
| 22 | #include "clk-factors.h" |
| 23 | |
| 24 | static DEFINE_SPINLOCK(clk_lock); |
| 25 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 26 | /* Maximum number of parents our clocks have */ |
| 27 | #define SUNXI_MAX_PARENTS 5 |
| 28 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 29 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 30 | * sun4i_osc_clk_setup() - Setup function for gatable oscillator |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 31 | */ |
| 32 | |
| 33 | #define SUNXI_OSC24M_GATE 0 |
| 34 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 35 | static void __init sun4i_osc_clk_setup(struct device_node *node) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 36 | { |
| 37 | struct clk *clk; |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 38 | struct clk_fixed_rate *fixed; |
| 39 | struct clk_gate *gate; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 40 | const char *clk_name = node->name; |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 41 | u32 rate; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 42 | |
Victor N. Ramos Mello | e71c69f | 2013-10-18 20:27:51 -0300 | [diff] [blame] | 43 | if (of_property_read_u32(node, "clock-frequency", &rate)) |
| 44 | return; |
| 45 | |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 46 | /* allocate fixed-rate and gate clock structs */ |
| 47 | fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); |
| 48 | if (!fixed) |
| 49 | return; |
| 50 | gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
Victor N. Ramos Mello | e71c69f | 2013-10-18 20:27:51 -0300 | [diff] [blame] | 51 | if (!gate) |
| 52 | goto err_free_fixed; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 53 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 54 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 55 | |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 56 | /* set up gate and fixed rate properties */ |
| 57 | gate->reg = of_iomap(node, 0); |
| 58 | gate->bit_idx = SUNXI_OSC24M_GATE; |
| 59 | gate->lock = &clk_lock; |
| 60 | fixed->fixed_rate = rate; |
| 61 | |
| 62 | clk = clk_register_composite(NULL, clk_name, |
| 63 | NULL, 0, |
| 64 | NULL, NULL, |
| 65 | &fixed->hw, &clk_fixed_rate_ops, |
| 66 | &gate->hw, &clk_gate_ops, |
| 67 | CLK_IS_ROOT); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 68 | |
Victor N. Ramos Mello | e71c69f | 2013-10-18 20:27:51 -0300 | [diff] [blame] | 69 | if (IS_ERR(clk)) |
| 70 | goto err_free_gate; |
| 71 | |
| 72 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 73 | clk_register_clkdev(clk, clk_name, NULL); |
| 74 | |
| 75 | return; |
| 76 | |
| 77 | err_free_gate: |
| 78 | kfree(gate); |
| 79 | err_free_fixed: |
| 80 | kfree(fixed); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 81 | } |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 82 | CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 83 | |
| 84 | |
| 85 | |
| 86 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 87 | * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 88 | * PLL1 rate is calculated as follows |
| 89 | * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); |
| 90 | * parent_rate is always 24Mhz |
| 91 | */ |
| 92 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 93 | static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 94 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 95 | { |
| 96 | u8 div; |
| 97 | |
| 98 | /* Normalize value to a 6M multiple */ |
| 99 | div = *freq / 6000000; |
| 100 | *freq = 6000000 * div; |
| 101 | |
| 102 | /* we were called to round the frequency, we can now return */ |
| 103 | if (n == NULL) |
| 104 | return; |
| 105 | |
| 106 | /* m is always zero for pll1 */ |
| 107 | *m = 0; |
| 108 | |
| 109 | /* k is 1 only on these cases */ |
| 110 | if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) |
| 111 | *k = 1; |
| 112 | else |
| 113 | *k = 0; |
| 114 | |
| 115 | /* p will be 3 for divs under 10 */ |
| 116 | if (div < 10) |
| 117 | *p = 3; |
| 118 | |
| 119 | /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ |
| 120 | else if (div < 20 || (div < 32 && (div & 1))) |
| 121 | *p = 2; |
| 122 | |
| 123 | /* p will be 1 for even divs under 32, divs under 40 and odd pairs |
| 124 | * of divs between 40-62 */ |
| 125 | else if (div < 40 || (div < 64 && (div & 2))) |
| 126 | *p = 1; |
| 127 | |
| 128 | /* any other entries have p = 0 */ |
| 129 | else |
| 130 | *p = 0; |
| 131 | |
| 132 | /* calculate a suitable n based on k and p */ |
| 133 | div <<= *p; |
| 134 | div /= (*k + 1); |
| 135 | *n = div / 4; |
| 136 | } |
| 137 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 138 | /** |
| 139 | * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1 |
| 140 | * PLL1 rate is calculated as follows |
| 141 | * rate = parent_rate * (n + 1) * (k + 1) / (m + 1); |
| 142 | * parent_rate should always be 24MHz |
| 143 | */ |
| 144 | static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, |
| 145 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 146 | { |
| 147 | /* |
| 148 | * We can operate only on MHz, this will make our life easier |
| 149 | * later. |
| 150 | */ |
| 151 | u32 freq_mhz = *freq / 1000000; |
| 152 | u32 parent_freq_mhz = parent_rate / 1000000; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 153 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 154 | /* |
| 155 | * Round down the frequency to the closest multiple of either |
| 156 | * 6 or 16 |
| 157 | */ |
| 158 | u32 round_freq_6 = round_down(freq_mhz, 6); |
| 159 | u32 round_freq_16 = round_down(freq_mhz, 16); |
| 160 | |
| 161 | if (round_freq_6 > round_freq_16) |
| 162 | freq_mhz = round_freq_6; |
| 163 | else |
| 164 | freq_mhz = round_freq_16; |
| 165 | |
| 166 | *freq = freq_mhz * 1000000; |
| 167 | |
| 168 | /* |
| 169 | * If the factors pointer are null, we were just called to |
| 170 | * round down the frequency. |
| 171 | * Exit. |
| 172 | */ |
| 173 | if (n == NULL) |
| 174 | return; |
| 175 | |
| 176 | /* If the frequency is a multiple of 32 MHz, k is always 3 */ |
| 177 | if (!(freq_mhz % 32)) |
| 178 | *k = 3; |
| 179 | /* If the frequency is a multiple of 9 MHz, k is always 2 */ |
| 180 | else if (!(freq_mhz % 9)) |
| 181 | *k = 2; |
| 182 | /* If the frequency is a multiple of 8 MHz, k is always 1 */ |
| 183 | else if (!(freq_mhz % 8)) |
| 184 | *k = 1; |
| 185 | /* Otherwise, we don't use the k factor */ |
| 186 | else |
| 187 | *k = 0; |
| 188 | |
| 189 | /* |
| 190 | * If the frequency is a multiple of 2 but not a multiple of |
| 191 | * 3, m is 3. This is the first time we use 6 here, yet we |
| 192 | * will use it on several other places. |
| 193 | * We use this number because it's the lowest frequency we can |
| 194 | * generate (with n = 0, k = 0, m = 3), so every other frequency |
| 195 | * somehow relates to this frequency. |
| 196 | */ |
| 197 | if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4) |
| 198 | *m = 2; |
| 199 | /* |
| 200 | * If the frequency is a multiple of 6MHz, but the factor is |
| 201 | * odd, m will be 3 |
| 202 | */ |
| 203 | else if ((freq_mhz / 6) & 1) |
| 204 | *m = 3; |
| 205 | /* Otherwise, we end up with m = 1 */ |
| 206 | else |
| 207 | *m = 1; |
| 208 | |
| 209 | /* Calculate n thanks to the above factors we already got */ |
| 210 | *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1; |
| 211 | |
| 212 | /* |
| 213 | * If n end up being outbound, and that we can still decrease |
| 214 | * m, do it. |
| 215 | */ |
| 216 | if ((*n + 1) > 31 && (*m + 1) > 1) { |
| 217 | *n = (*n + 1) / 2 - 1; |
| 218 | *m = (*m + 1) / 2 - 1; |
| 219 | } |
| 220 | } |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 221 | |
| 222 | /** |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 223 | * sun4i_get_pll5_factors() - calculates n, k factors for PLL5 |
| 224 | * PLL5 rate is calculated as follows |
| 225 | * rate = parent_rate * n * (k + 1) |
| 226 | * parent_rate is always 24Mhz |
| 227 | */ |
| 228 | |
| 229 | static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate, |
| 230 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 231 | { |
| 232 | u8 div; |
| 233 | |
| 234 | /* Normalize value to a parent_rate multiple (24M) */ |
| 235 | div = *freq / parent_rate; |
| 236 | *freq = parent_rate * div; |
| 237 | |
| 238 | /* we were called to round the frequency, we can now return */ |
| 239 | if (n == NULL) |
| 240 | return; |
| 241 | |
| 242 | if (div < 31) |
| 243 | *k = 0; |
| 244 | else if (div / 2 < 31) |
| 245 | *k = 1; |
| 246 | else if (div / 3 < 31) |
| 247 | *k = 2; |
| 248 | else |
| 249 | *k = 3; |
| 250 | |
| 251 | *n = DIV_ROUND_UP(div, (*k+1)); |
| 252 | } |
| 253 | |
| 254 | |
| 255 | |
| 256 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 257 | * sun4i_get_apb1_factors() - calculates m, p factors for APB1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 258 | * APB1 rate is calculated as follows |
| 259 | * rate = (parent_rate >> p) / (m + 1); |
| 260 | */ |
| 261 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 262 | static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 263 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 264 | { |
| 265 | u8 calcm, calcp; |
| 266 | |
| 267 | if (parent_rate < *freq) |
| 268 | *freq = parent_rate; |
| 269 | |
| 270 | parent_rate = (parent_rate + (*freq - 1)) / *freq; |
| 271 | |
| 272 | /* Invalid rate! */ |
| 273 | if (parent_rate > 32) |
| 274 | return; |
| 275 | |
| 276 | if (parent_rate <= 4) |
| 277 | calcp = 0; |
| 278 | else if (parent_rate <= 8) |
| 279 | calcp = 1; |
| 280 | else if (parent_rate <= 16) |
| 281 | calcp = 2; |
| 282 | else |
| 283 | calcp = 3; |
| 284 | |
| 285 | calcm = (parent_rate >> calcp) - 1; |
| 286 | |
| 287 | *freq = (parent_rate >> calcp) / (calcm + 1); |
| 288 | |
| 289 | /* we were called to round the frequency, we can now return */ |
| 290 | if (n == NULL) |
| 291 | return; |
| 292 | |
| 293 | *m = calcm; |
| 294 | *p = calcp; |
| 295 | } |
| 296 | |
| 297 | |
| 298 | |
| 299 | /** |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 300 | * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks |
| 301 | * MMC rate is calculated as follows |
| 302 | * rate = (parent_rate >> p) / (m + 1); |
| 303 | */ |
| 304 | |
| 305 | static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate, |
| 306 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 307 | { |
| 308 | u8 div, calcm, calcp; |
| 309 | |
| 310 | /* These clocks can only divide, so we will never be able to achieve |
| 311 | * frequencies higher than the parent frequency */ |
| 312 | if (*freq > parent_rate) |
| 313 | *freq = parent_rate; |
| 314 | |
| 315 | div = parent_rate / *freq; |
| 316 | |
| 317 | if (div < 16) |
| 318 | calcp = 0; |
| 319 | else if (div / 2 < 16) |
| 320 | calcp = 1; |
| 321 | else if (div / 4 < 16) |
| 322 | calcp = 2; |
| 323 | else |
| 324 | calcp = 3; |
| 325 | |
| 326 | calcm = DIV_ROUND_UP(div, 1 << calcp); |
| 327 | |
| 328 | *freq = (parent_rate >> calcp) / calcm; |
| 329 | |
| 330 | /* we were called to round the frequency, we can now return */ |
| 331 | if (n == NULL) |
| 332 | return; |
| 333 | |
| 334 | *m = calcm - 1; |
| 335 | *p = calcp; |
| 336 | } |
| 337 | |
| 338 | |
| 339 | |
| 340 | /** |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 341 | * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B |
| 342 | * CLK_OUT rate is calculated as follows |
| 343 | * rate = (parent_rate >> p) / (m + 1); |
| 344 | */ |
| 345 | |
| 346 | static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, |
| 347 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 348 | { |
| 349 | u8 div, calcm, calcp; |
| 350 | |
| 351 | /* These clocks can only divide, so we will never be able to achieve |
| 352 | * frequencies higher than the parent frequency */ |
| 353 | if (*freq > parent_rate) |
| 354 | *freq = parent_rate; |
| 355 | |
| 356 | div = parent_rate / *freq; |
| 357 | |
| 358 | if (div < 32) |
| 359 | calcp = 0; |
| 360 | else if (div / 2 < 32) |
| 361 | calcp = 1; |
| 362 | else if (div / 4 < 32) |
| 363 | calcp = 2; |
| 364 | else |
| 365 | calcp = 3; |
| 366 | |
| 367 | calcm = DIV_ROUND_UP(div, 1 << calcp); |
| 368 | |
| 369 | *freq = (parent_rate >> calcp) / calcm; |
| 370 | |
| 371 | /* we were called to round the frequency, we can now return */ |
| 372 | if (n == NULL) |
| 373 | return; |
| 374 | |
| 375 | *m = calcm - 1; |
| 376 | *p = calcp; |
| 377 | } |
| 378 | |
| 379 | |
| 380 | |
| 381 | /** |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 382 | * sunxi_factors_clk_setup() - Setup function for factor clocks |
| 383 | */ |
| 384 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 385 | #define SUNXI_FACTORS_MUX_MASK 0x3 |
| 386 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 387 | struct factors_data { |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 388 | int enable; |
| 389 | int mux; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 390 | struct clk_factors_config *table; |
| 391 | void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 392 | const char *name; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 393 | }; |
| 394 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 395 | static struct clk_factors_config sun4i_pll1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 396 | .nshift = 8, |
| 397 | .nwidth = 5, |
| 398 | .kshift = 4, |
| 399 | .kwidth = 2, |
| 400 | .mshift = 0, |
| 401 | .mwidth = 2, |
| 402 | .pshift = 16, |
| 403 | .pwidth = 2, |
| 404 | }; |
| 405 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 406 | static struct clk_factors_config sun6i_a31_pll1_config = { |
| 407 | .nshift = 8, |
| 408 | .nwidth = 5, |
| 409 | .kshift = 4, |
| 410 | .kwidth = 2, |
| 411 | .mshift = 0, |
| 412 | .mwidth = 2, |
| 413 | }; |
| 414 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 415 | static struct clk_factors_config sun4i_pll5_config = { |
| 416 | .nshift = 8, |
| 417 | .nwidth = 5, |
| 418 | .kshift = 4, |
| 419 | .kwidth = 2, |
| 420 | }; |
| 421 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 422 | static struct clk_factors_config sun4i_apb1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 423 | .mshift = 0, |
| 424 | .mwidth = 5, |
| 425 | .pshift = 16, |
| 426 | .pwidth = 2, |
| 427 | }; |
| 428 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 429 | /* user manual says "n" but it's really "p" */ |
| 430 | static struct clk_factors_config sun4i_mod0_config = { |
| 431 | .mshift = 0, |
| 432 | .mwidth = 4, |
| 433 | .pshift = 16, |
| 434 | .pwidth = 2, |
| 435 | }; |
| 436 | |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 437 | /* user manual says "n" but it's really "p" */ |
| 438 | static struct clk_factors_config sun7i_a20_out_config = { |
| 439 | .mshift = 8, |
| 440 | .mwidth = 5, |
| 441 | .pshift = 20, |
| 442 | .pwidth = 2, |
| 443 | }; |
| 444 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 445 | static const struct factors_data sun4i_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 446 | .enable = 31, |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 447 | .table = &sun4i_pll1_config, |
| 448 | .getter = sun4i_get_pll1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 449 | }; |
| 450 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 451 | static const struct factors_data sun6i_a31_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 452 | .enable = 31, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 453 | .table = &sun6i_a31_pll1_config, |
| 454 | .getter = sun6i_a31_get_pll1_factors, |
| 455 | }; |
| 456 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 457 | static const struct factors_data sun4i_pll5_data __initconst = { |
| 458 | .enable = 31, |
| 459 | .table = &sun4i_pll5_config, |
| 460 | .getter = sun4i_get_pll5_factors, |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 461 | .name = "pll5", |
| 462 | }; |
| 463 | |
| 464 | static const struct factors_data sun4i_pll6_data __initconst = { |
| 465 | .enable = 31, |
| 466 | .table = &sun4i_pll5_config, |
| 467 | .getter = sun4i_get_pll5_factors, |
| 468 | .name = "pll6", |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 469 | }; |
| 470 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 471 | static const struct factors_data sun4i_apb1_data __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 472 | .table = &sun4i_apb1_config, |
| 473 | .getter = sun4i_get_apb1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 474 | }; |
| 475 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 476 | static const struct factors_data sun4i_mod0_data __initconst = { |
| 477 | .enable = 31, |
| 478 | .mux = 24, |
| 479 | .table = &sun4i_mod0_config, |
| 480 | .getter = sun4i_get_mod0_factors, |
| 481 | }; |
| 482 | |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 483 | static const struct factors_data sun7i_a20_out_data __initconst = { |
| 484 | .enable = 31, |
| 485 | .mux = 24, |
| 486 | .table = &sun7i_a20_out_config, |
| 487 | .getter = sun7i_a20_get_out_factors, |
| 488 | }; |
| 489 | |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 490 | static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, |
| 491 | const struct factors_data *data) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 492 | { |
| 493 | struct clk *clk; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 494 | struct clk_factors *factors; |
| 495 | struct clk_gate *gate = NULL; |
| 496 | struct clk_mux *mux = NULL; |
| 497 | struct clk_hw *gate_hw = NULL; |
| 498 | struct clk_hw *mux_hw = NULL; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 499 | const char *clk_name = node->name; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 500 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 501 | void *reg; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 502 | int i = 0; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 503 | |
| 504 | reg = of_iomap(node, 0); |
| 505 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 506 | /* if we have a mux, we will have >1 parents */ |
| 507 | while (i < SUNXI_MAX_PARENTS && |
| 508 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
| 509 | i++; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 510 | |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 511 | /* |
| 512 | * some factor clocks, such as pll5 and pll6, may have multiple |
| 513 | * outputs, and have their name designated in factors_data |
| 514 | */ |
| 515 | if (data->name) |
| 516 | clk_name = data->name; |
| 517 | else |
| 518 | of_property_read_string(node, "clock-output-names", &clk_name); |
Emilio López | 76192dc | 2013-12-23 00:32:40 -0300 | [diff] [blame] | 519 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 520 | factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); |
| 521 | if (!factors) |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 522 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 523 | |
| 524 | /* Add a gate if this factor clock can be gated */ |
| 525 | if (data->enable) { |
| 526 | gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
| 527 | if (!gate) { |
| 528 | kfree(factors); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 529 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | /* set up gate properties */ |
| 533 | gate->reg = reg; |
| 534 | gate->bit_idx = data->enable; |
| 535 | gate->lock = &clk_lock; |
| 536 | gate_hw = &gate->hw; |
| 537 | } |
| 538 | |
| 539 | /* Add a mux if this factor clock can be muxed */ |
| 540 | if (data->mux) { |
| 541 | mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); |
| 542 | if (!mux) { |
| 543 | kfree(factors); |
| 544 | kfree(gate); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 545 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 546 | } |
| 547 | |
| 548 | /* set up gate properties */ |
| 549 | mux->reg = reg; |
| 550 | mux->shift = data->mux; |
| 551 | mux->mask = SUNXI_FACTORS_MUX_MASK; |
| 552 | mux->lock = &clk_lock; |
| 553 | mux_hw = &mux->hw; |
| 554 | } |
| 555 | |
| 556 | /* set up factors properties */ |
| 557 | factors->reg = reg; |
| 558 | factors->config = data->table; |
| 559 | factors->get_factors = data->getter; |
| 560 | factors->lock = &clk_lock; |
| 561 | |
| 562 | clk = clk_register_composite(NULL, clk_name, |
| 563 | parents, i, |
| 564 | mux_hw, &clk_mux_ops, |
| 565 | &factors->hw, &clk_factors_ops, |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 566 | gate_hw, &clk_gate_ops, 0); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 567 | |
Axel Lin | ee85e9b | 2013-07-12 16:15:15 +0800 | [diff] [blame] | 568 | if (!IS_ERR(clk)) { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 569 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 570 | clk_register_clkdev(clk, clk_name, NULL); |
| 571 | } |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 572 | |
| 573 | return clk; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 574 | } |
| 575 | |
| 576 | |
| 577 | |
| 578 | /** |
| 579 | * sunxi_mux_clk_setup() - Setup function for muxes |
| 580 | */ |
| 581 | |
| 582 | #define SUNXI_MUX_GATE_WIDTH 2 |
| 583 | |
| 584 | struct mux_data { |
| 585 | u8 shift; |
| 586 | }; |
| 587 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 588 | static const struct mux_data sun4i_cpu_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 589 | .shift = 16, |
| 590 | }; |
| 591 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 592 | static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 593 | .shift = 12, |
| 594 | }; |
| 595 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 596 | static const struct mux_data sun4i_apb1_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 597 | .shift = 24, |
| 598 | }; |
| 599 | |
| 600 | static void __init sunxi_mux_clk_setup(struct device_node *node, |
| 601 | struct mux_data *data) |
| 602 | { |
| 603 | struct clk *clk; |
| 604 | const char *clk_name = node->name; |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 605 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 606 | void *reg; |
| 607 | int i = 0; |
| 608 | |
| 609 | reg = of_iomap(node, 0); |
| 610 | |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 611 | while (i < SUNXI_MAX_PARENTS && |
| 612 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 613 | i++; |
| 614 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 615 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 616 | |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 617 | clk = clk_register_mux(NULL, clk_name, parents, i, |
| 618 | CLK_SET_RATE_NO_REPARENT, reg, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 619 | data->shift, SUNXI_MUX_GATE_WIDTH, |
| 620 | 0, &clk_lock); |
| 621 | |
| 622 | if (clk) { |
| 623 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 624 | clk_register_clkdev(clk, clk_name, NULL); |
| 625 | } |
| 626 | } |
| 627 | |
| 628 | |
| 629 | |
| 630 | /** |
| 631 | * sunxi_divider_clk_setup() - Setup function for simple divider clocks |
| 632 | */ |
| 633 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 634 | struct div_data { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 635 | u8 shift; |
| 636 | u8 pow; |
| 637 | u8 width; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 638 | }; |
| 639 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 640 | static const struct div_data sun4i_axi_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 641 | .shift = 0, |
| 642 | .pow = 0, |
| 643 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 644 | }; |
| 645 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 646 | static const struct div_data sun4i_ahb_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 647 | .shift = 4, |
| 648 | .pow = 1, |
| 649 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 650 | }; |
| 651 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 652 | static const struct div_data sun4i_apb0_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 653 | .shift = 8, |
| 654 | .pow = 1, |
| 655 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 656 | }; |
| 657 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 658 | static const struct div_data sun6i_a31_apb2_div_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 659 | .shift = 0, |
| 660 | .pow = 0, |
| 661 | .width = 4, |
| 662 | }; |
| 663 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 664 | static void __init sunxi_divider_clk_setup(struct device_node *node, |
| 665 | struct div_data *data) |
| 666 | { |
| 667 | struct clk *clk; |
| 668 | const char *clk_name = node->name; |
| 669 | const char *clk_parent; |
| 670 | void *reg; |
| 671 | |
| 672 | reg = of_iomap(node, 0); |
| 673 | |
| 674 | clk_parent = of_clk_get_parent_name(node, 0); |
| 675 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 676 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 677 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 678 | clk = clk_register_divider(NULL, clk_name, clk_parent, 0, |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 679 | reg, data->shift, data->width, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 680 | data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, |
| 681 | &clk_lock); |
| 682 | if (clk) { |
| 683 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 684 | clk_register_clkdev(clk, clk_name, NULL); |
| 685 | } |
| 686 | } |
| 687 | |
| 688 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 689 | |
| 690 | /** |
| 691 | * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks |
| 692 | */ |
| 693 | |
| 694 | #define SUNXI_GATES_MAX_SIZE 64 |
| 695 | |
| 696 | struct gates_data { |
| 697 | DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); |
| 698 | }; |
| 699 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 700 | static const struct gates_data sun4i_axi_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 701 | .mask = {1}, |
| 702 | }; |
| 703 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 704 | static const struct gates_data sun4i_ahb_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 705 | .mask = {0x7F77FFF, 0x14FB3F}, |
| 706 | }; |
| 707 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 708 | static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 709 | .mask = {0x147667e7, 0x185915}, |
| 710 | }; |
| 711 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 712 | static const struct gates_data sun5i_a13_ahb_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 713 | .mask = {0x107067e7, 0x185111}, |
| 714 | }; |
| 715 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 716 | static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 717 | .mask = {0xEDFE7F62, 0x794F931}, |
| 718 | }; |
| 719 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 720 | static const struct gates_data sun7i_a20_ahb_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 721 | .mask = { 0x12f77fff, 0x16ff3f }, |
| 722 | }; |
| 723 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 724 | static const struct gates_data sun4i_apb0_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 725 | .mask = {0x4EF}, |
| 726 | }; |
| 727 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 728 | static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 729 | .mask = {0x469}, |
| 730 | }; |
| 731 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 732 | static const struct gates_data sun5i_a13_apb0_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 733 | .mask = {0x61}, |
| 734 | }; |
| 735 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 736 | static const struct gates_data sun7i_a20_apb0_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 737 | .mask = { 0x4ff }, |
| 738 | }; |
| 739 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 740 | static const struct gates_data sun4i_apb1_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 741 | .mask = {0xFF00F7}, |
| 742 | }; |
| 743 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 744 | static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 745 | .mask = {0xf0007}, |
| 746 | }; |
| 747 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 748 | static const struct gates_data sun5i_a13_apb1_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 749 | .mask = {0xa0007}, |
| 750 | }; |
| 751 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 752 | static const struct gates_data sun6i_a31_apb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 753 | .mask = {0x3031}, |
| 754 | }; |
| 755 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 756 | static const struct gates_data sun6i_a31_apb2_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 757 | .mask = {0x3F000F}, |
| 758 | }; |
| 759 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 760 | static const struct gates_data sun7i_a20_apb1_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 761 | .mask = { 0xff80ff }, |
| 762 | }; |
| 763 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 764 | static void __init sunxi_gates_clk_setup(struct device_node *node, |
| 765 | struct gates_data *data) |
| 766 | { |
| 767 | struct clk_onecell_data *clk_data; |
| 768 | const char *clk_parent; |
| 769 | const char *clk_name; |
| 770 | void *reg; |
| 771 | int qty; |
| 772 | int i = 0; |
| 773 | int j = 0; |
| 774 | int ignore; |
| 775 | |
| 776 | reg = of_iomap(node, 0); |
| 777 | |
| 778 | clk_parent = of_clk_get_parent_name(node, 0); |
| 779 | |
| 780 | /* Worst-case size approximation and memory allocation */ |
| 781 | qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE); |
| 782 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 783 | if (!clk_data) |
| 784 | return; |
| 785 | clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); |
| 786 | if (!clk_data->clks) { |
| 787 | kfree(clk_data); |
| 788 | return; |
| 789 | } |
| 790 | |
| 791 | for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) { |
| 792 | of_property_read_string_index(node, "clock-output-names", |
| 793 | j, &clk_name); |
| 794 | |
| 795 | /* No driver claims this clock, but it should remain gated */ |
| 796 | ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0; |
| 797 | |
| 798 | clk_data->clks[i] = clk_register_gate(NULL, clk_name, |
| 799 | clk_parent, ignore, |
| 800 | reg + 4 * (i/32), i % 32, |
| 801 | 0, &clk_lock); |
| 802 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 803 | |
| 804 | j++; |
| 805 | } |
| 806 | |
| 807 | /* Adjust to the real max */ |
| 808 | clk_data->clk_num = i; |
| 809 | |
| 810 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 811 | } |
| 812 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 813 | |
| 814 | |
| 815 | /** |
| 816 | * sunxi_divs_clk_setup() helper data |
| 817 | */ |
| 818 | |
| 819 | #define SUNXI_DIVS_MAX_QTY 2 |
| 820 | #define SUNXI_DIVISOR_WIDTH 2 |
| 821 | |
| 822 | struct divs_data { |
| 823 | const struct factors_data *factors; /* data for the factor clock */ |
| 824 | struct { |
| 825 | u8 fixed; /* is it a fixed divisor? if not... */ |
| 826 | struct clk_div_table *table; /* is it a table based divisor? */ |
| 827 | u8 shift; /* otherwise it's a normal divisor with this shift */ |
| 828 | u8 pow; /* is it power-of-two based? */ |
| 829 | u8 gate; /* is it independently gateable? */ |
| 830 | } div[SUNXI_DIVS_MAX_QTY]; |
| 831 | }; |
| 832 | |
| 833 | static struct clk_div_table pll6_sata_tbl[] = { |
| 834 | { .val = 0, .div = 6, }, |
| 835 | { .val = 1, .div = 12, }, |
| 836 | { .val = 2, .div = 18, }, |
| 837 | { .val = 3, .div = 24, }, |
| 838 | { } /* sentinel */ |
| 839 | }; |
| 840 | |
| 841 | static const struct divs_data pll5_divs_data __initconst = { |
| 842 | .factors = &sun4i_pll5_data, |
| 843 | .div = { |
| 844 | { .shift = 0, .pow = 0, }, /* M, DDR */ |
| 845 | { .shift = 16, .pow = 1, }, /* P, other */ |
| 846 | } |
| 847 | }; |
| 848 | |
| 849 | static const struct divs_data pll6_divs_data __initconst = { |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 850 | .factors = &sun4i_pll6_data, |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 851 | .div = { |
| 852 | { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ |
| 853 | { .fixed = 2 }, /* P, other */ |
| 854 | } |
| 855 | }; |
| 856 | |
| 857 | /** |
| 858 | * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks |
| 859 | * |
| 860 | * These clocks look something like this |
| 861 | * ________________________ |
| 862 | * | ___divisor 1---|----> to consumer |
| 863 | * parent >--| pll___/___divisor 2---|----> to consumer |
| 864 | * | \_______________|____> to consumer |
| 865 | * |________________________| |
| 866 | */ |
| 867 | |
| 868 | static void __init sunxi_divs_clk_setup(struct device_node *node, |
| 869 | struct divs_data *data) |
| 870 | { |
| 871 | struct clk_onecell_data *clk_data; |
Chen-Yu Tsai | 97e36b3 | 2014-02-03 09:51:40 +0800 | [diff] [blame^] | 872 | const char *parent; |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 873 | const char *clk_name; |
| 874 | struct clk **clks, *pclk; |
| 875 | struct clk_hw *gate_hw, *rate_hw; |
| 876 | const struct clk_ops *rate_ops; |
| 877 | struct clk_gate *gate = NULL; |
| 878 | struct clk_fixed_factor *fix_factor; |
| 879 | struct clk_divider *divider; |
| 880 | void *reg; |
| 881 | int i = 0; |
| 882 | int flags, clkflags; |
| 883 | |
| 884 | /* Set up factor clock that we will be dividing */ |
| 885 | pclk = sunxi_factors_clk_setup(node, data->factors); |
Chen-Yu Tsai | 97e36b3 | 2014-02-03 09:51:40 +0800 | [diff] [blame^] | 886 | parent = __clk_get_name(pclk); |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 887 | |
| 888 | reg = of_iomap(node, 0); |
| 889 | |
| 890 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 891 | if (!clk_data) |
| 892 | return; |
| 893 | |
Emilio López | d193368 | 2014-01-24 22:32:41 -0300 | [diff] [blame] | 894 | clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL); |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 895 | if (!clks) |
| 896 | goto free_clkdata; |
| 897 | |
| 898 | clk_data->clks = clks; |
| 899 | |
| 900 | /* It's not a good idea to have automatic reparenting changing |
| 901 | * our RAM clock! */ |
| 902 | clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; |
| 903 | |
| 904 | for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) { |
| 905 | if (of_property_read_string_index(node, "clock-output-names", |
| 906 | i, &clk_name) != 0) |
| 907 | break; |
| 908 | |
| 909 | gate_hw = NULL; |
| 910 | rate_hw = NULL; |
| 911 | rate_ops = NULL; |
| 912 | |
| 913 | /* If this leaf clock can be gated, create a gate */ |
| 914 | if (data->div[i].gate) { |
| 915 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
| 916 | if (!gate) |
| 917 | goto free_clks; |
| 918 | |
| 919 | gate->reg = reg; |
| 920 | gate->bit_idx = data->div[i].gate; |
| 921 | gate->lock = &clk_lock; |
| 922 | |
| 923 | gate_hw = &gate->hw; |
| 924 | } |
| 925 | |
| 926 | /* Leaves can be fixed or configurable divisors */ |
| 927 | if (data->div[i].fixed) { |
| 928 | fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL); |
| 929 | if (!fix_factor) |
| 930 | goto free_gate; |
| 931 | |
| 932 | fix_factor->mult = 1; |
| 933 | fix_factor->div = data->div[i].fixed; |
| 934 | |
| 935 | rate_hw = &fix_factor->hw; |
| 936 | rate_ops = &clk_fixed_factor_ops; |
| 937 | } else { |
| 938 | divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
| 939 | if (!divider) |
| 940 | goto free_gate; |
| 941 | |
| 942 | flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; |
| 943 | |
| 944 | divider->reg = reg; |
| 945 | divider->shift = data->div[i].shift; |
| 946 | divider->width = SUNXI_DIVISOR_WIDTH; |
| 947 | divider->flags = flags; |
| 948 | divider->lock = &clk_lock; |
| 949 | divider->table = data->div[i].table; |
| 950 | |
| 951 | rate_hw = ÷r->hw; |
| 952 | rate_ops = &clk_divider_ops; |
| 953 | } |
| 954 | |
| 955 | /* Wrap the (potential) gate and the divisor on a composite |
| 956 | * clock to unify them */ |
| 957 | clks[i] = clk_register_composite(NULL, clk_name, &parent, 1, |
| 958 | NULL, NULL, |
| 959 | rate_hw, rate_ops, |
| 960 | gate_hw, &clk_gate_ops, |
| 961 | clkflags); |
| 962 | |
| 963 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 964 | clk_register_clkdev(clks[i], clk_name, NULL); |
| 965 | } |
| 966 | |
| 967 | /* The last clock available on the getter is the parent */ |
| 968 | clks[i++] = pclk; |
| 969 | |
| 970 | /* Adjust to the real max */ |
| 971 | clk_data->clk_num = i; |
| 972 | |
| 973 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 974 | |
| 975 | return; |
| 976 | |
| 977 | free_gate: |
| 978 | kfree(gate); |
| 979 | free_clks: |
| 980 | kfree(clks); |
| 981 | free_clkdata: |
| 982 | kfree(clk_data); |
| 983 | } |
| 984 | |
| 985 | |
| 986 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 987 | /* Matches for factors clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 988 | static const struct of_device_id clk_factors_match[] __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 989 | {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 990 | {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 991 | {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,}, |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 992 | {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,}, |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 993 | {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 994 | {} |
| 995 | }; |
| 996 | |
| 997 | /* Matches for divider clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 998 | static const struct of_device_id clk_div_match[] __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 999 | {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,}, |
| 1000 | {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,}, |
| 1001 | {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1002 | {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1003 | {} |
| 1004 | }; |
| 1005 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1006 | /* Matches for divided outputs */ |
| 1007 | static const struct of_device_id clk_divs_match[] __initconst = { |
| 1008 | {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,}, |
| 1009 | {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,}, |
| 1010 | {} |
| 1011 | }; |
| 1012 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1013 | /* Matches for mux clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1014 | static const struct of_device_id clk_mux_match[] __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 1015 | {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,}, |
| 1016 | {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1017 | {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1018 | {} |
| 1019 | }; |
| 1020 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1021 | /* Matches for gate clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1022 | static const struct of_device_id clk_gates_match[] __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1023 | {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,}, |
| 1024 | {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1025 | {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1026 | {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1027 | {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1028 | {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1029 | {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1030 | {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1031 | {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1032 | {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1033 | {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1034 | {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1035 | {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1036 | {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1037 | {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1038 | {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1039 | {} |
| 1040 | }; |
| 1041 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1042 | static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match, |
| 1043 | void *function) |
| 1044 | { |
| 1045 | struct device_node *np; |
| 1046 | const struct div_data *data; |
| 1047 | const struct of_device_id *match; |
| 1048 | void (*setup_function)(struct device_node *, const void *) = function; |
| 1049 | |
| 1050 | for_each_matching_node(np, clk_match) { |
| 1051 | match = of_match_node(clk_match, np); |
| 1052 | data = match->data; |
| 1053 | setup_function(np, data); |
| 1054 | } |
| 1055 | } |
| 1056 | |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1057 | /** |
| 1058 | * System clock protection |
| 1059 | * |
| 1060 | * By enabling these critical clocks, we prevent their accidental gating |
| 1061 | * by the framework |
| 1062 | */ |
| 1063 | static void __init sunxi_clock_protect(void) |
| 1064 | { |
| 1065 | struct clk *clk; |
| 1066 | |
| 1067 | /* memory bus clock - sun5i+ */ |
| 1068 | clk = clk_get(NULL, "mbus"); |
| 1069 | if (!IS_ERR(clk)) { |
| 1070 | clk_prepare_enable(clk); |
| 1071 | clk_put(clk); |
| 1072 | } |
| 1073 | |
| 1074 | /* DDR clock - sun4i+ */ |
| 1075 | clk = clk_get(NULL, "pll5_ddr"); |
| 1076 | if (!IS_ERR(clk)) { |
| 1077 | clk_prepare_enable(clk); |
| 1078 | clk_put(clk); |
| 1079 | } |
| 1080 | } |
| 1081 | |
Mike Turquette | 1d9438f | 2013-12-01 12:42:45 -0800 | [diff] [blame] | 1082 | static void __init sunxi_init_clocks(void) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1083 | { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1084 | /* Register factor clocks */ |
| 1085 | of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); |
| 1086 | |
| 1087 | /* Register divider clocks */ |
| 1088 | of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); |
| 1089 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1090 | /* Register divided output clocks */ |
| 1091 | of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup); |
| 1092 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1093 | /* Register mux clocks */ |
| 1094 | of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1095 | |
| 1096 | /* Register gate clocks */ |
| 1097 | of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1098 | |
| 1099 | /* Enable core system clocks */ |
| 1100 | sunxi_clock_protect(); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1101 | } |
Sebastian Hesselbarth | be08045 | 2013-09-06 14:59:57 +0200 | [diff] [blame] | 1102 | CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks); |
| 1103 | CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks); |
| 1104 | CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks); |
| 1105 | CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks); |
| 1106 | CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks); |