Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 3 | /include/ "tegra20.dtsi" |
| 4 | |
| 5 | / { |
| 6 | model = "NVIDIA Seaboard"; |
| 7 | compatible = "nvidia,seaboard", "nvidia,tegra20"; |
| 8 | |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 9 | memory { |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 10 | reg = <0x00000000 0x40000000>; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 11 | }; |
| 12 | |
Stephen Warren | a75191e | 2013-01-02 14:53:20 -0700 | [diff] [blame^] | 13 | host1x { |
| 14 | hdmi { |
| 15 | status = "okay"; |
| 16 | |
| 17 | vdd-supply = <&hdmi_vdd_reg>; |
| 18 | pll-supply = <&hdmi_pll_reg>; |
| 19 | |
| 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 21 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ |
| 22 | }; |
| 23 | }; |
| 24 | |
Stephen Warren | f9eb26a | 2012-05-11 16:17:47 -0600 | [diff] [blame] | 25 | pinmux { |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 26 | pinctrl-names = "default"; |
| 27 | pinctrl-0 = <&state_default>; |
| 28 | |
| 29 | state_default: pinmux { |
| 30 | ata { |
| 31 | nvidia,pins = "ata"; |
| 32 | nvidia,function = "ide"; |
| 33 | }; |
| 34 | atb { |
| 35 | nvidia,pins = "atb", "gma", "gme"; |
| 36 | nvidia,function = "sdio4"; |
| 37 | }; |
| 38 | atc { |
| 39 | nvidia,pins = "atc"; |
| 40 | nvidia,function = "nand"; |
| 41 | }; |
| 42 | atd { |
| 43 | nvidia,pins = "atd", "ate", "gmb", "spia", |
| 44 | "spib", "spic"; |
| 45 | nvidia,function = "gmi"; |
| 46 | }; |
| 47 | cdev1 { |
| 48 | nvidia,pins = "cdev1"; |
| 49 | nvidia,function = "plla_out"; |
| 50 | }; |
| 51 | cdev2 { |
| 52 | nvidia,pins = "cdev2"; |
| 53 | nvidia,function = "pllp_out4"; |
| 54 | }; |
| 55 | crtp { |
| 56 | nvidia,pins = "crtp", "lm1"; |
| 57 | nvidia,function = "crt"; |
| 58 | }; |
| 59 | csus { |
| 60 | nvidia,pins = "csus"; |
| 61 | nvidia,function = "vi_sensor_clk"; |
| 62 | }; |
| 63 | dap1 { |
| 64 | nvidia,pins = "dap1"; |
| 65 | nvidia,function = "dap1"; |
| 66 | }; |
| 67 | dap2 { |
| 68 | nvidia,pins = "dap2"; |
| 69 | nvidia,function = "dap2"; |
| 70 | }; |
| 71 | dap3 { |
| 72 | nvidia,pins = "dap3"; |
| 73 | nvidia,function = "dap3"; |
| 74 | }; |
| 75 | dap4 { |
| 76 | nvidia,pins = "dap4"; |
| 77 | nvidia,function = "dap4"; |
| 78 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 79 | dta { |
| 80 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; |
| 81 | nvidia,function = "vi"; |
| 82 | }; |
| 83 | dtf { |
| 84 | nvidia,pins = "dtf"; |
| 85 | nvidia,function = "i2c3"; |
| 86 | }; |
| 87 | gmc { |
| 88 | nvidia,pins = "gmc"; |
| 89 | nvidia,function = "uartd"; |
| 90 | }; |
| 91 | gmd { |
| 92 | nvidia,pins = "gmd"; |
| 93 | nvidia,function = "sflash"; |
| 94 | }; |
| 95 | gpu { |
| 96 | nvidia,pins = "gpu"; |
| 97 | nvidia,function = "pwm"; |
| 98 | }; |
| 99 | gpu7 { |
| 100 | nvidia,pins = "gpu7"; |
| 101 | nvidia,function = "rtck"; |
| 102 | }; |
| 103 | gpv { |
| 104 | nvidia,pins = "gpv", "slxa", "slxk"; |
| 105 | nvidia,function = "pcie"; |
| 106 | }; |
| 107 | hdint { |
| 108 | nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", |
Stephen Warren | 802a849 | 2012-04-26 11:21:54 -0600 | [diff] [blame] | 109 | "lsck", "lsda"; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 110 | nvidia,function = "hdmi"; |
| 111 | }; |
| 112 | i2cp { |
| 113 | nvidia,pins = "i2cp"; |
| 114 | nvidia,function = "i2cp"; |
| 115 | }; |
| 116 | irrx { |
| 117 | nvidia,pins = "irrx", "irtx"; |
| 118 | nvidia,function = "uartb"; |
| 119 | }; |
| 120 | kbca { |
| 121 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 122 | "kbce", "kbcf"; |
| 123 | nvidia,function = "kbc"; |
| 124 | }; |
| 125 | lcsn { |
| 126 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", |
| 127 | "lsdi", "lvp0"; |
| 128 | nvidia,function = "rsvd4"; |
| 129 | }; |
| 130 | ld0 { |
| 131 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 132 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 133 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 134 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 135 | "lhp1", "lhp2", "lhs", "lpp", "lsc0", |
| 136 | "lspi", "lvp1", "lvs"; |
| 137 | nvidia,function = "displaya"; |
| 138 | }; |
Stephen Warren | a18cf6d | 2012-04-16 17:41:17 -0600 | [diff] [blame] | 139 | owc { |
| 140 | nvidia,pins = "owc", "spdi", "spdo", "uac"; |
| 141 | nvidia,function = "rsvd2"; |
| 142 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 143 | pmc { |
| 144 | nvidia,pins = "pmc"; |
| 145 | nvidia,function = "pwr_on"; |
| 146 | }; |
| 147 | rm { |
| 148 | nvidia,pins = "rm"; |
| 149 | nvidia,function = "i2c1"; |
| 150 | }; |
| 151 | sdb { |
| 152 | nvidia,pins = "sdb", "sdc", "sdd"; |
| 153 | nvidia,function = "sdio3"; |
| 154 | }; |
| 155 | sdio1 { |
| 156 | nvidia,pins = "sdio1"; |
| 157 | nvidia,function = "sdio1"; |
| 158 | }; |
| 159 | slxc { |
| 160 | nvidia,pins = "slxc", "slxd"; |
| 161 | nvidia,function = "spdif"; |
| 162 | }; |
| 163 | spid { |
| 164 | nvidia,pins = "spid", "spie", "spif"; |
| 165 | nvidia,function = "spi1"; |
| 166 | }; |
| 167 | spig { |
| 168 | nvidia,pins = "spig", "spih"; |
| 169 | nvidia,function = "spi2_alt"; |
| 170 | }; |
| 171 | uaa { |
| 172 | nvidia,pins = "uaa", "uab", "uda"; |
| 173 | nvidia,function = "ulpi"; |
| 174 | }; |
| 175 | uad { |
| 176 | nvidia,pins = "uad"; |
| 177 | nvidia,function = "irda"; |
| 178 | }; |
| 179 | uca { |
| 180 | nvidia,pins = "uca", "ucb"; |
| 181 | nvidia,function = "uartc"; |
| 182 | }; |
| 183 | conf_ata { |
| 184 | nvidia,pins = "ata", "atb", "atc", "atd", |
| 185 | "cdev1", "cdev2", "dap1", "dap2", |
Stephen Warren | a18cf6d | 2012-04-16 17:41:17 -0600 | [diff] [blame] | 186 | "dap4", "ddc", "dtf", "gma", "gmc", "gmd", |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 187 | "gme", "gpu", "gpu7", "i2cp", "irrx", |
| 188 | "irtx", "pta", "rm", "sdc", "sdd", |
| 189 | "slxd", "slxk", "spdi", "spdo", "uac", |
| 190 | "uad", "uca", "ucb", "uda"; |
| 191 | nvidia,pull = <0>; |
| 192 | nvidia,tristate = <0>; |
| 193 | }; |
| 194 | conf_ate { |
Stephen Warren | a18cf6d | 2012-04-16 17:41:17 -0600 | [diff] [blame] | 195 | nvidia,pins = "ate", "csus", "dap3", |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 196 | "gpv", "owc", "slxc", "spib", "spid", |
| 197 | "spie"; |
| 198 | nvidia,pull = <0>; |
| 199 | nvidia,tristate = <1>; |
| 200 | }; |
| 201 | conf_ck32 { |
| 202 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
| 203 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
| 204 | nvidia,pull = <0>; |
| 205 | }; |
| 206 | conf_crtp { |
| 207 | nvidia,pins = "crtp", "gmb", "slxa", "spia", |
| 208 | "spig", "spih"; |
| 209 | nvidia,pull = <2>; |
| 210 | nvidia,tristate = <1>; |
| 211 | }; |
| 212 | conf_dta { |
| 213 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; |
| 214 | nvidia,pull = <1>; |
| 215 | nvidia,tristate = <0>; |
| 216 | }; |
| 217 | conf_dte { |
| 218 | nvidia,pins = "dte", "spif"; |
| 219 | nvidia,pull = <1>; |
| 220 | nvidia,tristate = <1>; |
| 221 | }; |
| 222 | conf_hdint { |
| 223 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
| 224 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", |
| 225 | "lvp0"; |
| 226 | nvidia,tristate = <1>; |
| 227 | }; |
| 228 | conf_kbca { |
| 229 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 230 | "kbce", "kbcf", "sdio1", "spic", "uaa", |
| 231 | "uab"; |
| 232 | nvidia,pull = <2>; |
| 233 | nvidia,tristate = <0>; |
| 234 | }; |
| 235 | conf_lc { |
| 236 | nvidia,pins = "lc", "ls"; |
| 237 | nvidia,pull = <2>; |
| 238 | }; |
| 239 | conf_ld0 { |
| 240 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 241 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 242 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 243 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 244 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
| 245 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", |
| 246 | "lvs", "pmc", "sdb"; |
| 247 | nvidia,tristate = <0>; |
| 248 | }; |
| 249 | conf_ld17_0 { |
| 250 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 251 | "ld23_22"; |
| 252 | nvidia,pull = <1>; |
| 253 | }; |
| 254 | drive_sdio1 { |
| 255 | nvidia,pins = "drive_sdio1"; |
| 256 | nvidia,high-speed-mode = <0>; |
| 257 | nvidia,schmitt = <0>; |
| 258 | nvidia,low-power-mode = <3>; |
| 259 | nvidia,pull-down-strength = <31>; |
| 260 | nvidia,pull-up-strength = <31>; |
| 261 | nvidia,slew-rate-rising = <3>; |
| 262 | nvidia,slew-rate-falling = <3>; |
| 263 | }; |
| 264 | }; |
Stephen Warren | a18cf6d | 2012-04-16 17:41:17 -0600 | [diff] [blame] | 265 | |
| 266 | state_i2cmux_ddc: pinmux_i2cmux_ddc { |
| 267 | ddc { |
| 268 | nvidia,pins = "ddc"; |
| 269 | nvidia,function = "i2c2"; |
| 270 | }; |
| 271 | pta { |
| 272 | nvidia,pins = "pta"; |
| 273 | nvidia,function = "rsvd4"; |
| 274 | }; |
| 275 | }; |
| 276 | |
| 277 | state_i2cmux_pta: pinmux_i2cmux_pta { |
| 278 | ddc { |
| 279 | nvidia,pins = "ddc"; |
| 280 | nvidia,function = "rsvd4"; |
| 281 | }; |
| 282 | pta { |
| 283 | nvidia,pins = "pta"; |
| 284 | nvidia,function = "i2c2"; |
| 285 | }; |
| 286 | }; |
| 287 | |
| 288 | state_i2cmux_idle: pinmux_i2cmux_idle { |
| 289 | ddc { |
| 290 | nvidia,pins = "ddc"; |
| 291 | nvidia,function = "rsvd4"; |
| 292 | }; |
| 293 | pta { |
| 294 | nvidia,pins = "pta"; |
| 295 | nvidia,function = "rsvd4"; |
| 296 | }; |
| 297 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 298 | }; |
| 299 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 300 | i2s@70002800 { |
| 301 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 302 | }; |
| 303 | |
| 304 | serial@70006300 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 305 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 306 | clock-frequency = <216000000>; |
| 307 | }; |
| 308 | |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 309 | i2c@7000c000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 310 | status = "okay"; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 311 | clock-frequency = <400000>; |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 312 | |
| 313 | wm8903: wm8903@1a { |
| 314 | compatible = "wlf,wm8903"; |
| 315 | reg = <0x1a>; |
| 316 | interrupt-parent = <&gpio>; |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 317 | interrupts = <187 0x04>; |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 318 | |
| 319 | gpio-controller; |
| 320 | #gpio-cells = <2>; |
| 321 | |
| 322 | micdet-cfg = <0>; |
| 323 | micdet-delay = <100>; |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 324 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 325 | }; |
Laxman Dewangan | b46b0b5 | 2012-04-23 17:41:36 +0530 | [diff] [blame] | 326 | |
| 327 | /* ALS and proximity sensor */ |
| 328 | isl29018@44 { |
| 329 | compatible = "isil,isl29018"; |
| 330 | reg = <0x44>; |
| 331 | interrupt-parent = <&gpio>; |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 332 | interrupts = <202 0x04>; /* GPIO PZ2 */ |
Laxman Dewangan | b46b0b5 | 2012-04-23 17:41:36 +0530 | [diff] [blame] | 333 | }; |
Olof Johansson | 45dbe9d | 2011-12-22 16:33:13 +0000 | [diff] [blame] | 334 | |
| 335 | gyrometer@68 { |
| 336 | compatible = "invn,mpu3050"; |
| 337 | reg = <0x68>; |
| 338 | interrupt-parent = <&gpio>; |
| 339 | interrupts = <204 0x04>; /* gpio PZ4 */ |
| 340 | }; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 341 | }; |
| 342 | |
| 343 | i2c@7000c400 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 344 | status = "okay"; |
Stephen Warren | 22bd1f7 | 2012-04-26 11:19:03 -0600 | [diff] [blame] | 345 | clock-frequency = <100000>; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 346 | }; |
| 347 | |
Stephen Warren | a18cf6d | 2012-04-16 17:41:17 -0600 | [diff] [blame] | 348 | i2cmux { |
| 349 | compatible = "i2c-mux-pinctrl"; |
| 350 | #address-cells = <1>; |
| 351 | #size-cells = <0>; |
| 352 | |
| 353 | i2c-parent = <&{/i2c@7000c400}>; |
| 354 | |
| 355 | pinctrl-names = "ddc", "pta", "idle"; |
| 356 | pinctrl-0 = <&state_i2cmux_ddc>; |
| 357 | pinctrl-1 = <&state_i2cmux_pta>; |
| 358 | pinctrl-2 = <&state_i2cmux_idle>; |
| 359 | |
Stephen Warren | a75191e | 2013-01-02 14:53:20 -0700 | [diff] [blame^] | 360 | hdmi_ddc: i2c@0 { |
Stephen Warren | a18cf6d | 2012-04-16 17:41:17 -0600 | [diff] [blame] | 361 | reg = <0>; |
| 362 | #address-cells = <1>; |
| 363 | #size-cells = <0>; |
| 364 | }; |
| 365 | |
| 366 | i2c@1 { |
| 367 | reg = <1>; |
| 368 | #address-cells = <1>; |
| 369 | #size-cells = <0>; |
Stephen Warren | 0879c5f | 2012-04-25 16:57:28 -0600 | [diff] [blame] | 370 | |
| 371 | smart-battery@b { |
| 372 | compatible = "ti,bq20z75", "smart-battery-1.1"; |
| 373 | reg = <0xb>; |
| 374 | ti,i2c-retry-count = <2>; |
| 375 | ti,poll-retry-count = <10>; |
| 376 | }; |
Stephen Warren | a18cf6d | 2012-04-16 17:41:17 -0600 | [diff] [blame] | 377 | }; |
| 378 | }; |
| 379 | |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 380 | i2c@7000c500 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 381 | status = "okay"; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 382 | clock-frequency = <400000>; |
| 383 | }; |
| 384 | |
| 385 | i2c@7000d000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 386 | status = "okay"; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 387 | clock-frequency = <400000>; |
Stephen Warren | 401c9a5 | 2011-12-17 23:29:32 -0700 | [diff] [blame] | 388 | |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 389 | pmic: tps6586x@34 { |
| 390 | compatible = "ti,tps6586x"; |
| 391 | reg = <0x34>; |
| 392 | interrupts = <0 86 0x4>; |
| 393 | |
Stephen Warren | 44b12ef | 2012-09-11 11:42:26 -0600 | [diff] [blame] | 394 | ti,system-power-controller; |
| 395 | |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 396 | #gpio-cells = <2>; |
| 397 | gpio-controller; |
| 398 | |
| 399 | sys-supply = <&vdd_5v0_reg>; |
| 400 | vin-sm0-supply = <&sys_reg>; |
| 401 | vin-sm1-supply = <&sys_reg>; |
| 402 | vin-sm2-supply = <&sys_reg>; |
| 403 | vinldo01-supply = <&sm2_reg>; |
| 404 | vinldo23-supply = <&sm2_reg>; |
| 405 | vinldo4-supply = <&sm2_reg>; |
| 406 | vinldo678-supply = <&sm2_reg>; |
| 407 | vinldo9-supply = <&sm2_reg>; |
| 408 | |
| 409 | regulators { |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 410 | sys_reg: sys { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 411 | regulator-name = "vdd_sys"; |
| 412 | regulator-always-on; |
| 413 | }; |
| 414 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 415 | sm0 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 416 | regulator-name = "vdd_sm0,vdd_core"; |
| 417 | regulator-min-microvolt = <1300000>; |
| 418 | regulator-max-microvolt = <1300000>; |
| 419 | regulator-always-on; |
| 420 | }; |
| 421 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 422 | sm1 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 423 | regulator-name = "vdd_sm1,vdd_cpu"; |
| 424 | regulator-min-microvolt = <1125000>; |
| 425 | regulator-max-microvolt = <1125000>; |
| 426 | regulator-always-on; |
| 427 | }; |
| 428 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 429 | sm2_reg: sm2 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 430 | regulator-name = "vdd_sm2,vin_ldo*"; |
| 431 | regulator-min-microvolt = <3700000>; |
| 432 | regulator-max-microvolt = <3700000>; |
| 433 | regulator-always-on; |
| 434 | }; |
| 435 | |
| 436 | /* LDO0 is not connected to anything */ |
| 437 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 438 | ldo1 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 439 | regulator-name = "vdd_ldo1,avdd_pll*"; |
| 440 | regulator-min-microvolt = <1100000>; |
| 441 | regulator-max-microvolt = <1100000>; |
| 442 | regulator-always-on; |
| 443 | }; |
| 444 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 445 | ldo2 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 446 | regulator-name = "vdd_ldo2,vdd_rtc"; |
| 447 | regulator-min-microvolt = <1200000>; |
| 448 | regulator-max-microvolt = <1200000>; |
| 449 | }; |
| 450 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 451 | ldo3 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 452 | regulator-name = "vdd_ldo3,avdd_usb*"; |
| 453 | regulator-min-microvolt = <3300000>; |
| 454 | regulator-max-microvolt = <3300000>; |
| 455 | regulator-always-on; |
| 456 | }; |
| 457 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 458 | ldo4 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 459 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
| 460 | regulator-min-microvolt = <1800000>; |
| 461 | regulator-max-microvolt = <1800000>; |
| 462 | regulator-always-on; |
| 463 | }; |
| 464 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 465 | ldo5 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 466 | regulator-name = "vdd_ldo5,vcore_mmc"; |
| 467 | regulator-min-microvolt = <2850000>; |
| 468 | regulator-max-microvolt = <2850000>; |
| 469 | regulator-always-on; |
| 470 | }; |
| 471 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 472 | ldo6 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 473 | regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; |
| 474 | regulator-min-microvolt = <1800000>; |
| 475 | regulator-max-microvolt = <1800000>; |
| 476 | }; |
| 477 | |
Stephen Warren | a75191e | 2013-01-02 14:53:20 -0700 | [diff] [blame^] | 478 | hdmi_vdd_reg: ldo7 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 479 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
| 480 | regulator-min-microvolt = <3300000>; |
| 481 | regulator-max-microvolt = <3300000>; |
| 482 | }; |
| 483 | |
Stephen Warren | a75191e | 2013-01-02 14:53:20 -0700 | [diff] [blame^] | 484 | hdmi_pll_reg: ldo8 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 485 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
| 486 | regulator-min-microvolt = <1800000>; |
| 487 | regulator-max-microvolt = <1800000>; |
| 488 | }; |
| 489 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 490 | ldo9 { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 491 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
| 492 | regulator-min-microvolt = <2850000>; |
| 493 | regulator-max-microvolt = <2850000>; |
| 494 | regulator-always-on; |
| 495 | }; |
| 496 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 497 | ldo_rtc { |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 498 | regulator-name = "vdd_rtc_out,vdd_cell"; |
| 499 | regulator-min-microvolt = <3300000>; |
| 500 | regulator-max-microvolt = <3300000>; |
| 501 | regulator-always-on; |
| 502 | }; |
| 503 | }; |
| 504 | }; |
| 505 | |
Olof Johansson | 45dbe9d | 2011-12-22 16:33:13 +0000 | [diff] [blame] | 506 | temperature-sensor@4c { |
Stephen Warren | 9846210 | 2012-11-19 15:34:44 -0700 | [diff] [blame] | 507 | compatible = "onnn,nct1008"; |
Stephen Warren | 401c9a5 | 2011-12-17 23:29:32 -0700 | [diff] [blame] | 508 | reg = <0x4c>; |
| 509 | }; |
Olof Johansson | 45dbe9d | 2011-12-22 16:33:13 +0000 | [diff] [blame] | 510 | |
| 511 | magnetometer@c { |
Stephen Warren | 9846210 | 2012-11-19 15:34:44 -0700 | [diff] [blame] | 512 | compatible = "ak,ak8975"; |
Olof Johansson | 45dbe9d | 2011-12-22 16:33:13 +0000 | [diff] [blame] | 513 | reg = <0xc>; |
| 514 | interrupt-parent = <&gpio>; |
| 515 | interrupts = <109 0x04>; /* gpio PN5 */ |
| 516 | }; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 517 | }; |
| 518 | |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 519 | pmc { |
| 520 | nvidia,invert-interrupt; |
| 521 | }; |
| 522 | |
Stephen Warren | bbfc33b | 2012-10-02 13:10:47 -0600 | [diff] [blame] | 523 | memory-controller@7000f400 { |
Olof Johansson | d8017a9 | 2011-10-18 11:06:06 -0700 | [diff] [blame] | 524 | emc-table@190000 { |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 525 | reg = <190000>; |
Olof Johansson | d8017a9 | 2011-10-18 11:06:06 -0700 | [diff] [blame] | 526 | compatible = "nvidia,tegra20-emc-table"; |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 527 | clock-frequency = <190000>; |
| 528 | nvidia,emc-registers = <0x0000000c 0x00000026 |
Olof Johansson | d8017a9 | 2011-10-18 11:06:06 -0700 | [diff] [blame] | 529 | 0x00000009 0x00000003 0x00000004 0x00000004 |
| 530 | 0x00000002 0x0000000c 0x00000003 0x00000003 |
| 531 | 0x00000002 0x00000001 0x00000004 0x00000005 |
| 532 | 0x00000004 0x00000009 0x0000000d 0x0000059f |
| 533 | 0x00000000 0x00000003 0x00000003 0x00000003 |
| 534 | 0x00000003 0x00000001 0x0000000b 0x000000c8 |
| 535 | 0x00000003 0x00000007 0x00000004 0x0000000f |
| 536 | 0x00000002 0x00000000 0x00000000 0x00000002 |
| 537 | 0x00000000 0x00000000 0x00000083 0xa06204ae |
| 538 | 0x007dc010 0x00000000 0x00000000 0x00000000 |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 539 | 0x00000000 0x00000000 0x00000000 0x00000000>; |
Olof Johansson | d8017a9 | 2011-10-18 11:06:06 -0700 | [diff] [blame] | 540 | }; |
| 541 | |
| 542 | emc-table@380000 { |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 543 | reg = <380000>; |
Olof Johansson | d8017a9 | 2011-10-18 11:06:06 -0700 | [diff] [blame] | 544 | compatible = "nvidia,tegra20-emc-table"; |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 545 | clock-frequency = <380000>; |
| 546 | nvidia,emc-registers = <0x00000017 0x0000004b |
Olof Johansson | d8017a9 | 2011-10-18 11:06:06 -0700 | [diff] [blame] | 547 | 0x00000012 0x00000006 0x00000004 0x00000005 |
| 548 | 0x00000003 0x0000000c 0x00000006 0x00000006 |
| 549 | 0x00000003 0x00000001 0x00000004 0x00000005 |
| 550 | 0x00000004 0x00000009 0x0000000d 0x00000b5f |
| 551 | 0x00000000 0x00000003 0x00000003 0x00000006 |
| 552 | 0x00000006 0x00000001 0x00000011 0x000000c8 |
| 553 | 0x00000003 0x0000000e 0x00000007 0x0000000f |
| 554 | 0x00000002 0x00000000 0x00000000 0x00000002 |
| 555 | 0x00000000 0x00000000 0x00000083 0xe044048b |
| 556 | 0x007d8010 0x00000000 0x00000000 0x00000000 |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 557 | 0x00000000 0x00000000 0x00000000 0x00000000>; |
Olof Johansson | d8017a9 | 2011-10-18 11:06:06 -0700 | [diff] [blame] | 558 | }; |
| 559 | }; |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 560 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 561 | usb@c5000000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 562 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 563 | nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ |
| 564 | dr_mode = "otg"; |
| 565 | }; |
| 566 | |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 567 | usb@c5004000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 568 | status = "okay"; |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 569 | nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ |
| 570 | }; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 571 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 572 | usb@c5008000 { |
| 573 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 574 | }; |
| 575 | |
Wei Ni | da2fc65 | 2012-09-21 16:54:57 +0800 | [diff] [blame] | 576 | sdhci@c8000000 { |
| 577 | status = "okay"; |
| 578 | power-gpios = <&gpio 86 0>; /* gpio PK6 */ |
| 579 | bus-width = <4>; |
| 580 | }; |
| 581 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 582 | sdhci@c8000400 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 583 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 584 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ |
| 585 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 586 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 587 | bus-width = <4>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 588 | }; |
| 589 | |
| 590 | sdhci@c8000600 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 591 | status = "okay"; |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 592 | bus-width = <8>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 593 | }; |
| 594 | |
| 595 | gpio-keys { |
| 596 | compatible = "gpio-keys"; |
| 597 | |
| 598 | power { |
| 599 | label = "Power"; |
| 600 | gpios = <&gpio 170 1>; /* gpio PV2, active low */ |
| 601 | linux,code = <116>; /* KEY_POWER */ |
| 602 | gpio-key,wakeup; |
| 603 | }; |
| 604 | |
| 605 | lid { |
| 606 | label = "Lid"; |
| 607 | gpios = <&gpio 23 0>; /* gpio PC7 */ |
| 608 | linux,input-type = <5>; /* EV_SW */ |
| 609 | linux,code = <0>; /* SW_LID */ |
| 610 | debounce-interval = <1>; |
| 611 | gpio-key,wakeup; |
| 612 | }; |
| 613 | }; |
| 614 | |
Stephen Warren | 6529e63 | 2012-06-20 15:58:34 -0600 | [diff] [blame] | 615 | regulators { |
| 616 | compatible = "simple-bus"; |
| 617 | #address-cells = <1>; |
| 618 | #size-cells = <0>; |
| 619 | |
| 620 | vdd_5v0_reg: regulator@0 { |
| 621 | compatible = "regulator-fixed"; |
| 622 | reg = <0>; |
| 623 | regulator-name = "vdd_5v0"; |
| 624 | regulator-min-microvolt = <5000000>; |
| 625 | regulator-max-microvolt = <5000000>; |
| 626 | regulator-always-on; |
| 627 | }; |
| 628 | |
| 629 | regulator@1 { |
| 630 | compatible = "regulator-fixed"; |
| 631 | reg = <1>; |
| 632 | regulator-name = "vdd_1v5"; |
| 633 | regulator-min-microvolt = <1500000>; |
| 634 | regulator-max-microvolt = <1500000>; |
| 635 | gpio = <&pmic 0 0>; |
| 636 | }; |
| 637 | |
| 638 | regulator@2 { |
| 639 | compatible = "regulator-fixed"; |
| 640 | reg = <2>; |
| 641 | regulator-name = "vdd_1v2"; |
| 642 | regulator-min-microvolt = <1200000>; |
| 643 | regulator-max-microvolt = <1200000>; |
| 644 | gpio = <&pmic 1 0>; |
| 645 | enable-active-high; |
| 646 | }; |
| 647 | }; |
| 648 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 649 | sound { |
| 650 | compatible = "nvidia,tegra-audio-wm8903-seaboard", |
| 651 | "nvidia,tegra-audio-wm8903"; |
| 652 | nvidia,model = "NVIDIA Tegra Seaboard"; |
| 653 | |
| 654 | nvidia,audio-routing = |
| 655 | "Headphone Jack", "HPOUTR", |
| 656 | "Headphone Jack", "HPOUTL", |
| 657 | "Int Spk", "ROP", |
| 658 | "Int Spk", "RON", |
| 659 | "Int Spk", "LOP", |
| 660 | "Int Spk", "LON", |
| 661 | "Mic Jack", "MICBIAS", |
| 662 | "IN1R", "Mic Jack"; |
| 663 | |
| 664 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 665 | nvidia,audio-codec = <&wm8903>; |
| 666 | |
| 667 | nvidia,spkr-en-gpios = <&wm8903 2 0>; |
| 668 | nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ |
| 669 | }; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 670 | }; |