Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include "skeleton64.dtsi" |
| 15 | #include <dt-bindings/gpio/gpio.h> |
Kiran Gunda | 0954f39 | 2017-10-16 16:24:55 +0530 | [diff] [blame] | 16 | #include <dt-bindings/spmi/spmi.h> |
Kiran Gunda | af6a0b6 | 2017-10-23 16:03:10 +0530 | [diff] [blame] | 17 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Kiran Gunda | 0954f39 | 2017-10-16 16:24:55 +0530 | [diff] [blame] | 18 | #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 19 | #include <dt-bindings/clock/msm-clocks-8953.h> |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 20 | |
| 21 | / { |
| 22 | model = "Qualcomm Technologies, Inc. MSM 8953"; |
| 23 | compatible = "qcom,msm8953"; |
| 24 | qcom,msm-id = <293 0x0>; |
| 25 | interrupt-parent = <&intc>; |
| 26 | |
| 27 | chosen { |
| 28 | bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1"; |
| 29 | }; |
| 30 | |
| 31 | reserved-memory { |
| 32 | #address-cells = <2>; |
| 33 | #size-cells = <2>; |
| 34 | ranges; |
| 35 | |
| 36 | other_ext_mem: other_ext_region@0 { |
| 37 | compatible = "removed-dma-pool"; |
| 38 | no-map; |
| 39 | reg = <0x0 0x85b00000 0x0 0xd00000>; |
| 40 | }; |
| 41 | |
| 42 | modem_mem: modem_region@0 { |
| 43 | compatible = "removed-dma-pool"; |
| 44 | no-map-fixup; |
| 45 | reg = <0x0 0x86c00000 0x0 0x6a00000>; |
| 46 | }; |
| 47 | |
| 48 | adsp_fw_mem: adsp_fw_region@0 { |
| 49 | compatible = "removed-dma-pool"; |
| 50 | no-map; |
| 51 | reg = <0x0 0x8d600000 0x0 0x1100000>; |
| 52 | }; |
| 53 | |
| 54 | wcnss_fw_mem: wcnss_fw_region@0 { |
| 55 | compatible = "removed-dma-pool"; |
| 56 | no-map; |
| 57 | reg = <0x0 0x8e700000 0x0 0x700000>; |
| 58 | }; |
| 59 | |
| 60 | venus_mem: venus_region@0 { |
| 61 | compatible = "shared-dma-pool"; |
| 62 | reusable; |
| 63 | alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; |
| 64 | alignment = <0 0x400000>; |
| 65 | size = <0 0x0800000>; |
| 66 | }; |
| 67 | |
| 68 | secure_mem: secure_region@0 { |
| 69 | compatible = "shared-dma-pool"; |
| 70 | reusable; |
| 71 | alignment = <0 0x400000>; |
| 72 | size = <0 0x09800000>; |
| 73 | }; |
| 74 | |
| 75 | qseecom_mem: qseecom_region@0 { |
| 76 | compatible = "shared-dma-pool"; |
| 77 | reusable; |
| 78 | alignment = <0 0x400000>; |
| 79 | size = <0 0x1000000>; |
| 80 | }; |
| 81 | |
| 82 | adsp_mem: adsp_region@0 { |
| 83 | compatible = "shared-dma-pool"; |
| 84 | reusable; |
| 85 | size = <0 0x400000>; |
| 86 | }; |
| 87 | |
| 88 | dfps_data_mem: dfps_data_mem@90000000 { |
| 89 | reg = <0 0x90000000 0 0x1000>; |
| 90 | label = "dfps_data_mem"; |
| 91 | }; |
| 92 | |
| 93 | cont_splash_mem: splash_region@0x90001000 { |
| 94 | reg = <0x0 0x90001000 0x0 0x13ff000>; |
| 95 | label = "cont_splash_mem"; |
| 96 | }; |
| 97 | |
| 98 | gpu_mem: gpu_region@0 { |
| 99 | compatible = "shared-dma-pool"; |
| 100 | reusable; |
| 101 | alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; |
| 102 | alignment = <0 0x400000>; |
| 103 | size = <0 0x800000>; |
| 104 | }; |
| 105 | }; |
| 106 | |
| 107 | aliases { |
| 108 | /* smdtty devices */ |
Arun Kumar Neelakantam | 36151aa | 2017-11-02 21:34:33 +0530 | [diff] [blame] | 109 | smd1 = &smdtty_apps_fm; |
| 110 | smd2 = &smdtty_apps_riva_bt_acl; |
| 111 | smd3 = &smdtty_apps_riva_bt_cmd; |
| 112 | smd4 = &smdtty_mbalbridge; |
| 113 | smd5 = &smdtty_apps_riva_ant_cmd; |
| 114 | smd6 = &smdtty_apps_riva_ant_data; |
| 115 | smd7 = &smdtty_data1; |
| 116 | smd8 = &smdtty_data4; |
| 117 | smd11 = &smdtty_data11; |
| 118 | smd21 = &smdtty_data21; |
| 119 | smd36 = &smdtty_loopback; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 120 | sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ |
| 121 | sdhc2 = &sdhc_2; /* SDC2 for SD card */ |
| 122 | }; |
| 123 | |
| 124 | soc: soc { }; |
| 125 | |
| 126 | }; |
| 127 | |
| 128 | #include "msm8953-pinctrl.dtsi" |
| 129 | #include "msm8953-cpu.dtsi" |
Raju P.L.S.S.S.N | e0b22c9 | 2017-11-02 13:42:27 +0530 | [diff] [blame] | 130 | #include "msm8953-pm.dtsi" |
Odelu Kukatla | 1a81104 | 2017-10-29 17:26:44 +0530 | [diff] [blame] | 131 | #include "msm8953-bus.dtsi" |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 132 | |
| 133 | |
| 134 | &soc { |
| 135 | #address-cells = <1>; |
| 136 | #size-cells = <1>; |
| 137 | ranges = <0 0 0 0xffffffff>; |
| 138 | compatible = "simple-bus"; |
| 139 | |
| 140 | apc_apm: apm@b111000 { |
| 141 | compatible = "qcom,msm8953-apm"; |
| 142 | reg = <0xb111000 0x1000>; |
| 143 | reg-names = "pm-apcc-glb"; |
| 144 | qcom,apm-post-halt-delay = <0x2>; |
| 145 | qcom,apm-halt-clk-delay = <0x11>; |
| 146 | qcom,apm-resume-clk-delay = <0x10>; |
| 147 | qcom,apm-sel-switch-delay = <0x01>; |
| 148 | }; |
| 149 | |
| 150 | intc: interrupt-controller@b000000 { |
| 151 | compatible = "qcom,msm-qgic2"; |
| 152 | interrupt-controller; |
| 153 | #interrupt-cells = <3>; |
| 154 | reg = <0x0b000000 0x1000>, |
| 155 | <0x0b002000 0x1000>; |
| 156 | }; |
| 157 | |
| 158 | qcom,msm-gladiator@b1c0000 { |
| 159 | compatible = "qcom,msm-gladiator"; |
| 160 | reg = <0x0b1c0000 0x4000>; |
| 161 | reg-names = "gladiator_base"; |
| 162 | interrupts = <0 22 0>; |
| 163 | }; |
| 164 | |
| 165 | timer { |
| 166 | compatible = "arm,armv8-timer"; |
| 167 | interrupts = <1 2 0xff08>, |
| 168 | <1 3 0xff08>, |
| 169 | <1 4 0xff08>, |
| 170 | <1 1 0xff08>; |
| 171 | clock-frequency = <19200000>; |
| 172 | }; |
| 173 | |
| 174 | timer@b120000 { |
| 175 | #address-cells = <1>; |
| 176 | #size-cells = <1>; |
| 177 | ranges; |
| 178 | compatible = "arm,armv7-timer-mem"; |
| 179 | reg = <0xb120000 0x1000>; |
| 180 | clock-frequency = <19200000>; |
| 181 | |
| 182 | frame@b121000 { |
| 183 | frame-number = <0>; |
| 184 | interrupts = <0 8 0x4>, |
| 185 | <0 7 0x4>; |
| 186 | reg = <0xb121000 0x1000>, |
| 187 | <0xb122000 0x1000>; |
| 188 | }; |
| 189 | |
| 190 | frame@b123000 { |
| 191 | frame-number = <1>; |
| 192 | interrupts = <0 9 0x4>; |
| 193 | reg = <0xb123000 0x1000>; |
| 194 | status = "disabled"; |
| 195 | }; |
| 196 | |
| 197 | frame@b124000 { |
| 198 | frame-number = <2>; |
| 199 | interrupts = <0 10 0x4>; |
| 200 | reg = <0xb124000 0x1000>; |
| 201 | status = "disabled"; |
| 202 | }; |
| 203 | |
| 204 | frame@b125000 { |
| 205 | frame-number = <3>; |
| 206 | interrupts = <0 11 0x4>; |
| 207 | reg = <0xb125000 0x1000>; |
| 208 | status = "disabled"; |
| 209 | }; |
| 210 | |
| 211 | frame@b126000 { |
| 212 | frame-number = <4>; |
| 213 | interrupts = <0 12 0x4>; |
| 214 | reg = <0xb126000 0x1000>; |
| 215 | status = "disabled"; |
| 216 | }; |
| 217 | |
| 218 | frame@b127000 { |
| 219 | frame-number = <5>; |
| 220 | interrupts = <0 13 0x4>; |
| 221 | reg = <0xb127000 0x1000>; |
| 222 | status = "disabled"; |
| 223 | }; |
| 224 | |
| 225 | frame@b128000 { |
| 226 | frame-number = <6>; |
| 227 | interrupts = <0 14 0x4>; |
| 228 | reg = <0xb128000 0x1000>; |
| 229 | status = "disabled"; |
| 230 | }; |
| 231 | }; |
| 232 | qcom,rmtfs_sharedmem@00000000 { |
| 233 | compatible = "qcom,sharedmem-uio"; |
| 234 | reg = <0x00000000 0x00180000>; |
| 235 | reg-names = "rmtfs"; |
| 236 | qcom,client-id = <0x00000001>; |
| 237 | }; |
| 238 | |
| 239 | restart@4ab000 { |
| 240 | compatible = "qcom,pshold"; |
| 241 | reg = <0x4ab000 0x4>, |
| 242 | <0x193d100 0x4>; |
| 243 | reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| 244 | }; |
| 245 | |
| 246 | qcom,mpm2-sleep-counter@4a3000 { |
| 247 | compatible = "qcom,mpm2-sleep-counter"; |
| 248 | reg = <0x4a3000 0x1000>; |
| 249 | clock-frequency = <32768>; |
| 250 | }; |
| 251 | |
| 252 | cpu-pmu { |
| 253 | compatible = "arm,armv8-pmuv3"; |
| 254 | interrupts = <1 7 0xff00>; |
| 255 | }; |
| 256 | |
| 257 | qcom,sps { |
| 258 | compatible = "qcom,msm_sps_4k"; |
| 259 | qcom,pipe-attr-ee; |
| 260 | }; |
| 261 | |
Ashok Jammigumpula | db43f57 | 2017-12-06 18:05:57 +0530 | [diff] [blame] | 262 | thermal_zones: thermal-zones { |
| 263 | mdm-core-usr { |
| 264 | polling-delay-passive = <0>; |
| 265 | polling-delay = <0>; |
| 266 | thermal-governor = "user_space"; |
| 267 | thermal-sensors = <&tsens0 1>; |
| 268 | trips { |
| 269 | active-config0 { |
| 270 | temperature = <125000>; |
| 271 | hysteresis = <1000>; |
| 272 | type = "passive"; |
| 273 | }; |
| 274 | }; |
| 275 | }; |
| 276 | |
| 277 | qdsp-usr { |
| 278 | polling-delay-passive = <0>; |
| 279 | polling-delay = <0>; |
| 280 | thermal-governor = "user_space"; |
| 281 | thermal-sensors = <&tsens0 2>; |
| 282 | trips { |
| 283 | active-config0 { |
| 284 | temperature = <125000>; |
| 285 | hysteresis = <1000>; |
| 286 | type = "passive"; |
| 287 | }; |
| 288 | }; |
| 289 | }; |
| 290 | |
| 291 | camera-usr { |
| 292 | polling-delay-passive = <0>; |
| 293 | polling-delay = <0>; |
| 294 | thermal-governor = "user_space"; |
| 295 | thermal-sensors = <&tsens0 3>; |
| 296 | trips { |
| 297 | active-config0 { |
| 298 | temperature = <125000>; |
| 299 | hysteresis = <1000>; |
| 300 | type = "passive"; |
| 301 | }; |
| 302 | }; |
| 303 | }; |
| 304 | |
| 305 | apc1_cpu0-usr { |
| 306 | polling-delay-passive = <0>; |
| 307 | polling-delay = <0>; |
| 308 | thermal-sensors = <&tsens0 4>; |
| 309 | thermal-governor = "user_space"; |
| 310 | trips { |
| 311 | active-config0 { |
| 312 | temperature = <125000>; |
| 313 | hysteresis = <1000>; |
| 314 | type = "passive"; |
| 315 | }; |
| 316 | }; |
| 317 | }; |
| 318 | |
| 319 | apc1_cpu1-usr { |
| 320 | polling-delay-passive = <0>; |
| 321 | polling-delay = <0>; |
| 322 | thermal-sensors = <&tsens0 5>; |
| 323 | thermal-governor = "user_space"; |
| 324 | trips { |
| 325 | active-config0 { |
| 326 | temperature = <125000>; |
| 327 | hysteresis = <1000>; |
| 328 | type = "passive"; |
| 329 | }; |
| 330 | }; |
| 331 | }; |
| 332 | |
| 333 | apc1_cpu2-usr { |
| 334 | polling-delay-passive = <0>; |
| 335 | polling-delay = <0>; |
| 336 | thermal-sensors = <&tsens0 6>; |
| 337 | thermal-governor = "user_space"; |
| 338 | trips { |
| 339 | active-config0 { |
| 340 | temperature = <125000>; |
| 341 | hysteresis = <1000>; |
| 342 | type = "passive"; |
| 343 | }; |
| 344 | }; |
| 345 | }; |
| 346 | |
| 347 | apc1_cpu3-usr { |
| 348 | polling-delay-passive = <0>; |
| 349 | polling-delay = <0>; |
| 350 | thermal-sensors = <&tsens0 7>; |
| 351 | thermal-governor = "user_space"; |
| 352 | trips { |
| 353 | active-config0 { |
| 354 | temperature = <125000>; |
| 355 | hysteresis = <1000>; |
| 356 | type = "passive"; |
| 357 | }; |
| 358 | }; |
| 359 | }; |
| 360 | |
| 361 | apc1_l2-usr { |
| 362 | polling-delay-passive = <0>; |
| 363 | polling-delay = <0>; |
| 364 | thermal-sensors = <&tsens0 8>; |
| 365 | thermal-governor = "user_space"; |
| 366 | trips { |
| 367 | active-config0 { |
| 368 | temperature = <125000>; |
| 369 | hysteresis = <1000>; |
| 370 | type = "passive"; |
| 371 | }; |
| 372 | }; |
| 373 | }; |
| 374 | |
| 375 | apc0_cpu0-usr { |
| 376 | polling-delay-passive = <0>; |
| 377 | polling-delay = <0>; |
| 378 | thermal-sensors = <&tsens0 9>; |
| 379 | thermal-governor = "user_space"; |
| 380 | trips { |
| 381 | active-config0 { |
| 382 | temperature = <125000>; |
| 383 | hysteresis = <1000>; |
| 384 | type = "passive"; |
| 385 | }; |
| 386 | }; |
| 387 | }; |
| 388 | |
| 389 | apc0_cpu1-usr { |
| 390 | polling-delay-passive = <0>; |
| 391 | polling-delay = <0>; |
| 392 | thermal-sensors = <&tsens0 10>; |
| 393 | thermal-governor = "user_space"; |
| 394 | trips { |
| 395 | active-config0 { |
| 396 | temperature = <125000>; |
| 397 | hysteresis = <1000>; |
| 398 | type = "passive"; |
| 399 | }; |
| 400 | }; |
| 401 | }; |
| 402 | |
| 403 | apc0_cpu2-usr { |
| 404 | polling-delay-passive = <0>; |
| 405 | polling-delay = <0>; |
| 406 | thermal-sensors = <&tsens0 11>; |
| 407 | thermal-governor = "user_space"; |
| 408 | trips { |
| 409 | active-config0 { |
| 410 | temperature = <125000>; |
| 411 | hysteresis = <1000>; |
| 412 | type = "passive"; |
| 413 | }; |
| 414 | }; |
| 415 | }; |
| 416 | |
| 417 | apc0_cpu3-usr { |
| 418 | polling-delay-passive = <0>; |
| 419 | polling-delay = <0>; |
| 420 | thermal-sensors = <&tsens0 12>; |
| 421 | thermal-governor = "user_space"; |
| 422 | trips { |
| 423 | active-config0 { |
| 424 | temperature = <125000>; |
| 425 | hysteresis = <1000>; |
| 426 | type = "passive"; |
| 427 | }; |
| 428 | }; |
| 429 | }; |
| 430 | |
| 431 | apc0_l2-usr { |
| 432 | polling-delay-passive = <0>; |
| 433 | polling-delay = <0>; |
| 434 | thermal-sensors = <&tsens0 13>; |
| 435 | thermal-governor = "user_space"; |
| 436 | trips { |
| 437 | active-config0 { |
| 438 | temperature = <125000>; |
| 439 | hysteresis = <1000>; |
| 440 | type = "passive"; |
| 441 | }; |
| 442 | }; |
| 443 | }; |
| 444 | |
| 445 | gpu0-usr { |
| 446 | polling-delay-passive = <0>; |
| 447 | polling-delay = <0>; |
| 448 | thermal-sensors = <&tsens0 14>; |
| 449 | thermal-governor = "user_space"; |
| 450 | trips { |
| 451 | active-config0 { |
| 452 | temperature = <125000>; |
| 453 | hysteresis = <1000>; |
| 454 | type = "passive"; |
| 455 | }; |
| 456 | }; |
| 457 | }; |
| 458 | |
| 459 | gpu1-usr { |
| 460 | polling-delay-passive = <0>; |
| 461 | polling-delay = <0>; |
| 462 | thermal-sensors = <&tsens0 15>; |
| 463 | thermal-governor = "user_space"; |
| 464 | trips { |
| 465 | active-config0 { |
| 466 | temperature = <125000>; |
| 467 | hysteresis = <1000>; |
| 468 | type = "passive"; |
| 469 | }; |
| 470 | }; |
| 471 | }; |
| 472 | }; |
| 473 | |
| 474 | tsens0: tsens@4a8000 { |
| 475 | compatible = "qcom,msm8953-tsens"; |
| 476 | reg = <0x4a8000 0x1000>, |
| 477 | <0x4a9000 0x1000>; |
| 478 | reg-names = "tsens_srot_physical", |
| 479 | "tsens_tm_physical"; |
| 480 | interrupts = <0 184 0>, <0 314 0>; |
| 481 | interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| 482 | #thermal-sensor-cells = <1>; |
| 483 | }; |
| 484 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 485 | blsp1_uart0: serial@78af000 { |
| 486 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 487 | reg = <0x78af000 0x200>; |
| 488 | interrupts = <0 107 0>; |
Maria Yu | af0e925 | 2017-11-30 19:58:44 +0800 | [diff] [blame] | 489 | clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, |
| 490 | <&clock_gcc clk_gcc_blsp1_ahb_clk>; |
| 491 | clock-names = "core", "iface"; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 492 | status = "disabled"; |
| 493 | }; |
| 494 | |
| 495 | dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */ |
| 496 | #dma-cells = <4>; |
| 497 | compatible = "qcom,sps-dma"; |
| 498 | reg = <0x7884000 0x1f000>; |
| 499 | interrupts = <0 238 0>; |
| 500 | qcom,summing-threshold = <10>; |
| 501 | }; |
| 502 | |
| 503 | dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */ |
| 504 | #dma-cells = <4>; |
| 505 | compatible = "qcom,sps-dma"; |
| 506 | reg = <0x7ac4000 0x1f000>; |
| 507 | interrupts = <0 239 0>; |
| 508 | qcom,summing-threshold = <10>; |
| 509 | }; |
| 510 | |
| 511 | slim_msm: slim@c140000{ |
| 512 | cell-index = <1>; |
| 513 | compatible = "qcom,slim-ngd"; |
| 514 | reg = <0xc140000 0x2c000>, |
| 515 | <0xc104000 0x2a000>; |
| 516 | reg-names = "slimbus_physical", "slimbus_bam_physical"; |
| 517 | interrupts = <0 163 0>, <0 180 0>; |
| 518 | interrupt-names = "slimbus_irq", "slimbus_bam_irq"; |
| 519 | qcom,apps-ch-pipes = <0x600000>; |
| 520 | qcom,ea-pc = <0x200>; |
| 521 | status = "disabled"; |
| 522 | }; |
| 523 | |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 524 | clock_gcc: qcom,gcc@1800000 { |
| 525 | compatible = "qcom,gcc-8953"; |
| 526 | reg = <0x1800000 0x80000>, |
| 527 | <0x00a4124 0x08>; |
| 528 | reg-names = "cc_base", "efuse"; |
| 529 | vdd_dig-supply = <&pm8953_s2_level>; |
| 530 | #clock-cells = <1>; |
| 531 | #reset-cells = <1>; |
| 532 | }; |
| 533 | |
| 534 | clock_debug: qcom,cc-debug@1874000 { |
| 535 | compatible = "qcom,cc-debug-8953"; |
| 536 | reg = <0x1874000 0x4>; |
| 537 | reg-names = "cc_base"; |
| 538 | clocks = <&clock_cpu clk_cpu_debug_pri_mux>; |
| 539 | clock-names = "debug_cpu_clk"; |
| 540 | #clock-cells = <1>; |
| 541 | }; |
| 542 | |
| 543 | clock_gcc_gfx: qcom,gcc-gfx@1800000 { |
| 544 | compatible = "qcom,gcc-gfx-8953"; |
| 545 | reg = <0x1800000 0x80000>; |
| 546 | reg-names = "cc_base"; |
| 547 | vdd_gfx-supply = <&gfx_vreg_corner>; |
| 548 | qcom,gfxfreq-corner = |
| 549 | < 0 0 >, |
| 550 | < 133330000 1 >, /* Min SVS */ |
| 551 | < 216000000 2 >, /* Low SVS */ |
| 552 | < 320000000 3 >, /* SVS */ |
| 553 | < 400000000 4 >, /* SVS Plus */ |
| 554 | < 510000000 5 >, /* NOM */ |
| 555 | < 560000000 6 >, /* Nom Plus */ |
| 556 | < 650000000 7 >; /* Turbo */ |
| 557 | #clock-cells = <1>; |
| 558 | }; |
| 559 | |
| 560 | clock_cpu: qcom,cpu-clock-8953@b116000 { |
| 561 | compatible = "qcom,cpu-clock-8953"; |
| 562 | reg = <0xb114000 0x68>, |
| 563 | <0xb014000 0x68>, |
| 564 | <0xb116000 0x400>, |
| 565 | <0xb111050 0x08>, |
| 566 | <0xb011050 0x08>, |
| 567 | <0xb1d1050 0x08>, |
| 568 | <0x00a4124 0x08>; |
| 569 | reg-names = "rcgwr-c0-base", "rcgwr-c1-base", |
| 570 | "c0-pll", "c0-mux", "c1-mux", |
| 571 | "cci-mux", "efuse"; |
| 572 | vdd-mx-supply = <&pm8953_s7_level_ao>; |
| 573 | vdd-cl-supply = <&apc_vreg>; |
| 574 | clocks = <&clock_gcc clk_xo_a_clk_src>; |
| 575 | clock-names = "xo_a"; |
| 576 | qcom,num-clusters = <2>; |
| 577 | qcom,speed0-bin-v0-cl = |
| 578 | < 0 0>, |
| 579 | < 652800000 1>, |
| 580 | < 1036800000 2>, |
| 581 | < 1401600000 3>, |
| 582 | < 1689600000 4>, |
| 583 | < 1804800000 5>, |
| 584 | < 1958400000 6>, |
| 585 | < 2016000000 7>; |
| 586 | qcom,speed0-bin-v0-cci = |
| 587 | < 0 0>, |
| 588 | < 261120000 1>, |
| 589 | < 414720000 2>, |
| 590 | < 560640000 3>, |
| 591 | < 675840000 4>, |
| 592 | < 721920000 5>, |
| 593 | < 783360000 6>, |
| 594 | < 806400000 7>; |
| 595 | qcom,speed2-bin-v0-cl = |
| 596 | < 0 0>, |
| 597 | < 652800000 1>, |
| 598 | < 1036800000 2>, |
| 599 | < 1401600000 3>, |
| 600 | < 1689600000 4>, |
| 601 | < 1804800000 5>, |
| 602 | < 1958400000 6>, |
| 603 | < 2016000000 7>; |
| 604 | qcom,speed2-bin-v0-cci = |
| 605 | < 0 0>, |
| 606 | < 261120000 1>, |
| 607 | < 414720000 2>, |
| 608 | < 560640000 3>, |
| 609 | < 675840000 4>, |
| 610 | < 721920000 5>, |
| 611 | < 783360000 6>, |
| 612 | < 806400000 7>; |
| 613 | qcom,speed7-bin-v0-cl = |
| 614 | < 0 0>, |
| 615 | < 652800000 1>, |
| 616 | < 1036800000 2>, |
| 617 | < 1401600000 3>, |
| 618 | < 1689600000 4>, |
| 619 | < 1804800000 5>, |
| 620 | < 1958400000 6>, |
| 621 | < 2016000000 7>, |
| 622 | < 2150400000 8>, |
| 623 | < 2208000000 9>; |
| 624 | qcom,speed7-bin-v0-cci = |
| 625 | < 0 0>, |
| 626 | < 261120000 1>, |
| 627 | < 414720000 2>, |
| 628 | < 560640000 3>, |
| 629 | < 675840000 4>, |
| 630 | < 721920000 5>, |
| 631 | < 783360000 6>, |
| 632 | < 806400000 7>, |
| 633 | < 860160000 8>, |
| 634 | < 883200000 9>; |
| 635 | qcom,speed6-bin-v0-cl = |
| 636 | < 0 0>, |
| 637 | < 652800000 1>, |
| 638 | < 1036800000 2>, |
| 639 | < 1401600000 3>, |
| 640 | < 1689600000 4>, |
| 641 | < 1804800000 5>; |
| 642 | qcom,speed6-bin-v0-cci = |
| 643 | < 0 0>, |
| 644 | < 261120000 1>, |
| 645 | < 414720000 2>, |
| 646 | < 560640000 3>, |
| 647 | < 675840000 4>, |
| 648 | < 721920000 5>; |
| 649 | #clock-cells = <1>; |
Maria Yu | b90c548 | 2017-12-01 13:28:56 +0800 | [diff] [blame] | 650 | }; |
| 651 | |
| 652 | msm_cpufreq: qcom,msm-cpufreq { |
| 653 | compatible = "qcom,msm-cpufreq"; |
| 654 | clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", |
| 655 | "cpu3_clk", "cpu4_clk", "cpu5_clk", |
| 656 | "cpu6_clk", "cpu7_clk"; |
| 657 | clocks = <&clock_cpu clk_cci_clk>, |
| 658 | <&clock_cpu clk_a53_pwr_clk>, |
| 659 | <&clock_cpu clk_a53_pwr_clk>, |
| 660 | <&clock_cpu clk_a53_pwr_clk>, |
| 661 | <&clock_cpu clk_a53_pwr_clk>, |
| 662 | <&clock_cpu clk_a53_pwr_clk>, |
| 663 | <&clock_cpu clk_a53_pwr_clk>, |
| 664 | <&clock_cpu clk_a53_pwr_clk>, |
| 665 | <&clock_cpu clk_a53_pwr_clk>; |
| 666 | |
| 667 | qcom,cpufreq-table = |
| 668 | < 652800 >, |
| 669 | < 1036800 >, |
| 670 | < 1401600 >, |
| 671 | < 1689600 >, |
| 672 | < 1804800 >, |
| 673 | < 1958400 >, |
| 674 | < 2016000 >, |
| 675 | < 2150400 >, |
| 676 | < 2208000 >; |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 677 | }; |
| 678 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 679 | cpubw: qcom,cpubw { |
| 680 | compatible = "qcom,devbw"; |
| 681 | governor = "cpufreq"; |
| 682 | qcom,src-dst-ports = <1 512>; |
| 683 | qcom,active-only; |
| 684 | qcom,bw-tbl = |
| 685 | < 769 /* 100.8 MHz */ >, |
| 686 | < 1611 /* 211.2 MHz */ >, /*Low SVS*/ |
| 687 | < 2124 /* 278.4 MHz */ >, |
| 688 | < 2929 /* 384 MHz */ >, |
| 689 | < 3221 /* 422.4 MHz */ >, /* SVS */ |
| 690 | < 4248 /* 556.8 MHz */ >, |
| 691 | < 5126 /* 672 MHz */ >, |
| 692 | < 5859 /* 768 MHz */ >, /* SVS+ */ |
| 693 | < 6152 /* 806.4 MHz */ >, |
| 694 | < 6445 /* 844.8 MHz */ >, /* NOM */ |
| 695 | < 7104 /* 931.2 MHz */ >; /* TURBO */ |
| 696 | }; |
| 697 | |
| 698 | mincpubw: qcom,mincpubw { |
| 699 | compatible = "qcom,devbw"; |
| 700 | governor = "cpufreq"; |
| 701 | qcom,src-dst-ports = <1 512>; |
| 702 | qcom,active-only; |
| 703 | qcom,bw-tbl = |
| 704 | < 769 /* 100.8 MHz */ >, |
| 705 | < 1611 /* 211.2 MHz */ >, /*Low SVS*/ |
| 706 | < 2124 /* 278.4 MHz */ >, |
| 707 | < 2929 /* 384 MHz */ >, |
| 708 | < 3221 /* 422.4 MHz */ >, /* SVS */ |
| 709 | < 4248 /* 556.8 MHz */ >, |
| 710 | < 5126 /* 672 MHz */ >, |
| 711 | < 5859 /* 768 MHz */ >, /* SVS+ */ |
| 712 | < 6152 /* 806.4 MHz */ >, |
| 713 | < 6445 /* 844.8 MHz */ >, /* NOM */ |
| 714 | < 7104 /* 931.2 MHz */ >; /* TURBO */ |
| 715 | }; |
| 716 | |
| 717 | qcom,cpu-bwmon { |
| 718 | compatible = "qcom,bimc-bwmon2"; |
| 719 | reg = <0x408000 0x300>, <0x401000 0x200>; |
| 720 | reg-names = "base", "global_base"; |
| 721 | interrupts = <0 183 4>; |
| 722 | qcom,mport = <0>; |
| 723 | qcom,target-dev = <&cpubw>; |
| 724 | }; |
| 725 | |
| 726 | devfreq-cpufreq { |
| 727 | cpubw-cpufreq { |
| 728 | target-dev = <&cpubw>; |
| 729 | cpu-to-dev-map = |
| 730 | < 652800 1611>, |
| 731 | < 1036800 3221>, |
| 732 | < 1401600 5859>, |
| 733 | < 1689600 6445>, |
| 734 | < 1804800 7104>, |
| 735 | < 1958400 7104>, |
| 736 | < 2208000 7104>; |
| 737 | }; |
| 738 | |
| 739 | mincpubw-cpufreq { |
| 740 | target-dev = <&mincpubw>; |
| 741 | cpu-to-dev-map = |
| 742 | < 652800 1611 >, |
| 743 | < 1401600 3221 >, |
| 744 | < 2208000 5859 >; |
| 745 | }; |
| 746 | }; |
| 747 | |
Jonathan Avila | c7a6fd5 | 2017-10-12 15:24:05 -0700 | [diff] [blame] | 748 | cpubw_compute: qcom,cpubw-compute { |
| 749 | compatible = "qcom,arm-cpu-mon"; |
| 750 | qcom,cpulist = < &CPU0 &CPU1 &CPU2 &CPU3 |
| 751 | &CPU4 &CPU5 &CPU6 &CPU7 >; |
| 752 | qcom,target-dev = <&cpubw>; |
| 753 | qcom,core-dev-table = |
| 754 | < 652800 1611>, |
| 755 | < 1036800 3221>, |
| 756 | < 1401600 5859>, |
| 757 | < 1689600 6445>, |
| 758 | < 1804800 7104>, |
| 759 | < 1958400 7104>, |
| 760 | < 2208000 7104>; |
| 761 | }; |
| 762 | |
| 763 | mincpubw_compute: qcom,mincpubw-compute { |
| 764 | compatible = "qcom,arm-cpu-mon"; |
| 765 | qcom,cpulist = < &CPU0 &CPU1 &CPU2 &CPU3 |
| 766 | &CPU4 &CPU5 &CPU6 &CPU7 >; |
| 767 | qcom,target-dev = <&mincpubw>; |
| 768 | qcom,core-dev-table = |
| 769 | < 652800 1611 >, |
| 770 | < 1401600 3221 >, |
| 771 | < 2208000 5859 >; |
| 772 | }; |
| 773 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 774 | qcom,ipc-spinlock@1905000 { |
| 775 | compatible = "qcom,ipc-spinlock-sfpb"; |
| 776 | reg = <0x1905000 0x8000>; |
| 777 | qcom,num-locks = <8>; |
| 778 | }; |
| 779 | |
| 780 | qcom,smem@86300000 { |
| 781 | compatible = "qcom,smem"; |
| 782 | reg = <0x86300000 0x100000>, |
| 783 | <0x0b011008 0x4>, |
| 784 | <0x60000 0x8000>, |
| 785 | <0x193d000 0x8>; |
| 786 | reg-names = "smem", "irq-reg-base", |
| 787 | "aux-mem1", "smem_targ_info_reg"; |
| 788 | qcom,mpu-enabled; |
| 789 | |
| 790 | qcom,smd-modem { |
| 791 | compatible = "qcom,smd"; |
| 792 | qcom,smd-edge = <0>; |
| 793 | qcom,smd-irq-offset = <0x0>; |
| 794 | qcom,smd-irq-bitmask = <0x1000>; |
| 795 | interrupts = <0 25 1>; |
| 796 | label = "modem"; |
| 797 | qcom,not-loadable; |
| 798 | }; |
| 799 | |
| 800 | qcom,smsm-modem { |
| 801 | compatible = "qcom,smsm"; |
| 802 | qcom,smsm-edge = <0>; |
| 803 | qcom,smsm-irq-offset = <0x0>; |
| 804 | qcom,smsm-irq-bitmask = <0x2000>; |
| 805 | interrupts = <0 26 1>; |
| 806 | }; |
| 807 | |
| 808 | qcom,smd-wcnss { |
| 809 | compatible = "qcom,smd"; |
| 810 | qcom,smd-edge = <6>; |
| 811 | qcom,smd-irq-offset = <0x0>; |
| 812 | qcom,smd-irq-bitmask = <0x20000>; |
| 813 | interrupts = <0 142 1>; |
| 814 | label = "wcnss"; |
| 815 | }; |
| 816 | |
| 817 | qcom,smsm-wcnss { |
| 818 | compatible = "qcom,smsm"; |
| 819 | qcom,smsm-edge = <6>; |
| 820 | qcom,smsm-irq-offset = <0x0>; |
| 821 | qcom,smsm-irq-bitmask = <0x80000>; |
| 822 | interrupts = <0 144 1>; |
| 823 | }; |
| 824 | |
| 825 | qcom,smd-adsp { |
| 826 | compatible = "qcom,smd"; |
| 827 | qcom,smd-edge = <1>; |
| 828 | qcom,smd-irq-offset = <0x0>; |
| 829 | qcom,smd-irq-bitmask = <0x100>; |
| 830 | interrupts = <0 289 1>; |
| 831 | label = "adsp"; |
| 832 | }; |
| 833 | |
| 834 | qcom,smsm-adsp { |
| 835 | compatible = "qcom,smsm"; |
| 836 | qcom,smsm-edge = <1>; |
| 837 | qcom,smsm-irq-offset = <0x0>; |
| 838 | qcom,smsm-irq-bitmask = <0x200>; |
| 839 | interrupts = <0 290 1>; |
| 840 | }; |
| 841 | |
| 842 | qcom,smd-rpm { |
| 843 | compatible = "qcom,smd"; |
| 844 | qcom,smd-edge = <15>; |
| 845 | qcom,smd-irq-offset = <0x0>; |
| 846 | qcom,smd-irq-bitmask = <0x1>; |
| 847 | interrupts = <0 168 1>; |
| 848 | label = "rpm"; |
| 849 | qcom,irq-no-suspend; |
| 850 | qcom,not-loadable; |
| 851 | }; |
| 852 | }; |
| 853 | |
Arun Kumar Neelakantam | 36151aa | 2017-11-02 21:34:33 +0530 | [diff] [blame] | 854 | qcom,smdtty { |
| 855 | compatible = "qcom,smdtty"; |
| 856 | |
| 857 | smdtty_apps_fm: qcom,smdtty-apps-fm { |
| 858 | qcom,smdtty-remote = "wcnss"; |
| 859 | qcom,smdtty-port-name = "APPS_FM"; |
| 860 | }; |
| 861 | |
| 862 | smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl { |
| 863 | qcom,smdtty-remote = "wcnss"; |
| 864 | qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; |
| 865 | }; |
| 866 | |
| 867 | smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd { |
| 868 | qcom,smdtty-remote = "wcnss"; |
| 869 | qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; |
| 870 | }; |
| 871 | |
| 872 | smdtty_mbalbridge: qcom,smdtty-mbalbridge { |
| 873 | qcom,smdtty-remote = "modem"; |
| 874 | qcom,smdtty-port-name = "MBALBRIDGE"; |
| 875 | }; |
| 876 | |
| 877 | smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd { |
| 878 | qcom,smdtty-remote = "wcnss"; |
| 879 | qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; |
| 880 | }; |
| 881 | |
| 882 | smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data { |
| 883 | qcom,smdtty-remote = "wcnss"; |
| 884 | qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; |
| 885 | }; |
| 886 | |
| 887 | smdtty_data1: qcom,smdtty-data1 { |
| 888 | qcom,smdtty-remote = "modem"; |
| 889 | qcom,smdtty-port-name = "DATA1"; |
| 890 | }; |
| 891 | |
| 892 | smdtty_data4: qcom,smdtty-data4 { |
| 893 | qcom,smdtty-remote = "modem"; |
| 894 | qcom,smdtty-port-name = "DATA4"; |
| 895 | }; |
| 896 | |
| 897 | smdtty_data11: qcom,smdtty-data11 { |
| 898 | qcom,smdtty-remote = "modem"; |
| 899 | qcom,smdtty-port-name = "DATA11"; |
| 900 | }; |
| 901 | |
| 902 | smdtty_data21: qcom,smdtty-data21 { |
| 903 | qcom,smdtty-remote = "modem"; |
| 904 | qcom,smdtty-port-name = "DATA21"; |
| 905 | }; |
| 906 | |
| 907 | smdtty_loopback: smdtty-loopback { |
| 908 | qcom,smdtty-remote = "modem"; |
| 909 | qcom,smdtty-port-name = "LOOPBACK"; |
| 910 | qcom,smdtty-dev-name = "LOOPBACK_TTY"; |
| 911 | }; |
| 912 | }; |
| 913 | |
Arun Kumar Neelakantam | ea07e3d | 2017-11-02 21:27:50 +0530 | [diff] [blame] | 914 | qcom,smdpkt { |
| 915 | compatible = "qcom,smdpkt"; |
| 916 | |
| 917 | qcom,smdpkt-data5-cntl { |
| 918 | qcom,smdpkt-remote = "modem"; |
| 919 | qcom,smdpkt-port-name = "DATA5_CNTL"; |
| 920 | qcom,smdpkt-dev-name = "smdcntl0"; |
| 921 | }; |
| 922 | |
| 923 | qcom,smdpkt-data22 { |
| 924 | qcom,smdpkt-remote = "modem"; |
| 925 | qcom,smdpkt-port-name = "DATA22"; |
| 926 | qcom,smdpkt-dev-name = "smd22"; |
| 927 | }; |
| 928 | |
| 929 | qcom,smdpkt-data40-cntl { |
| 930 | qcom,smdpkt-remote = "modem"; |
| 931 | qcom,smdpkt-port-name = "DATA40_CNTL"; |
| 932 | qcom,smdpkt-dev-name = "smdcntl8"; |
| 933 | }; |
| 934 | |
| 935 | qcom,smdpkt-apr-apps2 { |
| 936 | qcom,smdpkt-remote = "adsp"; |
| 937 | qcom,smdpkt-port-name = "apr_apps2"; |
| 938 | qcom,smdpkt-dev-name = "apr_apps2"; |
| 939 | }; |
| 940 | |
| 941 | qcom,smdpkt-loopback { |
| 942 | qcom,smdpkt-remote = "modem"; |
| 943 | qcom,smdpkt-port-name = "LOOPBACK"; |
| 944 | qcom,smdpkt-dev-name = "smd_pkt_loopback"; |
| 945 | }; |
| 946 | }; |
| 947 | |
Raju P.L.S.S.S.N | 786994d | 2017-11-08 17:03:56 +0530 | [diff] [blame] | 948 | rpm_bus: qcom,rpm-smd { |
| 949 | compatible = "qcom,rpm-smd"; |
| 950 | rpm-channel-name = "rpm_requests"; |
| 951 | rpm-channel-type = <15>; /* SMD_APPS_RPM */ |
| 952 | }; |
| 953 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 954 | qcom,wdt@b017000 { |
| 955 | compatible = "qcom,msm-watchdog"; |
| 956 | reg = <0xb017000 0x1000>; |
| 957 | reg-names = "wdt-base"; |
| 958 | interrupts = <0 3 0>, <0 4 0>; |
| 959 | qcom,bark-time = <11000>; |
| 960 | qcom,pet-time = <10000>; |
| 961 | qcom,ipi-ping; |
| 962 | qcom,wakeup-enable; |
| 963 | }; |
| 964 | |
| 965 | qcom,chd { |
| 966 | compatible = "qcom,core-hang-detect"; |
| 967 | qcom,threshold-arr = <0xb1880b0 0xb1980b0 0xb1a80b0 |
| 968 | 0xb1b80b0 0xb0880b0 0xb0980b0 0xb0a80b0 0xb0b80b0>; |
| 969 | qcom,config-arr = <0xb1880b8 0xb1980b8 0xb1a80b8 |
| 970 | 0xb1b80b8 0xb0880b8 0xb0980b8 0xb0a80b8 0xb0b80b8>; |
| 971 | }; |
| 972 | |
| 973 | qcom,msm-rtb { |
| 974 | compatible = "qcom,msm-rtb"; |
| 975 | qcom,rtb-size = <0x100000>; |
| 976 | }; |
| 977 | |
| 978 | qcom,msm-imem@8600000 { |
| 979 | compatible = "qcom,msm-imem"; |
| 980 | reg = <0x08600000 0x1000>; |
| 981 | ranges = <0x0 0x08600000 0x1000>; |
| 982 | #address-cells = <1>; |
| 983 | #size-cells = <1>; |
| 984 | |
| 985 | mem_dump_table@10 { |
| 986 | compatible = "qcom,msm-imem-mem_dump_table"; |
| 987 | reg = <0x10 8>; |
| 988 | }; |
| 989 | |
Maria Yu | 06cf96e | 2017-09-21 17:35:13 +0800 | [diff] [blame] | 990 | dload_type@18 { |
| 991 | compatible = "qcom,msm-imem-dload-type"; |
| 992 | reg = <0x18 4>; |
| 993 | }; |
| 994 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 995 | restart_reason@65c { |
| 996 | compatible = "qcom,msm-imem-restart_reason"; |
| 997 | reg = <0x65c 4>; |
| 998 | }; |
| 999 | |
| 1000 | boot_stats@6b0 { |
| 1001 | compatible = "qcom,msm-imem-boot_stats"; |
| 1002 | reg = <0x6b0 32>; |
| 1003 | }; |
| 1004 | |
Maria Yu | 575d67f | 2017-12-05 16:31:19 +0800 | [diff] [blame] | 1005 | kaslr_offset@6d0 { |
| 1006 | compatible = "qcom,msm-imem-kaslr_offset"; |
| 1007 | reg = <0x6d0 12>; |
| 1008 | }; |
| 1009 | |
| 1010 | pil@94c { |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1011 | compatible = "qcom,msm-imem-pil"; |
| 1012 | reg = <0x94c 200>; |
| 1013 | |
| 1014 | }; |
| 1015 | }; |
| 1016 | |
| 1017 | qcom,memshare { |
| 1018 | compatible = "qcom,memshare"; |
| 1019 | |
| 1020 | qcom,client_1 { |
| 1021 | compatible = "qcom,memshare-peripheral"; |
| 1022 | qcom,peripheral-size = <0x200000>; |
| 1023 | qcom,client-id = <0>; |
| 1024 | qcom,allocate-boot-time; |
| 1025 | label = "modem"; |
| 1026 | }; |
| 1027 | |
| 1028 | qcom,client_2 { |
| 1029 | compatible = "qcom,memshare-peripheral"; |
| 1030 | qcom,peripheral-size = <0x300000>; |
| 1031 | qcom,client-id = <2>; |
| 1032 | label = "modem"; |
| 1033 | }; |
| 1034 | |
| 1035 | mem_client_3_size: qcom,client_3 { |
| 1036 | compatible = "qcom,memshare-peripheral"; |
| 1037 | qcom,peripheral-size = <0x0>; |
| 1038 | qcom,client-id = <1>; |
| 1039 | label = "modem"; |
| 1040 | }; |
| 1041 | }; |
| 1042 | sdcc1_ice: sdcc1ice@7803000 { |
| 1043 | compatible = "qcom,ice"; |
| 1044 | reg = <0x7803000 0x8000>; |
| 1045 | interrupt-names = "sdcc_ice_nonsec_level_irq", |
| 1046 | "sdcc_ice_sec_level_irq"; |
| 1047 | interrupts = <0 312 0>, <0 313 0>; |
| 1048 | qcom,enable-ice-clk; |
Sayali Lokhande | 3129993 | 2017-12-06 09:41:17 +0530 | [diff] [blame] | 1049 | clock-names = "ice_core_clk_src", "ice_core_clk", |
| 1050 | "bus_clk", "iface_clk"; |
| 1051 | clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>, |
| 1052 | <&clock_gcc clk_gcc_sdcc1_ice_core_clk>, |
| 1053 | <&clock_gcc clk_gcc_sdcc1_apps_clk>, |
| 1054 | <&clock_gcc clk_gcc_sdcc1_ahb_clk>; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1055 | qcom,op-freq-hz = <270000000>, <0>, <0>, <0>; |
| 1056 | qcom,msm-bus,name = "sdcc_ice_noc"; |
| 1057 | qcom,msm-bus,num-cases = <2>; |
| 1058 | qcom,msm-bus,num-paths = <1>; |
| 1059 | qcom,msm-bus,vectors-KBps = |
| 1060 | <78 512 0 0>, /* No vote */ |
| 1061 | <78 512 1000 0>; /* Max. bandwidth */ |
| 1062 | qcom,bus-vector-names = "MIN", "MAX"; |
| 1063 | qcom,instance-type = "sdcc"; |
| 1064 | }; |
| 1065 | |
| 1066 | sdhc_1: sdhci@7824900 { |
| 1067 | compatible = "qcom,sdhci-msm"; |
| 1068 | reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>; |
| 1069 | reg-names = "hc_mem", "core_mem", "cmdq_mem"; |
| 1070 | |
| 1071 | interrupts = <0 123 0>, <0 138 0>; |
| 1072 | interrupt-names = "hc_irq", "pwr_irq"; |
| 1073 | |
| 1074 | sdhc-msm-crypto = <&sdcc1_ice>; |
| 1075 | qcom,bus-width = <8>; |
| 1076 | |
| 1077 | qcom,devfreq,freq-table = <50000000 200000000>; |
| 1078 | |
| 1079 | qcom,pm-qos-irq-type = "affine_irq"; |
| 1080 | qcom,pm-qos-irq-latency = <2 213>; |
| 1081 | |
| 1082 | qcom,pm-qos-cpu-groups = <0x0f 0xf0>; |
| 1083 | qcom,pm-qos-cmdq-latency-us = <2 213>, <2 213>; |
| 1084 | |
| 1085 | qcom,pm-qos-legacy-latency-us = <2 213>, <2 213>; |
| 1086 | |
| 1087 | qcom,msm-bus,name = "sdhc1"; |
| 1088 | qcom,msm-bus,num-cases = <9>; |
| 1089 | qcom,msm-bus,num-paths = <1>; |
| 1090 | qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ |
| 1091 | <78 512 1046 3200>, /* 400 KB/s*/ |
| 1092 | <78 512 52286 160000>, /* 20 MB/s */ |
| 1093 | <78 512 65360 200000>, /* 25 MB/s */ |
| 1094 | <78 512 130718 400000>, /* 50 MB/s */ |
| 1095 | <78 512 130718 400000>, /* 100 MB/s */ |
| 1096 | <78 512 261438 800000>, /* 200 MB/s */ |
| 1097 | <78 512 261438 800000>, /* 400 MB/s */ |
| 1098 | <78 512 1338562 4096000>; /* Max. bandwidth */ |
| 1099 | qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 1100 | 100000000 200000000 400000000 4294967295>; |
| 1101 | |
Sayali Lokhande | 3129993 | 2017-12-06 09:41:17 +0530 | [diff] [blame] | 1102 | clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, |
| 1103 | <&clock_gcc clk_gcc_sdcc1_apps_clk>, |
| 1104 | <&clock_gcc clk_gcc_sdcc1_ice_core_clk>; |
| 1105 | clock-names = "iface_clk", "core_clk", "ice_core_clk"; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1106 | qcom,ice-clk-rates = <270000000 160000000>; |
| 1107 | qcom,large-address-bus; |
| 1108 | |
| 1109 | status = "disabled"; |
| 1110 | }; |
| 1111 | |
| 1112 | sdhc_2: sdhci@7864900 { |
| 1113 | compatible = "qcom,sdhci-msm"; |
| 1114 | reg = <0x7864900 0x500>, <0x7864000 0x800>; |
| 1115 | reg-names = "hc_mem", "core_mem"; |
| 1116 | |
| 1117 | interrupts = <0 125 0>, <0 221 0>; |
| 1118 | interrupt-names = "hc_irq", "pwr_irq"; |
| 1119 | |
| 1120 | qcom,bus-width = <4>; |
| 1121 | |
| 1122 | qcom,pm-qos-irq-type = "affine_irq"; |
| 1123 | qcom,pm-qos-irq-latency = <2 213>; |
| 1124 | |
| 1125 | qcom,pm-qos-cpu-groups = <0x0f 0xf0>; |
| 1126 | qcom,pm-qos-legacy-latency-us = <2 213>, <2 213>; |
| 1127 | |
| 1128 | qcom,devfreq,freq-table = <50000000 200000000>; |
| 1129 | |
| 1130 | qcom,msm-bus,name = "sdhc2"; |
| 1131 | qcom,msm-bus,num-cases = <8>; |
| 1132 | qcom,msm-bus,num-paths = <1>; |
| 1133 | qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ |
| 1134 | <81 512 1046 3200>, /* 400 KB/s*/ |
| 1135 | <81 512 52286 160000>, /* 20 MB/s */ |
| 1136 | <81 512 65360 200000>, /* 25 MB/s */ |
| 1137 | <81 512 130718 400000>, /* 50 MB/s */ |
| 1138 | <81 512 261438 800000>, /* 100 MB/s */ |
| 1139 | <81 512 261438 800000>, /* 200 MB/s */ |
| 1140 | <81 512 1338562 4096000>; /* Max. bandwidth */ |
| 1141 | qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 1142 | 100000000 200000000 4294967295>; |
| 1143 | |
Sayali Lokhande | 3129993 | 2017-12-06 09:41:17 +0530 | [diff] [blame] | 1144 | clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, |
| 1145 | <&clock_gcc clk_gcc_sdcc2_apps_clk>; |
| 1146 | clock-names = "iface_clk", "core_clk"; |
| 1147 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1148 | qcom,large-address-bus; |
| 1149 | status = "disabled"; |
| 1150 | }; |
| 1151 | |
Kiran Gunda | af6a0b6 | 2017-10-23 16:03:10 +0530 | [diff] [blame] | 1152 | spmi_bus: qcom,spmi@200f000 { |
| 1153 | compatible = "qcom,spmi-pmic-arb"; |
| 1154 | reg = <0x200f000 0x1000>, |
| 1155 | <0x2400000 0x800000>, |
| 1156 | <0x2c00000 0x800000>, |
| 1157 | <0x3800000 0x200000>, |
| 1158 | <0x200a000 0x2100>; |
| 1159 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| 1160 | interrupt-names = "periph_irq"; |
| 1161 | interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; |
| 1162 | qcom,ee = <0>; |
| 1163 | qcom,channel = <0>; |
Kiran Gunda | 90e356a | 2017-11-22 17:04:46 +0530 | [diff] [blame] | 1164 | #address-cells = <2>; |
Kiran Gunda | af6a0b6 | 2017-10-23 16:03:10 +0530 | [diff] [blame] | 1165 | #size-cells = <0>; |
| 1166 | interrupt-controller; |
Kiran Gunda | 90e356a | 2017-11-22 17:04:46 +0530 | [diff] [blame] | 1167 | #interrupt-cells = <4>; |
Kiran Gunda | af6a0b6 | 2017-10-23 16:03:10 +0530 | [diff] [blame] | 1168 | cell-index = <0>; |
| 1169 | }; |
Chandana Kishori Chiluveru | 34872ee | 2017-11-30 17:35:26 +0530 | [diff] [blame] | 1170 | |
| 1171 | usb3: ssusb@7000000{ |
| 1172 | compatible = "qcom,dwc-usb3-msm"; |
| 1173 | reg = <0x07000000 0xfc000>, |
| 1174 | <0x0007e000 0x400>; |
| 1175 | reg-names = "core_base", |
| 1176 | "ahb2phy_base"; |
| 1177 | #address-cells = <1>; |
| 1178 | #size-cells = <1>; |
| 1179 | ranges; |
| 1180 | |
| 1181 | interrupts = <0 136 0>, <0 220 0>, <0 134 0>; |
| 1182 | interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; |
| 1183 | |
| 1184 | USB3_GDSC-supply = <&gdsc_usb30>; |
| 1185 | qcom,usb-dbm = <&dbm_1p5>; |
| 1186 | qcom,msm-bus,name = "usb3"; |
| 1187 | qcom,msm-bus,num-cases = <3>; |
| 1188 | qcom,msm-bus,num-paths = <1>; |
| 1189 | qcom,msm-bus,vectors-KBps = |
| 1190 | <61 512 0 0>, |
| 1191 | <61 512 240000 800000>, |
| 1192 | <61 512 240000 800000>; |
| 1193 | |
| 1194 | /* CPU-CLUSTER-WFI-LVL latency +1 */ |
| 1195 | qcom,pm-qos-latency = <2>; |
| 1196 | |
| 1197 | qcom,dwc-usb3-msm-tx-fifo-size = <21288>; |
| 1198 | |
| 1199 | clocks = <&clock_gcc clk_gcc_usb30_master_clk>, |
| 1200 | <&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>, |
| 1201 | <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, |
| 1202 | <&clock_gcc clk_gcc_usb30_sleep_clk>, |
| 1203 | <&clock_gcc clk_xo_dwc3_clk>, |
| 1204 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>; |
| 1205 | |
| 1206 | clock-names = "core_clk", "iface_clk", "utmi_clk", |
| 1207 | "sleep_clk", "xo", "cfg_ahb_clk"; |
| 1208 | |
| 1209 | qcom,core-clk-rate = <133333333>; /* NOM */ |
| 1210 | qcom,core-clk-rate-hs = <60000000>; /* LOW SVS */ |
| 1211 | |
| 1212 | resets = <&clock_gcc GCC_USB_30_BCR>; |
| 1213 | reset-names = "core_reset"; |
| 1214 | |
| 1215 | dwc3@7000000 { |
| 1216 | compatible = "snps,dwc3"; |
| 1217 | reg = <0x07000000 0xc8d0>; |
| 1218 | interrupt-parent = <&intc>; |
| 1219 | interrupts = <0 140 0>; |
| 1220 | usb-phy = <&qusb_phy>, <&ssphy>; |
| 1221 | tx-fifo-resize; |
| 1222 | snps,usb3-u1u2-disable; |
| 1223 | snps,nominal-elastic-buffer; |
| 1224 | snps,is-utmi-l1-suspend; |
| 1225 | snps,hird-threshold = /bits/ 8 <0x0>; |
| 1226 | }; |
| 1227 | |
| 1228 | qcom,usbbam@7104000 { |
| 1229 | compatible = "qcom,usb-bam-msm"; |
| 1230 | reg = <0x07104000 0x1a934>; |
| 1231 | interrupt-parent = <&intc>; |
| 1232 | interrupts = <0 135 0>; |
| 1233 | |
| 1234 | qcom,bam-type = <0>; |
| 1235 | qcom,usb-bam-fifo-baseaddr = <0x08605000>; |
| 1236 | qcom,usb-bam-num-pipes = <8>; |
| 1237 | qcom,ignore-core-reset-ack; |
| 1238 | qcom,disable-clk-gating; |
| 1239 | qcom,usb-bam-override-threshold = <0x4001>; |
| 1240 | qcom,usb-bam-max-mbps-highspeed = <400>; |
| 1241 | qcom,usb-bam-max-mbps-superspeed = <3600>; |
| 1242 | qcom,reset-bam-on-connect; |
| 1243 | |
| 1244 | qcom,pipe0 { |
| 1245 | label = "ssusb-ipa-out-0"; |
| 1246 | qcom,usb-bam-mem-type = <1>; |
| 1247 | qcom,dir = <0>; |
| 1248 | qcom,pipe-num = <0>; |
| 1249 | qcom,peer-bam = <1>; |
| 1250 | qcom,src-bam-pipe-index = <1>; |
| 1251 | qcom,data-fifo-size = <0x8000>; |
| 1252 | qcom,descriptor-fifo-size = <0x2000>; |
| 1253 | }; |
| 1254 | |
| 1255 | qcom,pipe1 { |
| 1256 | label = "ssusb-ipa-in-0"; |
| 1257 | qcom,usb-bam-mem-type = <1>; |
| 1258 | qcom,dir = <1>; |
| 1259 | qcom,pipe-num = <0>; |
| 1260 | qcom,peer-bam = <1>; |
| 1261 | qcom,dst-bam-pipe-index = <0>; |
| 1262 | qcom,data-fifo-size = <0x8000>; |
| 1263 | qcom,descriptor-fifo-size = <0x2000>; |
| 1264 | }; |
| 1265 | |
| 1266 | qcom,pipe2 { |
| 1267 | label = "ssusb-qdss-in-0"; |
| 1268 | qcom,usb-bam-mem-type = <2>; |
| 1269 | qcom,dir = <1>; |
| 1270 | qcom,pipe-num = <0>; |
| 1271 | qcom,peer-bam = <0>; |
| 1272 | qcom,peer-bam-physical-address = <0x06044000>; |
| 1273 | qcom,src-bam-pipe-index = <0>; |
| 1274 | qcom,dst-bam-pipe-index = <2>; |
| 1275 | qcom,data-fifo-offset = <0x0>; |
| 1276 | qcom,data-fifo-size = <0xe00>; |
| 1277 | qcom,descriptor-fifo-offset = <0xe00>; |
| 1278 | qcom,descriptor-fifo-size = <0x200>; |
| 1279 | }; |
| 1280 | |
| 1281 | qcom,pipe3 { |
| 1282 | label = "ssusb-dpl-ipa-in-1"; |
| 1283 | qcom,usb-bam-mem-type = <1>; |
| 1284 | qcom,dir = <1>; |
| 1285 | qcom,pipe-num = <1>; |
| 1286 | qcom,peer-bam = <1>; |
| 1287 | qcom,dst-bam-pipe-index = <2>; |
| 1288 | qcom,data-fifo-size = <0x8000>; |
| 1289 | qcom,descriptor-fifo-size = <0x2000>; |
| 1290 | }; |
| 1291 | }; |
| 1292 | }; |
| 1293 | |
| 1294 | qusb_phy: qusb@79000 { |
| 1295 | compatible = "qcom,qusb2phy"; |
| 1296 | reg = <0x079000 0x180>, |
| 1297 | <0x01841030 0x4>, |
| 1298 | <0x0193f020 0x4>; |
| 1299 | reg-names = "qusb_phy_base", |
| 1300 | "ref_clk_addr", |
| 1301 | "tcsr_clamp_dig_n_1p8"; |
| 1302 | |
| 1303 | USB3_GDSC-supply = <&gdsc_usb30>; |
| 1304 | vdd-supply = <&pm8953_l3>; |
| 1305 | vdda18-supply = <&pm8953_l7>; |
| 1306 | vdda33-supply = <&pm8953_l13>; |
| 1307 | qcom,vdd-voltage-level = <0 925000 925000>; |
| 1308 | |
| 1309 | qcom,qusb-phy-init-seq = <0xf8 0x80 |
| 1310 | 0xb3 0x84 |
| 1311 | 0x83 0x88 |
| 1312 | 0xc0 0x8c |
| 1313 | 0x14 0x9c |
| 1314 | 0x30 0x08 |
| 1315 | 0x79 0x0c |
| 1316 | 0x21 0x10 |
| 1317 | 0x00 0x90 |
| 1318 | 0x9f 0x1c |
| 1319 | 0x00 0x18>; |
| 1320 | phy_type= "utmi"; |
| 1321 | qcom,phy-clk-scheme = "cml"; |
| 1322 | qcom,major-rev = <1>; |
| 1323 | |
| 1324 | clocks = <&clock_gcc clk_bb_clk1>, |
| 1325 | <&clock_gcc clk_gcc_qusb_ref_clk>, |
| 1326 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, |
| 1327 | <&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>, |
| 1328 | <&clock_gcc clk_gcc_usb30_master_clk>; |
| 1329 | |
| 1330 | clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", |
| 1331 | "iface_clk", "core_clk"; |
| 1332 | |
| 1333 | resets = <&clock_gcc GCC_QUSB2_PHY_BCR>; |
| 1334 | reset-names = "phy_reset"; |
| 1335 | }; |
| 1336 | |
| 1337 | ssphy: ssphy@78000 { |
| 1338 | compatible = "qcom,usb-ssphy-qmp"; |
| 1339 | reg = <0x78000 0x9f8>, |
| 1340 | <0x0193f244 0x4>; |
| 1341 | reg-names = "qmp_phy_base", |
| 1342 | "vls_clamp_reg"; |
| 1343 | |
| 1344 | qcom,qmp-phy-init-seq = /*<reg_offset, value, delay>*/ |
| 1345 | <0xac 0x14 0x00 |
| 1346 | 0x34 0x08 0x00 |
| 1347 | 0x174 0x30 0x00 |
| 1348 | 0x3c 0x06 0x00 |
| 1349 | 0xb4 0x00 0x00 |
| 1350 | 0xb8 0x08 0x00 |
| 1351 | 0x194 0x06 0x3e8 |
| 1352 | 0x19c 0x01 0x00 |
| 1353 | 0x178 0x00 0x00 |
| 1354 | 0xd0 0x82 0x00 |
| 1355 | 0xdc 0x55 0x00 |
| 1356 | 0xe0 0x55 0x00 |
| 1357 | 0xe4 0x03 0x00 |
| 1358 | 0x78 0x0b 0x00 |
| 1359 | 0x84 0x16 0x00 |
| 1360 | 0x90 0x28 0x00 |
| 1361 | 0x108 0x80 0x00 |
| 1362 | 0x10c 0x00 0x00 |
| 1363 | 0x184 0x0a 0x00 |
| 1364 | 0x4c 0x15 0x00 |
| 1365 | 0x50 0x34 0x00 |
| 1366 | 0x54 0x00 0x00 |
| 1367 | 0xc8 0x00 0x00 |
| 1368 | 0x18c 0x00 0x00 |
| 1369 | 0xcc 0x00 0x00 |
| 1370 | 0x128 0x00 0x00 |
| 1371 | 0x0c 0x0a 0x00 |
| 1372 | 0x10 0x01 0x00 |
| 1373 | 0x1c 0x31 0x00 |
| 1374 | 0x20 0x01 0x00 |
| 1375 | 0x14 0x00 0x00 |
| 1376 | 0x18 0x00 0x00 |
| 1377 | 0x24 0xde 0x00 |
| 1378 | 0x28 0x07 0x00 |
| 1379 | 0x48 0x0f 0x00 |
| 1380 | 0x70 0x0f 0x00 |
| 1381 | 0x100 0x80 0x00 |
| 1382 | 0x440 0x0b 0x00 |
| 1383 | 0x4d8 0x02 0x00 |
| 1384 | 0x4dc 0x6c 0x00 |
| 1385 | 0x4e0 0xbb 0x00 |
| 1386 | 0x508 0x77 0x00 |
| 1387 | 0x50c 0x80 0x00 |
| 1388 | 0x514 0x03 0x00 |
| 1389 | 0x51c 0x16 0x00 |
| 1390 | 0x448 0x75 0x00 |
| 1391 | 0x454 0x00 0x00 |
| 1392 | 0x40c 0x0a 0x00 |
| 1393 | 0x41c 0x06 0x00 |
| 1394 | 0x510 0x00 0x00 |
| 1395 | 0x268 0x45 0x00 |
| 1396 | 0x2ac 0x12 0x00 |
| 1397 | 0x294 0x06 0x00 |
| 1398 | 0x254 0x00 0x00 |
| 1399 | 0x8c8 0x83 0x00 |
| 1400 | 0x8c4 0x02 0x00 |
| 1401 | 0x8cc 0x09 0x00 |
| 1402 | 0x8d0 0xa2 0x00 |
| 1403 | 0x8d4 0x85 0x00 |
| 1404 | 0x880 0xd1 0x00 |
| 1405 | 0x884 0x1f 0x00 |
| 1406 | 0x888 0x47 0x00 |
| 1407 | 0x80c 0x9f 0x00 |
| 1408 | 0x824 0x17 0x00 |
| 1409 | 0x828 0x0f 0x00 |
| 1410 | 0x8b8 0x75 0x00 |
| 1411 | 0x8bc 0x13 0x00 |
| 1412 | 0x8b0 0x86 0x00 |
| 1413 | 0x8a0 0x04 0x00 |
| 1414 | 0x88c 0x44 0x00 |
| 1415 | 0x870 0xe7 0x00 |
| 1416 | 0x874 0x03 0x00 |
| 1417 | 0x878 0x40 0x00 |
| 1418 | 0x87c 0x00 0x00 |
| 1419 | 0x9d8 0x88 0x00 |
| 1420 | 0xffffffff 0x00 0x00>; |
| 1421 | qcom,qmp-phy-reg-offset = |
| 1422 | <0x974 /* USB3_PHY_PCS_STATUS */ |
| 1423 | 0x8d8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ |
| 1424 | 0x8dc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ |
| 1425 | 0x804 /* USB3_PHY_POWER_DOWN_CONTROL */ |
| 1426 | 0x800 /* USB3_PHY_SW_RESET */ |
| 1427 | 0x808>; /* USB3_PHY_START */ |
| 1428 | |
| 1429 | vdd-supply = <&pm8953_l3>; |
| 1430 | core-supply = <&pm8953_l7>; |
| 1431 | qcom,vdd-voltage-level = <0 925000 925000>; |
| 1432 | qcom,core-voltage-level = <0 1800000 1800000>; |
| 1433 | qcom,vbus-valid-override; |
| 1434 | |
| 1435 | clocks = <&clock_gcc clk_gcc_usb3_aux_clk>, |
| 1436 | <&clock_gcc clk_gcc_usb3_pipe_clk>, |
| 1437 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, |
| 1438 | <&clock_gcc clk_bb_clk1>, |
| 1439 | <&clock_gcc clk_gcc_usb_ss_ref_clk>; |
| 1440 | |
| 1441 | clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", |
| 1442 | "ref_clk_src", "ref_clk"; |
| 1443 | |
| 1444 | resets = <&clock_gcc GCC_USB3_PHY_BCR>, |
| 1445 | <&clock_gcc GCC_USB3PHY_PHY_BCR>; |
| 1446 | |
| 1447 | reset-names = "phy_reset", "phy_phy_reset"; |
| 1448 | }; |
| 1449 | |
| 1450 | dbm_1p5: dbm@70f8000 { |
| 1451 | compatible = "qcom,usb-dbm-1p5"; |
| 1452 | reg = <0x070f8000 0x300>; |
| 1453 | qcom,reset-ep-after-lpm-resume; |
| 1454 | }; |
Jitendra Sharma | c5c3197 | 2017-11-10 14:26:13 +0530 | [diff] [blame^] | 1455 | |
| 1456 | qcom,lpass@c200000 { |
| 1457 | compatible = "qcom,pil-tz-generic"; |
| 1458 | reg = <0xc200000 0x00100>; |
| 1459 | interrupts = <0 293 1>; |
| 1460 | |
| 1461 | vdd_cx-supply = <&pm8953_s2_level>; |
| 1462 | qcom,proxy-reg-names = "vdd_cx"; |
| 1463 | qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; |
| 1464 | |
| 1465 | clocks = <&clock_gcc clk_xo_pil_lpass_clk>, |
| 1466 | <&clock_gcc clk_gcc_crypto_clk>, |
| 1467 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 1468 | <&clock_gcc clk_gcc_crypto_axi_clk>, |
| 1469 | <&clock_gcc clk_crypto_clk_src>; |
| 1470 | clock-names = "xo", "scm_core_clk", "scm_iface_clk", |
| 1471 | "scm_bus_clk", "scm_core_clk_src"; |
| 1472 | qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", |
| 1473 | "scm_bus_clk", "scm_core_clk_src"; |
| 1474 | qcom,scm_core_clk_src-freq = <80000000>; |
| 1475 | |
| 1476 | qcom,pas-id = <1>; |
| 1477 | qcom,complete-ramdump; |
| 1478 | qcom,proxy-timeout-ms = <10000>; |
| 1479 | qcom,smem-id = <423>; |
| 1480 | qcom,sysmon-id = <1>; |
| 1481 | qcom,ssctl-instance-id = <0x14>; |
| 1482 | qcom,firmware-name = "adsp"; |
| 1483 | |
| 1484 | memory-region = <&adsp_fw_mem>; |
| 1485 | }; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1486 | }; |
Kiran Gunda | 0954f39 | 2017-10-16 16:24:55 +0530 | [diff] [blame] | 1487 | |
| 1488 | #include "pm8953-rpm-regulator.dtsi" |
| 1489 | #include "pm8953.dtsi" |
| 1490 | #include "msm8953-regulator.dtsi" |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 1491 | #include "msm-gdsc-8916.dtsi" |
| 1492 | |
| 1493 | &gdsc_venus { |
| 1494 | clock-names = "bus_clk", "core_clk"; |
| 1495 | clocks = <&clock_gcc clk_gcc_venus0_axi_clk>, |
| 1496 | <&clock_gcc clk_gcc_venus0_vcodec0_clk>; |
| 1497 | status = "okay"; |
| 1498 | }; |
| 1499 | |
| 1500 | &gdsc_venus_core0 { |
| 1501 | qcom,support-hw-trigger; |
| 1502 | clock-names ="core0_clk"; |
| 1503 | clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>; |
| 1504 | status = "okay"; |
| 1505 | }; |
| 1506 | |
| 1507 | &gdsc_mdss { |
| 1508 | clock-names = "core_clk", "bus_clk"; |
| 1509 | clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, |
| 1510 | <&clock_gcc clk_gcc_mdss_axi_clk>; |
| 1511 | proxy-supply = <&gdsc_mdss>; |
| 1512 | qcom,proxy-consumer-enable; |
| 1513 | status = "okay"; |
| 1514 | }; |
| 1515 | |
| 1516 | &gdsc_oxili_gx { |
| 1517 | clock-names = "core_root_clk"; |
| 1518 | clocks =<&clock_gcc_gfx clk_gfx3d_clk_src>; |
| 1519 | qcom,force-enable-root-clk; |
| 1520 | parent-supply = <&gfx_vreg_corner>; |
| 1521 | status = "okay"; |
| 1522 | }; |
| 1523 | |
| 1524 | &gdsc_jpeg { |
| 1525 | clock-names = "core_clk", "bus_clk"; |
| 1526 | clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>, |
| 1527 | <&clock_gcc clk_gcc_camss_jpeg_axi_clk>; |
| 1528 | status = "okay"; |
| 1529 | }; |
| 1530 | |
| 1531 | &gdsc_vfe { |
| 1532 | clock-names = "core_clk", "bus_clk", "micro_clk", |
| 1533 | "csi_clk"; |
| 1534 | clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>, |
| 1535 | <&clock_gcc clk_gcc_camss_vfe_axi_clk>, |
| 1536 | <&clock_gcc clk_gcc_camss_micro_ahb_clk>, |
| 1537 | <&clock_gcc clk_gcc_camss_csi_vfe0_clk>; |
| 1538 | status = "okay"; |
| 1539 | }; |
| 1540 | |
| 1541 | &gdsc_vfe1 { |
| 1542 | clock-names = "core_clk", "bus_clk", "micro_clk", |
| 1543 | "csi_clk"; |
| 1544 | clocks = <&clock_gcc clk_gcc_camss_vfe1_clk>, |
| 1545 | <&clock_gcc clk_gcc_camss_vfe1_axi_clk>, |
| 1546 | <&clock_gcc clk_gcc_camss_micro_ahb_clk>, |
| 1547 | <&clock_gcc clk_gcc_camss_csi_vfe1_clk>; |
| 1548 | status = "okay"; |
| 1549 | }; |
| 1550 | |
| 1551 | &gdsc_cpp { |
| 1552 | clock-names = "core_clk", "bus_clk"; |
| 1553 | clocks = <&clock_gcc clk_gcc_camss_cpp_clk>, |
| 1554 | <&clock_gcc clk_gcc_camss_cpp_axi_clk>; |
| 1555 | status = "okay"; |
| 1556 | }; |
| 1557 | |
| 1558 | &gdsc_oxili_cx { |
| 1559 | clock-names = "core_clk"; |
| 1560 | clocks = <&clock_gcc_gfx clk_gcc_oxili_gfx3d_clk>; |
| 1561 | status = "okay"; |
| 1562 | }; |
| 1563 | |
| 1564 | &gdsc_usb30 { |
| 1565 | status = "okay"; |
| 1566 | }; |