Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 33 | #include "i915_drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 34 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 36 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
| 38 | { |
| 39 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 40 | u32 seqno; |
| 41 | |
| 42 | seqno = dev_priv->next_seqno; |
| 43 | |
| 44 | /* reserve 0 for non-seqno */ |
| 45 | if (++dev_priv->next_seqno == 0) |
| 46 | dev_priv->next_seqno = 1; |
| 47 | |
| 48 | return seqno; |
| 49 | } |
| 50 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 51 | static void |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 52 | render_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 53 | u32 invalidate_domains, |
| 54 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 55 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 56 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 57 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 58 | u32 cmd; |
| 59 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 60 | #if WATCH_EXEC |
| 61 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, |
| 62 | invalidate_domains, flush_domains); |
| 63 | #endif |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 64 | |
| 65 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 66 | invalidate_domains, flush_domains); |
| 67 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 68 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
| 69 | /* |
| 70 | * read/write caches: |
| 71 | * |
| 72 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 73 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 74 | * also flushed at 2d versus 3d pipeline switches. |
| 75 | * |
| 76 | * read-only caches: |
| 77 | * |
| 78 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 79 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 80 | * |
| 81 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 82 | * |
| 83 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 84 | * invalidated when MI_EXE_FLUSH is set. |
| 85 | * |
| 86 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 87 | * invalidated with every MI_FLUSH. |
| 88 | * |
| 89 | * TLBs: |
| 90 | * |
| 91 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 92 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 93 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 94 | * are flushed at any MI_FLUSH. |
| 95 | */ |
| 96 | |
| 97 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 98 | if ((invalidate_domains|flush_domains) & |
| 99 | I915_GEM_DOMAIN_RENDER) |
| 100 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 101 | if (INTEL_INFO(dev)->gen < 4) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 102 | /* |
| 103 | * On the 965, the sampler cache always gets flushed |
| 104 | * and this bit is reserved. |
| 105 | */ |
| 106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 107 | cmd |= MI_READ_FLUSH; |
| 108 | } |
| 109 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 110 | cmd |= MI_EXE_FLUSH; |
| 111 | |
Chris Wilson | 70eac33 | 2010-11-30 14:07:47 +0000 | [diff] [blame] | 112 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 113 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 114 | cmd |= MI_INVALIDATE_ISP; |
| 115 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 116 | #if WATCH_EXEC |
| 117 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); |
| 118 | #endif |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 119 | if (intel_ring_begin(ring, 2) == 0) { |
| 120 | intel_ring_emit(ring, cmd); |
| 121 | intel_ring_emit(ring, MI_NOOP); |
| 122 | intel_ring_advance(ring); |
| 123 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 124 | } |
| 125 | } |
| 126 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 127 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 128 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 129 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 130 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 131 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 132 | } |
| 133 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 134 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 135 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 136 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 137 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
Daniel Vetter | 3d281d8 | 2010-09-24 21:14:22 +0200 | [diff] [blame] | 138 | RING_ACTHD(ring->mmio_base) : ACTHD; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 139 | |
| 140 | return I915_READ(acthd_reg); |
| 141 | } |
| 142 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 143 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 144 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 145 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 146 | struct drm_i915_gem_object *obj = ring->obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 147 | u32 head; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 148 | |
| 149 | /* Stop the ring if it's running. */ |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 150 | I915_WRITE_CTL(ring, 0); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 151 | I915_WRITE_HEAD(ring, 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 152 | ring->write_tail(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 153 | |
| 154 | /* Initialize the ring. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 155 | I915_WRITE_START(ring, obj->gtt_offset); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 156 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 157 | |
| 158 | /* G45 ring initialization fails to reset head to zero */ |
| 159 | if (head != 0) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 160 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 161 | "ctl %08x head %08x tail %08x start %08x\n", |
| 162 | ring->name, |
| 163 | I915_READ_CTL(ring), |
| 164 | I915_READ_HEAD(ring), |
| 165 | I915_READ_TAIL(ring), |
| 166 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 167 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 168 | I915_WRITE_HEAD(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 169 | |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 170 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 171 | DRM_ERROR("failed to set %s head to zero " |
| 172 | "ctl %08x head %08x tail %08x start %08x\n", |
| 173 | ring->name, |
| 174 | I915_READ_CTL(ring), |
| 175 | I915_READ_HEAD(ring), |
| 176 | I915_READ_TAIL(ring), |
| 177 | I915_READ_START(ring)); |
| 178 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 179 | } |
| 180 | |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 181 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 182 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 6aa5606 | 2010-10-29 21:44:37 +0100 | [diff] [blame] | 183 | | RING_REPORT_64K | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 184 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 185 | /* If the head is still not zero, the ring is dead */ |
Chris Wilson | 176f28e | 2010-10-28 11:18:07 +0100 | [diff] [blame] | 186 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 187 | I915_READ_START(ring) != obj->gtt_offset || |
Chris Wilson | 176f28e | 2010-10-28 11:18:07 +0100 | [diff] [blame] | 188 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 189 | DRM_ERROR("%s initialization failed " |
| 190 | "ctl %08x head %08x tail %08x start %08x\n", |
| 191 | ring->name, |
| 192 | I915_READ_CTL(ring), |
| 193 | I915_READ_HEAD(ring), |
| 194 | I915_READ_TAIL(ring), |
| 195 | I915_READ_START(ring)); |
| 196 | return -EIO; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 197 | } |
| 198 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 199 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 200 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 201 | else { |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 202 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 203 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 204 | ring->space = ring->head - (ring->tail + 8); |
| 205 | if (ring->space < 0) |
| 206 | ring->space += ring->size; |
| 207 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 208 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 209 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 210 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 211 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame^] | 212 | /* |
| 213 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 214 | * over cache flushing. |
| 215 | */ |
| 216 | struct pipe_control { |
| 217 | struct drm_i915_gem_object *obj; |
| 218 | volatile u32 *cpu_page; |
| 219 | u32 gtt_offset; |
| 220 | }; |
| 221 | |
| 222 | static int |
| 223 | init_pipe_control(struct intel_ring_buffer *ring) |
| 224 | { |
| 225 | struct pipe_control *pc; |
| 226 | struct drm_i915_gem_object *obj; |
| 227 | int ret; |
| 228 | |
| 229 | if (ring->private) |
| 230 | return 0; |
| 231 | |
| 232 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
| 233 | if (!pc) |
| 234 | return -ENOMEM; |
| 235 | |
| 236 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 237 | if (obj == NULL) { |
| 238 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 239 | ret = -ENOMEM; |
| 240 | goto err; |
| 241 | } |
| 242 | obj->agp_type = AGP_USER_CACHED_MEMORY; |
| 243 | |
| 244 | ret = i915_gem_object_pin(obj, 4096, true); |
| 245 | if (ret) |
| 246 | goto err_unref; |
| 247 | |
| 248 | pc->gtt_offset = obj->gtt_offset; |
| 249 | pc->cpu_page = kmap(obj->pages[0]); |
| 250 | if (pc->cpu_page == NULL) |
| 251 | goto err_unpin; |
| 252 | |
| 253 | pc->obj = obj; |
| 254 | ring->private = pc; |
| 255 | return 0; |
| 256 | |
| 257 | err_unpin: |
| 258 | i915_gem_object_unpin(obj); |
| 259 | err_unref: |
| 260 | drm_gem_object_unreference(&obj->base); |
| 261 | err: |
| 262 | kfree(pc); |
| 263 | return ret; |
| 264 | } |
| 265 | |
| 266 | static void |
| 267 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
| 268 | { |
| 269 | struct pipe_control *pc = ring->private; |
| 270 | struct drm_i915_gem_object *obj; |
| 271 | |
| 272 | if (!ring->private) |
| 273 | return; |
| 274 | |
| 275 | obj = pc->obj; |
| 276 | kunmap(obj->pages[0]); |
| 277 | i915_gem_object_unpin(obj); |
| 278 | drm_gem_object_unreference(&obj->base); |
| 279 | |
| 280 | kfree(pc); |
| 281 | ring->private = NULL; |
| 282 | } |
| 283 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 284 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 285 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 286 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 287 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 288 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 289 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 290 | if (INTEL_INFO(dev)->gen > 3) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 291 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 292 | if (IS_GEN6(dev)) |
| 293 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; |
| 294 | I915_WRITE(MI_MODE, mode); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 295 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 296 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame^] | 297 | if (INTEL_INFO(dev)->gen >= 6) { |
| 298 | } else if (IS_GEN5(dev)) { |
| 299 | ret = init_pipe_control(ring); |
| 300 | if (ret) |
| 301 | return ret; |
| 302 | } |
| 303 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 304 | return ret; |
| 305 | } |
| 306 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame^] | 307 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 308 | { |
| 309 | if (!ring->private) |
| 310 | return; |
| 311 | |
| 312 | cleanup_pipe_control(ring); |
| 313 | } |
| 314 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 315 | static void |
| 316 | update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno) |
| 317 | { |
| 318 | struct drm_device *dev = ring->dev; |
| 319 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 320 | int id; |
| 321 | |
| 322 | /* |
| 323 | * cs -> 1 = vcs, 0 = bcs |
| 324 | * vcs -> 1 = bcs, 0 = cs, |
| 325 | * bcs -> 1 = cs, 0 = vcs. |
| 326 | */ |
| 327 | id = ring - dev_priv->ring; |
| 328 | id += 2 - i; |
| 329 | id %= 3; |
| 330 | |
| 331 | intel_ring_emit(ring, |
| 332 | MI_SEMAPHORE_MBOX | |
| 333 | MI_SEMAPHORE_REGISTER | |
| 334 | MI_SEMAPHORE_UPDATE); |
| 335 | intel_ring_emit(ring, seqno); |
| 336 | intel_ring_emit(ring, |
| 337 | RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i); |
| 338 | } |
| 339 | |
| 340 | static int |
| 341 | gen6_add_request(struct intel_ring_buffer *ring, |
| 342 | u32 *result) |
| 343 | { |
| 344 | u32 seqno; |
| 345 | int ret; |
| 346 | |
| 347 | ret = intel_ring_begin(ring, 10); |
| 348 | if (ret) |
| 349 | return ret; |
| 350 | |
| 351 | seqno = i915_gem_get_seqno(ring->dev); |
| 352 | update_semaphore(ring, 0, seqno); |
| 353 | update_semaphore(ring, 1, seqno); |
| 354 | |
| 355 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 356 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 357 | intel_ring_emit(ring, seqno); |
| 358 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 359 | intel_ring_advance(ring); |
| 360 | |
| 361 | *result = seqno; |
| 362 | return 0; |
| 363 | } |
| 364 | |
| 365 | int |
| 366 | intel_ring_sync(struct intel_ring_buffer *ring, |
| 367 | struct intel_ring_buffer *to, |
| 368 | u32 seqno) |
| 369 | { |
| 370 | int ret; |
| 371 | |
| 372 | ret = intel_ring_begin(ring, 4); |
| 373 | if (ret) |
| 374 | return ret; |
| 375 | |
| 376 | intel_ring_emit(ring, |
| 377 | MI_SEMAPHORE_MBOX | |
| 378 | MI_SEMAPHORE_REGISTER | |
| 379 | intel_ring_sync_index(ring, to) << 17 | |
| 380 | MI_SEMAPHORE_COMPARE); |
| 381 | intel_ring_emit(ring, seqno); |
| 382 | intel_ring_emit(ring, 0); |
| 383 | intel_ring_emit(ring, MI_NOOP); |
| 384 | intel_ring_advance(ring); |
| 385 | |
| 386 | return 0; |
| 387 | } |
| 388 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame^] | 389 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 390 | do { \ |
| 391 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
| 392 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
| 393 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 394 | intel_ring_emit(ring__, 0); \ |
| 395 | intel_ring_emit(ring__, 0); \ |
| 396 | } while (0) |
| 397 | |
| 398 | static int |
| 399 | pc_render_add_request(struct intel_ring_buffer *ring, |
| 400 | u32 *result) |
| 401 | { |
| 402 | struct drm_device *dev = ring->dev; |
| 403 | u32 seqno = i915_gem_get_seqno(dev); |
| 404 | struct pipe_control *pc = ring->private; |
| 405 | u32 scratch_addr = pc->gtt_offset + 128; |
| 406 | int ret; |
| 407 | |
| 408 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 409 | * incoherent with writes to memory, i.e. completely fubar, |
| 410 | * so we need to use PIPE_NOTIFY instead. |
| 411 | * |
| 412 | * However, we also need to workaround the qword write |
| 413 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 414 | * memory before requesting an interrupt. |
| 415 | */ |
| 416 | ret = intel_ring_begin(ring, 32); |
| 417 | if (ret) |
| 418 | return ret; |
| 419 | |
| 420 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
| 421 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); |
| 422 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 423 | intel_ring_emit(ring, seqno); |
| 424 | intel_ring_emit(ring, 0); |
| 425 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 426 | scratch_addr += 128; /* write to separate cachelines */ |
| 427 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 428 | scratch_addr += 128; |
| 429 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 430 | scratch_addr += 128; |
| 431 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 432 | scratch_addr += 128; |
| 433 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 434 | scratch_addr += 128; |
| 435 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 436 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
| 437 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | |
| 438 | PIPE_CONTROL_NOTIFY); |
| 439 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 440 | intel_ring_emit(ring, seqno); |
| 441 | intel_ring_emit(ring, 0); |
| 442 | intel_ring_advance(ring); |
| 443 | |
| 444 | *result = seqno; |
| 445 | return 0; |
| 446 | } |
| 447 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 448 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 449 | render_ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 450 | u32 *result) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 451 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 452 | struct drm_device *dev = ring->dev; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 453 | u32 seqno = i915_gem_get_seqno(dev); |
| 454 | int ret; |
Zhenyu Wang | ca76482 | 2010-05-27 10:26:42 +0800 | [diff] [blame] | 455 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 456 | ret = intel_ring_begin(ring, 4); |
| 457 | if (ret) |
| 458 | return ret; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 459 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 460 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 461 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 462 | intel_ring_emit(ring, seqno); |
| 463 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 464 | intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 465 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 466 | *result = seqno; |
| 467 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 468 | } |
| 469 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 470 | static u32 |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 471 | ring_get_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 472 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 473 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 474 | } |
| 475 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame^] | 476 | static u32 |
| 477 | pc_render_get_seqno(struct intel_ring_buffer *ring) |
| 478 | { |
| 479 | struct pipe_control *pc = ring->private; |
| 480 | return pc->cpu_page[0]; |
| 481 | } |
| 482 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 483 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 484 | render_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 485 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 486 | struct drm_device *dev = ring->dev; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 487 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 488 | if (!dev->irq_enabled) |
| 489 | return false; |
| 490 | |
| 491 | if (atomic_inc_return(&ring->irq_refcount) == 1) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 492 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 493 | unsigned long irqflags; |
| 494 | |
| 495 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 496 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 497 | ironlake_enable_graphics_irq(dev_priv, |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame^] | 498 | GT_PIPE_NOTIFY | GT_USER_INTERRUPT); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 499 | else |
| 500 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 501 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 502 | } |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 503 | |
| 504 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 505 | } |
| 506 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 507 | static void |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 508 | render_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 509 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 510 | struct drm_device *dev = ring->dev; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 511 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 512 | if (atomic_dec_and_test(&ring->irq_refcount)) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 513 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 514 | unsigned long irqflags; |
| 515 | |
| 516 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 517 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 518 | ironlake_disable_graphics_irq(dev_priv, |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame^] | 519 | GT_USER_INTERRUPT | |
| 520 | GT_PIPE_NOTIFY); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 521 | else |
| 522 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 523 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 524 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 525 | } |
| 526 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 527 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 528 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 529 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 530 | u32 mmio = IS_GEN6(ring->dev) ? |
| 531 | RING_HWS_PGA_GEN6(ring->mmio_base) : |
| 532 | RING_HWS_PGA(ring->mmio_base); |
| 533 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 534 | POSTING_READ(mmio); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 535 | } |
| 536 | |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 537 | static void |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 538 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 539 | u32 invalidate_domains, |
| 540 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 541 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 542 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) |
| 543 | return; |
| 544 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 545 | if (intel_ring_begin(ring, 2) == 0) { |
| 546 | intel_ring_emit(ring, MI_FLUSH); |
| 547 | intel_ring_emit(ring, MI_NOOP); |
| 548 | intel_ring_advance(ring); |
| 549 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 550 | } |
| 551 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 552 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 553 | ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 554 | u32 *result) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 555 | { |
| 556 | u32 seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 557 | int ret; |
| 558 | |
| 559 | ret = intel_ring_begin(ring, 4); |
| 560 | if (ret) |
| 561 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 562 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 563 | seqno = i915_gem_get_seqno(ring->dev); |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 564 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 565 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 566 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 567 | intel_ring_emit(ring, seqno); |
| 568 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 569 | intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 570 | |
| 571 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 572 | *result = seqno; |
| 573 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 574 | } |
| 575 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 576 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 577 | ring_get_irq(struct intel_ring_buffer *ring, u32 flag) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 578 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 579 | struct drm_device *dev = ring->dev; |
| 580 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 581 | if (!dev->irq_enabled) |
| 582 | return false; |
| 583 | |
| 584 | if (atomic_inc_return(&ring->irq_refcount) == 1) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 585 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 586 | unsigned long irqflags; |
| 587 | |
| 588 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 589 | ironlake_enable_graphics_irq(dev_priv, flag); |
| 590 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 591 | } |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 592 | |
| 593 | return true; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 594 | } |
| 595 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 596 | static void |
| 597 | ring_put_irq(struct intel_ring_buffer *ring, u32 flag) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 598 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 599 | struct drm_device *dev = ring->dev; |
| 600 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 601 | if (atomic_dec_and_test(&ring->irq_refcount)) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 602 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 603 | unsigned long irqflags; |
| 604 | |
| 605 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 606 | ironlake_disable_graphics_irq(dev_priv, flag); |
| 607 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 608 | } |
| 609 | } |
| 610 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 611 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 612 | bsd_ring_get_irq(struct intel_ring_buffer *ring) |
| 613 | { |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 614 | return ring_get_irq(ring, GT_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 615 | } |
| 616 | static void |
| 617 | bsd_ring_put_irq(struct intel_ring_buffer *ring) |
| 618 | { |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 619 | ring_put_irq(ring, GT_BSD_USER_INTERRUPT); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 620 | } |
| 621 | |
| 622 | static int |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 623 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 624 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 625 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 626 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 627 | ret = intel_ring_begin(ring, 2); |
| 628 | if (ret) |
| 629 | return ret; |
| 630 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 631 | intel_ring_emit(ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 632 | MI_BATCH_BUFFER_START | (2 << 6) | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 633 | MI_BATCH_NON_SECURE_I965); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 634 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 635 | intel_ring_advance(ring); |
| 636 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 637 | return 0; |
| 638 | } |
| 639 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 640 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 641 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 642 | u32 offset, u32 len) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 643 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 644 | struct drm_device *dev = ring->dev; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 645 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 646 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 647 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 648 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 649 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 650 | if (IS_I830(dev) || IS_845G(dev)) { |
| 651 | ret = intel_ring_begin(ring, 4); |
| 652 | if (ret) |
| 653 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 654 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 655 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 656 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
| 657 | intel_ring_emit(ring, offset + len - 8); |
| 658 | intel_ring_emit(ring, 0); |
| 659 | } else { |
| 660 | ret = intel_ring_begin(ring, 2); |
| 661 | if (ret) |
| 662 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 663 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 664 | if (INTEL_INFO(dev)->gen >= 4) { |
| 665 | intel_ring_emit(ring, |
| 666 | MI_BATCH_BUFFER_START | (2 << 6) | |
| 667 | MI_BATCH_NON_SECURE_I965); |
| 668 | intel_ring_emit(ring, offset); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 669 | } else { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 670 | intel_ring_emit(ring, |
| 671 | MI_BATCH_BUFFER_START | (2 << 6)); |
| 672 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 673 | } |
| 674 | } |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 675 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 676 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 677 | return 0; |
| 678 | } |
| 679 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 680 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 681 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 682 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 683 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 684 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 685 | obj = ring->status_page.obj; |
| 686 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 687 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 688 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 689 | kunmap(obj->pages[0]); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 690 | i915_gem_object_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 691 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 692 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 693 | |
| 694 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 695 | } |
| 696 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 697 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 698 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 699 | struct drm_device *dev = ring->dev; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 700 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 701 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 702 | int ret; |
| 703 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 704 | obj = i915_gem_alloc_object(dev, 4096); |
| 705 | if (obj == NULL) { |
| 706 | DRM_ERROR("Failed to allocate status page\n"); |
| 707 | ret = -ENOMEM; |
| 708 | goto err; |
| 709 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 710 | obj->agp_type = AGP_USER_CACHED_MEMORY; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 711 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 712 | ret = i915_gem_object_pin(obj, 4096, true); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 713 | if (ret != 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 714 | goto err_unref; |
| 715 | } |
| 716 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 717 | ring->status_page.gfx_addr = obj->gtt_offset; |
| 718 | ring->status_page.page_addr = kmap(obj->pages[0]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 719 | if (ring->status_page.page_addr == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 720 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 721 | goto err_unpin; |
| 722 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 723 | ring->status_page.obj = obj; |
| 724 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 725 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 726 | intel_ring_setup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 727 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 728 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 729 | |
| 730 | return 0; |
| 731 | |
| 732 | err_unpin: |
| 733 | i915_gem_object_unpin(obj); |
| 734 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 735 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 736 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 737 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 738 | } |
| 739 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 740 | int intel_init_ring_buffer(struct drm_device *dev, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 741 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 742 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 743 | struct drm_i915_gem_object *obj; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 744 | int ret; |
| 745 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 746 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 747 | INIT_LIST_HEAD(&ring->active_list); |
| 748 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 749 | INIT_LIST_HEAD(&ring->gpu_write_list); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 750 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 751 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 752 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 753 | if (ret) |
| 754 | return ret; |
| 755 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 756 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 757 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 758 | if (obj == NULL) { |
| 759 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 760 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 761 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 762 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 763 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 764 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 765 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 766 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 767 | if (ret) |
| 768 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 769 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 770 | ring->map.size = ring->size; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 771 | ring->map.offset = dev->agp->base + obj->gtt_offset; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 772 | ring->map.type = 0; |
| 773 | ring->map.flags = 0; |
| 774 | ring->map.mtrr = 0; |
| 775 | |
| 776 | drm_core_ioremap_wc(&ring->map, dev); |
| 777 | if (ring->map.handle == NULL) { |
| 778 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 779 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 780 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 781 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 782 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 783 | ring->virtual_start = ring->map.handle; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 784 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 785 | if (ret) |
| 786 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 787 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 788 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 789 | |
| 790 | err_unmap: |
| 791 | drm_core_ioremapfree(&ring->map, dev); |
| 792 | err_unpin: |
| 793 | i915_gem_object_unpin(obj); |
| 794 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 795 | drm_gem_object_unreference(&obj->base); |
| 796 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 797 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 798 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 799 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 800 | } |
| 801 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 802 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 803 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 804 | struct drm_i915_private *dev_priv; |
| 805 | int ret; |
| 806 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 807 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 808 | return; |
| 809 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 810 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 811 | dev_priv = ring->dev->dev_private; |
| 812 | ret = intel_wait_ring_buffer(ring, ring->size - 8); |
| 813 | I915_WRITE_CTL(ring, 0); |
| 814 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 815 | drm_core_ioremapfree(&ring->map, ring->dev); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 816 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 817 | i915_gem_object_unpin(ring->obj); |
| 818 | drm_gem_object_unreference(&ring->obj->base); |
| 819 | ring->obj = NULL; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 820 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 821 | if (ring->cleanup) |
| 822 | ring->cleanup(ring); |
| 823 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 824 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 825 | } |
| 826 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 827 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 828 | { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 829 | unsigned int *virt; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 830 | int rem; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 831 | rem = ring->size - ring->tail; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 832 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 833 | if (ring->space < rem) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 834 | int ret = intel_wait_ring_buffer(ring, rem); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 835 | if (ret) |
| 836 | return ret; |
| 837 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 838 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 839 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 840 | rem /= 8; |
| 841 | while (rem--) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 842 | *virt++ = MI_NOOP; |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 843 | *virt++ = MI_NOOP; |
| 844 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 845 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 846 | ring->tail = 0; |
Chris Wilson | 43ed340 | 2010-07-01 17:53:00 +0100 | [diff] [blame] | 847 | ring->space = ring->head - 8; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 848 | |
| 849 | return 0; |
| 850 | } |
| 851 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 852 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 853 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 854 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 855 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 856 | unsigned long end; |
Chris Wilson | 6aa5606 | 2010-10-29 21:44:37 +0100 | [diff] [blame] | 857 | u32 head; |
| 858 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 859 | trace_i915_ring_wait_begin (dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 860 | end = jiffies + 3 * HZ; |
| 861 | do { |
Chris Wilson | 8c0a6bf | 2010-12-09 12:56:37 +0000 | [diff] [blame] | 862 | /* If the reported head position has wrapped or hasn't advanced, |
| 863 | * fallback to the slow and accurate path. |
| 864 | */ |
| 865 | head = intel_read_status_page(ring, 4); |
| 866 | if (head < ring->actual_head) |
| 867 | head = I915_READ_HEAD(ring); |
| 868 | ring->actual_head = head; |
| 869 | ring->head = head & HEAD_ADDR; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 870 | ring->space = ring->head - (ring->tail + 8); |
| 871 | if (ring->space < 0) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 872 | ring->space += ring->size; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 873 | if (ring->space >= n) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 874 | trace_i915_ring_wait_end(dev); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 875 | return 0; |
| 876 | } |
| 877 | |
| 878 | if (dev->primary->master) { |
| 879 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 880 | if (master_priv->sarea_priv) |
| 881 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 882 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 883 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 884 | msleep(1); |
Chris Wilson | f4e0b29 | 2010-10-29 21:06:16 +0100 | [diff] [blame] | 885 | if (atomic_read(&dev_priv->mm.wedged)) |
| 886 | return -EAGAIN; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 887 | } while (!time_after(jiffies, end)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 888 | trace_i915_ring_wait_end (dev); |
| 889 | return -EBUSY; |
| 890 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 891 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 892 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 893 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 894 | { |
Zou Nan hai | be26a10 | 2010-06-12 17:40:24 +0800 | [diff] [blame] | 895 | int n = 4*num_dwords; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 896 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 897 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 898 | if (unlikely(ring->tail + n > ring->size)) { |
| 899 | ret = intel_wrap_ring_buffer(ring); |
| 900 | if (unlikely(ret)) |
| 901 | return ret; |
| 902 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 903 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 904 | if (unlikely(ring->space < n)) { |
| 905 | ret = intel_wait_ring_buffer(ring, n); |
| 906 | if (unlikely(ret)) |
| 907 | return ret; |
| 908 | } |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 909 | |
| 910 | ring->space -= n; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 911 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 912 | } |
| 913 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 914 | void intel_ring_advance(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 915 | { |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 916 | ring->tail &= ring->size - 1; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 917 | ring->write_tail(ring, ring->tail); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 918 | } |
| 919 | |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 920 | static const struct intel_ring_buffer render_ring = { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 921 | .name = "render ring", |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 922 | .id = RING_RENDER, |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 923 | .mmio_base = RENDER_RING_BASE, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 924 | .size = 32 * PAGE_SIZE, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 925 | .init = init_render_ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 926 | .write_tail = ring_write_tail, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 927 | .flush = render_ring_flush, |
| 928 | .add_request = render_ring_add_request, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 929 | .get_seqno = ring_get_seqno, |
| 930 | .irq_get = render_ring_get_irq, |
| 931 | .irq_put = render_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 932 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame^] | 933 | .cleanup = render_ring_cleanup, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 934 | }; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 935 | |
| 936 | /* ring buffer for bit-stream decoder */ |
| 937 | |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 938 | static const struct intel_ring_buffer bsd_ring = { |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 939 | .name = "bsd ring", |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 940 | .id = RING_BSD, |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 941 | .mmio_base = BSD_RING_BASE, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 942 | .size = 32 * PAGE_SIZE, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 943 | .init = init_ring_common, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 944 | .write_tail = ring_write_tail, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 945 | .flush = bsd_ring_flush, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 946 | .add_request = ring_add_request, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 947 | .get_seqno = ring_get_seqno, |
| 948 | .irq_get = bsd_ring_get_irq, |
| 949 | .irq_put = bsd_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 950 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 951 | }; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 952 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 953 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 954 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 955 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 956 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 957 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 958 | |
| 959 | /* Every tail move must follow the sequence below */ |
| 960 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 961 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 962 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); |
| 963 | I915_WRITE(GEN6_BSD_RNCID, 0x0); |
| 964 | |
| 965 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
| 966 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, |
| 967 | 50)) |
| 968 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); |
| 969 | |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 970 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 971 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 972 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 973 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); |
| 974 | } |
| 975 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 976 | static void gen6_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 977 | u32 invalidate_domains, |
| 978 | u32 flush_domains) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 979 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 980 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) |
| 981 | return; |
| 982 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 983 | if (intel_ring_begin(ring, 4) == 0) { |
| 984 | intel_ring_emit(ring, MI_FLUSH_DW); |
| 985 | intel_ring_emit(ring, 0); |
| 986 | intel_ring_emit(ring, 0); |
| 987 | intel_ring_emit(ring, 0); |
| 988 | intel_ring_advance(ring); |
| 989 | } |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 990 | } |
| 991 | |
| 992 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 993 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 994 | u32 offset, u32 len) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 995 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 996 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 997 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 998 | ret = intel_ring_begin(ring, 2); |
| 999 | if (ret) |
| 1000 | return ret; |
| 1001 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1002 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1003 | /* bit0-7 is the length on GEN6+ */ |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1004 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1005 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1006 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1007 | return 0; |
| 1008 | } |
| 1009 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1010 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1011 | gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
| 1012 | { |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1013 | return ring_get_irq(ring, GT_GEN6_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1014 | } |
| 1015 | |
| 1016 | static void |
| 1017 | gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) |
| 1018 | { |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1019 | ring_put_irq(ring, GT_GEN6_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1020 | } |
| 1021 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1022 | /* ring buffer for Video Codec for Gen6+ */ |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 1023 | static const struct intel_ring_buffer gen6_bsd_ring = { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1024 | .name = "gen6 bsd ring", |
| 1025 | .id = RING_BSD, |
| 1026 | .mmio_base = GEN6_BSD_RING_BASE, |
| 1027 | .size = 32 * PAGE_SIZE, |
| 1028 | .init = init_ring_common, |
| 1029 | .write_tail = gen6_bsd_ring_write_tail, |
| 1030 | .flush = gen6_ring_flush, |
| 1031 | .add_request = gen6_add_request, |
| 1032 | .get_seqno = ring_get_seqno, |
| 1033 | .irq_get = gen6_bsd_ring_get_irq, |
| 1034 | .irq_put = gen6_bsd_ring_put_irq, |
| 1035 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1036 | }; |
| 1037 | |
| 1038 | /* Blitter support (SandyBridge+) */ |
| 1039 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1040 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1041 | blt_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1042 | { |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1043 | return ring_get_irq(ring, GT_BLT_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1044 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1045 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1046 | static void |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1047 | blt_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1048 | { |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1049 | ring_put_irq(ring, GT_BLT_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1050 | } |
| 1051 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1052 | |
| 1053 | /* Workaround for some stepping of SNB, |
| 1054 | * each time when BLT engine ring tail moved, |
| 1055 | * the first command in the ring to be parsed |
| 1056 | * should be MI_BATCH_BUFFER_START |
| 1057 | */ |
| 1058 | #define NEED_BLT_WORKAROUND(dev) \ |
| 1059 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) |
| 1060 | |
| 1061 | static inline struct drm_i915_gem_object * |
| 1062 | to_blt_workaround(struct intel_ring_buffer *ring) |
| 1063 | { |
| 1064 | return ring->private; |
| 1065 | } |
| 1066 | |
| 1067 | static int blt_ring_init(struct intel_ring_buffer *ring) |
| 1068 | { |
| 1069 | if (NEED_BLT_WORKAROUND(ring->dev)) { |
| 1070 | struct drm_i915_gem_object *obj; |
Chris Wilson | 27153f7 | 2010-11-02 11:17:23 +0000 | [diff] [blame] | 1071 | u32 *ptr; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1072 | int ret; |
| 1073 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1074 | obj = i915_gem_alloc_object(ring->dev, 4096); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1075 | if (obj == NULL) |
| 1076 | return -ENOMEM; |
| 1077 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1078 | ret = i915_gem_object_pin(obj, 4096, true); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1079 | if (ret) { |
| 1080 | drm_gem_object_unreference(&obj->base); |
| 1081 | return ret; |
| 1082 | } |
| 1083 | |
| 1084 | ptr = kmap(obj->pages[0]); |
Chris Wilson | 27153f7 | 2010-11-02 11:17:23 +0000 | [diff] [blame] | 1085 | *ptr++ = MI_BATCH_BUFFER_END; |
| 1086 | *ptr++ = MI_NOOP; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1087 | kunmap(obj->pages[0]); |
| 1088 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1089 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1090 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1091 | i915_gem_object_unpin(obj); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1092 | drm_gem_object_unreference(&obj->base); |
| 1093 | return ret; |
| 1094 | } |
| 1095 | |
| 1096 | ring->private = obj; |
| 1097 | } |
| 1098 | |
| 1099 | return init_ring_common(ring); |
| 1100 | } |
| 1101 | |
| 1102 | static int blt_ring_begin(struct intel_ring_buffer *ring, |
| 1103 | int num_dwords) |
| 1104 | { |
| 1105 | if (ring->private) { |
| 1106 | int ret = intel_ring_begin(ring, num_dwords+2); |
| 1107 | if (ret) |
| 1108 | return ret; |
| 1109 | |
| 1110 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); |
| 1111 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); |
| 1112 | |
| 1113 | return 0; |
| 1114 | } else |
| 1115 | return intel_ring_begin(ring, 4); |
| 1116 | } |
| 1117 | |
| 1118 | static void blt_ring_flush(struct intel_ring_buffer *ring, |
| 1119 | u32 invalidate_domains, |
| 1120 | u32 flush_domains) |
| 1121 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1122 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) |
| 1123 | return; |
| 1124 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1125 | if (blt_ring_begin(ring, 4) == 0) { |
| 1126 | intel_ring_emit(ring, MI_FLUSH_DW); |
| 1127 | intel_ring_emit(ring, 0); |
| 1128 | intel_ring_emit(ring, 0); |
| 1129 | intel_ring_emit(ring, 0); |
| 1130 | intel_ring_advance(ring); |
| 1131 | } |
| 1132 | } |
| 1133 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1134 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) |
| 1135 | { |
| 1136 | if (!ring->private) |
| 1137 | return; |
| 1138 | |
| 1139 | i915_gem_object_unpin(ring->private); |
| 1140 | drm_gem_object_unreference(ring->private); |
| 1141 | ring->private = NULL; |
| 1142 | } |
| 1143 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1144 | static const struct intel_ring_buffer gen6_blt_ring = { |
| 1145 | .name = "blt ring", |
| 1146 | .id = RING_BLT, |
| 1147 | .mmio_base = BLT_RING_BASE, |
| 1148 | .size = 32 * PAGE_SIZE, |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1149 | .init = blt_ring_init, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1150 | .write_tail = ring_write_tail, |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1151 | .flush = blt_ring_flush, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1152 | .add_request = gen6_add_request, |
| 1153 | .get_seqno = ring_get_seqno, |
| 1154 | .irq_get = blt_ring_get_irq, |
| 1155 | .irq_put = blt_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1156 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1157 | .cleanup = blt_ring_cleanup, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1158 | }; |
| 1159 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1160 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1161 | { |
| 1162 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1163 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1164 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1165 | *ring = render_ring; |
| 1166 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1167 | ring->add_request = gen6_add_request; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame^] | 1168 | } else if (IS_GEN5(dev)) { |
| 1169 | ring->add_request = pc_render_add_request; |
| 1170 | ring->get_seqno = pc_render_get_seqno; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1171 | } |
| 1172 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1173 | if (!I915_NEED_GFX_HWS(dev)) { |
| 1174 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1175 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1176 | } |
| 1177 | |
| 1178 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1179 | } |
| 1180 | |
| 1181 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 1182 | { |
| 1183 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1184 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1185 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1186 | if (IS_GEN6(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1187 | *ring = gen6_bsd_ring; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1188 | else |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1189 | *ring = bsd_ring; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1190 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1191 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1192 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1193 | |
| 1194 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 1195 | { |
| 1196 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1197 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1198 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1199 | *ring = gen6_blt_ring; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1200 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1201 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1202 | } |