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Eric Anholt7d573822009-01-02 13:33:00 -08001/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Eric Anholt7d573822009-01-02 13:33:00 -080031#include <linux/delay.h>
Damien Lespiau178f7362013-08-06 20:32:18 +010032#include <linux/hdmi.h>
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drmP.h>
Matt Roperc6f95f22015-01-22 16:50:32 -080034#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
Eric Anholt7d573822009-01-02 13:33:00 -080037#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010038#include <drm/i915_drm.h>
Eric Anholt7d573822009-01-02 13:33:00 -080039#include "i915_drv.h"
40
Paulo Zanoni30add222012-10-26 19:05:45 -020041static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020043 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
Paulo Zanoni30add222012-10-26 19:05:45 -020044}
45
Daniel Vetterafba0182012-06-12 16:36:45 +020046static void
47assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48{
Paulo Zanoni30add222012-10-26 19:05:45 -020049 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
Daniel Vetterafba0182012-06-12 16:36:45 +020050 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
52
Paulo Zanoniaffa9352012-11-23 15:30:39 -020053 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
Daniel Vetterafba0182012-06-12 16:36:45 +020054
Paulo Zanonib242b7f2013-02-18 19:00:26 -030055 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
Daniel Vetterafba0182012-06-12 16:36:45 +020056 "HDMI port enabled, expecting disabled\n");
57}
58
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -030059struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
Chris Wilsonea5b2132010-08-04 13:50:23 +010060{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020061 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
Chris Wilsonea5b2132010-08-04 13:50:23 +010064}
65
Chris Wilsondf0e9242010-09-09 16:20:55 +010066static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020068 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
Chris Wilsondf0e9242010-09-09 16:20:55 +010069}
70
Damien Lespiau178f7362013-08-06 20:32:18 +010071static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
David Härdeman3c17fe42010-09-24 21:44:32 +020072{
Damien Lespiau178f7362013-08-06 20:32:18 +010073 switch (type) {
74 case HDMI_INFOFRAME_TYPE_AVI:
Paulo Zanonied517fb2012-05-14 17:12:50 -030075 return VIDEO_DIP_SELECT_AVI;
Damien Lespiau178f7362013-08-06 20:32:18 +010076 case HDMI_INFOFRAME_TYPE_SPD:
Paulo Zanonied517fb2012-05-14 17:12:50 -030077 return VIDEO_DIP_SELECT_SPD;
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +010078 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
Jesse Barnes45187ac2011-08-03 09:22:55 -070080 default:
Ville Syrjäläffc85da2015-12-16 18:10:00 +020081 MISSING_CASE(type);
Paulo Zanonied517fb2012-05-14 17:12:50 -030082 return 0;
Jesse Barnes45187ac2011-08-03 09:22:55 -070083 }
Jesse Barnes45187ac2011-08-03 09:22:55 -070084}
85
Damien Lespiau178f7362013-08-06 20:32:18 +010086static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
Jesse Barnes45187ac2011-08-03 09:22:55 -070087{
Damien Lespiau178f7362013-08-06 20:32:18 +010088 switch (type) {
89 case HDMI_INFOFRAME_TYPE_AVI:
Paulo Zanonied517fb2012-05-14 17:12:50 -030090 return VIDEO_DIP_ENABLE_AVI;
Damien Lespiau178f7362013-08-06 20:32:18 +010091 case HDMI_INFOFRAME_TYPE_SPD:
Paulo Zanonied517fb2012-05-14 17:12:50 -030092 return VIDEO_DIP_ENABLE_SPD;
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +010093 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
Paulo Zanonifa193ff2012-05-04 17:18:20 -030095 default:
Ville Syrjäläffc85da2015-12-16 18:10:00 +020096 MISSING_CASE(type);
Paulo Zanonied517fb2012-05-14 17:12:50 -030097 return 0;
Paulo Zanonifa193ff2012-05-04 17:18:20 -030098 }
Paulo Zanonifa193ff2012-05-04 17:18:20 -030099}
100
Damien Lespiau178f7362013-08-06 20:32:18 +0100101static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300102{
Damien Lespiau178f7362013-08-06 20:32:18 +0100103 switch (type) {
104 case HDMI_INFOFRAME_TYPE_AVI:
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300105 return VIDEO_DIP_ENABLE_AVI_HSW;
Damien Lespiau178f7362013-08-06 20:32:18 +0100106 case HDMI_INFOFRAME_TYPE_SPD:
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300107 return VIDEO_DIP_ENABLE_SPD_HSW;
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300110 default:
Ville Syrjäläffc85da2015-12-16 18:10:00 +0200111 MISSING_CASE(type);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300112 return 0;
113 }
114}
115
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200116static i915_reg_t
117hsw_dip_data_reg(struct drm_i915_private *dev_priv,
118 enum transcoder cpu_transcoder,
119 enum hdmi_infoframe_type type,
120 int i)
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300121{
Damien Lespiau178f7362013-08-06 20:32:18 +0100122 switch (type) {
123 case HDMI_INFOFRAME_TYPE_AVI:
Ville Syrjälä436c6d42015-09-18 20:03:37 +0300124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
Damien Lespiau178f7362013-08-06 20:32:18 +0100125 case HDMI_INFOFRAME_TYPE_SPD:
Ville Syrjälä436c6d42015-09-18 20:03:37 +0300126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100127 case HDMI_INFOFRAME_TYPE_VENDOR:
Ville Syrjälä436c6d42015-09-18 20:03:37 +0300128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300129 default:
Ville Syrjäläffc85da2015-12-16 18:10:00 +0200130 MISSING_CASE(type);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200131 return INVALID_MMIO_REG;
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300132 }
133}
134
Daniel Vettera3da1df2012-05-08 15:19:06 +0200135static void g4x_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100136 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200137 const void *frame, ssize_t len)
Jesse Barnes45187ac2011-08-03 09:22:55 -0700138{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200139 const uint32_t *data = frame;
David Härdeman3c17fe42010-09-24 21:44:32 +0200140 struct drm_device *dev = encoder->dev;
141 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300142 u32 val = I915_READ(VIDEO_DIP_CTL);
Damien Lespiau178f7362013-08-06 20:32:18 +0100143 int i;
David Härdeman3c17fe42010-09-24 21:44:32 +0200144
Paulo Zanoni822974a2012-05-28 16:42:51 -0300145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
146
Paulo Zanoni1d4f85a2012-05-04 17:18:18 -0300147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Damien Lespiau178f7362013-08-06 20:32:18 +0100148 val |= g4x_infoframe_index(type);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700149
Damien Lespiau178f7362013-08-06 20:32:18 +0100150 val &= ~g4x_infoframe_enable(type);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300151
152 I915_WRITE(VIDEO_DIP_CTL, val);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700153
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300154 mmiowb();
Jesse Barnes45187ac2011-08-03 09:22:55 -0700155 for (i = 0; i < len; i += 4) {
David Härdeman3c17fe42010-09-24 21:44:32 +0200156 I915_WRITE(VIDEO_DIP_DATA, *data);
157 data++;
158 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
161 I915_WRITE(VIDEO_DIP_DATA, 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300162 mmiowb();
David Härdeman3c17fe42010-09-24 21:44:32 +0200163
Damien Lespiau178f7362013-08-06 20:32:18 +0100164 val |= g4x_infoframe_enable(type);
Paulo Zanoni60c5ea22012-05-04 17:18:22 -0300165 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200166 val |= VIDEO_DIP_FREQ_VSYNC;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700167
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300168 I915_WRITE(VIDEO_DIP_CTL, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300169 POSTING_READ(VIDEO_DIP_CTL);
David Härdeman3c17fe42010-09-24 21:44:32 +0200170}
171
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200172static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
173 const struct intel_crtc_state *pipe_config)
Jesse Barnese43823e2014-11-05 14:26:08 -0800174{
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200175 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
Jesse Barnes89a35ec2014-11-20 13:24:13 -0800176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
Jesse Barnese43823e2014-11-05 14:26:08 -0800177 u32 val = I915_READ(VIDEO_DIP_CTL);
178
Ville Syrjäläec1dc602015-05-05 17:06:25 +0300179 if ((val & VIDEO_DIP_ENABLE) == 0)
180 return false;
Jesse Barnes89a35ec2014-11-20 13:24:13 -0800181
Ville Syrjäläec1dc602015-05-05 17:06:25 +0300182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
183 return false;
184
185 return val & (VIDEO_DIP_ENABLE_AVI |
186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
Jesse Barnese43823e2014-11-05 14:26:08 -0800187}
188
Paulo Zanonifdf12502012-05-04 17:18:24 -0300189static void ibx_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100190 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200191 const void *frame, ssize_t len)
Paulo Zanonifdf12502012-05-04 17:18:24 -0300192{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200193 const uint32_t *data = frame;
Paulo Zanonifdf12502012-05-04 17:18:24 -0300194 struct drm_device *dev = encoder->dev;
195 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300198 u32 val = I915_READ(reg);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200199 int i;
Paulo Zanonifdf12502012-05-04 17:18:24 -0300200
Paulo Zanoni822974a2012-05-28 16:42:51 -0300201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
202
Paulo Zanonifdf12502012-05-04 17:18:24 -0300203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Damien Lespiau178f7362013-08-06 20:32:18 +0100204 val |= g4x_infoframe_index(type);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300205
Damien Lespiau178f7362013-08-06 20:32:18 +0100206 val &= ~g4x_infoframe_enable(type);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300207
208 I915_WRITE(reg, val);
209
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300210 mmiowb();
Paulo Zanonifdf12502012-05-04 17:18:24 -0300211 for (i = 0; i < len; i += 4) {
212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
213 data++;
214 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300215 /* Write every possible data byte to force correct ECC calculation. */
216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300218 mmiowb();
Paulo Zanonifdf12502012-05-04 17:18:24 -0300219
Damien Lespiau178f7362013-08-06 20:32:18 +0100220 val |= g4x_infoframe_enable(type);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300221 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200222 val |= VIDEO_DIP_FREQ_VSYNC;
Paulo Zanonifdf12502012-05-04 17:18:24 -0300223
224 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300225 POSTING_READ(reg);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300226}
227
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200228static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
229 const struct intel_crtc_state *pipe_config)
Jesse Barnese43823e2014-11-05 14:26:08 -0800230{
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
Jani Nikula052f62f2015-04-29 15:30:07 +0300232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200233 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
Jesse Barnese43823e2014-11-05 14:26:08 -0800235 u32 val = I915_READ(reg);
236
Ville Syrjäläec1dc602015-05-05 17:06:25 +0300237 if ((val & VIDEO_DIP_ENABLE) == 0)
238 return false;
Jani Nikula052f62f2015-04-29 15:30:07 +0300239
Ville Syrjäläec1dc602015-05-05 17:06:25 +0300240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
241 return false;
242
243 return val & (VIDEO_DIP_ENABLE_AVI |
244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
Jesse Barnese43823e2014-11-05 14:26:08 -0800246}
247
Paulo Zanonifdf12502012-05-04 17:18:24 -0300248static void cpt_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100249 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200250 const void *frame, ssize_t len)
Jesse Barnes45187ac2011-08-03 09:22:55 -0700251{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200252 const uint32_t *data = frame;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300257 u32 val = I915_READ(reg);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200258 int i;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700259
Paulo Zanoni822974a2012-05-28 16:42:51 -0300260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
261
Jesse Barnes64a8fc02011-09-22 11:16:00 +0530262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Damien Lespiau178f7362013-08-06 20:32:18 +0100263 val |= g4x_infoframe_index(type);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700264
Paulo Zanoniecb97852012-05-04 17:18:21 -0300265 /* The DIP control register spec says that we need to update the AVI
266 * infoframe without clearing its enable bit */
Damien Lespiau178f7362013-08-06 20:32:18 +0100267 if (type != HDMI_INFOFRAME_TYPE_AVI)
268 val &= ~g4x_infoframe_enable(type);
Paulo Zanoniecb97852012-05-04 17:18:21 -0300269
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300270 I915_WRITE(reg, val);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700271
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300272 mmiowb();
Jesse Barnes45187ac2011-08-03 09:22:55 -0700273 for (i = 0; i < len; i += 4) {
274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
275 data++;
276 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300280 mmiowb();
Jesse Barnes45187ac2011-08-03 09:22:55 -0700281
Damien Lespiau178f7362013-08-06 20:32:18 +0100282 val |= g4x_infoframe_enable(type);
Paulo Zanoni60c5ea22012-05-04 17:18:22 -0300283 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200284 val |= VIDEO_DIP_FREQ_VSYNC;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700285
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300286 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300287 POSTING_READ(reg);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700288}
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700289
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200290static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
291 const struct intel_crtc_state *pipe_config)
Jesse Barnese43823e2014-11-05 14:26:08 -0800292{
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200293 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
294 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
Jesse Barnese43823e2014-11-05 14:26:08 -0800296
Ville Syrjäläec1dc602015-05-05 17:06:25 +0300297 if ((val & VIDEO_DIP_ENABLE) == 0)
298 return false;
299
300 return val & (VIDEO_DIP_ENABLE_AVI |
301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
Jesse Barnese43823e2014-11-05 14:26:08 -0800303}
304
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700305static void vlv_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100306 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200307 const void *frame, ssize_t len)
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700308{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200309 const uint32_t *data = frame;
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700310 struct drm_device *dev = encoder->dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300314 u32 val = I915_READ(reg);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200315 int i;
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700316
Paulo Zanoni822974a2012-05-28 16:42:51 -0300317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
318
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Damien Lespiau178f7362013-08-06 20:32:18 +0100320 val |= g4x_infoframe_index(type);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700321
Damien Lespiau178f7362013-08-06 20:32:18 +0100322 val &= ~g4x_infoframe_enable(type);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300323
324 I915_WRITE(reg, val);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700325
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300326 mmiowb();
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700327 for (i = 0; i < len; i += 4) {
328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
329 data++;
330 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300331 /* Write every possible data byte to force correct ECC calculation. */
332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300334 mmiowb();
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700335
Damien Lespiau178f7362013-08-06 20:32:18 +0100336 val |= g4x_infoframe_enable(type);
Paulo Zanoni60c5ea22012-05-04 17:18:22 -0300337 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200338 val |= VIDEO_DIP_FREQ_VSYNC;
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700339
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300340 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300341 POSTING_READ(reg);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700342}
343
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200344static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
Jesse Barnese43823e2014-11-05 14:26:08 -0800346{
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200347 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
Jesse Barnes535afa22015-04-15 16:52:29 -0700348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200349 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
Jesse Barnese43823e2014-11-05 14:26:08 -0800351
Ville Syrjäläec1dc602015-05-05 17:06:25 +0300352 if ((val & VIDEO_DIP_ENABLE) == 0)
353 return false;
Jesse Barnes535afa22015-04-15 16:52:29 -0700354
Ville Syrjäläec1dc602015-05-05 17:06:25 +0300355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
356 return false;
357
358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
Jesse Barnese43823e2014-11-05 14:26:08 -0800361}
362
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300363static void hsw_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100364 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200365 const void *frame, ssize_t len)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300366{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200367 const uint32_t *data = frame;
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300368 struct drm_device *dev = encoder->dev;
369 struct drm_i915_private *dev_priv = dev->dev_private;
370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Ville Syrjälä436c6d42015-09-18 20:03:37 +0300371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
373 i915_reg_t data_reg;
Damien Lespiau178f7362013-08-06 20:32:18 +0100374 int i;
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300375 u32 val = I915_READ(ctl_reg);
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300376
Ville Syrjälä436c6d42015-09-18 20:03:37 +0300377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300378
Damien Lespiau178f7362013-08-06 20:32:18 +0100379 val &= ~hsw_infoframe_enable(type);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300380 I915_WRITE(ctl_reg, val);
381
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300382 mmiowb();
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300383 for (i = 0; i < len; i += 4) {
Ville Syrjälä436c6d42015-09-18 20:03:37 +0300384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
385 type, i >> 2), *data);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300386 data++;
387 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
Ville Syrjälä436c6d42015-09-18 20:03:37 +0300390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
391 type, i >> 2), 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300392 mmiowb();
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300393
Damien Lespiau178f7362013-08-06 20:32:18 +0100394 val |= hsw_infoframe_enable(type);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300395 I915_WRITE(ctl_reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300396 POSTING_READ(ctl_reg);
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300397}
398
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200399static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
400 const struct intel_crtc_state *pipe_config)
Jesse Barnese43823e2014-11-05 14:26:08 -0800401{
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200402 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
Jesse Barnese43823e2014-11-05 14:26:08 -0800404
Ville Syrjäläec1dc602015-05-05 17:06:25 +0300405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
Jesse Barnese43823e2014-11-05 14:26:08 -0800408}
409
Damien Lespiau5adaea72013-08-06 20:32:19 +0100410/*
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
415 *
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
419 * DW3: ...
420 *
421 * (HB is Header Byte, DB is Data Byte)
422 *
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
425 * bytes by one.
426 */
Damien Lespiau9198ee52013-08-06 20:32:24 +0100427static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
Jesse Barnes45187ac2011-08-03 09:22:55 -0700429{
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Damien Lespiau5adaea72013-08-06 20:32:19 +0100431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
432 ssize_t len;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700433
Damien Lespiau5adaea72013-08-06 20:32:19 +0100434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
436 if (len < 0)
437 return;
438
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
443 buffer[3] = 0;
444 len++;
445
446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700447}
448
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300449static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300450 const struct drm_display_mode *adjusted_mode)
Jesse Barnesb055c8f2011-07-08 11:31:57 -0700451{
Ville Syrjäläabedc072013-01-17 16:31:31 +0200452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Daniel Vetter50f3b012013-03-27 00:44:56 +0100453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Damien Lespiau5adaea72013-08-06 20:32:19 +0100454 union hdmi_infoframe frame;
455 int ret;
Jesse Barnesb055c8f2011-07-08 11:31:57 -0700456
Damien Lespiau5adaea72013-08-06 20:32:19 +0100457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
458 adjusted_mode);
459 if (ret < 0) {
460 DRM_ERROR("couldn't fill AVI infoframe\n");
461 return;
462 }
Paulo Zanonic846b612012-04-13 16:31:41 -0300463
Ville Syrjäläabedc072013-01-17 16:31:31 +0200464 if (intel_hdmi->rgb_quant_range_selectable) {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200465 if (intel_crtc->config->limited_color_range)
Damien Lespiau5adaea72013-08-06 20:32:19 +0100466 frame.avi.quantization_range =
467 HDMI_QUANTIZATION_RANGE_LIMITED;
Ville Syrjäläabedc072013-01-17 16:31:31 +0200468 else
Damien Lespiau5adaea72013-08-06 20:32:19 +0100469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_FULL;
Ville Syrjäläabedc072013-01-17 16:31:31 +0200471 }
472
Damien Lespiau9198ee52013-08-06 20:32:24 +0100473 intel_write_infoframe(encoder, &frame);
Jesse Barnesb055c8f2011-07-08 11:31:57 -0700474}
475
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300476static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
Jesse Barnesc0864cb2011-08-03 09:22:56 -0700477{
Damien Lespiau5adaea72013-08-06 20:32:19 +0100478 union hdmi_infoframe frame;
479 int ret;
Jesse Barnesc0864cb2011-08-03 09:22:56 -0700480
Damien Lespiau5adaea72013-08-06 20:32:19 +0100481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
482 if (ret < 0) {
483 DRM_ERROR("couldn't fill SPD infoframe\n");
484 return;
485 }
Jesse Barnesc0864cb2011-08-03 09:22:56 -0700486
Damien Lespiau5adaea72013-08-06 20:32:19 +0100487 frame.spd.sdi = HDMI_SPD_SDI_PC;
488
Damien Lespiau9198ee52013-08-06 20:32:24 +0100489 intel_write_infoframe(encoder, &frame);
Jesse Barnesc0864cb2011-08-03 09:22:56 -0700490}
491
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100492static void
493intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300494 const struct drm_display_mode *adjusted_mode)
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100495{
496 union hdmi_infoframe frame;
497 int ret;
498
499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
500 adjusted_mode);
501 if (ret < 0)
502 return;
503
504 intel_write_infoframe(encoder, &frame);
505}
506
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300507static void g4x_set_infoframes(struct drm_encoder *encoder,
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200508 bool enable,
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300509 const struct drm_display_mode *adjusted_mode)
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300510{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300511 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
Ville Syrjälä69fde0a2013-01-24 15:29:26 +0200512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200514 i915_reg_t reg = VIDEO_DIP_CTL;
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300515 u32 val = I915_READ(reg);
Ville Syrjälä822cdc52014-01-23 23:15:34 +0200516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300517
Daniel Vetterafba0182012-06-12 16:36:45 +0200518 assert_hdmi_port_disabled(intel_hdmi);
519
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300520 /* If the registers were not initialized yet, they might be zeroes,
521 * which means we're selecting the AVI DIP and we're setting its
522 * frequency to once. This seems to really confuse the HW and make
523 * things stop working (the register spec says the AVI always needs to
524 * be sent every VSync). So here we avoid writing to the register more
525 * than we need and also explicitly select the AVI DIP and explicitly
526 * set its frequency to every VSync. Avoiding to write it twice seems to
527 * be enough to solve the problem, but being defensive shouldn't hurt us
528 * either. */
529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
530
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200531 if (!enable) {
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300532 if (!(val & VIDEO_DIP_ENABLE))
533 return;
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300534 if (port != (val & VIDEO_DIP_PORT_MASK)) {
535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
536 (val & VIDEO_DIP_PORT_MASK) >> 29);
537 return;
538 }
539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300541 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300542 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300543 return;
544 }
545
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300546 if (port != (val & VIDEO_DIP_PORT_MASK)) {
547 if (val & VIDEO_DIP_ENABLE) {
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
549 (val & VIDEO_DIP_PORT_MASK) >> 29);
550 return;
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300551 }
552 val &= ~VIDEO_DIP_PORT_MASK;
553 val |= port;
554 }
555
Paulo Zanoni822974a2012-05-28 16:42:51 -0300556 val |= VIDEO_DIP_ENABLE;
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300557 val &= ~(VIDEO_DIP_ENABLE_AVI |
558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300559
Paulo Zanonif278d972012-05-28 16:42:50 -0300560 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300561 POSTING_READ(reg);
Paulo Zanonif278d972012-05-28 16:42:50 -0300562
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
564 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300566}
567
Ville Syrjälä6d674152015-05-05 17:06:20 +0300568static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
569{
570 struct drm_device *dev = encoder->dev;
571 struct drm_connector *connector;
572
573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
574
575 /*
576 * HDMI cloning is only supported on g4x which doesn't
577 * support deep color or GCP infoframes anyway so no
578 * need to worry about multiple HDMI sinks here.
579 */
580 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
581 if (connector->encoder == encoder)
582 return connector->display_info.bpc > 8;
583
584 return false;
585}
586
Ville Syrjälä12aa3292015-05-05 17:06:21 +0300587/*
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
589 *
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
595 * phase of 0
596 */
597static bool gcp_default_phase_possible(int pipe_bpp,
598 const struct drm_display_mode *mode)
599{
600 unsigned int pixels_per_group;
601
602 switch (pipe_bpp) {
603 case 30:
604 /* 4 pixels in 5 clocks */
605 pixels_per_group = 4;
606 break;
607 case 36:
608 /* 2 pixels in 3 clocks */
609 pixels_per_group = 2;
610 break;
611 case 48:
612 /* 1 pixel in 2 clocks */
613 pixels_per_group = 1;
614 break;
615 default:
616 /* phase information not relevant for 8bpc */
617 return false;
618 }
619
620 return mode->crtc_hdisplay % pixels_per_group == 0 &&
621 mode->crtc_htotal % pixels_per_group == 0 &&
622 mode->crtc_hblank_start % pixels_per_group == 0 &&
623 mode->crtc_hblank_end % pixels_per_group == 0 &&
624 mode->crtc_hsync_start % pixels_per_group == 0 &&
625 mode->crtc_hsync_end % pixels_per_group == 0 &&
626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
627 mode->crtc_htotal/2 % pixels_per_group == 0);
628}
629
Ville Syrjälä6d674152015-05-05 17:06:20 +0300630static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
631{
632 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200634 i915_reg_t reg;
635 u32 val = 0;
Ville Syrjälä6d674152015-05-05 17:06:20 +0300636
637 if (HAS_DDI(dev_priv))
638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
Wayne Boyer666a4532015-12-09 12:29:35 -0800639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Ville Syrjälä6d674152015-05-05 17:06:20 +0300640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
641 else if (HAS_PCH_SPLIT(dev_priv->dev))
642 reg = TVIDEO_DIP_GCP(crtc->pipe);
643 else
644 return false;
645
646 /* Indicate color depth whenever the sink supports deep color */
647 if (hdmi_sink_is_deep_color(encoder))
648 val |= GCP_COLOR_INDICATION;
649
Ville Syrjälä12aa3292015-05-05 17:06:21 +0300650 /* Enable default_phase whenever the display mode is suitably aligned */
651 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
652 &crtc->config->base.adjusted_mode))
653 val |= GCP_DEFAULT_PHASE_ENABLE;
654
Ville Syrjälä6d674152015-05-05 17:06:20 +0300655 I915_WRITE(reg, val);
656
657 return val != 0;
658}
659
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300660static void ibx_set_infoframes(struct drm_encoder *encoder,
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200661 bool enable,
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300662 const struct drm_display_mode *adjusted_mode)
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300663{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300664 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Ville Syrjälä69fde0a2013-01-24 15:29:26 +0200666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300669 u32 val = I915_READ(reg);
Ville Syrjälä822cdc52014-01-23 23:15:34 +0200670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300671
Daniel Vetterafba0182012-06-12 16:36:45 +0200672 assert_hdmi_port_disabled(intel_hdmi);
673
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300674 /* See the big comment in g4x_set_infoframes() */
675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
676
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200677 if (!enable) {
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300678 if (!(val & VIDEO_DIP_ENABLE))
679 return;
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300683 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300684 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300685 return;
686 }
687
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300688 if (port != (val & VIDEO_DIP_PORT_MASK)) {
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300689 WARN(val & VIDEO_DIP_ENABLE,
690 "DIP already enabled on port %c\n",
691 (val & VIDEO_DIP_PORT_MASK) >> 29);
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300692 val &= ~VIDEO_DIP_PORT_MASK;
693 val |= port;
694 }
695
Paulo Zanoni822974a2012-05-28 16:42:51 -0300696 val |= VIDEO_DIP_ENABLE;
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300697 val &= ~(VIDEO_DIP_ENABLE_AVI |
698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300700
Ville Syrjälä6d674152015-05-05 17:06:20 +0300701 if (intel_hdmi_set_gcp_infoframe(encoder))
702 val |= VIDEO_DIP_ENABLE_GCP;
703
Paulo Zanonif278d972012-05-28 16:42:50 -0300704 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300705 POSTING_READ(reg);
Paulo Zanonif278d972012-05-28 16:42:50 -0300706
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
708 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300710}
711
712static void cpt_set_infoframes(struct drm_encoder *encoder,
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200713 bool enable,
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300714 const struct drm_display_mode *adjusted_mode)
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300715{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300716 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300720 u32 val = I915_READ(reg);
721
Daniel Vetterafba0182012-06-12 16:36:45 +0200722 assert_hdmi_port_disabled(intel_hdmi);
723
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300724 /* See the big comment in g4x_set_infoframes() */
725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
726
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200727 if (!enable) {
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300728 if (!(val & VIDEO_DIP_ENABLE))
729 return;
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300733 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300734 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300735 return;
736 }
737
Paulo Zanoni822974a2012-05-28 16:42:51 -0300738 /* Set both together, unset both together: see the spec. */
739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300742
Ville Syrjälä6d674152015-05-05 17:06:20 +0300743 if (intel_hdmi_set_gcp_infoframe(encoder))
744 val |= VIDEO_DIP_ENABLE_GCP;
745
Paulo Zanoni822974a2012-05-28 16:42:51 -0300746 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300747 POSTING_READ(reg);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300748
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
750 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300752}
753
754static void vlv_set_infoframes(struct drm_encoder *encoder,
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200755 bool enable,
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300756 const struct drm_display_mode *adjusted_mode)
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300757{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300758 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
Jesse Barnes6a2b8022014-04-02 10:08:51 -0700759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300763 u32 val = I915_READ(reg);
Jesse Barnes6a2b8022014-04-02 10:08:51 -0700764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300765
Daniel Vetterafba0182012-06-12 16:36:45 +0200766 assert_hdmi_port_disabled(intel_hdmi);
767
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300768 /* See the big comment in g4x_set_infoframes() */
769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
770
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200771 if (!enable) {
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300772 if (!(val & VIDEO_DIP_ENABLE))
773 return;
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300777 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300778 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300779 return;
780 }
781
Jesse Barnes6a2b8022014-04-02 10:08:51 -0700782 if (port != (val & VIDEO_DIP_PORT_MASK)) {
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300783 WARN(val & VIDEO_DIP_ENABLE,
784 "DIP already enabled on port %c\n",
785 (val & VIDEO_DIP_PORT_MASK) >> 29);
Jesse Barnes6a2b8022014-04-02 10:08:51 -0700786 val &= ~VIDEO_DIP_PORT_MASK;
787 val |= port;
788 }
789
Paulo Zanoni822974a2012-05-28 16:42:51 -0300790 val |= VIDEO_DIP_ENABLE;
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300791 val &= ~(VIDEO_DIP_ENABLE_AVI |
792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300794
Ville Syrjälä6d674152015-05-05 17:06:20 +0300795 if (intel_hdmi_set_gcp_infoframe(encoder))
796 val |= VIDEO_DIP_ENABLE_GCP;
797
Paulo Zanoni822974a2012-05-28 16:42:51 -0300798 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300799 POSTING_READ(reg);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300800
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
802 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300804}
805
806static void hsw_set_infoframes(struct drm_encoder *encoder,
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200807 bool enable,
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300808 const struct drm_display_mode *adjusted_mode)
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300809{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300810 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300814 u32 val = I915_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300815
Daniel Vetterafba0182012-06-12 16:36:45 +0200816 assert_hdmi_port_disabled(intel_hdmi);
817
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
821
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200822 if (!enable) {
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +0300823 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300824 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300825 return;
826 }
827
Ville Syrjälä6d674152015-05-05 17:06:20 +0300828 if (intel_hdmi_set_gcp_infoframe(encoder))
829 val |= VIDEO_DIP_ENABLE_GCP_HSW;
830
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300831 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300832 POSTING_READ(reg);
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300833
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
835 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300837}
838
Daniel Vetter4cde8a22014-04-24 23:54:56 +0200839static void intel_hdmi_prepare(struct intel_encoder *encoder)
Eric Anholt7d573822009-01-02 13:33:00 -0800840{
Daniel Vetterc59423a2013-07-21 21:37:04 +0200841 struct drm_device *dev = encoder->base.dev;
Eric Anholt7d573822009-01-02 13:33:00 -0800842 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterc59423a2013-07-21 21:37:04 +0200843 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
844 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300845 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300846 u32 hdmi_val;
Eric Anholt7d573822009-01-02 13:33:00 -0800847
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300848 hdmi_val = SDVO_ENCODING_HDMI;
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +0300849 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
850 hdmi_val |= HDMI_COLOR_RANGE_16_235;
Adam Jacksonb599c0b2010-07-16 14:46:31 -0400851 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300852 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
Adam Jacksonb599c0b2010-07-16 14:46:31 -0400853 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300854 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
Eric Anholt7d573822009-01-02 13:33:00 -0800855
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200856 if (crtc->config->pipe_bpp > 24)
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -0300857 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
Jesse Barnes020f6702011-06-24 12:19:25 -0700858 else
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -0300859 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
Jesse Barnes020f6702011-06-24 12:19:25 -0700860
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200861 if (crtc->config->has_hdmi_sink)
Paulo Zanonidc0fa712013-02-19 16:21:46 -0300862 hdmi_val |= HDMI_MODE_SELECT_HDMI;
Zhenyu Wang2e3d6002010-09-10 10:39:40 +0800863
Jesse Barnes75770562011-10-12 09:01:58 -0700864 if (HAS_PCH_CPT(dev))
Daniel Vetterc59423a2013-07-21 21:37:04 +0200865 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
Chon Ming Lee44f37d12014-04-09 13:28:21 +0300866 else if (IS_CHERRYVIEW(dev))
867 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
Paulo Zanonidc0fa712013-02-19 16:21:46 -0300868 else
Daniel Vetterc59423a2013-07-21 21:37:04 +0200869 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
Eric Anholt7d573822009-01-02 13:33:00 -0800870
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300871 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
872 POSTING_READ(intel_hdmi->hdmi_reg);
Eric Anholt7d573822009-01-02 13:33:00 -0800873}
874
Daniel Vetter85234cd2012-07-02 13:27:29 +0200875static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
876 enum pipe *pipe)
Eric Anholt7d573822009-01-02 13:33:00 -0800877{
Daniel Vetter85234cd2012-07-02 13:27:29 +0200878 struct drm_device *dev = encoder->base.dev;
Eric Anholt7d573822009-01-02 13:33:00 -0800879 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter85234cd2012-07-02 13:27:29 +0200880 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
Imre Deak6d129be2014-03-05 16:20:54 +0200881 enum intel_display_power_domain power_domain;
Daniel Vetter85234cd2012-07-02 13:27:29 +0200882 u32 tmp;
883
Imre Deak6d129be2014-03-05 16:20:54 +0200884 power_domain = intel_display_port_power_domain(encoder);
Daniel Vetterf458ebb2014-09-30 10:56:39 +0200885 if (!intel_display_power_is_enabled(dev_priv, power_domain))
Imre Deak6d129be2014-03-05 16:20:54 +0200886 return false;
887
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300888 tmp = I915_READ(intel_hdmi->hdmi_reg);
Daniel Vetter85234cd2012-07-02 13:27:29 +0200889
890 if (!(tmp & SDVO_ENABLE))
891 return false;
892
893 if (HAS_PCH_CPT(dev))
894 *pipe = PORT_TO_PIPE_CPT(tmp);
Ville Syrjälä71485e02014-04-09 13:28:55 +0300895 else if (IS_CHERRYVIEW(dev))
896 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
Daniel Vetter85234cd2012-07-02 13:27:29 +0200897 else
898 *pipe = PORT_TO_PIPE(tmp);
899
900 return true;
901}
902
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700903static void intel_hdmi_get_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200904 struct intel_crtc_state *pipe_config)
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700905{
906 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
Ville Syrjälä8c875fc2014-09-12 15:46:29 +0300907 struct drm_device *dev = encoder->base.dev;
908 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700909 u32 tmp, flags = 0;
Ville Syrjälä18442d02013-09-13 16:00:08 +0300910 int dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700911
912 tmp = I915_READ(intel_hdmi->hdmi_reg);
913
914 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
915 flags |= DRM_MODE_FLAG_PHSYNC;
916 else
917 flags |= DRM_MODE_FLAG_NHSYNC;
918
919 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
920 flags |= DRM_MODE_FLAG_PVSYNC;
921 else
922 flags |= DRM_MODE_FLAG_NVSYNC;
923
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200924 if (tmp & HDMI_MODE_SELECT_HDMI)
925 pipe_config->has_hdmi_sink = true;
926
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200927 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
Jesse Barnese43823e2014-11-05 14:26:08 -0800928 pipe_config->has_infoframe = true;
929
Jani Nikulac84db772014-09-17 15:34:58 +0300930 if (tmp & SDVO_AUDIO_ENABLE)
Daniel Vetter9ed109a2014-04-24 23:54:52 +0200931 pipe_config->has_audio = true;
932
Ville Syrjälä8c875fc2014-09-12 15:46:29 +0300933 if (!HAS_PCH_SPLIT(dev) &&
934 tmp & HDMI_COLOR_RANGE_16_235)
935 pipe_config->limited_color_range = true;
936
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +0200937 pipe_config->base.adjusted_mode.flags |= flags;
Ville Syrjälä18442d02013-09-13 16:00:08 +0300938
939 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
940 dotclock = pipe_config->port_clock * 2 / 3;
941 else
942 dotclock = pipe_config->port_clock;
943
Ville Syrjäläbe69a132015-05-05 17:06:26 +0300944 if (pipe_config->pixel_multiplier)
945 dotclock /= pipe_config->pixel_multiplier;
946
Ville Syrjälä18442d02013-09-13 16:00:08 +0300947 if (HAS_PCH_SPLIT(dev_priv->dev))
948 ironlake_check_encoder_dotclock(pipe_config, dotclock);
949
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +0200950 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700951}
952
Ville Syrjäläd1b15892015-05-05 17:06:19 +0300953static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
954{
955 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
956
957 WARN_ON(!crtc->config->has_hdmi_sink);
958 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
959 pipe_name(crtc->pipe));
960 intel_audio_codec_enable(encoder);
961}
962
Ville Syrjäläbf868c72015-05-05 17:06:23 +0300963static void g4x_enable_hdmi(struct intel_encoder *encoder)
Eric Anholt7d573822009-01-02 13:33:00 -0800964{
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200965 struct drm_device *dev = encoder->base.dev;
Eric Anholt7d573822009-01-02 13:33:00 -0800966 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläbf868c72015-05-05 17:06:23 +0300967 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200968 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
Eric Anholt7d573822009-01-02 13:33:00 -0800969 u32 temp;
970
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300971 temp = I915_READ(intel_hdmi->hdmi_reg);
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000972
Ville Syrjäläbf868c72015-05-05 17:06:23 +0300973 temp |= SDVO_ENABLE;
974 if (crtc->config->has_audio)
975 temp |= SDVO_AUDIO_ENABLE;
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200976
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300977 I915_WRITE(intel_hdmi->hdmi_reg, temp);
978 POSTING_READ(intel_hdmi->hdmi_reg);
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200979
Ville Syrjäläbf868c72015-05-05 17:06:23 +0300980 if (crtc->config->has_audio)
981 intel_enable_hdmi_audio(encoder);
982}
983
984static void ibx_enable_hdmi(struct intel_encoder *encoder)
985{
986 struct drm_device *dev = encoder->base.dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
989 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
990 u32 temp;
991
992 temp = I915_READ(intel_hdmi->hdmi_reg);
993
994 temp |= SDVO_ENABLE;
995 if (crtc->config->has_audio)
996 temp |= SDVO_AUDIO_ENABLE;
997
998 /*
999 * HW workaround, need to write this twice for issue
1000 * that may result in first write getting masked.
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001001 */
Ville Syrjäläbf868c72015-05-05 17:06:23 +03001002 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1003 POSTING_READ(intel_hdmi->hdmi_reg);
1004 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1005 POSTING_READ(intel_hdmi->hdmi_reg);
1006
1007 /*
1008 * HW workaround, need to toggle enable bit off and on
1009 * for 12bpc with pixel repeat.
1010 *
1011 * FIXME: BSpec says this should be done at the end of
1012 * of the modeset sequence, so not sure if this isn't too soon.
1013 */
1014 if (crtc->config->pipe_bpp > 24 &&
1015 crtc->config->pixel_multiplier > 1) {
1016 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1017 POSTING_READ(intel_hdmi->hdmi_reg);
1018
1019 /*
1020 * HW workaround, need to write this twice for issue
1021 * that may result in first write getting masked.
1022 */
1023 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1024 POSTING_READ(intel_hdmi->hdmi_reg);
Paulo Zanonib242b7f2013-02-18 19:00:26 -03001025 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1026 POSTING_READ(intel_hdmi->hdmi_reg);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001027 }
Jani Nikulac1dec792014-10-27 16:26:56 +02001028
Ville Syrjäläbf868c72015-05-05 17:06:23 +03001029 if (crtc->config->has_audio)
Ville Syrjäläd1b15892015-05-05 17:06:19 +03001030 intel_enable_hdmi_audio(encoder);
1031}
1032
1033static void cpt_enable_hdmi(struct intel_encoder *encoder)
1034{
1035 struct drm_device *dev = encoder->base.dev;
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1038 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1039 enum pipe pipe = crtc->pipe;
1040 u32 temp;
1041
1042 temp = I915_READ(intel_hdmi->hdmi_reg);
1043
1044 temp |= SDVO_ENABLE;
1045 if (crtc->config->has_audio)
1046 temp |= SDVO_AUDIO_ENABLE;
1047
1048 /*
1049 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1050 *
1051 * The procedure for 12bpc is as follows:
1052 * 1. disable HDMI clock gating
1053 * 2. enable HDMI with 8bpc
1054 * 3. enable HDMI with 12bpc
1055 * 4. enable HDMI clock gating
1056 */
1057
1058 if (crtc->config->pipe_bpp > 24) {
1059 I915_WRITE(TRANS_CHICKEN1(pipe),
1060 I915_READ(TRANS_CHICKEN1(pipe)) |
1061 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1062
1063 temp &= ~SDVO_COLOR_FORMAT_MASK;
1064 temp |= SDVO_COLOR_FORMAT_8bpc;
Jani Nikulac1dec792014-10-27 16:26:56 +02001065 }
Ville Syrjäläd1b15892015-05-05 17:06:19 +03001066
1067 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1068 POSTING_READ(intel_hdmi->hdmi_reg);
1069
1070 if (crtc->config->pipe_bpp > 24) {
1071 temp &= ~SDVO_COLOR_FORMAT_MASK;
1072 temp |= HDMI_COLOR_FORMAT_12bpc;
1073
1074 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1075 POSTING_READ(intel_hdmi->hdmi_reg);
1076
1077 I915_WRITE(TRANS_CHICKEN1(pipe),
1078 I915_READ(TRANS_CHICKEN1(pipe)) &
1079 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1080 }
1081
1082 if (crtc->config->has_audio)
1083 intel_enable_hdmi_audio(encoder);
Jani Nikulab76cf762013-07-30 12:20:31 +03001084}
Jesse Barnes89b667f2013-04-18 14:51:36 -07001085
Jani Nikulab76cf762013-07-30 12:20:31 +03001086static void vlv_enable_hdmi(struct intel_encoder *encoder)
1087{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001088}
1089
1090static void intel_disable_hdmi(struct intel_encoder *encoder)
1091{
1092 struct drm_device *dev = encoder->base.dev;
1093 struct drm_i915_private *dev_priv = dev->dev_private;
1094 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
Jani Nikula495a5bb2014-10-27 16:26:55 +02001095 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001096 u32 temp;
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001097
Paulo Zanonib242b7f2013-02-18 19:00:26 -03001098 temp = I915_READ(intel_hdmi->hdmi_reg);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001099
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03001100 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
Paulo Zanonib242b7f2013-02-18 19:00:26 -03001101 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1102 POSTING_READ(intel_hdmi->hdmi_reg);
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03001103
1104 /*
1105 * HW workaround for IBX, we need to move the port
1106 * to transcoder A after disabling it to allow the
1107 * matching DP port to be enabled on transcoder A.
1108 */
1109 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
Ville Syrjälä0c241d52015-10-30 19:23:22 +02001110 /*
1111 * We get CPU/PCH FIFO underruns on the other pipe when
1112 * doing the workaround. Sweep them under the rug.
1113 */
1114 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1115 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1116
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03001117 temp &= ~SDVO_PIPE_B_SELECT;
1118 temp |= SDVO_ENABLE;
1119 /*
1120 * HW workaround, need to write this twice for issue
1121 * that may result in first write getting masked.
1122 */
1123 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1124 POSTING_READ(intel_hdmi->hdmi_reg);
1125 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1126 POSTING_READ(intel_hdmi->hdmi_reg);
1127
1128 temp &= ~SDVO_ENABLE;
1129 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1130 POSTING_READ(intel_hdmi->hdmi_reg);
Ville Syrjälä0c241d52015-10-30 19:23:22 +02001131
1132 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1133 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1134 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03001135 }
Ville Syrjälä6d674152015-05-05 17:06:20 +03001136
Ville Syrjälä0be6f0c2015-05-05 17:06:24 +03001137 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
Eric Anholt7d573822009-01-02 13:33:00 -08001138}
1139
Ville Syrjäläa4790ce2015-05-05 17:17:35 +03001140static void g4x_disable_hdmi(struct intel_encoder *encoder)
1141{
1142 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1143
1144 if (crtc->config->has_audio)
1145 intel_audio_codec_disable(encoder);
1146
1147 intel_disable_hdmi(encoder);
1148}
1149
1150static void pch_disable_hdmi(struct intel_encoder *encoder)
1151{
1152 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1153
1154 if (crtc->config->has_audio)
1155 intel_audio_codec_disable(encoder);
1156}
1157
1158static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1159{
1160 intel_disable_hdmi(encoder);
1161}
1162
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001163static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
Daniel Vetter7d148ef2013-07-22 18:02:39 +02001164{
1165 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1166
Ville Syrjälä40478452014-03-27 11:08:45 +02001167 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
Daniel Vetter7d148ef2013-07-22 18:02:39 +02001168 return 165000;
Damien Lespiaue3c33572013-11-02 21:07:51 -07001169 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
Daniel Vetter7d148ef2013-07-22 18:02:39 +02001170 return 300000;
1171 else
1172 return 225000;
1173}
1174
Damien Lespiauc19de8e2013-11-28 15:29:18 +00001175static enum drm_mode_status
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001176hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1177 int clock, bool respect_dvi_limit)
1178{
1179 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1180
1181 if (clock < 25000)
1182 return MODE_CLOCK_LOW;
1183 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1184 return MODE_CLOCK_HIGH;
1185
Ville Syrjälä5e6ccc02015-07-06 14:44:11 +03001186 /* BXT DPLL can't generate 223-240 MHz */
1187 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1188 return MODE_CLOCK_RANGE;
1189
1190 /* CHV DPLL can't generate 216-240 MHz */
1191 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001192 return MODE_CLOCK_RANGE;
1193
1194 return MODE_OK;
1195}
1196
1197static enum drm_mode_status
Damien Lespiauc19de8e2013-11-28 15:29:18 +00001198intel_hdmi_mode_valid(struct drm_connector *connector,
1199 struct drm_display_mode *mode)
Eric Anholt7d573822009-01-02 13:33:00 -08001200{
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001201 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1202 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1203 enum drm_mode_status status;
1204 int clock;
Eric Anholt7d573822009-01-02 13:33:00 -08001205
1206 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1207 return MODE_NO_DBLESCAN;
1208
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001209 clock = mode->clock;
1210 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1211 clock *= 2;
1212
1213 /* check if we can do 8bpc */
1214 status = hdmi_port_clock_valid(hdmi, clock, true);
1215
1216 /* if we can't do 8bpc we may still be able to do 12bpc */
1217 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1218 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1219
1220 return status;
Eric Anholt7d573822009-01-02 13:33:00 -08001221}
1222
Ander Conselvan de Oliveira77f06c82015-03-20 16:18:11 +02001223static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
Ville Syrjälä71800632014-03-03 16:15:29 +02001224{
Ander Conselvan de Oliveira77f06c82015-03-20 16:18:11 +02001225 struct drm_device *dev = crtc_state->base.crtc->dev;
1226 struct drm_atomic_state *state;
Ville Syrjälä71800632014-03-03 16:15:29 +02001227 struct intel_encoder *encoder;
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +03001228 struct drm_connector *connector;
Ander Conselvan de Oliveira77f06c82015-03-20 16:18:11 +02001229 struct drm_connector_state *connector_state;
Ville Syrjälä71800632014-03-03 16:15:29 +02001230 int count = 0, count_hdmi = 0;
Ander Conselvan de Oliveira77f06c82015-03-20 16:18:11 +02001231 int i;
Ville Syrjälä71800632014-03-03 16:15:29 +02001232
Sonika Jindalf227ae92014-07-21 15:23:45 +05301233 if (HAS_GMCH_DISPLAY(dev))
Ville Syrjälä71800632014-03-03 16:15:29 +02001234 return false;
1235
Ander Conselvan de Oliveira77f06c82015-03-20 16:18:11 +02001236 state = crtc_state->base.state;
1237
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +03001238 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira77f06c82015-03-20 16:18:11 +02001239 if (connector_state->crtc != crtc_state->base.crtc)
1240 continue;
1241
1242 encoder = to_intel_encoder(connector_state->best_encoder);
1243
Ville Syrjälä71800632014-03-03 16:15:29 +02001244 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1245 count++;
1246 }
1247
1248 /*
1249 * HDMI 12bpc affects the clocks, so it's only possible
1250 * when not cloning with other encoder types.
1251 */
1252 return count_hdmi > 0 && count_hdmi == count;
1253}
1254
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01001255bool intel_hdmi_compute_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001256 struct intel_crtc_state *pipe_config)
Eric Anholt7d573822009-01-02 13:33:00 -08001257{
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01001258 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1259 struct drm_device *dev = encoder->base.dev;
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02001260 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001261 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1262 int clock_12bpc = clock_8bpc * 3 / 2;
Daniel Vettere29c22c2013-02-21 00:00:16 +01001263 int desired_bpp;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02001264
Daniel Vetter6897b4b2014-04-24 23:54:47 +02001265 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1266
Jesse Barnese43823e2014-11-05 14:26:08 -08001267 if (pipe_config->has_hdmi_sink)
1268 pipe_config->has_infoframe = true;
1269
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001270 if (intel_hdmi->color_range_auto) {
1271 /* See CEA-861-E - 5.1 Default Encoding Parameters */
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03001272 pipe_config->limited_color_range =
1273 pipe_config->has_hdmi_sink &&
1274 drm_match_cea_mode(adjusted_mode) > 1;
1275 } else {
1276 pipe_config->limited_color_range =
1277 intel_hdmi->limited_color_range;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001278 }
1279
Clint Taylor697c4072014-09-02 17:03:36 -07001280 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1281 pipe_config->pixel_multiplier = 2;
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001282 clock_8bpc *= 2;
Ville Syrjälä3320e372015-05-05 17:06:27 +03001283 clock_12bpc *= 2;
Clint Taylor697c4072014-09-02 17:03:36 -07001284 }
1285
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01001286 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1287 pipe_config->has_pch_encoder = true;
1288
Daniel Vetter9ed109a2014-04-24 23:54:52 +02001289 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1290 pipe_config->has_audio = true;
1291
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001292 /*
1293 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1294 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
Daniel Vetter325b9d02013-04-19 11:24:33 +02001295 * outputs. We also need to check that the higher clock still fits
1296 * within limits.
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001297 */
Daniel Vetter6897b4b2014-04-24 23:54:47 +02001298 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001299 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
Ville Syrjälä7a0baa62015-06-30 15:33:54 +03001300 hdmi_12bpc_possible(pipe_config)) {
Daniel Vettere29c22c2013-02-21 00:00:16 +01001301 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1302 desired_bpp = 12*3;
Daniel Vetter325b9d02013-04-19 11:24:33 +02001303
1304 /* Need to adjust the port link by 1.5x for 12bpc. */
Daniel Vetterff9a6752013-06-01 17:16:21 +02001305 pipe_config->port_clock = clock_12bpc;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001306 } else {
Daniel Vettere29c22c2013-02-21 00:00:16 +01001307 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1308 desired_bpp = 8*3;
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001309
1310 pipe_config->port_clock = clock_8bpc;
Daniel Vettere29c22c2013-02-21 00:00:16 +01001311 }
1312
1313 if (!pipe_config->bw_constrained) {
1314 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1315 pipe_config->pipe_bpp = desired_bpp;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001316 }
1317
Ville Syrjäläe64e7392015-06-30 19:23:59 +03001318 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1319 false) != MODE_OK) {
1320 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
Daniel Vetter325b9d02013-04-19 11:24:33 +02001321 return false;
1322 }
1323
Ville Syrjälä28b468a2015-09-08 13:40:48 +03001324 /* Set user selected PAR to incoming mode's member */
1325 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1326
Eric Anholt7d573822009-01-02 13:33:00 -08001327 return true;
1328}
1329
Chris Wilson953ece6972014-09-02 20:04:01 +01001330static void
1331intel_hdmi_unset_edid(struct drm_connector *connector)
Ma Ling9dff6af2009-04-02 13:13:26 +08001332{
Chris Wilsondf0e9242010-09-09 16:20:55 +01001333 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
Imre Deak671dedd2014-03-05 16:20:53 +02001334
Chris Wilsonea5b2132010-08-04 13:50:23 +01001335 intel_hdmi->has_hdmi_sink = false;
Zhenyu Wang2e3d6002010-09-10 10:39:40 +08001336 intel_hdmi->has_audio = false;
Ville Syrjäläabedc072013-01-17 16:31:31 +02001337 intel_hdmi->rgb_quant_range_selectable = false;
ling.ma@intel.com2ded9e22009-07-16 17:23:09 +08001338
Chris Wilson953ece6972014-09-02 20:04:01 +01001339 kfree(to_intel_connector(connector)->detect_edid);
1340 to_intel_connector(connector)->detect_edid = NULL;
Ma Ling9dff6af2009-04-02 13:13:26 +08001341}
1342
Chris Wilson953ece6972014-09-02 20:04:01 +01001343static bool
Sonika Jindal237ed862015-09-15 09:44:20 +05301344intel_hdmi_set_edid(struct drm_connector *connector, bool force)
Eric Anholt7d573822009-01-02 13:33:00 -08001345{
Chris Wilson953ece6972014-09-02 20:04:01 +01001346 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1347 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
Sonika Jindal237ed862015-09-15 09:44:20 +05301348 struct edid *edid = NULL;
Chris Wilson953ece6972014-09-02 20:04:01 +01001349 bool connected = false;
Eric Anholt7d573822009-01-02 13:33:00 -08001350
Imre Deak69172f22015-11-19 20:55:00 +02001351 if (force) {
1352 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
Imre Deak671dedd2014-03-05 16:20:53 +02001353
Sonika Jindal237ed862015-09-15 09:44:20 +05301354 edid = drm_get_edid(connector,
1355 intel_gmbus_get_adapter(dev_priv,
1356 intel_hdmi->ddc_bus));
Imre Deak671dedd2014-03-05 16:20:53 +02001357
Imre Deak69172f22015-11-19 20:55:00 +02001358 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1359 }
Imre Deak671dedd2014-03-05 16:20:53 +02001360
Chris Wilson953ece6972014-09-02 20:04:01 +01001361 to_intel_connector(connector)->detect_edid = edid;
1362 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1363 intel_hdmi->rgb_quant_range_selectable =
1364 drm_rgb_quant_range_selectable(edid);
1365
1366 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1367 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1368 intel_hdmi->has_audio =
1369 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1370
1371 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1372 intel_hdmi->has_hdmi_sink =
1373 drm_detect_hdmi_monitor(edid);
1374
1375 connected = true;
1376 }
1377
1378 return connected;
1379}
1380
Daniel Vetter8166fce2015-10-08 21:50:57 +02001381static enum drm_connector_status
1382intel_hdmi_detect(struct drm_connector *connector, bool force)
Chris Wilson953ece6972014-09-02 20:04:01 +01001383{
Daniel Vetter8166fce2015-10-08 21:50:57 +02001384 enum drm_connector_status status;
1385 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1386 struct drm_i915_private *dev_priv = to_i915(connector->dev);
Sonika Jindal237ed862015-09-15 09:44:20 +05301387 bool live_status = false;
Gary Wang61fb3982015-12-15 12:40:30 +08001388 unsigned int try;
Chris Wilson953ece6972014-09-02 20:04:01 +01001389
Daniel Vetter8166fce2015-10-08 21:50:57 +02001390 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1391 connector->base.id, connector->name);
1392
Imre Deak29bb94b2015-11-19 20:55:01 +02001393 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1394
Gary Wangf8d03ea2015-12-23 16:11:35 +08001395 for (try = 0; !live_status && try < 9; try++) {
Gary Wang61fb3982015-12-15 12:40:30 +08001396 if (try)
1397 msleep(10);
Sonika Jindal237ed862015-09-15 09:44:20 +05301398 live_status = intel_digital_port_connected(dev_priv,
1399 hdmi_to_dig_port(intel_hdmi));
Sonika Jindal237ed862015-09-15 09:44:20 +05301400 }
1401
1402 if (!live_status)
1403 DRM_DEBUG_KMS("Live status not up!");
1404
Daniel Vetter8166fce2015-10-08 21:50:57 +02001405 intel_hdmi_unset_edid(connector);
Chris Wilson953ece6972014-09-02 20:04:01 +01001406
Daniel Vetter8166fce2015-10-08 21:50:57 +02001407 if (intel_hdmi_set_edid(connector, live_status)) {
Chris Wilson953ece6972014-09-02 20:04:01 +01001408 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1409
1410 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1411 status = connector_status_connected;
Daniel Vetter8166fce2015-10-08 21:50:57 +02001412 } else
Chris Wilson953ece6972014-09-02 20:04:01 +01001413 status = connector_status_disconnected;
1414
Imre Deak29bb94b2015-11-19 20:55:01 +02001415 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1416
Chris Wilson953ece6972014-09-02 20:04:01 +01001417 return status;
1418}
1419
1420static void
1421intel_hdmi_force(struct drm_connector *connector)
1422{
1423 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1424
1425 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1426 connector->base.id, connector->name);
1427
1428 intel_hdmi_unset_edid(connector);
1429
1430 if (connector->status != connector_status_connected)
1431 return;
1432
Sonika Jindal237ed862015-09-15 09:44:20 +05301433 intel_hdmi_set_edid(connector, true);
Chris Wilson953ece6972014-09-02 20:04:01 +01001434 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1435}
1436
1437static int intel_hdmi_get_modes(struct drm_connector *connector)
1438{
1439 struct edid *edid;
1440
1441 edid = to_intel_connector(connector)->detect_edid;
1442 if (edid == NULL)
1443 return 0;
1444
1445 return intel_connector_update_modes(connector, edid);
Eric Anholt7d573822009-01-02 13:33:00 -08001446}
1447
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001448static bool
1449intel_hdmi_detect_audio(struct drm_connector *connector)
1450{
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001451 bool has_audio = false;
Chris Wilson953ece6972014-09-02 20:04:01 +01001452 struct edid *edid;
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001453
Chris Wilson953ece6972014-09-02 20:04:01 +01001454 edid = to_intel_connector(connector)->detect_edid;
1455 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1456 has_audio = drm_detect_monitor_audio(edid);
Imre Deak671dedd2014-03-05 16:20:53 +02001457
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001458 return has_audio;
1459}
1460
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001461static int
1462intel_hdmi_set_property(struct drm_connector *connector,
Paulo Zanonied517fb2012-05-14 17:12:50 -03001463 struct drm_property *property,
1464 uint64_t val)
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001465{
1466 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001467 struct intel_digital_port *intel_dig_port =
1468 hdmi_to_dig_port(intel_hdmi);
Chris Wilsone953fd72011-02-21 22:23:52 +00001469 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001470 int ret;
1471
Rob Clark662595d2012-10-11 20:36:04 -05001472 ret = drm_object_property_set_value(&connector->base, property, val);
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001473 if (ret)
1474 return ret;
1475
Chris Wilson3f43c482011-05-12 22:17:24 +01001476 if (property == dev_priv->force_audio_property) {
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001477 enum hdmi_force_audio i = val;
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001478 bool has_audio;
1479
1480 if (i == intel_hdmi->force_audio)
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001481 return 0;
1482
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001483 intel_hdmi->force_audio = i;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001484
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001485 if (i == HDMI_AUDIO_AUTO)
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001486 has_audio = intel_hdmi_detect_audio(connector);
1487 else
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001488 has_audio = (i == HDMI_AUDIO_ON);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001489
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001490 if (i == HDMI_AUDIO_OFF_DVI)
1491 intel_hdmi->has_hdmi_sink = 0;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001492
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001493 intel_hdmi->has_audio = has_audio;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001494 goto done;
1495 }
1496
Chris Wilsone953fd72011-02-21 22:23:52 +00001497 if (property == dev_priv->broadcast_rgb_property) {
Daniel Vetterae4edb82013-04-22 17:07:23 +02001498 bool old_auto = intel_hdmi->color_range_auto;
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03001499 bool old_range = intel_hdmi->limited_color_range;
Daniel Vetterae4edb82013-04-22 17:07:23 +02001500
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001501 switch (val) {
1502 case INTEL_BROADCAST_RGB_AUTO:
1503 intel_hdmi->color_range_auto = true;
1504 break;
1505 case INTEL_BROADCAST_RGB_FULL:
1506 intel_hdmi->color_range_auto = false;
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03001507 intel_hdmi->limited_color_range = false;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001508 break;
1509 case INTEL_BROADCAST_RGB_LIMITED:
1510 intel_hdmi->color_range_auto = false;
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03001511 intel_hdmi->limited_color_range = true;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001512 break;
1513 default:
1514 return -EINVAL;
1515 }
Daniel Vetterae4edb82013-04-22 17:07:23 +02001516
1517 if (old_auto == intel_hdmi->color_range_auto &&
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03001518 old_range == intel_hdmi->limited_color_range)
Daniel Vetterae4edb82013-04-22 17:07:23 +02001519 return 0;
1520
Chris Wilsone953fd72011-02-21 22:23:52 +00001521 goto done;
1522 }
1523
Vandana Kannan94a11dd2014-06-11 11:06:01 +05301524 if (property == connector->dev->mode_config.aspect_ratio_property) {
1525 switch (val) {
1526 case DRM_MODE_PICTURE_ASPECT_NONE:
1527 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1528 break;
1529 case DRM_MODE_PICTURE_ASPECT_4_3:
1530 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1531 break;
1532 case DRM_MODE_PICTURE_ASPECT_16_9:
1533 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1534 break;
1535 default:
1536 return -EINVAL;
1537 }
1538 goto done;
1539 }
1540
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001541 return -EINVAL;
1542
1543done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00001544 if (intel_dig_port->base.base.crtc)
1545 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001546
1547 return 0;
1548}
1549
Jesse Barnes13732ba2014-04-05 11:51:35 -07001550static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1551{
1552 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1553 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03001554 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
Jesse Barnes13732ba2014-04-05 11:51:35 -07001555
Daniel Vetter4cde8a22014-04-24 23:54:56 +02001556 intel_hdmi_prepare(encoder);
1557
Daniel Vetter6897b4b2014-04-24 23:54:47 +02001558 intel_hdmi->set_infoframes(&encoder->base,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001559 intel_crtc->config->has_hdmi_sink,
Daniel Vetter6897b4b2014-04-24 23:54:47 +02001560 adjusted_mode);
Jesse Barnes13732ba2014-04-05 11:51:35 -07001561}
1562
Chon Ming Lee9514ac62013-10-16 17:07:41 +08001563static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001564{
1565 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
Jesse Barnes13732ba2014-04-05 11:51:35 -07001566 struct intel_hdmi *intel_hdmi = &dport->hdmi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001567 struct drm_device *dev = encoder->base.dev;
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1569 struct intel_crtc *intel_crtc =
1570 to_intel_crtc(encoder->base.crtc);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03001571 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001572 enum dpio_channel port = vlv_dport_to_channel(dport);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001573 int pipe = intel_crtc->pipe;
1574 u32 val;
1575
Jesse Barnes89b667f2013-04-18 14:51:36 -07001576 /* Enable clock channels for this port */
Ville Syrjäläa5805162015-05-26 20:42:30 +03001577 mutex_lock(&dev_priv->sb_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001578 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001579 val = 0;
1580 if (pipe)
1581 val |= (1<<21);
1582 else
1583 val &= ~(1<<21);
1584 val |= 0x001000c4;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001585 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001586
1587 /* HDMI 1.0V-2dB */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001588 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1589 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1590 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1591 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1592 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1593 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1594 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1595 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001596
1597 /* Program lane clock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001598 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1599 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
Ville Syrjäläa5805162015-05-26 20:42:30 +03001600 mutex_unlock(&dev_priv->sb_lock);
Jani Nikulab76cf762013-07-30 12:20:31 +03001601
Daniel Vetter6897b4b2014-04-24 23:54:47 +02001602 intel_hdmi->set_infoframes(&encoder->base,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001603 intel_crtc->config->has_hdmi_sink,
Daniel Vetter6897b4b2014-04-24 23:54:47 +02001604 adjusted_mode);
Jesse Barnes13732ba2014-04-05 11:51:35 -07001605
Ville Syrjäläbf868c72015-05-05 17:06:23 +03001606 g4x_enable_hdmi(encoder);
Jani Nikulab76cf762013-07-30 12:20:31 +03001607
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001608 vlv_wait_port_ready(dev_priv, dport, 0x0);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001609}
1610
Chon Ming Lee9514ac62013-10-16 17:07:41 +08001611static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001612{
1613 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1614 struct drm_device *dev = encoder->base.dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001616 struct intel_crtc *intel_crtc =
1617 to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001618 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001619 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001620
Daniel Vetter4cde8a22014-04-24 23:54:56 +02001621 intel_hdmi_prepare(encoder);
1622
Jesse Barnes89b667f2013-04-18 14:51:36 -07001623 /* Program Tx lane resets to default */
Ville Syrjäläa5805162015-05-26 20:42:30 +03001624 mutex_lock(&dev_priv->sb_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001625 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001626 DPIO_PCS_TX_LANE2_RESET |
1627 DPIO_PCS_TX_LANE1_RESET);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001628 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001629 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1630 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1631 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1632 DPIO_PCS_CLK_SOFT_RESET);
1633
1634 /* Fix up inter-pair skew failure */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001635 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1636 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1637 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001638
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001639 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1640 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
Ville Syrjäläa5805162015-05-26 20:42:30 +03001641 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001642}
1643
Ville Syrjäläa8f327f2015-07-09 20:14:11 +03001644static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1645 bool reset)
1646{
1647 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1648 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1649 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1650 enum pipe pipe = crtc->pipe;
1651 uint32_t val;
1652
1653 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1654 if (reset)
1655 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1656 else
1657 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1658 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1659
1660 if (crtc->config->lane_count > 2) {
1661 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1662 if (reset)
1663 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1664 else
1665 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1666 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1667 }
1668
1669 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1670 val |= CHV_PCS_REQ_SOFTRESET_EN;
1671 if (reset)
1672 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1673 else
1674 val |= DPIO_PCS_CLK_SOFT_RESET;
1675 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1676
1677 if (crtc->config->lane_count > 2) {
1678 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1679 val |= CHV_PCS_REQ_SOFTRESET_EN;
1680 if (reset)
1681 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1682 else
1683 val |= DPIO_PCS_CLK_SOFT_RESET;
1684 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1685 }
1686}
1687
Ville Syrjälä9197c882014-04-09 13:29:05 +03001688static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1689{
1690 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1691 struct drm_device *dev = encoder->base.dev;
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 struct intel_crtc *intel_crtc =
1694 to_intel_crtc(encoder->base.crtc);
1695 enum dpio_channel ch = vlv_dport_to_channel(dport);
1696 enum pipe pipe = intel_crtc->pipe;
1697 u32 val;
1698
Ville Syrjälä625695f2014-06-28 02:04:02 +03001699 intel_hdmi_prepare(encoder);
1700
Ville Syrjäläb0b33842015-07-08 23:45:55 +03001701 /*
1702 * Must trick the second common lane into life.
1703 * Otherwise we can't even access the PLL.
1704 */
1705 if (ch == DPIO_CH0 && pipe == PIPE_B)
1706 dport->release_cl2_override =
1707 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1708
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001709 chv_phy_powergate_lanes(encoder, true, 0x0);
1710
Ville Syrjäläa5805162015-05-26 20:42:30 +03001711 mutex_lock(&dev_priv->sb_lock);
Ville Syrjälä9197c882014-04-09 13:29:05 +03001712
Ville Syrjäläa8f327f2015-07-09 20:14:11 +03001713 /* Assert data lane reset */
1714 chv_data_lane_soft_reset(encoder, true);
1715
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001716 /* program left/right clock distribution */
1717 if (pipe != PIPE_B) {
1718 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1719 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1720 if (ch == DPIO_CH0)
1721 val |= CHV_BUFLEFTENA1_FORCE;
1722 if (ch == DPIO_CH1)
1723 val |= CHV_BUFRIGHTENA1_FORCE;
1724 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1725 } else {
1726 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1727 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1728 if (ch == DPIO_CH0)
1729 val |= CHV_BUFLEFTENA2_FORCE;
1730 if (ch == DPIO_CH1)
1731 val |= CHV_BUFRIGHTENA2_FORCE;
1732 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1733 }
1734
Ville Syrjälä9197c882014-04-09 13:29:05 +03001735 /* program clock channel usage */
1736 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1737 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1738 if (pipe != PIPE_B)
1739 val &= ~CHV_PCS_USEDCLKCHANNEL;
1740 else
1741 val |= CHV_PCS_USEDCLKCHANNEL;
1742 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1743
1744 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1745 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1746 if (pipe != PIPE_B)
1747 val &= ~CHV_PCS_USEDCLKCHANNEL;
1748 else
1749 val |= CHV_PCS_USEDCLKCHANNEL;
1750 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1751
1752 /*
1753 * This a a bit weird since generally CL
1754 * matches the pipe, but here we need to
1755 * pick the CL based on the port.
1756 */
1757 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1758 if (pipe != PIPE_B)
1759 val &= ~CHV_CMN_USEDCLKCHANNEL;
1760 else
1761 val |= CHV_CMN_USEDCLKCHANNEL;
1762 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1763
Ville Syrjäläa5805162015-05-26 20:42:30 +03001764 mutex_unlock(&dev_priv->sb_lock);
Ville Syrjälä9197c882014-04-09 13:29:05 +03001765}
1766
Ville Syrjäläd6db9952015-07-08 23:45:49 +03001767static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1768{
1769 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1770 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1771 u32 val;
1772
1773 mutex_lock(&dev_priv->sb_lock);
1774
1775 /* disable left/right clock distribution */
1776 if (pipe != PIPE_B) {
1777 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1778 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1779 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1780 } else {
1781 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1782 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1783 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1784 }
1785
1786 mutex_unlock(&dev_priv->sb_lock);
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001787
Ville Syrjäläb0b33842015-07-08 23:45:55 +03001788 /*
1789 * Leave the power down bit cleared for at least one
1790 * lane so that chv_powergate_phy_ch() will power
1791 * on something when the channel is otherwise unused.
1792 * When the port is off and the override is removed
1793 * the lanes power down anyway, so otherwise it doesn't
1794 * really matter what the state of power down bits is
1795 * after this.
1796 */
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001797 chv_phy_powergate_lanes(encoder, false, 0x0);
Ville Syrjäläd6db9952015-07-08 23:45:49 +03001798}
1799
Chon Ming Lee9514ac62013-10-16 17:07:41 +08001800static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001801{
1802 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1803 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001804 struct intel_crtc *intel_crtc =
1805 to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001806 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001807 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001808
1809 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
Ville Syrjäläa5805162015-05-26 20:42:30 +03001810 mutex_lock(&dev_priv->sb_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001811 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1812 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
Ville Syrjäläa5805162015-05-26 20:42:30 +03001813 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001814}
1815
Ville Syrjälä580d3812014-04-09 13:29:00 +03001816static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1817{
Ville Syrjälä580d3812014-04-09 13:29:00 +03001818 struct drm_device *dev = encoder->base.dev;
1819 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä580d3812014-04-09 13:29:00 +03001820
Ville Syrjäläa5805162015-05-26 20:42:30 +03001821 mutex_lock(&dev_priv->sb_lock);
Ville Syrjälä580d3812014-04-09 13:29:00 +03001822
Ville Syrjäläa8f327f2015-07-09 20:14:11 +03001823 /* Assert data lane reset */
1824 chv_data_lane_soft_reset(encoder, true);
Ville Syrjälä580d3812014-04-09 13:29:00 +03001825
Ville Syrjäläa5805162015-05-26 20:42:30 +03001826 mutex_unlock(&dev_priv->sb_lock);
Ville Syrjälä580d3812014-04-09 13:29:00 +03001827}
1828
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001829static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1830{
1831 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
Clint Taylorb4eb1562014-11-21 11:13:02 -08001832 struct intel_hdmi *intel_hdmi = &dport->hdmi;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001833 struct drm_device *dev = encoder->base.dev;
1834 struct drm_i915_private *dev_priv = dev->dev_private;
1835 struct intel_crtc *intel_crtc =
1836 to_intel_crtc(encoder->base.crtc);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03001837 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001838 enum dpio_channel ch = vlv_dport_to_channel(dport);
1839 int pipe = intel_crtc->pipe;
Ville Syrjälä2e523e92015-04-10 18:21:27 +03001840 int data, i, stagger;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001841 u32 val;
1842
Ville Syrjäläa5805162015-05-26 20:42:30 +03001843 mutex_lock(&dev_priv->sb_lock);
Ville Syrjälä949c1d42014-04-09 13:28:58 +03001844
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001845 /* allow hardware to manage TX FIFO reset source */
1846 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1847 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1848 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1849
1850 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1851 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1852 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1853
Ville Syrjälä949c1d42014-04-09 13:28:58 +03001854 /* Program Tx latency optimal setting */
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001855 for (i = 0; i < 4; i++) {
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001856 /* Set the upar bit */
1857 data = (i == 1) ? 0x0 : 0x1;
1858 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1859 data << DPIO_UPAR_SHIFT);
1860 }
1861
1862 /* Data lane stagger programming */
Ville Syrjälä2e523e92015-04-10 18:21:27 +03001863 if (intel_crtc->config->port_clock > 270000)
1864 stagger = 0x18;
1865 else if (intel_crtc->config->port_clock > 135000)
1866 stagger = 0xd;
1867 else if (intel_crtc->config->port_clock > 67500)
1868 stagger = 0x7;
1869 else if (intel_crtc->config->port_clock > 33750)
1870 stagger = 0x4;
1871 else
1872 stagger = 0x2;
1873
1874 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1875 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1876 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1877
1878 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1879 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1880 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1881
1882 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1883 DPIO_LANESTAGGER_STRAP(stagger) |
1884 DPIO_LANESTAGGER_STRAP_OVRD |
1885 DPIO_TX1_STAGGER_MASK(0x1f) |
1886 DPIO_TX1_STAGGER_MULT(6) |
1887 DPIO_TX2_STAGGER_MULT(0));
1888
1889 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1890 DPIO_LANESTAGGER_STRAP(stagger) |
1891 DPIO_LANESTAGGER_STRAP_OVRD |
1892 DPIO_TX1_STAGGER_MASK(0x1f) |
1893 DPIO_TX1_STAGGER_MULT(7) |
1894 DPIO_TX2_STAGGER_MULT(5));
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001895
Ville Syrjäläa8f327f2015-07-09 20:14:11 +03001896 /* Deassert data lane reset */
1897 chv_data_lane_soft_reset(encoder, false);
1898
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001899 /* Clear calc init */
Ville Syrjälä1966e592014-04-09 13:29:04 +03001900 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1901 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001902 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1903 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
Ville Syrjälä1966e592014-04-09 13:29:04 +03001904 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1905
1906 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1907 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001908 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1909 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
Ville Syrjälä1966e592014-04-09 13:29:04 +03001910 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001911
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001912 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1913 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1914 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1915 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1916
1917 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1918 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1919 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1920 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1921
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001922 /* FIXME: Program the support xxx V-dB */
1923 /* Use 800mV-0dB */
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03001924 for (i = 0; i < 4; i++) {
1925 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1926 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1927 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1928 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1929 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001930
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03001931 for (i = 0; i < 4; i++) {
1932 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
Ville Syrjälä67fa24b2015-07-08 23:45:48 +03001933
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001934 val &= ~DPIO_SWING_MARGIN000_MASK;
1935 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
Ville Syrjälä67fa24b2015-07-08 23:45:48 +03001936
1937 /*
1938 * Supposedly this value shouldn't matter when unique transition
1939 * scale is disabled, but in fact it does matter. Let's just
1940 * always program the same value and hope it's OK.
1941 */
1942 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1943 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1944
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03001945 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1946 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001947
Ville Syrjälä67fa24b2015-07-08 23:45:48 +03001948 /*
1949 * The document said it needs to set bit 27 for ch0 and bit 26
1950 * for ch1. Might be a typo in the doc.
1951 * For now, for this unique transition scale selection, set bit
1952 * 27 for ch0 and ch1.
1953 */
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03001954 for (i = 0; i < 4; i++) {
1955 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1956 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1957 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1958 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001959
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001960 /* Start swing calculation */
Ville Syrjälä1966e592014-04-09 13:29:04 +03001961 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1962 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1963 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1964
1965 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1966 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1967 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001968
Ville Syrjäläa5805162015-05-26 20:42:30 +03001969 mutex_unlock(&dev_priv->sb_lock);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001970
Clint Taylorb4eb1562014-11-21 11:13:02 -08001971 intel_hdmi->set_infoframes(&encoder->base,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001972 intel_crtc->config->has_hdmi_sink,
Clint Taylorb4eb1562014-11-21 11:13:02 -08001973 adjusted_mode);
1974
Ville Syrjäläbf868c72015-05-05 17:06:23 +03001975 g4x_enable_hdmi(encoder);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001976
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001977 vlv_wait_port_ready(dev_priv, dport, 0x0);
Ville Syrjäläb0b33842015-07-08 23:45:55 +03001978
1979 /* Second common lane will stay alive on its own now */
1980 if (dport->release_cl2_override) {
1981 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
1982 dport->release_cl2_override = false;
1983 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03001984}
1985
Eric Anholt7d573822009-01-02 13:33:00 -08001986static void intel_hdmi_destroy(struct drm_connector *connector)
1987{
Chris Wilson10e972d2014-09-04 21:43:45 +01001988 kfree(to_intel_connector(connector)->detect_edid);
Eric Anholt7d573822009-01-02 13:33:00 -08001989 drm_connector_cleanup(connector);
Zhenyu Wang674e2d02010-03-29 15:57:42 +08001990 kfree(connector);
Eric Anholt7d573822009-01-02 13:33:00 -08001991}
1992
Eric Anholt7d573822009-01-02 13:33:00 -08001993static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
Maarten Lankhorst4d688a22015-08-05 12:37:06 +02001994 .dpms = drm_atomic_helper_connector_dpms,
Eric Anholt7d573822009-01-02 13:33:00 -08001995 .detect = intel_hdmi_detect,
Chris Wilson953ece6972014-09-02 20:04:01 +01001996 .force = intel_hdmi_force,
Eric Anholt7d573822009-01-02 13:33:00 -08001997 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001998 .set_property = intel_hdmi_set_property,
Matt Roper2545e4a2015-01-22 16:51:27 -08001999 .atomic_get_property = intel_connector_atomic_get_property,
Eric Anholt7d573822009-01-02 13:33:00 -08002000 .destroy = intel_hdmi_destroy,
Matt Roperc6f95f22015-01-22 16:50:32 -08002001 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
Ander Conselvan de Oliveira98969722015-03-20 16:18:06 +02002002 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
Eric Anholt7d573822009-01-02 13:33:00 -08002003};
2004
2005static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2006 .get_modes = intel_hdmi_get_modes,
2007 .mode_valid = intel_hdmi_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +01002008 .best_encoder = intel_best_encoder,
Eric Anholt7d573822009-01-02 13:33:00 -08002009};
2010
Eric Anholt7d573822009-01-02 13:33:00 -08002011static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
Chris Wilsonea5b2132010-08-04 13:50:23 +01002012 .destroy = intel_encoder_destroy,
Eric Anholt7d573822009-01-02 13:33:00 -08002013};
2014
Chris Wilson55b7d6e82010-09-19 09:29:33 +01002015static void
2016intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2017{
Chris Wilson3f43c482011-05-12 22:17:24 +01002018 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +00002019 intel_attach_broadcast_rgb_property(connector);
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02002020 intel_hdmi->color_range_auto = true;
Vandana Kannan94a11dd2014-06-11 11:06:01 +05302021 intel_attach_aspect_ratio_property(connector);
2022 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01002023}
2024
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002025void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2026 struct intel_connector *intel_connector)
Eric Anholt7d573822009-01-02 13:33:00 -08002027{
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002028 struct drm_connector *connector = &intel_connector->base;
2029 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2030 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2031 struct drm_device *dev = intel_encoder->base.dev;
Eric Anholt7d573822009-01-02 13:33:00 -08002032 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02002033 enum port port = intel_dig_port->port;
Xiong Zhang11c1b652015-08-17 16:04:04 +08002034 uint8_t alternate_ddc_pin;
Eric Anholt7d573822009-01-02 13:33:00 -08002035
Ville Syrjäläccb1a832015-12-08 19:59:38 +02002036 if (WARN(intel_dig_port->max_lanes < 4,
2037 "Not enough lanes (%d) for HDMI on port %c\n",
2038 intel_dig_port->max_lanes, port_name(port)))
2039 return;
2040
Eric Anholt7d573822009-01-02 13:33:00 -08002041 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
Adam Jackson8d911042009-09-23 15:08:29 -04002042 DRM_MODE_CONNECTOR_HDMIA);
Eric Anholt7d573822009-01-02 13:33:00 -08002043 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2044
Peter Rossc3febcc2012-01-28 14:49:26 +01002045 connector->interlace_allowed = 1;
Eric Anholt7d573822009-01-02 13:33:00 -08002046 connector->doublescan_allowed = 0;
Damien Lespiau573e74a2013-09-25 16:45:40 +01002047 connector->stereo_allowed = 1;
Eric Anholt7d573822009-01-02 13:33:00 -08002048
Daniel Vetter08d644a2012-07-12 20:19:59 +02002049 switch (port) {
2050 case PORT_B:
Jani Nikula4c272832015-04-01 10:58:05 +03002051 if (IS_BROXTON(dev_priv))
2052 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2053 else
2054 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
Sonika Jindalcf1d5882015-08-10 10:35:36 +05302055 /*
2056 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2057 * interrupts to check the external panel connection.
2058 */
Jani Nikulae87a0052015-10-20 15:22:02 +03002059 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
Sonika Jindalcf1d5882015-08-10 10:35:36 +05302060 intel_encoder->hpd_pin = HPD_PORT_A;
2061 else
2062 intel_encoder->hpd_pin = HPD_PORT_B;
Daniel Vetter08d644a2012-07-12 20:19:59 +02002063 break;
2064 case PORT_C:
Jani Nikula4c272832015-04-01 10:58:05 +03002065 if (IS_BROXTON(dev_priv))
2066 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2067 else
2068 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
Egbert Eich1d843f92013-02-25 12:06:49 -05002069 intel_encoder->hpd_pin = HPD_PORT_C;
Daniel Vetter08d644a2012-07-12 20:19:59 +02002070 break;
2071 case PORT_D:
Jani Nikula4c272832015-04-01 10:58:05 +03002072 if (WARN_ON(IS_BROXTON(dev_priv)))
2073 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2074 else if (IS_CHERRYVIEW(dev_priv))
Jani Nikula988c7012015-03-27 00:20:19 +02002075 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
Ville Syrjäläc0c35322014-04-09 13:28:52 +03002076 else
Jani Nikula988c7012015-03-27 00:20:19 +02002077 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
Egbert Eich1d843f92013-02-25 12:06:49 -05002078 intel_encoder->hpd_pin = HPD_PORT_D;
Daniel Vetter08d644a2012-07-12 20:19:59 +02002079 break;
Xiong Zhang11c1b652015-08-17 16:04:04 +08002080 case PORT_E:
2081 /* On SKL PORT E doesn't have seperate GMBUS pin
2082 * We rely on VBT to set a proper alternate GMBUS pin. */
2083 alternate_ddc_pin =
2084 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2085 switch (alternate_ddc_pin) {
2086 case DDC_PIN_B:
2087 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2088 break;
2089 case DDC_PIN_C:
2090 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2091 break;
2092 case DDC_PIN_D:
2093 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2094 break;
2095 default:
2096 MISSING_CASE(alternate_ddc_pin);
2097 }
2098 intel_encoder->hpd_pin = HPD_PORT_E;
2099 break;
Daniel Vetter08d644a2012-07-12 20:19:59 +02002100 case PORT_A:
Egbert Eich1d843f92013-02-25 12:06:49 -05002101 intel_encoder->hpd_pin = HPD_PORT_A;
Daniel Vetter08d644a2012-07-12 20:19:59 +02002102 /* Internal port only for eDP. */
2103 default:
Eugeni Dodonov6e4c1672012-05-09 15:37:13 -03002104 BUG();
Ma Lingf8aed702009-08-24 13:50:24 +08002105 }
Eric Anholt7d573822009-01-02 13:33:00 -08002106
Wayne Boyer666a4532015-12-09 12:29:35 -08002107 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Shobhit Kumar90b107c2012-03-28 13:39:32 -07002108 intel_hdmi->write_infoframe = vlv_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -03002109 intel_hdmi->set_infoframes = vlv_set_infoframes;
Jesse Barnese43823e2014-11-05 14:26:08 -08002110 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
Sonika Jindalb98856a2014-07-22 11:13:46 +05302111 } else if (IS_G4X(dev)) {
Jesse Barnes7637bfd2013-03-08 10:46:01 -08002112 intel_hdmi->write_infoframe = g4x_write_infoframe;
2113 intel_hdmi->set_infoframes = g4x_set_infoframes;
Jesse Barnese43823e2014-11-05 14:26:08 -08002114 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
Paulo Zanoni22b8bf12013-02-18 19:00:23 -03002115 } else if (HAS_DDI(dev)) {
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03002116 intel_hdmi->write_infoframe = hsw_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -03002117 intel_hdmi->set_infoframes = hsw_set_infoframes;
Jesse Barnese43823e2014-11-05 14:26:08 -08002118 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
Paulo Zanonifdf12502012-05-04 17:18:24 -03002119 } else if (HAS_PCH_IBX(dev)) {
2120 intel_hdmi->write_infoframe = ibx_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -03002121 intel_hdmi->set_infoframes = ibx_set_infoframes;
Jesse Barnese43823e2014-11-05 14:26:08 -08002122 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
Paulo Zanonifdf12502012-05-04 17:18:24 -03002123 } else {
2124 intel_hdmi->write_infoframe = cpt_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -03002125 intel_hdmi->set_infoframes = cpt_set_infoframes;
Jesse Barnese43823e2014-11-05 14:26:08 -08002126 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
Jesse Barnes64a8fc02011-09-22 11:16:00 +05302127 }
Jesse Barnes45187ac2011-08-03 09:22:55 -07002128
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002129 if (HAS_DDI(dev))
Paulo Zanonibcbc8892012-10-26 19:05:51 -02002130 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2131 else
2132 intel_connector->get_hw_state = intel_connector_get_hw_state;
Imre Deak4932e2c2014-02-11 17:12:48 +02002133 intel_connector->unregister = intel_connector_unregister;
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002134
2135 intel_hdmi_add_properties(intel_hdmi, connector);
2136
2137 intel_connector_attach_encoder(intel_connector, intel_encoder);
Thomas Wood34ea3d32014-05-29 16:57:41 +01002138 drm_connector_register(connector);
Shashank Sharmad8b4c432015-09-04 18:56:11 +05302139 intel_hdmi->attached_connector = intel_connector;
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002140
2141 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2142 * 0xd. Failure to do so will result in spurious interrupts being
2143 * generated on the port when a cable is not attached.
2144 */
2145 if (IS_G4X(dev) && !IS_GM45(dev)) {
2146 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2147 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2148 }
2149}
2150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002151void intel_hdmi_init(struct drm_device *dev,
2152 i915_reg_t hdmi_reg, enum port port)
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002153{
Takashi Iwai0bdf5a02015-11-30 18:19:39 +01002154 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002155 struct intel_digital_port *intel_dig_port;
2156 struct intel_encoder *intel_encoder;
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002157 struct intel_connector *intel_connector;
2158
Daniel Vetterb14c5672013-09-19 12:18:32 +02002159 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002160 if (!intel_dig_port)
2161 return;
2162
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03002163 intel_connector = intel_connector_alloc();
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002164 if (!intel_connector) {
2165 kfree(intel_dig_port);
2166 return;
2167 }
2168
2169 intel_encoder = &intel_dig_port->base;
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002170
2171 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2172 DRM_MODE_ENCODER_TMDS);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002173
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01002174 intel_encoder->compute_config = intel_hdmi_compute_config;
Ville Syrjäläa4790ce2015-05-05 17:17:35 +03002175 if (HAS_PCH_SPLIT(dev)) {
2176 intel_encoder->disable = pch_disable_hdmi;
2177 intel_encoder->post_disable = pch_post_disable_hdmi;
2178 } else {
2179 intel_encoder->disable = g4x_disable_hdmi;
2180 }
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002181 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002182 intel_encoder->get_config = intel_hdmi_get_config;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002183 if (IS_CHERRYVIEW(dev)) {
Ville Syrjälä9197c882014-04-09 13:29:05 +03002184 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002185 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2186 intel_encoder->enable = vlv_enable_hdmi;
Ville Syrjälä580d3812014-04-09 13:29:00 +03002187 intel_encoder->post_disable = chv_hdmi_post_disable;
Ville Syrjäläd6db9952015-07-08 23:45:49 +03002188 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002189 } else if (IS_VALLEYVIEW(dev)) {
Chon Ming Lee9514ac62013-10-16 17:07:41 +08002190 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2191 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
Jani Nikulab76cf762013-07-30 12:20:31 +03002192 intel_encoder->enable = vlv_enable_hdmi;
Chon Ming Lee9514ac62013-10-16 17:07:41 +08002193 intel_encoder->post_disable = vlv_hdmi_post_disable;
Jani Nikulab76cf762013-07-30 12:20:31 +03002194 } else {
Jesse Barnes13732ba2014-04-05 11:51:35 -07002195 intel_encoder->pre_enable = intel_hdmi_pre_enable;
Ville Syrjäläd1b15892015-05-05 17:06:19 +03002196 if (HAS_PCH_CPT(dev))
2197 intel_encoder->enable = cpt_enable_hdmi;
Ville Syrjäläbf868c72015-05-05 17:06:23 +03002198 else if (HAS_PCH_IBX(dev))
2199 intel_encoder->enable = ibx_enable_hdmi;
Ville Syrjäläd1b15892015-05-05 17:06:19 +03002200 else
Ville Syrjäläbf868c72015-05-05 17:06:23 +03002201 intel_encoder->enable = g4x_enable_hdmi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07002202 }
Daniel Vetter5ab432e2012-06-30 08:59:56 +02002203
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002204 intel_encoder->type = INTEL_OUTPUT_HDMI;
Ville Syrjälä882ec382014-04-28 14:07:43 +03002205 if (IS_CHERRYVIEW(dev)) {
2206 if (port == PORT_D)
2207 intel_encoder->crtc_mask = 1 << 2;
2208 else
2209 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2210 } else {
2211 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2212 }
Ville Syrjälä301ea742014-03-03 16:15:30 +02002213 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
Ville Syrjäläc6f14952014-03-03 16:15:31 +02002214 /*
2215 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2216 * to work on real hardware. And since g4x can send infoframes to
2217 * only one port anyway, nothing is lost by allowing it.
2218 */
2219 if (IS_G4X(dev))
2220 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
Eric Anholt7d573822009-01-02 13:33:00 -08002221
Paulo Zanoni174edf12012-10-26 19:05:50 -02002222 intel_dig_port->port = port;
Takashi Iwai0bdf5a02015-11-30 18:19:39 +01002223 dev_priv->dig_port_map[port] = intel_encoder;
Paulo Zanonib242b7f2013-02-18 19:00:26 -03002224 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002225 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
Ville Syrjäläccb1a832015-12-08 19:59:38 +02002226 intel_dig_port->max_lanes = 4;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01002227
Paulo Zanonib9cb2342012-10-26 19:05:47 -02002228 intel_hdmi_init_connector(intel_dig_port, intel_connector);
Eric Anholt7d573822009-01-02 13:33:00 -08002229}