Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007 Dave Airlied |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | /* |
| 25 | * Authors: Dave Airlied <airlied@linux.ie> |
| 26 | * Ben Skeggs <darktama@iinet.net.au> |
| 27 | * Jeremy Kolb <jkolb@brandeis.edu> |
| 28 | */ |
| 29 | |
Ben Skeggs | fdb751e | 2014-08-10 04:10:23 +1000 | [diff] [blame] | 30 | #include <linux/dma-mapping.h> |
Chris Metcalf | 3e2b756 | 2013-02-01 13:44:33 -0500 | [diff] [blame] | 31 | #include <linux/swiotlb.h> |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 32 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 33 | #include "nouveau_drm.h" |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 34 | #include "nouveau_dma.h" |
Ben Skeggs | d375e7d5 | 2012-04-30 13:30:00 +1000 | [diff] [blame] | 35 | #include "nouveau_fence.h" |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 36 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 37 | #include "nouveau_bo.h" |
| 38 | #include "nouveau_ttm.h" |
| 39 | #include "nouveau_gem.h" |
Maarten Maathuis | a510604 | 2009-12-26 21:46:36 +0100 | [diff] [blame] | 40 | |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 41 | /* |
| 42 | * NV10-NV40 tiling helpers |
| 43 | */ |
| 44 | |
| 45 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 46 | nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, |
| 47 | u32 addr, u32 size, u32 pitch, u32 flags) |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 48 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 49 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 50 | int i = reg - drm->tile.reg; |
Ben Skeggs | b1e4553 | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 51 | struct nvkm_fb *fb = nvxx_fb(&drm->device); |
| 52 | struct nvkm_fb_tile *tile = &fb->tile.region[i]; |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 53 | struct nvkm_engine *engine; |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 54 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 55 | nouveau_fence_unref(®->fence); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 56 | |
| 57 | if (tile->pitch) |
Ben Skeggs | b1e4553 | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 58 | fb->tile.fini(fb, i, tile); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 59 | |
| 60 | if (pitch) |
Ben Skeggs | b1e4553 | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 61 | fb->tile.init(fb, i, addr, size, pitch, flags, tile); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 62 | |
Ben Skeggs | b1e4553 | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 63 | fb->tile.prog(fb, i, tile); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 64 | |
Ben Skeggs | b1e4553 | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 65 | if ((engine = nvkm_engine(fb, NVDEV_ENGINE_GR))) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 66 | engine->tile_prog(engine, i); |
Ben Skeggs | b1e4553 | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 67 | if ((engine = nvkm_engine(fb, NVDEV_ENGINE_MPEG))) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 68 | engine->tile_prog(engine, i); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 69 | } |
| 70 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 71 | static struct nouveau_drm_tile * |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 72 | nv10_bo_get_tile_region(struct drm_device *dev, int i) |
| 73 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 74 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 75 | struct nouveau_drm_tile *tile = &drm->tile.reg[i]; |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 76 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 77 | spin_lock(&drm->tile.lock); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 78 | |
| 79 | if (!tile->used && |
| 80 | (!tile->fence || nouveau_fence_done(tile->fence))) |
| 81 | tile->used = true; |
| 82 | else |
| 83 | tile = NULL; |
| 84 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 85 | spin_unlock(&drm->tile.lock); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 86 | return tile; |
| 87 | } |
| 88 | |
| 89 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 90 | nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, |
Maarten Lankhorst | f2c24b8 | 2014-04-02 17:14:48 +0200 | [diff] [blame] | 91 | struct fence *fence) |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 92 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 93 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 94 | |
| 95 | if (tile) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 96 | spin_lock(&drm->tile.lock); |
Maarten Lankhorst | 809e944 | 2014-04-09 16:19:30 +0200 | [diff] [blame] | 97 | tile->fence = (struct nouveau_fence *)fence_get(fence); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 98 | tile->used = false; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 99 | spin_unlock(&drm->tile.lock); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 100 | } |
| 101 | } |
| 102 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 103 | static struct nouveau_drm_tile * |
| 104 | nv10_bo_set_tiling(struct drm_device *dev, u32 addr, |
| 105 | u32 size, u32 pitch, u32 flags) |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 106 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 107 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | b1e4553 | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 108 | struct nvkm_fb *fb = nvxx_fb(&drm->device); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 109 | struct nouveau_drm_tile *tile, *found = NULL; |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 110 | int i; |
| 111 | |
Ben Skeggs | b1e4553 | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 112 | for (i = 0; i < fb->tile.regions; i++) { |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 113 | tile = nv10_bo_get_tile_region(dev, i); |
| 114 | |
| 115 | if (pitch && !found) { |
| 116 | found = tile; |
| 117 | continue; |
| 118 | |
Ben Skeggs | b1e4553 | 2015-08-20 14:54:06 +1000 | [diff] [blame] | 119 | } else if (tile && fb->tile.region[i].pitch) { |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 120 | /* Kill an unused tile region. */ |
| 121 | nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); |
| 122 | } |
| 123 | |
| 124 | nv10_bo_put_tile_region(dev, tile, NULL); |
| 125 | } |
| 126 | |
| 127 | if (found) |
| 128 | nv10_bo_update_tile_region(dev, found, addr, size, |
| 129 | pitch, flags); |
| 130 | return found; |
| 131 | } |
| 132 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 133 | static void |
| 134 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) |
| 135 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 136 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
| 137 | struct drm_device *dev = drm->dev; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 138 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
| 139 | |
David Herrmann | 55fb74a | 2013-10-02 10:15:17 +0200 | [diff] [blame] | 140 | if (unlikely(nvbo->gem.filp)) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 141 | DRM_ERROR("bo %p still attached to GEM object\n", bo); |
Maarten Lankhorst | 4f38559 | 2013-07-07 10:37:35 +0200 | [diff] [blame] | 142 | WARN_ON(nvbo->pin_refcnt > 0); |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 143 | nv10_bo_put_tile_region(dev, nvbo->tile, NULL); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 144 | kfree(nvbo); |
| 145 | } |
| 146 | |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 147 | static void |
Ben Skeggs | db5c8e2 | 2011-02-10 13:41:01 +1000 | [diff] [blame] | 148 | nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, |
Ben Skeggs | f91bac5 | 2011-06-06 14:15:46 +1000 | [diff] [blame] | 149 | int *align, int *size) |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 150 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 151 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 152 | struct nvif_device *device = &drm->device; |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 153 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 154 | if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { |
Ben Skeggs | bfd83ac | 2010-11-12 15:12:51 +1000 | [diff] [blame] | 155 | if (nvbo->tile_mode) { |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 156 | if (device->info.chipset >= 0x40) { |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 157 | *align = 65536; |
Ben Skeggs | bfd83ac | 2010-11-12 15:12:51 +1000 | [diff] [blame] | 158 | *size = roundup(*size, 64 * nvbo->tile_mode); |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 159 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 160 | } else if (device->info.chipset >= 0x30) { |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 161 | *align = 32768; |
Ben Skeggs | bfd83ac | 2010-11-12 15:12:51 +1000 | [diff] [blame] | 162 | *size = roundup(*size, 64 * nvbo->tile_mode); |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 163 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 164 | } else if (device->info.chipset >= 0x20) { |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 165 | *align = 16384; |
Ben Skeggs | bfd83ac | 2010-11-12 15:12:51 +1000 | [diff] [blame] | 166 | *size = roundup(*size, 64 * nvbo->tile_mode); |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 167 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 168 | } else if (device->info.chipset >= 0x10) { |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 169 | *align = 16384; |
Ben Skeggs | bfd83ac | 2010-11-12 15:12:51 +1000 | [diff] [blame] | 170 | *size = roundup(*size, 32 * nvbo->tile_mode); |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 171 | } |
| 172 | } |
Ben Skeggs | bfd83ac | 2010-11-12 15:12:51 +1000 | [diff] [blame] | 173 | } else { |
Ben Skeggs | f91bac5 | 2011-06-06 14:15:46 +1000 | [diff] [blame] | 174 | *size = roundup(*size, (1 << nvbo->page_shift)); |
| 175 | *align = max((1 << nvbo->page_shift), *align); |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 176 | } |
| 177 | |
Maarten Maathuis | 1c7059e | 2009-12-25 18:51:17 +0100 | [diff] [blame] | 178 | *size = roundup(*size, PAGE_SIZE); |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 179 | } |
| 180 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 181 | int |
Ben Skeggs | 7375c95 | 2011-06-07 14:21:29 +1000 | [diff] [blame] | 182 | nouveau_bo_new(struct drm_device *dev, int size, int align, |
| 183 | uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, |
Maarten Lankhorst | bb6178b | 2014-01-09 11:03:15 +0100 | [diff] [blame] | 184 | struct sg_table *sg, struct reservation_object *robj, |
Ben Skeggs | 7375c95 | 2011-06-07 14:21:29 +1000 | [diff] [blame] | 185 | struct nouveau_bo **pnvbo) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 186 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 187 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 188 | struct nouveau_bo *nvbo; |
Jerome Glisse | 57de4ba | 2011-11-11 15:42:57 -0500 | [diff] [blame] | 189 | size_t acc_size; |
Ben Skeggs | f91bac5 | 2011-06-06 14:15:46 +1000 | [diff] [blame] | 190 | int ret; |
Dave Airlie | 22b33e8 | 2012-04-02 11:53:06 +0100 | [diff] [blame] | 191 | int type = ttm_bo_type_device; |
Maarten Lankhorst | 35095f7 | 2013-07-27 10:17:12 +0200 | [diff] [blame] | 192 | int lpg_shift = 12; |
| 193 | int max_size; |
| 194 | |
Ben Skeggs | 3ee6f5b | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 195 | if (drm->client.vm) |
Ben Skeggs | 5ce3bf3 | 2015-01-14 09:57:36 +1000 | [diff] [blame] | 196 | lpg_shift = drm->client.vm->mmu->lpg_shift; |
Maarten Lankhorst | 35095f7 | 2013-07-27 10:17:12 +0200 | [diff] [blame] | 197 | max_size = INT_MAX & ~((1 << lpg_shift) - 1); |
Maarten Lankhorst | 0108bc8 | 2013-07-07 10:40:19 +0200 | [diff] [blame] | 198 | |
| 199 | if (size <= 0 || size > max_size) { |
Ben Skeggs | fa2bade | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 200 | NV_WARN(drm, "skipped size %x\n", (u32)size); |
Maarten Lankhorst | 0108bc8 | 2013-07-07 10:40:19 +0200 | [diff] [blame] | 201 | return -EINVAL; |
| 202 | } |
Dave Airlie | 22b33e8 | 2012-04-02 11:53:06 +0100 | [diff] [blame] | 203 | |
| 204 | if (sg) |
| 205 | type = ttm_bo_type_sg; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 206 | |
| 207 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); |
| 208 | if (!nvbo) |
| 209 | return -ENOMEM; |
| 210 | INIT_LIST_HEAD(&nvbo->head); |
| 211 | INIT_LIST_HEAD(&nvbo->entry); |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 212 | INIT_LIST_HEAD(&nvbo->vma_list); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 213 | nvbo->tile_mode = tile_mode; |
| 214 | nvbo->tile_flags = tile_flags; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 215 | nvbo->bo.bdev = &drm->ttm.bdev; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 216 | |
Ben Skeggs | 989aa5b | 2015-01-12 12:33:37 +1000 | [diff] [blame] | 217 | if (!nv_device_is_cpu_coherent(nvxx_device(&drm->device))) |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 218 | nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED; |
| 219 | |
Ben Skeggs | f91bac5 | 2011-06-06 14:15:46 +1000 | [diff] [blame] | 220 | nvbo->page_shift = 12; |
Ben Skeggs | 3ee6f5b | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 221 | if (drm->client.vm) { |
Ben Skeggs | f91bac5 | 2011-06-06 14:15:46 +1000 | [diff] [blame] | 222 | if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024) |
Ben Skeggs | 5ce3bf3 | 2015-01-14 09:57:36 +1000 | [diff] [blame] | 223 | nvbo->page_shift = drm->client.vm->mmu->lpg_shift; |
Ben Skeggs | f91bac5 | 2011-06-06 14:15:46 +1000 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | nouveau_bo_fixup_align(nvbo, flags, &align, &size); |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 227 | nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; |
| 228 | nouveau_bo_placement_set(nvbo, flags, 0); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 229 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 230 | acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size, |
Jerome Glisse | 57de4ba | 2011-11-11 15:42:57 -0500 | [diff] [blame] | 231 | sizeof(struct nouveau_bo)); |
| 232 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 233 | ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size, |
Dave Airlie | 22b33e8 | 2012-04-02 11:53:06 +0100 | [diff] [blame] | 234 | type, &nvbo->placement, |
Marcin Slusarz | 0b91c4a | 2012-11-06 21:49:51 +0000 | [diff] [blame] | 235 | align >> PAGE_SHIFT, false, NULL, acc_size, sg, |
Maarten Lankhorst | bb6178b | 2014-01-09 11:03:15 +0100 | [diff] [blame] | 236 | robj, nouveau_bo_del_ttm); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 237 | if (ret) { |
| 238 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ |
| 239 | return ret; |
| 240 | } |
| 241 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 242 | *pnvbo = nvbo; |
| 243 | return 0; |
| 244 | } |
| 245 | |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 246 | static void |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 247 | set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 248 | { |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 249 | *n = 0; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 250 | |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 251 | if (type & TTM_PL_FLAG_VRAM) |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 252 | pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 253 | if (type & TTM_PL_FLAG_TT) |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 254 | pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 255 | if (type & TTM_PL_FLAG_SYSTEM) |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 256 | pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 257 | } |
Ben Skeggs | 37cb3e08 | 2009-12-16 16:22:42 +1000 | [diff] [blame] | 258 | |
Francisco Jerez | 699ddfd | 2010-10-10 06:07:32 +0200 | [diff] [blame] | 259 | static void |
| 260 | set_placement_range(struct nouveau_bo *nvbo, uint32_t type) |
| 261 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 262 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
Ben Skeggs | f392ec4 | 2014-08-10 04:10:28 +1000 | [diff] [blame] | 263 | u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT; |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 264 | unsigned i, fpfn, lpfn; |
Francisco Jerez | 699ddfd | 2010-10-10 06:07:32 +0200 | [diff] [blame] | 265 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 266 | if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && |
Francisco Jerez | 812f219 | 2011-02-03 01:49:33 +0100 | [diff] [blame] | 267 | nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) && |
Francisco Jerez | 4beb116 | 2011-11-06 21:21:28 +0100 | [diff] [blame] | 268 | nvbo->bo.mem.num_pages < vram_pages / 4) { |
Francisco Jerez | 699ddfd | 2010-10-10 06:07:32 +0200 | [diff] [blame] | 269 | /* |
| 270 | * Make sure that the color and depth buffers are handled |
| 271 | * by independent memory controller units. Up to a 9x |
| 272 | * speed up when alpha-blending and depth-test are enabled |
| 273 | * at the same time. |
| 274 | */ |
Francisco Jerez | 699ddfd | 2010-10-10 06:07:32 +0200 | [diff] [blame] | 275 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) { |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 276 | fpfn = vram_pages / 2; |
| 277 | lpfn = ~0; |
Francisco Jerez | 699ddfd | 2010-10-10 06:07:32 +0200 | [diff] [blame] | 278 | } else { |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 279 | fpfn = 0; |
| 280 | lpfn = vram_pages / 2; |
| 281 | } |
| 282 | for (i = 0; i < nvbo->placement.num_placement; ++i) { |
| 283 | nvbo->placements[i].fpfn = fpfn; |
| 284 | nvbo->placements[i].lpfn = lpfn; |
| 285 | } |
| 286 | for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { |
| 287 | nvbo->busy_placements[i].fpfn = fpfn; |
| 288 | nvbo->busy_placements[i].lpfn = lpfn; |
Francisco Jerez | 699ddfd | 2010-10-10 06:07:32 +0200 | [diff] [blame] | 289 | } |
| 290 | } |
| 291 | } |
| 292 | |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 293 | void |
| 294 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) |
| 295 | { |
| 296 | struct ttm_placement *pl = &nvbo->placement; |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 297 | uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : |
| 298 | TTM_PL_MASK_CACHING) | |
| 299 | (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 300 | |
| 301 | pl->placement = nvbo->placements; |
| 302 | set_placement_list(nvbo->placements, &pl->num_placement, |
| 303 | type, flags); |
| 304 | |
| 305 | pl->busy_placement = nvbo->busy_placements; |
| 306 | set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, |
| 307 | type | busy, flags); |
Francisco Jerez | 699ddfd | 2010-10-10 06:07:32 +0200 | [diff] [blame] | 308 | |
| 309 | set_placement_range(nvbo, type); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | int |
Ben Skeggs | ad76b3f | 2014-11-10 11:24:27 +1000 | [diff] [blame] | 313 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 314 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 315 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 316 | struct ttm_buffer_object *bo = &nvbo->bo; |
Ben Skeggs | ad76b3f | 2014-11-10 11:24:27 +1000 | [diff] [blame] | 317 | bool force = false, evict = false; |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 318 | int ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 319 | |
Thierry Reding | ee3939e | 2014-07-21 13:15:51 +0200 | [diff] [blame] | 320 | ret = ttm_bo_reserve(bo, false, false, false, NULL); |
Daniel Vetter | 0ae6d7b | 2012-12-11 21:52:30 +0100 | [diff] [blame] | 321 | if (ret) |
Ben Skeggs | 50ab2e5 | 2014-11-10 11:12:17 +1000 | [diff] [blame] | 322 | return ret; |
Daniel Vetter | 0ae6d7b | 2012-12-11 21:52:30 +0100 | [diff] [blame] | 323 | |
Ben Skeggs | ad76b3f | 2014-11-10 11:24:27 +1000 | [diff] [blame] | 324 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA && |
| 325 | memtype == TTM_PL_FLAG_VRAM && contig) { |
| 326 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) { |
| 327 | if (bo->mem.mem_type == TTM_PL_VRAM) { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 328 | struct nvkm_mem *mem = bo->mem.mm_node; |
Ben Skeggs | ad76b3f | 2014-11-10 11:24:27 +1000 | [diff] [blame] | 329 | if (!list_is_singular(&mem->regions)) |
| 330 | evict = true; |
| 331 | } |
| 332 | nvbo->tile_flags &= ~NOUVEAU_GEM_TILE_NONCONTIG; |
| 333 | force = true; |
| 334 | } |
| 335 | } |
| 336 | |
| 337 | if (nvbo->pin_refcnt) { |
| 338 | if (!(memtype & (1 << bo->mem.mem_type)) || evict) { |
| 339 | NV_ERROR(drm, "bo %p pinned elsewhere: " |
| 340 | "0x%08x vs 0x%08x\n", bo, |
| 341 | 1 << bo->mem.mem_type, memtype); |
| 342 | ret = -EBUSY; |
| 343 | } |
| 344 | nvbo->pin_refcnt++; |
Daniel Vetter | 0ae6d7b | 2012-12-11 21:52:30 +0100 | [diff] [blame] | 345 | goto out; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 346 | } |
| 347 | |
Ben Skeggs | ad76b3f | 2014-11-10 11:24:27 +1000 | [diff] [blame] | 348 | if (evict) { |
| 349 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); |
| 350 | ret = nouveau_bo_validate(nvbo, false, false); |
| 351 | if (ret) |
| 352 | goto out; |
| 353 | } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 354 | |
Ben Skeggs | ad76b3f | 2014-11-10 11:24:27 +1000 | [diff] [blame] | 355 | nvbo->pin_refcnt++; |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 356 | nouveau_bo_placement_set(nvbo, memtype, 0); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 357 | |
Ben Skeggs | 50ab2e5 | 2014-11-10 11:12:17 +1000 | [diff] [blame] | 358 | /* drop pin_refcnt temporarily, so we don't trip the assertion |
| 359 | * in nouveau_bo_move() that makes sure we're not trying to |
| 360 | * move a pinned buffer |
| 361 | */ |
| 362 | nvbo->pin_refcnt--; |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 363 | ret = nouveau_bo_validate(nvbo, false, false); |
Ben Skeggs | 6aac6ce | 2014-11-06 14:34:31 +1000 | [diff] [blame] | 364 | if (ret) |
| 365 | goto out; |
Ben Skeggs | 50ab2e5 | 2014-11-10 11:12:17 +1000 | [diff] [blame] | 366 | nvbo->pin_refcnt++; |
Ben Skeggs | 6aac6ce | 2014-11-06 14:34:31 +1000 | [diff] [blame] | 367 | |
| 368 | switch (bo->mem.mem_type) { |
| 369 | case TTM_PL_VRAM: |
| 370 | drm->gem.vram_available -= bo->mem.size; |
| 371 | break; |
| 372 | case TTM_PL_TT: |
| 373 | drm->gem.gart_available -= bo->mem.size; |
| 374 | break; |
| 375 | default: |
| 376 | break; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 377 | } |
Alexandre Courbot | 5be5a15 | 2014-10-27 18:11:52 +0900 | [diff] [blame] | 378 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 379 | out: |
Ben Skeggs | ad76b3f | 2014-11-10 11:24:27 +1000 | [diff] [blame] | 380 | if (force && ret) |
| 381 | nvbo->tile_flags |= NOUVEAU_GEM_TILE_NONCONTIG; |
Daniel Vetter | 0ae6d7b | 2012-12-11 21:52:30 +0100 | [diff] [blame] | 382 | ttm_bo_unreserve(bo); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 383 | return ret; |
| 384 | } |
| 385 | |
| 386 | int |
| 387 | nouveau_bo_unpin(struct nouveau_bo *nvbo) |
| 388 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 389 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 390 | struct ttm_buffer_object *bo = &nvbo->bo; |
Maarten Lankhorst | 4f38559 | 2013-07-07 10:37:35 +0200 | [diff] [blame] | 391 | int ret, ref; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 392 | |
Thierry Reding | ee3939e | 2014-07-21 13:15:51 +0200 | [diff] [blame] | 393 | ret = ttm_bo_reserve(bo, false, false, false, NULL); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 394 | if (ret) |
| 395 | return ret; |
| 396 | |
Maarten Lankhorst | 4f38559 | 2013-07-07 10:37:35 +0200 | [diff] [blame] | 397 | ref = --nvbo->pin_refcnt; |
| 398 | WARN_ON_ONCE(ref < 0); |
| 399 | if (ref) |
Daniel Vetter | 0ae6d7b | 2012-12-11 21:52:30 +0100 | [diff] [blame] | 400 | goto out; |
| 401 | |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 402 | nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 403 | |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 404 | ret = nouveau_bo_validate(nvbo, false, false); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 405 | if (ret == 0) { |
| 406 | switch (bo->mem.mem_type) { |
| 407 | case TTM_PL_VRAM: |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 408 | drm->gem.vram_available += bo->mem.size; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 409 | break; |
| 410 | case TTM_PL_TT: |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 411 | drm->gem.gart_available += bo->mem.size; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 412 | break; |
| 413 | default: |
| 414 | break; |
| 415 | } |
| 416 | } |
| 417 | |
Daniel Vetter | 0ae6d7b | 2012-12-11 21:52:30 +0100 | [diff] [blame] | 418 | out: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 419 | ttm_bo_unreserve(bo); |
| 420 | return ret; |
| 421 | } |
| 422 | |
| 423 | int |
| 424 | nouveau_bo_map(struct nouveau_bo *nvbo) |
| 425 | { |
| 426 | int ret; |
| 427 | |
Thierry Reding | ee3939e | 2014-07-21 13:15:51 +0200 | [diff] [blame] | 428 | ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 429 | if (ret) |
| 430 | return ret; |
| 431 | |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 432 | /* |
| 433 | * TTM buffers allocated using the DMA API already have a mapping, let's |
| 434 | * use it instead. |
| 435 | */ |
| 436 | if (!nvbo->force_coherent) |
| 437 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, |
| 438 | &nvbo->kmap); |
| 439 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 440 | ttm_bo_unreserve(&nvbo->bo); |
| 441 | return ret; |
| 442 | } |
| 443 | |
| 444 | void |
| 445 | nouveau_bo_unmap(struct nouveau_bo *nvbo) |
| 446 | { |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 447 | if (!nvbo) |
| 448 | return; |
| 449 | |
| 450 | /* |
| 451 | * TTM buffers allocated using the DMA API already had a coherent |
| 452 | * mapping which we used, no need to unmap. |
| 453 | */ |
| 454 | if (!nvbo->force_coherent) |
Ben Skeggs | 9d59e8a | 2010-08-27 13:04:41 +1000 | [diff] [blame] | 455 | ttm_bo_kunmap(&nvbo->kmap); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 456 | } |
| 457 | |
Alexandre Courbot | b22870b | 2014-10-27 18:49:19 +0900 | [diff] [blame] | 458 | void |
| 459 | nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) |
| 460 | { |
| 461 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 462 | struct nvkm_device *device = nvxx_device(&drm->device); |
Alexandre Courbot | b22870b | 2014-10-27 18:49:19 +0900 | [diff] [blame] | 463 | struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; |
| 464 | int i; |
| 465 | |
| 466 | if (!ttm_dma) |
| 467 | return; |
| 468 | |
| 469 | /* Don't waste time looping if the object is coherent */ |
| 470 | if (nvbo->force_coherent) |
| 471 | return; |
| 472 | |
| 473 | for (i = 0; i < ttm_dma->ttm.num_pages; i++) |
| 474 | dma_sync_single_for_device(nv_device_base(device), |
| 475 | ttm_dma->dma_address[i], PAGE_SIZE, DMA_TO_DEVICE); |
| 476 | } |
| 477 | |
| 478 | void |
| 479 | nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) |
| 480 | { |
| 481 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 482 | struct nvkm_device *device = nvxx_device(&drm->device); |
Alexandre Courbot | b22870b | 2014-10-27 18:49:19 +0900 | [diff] [blame] | 483 | struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; |
| 484 | int i; |
| 485 | |
| 486 | if (!ttm_dma) |
| 487 | return; |
| 488 | |
| 489 | /* Don't waste time looping if the object is coherent */ |
| 490 | if (nvbo->force_coherent) |
| 491 | return; |
| 492 | |
| 493 | for (i = 0; i < ttm_dma->ttm.num_pages; i++) |
| 494 | dma_sync_single_for_cpu(nv_device_base(device), |
| 495 | ttm_dma->dma_address[i], PAGE_SIZE, DMA_FROM_DEVICE); |
| 496 | } |
| 497 | |
Ben Skeggs | 7a45d76 | 2010-11-22 08:50:27 +1000 | [diff] [blame] | 498 | int |
| 499 | nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 500 | bool no_wait_gpu) |
Ben Skeggs | 7a45d76 | 2010-11-22 08:50:27 +1000 | [diff] [blame] | 501 | { |
| 502 | int ret; |
| 503 | |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 504 | ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, |
| 505 | interruptible, no_wait_gpu); |
Ben Skeggs | 7a45d76 | 2010-11-22 08:50:27 +1000 | [diff] [blame] | 506 | if (ret) |
| 507 | return ret; |
| 508 | |
Alexandre Courbot | b22870b | 2014-10-27 18:49:19 +0900 | [diff] [blame] | 509 | nouveau_bo_sync_for_device(nvbo); |
| 510 | |
Ben Skeggs | 7a45d76 | 2010-11-22 08:50:27 +1000 | [diff] [blame] | 511 | return 0; |
| 512 | } |
| 513 | |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 514 | static inline void * |
| 515 | _nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz) |
| 516 | { |
| 517 | struct ttm_dma_tt *dma_tt; |
| 518 | u8 *m = mem; |
| 519 | |
| 520 | index *= sz; |
| 521 | |
| 522 | if (m) { |
| 523 | /* kmap'd address, return the corresponding offset */ |
| 524 | m += index; |
| 525 | } else { |
| 526 | /* DMA-API mapping, lookup the right address */ |
| 527 | dma_tt = (struct ttm_dma_tt *)nvbo->bo.ttm; |
| 528 | m = dma_tt->cpu_address[index / PAGE_SIZE]; |
| 529 | m += index % PAGE_SIZE; |
| 530 | } |
| 531 | |
| 532 | return m; |
| 533 | } |
| 534 | #define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m)) |
| 535 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 536 | void |
| 537 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) |
| 538 | { |
| 539 | bool is_iomem; |
| 540 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 541 | |
| 542 | mem = nouveau_bo_mem_index(nvbo, index, mem); |
| 543 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 544 | if (is_iomem) |
| 545 | iowrite16_native(val, (void __force __iomem *)mem); |
| 546 | else |
| 547 | *mem = val; |
| 548 | } |
| 549 | |
| 550 | u32 |
| 551 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) |
| 552 | { |
| 553 | bool is_iomem; |
| 554 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 555 | |
| 556 | mem = nouveau_bo_mem_index(nvbo, index, mem); |
| 557 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 558 | if (is_iomem) |
| 559 | return ioread32_native((void __force __iomem *)mem); |
| 560 | else |
| 561 | return *mem; |
| 562 | } |
| 563 | |
| 564 | void |
| 565 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) |
| 566 | { |
| 567 | bool is_iomem; |
| 568 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 569 | |
| 570 | mem = nouveau_bo_mem_index(nvbo, index, mem); |
| 571 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 572 | if (is_iomem) |
| 573 | iowrite32_native(val, (void __force __iomem *)mem); |
| 574 | else |
| 575 | *mem = val; |
| 576 | } |
| 577 | |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 578 | static struct ttm_tt * |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 579 | nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, |
| 580 | uint32_t page_flags, struct page *dummy_read) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 581 | { |
Max Filippov | df1b4b9 | 2012-10-14 01:58:26 +0400 | [diff] [blame] | 582 | #if __OS_HAS_AGP |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 583 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
| 584 | struct drm_device *dev = drm->dev; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 585 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 586 | if (drm->agp.stat == ENABLED) { |
| 587 | return ttm_agp_tt_create(bdev, dev->agp->bridge, size, |
| 588 | page_flags, dummy_read); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 589 | } |
Max Filippov | df1b4b9 | 2012-10-14 01:58:26 +0400 | [diff] [blame] | 590 | #endif |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 591 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 592 | return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 593 | } |
| 594 | |
| 595 | static int |
| 596 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
| 597 | { |
| 598 | /* We'll do this from user space. */ |
| 599 | return 0; |
| 600 | } |
| 601 | |
| 602 | static int |
| 603 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, |
| 604 | struct ttm_mem_type_manager *man) |
| 605 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 606 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 607 | |
| 608 | switch (type) { |
| 609 | case TTM_PL_SYSTEM: |
| 610 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
| 611 | man->available_caching = TTM_PL_MASK_CACHING; |
| 612 | man->default_caching = TTM_PL_FLAG_CACHED; |
| 613 | break; |
| 614 | case TTM_PL_VRAM: |
Alexandre Courbot | e2a4e78 | 2014-06-27 19:28:50 +0900 | [diff] [blame] | 615 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
| 616 | TTM_MEMTYPE_FLAG_MAPPABLE; |
| 617 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
| 618 | TTM_PL_FLAG_WC; |
| 619 | man->default_caching = TTM_PL_FLAG_WC; |
| 620 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 621 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
Alexandre Courbot | e2a4e78 | 2014-06-27 19:28:50 +0900 | [diff] [blame] | 622 | /* Some BARs do not support being ioremapped WC */ |
Ben Skeggs | 989aa5b | 2015-01-12 12:33:37 +1000 | [diff] [blame] | 623 | if (nvxx_bar(&drm->device)->iomap_uncached) { |
Alexandre Courbot | e2a4e78 | 2014-06-27 19:28:50 +0900 | [diff] [blame] | 624 | man->available_caching = TTM_PL_FLAG_UNCACHED; |
| 625 | man->default_caching = TTM_PL_FLAG_UNCACHED; |
| 626 | } |
| 627 | |
Ben Skeggs | 573a2a3 | 2010-08-25 15:26:04 +1000 | [diff] [blame] | 628 | man->func = &nouveau_vram_manager; |
Ben Skeggs | f869ef8 | 2010-11-15 11:53:16 +1000 | [diff] [blame] | 629 | man->io_reserve_fastpath = false; |
| 630 | man->use_io_reserve_lru = true; |
| 631 | } else { |
Ben Skeggs | 573a2a3 | 2010-08-25 15:26:04 +1000 | [diff] [blame] | 632 | man->func = &ttm_bo_manager_func; |
Ben Skeggs | f869ef8 | 2010-11-15 11:53:16 +1000 | [diff] [blame] | 633 | } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 634 | break; |
| 635 | case TTM_PL_TT: |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 636 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) |
Ben Skeggs | 26c0c9e | 2011-02-10 12:59:51 +1000 | [diff] [blame] | 637 | man->func = &nouveau_gart_manager; |
| 638 | else |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 639 | if (drm->agp.stat != ENABLED) |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 640 | man->func = &nv04_gart_manager; |
| 641 | else |
Ben Skeggs | 26c0c9e | 2011-02-10 12:59:51 +1000 | [diff] [blame] | 642 | man->func = &ttm_bo_manager_func; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 643 | |
| 644 | if (drm->agp.stat == ENABLED) { |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 645 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
Francisco Jerez | a3d487e | 2010-11-20 22:11:22 +0100 | [diff] [blame] | 646 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
| 647 | TTM_PL_FLAG_WC; |
| 648 | man->default_caching = TTM_PL_FLAG_WC; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 649 | } else { |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 650 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | |
| 651 | TTM_MEMTYPE_FLAG_CMA; |
| 652 | man->available_caching = TTM_PL_MASK_CACHING; |
| 653 | man->default_caching = TTM_PL_FLAG_CACHED; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 654 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 655 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 656 | break; |
| 657 | default: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 658 | return -EINVAL; |
| 659 | } |
| 660 | return 0; |
| 661 | } |
| 662 | |
| 663 | static void |
| 664 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) |
| 665 | { |
| 666 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
| 667 | |
| 668 | switch (bo->mem.mem_type) { |
Francisco Jerez | 22fbd53 | 2009-12-11 18:40:17 +0100 | [diff] [blame] | 669 | case TTM_PL_VRAM: |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 670 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, |
| 671 | TTM_PL_FLAG_SYSTEM); |
Francisco Jerez | 22fbd53 | 2009-12-11 18:40:17 +0100 | [diff] [blame] | 672 | break; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 673 | default: |
Francisco Jerez | 78ad0f7 | 2010-03-18 13:07:47 +0100 | [diff] [blame] | 674 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 675 | break; |
| 676 | } |
Francisco Jerez | 22fbd53 | 2009-12-11 18:40:17 +0100 | [diff] [blame] | 677 | |
| 678 | *pl = nvbo->placement; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 679 | } |
| 680 | |
| 681 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 682 | static int |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 683 | nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) |
| 684 | { |
| 685 | int ret = RING_SPACE(chan, 2); |
| 686 | if (ret == 0) { |
| 687 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); |
Ben Skeggs | 00fc6f6 | 2013-07-09 14:20:15 +1000 | [diff] [blame] | 688 | OUT_RING (chan, handle & 0x0000ffff); |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 689 | FIRE_RING (chan); |
| 690 | } |
| 691 | return ret; |
| 692 | } |
| 693 | |
| 694 | static int |
Ben Skeggs | c6b7e89 | 2012-03-20 14:36:04 +1000 | [diff] [blame] | 695 | nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
| 696 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) |
| 697 | { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 698 | struct nvkm_mem *node = old_mem->mm_node; |
Ben Skeggs | c6b7e89 | 2012-03-20 14:36:04 +1000 | [diff] [blame] | 699 | int ret = RING_SPACE(chan, 10); |
| 700 | if (ret == 0) { |
Ben Skeggs | 6d59702 | 2012-04-01 21:09:13 +1000 | [diff] [blame] | 701 | BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); |
Ben Skeggs | c6b7e89 | 2012-03-20 14:36:04 +1000 | [diff] [blame] | 702 | OUT_RING (chan, upper_32_bits(node->vma[0].offset)); |
| 703 | OUT_RING (chan, lower_32_bits(node->vma[0].offset)); |
| 704 | OUT_RING (chan, upper_32_bits(node->vma[1].offset)); |
| 705 | OUT_RING (chan, lower_32_bits(node->vma[1].offset)); |
| 706 | OUT_RING (chan, PAGE_SIZE); |
| 707 | OUT_RING (chan, PAGE_SIZE); |
| 708 | OUT_RING (chan, PAGE_SIZE); |
| 709 | OUT_RING (chan, new_mem->num_pages); |
Ben Skeggs | 6d59702 | 2012-04-01 21:09:13 +1000 | [diff] [blame] | 710 | BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); |
Ben Skeggs | c6b7e89 | 2012-03-20 14:36:04 +1000 | [diff] [blame] | 711 | } |
| 712 | return ret; |
| 713 | } |
| 714 | |
| 715 | static int |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 716 | nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) |
| 717 | { |
| 718 | int ret = RING_SPACE(chan, 2); |
| 719 | if (ret == 0) { |
| 720 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); |
| 721 | OUT_RING (chan, handle); |
| 722 | } |
| 723 | return ret; |
| 724 | } |
| 725 | |
| 726 | static int |
Ben Skeggs | 1a46098 | 2012-05-04 15:17:28 +1000 | [diff] [blame] | 727 | nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
| 728 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) |
| 729 | { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 730 | struct nvkm_mem *node = old_mem->mm_node; |
Ben Skeggs | 1a46098 | 2012-05-04 15:17:28 +1000 | [diff] [blame] | 731 | u64 src_offset = node->vma[0].offset; |
| 732 | u64 dst_offset = node->vma[1].offset; |
| 733 | u32 page_count = new_mem->num_pages; |
| 734 | int ret; |
| 735 | |
| 736 | page_count = new_mem->num_pages; |
| 737 | while (page_count) { |
| 738 | int line_count = (page_count > 8191) ? 8191 : page_count; |
| 739 | |
| 740 | ret = RING_SPACE(chan, 11); |
| 741 | if (ret) |
| 742 | return ret; |
| 743 | |
| 744 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); |
| 745 | OUT_RING (chan, upper_32_bits(src_offset)); |
| 746 | OUT_RING (chan, lower_32_bits(src_offset)); |
| 747 | OUT_RING (chan, upper_32_bits(dst_offset)); |
| 748 | OUT_RING (chan, lower_32_bits(dst_offset)); |
| 749 | OUT_RING (chan, PAGE_SIZE); |
| 750 | OUT_RING (chan, PAGE_SIZE); |
| 751 | OUT_RING (chan, PAGE_SIZE); |
| 752 | OUT_RING (chan, line_count); |
| 753 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); |
| 754 | OUT_RING (chan, 0x00000110); |
| 755 | |
| 756 | page_count -= line_count; |
| 757 | src_offset += (PAGE_SIZE * line_count); |
| 758 | dst_offset += (PAGE_SIZE * line_count); |
| 759 | } |
| 760 | |
| 761 | return 0; |
| 762 | } |
| 763 | |
| 764 | static int |
Ben Skeggs | 183720b | 2010-12-09 15:17:10 +1000 | [diff] [blame] | 765 | nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
| 766 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) |
| 767 | { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 768 | struct nvkm_mem *node = old_mem->mm_node; |
Ben Skeggs | d2f96666 | 2011-06-06 20:54:42 +1000 | [diff] [blame] | 769 | u64 src_offset = node->vma[0].offset; |
| 770 | u64 dst_offset = node->vma[1].offset; |
Ben Skeggs | 183720b | 2010-12-09 15:17:10 +1000 | [diff] [blame] | 771 | u32 page_count = new_mem->num_pages; |
| 772 | int ret; |
| 773 | |
Ben Skeggs | 183720b | 2010-12-09 15:17:10 +1000 | [diff] [blame] | 774 | page_count = new_mem->num_pages; |
| 775 | while (page_count) { |
| 776 | int line_count = (page_count > 2047) ? 2047 : page_count; |
| 777 | |
| 778 | ret = RING_SPACE(chan, 12); |
| 779 | if (ret) |
| 780 | return ret; |
| 781 | |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 782 | BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); |
Ben Skeggs | 183720b | 2010-12-09 15:17:10 +1000 | [diff] [blame] | 783 | OUT_RING (chan, upper_32_bits(dst_offset)); |
| 784 | OUT_RING (chan, lower_32_bits(dst_offset)); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 785 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); |
Ben Skeggs | 183720b | 2010-12-09 15:17:10 +1000 | [diff] [blame] | 786 | OUT_RING (chan, upper_32_bits(src_offset)); |
| 787 | OUT_RING (chan, lower_32_bits(src_offset)); |
| 788 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ |
| 789 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ |
| 790 | OUT_RING (chan, PAGE_SIZE); /* line_length */ |
| 791 | OUT_RING (chan, line_count); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 792 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); |
Ben Skeggs | 183720b | 2010-12-09 15:17:10 +1000 | [diff] [blame] | 793 | OUT_RING (chan, 0x00100110); |
| 794 | |
| 795 | page_count -= line_count; |
| 796 | src_offset += (PAGE_SIZE * line_count); |
| 797 | dst_offset += (PAGE_SIZE * line_count); |
| 798 | } |
| 799 | |
| 800 | return 0; |
| 801 | } |
| 802 | |
| 803 | static int |
Ben Skeggs | fdf5324 | 2012-05-04 15:15:12 +1000 | [diff] [blame] | 804 | nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
| 805 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) |
| 806 | { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 807 | struct nvkm_mem *node = old_mem->mm_node; |
Ben Skeggs | fdf5324 | 2012-05-04 15:15:12 +1000 | [diff] [blame] | 808 | u64 src_offset = node->vma[0].offset; |
| 809 | u64 dst_offset = node->vma[1].offset; |
| 810 | u32 page_count = new_mem->num_pages; |
| 811 | int ret; |
| 812 | |
| 813 | page_count = new_mem->num_pages; |
| 814 | while (page_count) { |
| 815 | int line_count = (page_count > 8191) ? 8191 : page_count; |
| 816 | |
| 817 | ret = RING_SPACE(chan, 11); |
| 818 | if (ret) |
| 819 | return ret; |
| 820 | |
| 821 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); |
| 822 | OUT_RING (chan, upper_32_bits(src_offset)); |
| 823 | OUT_RING (chan, lower_32_bits(src_offset)); |
| 824 | OUT_RING (chan, upper_32_bits(dst_offset)); |
| 825 | OUT_RING (chan, lower_32_bits(dst_offset)); |
| 826 | OUT_RING (chan, PAGE_SIZE); |
| 827 | OUT_RING (chan, PAGE_SIZE); |
| 828 | OUT_RING (chan, PAGE_SIZE); |
| 829 | OUT_RING (chan, line_count); |
| 830 | BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); |
| 831 | OUT_RING (chan, 0x00000110); |
| 832 | |
| 833 | page_count -= line_count; |
| 834 | src_offset += (PAGE_SIZE * line_count); |
| 835 | dst_offset += (PAGE_SIZE * line_count); |
| 836 | } |
| 837 | |
| 838 | return 0; |
| 839 | } |
| 840 | |
| 841 | static int |
Ben Skeggs | 5490e5d | 2012-05-04 14:34:16 +1000 | [diff] [blame] | 842 | nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
| 843 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) |
| 844 | { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 845 | struct nvkm_mem *node = old_mem->mm_node; |
Ben Skeggs | 5490e5d | 2012-05-04 14:34:16 +1000 | [diff] [blame] | 846 | int ret = RING_SPACE(chan, 7); |
| 847 | if (ret == 0) { |
| 848 | BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); |
| 849 | OUT_RING (chan, upper_32_bits(node->vma[0].offset)); |
| 850 | OUT_RING (chan, lower_32_bits(node->vma[0].offset)); |
| 851 | OUT_RING (chan, upper_32_bits(node->vma[1].offset)); |
| 852 | OUT_RING (chan, lower_32_bits(node->vma[1].offset)); |
| 853 | OUT_RING (chan, 0x00000000 /* COPY */); |
| 854 | OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); |
| 855 | } |
| 856 | return ret; |
| 857 | } |
| 858 | |
| 859 | static int |
Ben Skeggs | 4c193d2 | 2012-05-04 14:21:15 +1000 | [diff] [blame] | 860 | nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
| 861 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) |
| 862 | { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 863 | struct nvkm_mem *node = old_mem->mm_node; |
Ben Skeggs | 4c193d2 | 2012-05-04 14:21:15 +1000 | [diff] [blame] | 864 | int ret = RING_SPACE(chan, 7); |
| 865 | if (ret == 0) { |
| 866 | BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); |
| 867 | OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); |
| 868 | OUT_RING (chan, upper_32_bits(node->vma[0].offset)); |
| 869 | OUT_RING (chan, lower_32_bits(node->vma[0].offset)); |
| 870 | OUT_RING (chan, upper_32_bits(node->vma[1].offset)); |
| 871 | OUT_RING (chan, lower_32_bits(node->vma[1].offset)); |
| 872 | OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); |
| 873 | } |
| 874 | return ret; |
| 875 | } |
| 876 | |
| 877 | static int |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 878 | nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) |
| 879 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 880 | int ret = RING_SPACE(chan, 6); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 881 | if (ret == 0) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 882 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
| 883 | OUT_RING (chan, handle); |
| 884 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); |
Ben Skeggs | f45f55c | 2014-08-10 04:10:23 +1000 | [diff] [blame] | 885 | OUT_RING (chan, chan->drm->ntfy.handle); |
| 886 | OUT_RING (chan, chan->vram.handle); |
| 887 | OUT_RING (chan, chan->vram.handle); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 888 | } |
| 889 | |
| 890 | return ret; |
| 891 | } |
| 892 | |
| 893 | static int |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 894 | nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
| 895 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 896 | { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 897 | struct nvkm_mem *node = old_mem->mm_node; |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 898 | u64 length = (new_mem->num_pages << PAGE_SHIFT); |
Ben Skeggs | d2f96666 | 2011-06-06 20:54:42 +1000 | [diff] [blame] | 899 | u64 src_offset = node->vma[0].offset; |
| 900 | u64 dst_offset = node->vma[1].offset; |
Maarten Lankhorst | ce8f769 | 2013-11-12 13:34:08 +0100 | [diff] [blame] | 901 | int src_tiled = !!node->memtype; |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 902 | int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 903 | int ret; |
| 904 | |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 905 | while (length) { |
| 906 | u32 amount, stride, height; |
| 907 | |
Maarten Lankhorst | ce8f769 | 2013-11-12 13:34:08 +0100 | [diff] [blame] | 908 | ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); |
| 909 | if (ret) |
| 910 | return ret; |
| 911 | |
Ben Skeggs | 5220b3c | 2010-09-23 15:21:17 +1000 | [diff] [blame] | 912 | amount = min(length, (u64)(4 * 1024 * 1024)); |
| 913 | stride = 16 * 4; |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 914 | height = amount / stride; |
| 915 | |
Maarten Lankhorst | ce8f769 | 2013-11-12 13:34:08 +0100 | [diff] [blame] | 916 | if (src_tiled) { |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 917 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 918 | OUT_RING (chan, 0); |
Ben Skeggs | 5220b3c | 2010-09-23 15:21:17 +1000 | [diff] [blame] | 919 | OUT_RING (chan, 0); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 920 | OUT_RING (chan, stride); |
| 921 | OUT_RING (chan, height); |
| 922 | OUT_RING (chan, 1); |
| 923 | OUT_RING (chan, 0); |
| 924 | OUT_RING (chan, 0); |
| 925 | } else { |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 926 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 927 | OUT_RING (chan, 1); |
| 928 | } |
Maarten Lankhorst | ce8f769 | 2013-11-12 13:34:08 +0100 | [diff] [blame] | 929 | if (dst_tiled) { |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 930 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 931 | OUT_RING (chan, 0); |
Ben Skeggs | 5220b3c | 2010-09-23 15:21:17 +1000 | [diff] [blame] | 932 | OUT_RING (chan, 0); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 933 | OUT_RING (chan, stride); |
| 934 | OUT_RING (chan, height); |
| 935 | OUT_RING (chan, 1); |
| 936 | OUT_RING (chan, 0); |
| 937 | OUT_RING (chan, 0); |
| 938 | } else { |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 939 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 940 | OUT_RING (chan, 1); |
| 941 | } |
| 942 | |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 943 | BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 944 | OUT_RING (chan, upper_32_bits(src_offset)); |
| 945 | OUT_RING (chan, upper_32_bits(dst_offset)); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 946 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 947 | OUT_RING (chan, lower_32_bits(src_offset)); |
| 948 | OUT_RING (chan, lower_32_bits(dst_offset)); |
| 949 | OUT_RING (chan, stride); |
| 950 | OUT_RING (chan, stride); |
| 951 | OUT_RING (chan, stride); |
| 952 | OUT_RING (chan, height); |
| 953 | OUT_RING (chan, 0x00000101); |
| 954 | OUT_RING (chan, 0x00000000); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 955 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 956 | OUT_RING (chan, 0); |
| 957 | |
| 958 | length -= amount; |
| 959 | src_offset += amount; |
| 960 | dst_offset += amount; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 961 | } |
| 962 | |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 963 | return 0; |
| 964 | } |
| 965 | |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 966 | static int |
| 967 | nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) |
| 968 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 969 | int ret = RING_SPACE(chan, 4); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 970 | if (ret == 0) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 971 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
| 972 | OUT_RING (chan, handle); |
| 973 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); |
Ben Skeggs | f45f55c | 2014-08-10 04:10:23 +1000 | [diff] [blame] | 974 | OUT_RING (chan, chan->drm->ntfy.handle); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 975 | } |
| 976 | |
| 977 | return ret; |
| 978 | } |
| 979 | |
Ben Skeggs | a670478 | 2011-02-16 09:10:20 +1000 | [diff] [blame] | 980 | static inline uint32_t |
| 981 | nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, |
| 982 | struct nouveau_channel *chan, struct ttm_mem_reg *mem) |
| 983 | { |
| 984 | if (mem->mem_type == TTM_PL_TT) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 985 | return NvDmaTT; |
Ben Skeggs | f45f55c | 2014-08-10 04:10:23 +1000 | [diff] [blame] | 986 | return chan->vram.handle; |
Ben Skeggs | a670478 | 2011-02-16 09:10:20 +1000 | [diff] [blame] | 987 | } |
| 988 | |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 989 | static int |
| 990 | nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
| 991 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) |
| 992 | { |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 993 | u32 src_offset = old_mem->start << PAGE_SHIFT; |
| 994 | u32 dst_offset = new_mem->start << PAGE_SHIFT; |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 995 | u32 page_count = new_mem->num_pages; |
| 996 | int ret; |
| 997 | |
| 998 | ret = RING_SPACE(chan, 3); |
| 999 | if (ret) |
| 1000 | return ret; |
| 1001 | |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1002 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 1003 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); |
| 1004 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); |
| 1005 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1006 | page_count = new_mem->num_pages; |
| 1007 | while (page_count) { |
| 1008 | int line_count = (page_count > 2047) ? 2047 : page_count; |
| 1009 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1010 | ret = RING_SPACE(chan, 11); |
| 1011 | if (ret) |
| 1012 | return ret; |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 1013 | |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1014 | BEGIN_NV04(chan, NvSubCopy, |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1015 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 1016 | OUT_RING (chan, src_offset); |
| 1017 | OUT_RING (chan, dst_offset); |
| 1018 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ |
| 1019 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ |
| 1020 | OUT_RING (chan, PAGE_SIZE); /* line_length */ |
| 1021 | OUT_RING (chan, line_count); |
| 1022 | OUT_RING (chan, 0x00000101); |
| 1023 | OUT_RING (chan, 0x00000000); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1024 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 1025 | OUT_RING (chan, 0); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1026 | |
| 1027 | page_count -= line_count; |
| 1028 | src_offset += (PAGE_SIZE * line_count); |
| 1029 | dst_offset += (PAGE_SIZE * line_count); |
| 1030 | } |
| 1031 | |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 1032 | return 0; |
| 1033 | } |
| 1034 | |
| 1035 | static int |
Ben Skeggs | 3c57d85 | 2013-11-22 10:35:25 +1000 | [diff] [blame] | 1036 | nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, |
| 1037 | struct ttm_mem_reg *mem) |
Ben Skeggs | d2f96666 | 2011-06-06 20:54:42 +1000 | [diff] [blame] | 1038 | { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1039 | struct nvkm_mem *old_node = bo->mem.mm_node; |
| 1040 | struct nvkm_mem *new_node = mem->mm_node; |
Ben Skeggs | 3c57d85 | 2013-11-22 10:35:25 +1000 | [diff] [blame] | 1041 | u64 size = (u64)mem->num_pages << PAGE_SHIFT; |
Ben Skeggs | d2f96666 | 2011-06-06 20:54:42 +1000 | [diff] [blame] | 1042 | int ret; |
| 1043 | |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1044 | ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift, |
| 1045 | NV_MEM_ACCESS_RW, &old_node->vma[0]); |
Ben Skeggs | d2f96666 | 2011-06-06 20:54:42 +1000 | [diff] [blame] | 1046 | if (ret) |
| 1047 | return ret; |
| 1048 | |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1049 | ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift, |
| 1050 | NV_MEM_ACCESS_RW, &old_node->vma[1]); |
Ben Skeggs | 3c57d85 | 2013-11-22 10:35:25 +1000 | [diff] [blame] | 1051 | if (ret) { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1052 | nvkm_vm_put(&old_node->vma[0]); |
Ben Skeggs | 3c57d85 | 2013-11-22 10:35:25 +1000 | [diff] [blame] | 1053 | return ret; |
| 1054 | } |
| 1055 | |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1056 | nvkm_vm_map(&old_node->vma[0], old_node); |
| 1057 | nvkm_vm_map(&old_node->vma[1], new_node); |
Ben Skeggs | d2f96666 | 2011-06-06 20:54:42 +1000 | [diff] [blame] | 1058 | return 0; |
| 1059 | } |
| 1060 | |
| 1061 | static int |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 1062 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1063 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 1064 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1065 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
Dave Jones | 1934a2a | 2013-09-17 17:26:34 -0400 | [diff] [blame] | 1066 | struct nouveau_channel *chan = drm->ttm.chan; |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 1067 | struct nouveau_cli *cli = (void *)chan->user.client; |
Ben Skeggs | 35b8141 | 2013-11-22 10:39:57 +1000 | [diff] [blame] | 1068 | struct nouveau_fence *fence; |
Ben Skeggs | f1ab0cc | 2010-08-26 11:32:01 +1000 | [diff] [blame] | 1069 | int ret; |
| 1070 | |
Ben Skeggs | d2f96666 | 2011-06-06 20:54:42 +1000 | [diff] [blame] | 1071 | /* create temporary vmas for the transfer and attach them to the |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1072 | * old nvkm_mem node, these will get cleaned up after ttm has |
Ben Skeggs | d2f96666 | 2011-06-06 20:54:42 +1000 | [diff] [blame] | 1073 | * destroyed the ttm_mem_reg |
Ben Skeggs | 3425df4 | 2011-02-10 11:22:12 +1000 | [diff] [blame] | 1074 | */ |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1075 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
Ben Skeggs | 3c57d85 | 2013-11-22 10:35:25 +1000 | [diff] [blame] | 1076 | ret = nouveau_bo_move_prep(drm, bo, new_mem); |
Ben Skeggs | d2f96666 | 2011-06-06 20:54:42 +1000 | [diff] [blame] | 1077 | if (ret) |
Ben Skeggs | 3c57d85 | 2013-11-22 10:35:25 +1000 | [diff] [blame] | 1078 | return ret; |
Ben Skeggs | 3425df4 | 2011-02-10 11:22:12 +1000 | [diff] [blame] | 1079 | } |
| 1080 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1081 | mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); |
Maarten Lankhorst | e3be4c2 | 2014-09-16 11:15:07 +0200 | [diff] [blame] | 1082 | ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); |
Ben Skeggs | 6a6b73f | 2010-10-05 16:53:48 +1000 | [diff] [blame] | 1083 | if (ret == 0) { |
Ben Skeggs | 35b8141 | 2013-11-22 10:39:57 +1000 | [diff] [blame] | 1084 | ret = drm->ttm.move(chan, bo, &bo->mem, new_mem); |
| 1085 | if (ret == 0) { |
| 1086 | ret = nouveau_fence_new(chan, false, &fence); |
| 1087 | if (ret == 0) { |
Maarten Lankhorst | f2c24b8 | 2014-04-02 17:14:48 +0200 | [diff] [blame] | 1088 | ret = ttm_bo_move_accel_cleanup(bo, |
| 1089 | &fence->base, |
Ben Skeggs | 35b8141 | 2013-11-22 10:39:57 +1000 | [diff] [blame] | 1090 | evict, |
| 1091 | no_wait_gpu, |
| 1092 | new_mem); |
| 1093 | nouveau_fence_unref(&fence); |
| 1094 | } |
| 1095 | } |
Ben Skeggs | 6a6b73f | 2010-10-05 16:53:48 +1000 | [diff] [blame] | 1096 | } |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1097 | mutex_unlock(&cli->mutex); |
Ben Skeggs | 6a6b73f | 2010-10-05 16:53:48 +1000 | [diff] [blame] | 1098 | return ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1099 | } |
| 1100 | |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1101 | void |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 1102 | nouveau_bo_move_init(struct nouveau_drm *drm) |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1103 | { |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1104 | static const struct { |
| 1105 | const char *name; |
Ben Skeggs | 1a46098 | 2012-05-04 15:17:28 +1000 | [diff] [blame] | 1106 | int engine; |
Ben Skeggs | 315a8b2 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 1107 | s32 oclass; |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1108 | int (*exec)(struct nouveau_channel *, |
| 1109 | struct ttm_buffer_object *, |
| 1110 | struct ttm_mem_reg *, struct ttm_mem_reg *); |
| 1111 | int (*init)(struct nouveau_channel *, u32 handle); |
| 1112 | } _methods[] = { |
Ben Skeggs | 990b454 | 2015-04-14 11:50:35 +1000 | [diff] [blame] | 1113 | { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
| 1114 | { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, |
Ben Skeggs | 00fc6f6 | 2013-07-09 14:20:15 +1000 | [diff] [blame] | 1115 | { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 1116 | { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, |
Ben Skeggs | 1a46098 | 2012-05-04 15:17:28 +1000 | [diff] [blame] | 1117 | { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, |
| 1118 | { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, |
| 1119 | { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, |
| 1120 | { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, |
| 1121 | { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, |
| 1122 | { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, |
| 1123 | { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, |
Ben Skeggs | 5490e5d | 2012-05-04 14:34:16 +1000 | [diff] [blame] | 1124 | {}, |
Ben Skeggs | 1a46098 | 2012-05-04 15:17:28 +1000 | [diff] [blame] | 1125 | { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1126 | }, *mthd = _methods; |
| 1127 | const char *name = "CPU"; |
| 1128 | int ret; |
| 1129 | |
| 1130 | do { |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 1131 | struct nouveau_channel *chan; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1132 | |
Ben Skeggs | 00fc6f6 | 2013-07-09 14:20:15 +1000 | [diff] [blame] | 1133 | if (mthd->engine) |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 1134 | chan = drm->cechan; |
| 1135 | else |
| 1136 | chan = drm->channel; |
| 1137 | if (chan == NULL) |
| 1138 | continue; |
| 1139 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 1140 | ret = nvif_object_init(&chan->user, |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1141 | mthd->oclass | (mthd->engine << 16), |
| 1142 | mthd->oclass, NULL, 0, |
| 1143 | &drm->ttm.copy); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1144 | if (ret == 0) { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1145 | ret = mthd->init(chan, drm->ttm.copy.handle); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1146 | if (ret) { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1147 | nvif_object_fini(&drm->ttm.copy); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1148 | continue; |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1149 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1150 | |
| 1151 | drm->ttm.move = mthd->exec; |
Ben Skeggs | 1bb3f6a | 2013-07-08 10:40:35 +1000 | [diff] [blame] | 1152 | drm->ttm.chan = chan; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1153 | name = mthd->name; |
| 1154 | break; |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1155 | } |
| 1156 | } while ((++mthd)->exec); |
| 1157 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1158 | NV_INFO(drm, "MM: using %s for buffer copies\n", name); |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 1159 | } |
| 1160 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1161 | static int |
| 1162 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1163 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1164 | { |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 1165 | struct ttm_place placement_memtype = { |
| 1166 | .fpfn = 0, |
| 1167 | .lpfn = 0, |
| 1168 | .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING |
| 1169 | }; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1170 | struct ttm_placement placement; |
| 1171 | struct ttm_mem_reg tmp_mem; |
| 1172 | int ret; |
| 1173 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1174 | placement.num_placement = placement.num_busy_placement = 1; |
Francisco Jerez | 77e2b5e | 2009-12-16 19:05:00 +0100 | [diff] [blame] | 1175 | placement.placement = placement.busy_placement = &placement_memtype; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1176 | |
| 1177 | tmp_mem = *new_mem; |
| 1178 | tmp_mem.mm_node = NULL; |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1179 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1180 | if (ret) |
| 1181 | return ret; |
| 1182 | |
| 1183 | ret = ttm_tt_bind(bo->ttm, &tmp_mem); |
| 1184 | if (ret) |
| 1185 | goto out; |
| 1186 | |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1187 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1188 | if (ret) |
| 1189 | goto out; |
| 1190 | |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1191 | ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1192 | out: |
Ben Skeggs | 42311ff | 2010-08-04 12:07:08 +1000 | [diff] [blame] | 1193 | ttm_bo_mem_put(bo, &tmp_mem); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1194 | return ret; |
| 1195 | } |
| 1196 | |
| 1197 | static int |
| 1198 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1199 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1200 | { |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 1201 | struct ttm_place placement_memtype = { |
| 1202 | .fpfn = 0, |
| 1203 | .lpfn = 0, |
| 1204 | .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING |
| 1205 | }; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1206 | struct ttm_placement placement; |
| 1207 | struct ttm_mem_reg tmp_mem; |
| 1208 | int ret; |
| 1209 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1210 | placement.num_placement = placement.num_busy_placement = 1; |
Francisco Jerez | 77e2b5e | 2009-12-16 19:05:00 +0100 | [diff] [blame] | 1211 | placement.placement = placement.busy_placement = &placement_memtype; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1212 | |
| 1213 | tmp_mem = *new_mem; |
| 1214 | tmp_mem.mm_node = NULL; |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1215 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1216 | if (ret) |
| 1217 | return ret; |
| 1218 | |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1219 | ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1220 | if (ret) |
| 1221 | goto out; |
| 1222 | |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1223 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1224 | if (ret) |
| 1225 | goto out; |
| 1226 | |
| 1227 | out: |
Ben Skeggs | 42311ff | 2010-08-04 12:07:08 +1000 | [diff] [blame] | 1228 | ttm_bo_mem_put(bo, &tmp_mem); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1229 | return ret; |
| 1230 | } |
| 1231 | |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1232 | static void |
| 1233 | nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) |
| 1234 | { |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1235 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1236 | struct nvkm_vma *vma; |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1237 | |
Ben Skeggs | 9f1feed | 2012-01-25 15:34:22 +1000 | [diff] [blame] | 1238 | /* ttm can now (stupidly) pass the driver bos it didn't create... */ |
| 1239 | if (bo->destroy != nouveau_bo_del_ttm) |
| 1240 | return; |
| 1241 | |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1242 | list_for_each_entry(vma, &nvbo->vma_list, head) { |
Ben Skeggs | 2e2cfbe | 2013-11-15 11:56:49 +1000 | [diff] [blame] | 1243 | if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM && |
| 1244 | (new_mem->mem_type == TTM_PL_VRAM || |
Ben Skeggs | 5ce3bf3 | 2015-01-14 09:57:36 +1000 | [diff] [blame] | 1245 | nvbo->page_shift != vma->vm->mmu->lpg_shift)) { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1246 | nvkm_vm_map(vma, new_mem->mm_node); |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1247 | } else { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1248 | nvkm_vm_unmap(vma); |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1249 | } |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1250 | } |
| 1251 | } |
| 1252 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1253 | static int |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1254 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1255 | struct nouveau_drm_tile **new_tile) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1256 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1257 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
| 1258 | struct drm_device *dev = drm->dev; |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1259 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1260 | u64 offset = new_mem->start << PAGE_SHIFT; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1261 | |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1262 | *new_tile = NULL; |
| 1263 | if (new_mem->mem_type != TTM_PL_VRAM) |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1264 | return 0; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1265 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1266 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { |
Ben Skeggs | bc9e7b9 | 2012-07-19 17:54:21 +1000 | [diff] [blame] | 1267 | *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size, |
Francisco Jerez | a5cf68b | 2010-10-24 16:14:41 +0200 | [diff] [blame] | 1268 | nvbo->tile_mode, |
| 1269 | nvbo->tile_flags); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1270 | } |
| 1271 | |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1272 | return 0; |
| 1273 | } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1274 | |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1275 | static void |
| 1276 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1277 | struct nouveau_drm_tile *new_tile, |
| 1278 | struct nouveau_drm_tile **old_tile) |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1279 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1280 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
| 1281 | struct drm_device *dev = drm->dev; |
Maarten Lankhorst | f2c24b8 | 2014-04-02 17:14:48 +0200 | [diff] [blame] | 1282 | struct fence *fence = reservation_object_get_excl(bo->resv); |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1283 | |
Maarten Lankhorst | f2c24b8 | 2014-04-02 17:14:48 +0200 | [diff] [blame] | 1284 | nv10_bo_put_tile_region(dev, *old_tile, fence); |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1285 | *old_tile = new_tile; |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1286 | } |
| 1287 | |
| 1288 | static int |
| 1289 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1290 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1291 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1292 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1293 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
| 1294 | struct ttm_mem_reg *old_mem = &bo->mem; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1295 | struct nouveau_drm_tile *new_tile = NULL; |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1296 | int ret = 0; |
| 1297 | |
Alexandre Courbot | 5be5a15 | 2014-10-27 18:11:52 +0900 | [diff] [blame] | 1298 | if (nvbo->pin_refcnt) |
| 1299 | NV_WARN(drm, "Moving pinned object %p!\n", nvbo); |
| 1300 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1301 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1302 | ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); |
| 1303 | if (ret) |
| 1304 | return ret; |
| 1305 | } |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1306 | |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1307 | /* Fake bo copy. */ |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1308 | if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
| 1309 | BUG_ON(bo->mem.mm_node != NULL); |
| 1310 | bo->mem = *new_mem; |
| 1311 | new_mem->mm_node = NULL; |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1312 | goto out; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1313 | } |
| 1314 | |
Ben Skeggs | cef9e99 | 2013-11-22 10:52:54 +1000 | [diff] [blame] | 1315 | /* Hardware assisted copy. */ |
| 1316 | if (drm->ttm.move) { |
| 1317 | if (new_mem->mem_type == TTM_PL_SYSTEM) |
| 1318 | ret = nouveau_bo_move_flipd(bo, evict, intr, |
| 1319 | no_wait_gpu, new_mem); |
| 1320 | else if (old_mem->mem_type == TTM_PL_SYSTEM) |
| 1321 | ret = nouveau_bo_move_flips(bo, evict, intr, |
| 1322 | no_wait_gpu, new_mem); |
| 1323 | else |
| 1324 | ret = nouveau_bo_move_m2mf(bo, evict, intr, |
| 1325 | no_wait_gpu, new_mem); |
| 1326 | if (!ret) |
| 1327 | goto out; |
Ben Skeggs | b8a6a80 | 2010-08-27 11:55:43 +1000 | [diff] [blame] | 1328 | } |
| 1329 | |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1330 | /* Fallback to software copy. */ |
Ben Skeggs | cef9e99 | 2013-11-22 10:52:54 +1000 | [diff] [blame] | 1331 | ret = ttm_bo_wait(bo, true, intr, no_wait_gpu); |
Ben Skeggs | cef9e99 | 2013-11-22 10:52:54 +1000 | [diff] [blame] | 1332 | if (ret == 0) |
| 1333 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1334 | |
| 1335 | out: |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1336 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1337 | if (ret) |
| 1338 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); |
| 1339 | else |
| 1340 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); |
| 1341 | } |
Francisco Jerez | a0af9ad | 2009-12-11 16:51:09 +0100 | [diff] [blame] | 1342 | |
| 1343 | return ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1344 | } |
| 1345 | |
| 1346 | static int |
| 1347 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) |
| 1348 | { |
David Herrmann | acb4652 | 2013-08-25 18:28:59 +0200 | [diff] [blame] | 1349 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
| 1350 | |
David Herrmann | 55fb74a | 2013-10-02 10:15:17 +0200 | [diff] [blame] | 1351 | return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1352 | } |
| 1353 | |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 1354 | static int |
| 1355 | nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
| 1356 | { |
| 1357 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1358 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1359 | struct nvkm_mem *node = mem->mm_node; |
Ben Skeggs | f869ef8 | 2010-11-15 11:53:16 +1000 | [diff] [blame] | 1360 | int ret; |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 1361 | |
| 1362 | mem->bus.addr = NULL; |
| 1363 | mem->bus.offset = 0; |
| 1364 | mem->bus.size = mem->num_pages << PAGE_SHIFT; |
| 1365 | mem->bus.base = 0; |
| 1366 | mem->bus.is_iomem = false; |
| 1367 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) |
| 1368 | return -EINVAL; |
| 1369 | switch (mem->mem_type) { |
| 1370 | case TTM_PL_SYSTEM: |
| 1371 | /* System memory */ |
| 1372 | return 0; |
| 1373 | case TTM_PL_TT: |
| 1374 | #if __OS_HAS_AGP |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1375 | if (drm->agp.stat == ENABLED) { |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 1376 | mem->bus.offset = mem->start << PAGE_SHIFT; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1377 | mem->bus.base = drm->agp.base; |
Ben Skeggs | 5c13cac | 2014-08-10 12:39:09 +1000 | [diff] [blame] | 1378 | mem->bus.is_iomem = !drm->dev->agp->cant_use_aperture; |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 1379 | } |
| 1380 | #endif |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1381 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype) |
Maarten Lankhorst | a554090 | 2013-11-12 13:34:09 +0100 | [diff] [blame] | 1382 | /* untiled */ |
| 1383 | break; |
| 1384 | /* fallthrough, tiled memory */ |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 1385 | case TTM_PL_VRAM: |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 1386 | mem->bus.offset = mem->start << PAGE_SHIFT; |
Ben Skeggs | 989aa5b | 2015-01-12 12:33:37 +1000 | [diff] [blame] | 1387 | mem->bus.base = nv_device_resource_start(nvxx_device(&drm->device), 1); |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 1388 | mem->bus.is_iomem = true; |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1389 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1390 | struct nvkm_bar *bar = nvxx_bar(&drm->device); |
Ben Skeggs | d8e8399 | 2015-08-20 14:54:17 +1000 | [diff] [blame^] | 1391 | int page_shift = 12; |
| 1392 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI) |
| 1393 | page_shift = node->page_shift; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 1394 | |
Ben Skeggs | d8e8399 | 2015-08-20 14:54:17 +1000 | [diff] [blame^] | 1395 | ret = bar->umap(bar, node->size << 12, page_shift, |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 1396 | &node->bar_vma); |
| 1397 | if (ret) |
| 1398 | return ret; |
| 1399 | |
Ben Skeggs | d8e8399 | 2015-08-20 14:54:17 +1000 | [diff] [blame^] | 1400 | nvkm_vm_map(&node->bar_vma, node); |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 1401 | mem->bus.offset = node->bar_vma.offset; |
| 1402 | } |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 1403 | break; |
| 1404 | default: |
| 1405 | return -EINVAL; |
| 1406 | } |
| 1407 | return 0; |
| 1408 | } |
| 1409 | |
| 1410 | static void |
| 1411 | nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
| 1412 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1413 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1414 | struct nvkm_bar *bar = nvxx_bar(&drm->device); |
| 1415 | struct nvkm_mem *node = mem->mm_node; |
Ben Skeggs | f869ef8 | 2010-11-15 11:53:16 +1000 | [diff] [blame] | 1416 | |
Ben Skeggs | d5f4239 | 2011-02-10 12:22:52 +1000 | [diff] [blame] | 1417 | if (!node->bar_vma.node) |
Ben Skeggs | f869ef8 | 2010-11-15 11:53:16 +1000 | [diff] [blame] | 1418 | return; |
| 1419 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1420 | bar->unmap(bar, &node->bar_vma); |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 1421 | } |
| 1422 | |
| 1423 | static int |
| 1424 | nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) |
| 1425 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1426 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
Ben Skeggs | e1429b4 | 2010-09-10 11:12:25 +1000 | [diff] [blame] | 1427 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1428 | struct nvif_device *device = &drm->device; |
Ben Skeggs | 989aa5b | 2015-01-12 12:33:37 +1000 | [diff] [blame] | 1429 | u32 mappable = nv_device_resource_len(nvxx_device(device), 1) >> PAGE_SHIFT; |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 1430 | int i, ret; |
Ben Skeggs | e1429b4 | 2010-09-10 11:12:25 +1000 | [diff] [blame] | 1431 | |
| 1432 | /* as long as the bo isn't in vram, and isn't tiled, we've got |
| 1433 | * nothing to do here. |
| 1434 | */ |
| 1435 | if (bo->mem.mem_type != TTM_PL_VRAM) { |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1436 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || |
Francisco Jerez | f13b326 | 2010-10-10 06:01:08 +0200 | [diff] [blame] | 1437 | !nouveau_bo_tile_layout(nvbo)) |
Ben Skeggs | e1429b4 | 2010-09-10 11:12:25 +1000 | [diff] [blame] | 1438 | return 0; |
Maarten Lankhorst | a554090 | 2013-11-12 13:34:09 +0100 | [diff] [blame] | 1439 | |
| 1440 | if (bo->mem.mem_type == TTM_PL_SYSTEM) { |
| 1441 | nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); |
| 1442 | |
| 1443 | ret = nouveau_bo_validate(nvbo, false, false); |
| 1444 | if (ret) |
| 1445 | return ret; |
| 1446 | } |
| 1447 | return 0; |
Ben Skeggs | e1429b4 | 2010-09-10 11:12:25 +1000 | [diff] [blame] | 1448 | } |
| 1449 | |
| 1450 | /* make sure bo is in mappable vram */ |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 1451 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA || |
Maarten Lankhorst | a554090 | 2013-11-12 13:34:09 +0100 | [diff] [blame] | 1452 | bo->mem.start + bo->mem.num_pages < mappable) |
Ben Skeggs | e1429b4 | 2010-09-10 11:12:25 +1000 | [diff] [blame] | 1453 | return 0; |
| 1454 | |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 1455 | for (i = 0; i < nvbo->placement.num_placement; ++i) { |
| 1456 | nvbo->placements[i].fpfn = 0; |
| 1457 | nvbo->placements[i].lpfn = mappable; |
| 1458 | } |
Ben Skeggs | e1429b4 | 2010-09-10 11:12:25 +1000 | [diff] [blame] | 1459 | |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 1460 | for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { |
| 1461 | nvbo->busy_placements[i].fpfn = 0; |
| 1462 | nvbo->busy_placements[i].lpfn = mappable; |
| 1463 | } |
| 1464 | |
Dave Airlie | c284815 | 2012-05-18 15:31:12 +0100 | [diff] [blame] | 1465 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 1466 | return nouveau_bo_validate(nvbo, false, false); |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 1467 | } |
| 1468 | |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1469 | static int |
| 1470 | nouveau_ttm_tt_populate(struct ttm_tt *ttm) |
| 1471 | { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 1472 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1473 | struct nouveau_drm *drm; |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1474 | struct nvkm_device *device; |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1475 | struct drm_device *dev; |
Alexandre Courbot | fd1496a | 2014-07-31 18:09:42 +0900 | [diff] [blame] | 1476 | struct device *pdev; |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1477 | unsigned i; |
| 1478 | int r; |
Dave Airlie | 22b33e8 | 2012-04-02 11:53:06 +0100 | [diff] [blame] | 1479 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1480 | |
| 1481 | if (ttm->state != tt_unpopulated) |
| 1482 | return 0; |
| 1483 | |
Dave Airlie | 22b33e8 | 2012-04-02 11:53:06 +0100 | [diff] [blame] | 1484 | if (slave && ttm->sg) { |
| 1485 | /* make userspace faulting work */ |
| 1486 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, |
| 1487 | ttm_dma->dma_address, ttm->num_pages); |
| 1488 | ttm->state = tt_unbound; |
| 1489 | return 0; |
| 1490 | } |
| 1491 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1492 | drm = nouveau_bdev(ttm->bdev); |
Ben Skeggs | 989aa5b | 2015-01-12 12:33:37 +1000 | [diff] [blame] | 1493 | device = nvxx_device(&drm->device); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1494 | dev = drm->dev; |
Alexandre Courbot | fd1496a | 2014-07-31 18:09:42 +0900 | [diff] [blame] | 1495 | pdev = nv_device_base(device); |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1496 | |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 1497 | /* |
| 1498 | * Objects matching this condition have been marked as force_coherent, |
| 1499 | * so use the DMA API for them. |
| 1500 | */ |
| 1501 | if (!nv_device_is_cpu_coherent(device) && |
| 1502 | ttm->caching_state == tt_uncached) |
| 1503 | return ttm_dma_populate(ttm_dma, dev->dev); |
| 1504 | |
Jerome Glisse | dea7e0a | 2012-01-03 17:37:37 -0500 | [diff] [blame] | 1505 | #if __OS_HAS_AGP |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1506 | if (drm->agp.stat == ENABLED) { |
Jerome Glisse | dea7e0a | 2012-01-03 17:37:37 -0500 | [diff] [blame] | 1507 | return ttm_agp_tt_populate(ttm); |
| 1508 | } |
| 1509 | #endif |
| 1510 | |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1511 | #ifdef CONFIG_SWIOTLB |
| 1512 | if (swiotlb_nr_tbl()) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 1513 | return ttm_dma_populate((void *)ttm, dev->dev); |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1514 | } |
| 1515 | #endif |
| 1516 | |
| 1517 | r = ttm_pool_populate(ttm); |
| 1518 | if (r) { |
| 1519 | return r; |
| 1520 | } |
| 1521 | |
| 1522 | for (i = 0; i < ttm->num_pages; i++) { |
Alexandre Courbot | fd1496a | 2014-07-31 18:09:42 +0900 | [diff] [blame] | 1523 | dma_addr_t addr; |
| 1524 | |
| 1525 | addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE, |
| 1526 | DMA_BIDIRECTIONAL); |
| 1527 | |
| 1528 | if (dma_mapping_error(pdev, addr)) { |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1529 | while (--i) { |
Alexandre Courbot | fd1496a | 2014-07-31 18:09:42 +0900 | [diff] [blame] | 1530 | dma_unmap_page(pdev, ttm_dma->dma_address[i], |
| 1531 | PAGE_SIZE, DMA_BIDIRECTIONAL); |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 1532 | ttm_dma->dma_address[i] = 0; |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1533 | } |
| 1534 | ttm_pool_unpopulate(ttm); |
| 1535 | return -EFAULT; |
| 1536 | } |
Alexandre Courbot | fd1496a | 2014-07-31 18:09:42 +0900 | [diff] [blame] | 1537 | |
| 1538 | ttm_dma->dma_address[i] = addr; |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1539 | } |
| 1540 | return 0; |
| 1541 | } |
| 1542 | |
| 1543 | static void |
| 1544 | nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) |
| 1545 | { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 1546 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1547 | struct nouveau_drm *drm; |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1548 | struct nvkm_device *device; |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1549 | struct drm_device *dev; |
Alexandre Courbot | fd1496a | 2014-07-31 18:09:42 +0900 | [diff] [blame] | 1550 | struct device *pdev; |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1551 | unsigned i; |
Dave Airlie | 22b33e8 | 2012-04-02 11:53:06 +0100 | [diff] [blame] | 1552 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
| 1553 | |
| 1554 | if (slave) |
| 1555 | return; |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1556 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1557 | drm = nouveau_bdev(ttm->bdev); |
Ben Skeggs | 989aa5b | 2015-01-12 12:33:37 +1000 | [diff] [blame] | 1558 | device = nvxx_device(&drm->device); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1559 | dev = drm->dev; |
Alexandre Courbot | fd1496a | 2014-07-31 18:09:42 +0900 | [diff] [blame] | 1560 | pdev = nv_device_base(device); |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1561 | |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 1562 | /* |
| 1563 | * Objects matching this condition have been marked as force_coherent, |
| 1564 | * so use the DMA API for them. |
| 1565 | */ |
| 1566 | if (!nv_device_is_cpu_coherent(device) && |
Alexandre Courbot | dcccdc1 | 2014-12-11 03:09:10 +0900 | [diff] [blame] | 1567 | ttm->caching_state == tt_uncached) { |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 1568 | ttm_dma_unpopulate(ttm_dma, dev->dev); |
Alexandre Courbot | dcccdc1 | 2014-12-11 03:09:10 +0900 | [diff] [blame] | 1569 | return; |
| 1570 | } |
Alexandre Courbot | c3a0c77 | 2014-10-27 18:49:17 +0900 | [diff] [blame] | 1571 | |
Jerome Glisse | dea7e0a | 2012-01-03 17:37:37 -0500 | [diff] [blame] | 1572 | #if __OS_HAS_AGP |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1573 | if (drm->agp.stat == ENABLED) { |
Jerome Glisse | dea7e0a | 2012-01-03 17:37:37 -0500 | [diff] [blame] | 1574 | ttm_agp_tt_unpopulate(ttm); |
| 1575 | return; |
| 1576 | } |
| 1577 | #endif |
| 1578 | |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1579 | #ifdef CONFIG_SWIOTLB |
| 1580 | if (swiotlb_nr_tbl()) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 1581 | ttm_dma_unpopulate((void *)ttm, dev->dev); |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1582 | return; |
| 1583 | } |
| 1584 | #endif |
| 1585 | |
| 1586 | for (i = 0; i < ttm->num_pages; i++) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 1587 | if (ttm_dma->dma_address[i]) { |
Alexandre Courbot | fd1496a | 2014-07-31 18:09:42 +0900 | [diff] [blame] | 1588 | dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE, |
| 1589 | DMA_BIDIRECTIONAL); |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1590 | } |
| 1591 | } |
| 1592 | |
| 1593 | ttm_pool_unpopulate(ttm); |
| 1594 | } |
| 1595 | |
Maarten Lankhorst | dd7cfd6 | 2014-01-21 13:07:31 +0100 | [diff] [blame] | 1596 | void |
Maarten Lankhorst | 809e944 | 2014-04-09 16:19:30 +0200 | [diff] [blame] | 1597 | nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) |
Maarten Lankhorst | dd7cfd6 | 2014-01-21 13:07:31 +0100 | [diff] [blame] | 1598 | { |
Maarten Lankhorst | 29ba89b | 2014-01-09 11:03:11 +0100 | [diff] [blame] | 1599 | struct reservation_object *resv = nvbo->bo.resv; |
Maarten Lankhorst | dd7cfd6 | 2014-01-21 13:07:31 +0100 | [diff] [blame] | 1600 | |
Maarten Lankhorst | 809e944 | 2014-04-09 16:19:30 +0200 | [diff] [blame] | 1601 | if (exclusive) |
| 1602 | reservation_object_add_excl_fence(resv, &fence->base); |
| 1603 | else if (fence) |
| 1604 | reservation_object_add_shared_fence(resv, &fence->base); |
Maarten Lankhorst | dd7cfd6 | 2014-01-21 13:07:31 +0100 | [diff] [blame] | 1605 | } |
| 1606 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1607 | struct ttm_bo_driver nouveau_bo_driver = { |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 1608 | .ttm_tt_create = &nouveau_ttm_tt_create, |
Konrad Rzeszutek Wilk | 3230cfc | 2011-10-17 17:14:26 -0400 | [diff] [blame] | 1609 | .ttm_tt_populate = &nouveau_ttm_tt_populate, |
| 1610 | .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1611 | .invalidate_caches = nouveau_bo_invalidate_caches, |
| 1612 | .init_mem_type = nouveau_bo_init_mem_type, |
| 1613 | .evict_flags = nouveau_bo_evict_flags, |
Ben Skeggs | a4154bb | 2011-02-10 10:35:16 +1000 | [diff] [blame] | 1614 | .move_notify = nouveau_bo_move_ntfy, |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1615 | .move = nouveau_bo_move, |
| 1616 | .verify_access = nouveau_bo_verify_access, |
Jerome Glisse | f32f02f | 2010-04-09 14:39:25 +0200 | [diff] [blame] | 1617 | .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, |
| 1618 | .io_mem_reserve = &nouveau_ttm_io_mem_reserve, |
| 1619 | .io_mem_free = &nouveau_ttm_io_mem_free, |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1620 | }; |
| 1621 | |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1622 | struct nvkm_vma * |
| 1623 | nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nvkm_vm *vm) |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1624 | { |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1625 | struct nvkm_vma *vma; |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1626 | list_for_each_entry(vma, &nvbo->vma_list, head) { |
| 1627 | if (vma->vm == vm) |
| 1628 | return vma; |
| 1629 | } |
| 1630 | |
| 1631 | return NULL; |
| 1632 | } |
| 1633 | |
| 1634 | int |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1635 | nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm, |
| 1636 | struct nvkm_vma *vma) |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1637 | { |
| 1638 | const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT; |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1639 | int ret; |
| 1640 | |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1641 | ret = nvkm_vm_get(vm, size, nvbo->page_shift, |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1642 | NV_MEM_ACCESS_RW, vma); |
| 1643 | if (ret) |
| 1644 | return ret; |
| 1645 | |
Ben Skeggs | 2e2cfbe | 2013-11-15 11:56:49 +1000 | [diff] [blame] | 1646 | if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM && |
| 1647 | (nvbo->bo.mem.mem_type == TTM_PL_VRAM || |
Ben Skeggs | 5ce3bf3 | 2015-01-14 09:57:36 +1000 | [diff] [blame] | 1648 | nvbo->page_shift != vma->vm->mmu->lpg_shift)) |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1649 | nvkm_vm_map(vma, nvbo->bo.mem.mm_node); |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1650 | |
| 1651 | list_add_tail(&vma->head, &nvbo->vma_list); |
Ben Skeggs | 2fd3db6 | 2011-06-07 15:25:12 +1000 | [diff] [blame] | 1652 | vma->refcount = 1; |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1653 | return 0; |
| 1654 | } |
| 1655 | |
| 1656 | void |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1657 | nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nvkm_vma *vma) |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1658 | { |
| 1659 | if (vma->node) { |
Ben Skeggs | c4c7044 | 2013-05-07 09:48:30 +1000 | [diff] [blame] | 1660 | if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) |
Ben Skeggs | be83cd4 | 2015-01-14 15:36:34 +1000 | [diff] [blame] | 1661 | nvkm_vm_unmap(vma); |
| 1662 | nvkm_vm_put(vma); |
Ben Skeggs | fd2871a | 2011-06-06 14:07:04 +1000 | [diff] [blame] | 1663 | list_del(&vma->head); |
| 1664 | } |
| 1665 | } |