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gerrit-public.fairphone.software / kernel / msm-4.9 / e34dcd76b41d084e620b031cacc29d6793028eae / . / arch / arm64 / boot / dts / qcom / sdm670-sde-display.dtsi
blob: dc7f57711a1cb15d40ac83b0492af5fb2ba027df [file] [log] [blame]
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]1/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "dsi-panel-sim-video.dtsi"
14#include "dsi-panel-sim-cmd.dtsi"
15#include "dsi-panel-sim-dsc375-cmd.dtsi"
16#include "dsi-panel-sim-dualmipi-video.dtsi"
17#include "dsi-panel-sim-dualmipi-cmd.dtsi"
18#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
19#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
20#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
21#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
22#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]23#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
24#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
25#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
26#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
27#include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi"
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]28#include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi"
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]29#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
30
31&soc {
32 dsi_panel_pwr_supply: dsi_panel_pwr_supply {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 qcom,panel-supply-entry@0 {
37 reg = <0>;
38 qcom,supply-name = "vddio";
39 qcom,supply-min-voltage = <1800000>;
40 qcom,supply-max-voltage = <1800000>;
41 qcom,supply-enable-load = <62000>;
42 qcom,supply-disable-load = <80>;
43 qcom,supply-post-on-sleep = <20>;
44 };
45
46 qcom,panel-supply-entry@1 {
47 reg = <1>;
48 qcom,supply-name = "lab";
49 qcom,supply-min-voltage = <4600000>;
50 qcom,supply-max-voltage = <6000000>;
51 qcom,supply-enable-load = <100000>;
52 qcom,supply-disable-load = <100>;
53 };
54
55 qcom,panel-supply-entry@2 {
56 reg = <2>;
57 qcom,supply-name = "ibb";
58 qcom,supply-min-voltage = <4600000>;
59 qcom,supply-max-voltage = <6000000>;
60 qcom,supply-enable-load = <100000>;
61 qcom,supply-disable-load = <100>;
62 qcom,supply-post-on-sleep = <20>;
63 };
64 };
65
66 dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 qcom,panel-supply-entry@0 {
71 reg = <0>;
72 qcom,supply-name = "vddio";
73 qcom,supply-min-voltage = <1800000>;
74 qcom,supply-max-voltage = <1800000>;
75 qcom,supply-enable-load = <62000>;
76 qcom,supply-disable-load = <80>;
77 qcom,supply-post-on-sleep = <20>;
78 };
79 };
80
81 dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 qcom,panel-supply-entry@0 {
86 reg = <0>;
87 qcom,supply-name = "vddio";
88 qcom,supply-min-voltage = <1800000>;
89 qcom,supply-max-voltage = <1800000>;
90 qcom,supply-enable-load = <62000>;
91 qcom,supply-disable-load = <80>;
92 qcom,supply-post-on-sleep = <20>;
93 };
94
95 qcom,panel-supply-entry@1 {
96 reg = <1>;
97 qcom,supply-name = "vdd";
98 qcom,supply-min-voltage = <3000000>;
99 qcom,supply-max-voltage = <3000000>;
100 qcom,supply-enable-load = <857000>;
101 qcom,supply-disable-load = <0>;
102 qcom,supply-post-on-sleep = <0>;
103 };
104 };
105
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]106 dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 qcom,panel-supply-entry@0 {
111 reg = <0>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530[diff] [blame]112 qcom,supply-name = "vddio";
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]113 qcom,supply-min-voltage = <1800000>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530[diff] [blame]114 qcom,supply-max-voltage = <1800000>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]115 qcom,supply-enable-load = <32000>;
116 qcom,supply-disable-load = <80>;
117 };
118
119 qcom,panel-supply-entry@1 {
120 reg = <1>;
121 qcom,supply-name = "vdda-3p3";
122 qcom,supply-min-voltage = <3300000>;
123 qcom,supply-max-voltage = <3300000>;
124 qcom,supply-enable-load = <13200>;
125 qcom,supply-disable-load = <80>;
126 };
127
128 qcom,panel-supply-entry@2 {
129 reg = <2>;
130 qcom,supply-name = "lab";
131 qcom,supply-min-voltage = <4600000>;
132 qcom,supply-max-voltage = <6100000>;
133 qcom,supply-enable-load = <100000>;
134 qcom,supply-disable-load = <100>;
135 };
136
137 qcom,panel-supply-entry@3 {
138 reg = <3>;
139 qcom,supply-name = "ibb";
140 qcom,supply-min-voltage = <4000000>;
141 qcom,supply-max-voltage = <6300000>;
142 qcom,supply-enable-load = <100000>;
143 qcom,supply-disable-load = <100>;
144 };
145
146 qcom,panel-supply-entry@4 {
147 reg = <4>;
148 qcom,supply-name = "oledb";
149 qcom,supply-min-voltage = <5000000>;
150 qcom,supply-max-voltage = <8100000>;
151 qcom,supply-enable-load = <100000>;
152 qcom,supply-disable-load = <100>;
153 };
154 };
155
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]156 dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 {
157 compatible = "qcom,dsi-display";
158 label = "dsi_dual_nt35597_truly_video_display";
159 qcom,display-type = "primary";
160
161 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
162 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
163 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
164 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
165 clock-names = "src_byte_clk", "src_pixel_clk";
166
167 pinctrl-names = "panel_active", "panel_suspend";
168 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
169 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
170 qcom,platform-reset-gpio = <&tlmm 75 0>;
171 qcom,panel-mode-gpio = <&tlmm 76 0>;
172
173 qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;
174 vddio-supply = <&pm660_l11>;
175 lab-supply = <&lcdb_ldo_vreg>;
176 ibb-supply = <&lcdb_ncp_vreg>;
177 };
178
179 dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 {
180 compatible = "qcom,dsi-display";
181 label = "dsi_dual_nt35597_truly_cmd_display";
182 qcom,display-type = "primary";
183
184 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
185 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
186 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
187 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
188 clock-names = "src_byte_clk", "src_pixel_clk";
189
190 pinctrl-names = "panel_active", "panel_suspend";
191 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
192 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
193 qcom,platform-te-gpio = <&tlmm 10 0>;
194 qcom,platform-reset-gpio = <&tlmm 75 0>;
195 qcom,panel-mode-gpio = <&tlmm 76 0>;
196
197 qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
198 vddio-supply = <&pm660_l11>;
199 lab-supply = <&lcdb_ldo_vreg>;
200 ibb-supply = <&lcdb_ncp_vreg>;
201 };
202
203 dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 {
204 compatible = "qcom,dsi-display";
205 label = "dsi_nt35597_truly_dsc_cmd_display";
206 qcom,display-type = "primary";
207
208 qcom,dsi-ctrl = <&mdss_dsi1>;
209 qcom,dsi-phy = <&mdss_dsi_phy1>;
210 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
211 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
212 clock-names = "src_byte_clk", "src_pixel_clk";
213
214 pinctrl-names = "panel_active", "panel_suspend";
215 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
216 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
217 qcom,platform-te-gpio = <&tlmm 10 0>;
218 qcom,platform-reset-gpio = <&tlmm 75 0>;
219 qcom,panel-mode-gpio = <&tlmm 76 0>;
220
221 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
222 vddio-supply = <&pm660_l11>;
223 lab-supply = <&lcdb_ldo_vreg>;
224 ibb-supply = <&lcdb_ncp_vreg>;
225 };
226
227 dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 {
228 compatible = "qcom,dsi-display";
229 label = "dsi_nt35597_truly_dsc_video_display";
230 qcom,display-type = "primary";
231
232 qcom,dsi-ctrl = <&mdss_dsi1>;
233 qcom,dsi-phy = <&mdss_dsi_phy1>;
234 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
235 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
236 clock-names = "src_byte_clk", "src_pixel_clk";
237
238 pinctrl-names = "panel_active", "panel_suspend";
239 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
240 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
241 qcom,platform-te-gpio = <&tlmm 10 0>;
242 qcom,platform-reset-gpio = <&tlmm 75 0>;
243 qcom,panel-mode-gpio = <&tlmm 76 0>;
244
245 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
246 vddio-supply = <&pm660_l11>;
247 lab-supply = <&lcdb_ldo_vreg>;
248 ibb-supply = <&lcdb_ncp_vreg>;
249 };
250
251 dsi_sim_vid_display: qcom,dsi-display@4 {
252 compatible = "qcom,dsi-display";
253 label = "dsi_sim_vid_display";
254 qcom,display-type = "primary";
255
256 qcom,dsi-ctrl = <&mdss_dsi0>;
257 qcom,dsi-phy = <&mdss_dsi_phy0>;
258 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
259 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
260 clock-names = "src_byte_clk", "src_pixel_clk";
261
262 pinctrl-names = "panel_active", "panel_suspend";
263 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
264 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
265
266 qcom,dsi-panel = <&dsi_sim_vid>;
267 };
268
269 dsi_dual_sim_vid_display: qcom,dsi-display@5 {
270 compatible = "qcom,dsi-display";
271 label = "dsi_dual_sim_vid_display";
272 qcom,display-type = "primary";
273
274 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
275 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
276 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
277 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
278 clock-names = "src_byte_clk", "src_pixel_clk";
279
280 pinctrl-names = "panel_active", "panel_suspend";
281 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
282 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
283
284 qcom,dsi-panel = <&dsi_dual_sim_vid>;
285 };
286
287 dsi_sim_cmd_display: qcom,dsi-display@6 {
288 compatible = "qcom,dsi-display";
289 label = "dsi_sim_cmd_display";
290 qcom,display-type = "primary";
291
292 qcom,dsi-ctrl = <&mdss_dsi0>;
293 qcom,dsi-phy = <&mdss_dsi_phy0>;
294 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
295 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
296 clock-names = "src_byte_clk", "src_pixel_clk";
297
298 pinctrl-names = "panel_active", "panel_suspend";
299 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
300 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
301
302 qcom,dsi-panel = <&dsi_sim_cmd>;
303 };
304
305 dsi_dual_sim_cmd_display: qcom,dsi-display@7 {
306 compatible = "qcom,dsi-display";
307 label = "dsi_dual_sim_cmd_display";
308 qcom,display-type = "primary";
309
310 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
311 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
312 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
313 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
314 clock-names = "src_byte_clk", "src_pixel_clk";
315
316 pinctrl-names = "panel_active", "panel_suspend";
317 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
318 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
319
320 qcom,dsi-panel = <&dsi_dual_sim_cmd>;
321 };
322
323 dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 {
324 compatible = "qcom,dsi-display";
325 label = "dsi_sim_dsc_375_cmd_display";
326 qcom,display-type = "primary";
327
328 qcom,dsi-ctrl = <&mdss_dsi0>;
329 qcom,dsi-phy = <&mdss_dsi_phy0>;
330 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
331 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
332 clock-names = "src_byte_clk", "src_pixel_clk";
333
334 pinctrl-names = "panel_active", "panel_suspend";
335 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
336 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
337
338 qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>;
339 };
340
341 dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 {
342 compatible = "qcom,dsi-display";
343 label = "dsi_dual_sim_dsc_375_cmd_display";
344 qcom,display-type = "primary";
345
346 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
347 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
348 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
349 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
350 clock-names = "src_byte_clk", "src_pixel_clk";
351
352 pinctrl-names = "panel_active", "panel_suspend";
353 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
354 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
355
356 qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>;
357 };
358
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]359 dsi_dual_nt35597_video_display: qcom,dsi-display@10 {
360 compatible = "qcom,dsi-display";
361 label = "dsi_dual_nt35597_video_display";
362 qcom,display-type = "primary";
363
364 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
365 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
366 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
367 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
368 clock-names = "src_byte_clk", "src_pixel_clk";
369
370 pinctrl-names = "panel_active", "panel_suspend";
371 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
372 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
373 qcom,platform-reset-gpio = <&tlmm 75 0>;
374 qcom,panel-mode-gpio = <&tlmm 76 0>;
375
376 qcom,dsi-panel = <&dsi_dual_nt35597_video>;
377 vddio-supply = <&pm660_l11>;
378 lab-supply = <&lcdb_ldo_vreg>;
379 ibb-supply = <&lcdb_ncp_vreg>;
380 };
381
382 dsi_dual_nt35597_cmd_display: qcom,dsi-display@11 {
383 compatible = "qcom,dsi-display";
384 label = "dsi_dual_nt35597_cmd_display";
385 qcom,display-type = "primary";
386
387 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
388 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
389 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
390 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
391 clock-names = "src_byte_clk", "src_pixel_clk";
392
393 pinctrl-names = "panel_active", "panel_suspend";
394 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
395 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
396 qcom,platform-reset-gpio = <&tlmm 75 0>;
397 qcom,panel-mode-gpio = <&tlmm 76 0>;
398
399 qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
400 vddio-supply = <&pm660_l11>;
401 lab-supply = <&lcdb_ldo_vreg>;
402 ibb-supply = <&lcdb_ncp_vreg>;
403 };
404
405 dsi_rm67195_amoled_fhd_cmd_display: qcom,dsi-display@12 {
406 compatible = "qcom,dsi-display";
407 label = "dsi_rm67195_amoled_fhd_cmd_display";
408 qcom,display-type = "primary";
409
410 qcom,dsi-ctrl = <&mdss_dsi0>;
411 qcom,dsi-phy = <&mdss_dsi_phy0>;
412 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
413 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
414 clock-names = "src_byte_clk", "src_pixel_clk";
415
416 pinctrl-names = "panel_active", "panel_suspend";
417 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
418 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
419 qcom,platform-te-gpio = <&tlmm 10 0>;
420 qcom,platform-reset-gpio = <&tlmm 75 0>;
421
422 qcom,dsi-panel = <&dsi_rm67195_amoled_fhd_cmd>;
423 vddio-supply = <&pm660_l11>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530[diff] [blame]424 vdda-3p3-supply = <&pm660l_l6>;
425 lab-supply = <&lab_regulator>;
426 ibb-supply = <&ibb_regulator>;
427 oledb-supply = <&pm660a_oledb>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]428 };
429
430 dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 {
431 compatible = "qcom,dsi-display";
432 label = "dsi_nt35695b_truly_fhd_video_display";
433 qcom,display-type = "primary";
434
435 qcom,dsi-ctrl = <&mdss_dsi0>;
436 qcom,dsi-phy = <&mdss_dsi_phy0>;
437 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
438 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
439 clock-names = "src_byte_clk", "src_pixel_clk";
440
441 pinctrl-names = "panel_active", "panel_suspend";
442 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
443 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
444 qcom,platform-reset-gpio = <&tlmm 75 0>;
445
446 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>;
447 vddio-supply = <&pm660_l11>;
448 lab-supply = <&lcdb_ldo_vreg>;
449 ibb-supply = <&lcdb_ncp_vreg>;
450 };
451
452 dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 {
453 compatible = "qcom,dsi-display";
454 label = "dsi_nt35695b_truly_fhd_cmd_display";
455 qcom,display-type = "primary";
456
457 qcom,dsi-ctrl = <&mdss_dsi0>;
458 qcom,dsi-phy = <&mdss_dsi_phy0>;
459 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
460 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
461 clock-names = "src_byte_clk", "src_pixel_clk";
462
463 pinctrl-names = "panel_active", "panel_suspend";
464 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
465 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
466 qcom,platform-te-gpio = <&tlmm 10 0>;
467 qcom,platform-reset-gpio = <&tlmm 75 0>;
468
469 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>;
470 vddio-supply = <&pm660_l11>;
471 lab-supply = <&lcdb_ldo_vreg>;
472 ibb-supply = <&lcdb_ncp_vreg>;
473 };
474
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]475 dsi_dual_nt36850_truly_cmd_display: qcom,dsi-display@15 {
476 compatible = "qcom,dsi-display";
477 label = "dsi_dual_nt36850_truly_cmd_display";
478 qcom,display-type = "primary";
479
480 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
481 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
482 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
483 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
484 clock-names = "src_byte_clk", "src_pixel_clk";
485
486 pinctrl-names = "panel_active", "panel_suspend";
487 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
488 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
489 qcom,platform-te-gpio = <&tlmm 10 0>;
490 qcom,platform-reset-gpio = <&tlmm 75 0>;
491
492 qcom,dsi-panel = <&dsi_dual_nt36850_truly_cmd>;
493 vddio-supply = <&pm660_l11>;
494 lab-supply = <&lcdb_ldo_vreg>;
495 ibb-supply = <&lcdb_ncp_vreg>;
496 };
497
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]498 sde_wb: qcom,wb-display@0 {
499 compatible = "qcom,wb-display";
500 cell-index = <0>;
501 label = "wb_display";
502 };
503
504 ext_disp: qcom,msm-ext-disp {
505 compatible = "qcom,msm-ext-disp";
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]506
507 ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
508 compatible = "qcom,msm-ext-disp-audio-codec-rx";
509 };
510 };
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]511};
512
513&sde_dp {
Padmanabhan Komanduruf3838e42017-10-20 12:50:47 +0530[diff] [blame]514 qcom,dp-usbpd-detection = <&pm660_pdphy>;
515 qcom,ext-disp = <&ext_disp>;
516
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]517 pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
518 pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
519 pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
520 qcom,aux-en-gpio = <&tlmm 50 0>;
521 qcom,aux-sel-gpio = <&tlmm 40 0>;
522 qcom,usbplug-cc-gpio = <&tlmm 38 0>;
523};
524
525&mdss_mdp {
Padmanabhan Komandurud03f38f2017-10-10 15:34:41 +0530[diff] [blame]526 connectors = <&sde_rscc &sde_wb &sde_dp>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]527};
528
529&dsi_dual_nt35597_truly_video {
530 qcom,mdss-dsi-t-clk-post = <0x0D>;
531 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530[diff] [blame]532 qcom,mdss-dsi-min-refresh-rate = <53>;
533 qcom,mdss-dsi-max-refresh-rate = <60>;
534 qcom,mdss-dsi-pan-enable-dynamic-fps;
535 qcom,mdss-dsi-pan-fps-update =
536 "dfps_immediate_porch_mode_vfp";
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]537 qcom,esd-check-enabled;
538 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
539 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
540 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
541 qcom,mdss-dsi-panel-status-value = <0x9c>;
542 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
543 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]544 qcom,mdss-dsi-display-timings {
545 timing@0{
546 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
547 07 05 03 04 00];
548 qcom,display-topology = <2 0 2>,
549 <1 0 2>;
550 qcom,default-topology-index = <0>;
551 };
552 };
553};
554
555&dsi_dual_nt35597_truly_cmd {
556 qcom,mdss-dsi-t-clk-post = <0x0D>;
557 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]558 qcom,ulps-enabled;
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]559 qcom,esd-check-enabled;
560 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
561 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
562 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
563 qcom,mdss-dsi-panel-status-value = <0x9c>;
564 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
565 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]566 qcom,mdss-dsi-display-timings {
567 timing@0{
568 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
569 07 05 03 04 00];
570 qcom,display-topology = <2 0 2>,
571 <1 0 2>;
572 qcom,default-topology-index = <0>;
Sandeep Pandae34dcd72017-11-23 18:33:00 +0530[diff] [blame^]573 qcom,partial-update-enabled = "single_roi";
574 qcom,panel-roi-alignment = <720 128 720 128 1440 128>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]575 };
576 };
577};
578
579&dsi_nt35597_truly_dsc_cmd {
580 qcom,mdss-dsi-t-clk-post = <0x0b>;
581 qcom,mdss-dsi-t-clk-pre = <0x23>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]582 qcom,ulps-enabled;
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]583 qcom,esd-check-enabled;
584 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
585 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
586 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
587 qcom,mdss-dsi-panel-status-value = <0x9c>;
588 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
589 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]590 qcom,mdss-dsi-display-timings {
591 timing@0{
592 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
593 05 03 03 04 00];
594 qcom,display-topology = <1 1 1>,
595 <2 2 1>, /* dsc merge */
596 <2 1 1>; /* 3d mux */
597 qcom,default-topology-index = <1>;
598 };
599 };
600};
601
602&dsi_nt35597_truly_dsc_video {
603 qcom,mdss-dsi-t-clk-post = <0x0b>;
604 qcom,mdss-dsi-t-clk-pre = <0x23>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530[diff] [blame]605 qcom,mdss-dsi-min-refresh-rate = <53>;
606 qcom,mdss-dsi-max-refresh-rate = <60>;
607 qcom,mdss-dsi-pan-enable-dynamic-fps;
608 qcom,mdss-dsi-pan-fps-update =
609 "dfps_immediate_porch_mode_vfp";
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]610 qcom,esd-check-enabled;
611 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
612 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
613 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
614 qcom,mdss-dsi-panel-status-value = <0x9c>;
615 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
616 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]617 qcom,mdss-dsi-display-timings {
618 timing@0{
619 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
620 04 03 03 04 00];
621 qcom,display-topology = <1 1 1>,
622 <2 2 1>, /* dsc merge */
623 <2 1 1>; /* 3d mux */
624 qcom,default-topology-index = <1>;
625 };
626 };
627};
628
629&dsi_sim_vid {
630 qcom,mdss-dsi-t-clk-post = <0x0d>;
631 qcom,mdss-dsi-t-clk-pre = <0x2d>;
632 qcom,mdss-dsi-display-timings {
633 timing@0{
634 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
635 07 05 03 04 00];
636 qcom,display-topology = <1 0 1>,
637 <2 0 1>;
638 qcom,default-topology-index = <0>;
639 };
640 };
641};
642
643&dsi_dual_sim_vid {
644 qcom,mdss-dsi-t-clk-post = <0x0d>;
645 qcom,mdss-dsi-t-clk-pre = <0x2d>;
646 qcom,mdss-dsi-display-timings {
647 timing@0{
648 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
649 07 05 03 04 00];
650 qcom,display-topology = <2 0 2>,
651 <1 0 2>;
652 qcom,default-topology-index = <0>;
653 };
654 };
655};
656
657&dsi_sim_cmd {
658 qcom,mdss-dsi-t-clk-post = <0x0d>;
659 qcom,mdss-dsi-t-clk-pre = <0x2d>;
660 qcom,mdss-dsi-display-timings {
661 timing@0{
662 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
663 07 05 03 04 00];
664 qcom,display-topology = <1 0 1>,
665 <2 0 1>;
666 qcom,default-topology-index = <0>;
667 };
668 };
669};
670
671&dsi_dual_sim_cmd {
672 qcom,mdss-dsi-t-clk-post = <0x0d>;
673 qcom,mdss-dsi-t-clk-pre = <0x2d>;
674 qcom,mdss-dsi-display-timings {
675 timing@0{
676 qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
677 09 06 03 04 00];
678 qcom,display-topology = <2 0 2>;
679 qcom,default-topology-index = <0>;
680 };
681 timing@1{
682 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
683 07 05 03 04 00];
684 qcom,display-topology = <2 0 2>,
685 <1 0 2>;
686 qcom,default-topology-index = <0>;
687 };
688 timing@2{
689 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
690 06 04 03 04 00];
691 qcom,display-topology = <2 0 2>;
692 qcom,default-topology-index = <0>;
693 };
694 };
695};
696
697&dsi_sim_dsc_375_cmd {
698 qcom,mdss-dsi-t-clk-post = <0x0d>;
699 qcom,mdss-dsi-t-clk-pre = <0x2d>;
700 qcom,mdss-dsi-display-timings {
701 timing@0 { /* 1080p */
702 qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
703 07 04 03 04 00];
704 qcom,display-topology = <1 1 1>;
705 qcom,default-topology-index = <0>;
706 };
707 timing@1 { /* qhd */
708 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
709 05 03 03 04 00];
710 qcom,display-topology = <1 1 1>,
711 <2 2 1>, /* dsc merge */
712 <2 1 1>; /* 3d mux */
713 qcom,default-topology-index = <0>;
714 };
715 };
716};
717
718&dsi_dual_sim_dsc_375_cmd {
719 qcom,mdss-dsi-t-clk-post = <0x0d>;
720 qcom,mdss-dsi-t-clk-pre = <0x2d>;
721 qcom,mdss-dsi-display-timings {
722 timing@0 { /* qhd */
723 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
724 07 05 03 04 00];
725 qcom,display-topology = <2 2 2>;
726 qcom,default-topology-index = <0>;
727 };
728 timing@1 { /* 4k */
729 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
730 06 04 03 04 00];
731 qcom,display-topology = <2 2 2>;
732 qcom,default-topology-index = <0>;
733 };
734 };
735};
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]736
737&dsi_dual_nt35597_video {
738 qcom,mdss-dsi-t-clk-post = <0x0d>;
739 qcom,mdss-dsi-t-clk-pre = <0x2d>;
740 qcom,mdss-dsi-display-timings {
741 timing@0 {
742 qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
743 05 03 04 00];
744 qcom,display-topology = <2 0 2>,
745 <1 0 2>;
746 qcom,default-topology-index = <0>;
747 };
748 };
749};
750
751&dsi_dual_nt35597_cmd {
752 qcom,mdss-dsi-t-clk-post = <0x0d>;
753 qcom,mdss-dsi-t-clk-pre = <0x2d>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]754 qcom,ulps-enabled;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]755 qcom,mdss-dsi-display-timings {
756 timing@0 {
757 qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
758 05 03 04 00];
759 qcom,display-topology = <2 0 2>,
760 <1 0 2>;
761 qcom,default-topology-index = <0>;
Sandeep Pandae34dcd72017-11-23 18:33:00 +0530[diff] [blame^]762 qcom,partial-update-enabled = "single_roi";
763 qcom,panel-roi-alignment = <720 128 720 128 1440 128>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]764 };
765 };
766};
767
768&dsi_rm67195_amoled_fhd_cmd {
769 qcom,mdss-dsi-t-clk-post = <0x07>;
770 qcom,mdss-dsi-t-clk-pre = <0x1c>;
771 qcom,mdss-dsi-display-timings {
772 timing@0 {
773 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
774 05 07 05 03 04 00];
775 qcom,display-topology = <1 0 1>;
776 qcom,default-topology-index = <0>;
777 };
778 };
779};
780
781&dsi_nt35695b_truly_fhd_video {
782 qcom,mdss-dsi-t-clk-post = <0x07>;
783 qcom,mdss-dsi-t-clk-pre = <0x1c>;
784 qcom,mdss-dsi-display-timings {
785 timing@0 {
786 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
787 05 07 05 03 04 00];
788 qcom,display-topology = <1 0 1>;
789 qcom,default-topology-index = <0>;
790 };
791 };
792};
793
794&dsi_nt35695b_truly_fhd_cmd {
795 qcom,mdss-dsi-t-clk-post = <0x07>;
796 qcom,mdss-dsi-t-clk-pre = <0x1c>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]797 qcom,ulps-enabled;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]798 qcom,mdss-dsi-display-timings {
799 timing@0 {
800 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
801 05 07 05 03 04 00];
802 qcom,display-topology = <1 0 1>;
803 qcom,default-topology-index = <0>;
804 };
805 };
806};
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]807
808&dsi_dual_nt36850_truly_cmd {
809 qcom,mdss-dsi-t-clk-post = <0x0E>;
810 qcom,mdss-dsi-t-clk-pre = <0x30>;
811 qcom,mdss-dsi-display-timings {
812 timing@0{
813 qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 23 08
814 08 05 03 04 00];
815 qcom,display-topology = <2 0 2>,
816 <1 0 2>;
817 qcom,default-topology-index = <0>;
818 };
819 };
820};