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Catalin Marinas382266a2007-02-05 14:48:19 +01001/*
2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
Rob Herring8c369262011-08-03 18:12:05 +010019#include <linux/err.h>
Catalin Marinas382266a2007-02-05 14:48:19 +010020#include <linux/init.h>
Catalin Marinas07620972007-07-20 11:42:40 +010021#include <linux/spinlock.h>
Russell Kingfced80c2008-09-06 12:10:45 +010022#include <linux/io.h>
Rob Herring8c369262011-08-03 18:12:05 +010023#include <linux/of.h>
24#include <linux/of_address.h>
Catalin Marinas382266a2007-02-05 14:48:19 +010025
26#include <asm/cacheflush.h>
Catalin Marinas382266a2007-02-05 14:48:19 +010027#include <asm/hardware/cache-l2x0.h>
28
29#define CACHE_LINE_SIZE 32
30
31static void __iomem *l2x0_base;
Thomas Gleixnerbd31b852009-07-03 08:44:46 -050032static DEFINE_RAW_SPINLOCK(l2x0_lock);
Russell King3e175ca2011-09-18 11:27:30 +010033static u32 l2x0_way_mask; /* Bitmask of active ways */
34static u32 l2x0_size;
Will Deaconf154fe92012-04-20 17:21:08 +010035static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
Catalin Marinas382266a2007-02-05 14:48:19 +010036
Barry Song91c2ebb2011-09-30 14:43:12 +010037struct l2x0_regs l2x0_saved_regs;
38
39struct l2x0_of_data {
Russell King3e175ca2011-09-18 11:27:30 +010040 void (*setup)(const struct device_node *, u32 *, u32 *);
Barry Song91c2ebb2011-09-30 14:43:12 +010041 void (*save)(void);
42 void (*resume)(void);
43};
44
Catalin Marinas9a6655e2010-08-31 13:05:22 +010045static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
Catalin Marinas382266a2007-02-05 14:48:19 +010046{
Catalin Marinas9a6655e2010-08-31 13:05:22 +010047 /* wait for cache operation by line or way to complete */
Catalin Marinas6775a552010-07-28 22:01:25 +010048 while (readl_relaxed(reg) & mask)
Barry Song1caf3092011-09-09 10:30:34 +010049 cpu_relax();
Catalin Marinas382266a2007-02-05 14:48:19 +010050}
51
Catalin Marinas9a6655e2010-08-31 13:05:22 +010052#ifdef CONFIG_CACHE_PL310
53static inline void cache_wait(void __iomem *reg, unsigned long mask)
54{
55 /* cache operations by line are atomic on PL310 */
56}
57#else
58#define cache_wait cache_wait_way
59#endif
60
Catalin Marinas382266a2007-02-05 14:48:19 +010061static inline void cache_sync(void)
62{
Russell King3d107432009-11-19 11:41:09 +000063 void __iomem *base = l2x0_base;
Srinidhi Kasagar885028e2011-02-17 07:03:51 +010064
Will Deaconf154fe92012-04-20 17:21:08 +010065 writel_relaxed(0, base + sync_reg_offset);
Russell King3d107432009-11-19 11:41:09 +000066 cache_wait(base + L2X0_CACHE_SYNC, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +010067}
68
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010069static inline void l2x0_clean_line(unsigned long addr)
70{
71 void __iomem *base = l2x0_base;
72 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +010073 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010074}
75
76static inline void l2x0_inv_line(unsigned long addr)
77{
78 void __iomem *base = l2x0_base;
79 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +010080 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010081}
82
Santosh Shilimkar2839e062011-03-08 06:59:54 +010083#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
Will Deaconab4d5362012-04-20 17:22:11 +010084static inline void debug_writel(unsigned long val)
85{
86 if (outer_cache.set_debug)
87 outer_cache.set_debug(val);
88}
Santosh Shilimkar9e655822010-02-04 19:42:42 +010089
Will Deaconab4d5362012-04-20 17:22:11 +010090static void pl310_set_debug(unsigned long val)
Santosh Shilimkar2839e062011-03-08 06:59:54 +010091{
92 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
93}
94#else
95/* Optimised out for non-errata case */
96static inline void debug_writel(unsigned long val)
97{
Santosh Shilimkar9e655822010-02-04 19:42:42 +010098}
99
Will Deaconab4d5362012-04-20 17:22:11 +0100100#define pl310_set_debug NULL
Santosh Shilimkar2839e062011-03-08 06:59:54 +0100101#endif
102
103#ifdef CONFIG_PL310_ERRATA_588369
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100104static inline void l2x0_flush_line(unsigned long addr)
105{
106 void __iomem *base = l2x0_base;
107
108 /* Clean by PA followed by Invalidate by PA */
109 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100110 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100111 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100112 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100113}
114#else
115
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100116static inline void l2x0_flush_line(unsigned long addr)
117{
118 void __iomem *base = l2x0_base;
119 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100120 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100121}
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100122#endif
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100123
Catalin Marinas23107c52010-03-24 16:48:53 +0100124static void l2x0_cache_sync(void)
125{
126 unsigned long flags;
127
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500128 raw_spin_lock_irqsave(&l2x0_lock, flags);
Catalin Marinas23107c52010-03-24 16:48:53 +0100129 cache_sync();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500130 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas23107c52010-03-24 16:48:53 +0100131}
132
Will Deacon38a89142011-07-01 14:36:19 +0100133static void __l2x0_flush_all(void)
134{
135 debug_writel(0x03);
136 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
137 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
138 cache_sync();
139 debug_writel(0x00);
140}
141
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530142static void l2x0_flush_all(void)
143{
144 unsigned long flags;
145
146 /* clean all ways */
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500147 raw_spin_lock_irqsave(&l2x0_lock, flags);
Will Deacon38a89142011-07-01 14:36:19 +0100148 __l2x0_flush_all();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500149 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530150}
151
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530152static void l2x0_clean_all(void)
153{
154 unsigned long flags;
155
156 /* clean all ways */
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500157 raw_spin_lock_irqsave(&l2x0_lock, flags);
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530158 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
159 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
160 cache_sync();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500161 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530162}
163
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530164static void l2x0_inv_all(void)
Catalin Marinas382266a2007-02-05 14:48:19 +0100165{
Russell King0eb948d2009-11-19 11:12:15 +0000166 unsigned long flags;
167
Catalin Marinas382266a2007-02-05 14:48:19 +0100168 /* invalidate all ways */
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500169 raw_spin_lock_irqsave(&l2x0_lock, flags);
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530170 /* Invalidating when L2 is enabled is a nono */
171 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100172 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
Catalin Marinas9a6655e2010-08-31 13:05:22 +0100173 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
Catalin Marinas382266a2007-02-05 14:48:19 +0100174 cache_sync();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500175 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100176}
177
178static void l2x0_inv_range(unsigned long start, unsigned long end)
179{
Russell King3d107432009-11-19 11:41:09 +0000180 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000181 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100182
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500183 raw_spin_lock_irqsave(&l2x0_lock, flags);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100184 if (start & (CACHE_LINE_SIZE - 1)) {
185 start &= ~(CACHE_LINE_SIZE - 1);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100186 debug_writel(0x03);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100187 l2x0_flush_line(start);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100188 debug_writel(0x00);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100189 start += CACHE_LINE_SIZE;
190 }
191
192 if (end & (CACHE_LINE_SIZE - 1)) {
193 end &= ~(CACHE_LINE_SIZE - 1);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100194 debug_writel(0x03);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100195 l2x0_flush_line(end);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100196 debug_writel(0x00);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100197 }
198
Russell King0eb948d2009-11-19 11:12:15 +0000199 while (start < end) {
200 unsigned long blk_end = start + min(end - start, 4096UL);
201
202 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100203 l2x0_inv_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000204 start += CACHE_LINE_SIZE;
205 }
206
207 if (blk_end < end) {
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500208 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
209 raw_spin_lock_irqsave(&l2x0_lock, flags);
Russell King0eb948d2009-11-19 11:12:15 +0000210 }
211 }
Russell King3d107432009-11-19 11:41:09 +0000212 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100213 cache_sync();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500214 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100215}
216
217static void l2x0_clean_range(unsigned long start, unsigned long end)
218{
Russell King3d107432009-11-19 11:41:09 +0000219 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000220 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100221
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530222 if ((end - start) >= l2x0_size) {
223 l2x0_clean_all();
224 return;
225 }
226
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500227 raw_spin_lock_irqsave(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100228 start &= ~(CACHE_LINE_SIZE - 1);
Russell King0eb948d2009-11-19 11:12:15 +0000229 while (start < end) {
230 unsigned long blk_end = start + min(end - start, 4096UL);
231
232 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100233 l2x0_clean_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000234 start += CACHE_LINE_SIZE;
235 }
236
237 if (blk_end < end) {
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500238 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
239 raw_spin_lock_irqsave(&l2x0_lock, flags);
Russell King0eb948d2009-11-19 11:12:15 +0000240 }
241 }
Russell King3d107432009-11-19 11:41:09 +0000242 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100243 cache_sync();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500244 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100245}
246
247static void l2x0_flush_range(unsigned long start, unsigned long end)
248{
Russell King3d107432009-11-19 11:41:09 +0000249 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000250 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100251
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530252 if ((end - start) >= l2x0_size) {
253 l2x0_flush_all();
254 return;
255 }
256
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500257 raw_spin_lock_irqsave(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100258 start &= ~(CACHE_LINE_SIZE - 1);
Russell King0eb948d2009-11-19 11:12:15 +0000259 while (start < end) {
260 unsigned long blk_end = start + min(end - start, 4096UL);
261
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100262 debug_writel(0x03);
Russell King0eb948d2009-11-19 11:12:15 +0000263 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100264 l2x0_flush_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000265 start += CACHE_LINE_SIZE;
266 }
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100267 debug_writel(0x00);
Russell King0eb948d2009-11-19 11:12:15 +0000268
269 if (blk_end < end) {
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500270 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
271 raw_spin_lock_irqsave(&l2x0_lock, flags);
Russell King0eb948d2009-11-19 11:12:15 +0000272 }
273 }
Russell King3d107432009-11-19 11:41:09 +0000274 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100275 cache_sync();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500276 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100277}
278
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530279static void l2x0_disable(void)
280{
281 unsigned long flags;
282
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500283 raw_spin_lock_irqsave(&l2x0_lock, flags);
Will Deacon38a89142011-07-01 14:36:19 +0100284 __l2x0_flush_all();
285 writel_relaxed(0, l2x0_base + L2X0_CTRL);
286 dsb();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500287 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530288}
289
Russell King3e175ca2011-09-18 11:27:30 +0100290static void l2x0_unlock(u32 cache_id)
Linus Walleijbac7e6e2011-09-06 07:45:46 +0100291{
292 int lockregs;
293 int i;
294
295 if (cache_id == L2X0_CACHE_ID_PART_L310)
296 lockregs = 8;
297 else
298 /* L210 and unknown types */
299 lockregs = 1;
300
301 for (i = 0; i < lockregs; i++) {
302 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
303 i * L2X0_LOCKDOWN_STRIDE);
304 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
305 i * L2X0_LOCKDOWN_STRIDE);
306 }
307}
308
Russell King3e175ca2011-09-18 11:27:30 +0100309void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
Catalin Marinas382266a2007-02-05 14:48:19 +0100310{
Russell King3e175ca2011-09-18 11:27:30 +0100311 u32 aux;
312 u32 cache_id;
313 u32 way_size = 0;
Jason McMullan64039be2010-05-05 18:59:37 +0100314 int ways;
315 const char *type;
Catalin Marinas382266a2007-02-05 14:48:19 +0100316
317 l2x0_base = base;
318
Catalin Marinas6775a552010-07-28 22:01:25 +0100319 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
320 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
Jason McMullan64039be2010-05-05 18:59:37 +0100321
Sascha Hauer4082cfa2010-07-08 08:36:21 +0100322 aux &= aux_mask;
323 aux |= aux_val;
324
Jason McMullan64039be2010-05-05 18:59:37 +0100325 /* Determine the number of ways */
326 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
327 case L2X0_CACHE_ID_PART_L310:
328 if (aux & (1 << 16))
329 ways = 16;
330 else
331 ways = 8;
332 type = "L310";
Will Deaconf154fe92012-04-20 17:21:08 +0100333#ifdef CONFIG_PL310_ERRATA_753970
334 /* Unmapped register. */
335 sync_reg_offset = L2X0_DUMMY_REG;
336#endif
Will Deaconab4d5362012-04-20 17:22:11 +0100337 outer_cache.set_debug = pl310_set_debug;
Jason McMullan64039be2010-05-05 18:59:37 +0100338 break;
339 case L2X0_CACHE_ID_PART_L210:
340 ways = (aux >> 13) & 0xf;
341 type = "L210";
342 break;
343 default:
344 /* Assume unknown chips have 8 ways */
345 ways = 8;
346 type = "L2x0 series";
347 break;
348 }
349
350 l2x0_way_mask = (1 << ways) - 1;
351
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100352 /*
Santosh Shilimkar5ba70372010-07-11 14:35:37 +0530353 * L2 cache Size = Way size * Number of ways
354 */
355 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
356 way_size = 1 << (way_size + 3);
357 l2x0_size = ways * way_size * SZ_1K;
358
359 /*
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100360 * Check if l2x0 controller is already enabled.
361 * If you are booting from non-secure mode
362 * accessing the below registers will fault.
363 */
Catalin Marinas6775a552010-07-28 22:01:25 +0100364 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
Linus Walleijbac7e6e2011-09-06 07:45:46 +0100365 /* Make sure that I&D is not locked down when starting */
366 l2x0_unlock(cache_id);
Catalin Marinas382266a2007-02-05 14:48:19 +0100367
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100368 /* l2x0 controller is disabled */
Catalin Marinas6775a552010-07-28 22:01:25 +0100369 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
Catalin Marinas382266a2007-02-05 14:48:19 +0100370
Barry Song91c2ebb2011-09-30 14:43:12 +0100371 l2x0_saved_regs.aux_ctrl = aux;
372
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100373 l2x0_inv_all();
374
375 /* enable L2X0 */
Catalin Marinas6775a552010-07-28 22:01:25 +0100376 writel_relaxed(1, l2x0_base + L2X0_CTRL);
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100377 }
Catalin Marinas382266a2007-02-05 14:48:19 +0100378
379 outer_cache.inv_range = l2x0_inv_range;
380 outer_cache.clean_range = l2x0_clean_range;
381 outer_cache.flush_range = l2x0_flush_range;
Catalin Marinas23107c52010-03-24 16:48:53 +0100382 outer_cache.sync = l2x0_cache_sync;
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530383 outer_cache.flush_all = l2x0_flush_all;
384 outer_cache.inv_all = l2x0_inv_all;
385 outer_cache.disable = l2x0_disable;
Catalin Marinas382266a2007-02-05 14:48:19 +0100386
Jason McMullan64039be2010-05-05 18:59:37 +0100387 printk(KERN_INFO "%s cache controller enabled\n", type);
Santosh Shilimkar5ba70372010-07-11 14:35:37 +0530388 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
389 ways, cache_id, aux, l2x0_size);
Catalin Marinas382266a2007-02-05 14:48:19 +0100390}
Rob Herring8c369262011-08-03 18:12:05 +0100391
392#ifdef CONFIG_OF
393static void __init l2x0_of_setup(const struct device_node *np,
Russell King3e175ca2011-09-18 11:27:30 +0100394 u32 *aux_val, u32 *aux_mask)
Rob Herring8c369262011-08-03 18:12:05 +0100395{
396 u32 data[2] = { 0, 0 };
397 u32 tag = 0;
398 u32 dirty = 0;
399 u32 val = 0, mask = 0;
400
401 of_property_read_u32(np, "arm,tag-latency", &tag);
402 if (tag) {
403 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
404 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
405 }
406
407 of_property_read_u32_array(np, "arm,data-latency",
408 data, ARRAY_SIZE(data));
409 if (data[0] && data[1]) {
410 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
411 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
412 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
413 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
414 }
415
416 of_property_read_u32(np, "arm,dirty-latency", &dirty);
417 if (dirty) {
418 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
419 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
420 }
421
422 *aux_val &= ~mask;
423 *aux_val |= val;
424 *aux_mask &= ~mask;
425}
426
427static void __init pl310_of_setup(const struct device_node *np,
Russell King3e175ca2011-09-18 11:27:30 +0100428 u32 *aux_val, u32 *aux_mask)
Rob Herring8c369262011-08-03 18:12:05 +0100429{
430 u32 data[3] = { 0, 0, 0 };
431 u32 tag[3] = { 0, 0, 0 };
432 u32 filter[2] = { 0, 0 };
433
434 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
435 if (tag[0] && tag[1] && tag[2])
436 writel_relaxed(
437 ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
438 ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
439 ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
440 l2x0_base + L2X0_TAG_LATENCY_CTRL);
441
442 of_property_read_u32_array(np, "arm,data-latency",
443 data, ARRAY_SIZE(data));
444 if (data[0] && data[1] && data[2])
445 writel_relaxed(
446 ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
447 ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
448 ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
449 l2x0_base + L2X0_DATA_LATENCY_CTRL);
450
451 of_property_read_u32_array(np, "arm,filter-ranges",
452 filter, ARRAY_SIZE(filter));
Barry Song74d41f32011-09-14 03:20:01 +0100453 if (filter[1]) {
Rob Herring8c369262011-08-03 18:12:05 +0100454 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
455 l2x0_base + L2X0_ADDR_FILTER_END);
456 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
457 l2x0_base + L2X0_ADDR_FILTER_START);
458 }
459}
460
Barry Song91c2ebb2011-09-30 14:43:12 +0100461static void __init pl310_save(void)
462{
463 u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
464 L2X0_CACHE_ID_RTL_MASK;
465
466 l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
467 L2X0_TAG_LATENCY_CTRL);
468 l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
469 L2X0_DATA_LATENCY_CTRL);
470 l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
471 L2X0_ADDR_FILTER_END);
472 l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
473 L2X0_ADDR_FILTER_START);
474
475 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
476 /*
477 * From r2p0, there is Prefetch offset/control register
478 */
479 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
480 L2X0_PREFETCH_CTRL);
481 /*
482 * From r3p0, there is Power control register
483 */
484 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
485 l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
486 L2X0_POWER_CTRL);
487 }
488}
489
490static void l2x0_resume(void)
491{
492 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
493 /* restore aux ctrl and enable l2 */
494 l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
495
496 writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
497 L2X0_AUX_CTRL);
498
499 l2x0_inv_all();
500
501 writel_relaxed(1, l2x0_base + L2X0_CTRL);
502 }
503}
504
505static void pl310_resume(void)
506{
507 u32 l2x0_revision;
508
509 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
510 /* restore pl310 setup */
511 writel_relaxed(l2x0_saved_regs.tag_latency,
512 l2x0_base + L2X0_TAG_LATENCY_CTRL);
513 writel_relaxed(l2x0_saved_regs.data_latency,
514 l2x0_base + L2X0_DATA_LATENCY_CTRL);
515 writel_relaxed(l2x0_saved_regs.filter_end,
516 l2x0_base + L2X0_ADDR_FILTER_END);
517 writel_relaxed(l2x0_saved_regs.filter_start,
518 l2x0_base + L2X0_ADDR_FILTER_START);
519
520 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
521 L2X0_CACHE_ID_RTL_MASK;
522
523 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
524 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
525 l2x0_base + L2X0_PREFETCH_CTRL);
526 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
527 writel_relaxed(l2x0_saved_regs.pwr_ctrl,
528 l2x0_base + L2X0_POWER_CTRL);
529 }
530 }
531
532 l2x0_resume();
533}
534
535static const struct l2x0_of_data pl310_data = {
536 pl310_of_setup,
537 pl310_save,
538 pl310_resume,
539};
540
541static const struct l2x0_of_data l2x0_data = {
542 l2x0_of_setup,
543 NULL,
544 l2x0_resume,
545};
546
Rob Herring8c369262011-08-03 18:12:05 +0100547static const struct of_device_id l2x0_ids[] __initconst = {
Barry Song91c2ebb2011-09-30 14:43:12 +0100548 { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
549 { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
550 { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
Rob Herring8c369262011-08-03 18:12:05 +0100551 {}
552};
553
Russell King3e175ca2011-09-18 11:27:30 +0100554int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
Rob Herring8c369262011-08-03 18:12:05 +0100555{
556 struct device_node *np;
Uwe Kleine-Könige5b5d022012-05-21 21:54:06 +0200557 const struct l2x0_of_data *data;
Barry Song91c2ebb2011-09-30 14:43:12 +0100558 struct resource res;
Rob Herring8c369262011-08-03 18:12:05 +0100559
560 np = of_find_matching_node(NULL, l2x0_ids);
561 if (!np)
562 return -ENODEV;
Barry Song91c2ebb2011-09-30 14:43:12 +0100563
564 if (of_address_to_resource(np, 0, &res))
565 return -ENODEV;
566
567 l2x0_base = ioremap(res.start, resource_size(&res));
Rob Herring8c369262011-08-03 18:12:05 +0100568 if (!l2x0_base)
569 return -ENOMEM;
570
Barry Song91c2ebb2011-09-30 14:43:12 +0100571 l2x0_saved_regs.phy_base = res.start;
572
573 data = of_match_node(l2x0_ids, np)->data;
574
Rob Herring8c369262011-08-03 18:12:05 +0100575 /* L2 configuration can only be changed if the cache is disabled */
576 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
Barry Song91c2ebb2011-09-30 14:43:12 +0100577 if (data->setup)
578 data->setup(np, &aux_val, &aux_mask);
Rob Herring8c369262011-08-03 18:12:05 +0100579 }
Barry Song91c2ebb2011-09-30 14:43:12 +0100580
581 if (data->save)
582 data->save();
583
Rob Herring8c369262011-08-03 18:12:05 +0100584 l2x0_init(l2x0_base, aux_val, aux_mask);
Barry Song91c2ebb2011-09-30 14:43:12 +0100585
586 outer_cache.resume = data->resume;
Rob Herring8c369262011-08-03 18:12:05 +0100587 return 0;
588}
589#endif