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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02005 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Sergei Shtylyov59c8d042009-04-18 17:42:19 +02006 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
Alan Coxb39b01f2005-06-27 15:24:27 -070013 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080014 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
Alan Coxb39b01f2005-06-27 15:24:27 -070019 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 * Note that final HPT370 support was done by force extraction of GPL.
21 *
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
36 *
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
42 *
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
45 *
46 * On hpt366:
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
50 *
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
54 * keeping me sane.
Alan Coxccd32e22008-11-02 21:40:08 +010055 * Alan Cox <alan@lxorguk.ukuu.org.uk>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080057 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010062 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -080066 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
Sergei Shtylyov26c068d2006-12-13 00:35:52 -080069 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
Sergei Shtylyov72931362007-09-11 22:28:35 +020070 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
Sergei Shtylyov33b18a62006-12-13 00:35:50 -080072 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -080074 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010076 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
Sergei Shtylyov90778572007-02-07 18:17:51 +010078 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +020080 * - optimize the UltraDMA filtering and the drive list lookup code
Sergei Shtylyovb4586712007-02-07 18:17:54 +010081 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010082 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +010086 * - rename all the register related variables consistently
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010087 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
Sergei Shtylyov866664d2008-01-25 22:17:05 +010089 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010090 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +010094 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010095 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
Sergei Shtylyov278978e2007-06-08 15:14:32 +0200109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
Sergei Shtylyov6273d262007-02-07 18:18:20 +0100111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200115 * - set the correct hwif->ultra_mask for each individual chip
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
Sergei Shtylyovc018f1e2009-04-18 17:42:19 +0200117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 */
121
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122#include <linux/types.h>
123#include <linux/module.h>
124#include <linux/kernel.h>
125#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126#include <linux/blkdev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127#include <linux/interrupt.h>
128#include <linux/pci.h>
129#include <linux/init.h>
130#include <linux/ide.h>
131
132#include <asm/uaccess.h>
133#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200135#define DRV_NAME "hpt366"
136
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137/* various tuning parameters */
Sergei Shtylyovc018f1e2009-04-18 17:42:19 +0200138#undef HPT_RESET_STATE_ENGINE
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800139#undef HPT_DELAY_INTERRUPT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141static const char *bad_ata100_5[] = {
142 "IBM-DTLA-307075",
143 "IBM-DTLA-307060",
144 "IBM-DTLA-307045",
145 "IBM-DTLA-307030",
146 "IBM-DTLA-307020",
147 "IBM-DTLA-307015",
148 "IBM-DTLA-305040",
149 "IBM-DTLA-305030",
150 "IBM-DTLA-305020",
151 "IC35L010AVER07-0",
152 "IC35L020AVER07-0",
153 "IC35L030AVER07-0",
154 "IC35L040AVER07-0",
155 "IC35L060AVER07-0",
156 "WDC AC310200R",
157 NULL
158};
159
160static const char *bad_ata66_4[] = {
161 "IBM-DTLA-307075",
162 "IBM-DTLA-307060",
163 "IBM-DTLA-307045",
164 "IBM-DTLA-307030",
165 "IBM-DTLA-307020",
166 "IBM-DTLA-307015",
167 "IBM-DTLA-305040",
168 "IBM-DTLA-305030",
169 "IBM-DTLA-305020",
170 "IC35L010AVER07-0",
171 "IC35L020AVER07-0",
172 "IC35L030AVER07-0",
173 "IC35L040AVER07-0",
174 "IC35L060AVER07-0",
175 "WDC AC310200R",
Sergei Shtylyov783353b2007-07-03 22:28:35 +0200176 "MAXTOR STM3320620A",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 NULL
178};
179
180static const char *bad_ata66_3[] = {
181 "WDC AC310200R",
182 NULL
183};
184
185static const char *bad_ata33[] = {
186 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
187 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
188 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
189 "Maxtor 90510D4",
190 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
191 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
192 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
193 NULL
194};
195
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800196static u8 xfer_speeds[] = {
197 XFER_UDMA_6,
198 XFER_UDMA_5,
199 XFER_UDMA_4,
200 XFER_UDMA_3,
201 XFER_UDMA_2,
202 XFER_UDMA_1,
203 XFER_UDMA_0,
204
205 XFER_MW_DMA_2,
206 XFER_MW_DMA_1,
207 XFER_MW_DMA_0,
208
209 XFER_PIO_4,
210 XFER_PIO_3,
211 XFER_PIO_2,
212 XFER_PIO_1,
213 XFER_PIO_0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214};
215
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800216/* Key for bus clock timings
217 * 36x 37x
218 * bits bits
219 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
220 * cycles = value + 1
221 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
222 * cycles = value + 1
223 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
224 * register access.
225 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
226 * register access.
227 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
228 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
229 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
230 * MW DMA xfer.
231 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
232 * task file register access.
233 * 28 28 UDMA enable.
234 * 29 29 DMA enable.
235 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
236 * PIO xfer.
237 * 31 31 FIFO enable.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800240static u32 forty_base_hpt36x[] = {
241 /* XFER_UDMA_6 */ 0x900fd943,
242 /* XFER_UDMA_5 */ 0x900fd943,
243 /* XFER_UDMA_4 */ 0x900fd943,
244 /* XFER_UDMA_3 */ 0x900ad943,
245 /* XFER_UDMA_2 */ 0x900bd943,
246 /* XFER_UDMA_1 */ 0x9008d943,
247 /* XFER_UDMA_0 */ 0x9008d943,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800249 /* XFER_MW_DMA_2 */ 0xa008d943,
250 /* XFER_MW_DMA_1 */ 0xa010d955,
251 /* XFER_MW_DMA_0 */ 0xa010d9fc,
252
253 /* XFER_PIO_4 */ 0xc008d963,
254 /* XFER_PIO_3 */ 0xc010d974,
255 /* XFER_PIO_2 */ 0xc010d997,
256 /* XFER_PIO_1 */ 0xc010d9c7,
257 /* XFER_PIO_0 */ 0xc018d9d9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258};
259
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800260static u32 thirty_three_base_hpt36x[] = {
261 /* XFER_UDMA_6 */ 0x90c9a731,
262 /* XFER_UDMA_5 */ 0x90c9a731,
263 /* XFER_UDMA_4 */ 0x90c9a731,
264 /* XFER_UDMA_3 */ 0x90cfa731,
265 /* XFER_UDMA_2 */ 0x90caa731,
266 /* XFER_UDMA_1 */ 0x90cba731,
267 /* XFER_UDMA_0 */ 0x90c8a731,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800269 /* XFER_MW_DMA_2 */ 0xa0c8a731,
270 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
271 /* XFER_MW_DMA_0 */ 0xa0c8a797,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800273 /* XFER_PIO_4 */ 0xc0c8a731,
274 /* XFER_PIO_3 */ 0xc0c8a742,
275 /* XFER_PIO_2 */ 0xc0d0a753,
276 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
277 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278};
279
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800280static u32 twenty_five_base_hpt36x[] = {
281 /* XFER_UDMA_6 */ 0x90c98521,
282 /* XFER_UDMA_5 */ 0x90c98521,
283 /* XFER_UDMA_4 */ 0x90c98521,
284 /* XFER_UDMA_3 */ 0x90cf8521,
285 /* XFER_UDMA_2 */ 0x90cf8521,
286 /* XFER_UDMA_1 */ 0x90cb8521,
287 /* XFER_UDMA_0 */ 0x90cb8521,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800289 /* XFER_MW_DMA_2 */ 0xa0ca8521,
290 /* XFER_MW_DMA_1 */ 0xa0ca8532,
291 /* XFER_MW_DMA_0 */ 0xa0ca8575,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800293 /* XFER_PIO_4 */ 0xc0ca8521,
294 /* XFER_PIO_3 */ 0xc0ca8532,
295 /* XFER_PIO_2 */ 0xc0ca8542,
296 /* XFER_PIO_1 */ 0xc0d08572,
297 /* XFER_PIO_0 */ 0xc0d08585
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298};
299
Sergei Shtylyov809b53c2007-12-12 23:31:58 +0100300#if 0
301/* These are the timing tables from the HighPoint open source drivers... */
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800302static u32 thirty_three_base_hpt37x[] = {
303 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
304 /* XFER_UDMA_5 */ 0x12446231,
305 /* XFER_UDMA_4 */ 0x12446231,
306 /* XFER_UDMA_3 */ 0x126c6231,
307 /* XFER_UDMA_2 */ 0x12486231,
308 /* XFER_UDMA_1 */ 0x124c6233,
309 /* XFER_UDMA_0 */ 0x12506297,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800311 /* XFER_MW_DMA_2 */ 0x22406c31,
312 /* XFER_MW_DMA_1 */ 0x22406c33,
313 /* XFER_MW_DMA_0 */ 0x22406c97,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800315 /* XFER_PIO_4 */ 0x06414e31,
316 /* XFER_PIO_3 */ 0x06414e42,
317 /* XFER_PIO_2 */ 0x06414e53,
318 /* XFER_PIO_1 */ 0x06814e93,
319 /* XFER_PIO_0 */ 0x06814ea7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320};
321
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800322static u32 fifty_base_hpt37x[] = {
323 /* XFER_UDMA_6 */ 0x12848242,
324 /* XFER_UDMA_5 */ 0x12848242,
325 /* XFER_UDMA_4 */ 0x12ac8242,
326 /* XFER_UDMA_3 */ 0x128c8242,
327 /* XFER_UDMA_2 */ 0x120c8242,
328 /* XFER_UDMA_1 */ 0x12148254,
329 /* XFER_UDMA_0 */ 0x121882ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800331 /* XFER_MW_DMA_2 */ 0x22808242,
332 /* XFER_MW_DMA_1 */ 0x22808254,
333 /* XFER_MW_DMA_0 */ 0x228082ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800335 /* XFER_PIO_4 */ 0x0a81f442,
336 /* XFER_PIO_3 */ 0x0a81f443,
337 /* XFER_PIO_2 */ 0x0a81f454,
338 /* XFER_PIO_1 */ 0x0ac1f465,
339 /* XFER_PIO_0 */ 0x0ac1f48a
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340};
341
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800342static u32 sixty_six_base_hpt37x[] = {
343 /* XFER_UDMA_6 */ 0x1c869c62,
344 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
345 /* XFER_UDMA_4 */ 0x1c8a9c62,
346 /* XFER_UDMA_3 */ 0x1c8e9c62,
347 /* XFER_UDMA_2 */ 0x1c929c62,
348 /* XFER_UDMA_1 */ 0x1c9a9c62,
349 /* XFER_UDMA_0 */ 0x1c829c62,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800351 /* XFER_MW_DMA_2 */ 0x2c829c62,
352 /* XFER_MW_DMA_1 */ 0x2c829c66,
353 /* XFER_MW_DMA_0 */ 0x2c829d2e,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800355 /* XFER_PIO_4 */ 0x0c829c62,
356 /* XFER_PIO_3 */ 0x0c829c84,
357 /* XFER_PIO_2 */ 0x0c829ca6,
358 /* XFER_PIO_1 */ 0x0d029d26,
359 /* XFER_PIO_0 */ 0x0d029d5e
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360};
Sergei Shtylyov809b53c2007-12-12 23:31:58 +0100361#else
362/*
363 * The following are the new timing tables with PIO mode data/taskfile transfer
364 * overclocking fixed...
365 */
366
367/* This table is taken from the HPT370 data manual rev. 1.02 */
368static u32 thirty_three_base_hpt37x[] = {
369 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
370 /* XFER_UDMA_5 */ 0x16455031,
371 /* XFER_UDMA_4 */ 0x16455031,
372 /* XFER_UDMA_3 */ 0x166d5031,
373 /* XFER_UDMA_2 */ 0x16495031,
374 /* XFER_UDMA_1 */ 0x164d5033,
375 /* XFER_UDMA_0 */ 0x16515097,
376
377 /* XFER_MW_DMA_2 */ 0x26515031,
378 /* XFER_MW_DMA_1 */ 0x26515033,
379 /* XFER_MW_DMA_0 */ 0x26515097,
380
381 /* XFER_PIO_4 */ 0x06515021,
382 /* XFER_PIO_3 */ 0x06515022,
383 /* XFER_PIO_2 */ 0x06515033,
384 /* XFER_PIO_1 */ 0x06915065,
385 /* XFER_PIO_0 */ 0x06d1508a
386};
387
388static u32 fifty_base_hpt37x[] = {
389 /* XFER_UDMA_6 */ 0x1a861842,
390 /* XFER_UDMA_5 */ 0x1a861842,
391 /* XFER_UDMA_4 */ 0x1aae1842,
392 /* XFER_UDMA_3 */ 0x1a8e1842,
393 /* XFER_UDMA_2 */ 0x1a0e1842,
394 /* XFER_UDMA_1 */ 0x1a161854,
395 /* XFER_UDMA_0 */ 0x1a1a18ea,
396
397 /* XFER_MW_DMA_2 */ 0x2a821842,
398 /* XFER_MW_DMA_1 */ 0x2a821854,
399 /* XFER_MW_DMA_0 */ 0x2a8218ea,
400
401 /* XFER_PIO_4 */ 0x0a821842,
402 /* XFER_PIO_3 */ 0x0a821843,
403 /* XFER_PIO_2 */ 0x0a821855,
404 /* XFER_PIO_1 */ 0x0ac218a8,
405 /* XFER_PIO_0 */ 0x0b02190c
406};
407
408static u32 sixty_six_base_hpt37x[] = {
409 /* XFER_UDMA_6 */ 0x1c86fe62,
410 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
411 /* XFER_UDMA_4 */ 0x1c8afe62,
412 /* XFER_UDMA_3 */ 0x1c8efe62,
413 /* XFER_UDMA_2 */ 0x1c92fe62,
414 /* XFER_UDMA_1 */ 0x1c9afe62,
415 /* XFER_UDMA_0 */ 0x1c82fe62,
416
417 /* XFER_MW_DMA_2 */ 0x2c82fe62,
418 /* XFER_MW_DMA_1 */ 0x2c82fe66,
419 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
420
421 /* XFER_PIO_4 */ 0x0c82fe62,
422 /* XFER_PIO_3 */ 0x0c82fe84,
423 /* XFER_PIO_2 */ 0x0c82fea6,
424 /* XFER_PIO_1 */ 0x0d02ff26,
425 /* XFER_PIO_0 */ 0x0d42ff7f
426};
427#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429#define HPT366_DEBUG_DRIVE_INFO 0
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100430#define HPT371_ALLOW_ATA133_6 1
431#define HPT302_ALLOW_ATA133_6 1
432#define HPT372_ALLOW_ATA133_6 1
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100433#define HPT370_ALLOW_ATA100_5 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434#define HPT366_ALLOW_ATA66_4 1
435#define HPT366_ALLOW_ATA66_3 1
436#define HPT366_MAX_DEVS 8
437
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100438/* Supported ATA clock frequencies */
439enum ata_clock {
440 ATA_CLOCK_25MHZ,
441 ATA_CLOCK_33MHZ,
442 ATA_CLOCK_40MHZ,
443 ATA_CLOCK_50MHZ,
444 ATA_CLOCK_66MHZ,
445 NUM_ATA_CLOCKS
Alan Coxb39b01f2005-06-27 15:24:27 -0700446};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100448struct hpt_timings {
449 u32 pio_mask;
450 u32 dma_mask;
451 u32 ultra_mask;
452 u32 *clock_table[NUM_ATA_CLOCKS];
453};
454
Alan Coxb39b01f2005-06-27 15:24:27 -0700455/*
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100456 * Hold all the HighPoint chip information in one place.
Alan Coxb39b01f2005-06-27 15:24:27 -0700457 */
458
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100459struct hpt_info {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200460 char *chip_name; /* Chip name */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100461 u8 chip_type; /* Chip type */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200462 u8 udma_mask; /* Allowed UltraDMA modes mask. */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100463 u8 dpll_clk; /* DPLL clock in MHz */
464 u8 pci_clk; /* PCI clock in MHz */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100465 struct hpt_timings *timings; /* Chipset timing data */
466 u8 clock; /* ATA clock selected */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100467};
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100468
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100469/* Supported HighPoint chips */
470enum {
471 HPT36x,
472 HPT370,
473 HPT370A,
474 HPT374,
475 HPT372,
476 HPT372A,
477 HPT302,
478 HPT371,
479 HPT372N,
480 HPT302N,
481 HPT371N
482};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100484static struct hpt_timings hpt36x_timings = {
485 .pio_mask = 0xc1f8ffff,
486 .dma_mask = 0x303800ff,
487 .ultra_mask = 0x30070000,
488 .clock_table = {
489 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
490 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
491 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
492 [ATA_CLOCK_50MHZ] = NULL,
493 [ATA_CLOCK_66MHZ] = NULL
494 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100495};
496
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100497static struct hpt_timings hpt37x_timings = {
498 .pio_mask = 0xcfc3ffff,
499 .dma_mask = 0x31c001ff,
500 .ultra_mask = 0x303c0000,
501 .clock_table = {
502 [ATA_CLOCK_25MHZ] = NULL,
503 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
504 [ATA_CLOCK_40MHZ] = NULL,
505 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
506 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
507 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100508};
509
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200510static const struct hpt_info hpt36x __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200511 .chip_name = "HPT36x",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100512 .chip_type = HPT36x,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200513 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100514 .dpll_clk = 0, /* no DPLL */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100515 .timings = &hpt36x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100516};
517
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200518static const struct hpt_info hpt370 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200519 .chip_name = "HPT370",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100520 .chip_type = HPT370,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200521 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100522 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100523 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100524};
525
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200526static const struct hpt_info hpt370a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200527 .chip_name = "HPT370A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100528 .chip_type = HPT370A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200529 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100530 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100531 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100532};
533
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200534static const struct hpt_info hpt374 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200535 .chip_name = "HPT374",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100536 .chip_type = HPT374,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200537 .udma_mask = ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100538 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100539 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100540};
541
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200542static const struct hpt_info hpt372 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200543 .chip_name = "HPT372",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100544 .chip_type = HPT372,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200545 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100546 .dpll_clk = 55,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100547 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100548};
549
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200550static const struct hpt_info hpt372a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200551 .chip_name = "HPT372A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100552 .chip_type = HPT372A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200553 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100554 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100555 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100556};
557
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200558static const struct hpt_info hpt302 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200559 .chip_name = "HPT302",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100560 .chip_type = HPT302,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200561 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100562 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100563 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100564};
565
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200566static const struct hpt_info hpt371 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200567 .chip_name = "HPT371",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100568 .chip_type = HPT371,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200569 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100570 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100571 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100572};
573
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200574static const struct hpt_info hpt372n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200575 .chip_name = "HPT372N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100576 .chip_type = HPT372N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200577 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100578 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100579 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100580};
581
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200582static const struct hpt_info hpt302n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200583 .chip_name = "HPT302N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100584 .chip_type = HPT302N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200585 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100586 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100587 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100588};
589
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200590static const struct hpt_info hpt371n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200591 .chip_name = "HPT371N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100592 .chip_type = HPT371N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200593 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100594 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100595 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100596};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100598static int check_in_drive_list(ide_drive_t *drive, const char **list)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599{
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200600 char *m = (char *)&drive->id[ATA_ID_PROD];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100602 while (*list)
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200603 if (!strcmp(*list++, m))
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100604 return 1;
605 return 0;
606}
Alan Coxb39b01f2005-06-27 15:24:27 -0700607
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200608static struct hpt_info *hpt3xx_get_info(struct device *dev)
609{
610 struct ide_host *host = dev_get_drvdata(dev);
611 struct hpt_info *info = (struct hpt_info *)host->host_priv;
612
613 return dev == host->dev[1] ? info + 1 : info;
614}
615
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616/*
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200617 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
618 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619 */
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200620
621static u8 hpt3xx_udma_filter(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100623 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200624 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200625 u8 mask = hwif->ultra_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200627 switch (info->chip_type) {
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200628 case HPT36x:
629 if (!HPT366_ALLOW_ATA66_4 ||
630 check_in_drive_list(drive, bad_ata66_4))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200631 mask = ATA_UDMA3;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100632
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200633 if (!HPT366_ALLOW_ATA66_3 ||
634 check_in_drive_list(drive, bad_ata66_3))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200635 mask = ATA_UDMA2;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200636 break;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200637 case HPT370:
638 if (!HPT370_ALLOW_ATA100_5 ||
639 check_in_drive_list(drive, bad_ata100_5))
640 mask = ATA_UDMA4;
641 break;
642 case HPT370A:
643 if (!HPT370_ALLOW_ATA100_5 ||
644 check_in_drive_list(drive, bad_ata100_5))
645 return ATA_UDMA4;
646 case HPT372 :
647 case HPT372A:
648 case HPT372N:
649 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200650 if (ata_id_is_sata(drive->id))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200651 mask &= ~0x0e;
652 /* Fall thru */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200653 default:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200654 return mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655 }
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200656
657 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658}
659
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200660static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
661{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100662 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200663 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200664
665 switch (info->chip_type) {
666 case HPT372 :
667 case HPT372A:
668 case HPT372N:
669 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200670 if (ata_id_is_sata(drive->id))
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200671 return 0x00;
672 /* Fall thru */
673 default:
674 return 0x07;
675 }
676}
677
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100678static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679{
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800680 int i;
681
682 /*
683 * Lookup the transfer mode table to get the index into
684 * the timing table.
685 *
686 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
687 */
688 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
689 if (xfer_speeds[i] == speed)
690 break;
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100691
692 return info->timings->clock_table[info->clock][i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693}
694
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100695static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696{
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +0200697 ide_hwif_t *hwif = drive->hwif;
698 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200699 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100700 struct hpt_timings *t = info->timings;
701 u8 itr_addr = 0x40 + (drive->dn * 4);
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100702 u32 old_itr = 0;
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100703 u32 new_itr = get_speed_setting(speed, info);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100704 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
705 (speed < XFER_UDMA_0 ? t->dma_mask :
706 t->ultra_mask);
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200707
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100708 pci_read_config_dword(dev, itr_addr, &old_itr);
709 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710 /*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100711 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
712 * to avoid problems handling I/O errors later
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100714 new_itr &= ~0xc0000000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100716 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717}
718
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200719static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720{
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100721 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722}
723
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100724static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100726 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100727 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200728 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729
Bartlomiej Zolnierkiewicz734affd2009-06-07 15:37:10 +0200730 if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200731 return;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100732
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200733 if (info->chip_type >= HPT370) {
734 u8 scr1 = 0;
735
736 pci_read_config_byte(dev, 0x5a, &scr1);
737 if (((scr1 & 0x10) >> 4) != mask) {
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100738 if (mask)
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200739 scr1 |= 0x10;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100740 else
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200741 scr1 &= ~0x10;
742 pci_write_config_byte(dev, 0x5a, scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743 }
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200744 } else if (mask)
745 disable_irq(hwif->irq);
746 else
747 enable_irq(hwif->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748}
749
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750/*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100751 * This is specific to the HPT366 UDMA chipset
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 * by HighPoint|Triones Technologies, Inc.
753 */
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200754static void hpt366_dma_lost_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100756 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100757 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100759 pci_read_config_byte(dev, 0x50, &mcr1);
760 pci_read_config_byte(dev, 0x52, &mcr3);
761 pci_read_config_byte(dev, 0x5a, &scr1);
762 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
Harvey Harrisoneb639632008-04-26 22:25:20 +0200763 drive->name, __func__, mcr1, mcr3, scr1);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100764 if (scr1 & 0x10)
765 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200766 ide_dma_lost_irq(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767}
768
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100769static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100771 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100772 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100773
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100774 pci_write_config_byte(dev, hwif->select_data, 0x37);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 udelay(10);
776}
777
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100778static void hpt370_irq_timeout(ide_drive_t *drive)
779{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100780 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100781 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100782 u16 bfifo = 0;
783 u8 dma_cmd;
784
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100785 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100786 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
787
788 /* get DMA command mode */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200789 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100790 /* stop DMA */
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200791 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100792 hpt370_clear_engine(drive);
793}
794
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200795static void hpt370_dma_start(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796{
797#ifdef HPT_RESET_STATE_ENGINE
798 hpt370_clear_engine(drive);
799#endif
800 ide_dma_start(drive);
801}
802
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200803static int hpt370_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100805 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200806 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200808 if (dma_stat & ATA_DMA_ACTIVE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809 /* wait a little */
810 udelay(20);
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200811 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200812 if (dma_stat & ATA_DMA_ACTIVE)
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100813 hpt370_irq_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 }
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200815 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816}
817
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818/* returns 1 if DMA IRQ issued, 0 otherwise */
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200819static int hpt374_dma_test_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100821 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100822 struct pci_dev *dev = to_pci_dev(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823 u16 bfifo = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100824 u8 dma_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100826 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827 if (bfifo & 0x1FF) {
828// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
829 return 0;
830 }
831
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200832 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 /* return 1 if INTR asserted */
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200834 if (dma_stat & ATA_DMA_INTR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835 return 1;
836
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 return 0;
838}
839
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200840static int hpt374_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100842 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100843 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100844 u8 mcr = 0, mcr_addr = hwif->select_data;
845 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100847 pci_read_config_byte(dev, 0x6a, &bwsr);
848 pci_read_config_byte(dev, mcr_addr, &mcr);
849 if (bwsr & mask)
850 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200851 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852}
853
854/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800855 * hpt3xxn_set_clock - perform clock switching dance
856 * @hwif: hwif to switch
857 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800859 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800861
862static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863{
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100864 unsigned long base = hwif->extra_base;
865 u8 scr2 = inb(base + 0x6b);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800866
867 if ((scr2 & 0x7f) == mode)
868 return;
869
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 /* Tristate the bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100871 outb(0x80, base + 0x63);
872 outb(0x80, base + 0x67);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800873
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 /* Switch clock and reset channels */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100875 outb(mode, base + 0x6b);
876 outb(0xc0, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800877
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100878 /*
879 * Reset the state machines.
880 * NOTE: avoid accidentally enabling the disabled channels.
881 */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100882 outb(inb(base + 0x60) | 0x32, base + 0x60);
883 outb(inb(base + 0x64) | 0x32, base + 0x64);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800884
Linus Torvalds1da177e2005-04-16 15:20:36 -0700885 /* Complete reset */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100886 outb(0x00, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800887
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888 /* Reconnect channels to bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100889 outb(0x00, base + 0x63);
890 outb(0x00, base + 0x67);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891}
892
893/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800894 * hpt3xxn_rw_disk - prepare for I/O
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895 * @drive: drive for command
896 * @rq: block request structure
897 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800898 * This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899 * We need it because of the clock switching.
900 */
901
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800902static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100904 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905}
906
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100907/**
908 * hpt37x_calibrate_dpll - calibrate the DPLL
909 * @dev: PCI device
910 *
911 * Perform a calibration cycle on the DPLL.
912 * Returns 1 if this succeeds
913 */
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200914static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700915{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100916 u32 dpll = (f_high << 16) | f_low | 0x100;
917 u8 scr2;
918 int i;
Alan Coxb39b01f2005-06-27 15:24:27 -0700919
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100920 pci_write_config_dword(dev, 0x5c, dpll);
Alan Coxb39b01f2005-06-27 15:24:27 -0700921
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100922 /* Wait for oscillator ready */
923 for(i = 0; i < 0x5000; ++i) {
924 udelay(50);
925 pci_read_config_byte(dev, 0x5b, &scr2);
926 if (scr2 & 0x80)
Alan Coxb39b01f2005-06-27 15:24:27 -0700927 break;
928 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100929 /* See if it stays ready (we'll just bail out if it's not yet) */
930 for(i = 0; i < 0x1000; ++i) {
931 pci_read_config_byte(dev, 0x5b, &scr2);
932 /* DPLL destabilized? */
933 if(!(scr2 & 0x80))
934 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +0100935 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100936 /* Turn off tuning, we have the DPLL set */
937 pci_read_config_dword (dev, 0x5c, &dpll);
938 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
939 return 1;
Alan Coxb39b01f2005-06-27 15:24:27 -0700940}
941
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200942static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +0200943{
944 struct ide_host *host = pci_get_drvdata(dev);
945 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
946 u8 chip_type = info->chip_type;
947 u8 new_mcr, old_mcr = 0;
948
949 /*
950 * Disable the "fast interrupt" prediction. Don't hold off
951 * on interrupts. (== 0x01 despite what the docs say)
952 */
953 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
954
955 if (chip_type >= HPT374)
956 new_mcr = old_mcr & ~0x07;
957 else if (chip_type >= HPT370) {
958 new_mcr = old_mcr;
959 new_mcr &= ~0x02;
960#ifdef HPT_DELAY_INTERRUPT
961 new_mcr &= ~0x01;
962#else
963 new_mcr |= 0x01;
964#endif
965 } else /* HPT366 and HPT368 */
966 new_mcr = old_mcr & ~0x80;
967
968 if (new_mcr != old_mcr)
969 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
970}
971
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +0100972static int init_chipset_hpt366(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100974 unsigned long io_base = pci_resource_start(dev, 4);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200975 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
Bartlomiej Zolnierkiewicza326b022008-07-24 22:53:33 +0200976 const char *name = DRV_NAME;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100977 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200978 u8 chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100979 enum ata_clock clock;
980
Sergei Shtylyov72931362007-09-11 22:28:35 +0200981 chip_type = info->chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100982
Alan Coxb39b01f2005-06-27 15:24:27 -0700983 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
984 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
985 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
986 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100988 /*
989 * First, try to estimate the PCI clock frequency...
990 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200991 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100992 u8 scr1 = 0;
993 u16 f_cnt = 0;
994 u32 temp = 0;
Alan Coxb39b01f2005-06-27 15:24:27 -0700995
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100996 /* Interrupt force enable. */
997 pci_read_config_byte(dev, 0x5a, &scr1);
998 if (scr1 & 0x10)
999 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001000
1001 /*
1002 * HighPoint does this for HPT372A.
1003 * NOTE: This register is only writeable via I/O space.
1004 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001005 if (chip_type == HPT372A)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001006 outb(0x0e, io_base + 0x9c);
1007
1008 /*
1009 * Default to PCI clock. Make sure MA15/16 are set to output
1010 * to prevent drives having problems with 40-pin cables.
1011 */
1012 pci_write_config_byte(dev, 0x5b, 0x23);
1013
1014 /*
1015 * We'll have to read f_CNT value in order to determine
1016 * the PCI clock frequency according to the following ratio:
1017 *
1018 * f_CNT = Fpci * 192 / Fdpll
1019 *
1020 * First try reading the register in which the HighPoint BIOS
1021 * saves f_CNT value before reprogramming the DPLL from its
1022 * default setting (which differs for the various chips).
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001023 *
Sergei Shtylyov72931362007-09-11 22:28:35 +02001024 * NOTE: This register is only accessible via I/O space;
1025 * HPT374 BIOS only saves it for the function 0, so we have to
1026 * always read it from there -- no need to check the result of
1027 * pci_get_slot() for the function 0 as the whole device has
1028 * been already "pinned" (via function 1) in init_setup_hpt374()
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001029 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001030 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1031 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1032 dev->devfn - 1);
1033 unsigned long io_base = pci_resource_start(dev1, 4);
1034
1035 temp = inl(io_base + 0x90);
1036 pci_dev_put(dev1);
1037 } else
1038 temp = inl(io_base + 0x90);
1039
1040 /*
1041 * In case the signature check fails, we'll have to
1042 * resort to reading the f_CNT register itself in hopes
1043 * that nobody has touched the DPLL yet...
1044 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001045 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1046 int i;
1047
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001048 printk(KERN_WARNING "%s %s: no clock data saved by "
1049 "BIOS\n", name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001050
1051 /* Calculate the average value of f_CNT. */
1052 for (temp = i = 0; i < 128; i++) {
1053 pci_read_config_word(dev, 0x78, &f_cnt);
1054 temp += f_cnt & 0x1ff;
1055 mdelay(1);
1056 }
1057 f_cnt = temp / 128;
1058 } else
1059 f_cnt = temp & 0x1ff;
1060
1061 dpll_clk = info->dpll_clk;
1062 pci_clk = (f_cnt * dpll_clk) / 192;
1063
1064 /* Clamp PCI clock to bands. */
1065 if (pci_clk < 40)
1066 pci_clk = 33;
1067 else if(pci_clk < 45)
1068 pci_clk = 40;
1069 else if(pci_clk < 55)
1070 pci_clk = 50;
1071 else
1072 pci_clk = 66;
1073
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001074 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1075 "assuming %d MHz PCI\n", name, pci_name(dev),
1076 dpll_clk, f_cnt, pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001077 } else {
1078 u32 itr1 = 0;
1079
1080 pci_read_config_dword(dev, 0x40, &itr1);
1081
1082 /* Detect PCI clock by looking at cmd_high_time. */
1083 switch((itr1 >> 8) & 0x07) {
1084 case 0x09:
1085 pci_clk = 40;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001086 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001087 case 0x05:
1088 pci_clk = 25;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001089 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001090 case 0x07:
1091 default:
1092 pci_clk = 33;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001093 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001094 }
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001095 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001097 /* Let's assume we'll use PCI clock for the ATA clock... */
1098 switch (pci_clk) {
1099 case 25:
1100 clock = ATA_CLOCK_25MHZ;
1101 break;
1102 case 33:
1103 default:
1104 clock = ATA_CLOCK_33MHZ;
1105 break;
1106 case 40:
1107 clock = ATA_CLOCK_40MHZ;
1108 break;
1109 case 50:
1110 clock = ATA_CLOCK_50MHZ;
1111 break;
1112 case 66:
1113 clock = ATA_CLOCK_66MHZ;
1114 break;
1115 }
1116
1117 /*
1118 * Only try the DPLL if we don't have a table for the PCI clock that
1119 * we are running at for HPT370/A, always use it for anything newer...
1120 *
1121 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1122 * We also don't like using the DPLL because this causes glitches
1123 * on PRST-/SRST- when the state engine gets reset...
1124 */
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001125 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001126 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1127 int adjust;
1128
1129 /*
1130 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1131 * supported/enabled, use 50 MHz DPLL clock otherwise...
1132 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001133 if (info->udma_mask == ATA_UDMA6) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001134 dpll_clk = 66;
1135 clock = ATA_CLOCK_66MHZ;
1136 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1137 dpll_clk = 50;
1138 clock = ATA_CLOCK_50MHZ;
1139 }
1140
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001141 if (info->timings->clock_table[clock] == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001142 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1143 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001144 return -EIO;
1145 }
1146
1147 /* Select the DPLL clock. */
1148 pci_write_config_byte(dev, 0x5b, 0x21);
1149
1150 /*
1151 * Adjust the DPLL based upon PCI clock, enable it,
1152 * and wait for stabilization...
1153 */
1154 f_low = (pci_clk * 48) / dpll_clk;
1155
1156 for (adjust = 0; adjust < 8; adjust++) {
1157 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1158 break;
1159
1160 /*
1161 * See if it'll settle at a fractionally different clock
1162 */
1163 if (adjust & 1)
1164 f_low -= adjust >> 1;
1165 else
1166 f_low += adjust >> 1;
1167 }
1168 if (adjust == 8) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001169 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1170 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001171 return -EIO;
1172 }
1173
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001174 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1175 name, pci_name(dev), dpll_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001176 } else {
1177 /* Mark the fact that we're not using the DPLL. */
1178 dpll_clk = 0;
1179
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001180 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1181 name, pci_name(dev), pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001182 }
1183
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001184 /* Store the clock frequencies. */
1185 info->dpll_clk = dpll_clk;
1186 info->pci_clk = pci_clk;
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001187 info->clock = clock;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001188
Sergei Shtylyov72931362007-09-11 22:28:35 +02001189 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001190 u8 mcr1, mcr4;
1191
1192 /*
1193 * Reset the state engines.
1194 * NOTE: Avoid accidentally enabling the disabled channels.
1195 */
1196 pci_read_config_byte (dev, 0x50, &mcr1);
1197 pci_read_config_byte (dev, 0x54, &mcr4);
1198 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1199 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1200 udelay(100);
1201 }
1202
1203 /*
1204 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1205 * the MISC. register to stretch the UltraDMA Tss timing.
1206 * NOTE: This register is only writeable via I/O space.
1207 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001208 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001209 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1210
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +02001211 hpt3xx_disable_fast_irq(dev, 0x50);
1212 hpt3xx_disable_fast_irq(dev, 0x54);
1213
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +01001214 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215}
1216
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +02001217static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001218{
1219 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001220 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001221 u8 chip_type = info->chip_type;
1222 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1223
1224 /*
1225 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1226 * address lines to access an external EEPROM. To read valid
1227 * cable detect state the pins must be enabled as inputs.
1228 */
1229 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1230 /*
1231 * HPT374 PCI function 1
1232 * - set bit 15 of reg 0x52 to enable TCBLID as input
1233 * - set bit 15 of reg 0x56 to enable FCBLID as input
1234 */
1235 u8 mcr_addr = hwif->select_data + 2;
1236 u16 mcr;
1237
1238 pci_read_config_word(dev, mcr_addr, &mcr);
1239 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1240 /* now read cable id register */
1241 pci_read_config_byte(dev, 0x5a, &scr1);
1242 pci_write_config_word(dev, mcr_addr, mcr);
1243 } else if (chip_type >= HPT370) {
1244 /*
1245 * HPT370/372 and 374 pcifn 0
1246 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1247 */
1248 u8 scr2 = 0;
1249
1250 pci_read_config_byte(dev, 0x5b, &scr2);
1251 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1252 /* now read cable id register */
1253 pci_read_config_byte(dev, 0x5a, &scr1);
1254 pci_write_config_byte(dev, 0x5b, scr2);
1255 } else
1256 pci_read_config_byte(dev, 0x5a, &scr1);
1257
1258 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1259}
1260
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1262{
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001263 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001264 u8 chip_type = info->chip_type;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001265
1266 /* Cache the channel's MISC. control registers' offset */
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001267 hwif->select_data = hwif->channel ? 0x54 : 0x50;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001268
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001269 /*
1270 * HPT3xxN chips have some complications:
1271 *
1272 * - on 33 MHz PCI we must clock switch
1273 * - on 66 MHz PCI we must NOT use the PCI clock
1274 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001275 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001276 /*
1277 * Clock is shared between the channels,
1278 * so we'll have to serialize them... :-(
1279 */
Bartlomiej Zolnierkiewicz702c0262008-12-29 20:27:36 +01001280 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001281 hwif->rw_disk = &hpt3xxn_rw_disk;
1282 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001283}
1284
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001285static int __devinit init_dma_hpt366(ide_hwif_t *hwif,
1286 const struct ide_port_info *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001288 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001289 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1290 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001291
Bartlomiej Zolnierkiewiczebb00fb2008-07-23 19:55:51 +02001292 if (base == 0)
1293 return -1;
1294
1295 hwif->dma_base = base;
1296
1297 if (ide_pci_check_simplex(hwif, d) < 0)
1298 return -1;
1299
1300 if (ide_pci_set_master(dev, d->name) < 0)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001301 return -1;
1302
1303 dma_old = inb(base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304
1305 local_irq_save(flags);
1306
1307 dma_new = dma_old;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001308 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1309 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001310
1311 if (masterdma & 0x30) dma_new |= 0x20;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001312 if ( slavedma & 0x30) dma_new |= 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313 if (dma_new != dma_old)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001314 outb(dma_new, base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315
1316 local_irq_restore(flags);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001317
1318 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1319 hwif->name, base, base + 7);
1320
1321 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1322
1323 if (ide_allocate_dma_engine(hwif))
1324 return -1;
1325
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001326 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001327}
1328
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001329static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001331 if (dev2->irq != dev->irq) {
1332 /* FIXME: we need a core pci_set_interrupt() */
1333 dev2->irq = dev->irq;
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001334 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001335 "fixed\n", pci_name(dev2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337}
1338
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001339static void __devinit hpt371_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340{
Auke Kok44c10132007-06-08 15:46:36 -07001341 u8 mcr1 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001342
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001343 /*
1344 * HPT371 chips physically have only one channel, the secondary one,
1345 * but the primary channel registers do exist! Go figure...
1346 * So, we manually disable the non-existing channel here
1347 * (if the BIOS hasn't done this already).
1348 */
1349 pci_read_config_byte(dev, 0x50, &mcr1);
1350 if (mcr1 & 0x04)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001351 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001352}
1353
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001354static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001355{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001356 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001357
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001358 /*
1359 * Now we'll have to force both channels enabled if
1360 * at least one of them has been enabled by BIOS...
1361 */
1362 pci_read_config_byte(dev, 0x50, &mcr1);
1363 if (mcr1 & 0x30)
1364 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001365
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001366 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1367 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001368
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001369 if (pin1 != pin2 && dev->irq == dev2->irq) {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001370 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001371 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001372 return 1;
1373 }
1374
1375 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001376}
1377
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001378#define IDE_HFLAGS_HPT3XX \
1379 (IDE_HFLAG_NO_ATAPI_DMA | \
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001380 IDE_HFLAG_OFF_BOARD)
1381
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001382static const struct ide_port_ops hpt3xx_port_ops = {
1383 .set_pio_mode = hpt3xx_set_pio_mode,
1384 .set_dma_mode = hpt3xx_set_mode,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001385 .maskproc = hpt3xx_maskproc,
1386 .mdma_filter = hpt3xx_mdma_filter,
1387 .udma_filter = hpt3xx_udma_filter,
1388 .cable_detect = hpt3xx_cable_detect,
1389};
1390
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001391static const struct ide_dma_ops hpt37x_dma_ops = {
1392 .dma_host_set = ide_dma_host_set,
1393 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001394 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001395 .dma_end = hpt374_dma_end,
1396 .dma_test_irq = hpt374_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001397 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001398 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001399 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001400};
1401
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001402static const struct ide_dma_ops hpt370_dma_ops = {
1403 .dma_host_set = ide_dma_host_set,
1404 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001405 .dma_start = hpt370_dma_start,
1406 .dma_end = hpt370_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001407 .dma_test_irq = ide_dma_test_irq,
1408 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001409 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Bartlomiej Zolnierkiewicz35c9b4d2009-03-31 20:15:19 +02001410 .dma_clear = hpt370_irq_timeout,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001411 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001412};
1413
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001414static const struct ide_dma_ops hpt36x_dma_ops = {
1415 .dma_host_set = ide_dma_host_set,
1416 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001417 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +02001418 .dma_end = ide_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001419 .dma_test_irq = ide_dma_test_irq,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001420 .dma_lost_irq = hpt366_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001421 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001422 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001423};
1424
Bartlomiej Zolnierkiewicz85620432007-10-20 00:32:34 +02001425static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001426 { /* 0: HPT36x */
1427 .name = DRV_NAME,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001428 .init_chipset = init_chipset_hpt366,
1429 .init_hwif = init_hwif_hpt366,
1430 .init_dma = init_dma_hpt366,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001431 /*
1432 * HPT36x chips have one channel per function and have
1433 * both channel enable bits located differently and visible
1434 * to both functions -- really stupid design decision... :-(
1435 * Bit 4 is for the primary channel, bit 5 for the secondary.
1436 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001437 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001438 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001439 .dma_ops = &hpt36x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001440 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001441 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001442 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001443 },
1444 { /* 1: HPT3xx */
1445 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446 .init_chipset = init_chipset_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447 .init_hwif = init_hwif_hpt366,
1448 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001449 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001450 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001451 .dma_ops = &hpt37x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001452 .host_flags = IDE_HFLAGS_HPT3XX,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001453 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001454 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001455 }
1456};
1457
1458/**
1459 * hpt366_init_one - called when an HPT366 is found
1460 * @dev: the hpt366 device
1461 * @id: the matching pci id
1462 *
1463 * Called when the PCI registration layer (or the IDE initialization)
1464 * finds a device matching our IDE device tables.
1465 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1467{
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +02001468 const struct hpt_info *info = NULL;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001469 struct hpt_info *dyn_info;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001470 struct pci_dev *dev2 = NULL;
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +02001471 struct ide_port_info d;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001472 u8 idx = id->driver_data;
1473 u8 rev = dev->revision;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001474 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001476 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1477 return -ENODEV;
1478
1479 switch (idx) {
1480 case 0:
1481 if (rev < 3)
1482 info = &hpt36x;
1483 else {
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001484 switch (min_t(u8, rev, 6)) {
1485 case 3: info = &hpt370; break;
1486 case 4: info = &hpt370a; break;
1487 case 5: info = &hpt372; break;
1488 case 6: info = &hpt372n; break;
1489 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001490 idx++;
1491 }
1492 break;
1493 case 1:
1494 info = (rev > 1) ? &hpt372n : &hpt372a;
1495 break;
1496 case 2:
1497 info = (rev > 1) ? &hpt302n : &hpt302;
1498 break;
1499 case 3:
1500 hpt371_init(dev);
1501 info = (rev > 1) ? &hpt371n : &hpt371;
1502 break;
1503 case 4:
1504 info = &hpt374;
1505 break;
1506 case 5:
1507 info = &hpt372n;
1508 break;
1509 }
1510
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001511 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001512
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001513 d = hpt366_chipsets[min_t(u8, idx, 1)];
1514
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001515 d.udma_mask = info->udma_mask;
1516
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001517 /* fixup ->dma_ops for HPT370/HPT370A */
1518 if (info == &hpt370 || info == &hpt370a)
1519 d.dma_ops = &hpt370_dma_ops;
1520
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001521 if (info == &hpt36x || info == &hpt374)
1522 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1523
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001524 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1525 if (dyn_info == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001526 printk(KERN_ERR "%s %s: out of memory!\n",
1527 d.name, pci_name(dev));
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001528 pci_dev_put(dev2);
1529 return -ENOMEM;
1530 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001531
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001532 /*
1533 * Copy everything from a static "template" structure
1534 * to just allocated per-chip hpt_info structure.
1535 */
1536 memcpy(dyn_info, info, sizeof(*dyn_info));
1537
1538 if (dev2) {
1539 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001540
1541 if (info == &hpt374)
1542 hpt374_init(dev, dev2);
1543 else {
1544 if (hpt36x_init(dev, dev2))
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +02001545 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001546 }
1547
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001548 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1549 if (ret < 0) {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001550 pci_dev_put(dev2);
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001551 kfree(dyn_info);
1552 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001553 return ret;
1554 }
1555
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001556 ret = ide_pci_init_one(dev, &d, dyn_info);
1557 if (ret < 0)
1558 kfree(dyn_info);
1559
1560 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561}
1562
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001563static void __devexit hpt366_remove(struct pci_dev *dev)
1564{
1565 struct ide_host *host = pci_get_drvdata(dev);
1566 struct ide_info *info = host->host_priv;
1567 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1568
1569 ide_pci_remove(dev);
1570 pci_dev_put(dev2);
1571 kfree(info);
1572}
1573
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001574static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = {
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001575 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1576 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1577 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1578 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1579 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1580 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581 { 0, },
1582};
1583MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1584
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +02001585static struct pci_driver hpt366_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001586 .name = "HPT366_IDE",
1587 .id_table = hpt366_pci_tbl,
1588 .probe = hpt366_init_one,
Adrian Bunka69999e2008-08-18 21:40:03 +02001589 .remove = __devexit_p(hpt366_remove),
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +02001590 .suspend = ide_pci_suspend,
1591 .resume = ide_pci_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001592};
1593
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +01001594static int __init hpt366_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001595{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +02001596 return ide_pci_register_driver(&hpt366_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597}
1598
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001599static void __exit hpt366_ide_exit(void)
1600{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +02001601 pci_unregister_driver(&hpt366_pci_driver);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001602}
1603
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604module_init(hpt366_ide_init);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001605module_exit(hpt366_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606
1607MODULE_AUTHOR("Andre Hedrick");
1608MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1609MODULE_LICENSE("GPL");