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R Sricharan6e58b8f2013-08-14 19:08:20 +05301/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
R Sricharana46631c2014-06-26 12:55:31 +053015#define MAX_SOURCES 400
16#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
17
R Sricharan6e58b8f2013-08-14 19:08:20 +053018/ {
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 compatible = "ti,dra7xx";
23 interrupt-parent = <&gic>;
24
25 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -050026 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 i2c4 = &i2c5;
R Sricharan6e58b8f2013-08-14 19:08:20 +053031 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 serial5 = &uart6;
Nishanth Menon065bd7f2014-10-21 11:18:15 -050037 serial6 = &uart7;
38 serial7 = &uart8;
39 serial8 = &uart9;
40 serial9 = &uart10;
Mugunthan V Nef9c5b62014-10-21 15:31:00 +053041 ethernet0 = &cpsw_emac0;
42 ethernet1 = &cpsw_emac1;
Roger Quadros9ec49b92014-08-15 16:08:36 +030043 d_can0 = &dcan1;
44 d_can1 = &dcan2;
R Sricharan6e58b8f2013-08-14 19:08:20 +053045 };
46
R Sricharan6e58b8f2013-08-14 19:08:20 +053047 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 };
54
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
57 interrupt-controller;
58 #interrupt-cells = <3>;
R Sricharan51300632014-06-26 12:55:30 +053059 arm,routable-irqs = <192>;
R Sricharan6e58b8f2013-08-14 19:08:20 +053060 reg = <0x48211000 0x1000>,
61 <0x48212000 0x1000>,
62 <0x48214000 0x2000>,
63 <0x48216000 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 };
66
67 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +010068 * The soc node represents the soc top level view. It is used for IPs
R Sricharan6e58b8f2013-08-14 19:08:20 +053069 * that are not memory mapped in the MPU view or for the MPU itself.
70 */
71 soc {
72 compatible = "ti,omap-infra";
73 mpu {
74 compatible = "ti,omap5-mpu";
75 ti,hwmods = "mpu";
76 };
77 };
78
79 /*
80 * XXX: Use a flat representation of the SOC interconnect.
81 * The real OMAP interconnect network is quite complex.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +010082 * Since it will not bring real advantage to represent that in DT for
R Sricharan6e58b8f2013-08-14 19:08:20 +053083 * the moment, just use a fake OCP bus entry to represent the whole bus
84 * hierarchy.
85 */
86 ocp {
Rajendra Nayakfba387a2014-04-10 11:34:32 -050087 compatible = "ti,dra7-l3-noc", "simple-bus";
R Sricharan6e58b8f2013-08-14 19:08:20 +053088 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91 ti,hwmods = "l3_main_1", "l3_main_2";
Rajendra Nayakfba387a2014-04-10 11:34:32 -050092 reg = <0x44000000 0x1000000>,
93 <0x45000000 0x1000>;
R Sricharana46631c2014-06-26 12:55:31 +053094 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +053096
Tero Kristoee6c7502013-07-18 17:18:33 +030097 prm: prm@4ae06000 {
98 compatible = "ti,dra7-prm";
99 reg = <0x4ae06000 0x3000>;
Nishanth Menon5081ce62014-08-22 09:03:50 -0500100 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
Tero Kristoee6c7502013-07-18 17:18:33 +0300101
102 prm_clocks: clocks {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 };
106
107 prm_clockdomains: clockdomains {
108 };
109 };
110
Kishon Vijay Abraham I18dcd792014-07-14 16:12:23 +0530111 axi@0 {
112 compatible = "simple-bus";
113 #size-cells = <1>;
114 #address-cells = <1>;
115 ranges = <0x51000000 0x51000000 0x3000
116 0x0 0x20000000 0x10000000>;
117 pcie@51000000 {
118 compatible = "ti,dra7-pcie";
119 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
120 reg-names = "rc_dbics", "ti_conf", "config";
121 interrupts = <0 232 0x4>, <0 233 0x4>;
122 #address-cells = <3>;
123 #size-cells = <2>;
124 device_type = "pci";
125 ranges = <0x81000000 0 0 0x03000 0 0x00010000
126 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
127 #interrupt-cells = <1>;
128 num-lanes = <1>;
129 ti,hwmods = "pcie1";
130 phys = <&pcie1_phy>;
131 phy-names = "pcie-phy0";
132 interrupt-map-mask = <0 0 0 7>;
133 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
134 <0 0 0 2 &pcie1_intc 2>,
135 <0 0 0 3 &pcie1_intc 3>,
136 <0 0 0 4 &pcie1_intc 4>;
137 pcie1_intc: interrupt-controller {
138 interrupt-controller;
139 #address-cells = <0>;
140 #interrupt-cells = <1>;
141 };
142 };
143 };
144
145 axi@1 {
146 compatible = "simple-bus";
147 #size-cells = <1>;
148 #address-cells = <1>;
149 ranges = <0x51800000 0x51800000 0x3000
150 0x0 0x30000000 0x10000000>;
151 status = "disabled";
152 pcie@51000000 {
153 compatible = "ti,dra7-pcie";
154 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
155 reg-names = "rc_dbics", "ti_conf", "config";
156 interrupts = <0 355 0x4>, <0 356 0x4>;
157 #address-cells = <3>;
158 #size-cells = <2>;
159 device_type = "pci";
160 ranges = <0x81000000 0 0 0x03000 0 0x00010000
161 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
162 #interrupt-cells = <1>;
163 num-lanes = <1>;
164 ti,hwmods = "pcie2";
165 phys = <&pcie2_phy>;
166 phy-names = "pcie-phy0";
167 interrupt-map-mask = <0 0 0 7>;
168 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
169 <0 0 0 2 &pcie2_intc 2>,
170 <0 0 0 3 &pcie2_intc 3>,
171 <0 0 0 4 &pcie2_intc 4>;
172 pcie2_intc: interrupt-controller {
173 interrupt-controller;
174 #address-cells = <0>;
175 #interrupt-cells = <1>;
176 };
177 };
178 };
179
Tero Kristoee6c7502013-07-18 17:18:33 +0300180 cm_core_aon: cm_core_aon@4a005000 {
181 compatible = "ti,dra7-cm-core-aon";
182 reg = <0x4a005000 0x2000>;
183
184 cm_core_aon_clocks: clocks {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188
189 cm_core_aon_clockdomains: clockdomains {
190 };
191 };
192
193 cm_core: cm_core@4a008000 {
194 compatible = "ti,dra7-cm-core";
195 reg = <0x4a008000 0x3000>;
196
197 cm_core_clocks: clocks {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 };
201
202 cm_core_clockdomains: clockdomains {
203 };
204 };
205
R Sricharan6e58b8f2013-08-14 19:08:20 +0530206 counter32k: counter@4ae04000 {
207 compatible = "ti,omap-counter32k";
208 reg = <0x4ae04000 0x40>;
209 ti,hwmods = "counter_32k";
210 };
211
Roger Quadrosae3c0f72014-09-03 17:21:45 +0300212 dra7_ctrl_core: ctrl_core@4a002000 {
213 compatible = "syscon";
214 reg = <0x4a002000 0x6d0>;
215 };
216
Balaji T Kcd042fe2014-02-19 20:26:40 +0530217 dra7_ctrl_general: tisyscon@4a002e00 {
218 compatible = "syscon";
219 reg = <0x4a002e00 0x7c>;
220 };
221
222 pbias_regulator: pbias_regulator {
223 compatible = "ti,pbias-omap";
224 reg = <0 0x4>;
225 syscon = <&dra7_ctrl_general>;
226 pbias_mmc_reg: pbias_mmc_omap5 {
227 regulator-name = "pbias_mmc_omap5";
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <3000000>;
230 };
231 };
232
R Sricharan6e58b8f2013-08-14 19:08:20 +0530233 dra7_pmx_core: pinmux@4a003400 {
Nishanth Menon817c0372014-05-22 23:47:46 -0500234 compatible = "ti,dra7-padconf", "pinctrl-single";
R Sricharan6e58b8f2013-08-14 19:08:20 +0530235 reg = <0x4a003400 0x0464>;
236 #address-cells = <1>;
237 #size-cells = <0>;
Nishanth Menon817c0372014-05-22 23:47:46 -0500238 #interrupt-cells = <1>;
239 interrupt-controller;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530240 pinctrl-single,register-width = <32>;
241 pinctrl-single,function-mask = <0x3fffffff>;
242 };
243
244 sdma: dma-controller@4a056000 {
245 compatible = "ti,omap4430-sdma";
246 reg = <0x4a056000 0x1000>;
R Sricharana46631c2014-06-26 12:55:31 +0530247 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530251 #dma-cells = <1>;
252 #dma-channels = <32>;
253 #dma-requests = <127>;
254 };
255
256 gpio1: gpio@4ae10000 {
257 compatible = "ti,omap4-gpio";
258 reg = <0x4ae10000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +0530259 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530260 ti,hwmods = "gpio1";
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
Nishanth Menone49d5192014-08-25 16:15:34 -0700264 #interrupt-cells = <2>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530265 };
266
267 gpio2: gpio@48055000 {
268 compatible = "ti,omap4-gpio";
269 reg = <0x48055000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +0530270 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530271 ti,hwmods = "gpio2";
272 gpio-controller;
273 #gpio-cells = <2>;
274 interrupt-controller;
Nishanth Menone49d5192014-08-25 16:15:34 -0700275 #interrupt-cells = <2>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530276 };
277
278 gpio3: gpio@48057000 {
279 compatible = "ti,omap4-gpio";
280 reg = <0x48057000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +0530281 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530282 ti,hwmods = "gpio3";
283 gpio-controller;
284 #gpio-cells = <2>;
285 interrupt-controller;
Nishanth Menone49d5192014-08-25 16:15:34 -0700286 #interrupt-cells = <2>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530287 };
288
289 gpio4: gpio@48059000 {
290 compatible = "ti,omap4-gpio";
291 reg = <0x48059000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +0530292 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530293 ti,hwmods = "gpio4";
294 gpio-controller;
295 #gpio-cells = <2>;
296 interrupt-controller;
Nishanth Menone49d5192014-08-25 16:15:34 -0700297 #interrupt-cells = <2>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530298 };
299
300 gpio5: gpio@4805b000 {
301 compatible = "ti,omap4-gpio";
302 reg = <0x4805b000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +0530303 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530304 ti,hwmods = "gpio5";
305 gpio-controller;
306 #gpio-cells = <2>;
307 interrupt-controller;
Nishanth Menone49d5192014-08-25 16:15:34 -0700308 #interrupt-cells = <2>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530309 };
310
311 gpio6: gpio@4805d000 {
312 compatible = "ti,omap4-gpio";
313 reg = <0x4805d000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +0530314 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530315 ti,hwmods = "gpio6";
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
Nishanth Menone49d5192014-08-25 16:15:34 -0700319 #interrupt-cells = <2>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530320 };
321
322 gpio7: gpio@48051000 {
323 compatible = "ti,omap4-gpio";
324 reg = <0x48051000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +0530325 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530326 ti,hwmods = "gpio7";
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
Nishanth Menone49d5192014-08-25 16:15:34 -0700330 #interrupt-cells = <2>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530331 };
332
333 gpio8: gpio@48053000 {
334 compatible = "ti,omap4-gpio";
335 reg = <0x48053000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +0530336 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530337 ti,hwmods = "gpio8";
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
Nishanth Menone49d5192014-08-25 16:15:34 -0700341 #interrupt-cells = <2>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530342 };
343
344 uart1: serial@4806a000 {
345 compatible = "ti,omap4-uart";
346 reg = <0x4806a000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500347 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530348 ti,hwmods = "uart1";
349 clock-frequency = <48000000>;
350 status = "disabled";
Sebastian Andrzej Siewiorf0199a22014-09-29 20:06:47 +0200351 dmas = <&sdma 49>, <&sdma 50>;
352 dma-names = "tx", "rx";
R Sricharan6e58b8f2013-08-14 19:08:20 +0530353 };
354
355 uart2: serial@4806c000 {
356 compatible = "ti,omap4-uart";
357 reg = <0x4806c000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500358 interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530359 ti,hwmods = "uart2";
360 clock-frequency = <48000000>;
361 status = "disabled";
Sebastian Andrzej Siewiorf0199a22014-09-29 20:06:47 +0200362 dmas = <&sdma 51>, <&sdma 52>;
363 dma-names = "tx", "rx";
R Sricharan6e58b8f2013-08-14 19:08:20 +0530364 };
365
366 uart3: serial@48020000 {
367 compatible = "ti,omap4-uart";
368 reg = <0x48020000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500369 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530370 ti,hwmods = "uart3";
371 clock-frequency = <48000000>;
372 status = "disabled";
Sebastian Andrzej Siewiorf0199a22014-09-29 20:06:47 +0200373 dmas = <&sdma 53>, <&sdma 54>;
374 dma-names = "tx", "rx";
R Sricharan6e58b8f2013-08-14 19:08:20 +0530375 };
376
377 uart4: serial@4806e000 {
378 compatible = "ti,omap4-uart";
379 reg = <0x4806e000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500380 interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530381 ti,hwmods = "uart4";
382 clock-frequency = <48000000>;
383 status = "disabled";
Sebastian Andrzej Siewiorf0199a22014-09-29 20:06:47 +0200384 dmas = <&sdma 55>, <&sdma 56>;
385 dma-names = "tx", "rx";
R Sricharan6e58b8f2013-08-14 19:08:20 +0530386 };
387
388 uart5: serial@48066000 {
389 compatible = "ti,omap4-uart";
390 reg = <0x48066000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500391 interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530392 ti,hwmods = "uart5";
393 clock-frequency = <48000000>;
394 status = "disabled";
Sebastian Andrzej Siewiorf0199a22014-09-29 20:06:47 +0200395 dmas = <&sdma 63>, <&sdma 64>;
396 dma-names = "tx", "rx";
R Sricharan6e58b8f2013-08-14 19:08:20 +0530397 };
398
399 uart6: serial@48068000 {
400 compatible = "ti,omap4-uart";
401 reg = <0x48068000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500402 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530403 ti,hwmods = "uart6";
404 clock-frequency = <48000000>;
405 status = "disabled";
Sebastian Andrzej Siewiorf0199a22014-09-29 20:06:47 +0200406 dmas = <&sdma 79>, <&sdma 80>;
407 dma-names = "tx", "rx";
R Sricharan6e58b8f2013-08-14 19:08:20 +0530408 };
409
410 uart7: serial@48420000 {
411 compatible = "ti,omap4-uart";
412 reg = <0x48420000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500413 interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530414 ti,hwmods = "uart7";
415 clock-frequency = <48000000>;
416 status = "disabled";
417 };
418
419 uart8: serial@48422000 {
420 compatible = "ti,omap4-uart";
421 reg = <0x48422000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500422 interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530423 ti,hwmods = "uart8";
424 clock-frequency = <48000000>;
425 status = "disabled";
426 };
427
428 uart9: serial@48424000 {
429 compatible = "ti,omap4-uart";
430 reg = <0x48424000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500431 interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530432 ti,hwmods = "uart9";
433 clock-frequency = <48000000>;
434 status = "disabled";
435 };
436
437 uart10: serial@4ae2b000 {
438 compatible = "ti,omap4-uart";
439 reg = <0x4ae2b000 0x100>;
Nishanth Menone2265ab2014-05-23 00:04:02 -0500440 interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530441 ti,hwmods = "uart10";
442 clock-frequency = <48000000>;
443 status = "disabled";
444 };
445
Suman Anna38baefb2014-07-11 16:44:38 -0500446 mailbox1: mailbox@4a0f4000 {
447 compatible = "ti,omap4-mailbox";
448 reg = <0x4a0f4000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600449 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500452 ti,hwmods = "mailbox1";
Suman Anna24df0452014-11-03 17:07:35 -0600453 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500454 ti,mbox-num-users = <3>;
455 ti,mbox-num-fifos = <8>;
456 status = "disabled";
457 };
458
459 mailbox2: mailbox@4883a000 {
460 compatible = "ti,omap4-mailbox";
461 reg = <0x4883a000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600462 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500466 ti,hwmods = "mailbox2";
Suman Anna24df0452014-11-03 17:07:35 -0600467 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500468 ti,mbox-num-users = <4>;
469 ti,mbox-num-fifos = <12>;
470 status = "disabled";
471 };
472
473 mailbox3: mailbox@4883c000 {
474 compatible = "ti,omap4-mailbox";
475 reg = <0x4883c000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600476 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500480 ti,hwmods = "mailbox3";
Suman Anna24df0452014-11-03 17:07:35 -0600481 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500482 ti,mbox-num-users = <4>;
483 ti,mbox-num-fifos = <12>;
484 status = "disabled";
485 };
486
487 mailbox4: mailbox@4883e000 {
488 compatible = "ti,omap4-mailbox";
489 reg = <0x4883e000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600490 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500494 ti,hwmods = "mailbox4";
Suman Anna24df0452014-11-03 17:07:35 -0600495 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500496 ti,mbox-num-users = <4>;
497 ti,mbox-num-fifos = <12>;
498 status = "disabled";
499 };
500
501 mailbox5: mailbox@48840000 {
502 compatible = "ti,omap4-mailbox";
503 reg = <0x48840000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600504 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500508 ti,hwmods = "mailbox5";
Suman Anna24df0452014-11-03 17:07:35 -0600509 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500510 ti,mbox-num-users = <4>;
511 ti,mbox-num-fifos = <12>;
512 status = "disabled";
513 };
514
515 mailbox6: mailbox@48842000 {
516 compatible = "ti,omap4-mailbox";
517 reg = <0x48842000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600518 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500522 ti,hwmods = "mailbox6";
Suman Anna24df0452014-11-03 17:07:35 -0600523 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500524 ti,mbox-num-users = <4>;
525 ti,mbox-num-fifos = <12>;
526 status = "disabled";
527 };
528
529 mailbox7: mailbox@48844000 {
530 compatible = "ti,omap4-mailbox";
531 reg = <0x48844000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600532 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500536 ti,hwmods = "mailbox7";
Suman Anna24df0452014-11-03 17:07:35 -0600537 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500538 ti,mbox-num-users = <4>;
539 ti,mbox-num-fifos = <12>;
540 status = "disabled";
541 };
542
543 mailbox8: mailbox@48846000 {
544 compatible = "ti,omap4-mailbox";
545 reg = <0x48846000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600546 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500550 ti,hwmods = "mailbox8";
Suman Anna24df0452014-11-03 17:07:35 -0600551 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500552 ti,mbox-num-users = <4>;
553 ti,mbox-num-fifos = <12>;
554 status = "disabled";
555 };
556
557 mailbox9: mailbox@4885e000 {
558 compatible = "ti,omap4-mailbox";
559 reg = <0x4885e000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600560 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500564 ti,hwmods = "mailbox9";
Suman Anna24df0452014-11-03 17:07:35 -0600565 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500566 ti,mbox-num-users = <4>;
567 ti,mbox-num-fifos = <12>;
568 status = "disabled";
569 };
570
571 mailbox10: mailbox@48860000 {
572 compatible = "ti,omap4-mailbox";
573 reg = <0x48860000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600574 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500578 ti,hwmods = "mailbox10";
Suman Anna24df0452014-11-03 17:07:35 -0600579 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500580 ti,mbox-num-users = <4>;
581 ti,mbox-num-fifos = <12>;
582 status = "disabled";
583 };
584
585 mailbox11: mailbox@48862000 {
586 compatible = "ti,omap4-mailbox";
587 reg = <0x48862000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600588 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500592 ti,hwmods = "mailbox11";
Suman Anna24df0452014-11-03 17:07:35 -0600593 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500594 ti,mbox-num-users = <4>;
595 ti,mbox-num-fifos = <12>;
596 status = "disabled";
597 };
598
599 mailbox12: mailbox@48864000 {
600 compatible = "ti,omap4-mailbox";
601 reg = <0x48864000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600602 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500606 ti,hwmods = "mailbox12";
Suman Anna24df0452014-11-03 17:07:35 -0600607 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500608 ti,mbox-num-users = <4>;
609 ti,mbox-num-fifos = <12>;
610 status = "disabled";
611 };
612
613 mailbox13: mailbox@48802000 {
614 compatible = "ti,omap4-mailbox";
615 reg = <0x48802000 0x200>;
Suman Annab46a6ae2014-11-03 17:07:34 -0600616 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
Suman Anna38baefb2014-07-11 16:44:38 -0500620 ti,hwmods = "mailbox13";
Suman Anna24df0452014-11-03 17:07:35 -0600621 #mbox-cells = <1>;
Suman Anna38baefb2014-07-11 16:44:38 -0500622 ti,mbox-num-users = <4>;
623 ti,mbox-num-fifos = <12>;
624 status = "disabled";
625 };
626
R Sricharan6e58b8f2013-08-14 19:08:20 +0530627 timer1: timer@4ae18000 {
628 compatible = "ti,omap5430-timer";
629 reg = <0x4ae18000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530630 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530631 ti,hwmods = "timer1";
632 ti,timer-alwon;
633 };
634
635 timer2: timer@48032000 {
636 compatible = "ti,omap5430-timer";
637 reg = <0x48032000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530638 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530639 ti,hwmods = "timer2";
640 };
641
642 timer3: timer@48034000 {
643 compatible = "ti,omap5430-timer";
644 reg = <0x48034000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530645 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530646 ti,hwmods = "timer3";
647 };
648
649 timer4: timer@48036000 {
650 compatible = "ti,omap5430-timer";
651 reg = <0x48036000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530652 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530653 ti,hwmods = "timer4";
654 };
655
656 timer5: timer@48820000 {
657 compatible = "ti,omap5430-timer";
658 reg = <0x48820000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530659 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530660 ti,hwmods = "timer5";
661 ti,timer-dsp;
662 };
663
664 timer6: timer@48822000 {
665 compatible = "ti,omap5430-timer";
666 reg = <0x48822000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530667 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530668 ti,hwmods = "timer6";
669 ti,timer-dsp;
670 ti,timer-pwm;
671 };
672
673 timer7: timer@48824000 {
674 compatible = "ti,omap5430-timer";
675 reg = <0x48824000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530676 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530677 ti,hwmods = "timer7";
678 ti,timer-dsp;
679 };
680
681 timer8: timer@48826000 {
682 compatible = "ti,omap5430-timer";
683 reg = <0x48826000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530684 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530685 ti,hwmods = "timer8";
686 ti,timer-dsp;
687 ti,timer-pwm;
688 };
689
690 timer9: timer@4803e000 {
691 compatible = "ti,omap5430-timer";
692 reg = <0x4803e000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530693 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530694 ti,hwmods = "timer9";
695 };
696
697 timer10: timer@48086000 {
698 compatible = "ti,omap5430-timer";
699 reg = <0x48086000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530700 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530701 ti,hwmods = "timer10";
702 };
703
704 timer11: timer@48088000 {
705 compatible = "ti,omap5430-timer";
706 reg = <0x48088000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530707 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530708 ti,hwmods = "timer11";
709 ti,timer-pwm;
710 };
711
712 timer13: timer@48828000 {
713 compatible = "ti,omap5430-timer";
714 reg = <0x48828000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530715 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530716 ti,hwmods = "timer13";
717 status = "disabled";
718 };
719
720 timer14: timer@4882a000 {
721 compatible = "ti,omap5430-timer";
722 reg = <0x4882a000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530723 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530724 ti,hwmods = "timer14";
725 status = "disabled";
726 };
727
728 timer15: timer@4882c000 {
729 compatible = "ti,omap5430-timer";
730 reg = <0x4882c000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530731 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530732 ti,hwmods = "timer15";
733 status = "disabled";
734 };
735
736 timer16: timer@4882e000 {
737 compatible = "ti,omap5430-timer";
738 reg = <0x4882e000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530739 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530740 ti,hwmods = "timer16";
741 status = "disabled";
742 };
743
744 wdt2: wdt@4ae14000 {
Lokesh Vutlabe668832014-11-12 10:54:15 +0530745 compatible = "ti,omap3-wdt";
R Sricharan6e58b8f2013-08-14 19:08:20 +0530746 reg = <0x4ae14000 0x80>;
R Sricharana46631c2014-06-26 12:55:31 +0530747 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530748 ti,hwmods = "wd_timer2";
749 };
750
Suman Annadbd7c192014-01-13 18:26:46 -0600751 hwspinlock: spinlock@4a0f6000 {
752 compatible = "ti,omap4-hwspinlock";
753 reg = <0x4a0f6000 0x1000>;
754 ti,hwmods = "spinlock";
755 #hwlock-cells = <1>;
756 };
757
Archit Taneja1a5fe3c2013-12-17 15:32:21 +0530758 dmm@4e000000 {
759 compatible = "ti,omap5-dmm";
760 reg = <0x4e000000 0x800>;
R Sricharana46631c2014-06-26 12:55:31 +0530761 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Archit Taneja1a5fe3c2013-12-17 15:32:21 +0530762 ti,hwmods = "dmm";
763 };
764
R Sricharan6e58b8f2013-08-14 19:08:20 +0530765 i2c1: i2c@48070000 {
766 compatible = "ti,omap4-i2c";
767 reg = <0x48070000 0x100>;
R Sricharana46631c2014-06-26 12:55:31 +0530768 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530769 #address-cells = <1>;
770 #size-cells = <0>;
771 ti,hwmods = "i2c1";
772 status = "disabled";
773 };
774
775 i2c2: i2c@48072000 {
776 compatible = "ti,omap4-i2c";
777 reg = <0x48072000 0x100>;
R Sricharana46631c2014-06-26 12:55:31 +0530778 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530779 #address-cells = <1>;
780 #size-cells = <0>;
781 ti,hwmods = "i2c2";
782 status = "disabled";
783 };
784
785 i2c3: i2c@48060000 {
786 compatible = "ti,omap4-i2c";
787 reg = <0x48060000 0x100>;
R Sricharana46631c2014-06-26 12:55:31 +0530788 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530789 #address-cells = <1>;
790 #size-cells = <0>;
791 ti,hwmods = "i2c3";
792 status = "disabled";
793 };
794
795 i2c4: i2c@4807a000 {
796 compatible = "ti,omap4-i2c";
797 reg = <0x4807a000 0x100>;
R Sricharana46631c2014-06-26 12:55:31 +0530798 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530799 #address-cells = <1>;
800 #size-cells = <0>;
801 ti,hwmods = "i2c4";
802 status = "disabled";
803 };
804
805 i2c5: i2c@4807c000 {
806 compatible = "ti,omap4-i2c";
807 reg = <0x4807c000 0x100>;
R Sricharana46631c2014-06-26 12:55:31 +0530808 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530809 #address-cells = <1>;
810 #size-cells = <0>;
811 ti,hwmods = "i2c5";
812 status = "disabled";
813 };
814
815 mmc1: mmc@4809c000 {
816 compatible = "ti,omap4-hsmmc";
817 reg = <0x4809c000 0x400>;
R Sricharana46631c2014-06-26 12:55:31 +0530818 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530819 ti,hwmods = "mmc1";
820 ti,dual-volt;
821 ti,needs-special-reset;
822 dmas = <&sdma 61>, <&sdma 62>;
823 dma-names = "tx", "rx";
824 status = "disabled";
Balaji T Kcd042fe2014-02-19 20:26:40 +0530825 pbias-supply = <&pbias_mmc_reg>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530826 };
827
828 mmc2: mmc@480b4000 {
829 compatible = "ti,omap4-hsmmc";
830 reg = <0x480b4000 0x400>;
R Sricharana46631c2014-06-26 12:55:31 +0530831 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530832 ti,hwmods = "mmc2";
833 ti,needs-special-reset;
834 dmas = <&sdma 47>, <&sdma 48>;
835 dma-names = "tx", "rx";
836 status = "disabled";
837 };
838
839 mmc3: mmc@480ad000 {
840 compatible = "ti,omap4-hsmmc";
841 reg = <0x480ad000 0x400>;
R Sricharana46631c2014-06-26 12:55:31 +0530842 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530843 ti,hwmods = "mmc3";
844 ti,needs-special-reset;
845 dmas = <&sdma 77>, <&sdma 78>;
846 dma-names = "tx", "rx";
847 status = "disabled";
848 };
849
850 mmc4: mmc@480d1000 {
851 compatible = "ti,omap4-hsmmc";
852 reg = <0x480d1000 0x400>;
R Sricharana46631c2014-06-26 12:55:31 +0530853 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530854 ti,hwmods = "mmc4";
855 ti,needs-special-reset;
856 dmas = <&sdma 57>, <&sdma 58>;
857 dma-names = "tx", "rx";
858 status = "disabled";
859 };
860
Nishanth Menona1b8ee12014-03-03 20:20:23 +0530861 abb_mpu: regulator-abb-mpu {
862 compatible = "ti,abb-v3";
863 regulator-name = "abb_mpu";
864 #address-cells = <0>;
865 #size-cells = <0>;
866 clocks = <&sys_clkin1>;
867 ti,settling-time = <50>;
868 ti,clock-cycles = <16>;
869
870 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
871 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
872 <0x4ae0c158 0x4>;
873 reg-names = "setup-address", "control-address",
874 "int-address", "efuse-address",
875 "ldo-address";
876 ti,tranxdone-status-mask = <0x80>;
877 /* LDOVBBMPU_FBB_MUX_CTRL */
878 ti,ldovbb-override-mask = <0x400>;
879 /* LDOVBBMPU_FBB_VSET_OUT */
880 ti,ldovbb-vset-mask = <0x1F>;
881
882 /*
883 * NOTE: only FBB mode used but actual vset will
884 * determine final biasing
885 */
886 ti,abb_info = <
887 /*uV ABB efuse rbb_m fbb_m vset_m*/
888 1060000 0 0x0 0 0x02000000 0x01F00000
889 1160000 0 0x4 0 0x02000000 0x01F00000
890 1210000 0 0x8 0 0x02000000 0x01F00000
891 >;
892 };
893
894 abb_ivahd: regulator-abb-ivahd {
895 compatible = "ti,abb-v3";
896 regulator-name = "abb_ivahd";
897 #address-cells = <0>;
898 #size-cells = <0>;
899 clocks = <&sys_clkin1>;
900 ti,settling-time = <50>;
901 ti,clock-cycles = <16>;
902
903 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
904 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
905 <0x4a002470 0x4>;
906 reg-names = "setup-address", "control-address",
907 "int-address", "efuse-address",
908 "ldo-address";
909 ti,tranxdone-status-mask = <0x40000000>;
910 /* LDOVBBIVA_FBB_MUX_CTRL */
911 ti,ldovbb-override-mask = <0x400>;
912 /* LDOVBBIVA_FBB_VSET_OUT */
913 ti,ldovbb-vset-mask = <0x1F>;
914
915 /*
916 * NOTE: only FBB mode used but actual vset will
917 * determine final biasing
918 */
919 ti,abb_info = <
920 /*uV ABB efuse rbb_m fbb_m vset_m*/
921 1055000 0 0x0 0 0x02000000 0x01F00000
922 1150000 0 0x4 0 0x02000000 0x01F00000
923 1250000 0 0x8 0 0x02000000 0x01F00000
924 >;
925 };
926
927 abb_dspeve: regulator-abb-dspeve {
928 compatible = "ti,abb-v3";
929 regulator-name = "abb_dspeve";
930 #address-cells = <0>;
931 #size-cells = <0>;
932 clocks = <&sys_clkin1>;
933 ti,settling-time = <50>;
934 ti,clock-cycles = <16>;
935
936 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
937 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
938 <0x4a00246c 0x4>;
939 reg-names = "setup-address", "control-address",
940 "int-address", "efuse-address",
941 "ldo-address";
942 ti,tranxdone-status-mask = <0x20000000>;
943 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
944 ti,ldovbb-override-mask = <0x400>;
945 /* LDOVBBDSPEVE_FBB_VSET_OUT */
946 ti,ldovbb-vset-mask = <0x1F>;
947
948 /*
949 * NOTE: only FBB mode used but actual vset will
950 * determine final biasing
951 */
952 ti,abb_info = <
953 /*uV ABB efuse rbb_m fbb_m vset_m*/
954 1055000 0 0x0 0 0x02000000 0x01F00000
955 1150000 0 0x4 0 0x02000000 0x01F00000
956 1250000 0 0x8 0 0x02000000 0x01F00000
957 >;
958 };
959
960 abb_gpu: regulator-abb-gpu {
961 compatible = "ti,abb-v3";
962 regulator-name = "abb_gpu";
963 #address-cells = <0>;
964 #size-cells = <0>;
965 clocks = <&sys_clkin1>;
966 ti,settling-time = <50>;
967 ti,clock-cycles = <16>;
968
969 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
970 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
971 <0x4ae0c154 0x4>;
972 reg-names = "setup-address", "control-address",
973 "int-address", "efuse-address",
974 "ldo-address";
975 ti,tranxdone-status-mask = <0x10000000>;
976 /* LDOVBBGPU_FBB_MUX_CTRL */
977 ti,ldovbb-override-mask = <0x400>;
978 /* LDOVBBGPU_FBB_VSET_OUT */
979 ti,ldovbb-vset-mask = <0x1F>;
980
981 /*
982 * NOTE: only FBB mode used but actual vset will
983 * determine final biasing
984 */
985 ti,abb_info = <
986 /*uV ABB efuse rbb_m fbb_m vset_m*/
987 1090000 0 0x0 0 0x02000000 0x01F00000
988 1210000 0 0x4 0 0x02000000 0x01F00000
989 1280000 0 0x8 0 0x02000000 0x01F00000
990 >;
991 };
992
R Sricharan6e58b8f2013-08-14 19:08:20 +0530993 mcspi1: spi@48098000 {
994 compatible = "ti,omap4-mcspi";
995 reg = <0x48098000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +0530996 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530997 #address-cells = <1>;
998 #size-cells = <0>;
999 ti,hwmods = "mcspi1";
1000 ti,spi-num-cs = <4>;
1001 dmas = <&sdma 35>,
1002 <&sdma 36>,
1003 <&sdma 37>,
1004 <&sdma 38>,
1005 <&sdma 39>,
1006 <&sdma 40>,
1007 <&sdma 41>,
1008 <&sdma 42>;
1009 dma-names = "tx0", "rx0", "tx1", "rx1",
1010 "tx2", "rx2", "tx3", "rx3";
1011 status = "disabled";
1012 };
1013
1014 mcspi2: spi@4809a000 {
1015 compatible = "ti,omap4-mcspi";
1016 reg = <0x4809a000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +05301017 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +05301018 #address-cells = <1>;
1019 #size-cells = <0>;
1020 ti,hwmods = "mcspi2";
1021 ti,spi-num-cs = <2>;
1022 dmas = <&sdma 43>,
1023 <&sdma 44>,
1024 <&sdma 45>,
1025 <&sdma 46>;
1026 dma-names = "tx0", "rx0", "tx1", "rx1";
1027 status = "disabled";
1028 };
1029
1030 mcspi3: spi@480b8000 {
1031 compatible = "ti,omap4-mcspi";
1032 reg = <0x480b8000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +05301033 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +05301034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 ti,hwmods = "mcspi3";
1037 ti,spi-num-cs = <2>;
1038 dmas = <&sdma 15>, <&sdma 16>;
1039 dma-names = "tx0", "rx0";
1040 status = "disabled";
1041 };
1042
1043 mcspi4: spi@480ba000 {
1044 compatible = "ti,omap4-mcspi";
1045 reg = <0x480ba000 0x200>;
R Sricharana46631c2014-06-26 12:55:31 +05301046 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
R Sricharan6e58b8f2013-08-14 19:08:20 +05301047 #address-cells = <1>;
1048 #size-cells = <0>;
1049 ti,hwmods = "mcspi4";
1050 ti,spi-num-cs = <1>;
1051 dmas = <&sdma 70>, <&sdma 71>;
1052 dma-names = "tx0", "rx0";
1053 status = "disabled";
1054 };
Sourav Poddardc2dd5b2014-05-06 16:37:24 +05301055
1056 qspi: qspi@4b300000 {
1057 compatible = "ti,dra7xxx-qspi";
1058 reg = <0x4b300000 0x100>;
1059 reg-names = "qspi_base";
1060 #address-cells = <1>;
1061 #size-cells = <0>;
1062 ti,hwmods = "qspi";
1063 clocks = <&qspi_gfclk_div>;
1064 clock-names = "fck";
1065 num-cs = <4>;
R Sricharana46631c2014-06-26 12:55:31 +05301066 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
Sourav Poddardc2dd5b2014-05-06 16:37:24 +05301067 status = "disabled";
1068 };
Balaji T K7be80562014-05-07 14:58:58 +03001069
1070 omap_control_sata: control-phy@4a002374 {
1071 compatible = "ti,control-phy-pipe3";
1072 reg = <0x4a002374 0x4>;
1073 reg-names = "power";
1074 clocks = <&sys_clkin1>;
1075 clock-names = "sysclk";
1076 };
1077
1078 /* OCP2SCP3 */
1079 ocp2scp@4a090000 {
1080 compatible = "ti,omap-ocp2scp";
1081 #address-cells = <1>;
1082 #size-cells = <1>;
1083 ranges;
1084 reg = <0x4a090000 0x20>;
1085 ti,hwmods = "ocp2scp3";
1086 sata_phy: phy@4A096000 {
1087 compatible = "ti,phy-pipe3-sata";
1088 reg = <0x4A096000 0x80>, /* phy_rx */
1089 <0x4A096400 0x64>, /* phy_tx */
1090 <0x4A096800 0x40>; /* pll_ctrl */
1091 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1092 ctrl-module = <&omap_control_sata>;
1093 clocks = <&sys_clkin1>;
1094 clock-names = "sysclk";
1095 #phy-cells = <0>;
1096 };
Kishon Vijay Abraham I692df0e2014-07-14 16:12:22 +05301097
1098 pcie1_phy: pciephy@4a094000 {
1099 compatible = "ti,phy-pipe3-pcie";
1100 reg = <0x4a094000 0x80>, /* phy_rx */
1101 <0x4a094400 0x64>; /* phy_tx */
1102 reg-names = "phy_rx", "phy_tx";
1103 ctrl-module = <&omap_control_pcie1phy>;
1104 clocks = <&dpll_pcie_ref_ck>,
1105 <&dpll_pcie_ref_m2ldo_ck>,
1106 <&optfclk_pciephy1_32khz>,
1107 <&optfclk_pciephy1_clk>,
1108 <&optfclk_pciephy1_div_clk>,
1109 <&optfclk_pciephy_div>;
1110 clock-names = "dpll_ref", "dpll_ref_m2",
1111 "wkupclk", "refclk",
1112 "div-clk", "phy-div";
1113 #phy-cells = <0>;
Kishon Vijay Abraham I692df0e2014-07-14 16:12:22 +05301114 ti,hwmods = "pcie1-phy";
1115 };
1116
1117 pcie2_phy: pciephy@4a095000 {
1118 compatible = "ti,phy-pipe3-pcie";
1119 reg = <0x4a095000 0x80>, /* phy_rx */
1120 <0x4a095400 0x64>; /* phy_tx */
1121 reg-names = "phy_rx", "phy_tx";
1122 ctrl-module = <&omap_control_pcie2phy>;
1123 clocks = <&dpll_pcie_ref_ck>,
1124 <&dpll_pcie_ref_m2ldo_ck>,
1125 <&optfclk_pciephy2_32khz>,
1126 <&optfclk_pciephy2_clk>,
1127 <&optfclk_pciephy2_div_clk>,
1128 <&optfclk_pciephy_div>;
1129 clock-names = "dpll_ref", "dpll_ref_m2",
1130 "wkupclk", "refclk",
1131 "div-clk", "phy-div";
1132 #phy-cells = <0>;
1133 ti,hwmods = "pcie2-phy";
Kishon Vijay Abraham I692df0e2014-07-14 16:12:22 +05301134 status = "disabled";
1135 };
Balaji T K7be80562014-05-07 14:58:58 +03001136 };
1137
1138 sata: sata@4a141100 {
1139 compatible = "snps,dwc-ahci";
1140 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
R Sricharana46631c2014-06-26 12:55:31 +05301141 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
Balaji T K7be80562014-05-07 14:58:58 +03001142 phys = <&sata_phy>;
1143 phy-names = "sata-phy";
1144 clocks = <&sata_ref_clk>;
1145 ti,hwmods = "sata";
1146 };
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001147
Kishon Vijay Abraham Id1ff66b2014-07-14 16:12:21 +05301148 omap_control_pcie1phy: control-phy@0x4a003c40 {
1149 compatible = "ti,control-phy-pcie";
1150 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1151 reg-names = "power", "control_sma", "pcie_pcs";
1152 clocks = <&sys_clkin1>;
1153 clock-names = "sysclk";
1154 };
1155
1156 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1157 compatible = "ti,control-phy-pcie";
1158 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1159 reg-names = "power", "control_sma", "pcie_pcs";
1160 clocks = <&sys_clkin1>;
1161 clock-names = "sysclk";
1162 status = "disabled";
1163 };
1164
Lokesh Vutlabc078312014-11-19 17:53:08 +05301165 rtc@48838000 {
1166 compatible = "ti,am3352-rtc";
1167 reg = <0x48838000 0x100>;
1168 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1170 ti,hwmods = "rtcss";
1171 clocks = <&sys_32k_ck>;
1172 };
1173
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001174 omap_control_usb2phy1: control-phy@4a002300 {
1175 compatible = "ti,control-phy-usb2";
1176 reg = <0x4a002300 0x4>;
1177 reg-names = "power";
1178 };
1179
1180 omap_control_usb3phy1: control-phy@4a002370 {
1181 compatible = "ti,control-phy-pipe3";
1182 reg = <0x4a002370 0x4>;
1183 reg-names = "power";
1184 };
1185
1186 omap_control_usb2phy2: control-phy@0x4a002e74 {
1187 compatible = "ti,control-phy-usb2-dra7";
1188 reg = <0x4a002e74 0x4>;
1189 reg-names = "power";
1190 };
1191
1192 /* OCP2SCP1 */
1193 ocp2scp@4a080000 {
1194 compatible = "ti,omap-ocp2scp";
1195 #address-cells = <1>;
1196 #size-cells = <1>;
1197 ranges;
1198 reg = <0x4a080000 0x20>;
1199 ti,hwmods = "ocp2scp1";
1200
1201 usb2_phy1: phy@4a084000 {
1202 compatible = "ti,omap-usb2";
1203 reg = <0x4a084000 0x400>;
1204 ctrl-module = <&omap_control_usb2phy1>;
1205 clocks = <&usb_phy1_always_on_clk32k>,
1206 <&usb_otg_ss1_refclk960m>;
1207 clock-names = "wkupclk",
1208 "refclk";
1209 #phy-cells = <0>;
1210 };
1211
1212 usb2_phy2: phy@4a085000 {
1213 compatible = "ti,omap-usb2";
1214 reg = <0x4a085000 0x400>;
1215 ctrl-module = <&omap_control_usb2phy2>;
1216 clocks = <&usb_phy2_always_on_clk32k>,
1217 <&usb_otg_ss2_refclk960m>;
1218 clock-names = "wkupclk",
1219 "refclk";
1220 #phy-cells = <0>;
1221 };
1222
1223 usb3_phy1: phy@4a084400 {
1224 compatible = "ti,omap-usb3";
1225 reg = <0x4a084400 0x80>,
1226 <0x4a084800 0x64>,
1227 <0x4a084c00 0x40>;
1228 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1229 ctrl-module = <&omap_control_usb3phy1>;
1230 clocks = <&usb_phy3_always_on_clk32k>,
1231 <&sys_clkin1>,
1232 <&usb_otg_ss1_refclk960m>;
1233 clock-names = "wkupclk",
1234 "sysclk",
1235 "refclk";
1236 #phy-cells = <0>;
1237 };
1238 };
1239
Felipe Balbi4f6dec72014-11-03 10:28:42 -06001240 omap_dwc3_1: omap_dwc3_1@48880000 {
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001241 compatible = "ti,dwc3";
1242 ti,hwmods = "usb_otg_ss1";
1243 reg = <0x48880000 0x10000>;
R Sricharana46631c2014-06-26 12:55:31 +05301244 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001245 #address-cells = <1>;
1246 #size-cells = <1>;
1247 utmi-mode = <2>;
1248 ranges;
1249 usb1: usb@48890000 {
1250 compatible = "snps,dwc3";
1251 reg = <0x48890000 0x17000>;
R Sricharana46631c2014-06-26 12:55:31 +05301252 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001253 phys = <&usb2_phy1>, <&usb3_phy1>;
1254 phy-names = "usb2-phy", "usb3-phy";
1255 tx-fifo-resize;
1256 maximum-speed = "super-speed";
1257 dr_mode = "otg";
Felipe Balbi8c606732015-01-15 09:38:03 -06001258 snps,dis_u3_susphy_quirk;
1259 snps,dis_u2_susphy_quirk;
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001260 };
1261 };
1262
Felipe Balbi4f6dec72014-11-03 10:28:42 -06001263 omap_dwc3_2: omap_dwc3_2@488c0000 {
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001264 compatible = "ti,dwc3";
1265 ti,hwmods = "usb_otg_ss2";
1266 reg = <0x488c0000 0x10000>;
R Sricharana46631c2014-06-26 12:55:31 +05301267 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001268 #address-cells = <1>;
1269 #size-cells = <1>;
1270 utmi-mode = <2>;
1271 ranges;
1272 usb2: usb@488d0000 {
1273 compatible = "snps,dwc3";
1274 reg = <0x488d0000 0x17000>;
R Sricharana46631c2014-06-26 12:55:31 +05301275 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001276 phys = <&usb2_phy2>;
1277 phy-names = "usb2-phy";
1278 tx-fifo-resize;
1279 maximum-speed = "high-speed";
1280 dr_mode = "otg";
Felipe Balbi8c606732015-01-15 09:38:03 -06001281 snps,dis_u3_susphy_quirk;
1282 snps,dis_u2_susphy_quirk;
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001283 };
1284 };
1285
1286 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
Felipe Balbi4f6dec72014-11-03 10:28:42 -06001287 omap_dwc3_3: omap_dwc3_3@48900000 {
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001288 compatible = "ti,dwc3";
1289 ti,hwmods = "usb_otg_ss3";
1290 reg = <0x48900000 0x10000>;
R Sricharana46631c2014-06-26 12:55:31 +05301291 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001292 #address-cells = <1>;
1293 #size-cells = <1>;
1294 utmi-mode = <2>;
1295 ranges;
1296 status = "disabled";
1297 usb3: usb@48910000 {
1298 compatible = "snps,dwc3";
1299 reg = <0x48910000 0x17000>;
R Sricharana46631c2014-06-26 12:55:31 +05301300 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001301 tx-fifo-resize;
1302 maximum-speed = "high-speed";
1303 dr_mode = "otg";
Felipe Balbi8c606732015-01-15 09:38:03 -06001304 snps,dis_u3_susphy_quirk;
1305 snps,dis_u2_susphy_quirk;
Roger Quadrosfbf3e552014-05-05 12:54:45 +03001306 };
1307 };
1308
Minal Shahff66a3c2014-05-19 14:45:47 +05301309 elm: elm@48078000 {
1310 compatible = "ti,am3352-elm";
1311 reg = <0x48078000 0xfc0>; /* device IO registers */
R Sricharana46631c2014-06-26 12:55:31 +05301312 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
Minal Shahff66a3c2014-05-19 14:45:47 +05301313 ti,hwmods = "elm";
1314 status = "disabled";
1315 };
1316
1317 gpmc: gpmc@50000000 {
1318 compatible = "ti,am3352-gpmc";
1319 ti,hwmods = "gpmc";
1320 reg = <0x50000000 0x37c>; /* device IO registers */
R Sricharana46631c2014-06-26 12:55:31 +05301321 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
Minal Shahff66a3c2014-05-19 14:45:47 +05301322 gpmc,num-cs = <8>;
1323 gpmc,num-waitpins = <2>;
1324 #address-cells = <2>;
1325 #size-cells = <1>;
1326 status = "disabled";
1327 };
Peter Ujfalusi2ca09452014-05-07 13:20:48 +03001328
1329 atl: atl@4843c000 {
1330 compatible = "ti,dra7-atl";
1331 reg = <0x4843c000 0x3ff>;
1332 ti,hwmods = "atl";
1333 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1334 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1335 clocks = <&atl_gfclk_mux>;
1336 clock-names = "fck";
1337 status = "disabled";
1338 };
Olof Johansson412a9bb2014-07-18 22:16:15 -07001339
R Sricharana46631c2014-06-26 12:55:31 +05301340 crossbar_mpu: crossbar@4a020000 {
1341 compatible = "ti,irq-crossbar";
1342 reg = <0x4a002a48 0x130>;
1343 ti,max-irqs = <160>;
1344 ti,max-crossbar-sources = <MAX_SOURCES>;
1345 ti,reg-size = <2>;
1346 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1347 ti,irqs-skip = <10 133 139 140>;
1348 ti,irqs-safe-map = <0>;
1349 };
Mugunthan V Nef9c5b62014-10-21 15:31:00 +05301350
1351 mac: ethernet@4a100000 {
1352 compatible = "ti,cpsw";
1353 ti,hwmods = "gmac";
1354 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1355 clock-names = "fck", "cpts";
1356 cpdma_channels = <8>;
1357 ale_entries = <1024>;
1358 bd_ram_size = <0x2000>;
1359 no_bd_ram = <0>;
1360 rx_descs = <64>;
1361 mac_control = <0x20>;
1362 slaves = <2>;
1363 active_slave = <0>;
1364 cpts_clock_mult = <0x80000000>;
1365 cpts_clock_shift = <29>;
1366 reg = <0x48484000 0x1000
1367 0x48485200 0x2E00>;
1368 #address-cells = <1>;
1369 #size-cells = <1>;
1370 /*
1371 * rx_thresh_pend
1372 * rx_pend
1373 * tx_pend
1374 * misc_pend
1375 */
1376 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1380 ranges;
1381 status = "disabled";
1382
1383 davinci_mdio: mdio@48485000 {
1384 compatible = "ti,davinci_mdio";
1385 #address-cells = <1>;
1386 #size-cells = <0>;
1387 ti,hwmods = "davinci_mdio";
1388 bus_freq = <1000000>;
1389 reg = <0x48485000 0x100>;
1390 };
1391
1392 cpsw_emac0: slave@48480200 {
1393 /* Filled in by U-Boot */
1394 mac-address = [ 00 00 00 00 00 00 ];
1395 };
1396
1397 cpsw_emac1: slave@48480300 {
1398 /* Filled in by U-Boot */
1399 mac-address = [ 00 00 00 00 00 00 ];
1400 };
1401
1402 phy_sel: cpsw-phy-sel@4a002554 {
1403 compatible = "ti,dra7xx-cpsw-phy-sel";
1404 reg= <0x4a002554 0x4>;
1405 reg-names = "gmii-sel";
1406 };
1407 };
1408
Roger Quadros9ec49b92014-08-15 16:08:36 +03001409 dcan1: can@481cc000 {
1410 compatible = "ti,dra7-d_can";
1411 ti,hwmods = "dcan1";
1412 reg = <0x4ae3c000 0x2000>;
1413 syscon-raminit = <&dra7_ctrl_core 0x558 0>;
1414 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&dcan1_sys_clk_mux>;
1416 status = "disabled";
1417 };
1418
1419 dcan2: can@481d0000 {
1420 compatible = "ti,dra7-d_can";
1421 ti,hwmods = "dcan2";
1422 reg = <0x48480000 0x2000>;
1423 syscon-raminit = <&dra7_ctrl_core 0x558 1>;
1424 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&sys_clkin1>;
1426 status = "disabled";
1427 };
R Sricharan6e58b8f2013-08-14 19:08:20 +05301428 };
1429};
Tero Kristoee6c7502013-07-18 17:18:33 +03001430
1431/include/ "dra7xx-clocks.dtsi"