Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 1 | #include <linux/delay.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | #include <linux/pci.h> |
| 3 | #include <linux/module.h> |
Al Viro | f6a5703 | 2006-10-18 01:47:25 -0400 | [diff] [blame] | 4 | #include <linux/sched.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 5 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | #include <linux/ioport.h> |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 7 | #include <linux/wait.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | |
Adrian Bunk | 48b1914 | 2005-11-06 01:45:08 +0100 | [diff] [blame] | 9 | #include "pci.h" |
| 10 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | /* |
| 12 | * This interrupt-safe spinlock protects all accesses to PCI |
| 13 | * configuration space. |
| 14 | */ |
| 15 | |
Jan Kiszka | a2e2778 | 2011-11-04 09:46:00 +0100 | [diff] [blame] | 16 | DEFINE_RAW_SPINLOCK(pci_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | |
| 18 | /* |
| 19 | * Wrappers for all PCI configuration access functions. They just check |
| 20 | * alignment, do locking and call the low-level functions pointed to |
| 21 | * by pci_dev->ops. |
| 22 | */ |
| 23 | |
| 24 | #define PCI_byte_BAD 0 |
| 25 | #define PCI_word_BAD (pos & 1) |
| 26 | #define PCI_dword_BAD (pos & 3) |
| 27 | |
Bogicevic Sasa | ff3ce48 | 2015-12-27 13:21:11 -0800 | [diff] [blame] | 28 | #define PCI_OP_READ(size, type, len) \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | int pci_bus_read_config_##size \ |
| 30 | (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ |
| 31 | { \ |
| 32 | int res; \ |
| 33 | unsigned long flags; \ |
| 34 | u32 data = 0; \ |
| 35 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 36 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | res = bus->ops->read(bus, devfn, pos, len, &data); \ |
| 38 | *value = (type)data; \ |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 39 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | return res; \ |
| 41 | } |
| 42 | |
Bogicevic Sasa | ff3ce48 | 2015-12-27 13:21:11 -0800 | [diff] [blame] | 43 | #define PCI_OP_WRITE(size, type, len) \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | int pci_bus_write_config_##size \ |
| 45 | (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ |
| 46 | { \ |
| 47 | int res; \ |
| 48 | unsigned long flags; \ |
| 49 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 50 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | res = bus->ops->write(bus, devfn, pos, len, value); \ |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 52 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | return res; \ |
| 54 | } |
| 55 | |
| 56 | PCI_OP_READ(byte, u8, 1) |
| 57 | PCI_OP_READ(word, u16, 2) |
| 58 | PCI_OP_READ(dword, u32, 4) |
| 59 | PCI_OP_WRITE(byte, u8, 1) |
| 60 | PCI_OP_WRITE(word, u16, 2) |
| 61 | PCI_OP_WRITE(dword, u32, 4) |
| 62 | |
| 63 | EXPORT_SYMBOL(pci_bus_read_config_byte); |
| 64 | EXPORT_SYMBOL(pci_bus_read_config_word); |
| 65 | EXPORT_SYMBOL(pci_bus_read_config_dword); |
| 66 | EXPORT_SYMBOL(pci_bus_write_config_byte); |
| 67 | EXPORT_SYMBOL(pci_bus_write_config_word); |
| 68 | EXPORT_SYMBOL(pci_bus_write_config_dword); |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 69 | |
Rob Herring | 1f94a94 | 2015-01-09 20:34:39 -0600 | [diff] [blame] | 70 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, |
| 71 | int where, int size, u32 *val) |
| 72 | { |
| 73 | void __iomem *addr; |
| 74 | |
| 75 | addr = bus->ops->map_bus(bus, devfn, where); |
| 76 | if (!addr) { |
| 77 | *val = ~0; |
| 78 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 79 | } |
| 80 | |
| 81 | if (size == 1) |
| 82 | *val = readb(addr); |
| 83 | else if (size == 2) |
| 84 | *val = readw(addr); |
| 85 | else |
| 86 | *val = readl(addr); |
| 87 | |
| 88 | return PCIBIOS_SUCCESSFUL; |
| 89 | } |
| 90 | EXPORT_SYMBOL_GPL(pci_generic_config_read); |
| 91 | |
| 92 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, |
| 93 | int where, int size, u32 val) |
| 94 | { |
| 95 | void __iomem *addr; |
| 96 | |
| 97 | addr = bus->ops->map_bus(bus, devfn, where); |
| 98 | if (!addr) |
| 99 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 100 | |
| 101 | if (size == 1) |
| 102 | writeb(val, addr); |
| 103 | else if (size == 2) |
| 104 | writew(val, addr); |
| 105 | else |
| 106 | writel(val, addr); |
| 107 | |
| 108 | return PCIBIOS_SUCCESSFUL; |
| 109 | } |
| 110 | EXPORT_SYMBOL_GPL(pci_generic_config_write); |
| 111 | |
| 112 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, |
| 113 | int where, int size, u32 *val) |
| 114 | { |
| 115 | void __iomem *addr; |
| 116 | |
| 117 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); |
| 118 | if (!addr) { |
| 119 | *val = ~0; |
| 120 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 121 | } |
| 122 | |
| 123 | *val = readl(addr); |
| 124 | |
| 125 | if (size <= 2) |
| 126 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); |
| 127 | |
| 128 | return PCIBIOS_SUCCESSFUL; |
| 129 | } |
| 130 | EXPORT_SYMBOL_GPL(pci_generic_config_read32); |
| 131 | |
| 132 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, |
| 133 | int where, int size, u32 val) |
| 134 | { |
| 135 | void __iomem *addr; |
| 136 | u32 mask, tmp; |
| 137 | |
| 138 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); |
| 139 | if (!addr) |
| 140 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 141 | |
| 142 | if (size == 4) { |
| 143 | writel(val, addr); |
| 144 | return PCIBIOS_SUCCESSFUL; |
| 145 | } else { |
| 146 | mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); |
| 147 | } |
| 148 | |
| 149 | tmp = readl(addr) & mask; |
| 150 | tmp |= val << ((where & 0x3) * 8); |
| 151 | writel(tmp, addr); |
| 152 | |
| 153 | return PCIBIOS_SUCCESSFUL; |
| 154 | } |
| 155 | EXPORT_SYMBOL_GPL(pci_generic_config_write32); |
| 156 | |
Huang Ying | a72b46c | 2009-04-24 10:45:17 +0800 | [diff] [blame] | 157 | /** |
| 158 | * pci_bus_set_ops - Set raw operations of pci bus |
| 159 | * @bus: pci bus struct |
| 160 | * @ops: new raw operations |
| 161 | * |
| 162 | * Return previous raw operations |
| 163 | */ |
| 164 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) |
| 165 | { |
| 166 | struct pci_ops *old_ops; |
| 167 | unsigned long flags; |
| 168 | |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 169 | raw_spin_lock_irqsave(&pci_lock, flags); |
Huang Ying | a72b46c | 2009-04-24 10:45:17 +0800 | [diff] [blame] | 170 | old_ops = bus->ops; |
| 171 | bus->ops = ops; |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 172 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
Huang Ying | a72b46c | 2009-04-24 10:45:17 +0800 | [diff] [blame] | 173 | return old_ops; |
| 174 | } |
| 175 | EXPORT_SYMBOL(pci_bus_set_ops); |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 176 | |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 177 | /* |
| 178 | * The following routines are to prevent the user from accessing PCI config |
| 179 | * space when it's unsafe to do so. Some devices require this during BIST and |
| 180 | * we're required to prevent it during D-state transitions. |
| 181 | * |
| 182 | * We have a bit per device to indicate it's blocked and a global wait queue |
| 183 | * for callers to sleep on until devices are unblocked. |
| 184 | */ |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 185 | static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait); |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 186 | |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 187 | static noinline void pci_wait_cfg(struct pci_dev *dev) |
Bjorn Helgaas | f5808a9 | 2020-06-25 18:14:55 -0500 | [diff] [blame^] | 188 | __must_hold(&pci_lock) |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 189 | { |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 190 | do { |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 191 | raw_spin_unlock_irq(&pci_lock); |
Bjorn Helgaas | f5808a9 | 2020-06-25 18:14:55 -0500 | [diff] [blame^] | 192 | wait_event(pci_cfg_wait, !dev->block_cfg_access); |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 193 | raw_spin_lock_irq(&pci_lock); |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 194 | } while (dev->block_cfg_access); |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 195 | } |
| 196 | |
Greg Thelen | 34e3207 | 2011-04-17 08:20:32 -0700 | [diff] [blame] | 197 | /* Returns 0 on success, negative values indicate error. */ |
Bogicevic Sasa | ff3ce48 | 2015-12-27 13:21:11 -0800 | [diff] [blame] | 198 | #define PCI_USER_READ_CONFIG(size, type) \ |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 199 | int pci_user_read_config_##size \ |
| 200 | (struct pci_dev *dev, int pos, type *val) \ |
| 201 | { \ |
Gavin Shan | d97ffe2 | 2014-05-21 15:23:30 +1000 | [diff] [blame] | 202 | int ret = PCIBIOS_SUCCESSFUL; \ |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 203 | u32 data = -1; \ |
Greg Thelen | 34e3207 | 2011-04-17 08:20:32 -0700 | [diff] [blame] | 204 | if (PCI_##size##_BAD) \ |
| 205 | return -EINVAL; \ |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 206 | raw_spin_lock_irq(&pci_lock); \ |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 207 | if (unlikely(dev->block_cfg_access)) \ |
| 208 | pci_wait_cfg(dev); \ |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 209 | ret = dev->bus->ops->read(dev->bus, dev->devfn, \ |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 210 | pos, sizeof(type), &data); \ |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 211 | raw_spin_unlock_irq(&pci_lock); \ |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 212 | *val = (type)data; \ |
Gavin Shan | d97ffe2 | 2014-05-21 15:23:30 +1000 | [diff] [blame] | 213 | return pcibios_err_to_errno(ret); \ |
Alex Williamson | c63587d | 2012-06-11 05:27:19 +0000 | [diff] [blame] | 214 | } \ |
| 215 | EXPORT_SYMBOL_GPL(pci_user_read_config_##size); |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 216 | |
Greg Thelen | 34e3207 | 2011-04-17 08:20:32 -0700 | [diff] [blame] | 217 | /* Returns 0 on success, negative values indicate error. */ |
Bogicevic Sasa | ff3ce48 | 2015-12-27 13:21:11 -0800 | [diff] [blame] | 218 | #define PCI_USER_WRITE_CONFIG(size, type) \ |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 219 | int pci_user_write_config_##size \ |
| 220 | (struct pci_dev *dev, int pos, type val) \ |
| 221 | { \ |
Gavin Shan | d97ffe2 | 2014-05-21 15:23:30 +1000 | [diff] [blame] | 222 | int ret = PCIBIOS_SUCCESSFUL; \ |
Greg Thelen | 34e3207 | 2011-04-17 08:20:32 -0700 | [diff] [blame] | 223 | if (PCI_##size##_BAD) \ |
| 224 | return -EINVAL; \ |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 225 | raw_spin_lock_irq(&pci_lock); \ |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 226 | if (unlikely(dev->block_cfg_access)) \ |
| 227 | pci_wait_cfg(dev); \ |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 228 | ret = dev->bus->ops->write(dev->bus, dev->devfn, \ |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 229 | pos, sizeof(type), val); \ |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 230 | raw_spin_unlock_irq(&pci_lock); \ |
Gavin Shan | d97ffe2 | 2014-05-21 15:23:30 +1000 | [diff] [blame] | 231 | return pcibios_err_to_errno(ret); \ |
Alex Williamson | c63587d | 2012-06-11 05:27:19 +0000 | [diff] [blame] | 232 | } \ |
| 233 | EXPORT_SYMBOL_GPL(pci_user_write_config_##size); |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 234 | |
| 235 | PCI_USER_READ_CONFIG(byte, u8) |
| 236 | PCI_USER_READ_CONFIG(word, u16) |
| 237 | PCI_USER_READ_CONFIG(dword, u32) |
| 238 | PCI_USER_WRITE_CONFIG(byte, u8) |
| 239 | PCI_USER_WRITE_CONFIG(word, u16) |
| 240 | PCI_USER_WRITE_CONFIG(dword, u32) |
| 241 | |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 242 | /* VPD access through PCI 2.2+ VPD capability */ |
| 243 | |
Bjorn Helgaas | fc0a407 | 2016-02-22 13:57:50 -0600 | [diff] [blame] | 244 | /** |
| 245 | * pci_read_vpd - Read one entry from Vital Product Data |
| 246 | * @dev: pci device struct |
| 247 | * @pos: offset in vpd space |
| 248 | * @count: number of bytes to read |
| 249 | * @buf: pointer to where to store result |
| 250 | */ |
| 251 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf) |
| 252 | { |
| 253 | if (!dev->vpd || !dev->vpd->ops) |
| 254 | return -ENODEV; |
| 255 | return dev->vpd->ops->read(dev, pos, count, buf); |
| 256 | } |
| 257 | EXPORT_SYMBOL(pci_read_vpd); |
| 258 | |
| 259 | /** |
| 260 | * pci_write_vpd - Write entry to Vital Product Data |
| 261 | * @dev: pci device struct |
| 262 | * @pos: offset in vpd space |
| 263 | * @count: number of bytes to write |
| 264 | * @buf: buffer containing write data |
| 265 | */ |
| 266 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf) |
| 267 | { |
| 268 | if (!dev->vpd || !dev->vpd->ops) |
| 269 | return -ENODEV; |
| 270 | return dev->vpd->ops->write(dev, pos, count, buf); |
| 271 | } |
| 272 | EXPORT_SYMBOL(pci_write_vpd); |
| 273 | |
Hariprasad Shenai | cb92148 | 2016-04-15 13:00:11 -0500 | [diff] [blame] | 274 | /** |
| 275 | * pci_set_vpd_size - Set size of Vital Product Data space |
| 276 | * @dev: pci device struct |
| 277 | * @len: size of vpd space |
| 278 | */ |
| 279 | int pci_set_vpd_size(struct pci_dev *dev, size_t len) |
| 280 | { |
| 281 | if (!dev->vpd || !dev->vpd->ops) |
| 282 | return -ENODEV; |
| 283 | return dev->vpd->ops->set_size(dev, len); |
| 284 | } |
| 285 | EXPORT_SYMBOL(pci_set_vpd_size); |
| 286 | |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 287 | #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1) |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 288 | |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 289 | /** |
| 290 | * pci_vpd_size - determine actual size of Vital Product Data |
| 291 | * @dev: pci device struct |
| 292 | * @old_size: current assumed size, also maximum allowed size |
| 293 | */ |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 294 | static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size) |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 295 | { |
| 296 | size_t off = 0; |
| 297 | unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */ |
| 298 | |
| 299 | while (off < old_size && |
| 300 | pci_read_vpd(dev, off, 1, header) == 1) { |
| 301 | unsigned char tag; |
| 302 | |
| 303 | if (header[0] & PCI_VPD_LRDT) { |
| 304 | /* Large Resource Data Type Tag */ |
| 305 | tag = pci_vpd_lrdt_tag(header); |
| 306 | /* Only read length from known tag items */ |
| 307 | if ((tag == PCI_VPD_LTIN_ID_STRING) || |
| 308 | (tag == PCI_VPD_LTIN_RO_DATA) || |
| 309 | (tag == PCI_VPD_LTIN_RW_DATA)) { |
| 310 | if (pci_read_vpd(dev, off+1, 2, |
| 311 | &header[1]) != 2) { |
| 312 | dev_warn(&dev->dev, |
| 313 | "invalid large VPD tag %02x size at offset %zu", |
| 314 | tag, off + 1); |
| 315 | return 0; |
| 316 | } |
| 317 | off += PCI_VPD_LRDT_TAG_SIZE + |
| 318 | pci_vpd_lrdt_size(header); |
| 319 | } |
| 320 | } else { |
| 321 | /* Short Resource Data Type Tag */ |
| 322 | off += PCI_VPD_SRDT_TAG_SIZE + |
| 323 | pci_vpd_srdt_size(header); |
| 324 | tag = pci_vpd_srdt_tag(header); |
| 325 | } |
| 326 | |
| 327 | if (tag == PCI_VPD_STIN_END) /* End tag descriptor */ |
| 328 | return off; |
| 329 | |
| 330 | if ((tag != PCI_VPD_LTIN_ID_STRING) && |
| 331 | (tag != PCI_VPD_LTIN_RO_DATA) && |
| 332 | (tag != PCI_VPD_LTIN_RW_DATA)) { |
| 333 | dev_warn(&dev->dev, |
| 334 | "invalid %s VPD tag %02x at offset %zu", |
| 335 | (header[0] & PCI_VPD_LRDT) ? "large" : "short", |
| 336 | tag, off); |
| 337 | return 0; |
| 338 | } |
| 339 | } |
| 340 | return 0; |
| 341 | } |
| 342 | |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 343 | /* |
| 344 | * Wait for last operation to complete. |
| 345 | * This code has to spin since there is no other notification from the PCI |
| 346 | * hardware. Since the VPD is often implemented by serial attachment to an |
| 347 | * EEPROM, it may take many milliseconds to complete. |
Greg Thelen | 34e3207 | 2011-04-17 08:20:32 -0700 | [diff] [blame] | 348 | * |
| 349 | * Returns 0 on success, negative values indicate error. |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 350 | */ |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 351 | static int pci_vpd_wait(struct pci_dev *dev) |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 352 | { |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 353 | struct pci_vpd *vpd = dev->vpd; |
Bjorn Helgaas | c521b01 | 2016-02-22 14:58:18 -0600 | [diff] [blame] | 354 | unsigned long timeout = jiffies + msecs_to_jiffies(50); |
| 355 | unsigned long max_sleep = 16; |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 356 | u16 status; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 357 | int ret; |
| 358 | |
| 359 | if (!vpd->busy) |
| 360 | return 0; |
| 361 | |
Bjorn Helgaas | c521b01 | 2016-02-22 14:58:18 -0600 | [diff] [blame] | 362 | while (time_before(jiffies, timeout)) { |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 363 | ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 364 | &status); |
Greg Thelen | 34e3207 | 2011-04-17 08:20:32 -0700 | [diff] [blame] | 365 | if (ret < 0) |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 366 | return ret; |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 367 | |
| 368 | if ((status & PCI_VPD_ADDR_F) == vpd->flag) { |
Bjorn Helgaas | c556388 | 2016-02-22 14:04:07 -0600 | [diff] [blame] | 369 | vpd->busy = 0; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 370 | return 0; |
| 371 | } |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 372 | |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 373 | if (fatal_signal_pending(current)) |
| 374 | return -EINTR; |
Bjorn Helgaas | c521b01 | 2016-02-22 14:58:18 -0600 | [diff] [blame] | 375 | |
| 376 | usleep_range(10, max_sleep); |
| 377 | if (max_sleep < 1024) |
| 378 | max_sleep *= 2; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 379 | } |
Bjorn Helgaas | c521b01 | 2016-02-22 14:58:18 -0600 | [diff] [blame] | 380 | |
| 381 | dev_warn(&dev->dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n"); |
| 382 | return -ETIMEDOUT; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 383 | } |
| 384 | |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 385 | static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count, |
| 386 | void *arg) |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 387 | { |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 388 | struct pci_vpd *vpd = dev->vpd; |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 389 | int ret; |
| 390 | loff_t end = pos + count; |
| 391 | u8 *buf = arg; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 392 | |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 393 | if (pos < 0) |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 394 | return -EINVAL; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 395 | |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 396 | if (!vpd->valid) { |
| 397 | vpd->valid = 1; |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 398 | vpd->len = pci_vpd_size(dev, vpd->len); |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 399 | } |
| 400 | |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 401 | if (vpd->len == 0) |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 402 | return -EIO; |
| 403 | |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 404 | if (pos > vpd->len) |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 405 | return 0; |
| 406 | |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 407 | if (end > vpd->len) { |
| 408 | end = vpd->len; |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 409 | count = end - pos; |
| 410 | } |
| 411 | |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 412 | if (mutex_lock_killable(&vpd->lock)) |
| 413 | return -EINTR; |
| 414 | |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 415 | ret = pci_vpd_wait(dev); |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 416 | if (ret < 0) |
| 417 | goto out; |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 418 | |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 419 | while (pos < end) { |
| 420 | u32 val; |
| 421 | unsigned int i, skip; |
| 422 | |
| 423 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, |
| 424 | pos & ~3); |
| 425 | if (ret < 0) |
| 426 | break; |
Bjorn Helgaas | c556388 | 2016-02-22 14:04:07 -0600 | [diff] [blame] | 427 | vpd->busy = 1; |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 428 | vpd->flag = PCI_VPD_ADDR_F; |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 429 | ret = pci_vpd_wait(dev); |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 430 | if (ret < 0) |
| 431 | break; |
| 432 | |
| 433 | ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); |
| 434 | if (ret < 0) |
| 435 | break; |
| 436 | |
| 437 | skip = pos & 3; |
| 438 | for (i = 0; i < sizeof(u32); i++) { |
| 439 | if (i >= skip) { |
| 440 | *buf++ = val; |
| 441 | if (++pos == end) |
| 442 | break; |
| 443 | } |
| 444 | val >>= 8; |
| 445 | } |
| 446 | } |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 447 | out: |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 448 | mutex_unlock(&vpd->lock); |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 449 | return ret ? ret : count; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 450 | } |
| 451 | |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 452 | static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count, |
| 453 | const void *arg) |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 454 | { |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 455 | struct pci_vpd *vpd = dev->vpd; |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 456 | const u8 *buf = arg; |
| 457 | loff_t end = pos + count; |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 458 | int ret = 0; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 459 | |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 460 | if (pos < 0 || (pos & 3) || (count & 3)) |
| 461 | return -EINVAL; |
| 462 | |
| 463 | if (!vpd->valid) { |
| 464 | vpd->valid = 1; |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 465 | vpd->len = pci_vpd_size(dev, vpd->len); |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 466 | } |
| 467 | |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 468 | if (vpd->len == 0) |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 469 | return -EIO; |
| 470 | |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 471 | if (end > vpd->len) |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 472 | return -EINVAL; |
| 473 | |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 474 | if (mutex_lock_killable(&vpd->lock)) |
| 475 | return -EINTR; |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 476 | |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 477 | ret = pci_vpd_wait(dev); |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 478 | if (ret < 0) |
| 479 | goto out; |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 480 | |
| 481 | while (pos < end) { |
| 482 | u32 val; |
| 483 | |
| 484 | val = *buf++; |
| 485 | val |= *buf++ << 8; |
| 486 | val |= *buf++ << 16; |
| 487 | val |= *buf++ << 24; |
| 488 | |
| 489 | ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); |
| 490 | if (ret < 0) |
| 491 | break; |
| 492 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, |
| 493 | pos | PCI_VPD_ADDR_F); |
| 494 | if (ret < 0) |
| 495 | break; |
| 496 | |
Bjorn Helgaas | c556388 | 2016-02-22 14:04:07 -0600 | [diff] [blame] | 497 | vpd->busy = 1; |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 498 | vpd->flag = 0; |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 499 | ret = pci_vpd_wait(dev); |
Greg Thelen | d97ecd8 | 2011-04-17 08:22:21 -0700 | [diff] [blame] | 500 | if (ret < 0) |
| 501 | break; |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 502 | |
| 503 | pos += sizeof(u32); |
| 504 | } |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 505 | out: |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 506 | mutex_unlock(&vpd->lock); |
Stephen Hemminger | 287d19c | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 507 | return ret ? ret : count; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 508 | } |
| 509 | |
Hariprasad Shenai | cb92148 | 2016-04-15 13:00:11 -0500 | [diff] [blame] | 510 | static int pci_vpd_set_size(struct pci_dev *dev, size_t len) |
| 511 | { |
| 512 | struct pci_vpd *vpd = dev->vpd; |
| 513 | |
| 514 | if (len == 0 || len > PCI_VPD_MAX_SIZE) |
| 515 | return -EIO; |
| 516 | |
| 517 | vpd->valid = 1; |
| 518 | vpd->len = len; |
| 519 | |
| 520 | return 0; |
| 521 | } |
| 522 | |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 523 | static const struct pci_vpd_ops pci_vpd_ops = { |
| 524 | .read = pci_vpd_read, |
| 525 | .write = pci_vpd_write, |
Hariprasad Shenai | cb92148 | 2016-04-15 13:00:11 -0500 | [diff] [blame] | 526 | .set_size = pci_vpd_set_size, |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 527 | }; |
| 528 | |
Mark Rustad | 932c435 | 2015-07-13 11:40:02 -0700 | [diff] [blame] | 529 | static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count, |
| 530 | void *arg) |
| 531 | { |
Alex Williamson | 9d92407 | 2015-09-15 11:17:21 -0600 | [diff] [blame] | 532 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
| 533 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
Mark Rustad | 932c435 | 2015-07-13 11:40:02 -0700 | [diff] [blame] | 534 | ssize_t ret; |
| 535 | |
| 536 | if (!tdev) |
| 537 | return -ENODEV; |
| 538 | |
| 539 | ret = pci_read_vpd(tdev, pos, count, arg); |
| 540 | pci_dev_put(tdev); |
| 541 | return ret; |
| 542 | } |
| 543 | |
| 544 | static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count, |
| 545 | const void *arg) |
| 546 | { |
Alex Williamson | 9d92407 | 2015-09-15 11:17:21 -0600 | [diff] [blame] | 547 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
| 548 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
Mark Rustad | 932c435 | 2015-07-13 11:40:02 -0700 | [diff] [blame] | 549 | ssize_t ret; |
| 550 | |
| 551 | if (!tdev) |
| 552 | return -ENODEV; |
| 553 | |
| 554 | ret = pci_write_vpd(tdev, pos, count, arg); |
| 555 | pci_dev_put(tdev); |
| 556 | return ret; |
| 557 | } |
| 558 | |
Hariprasad Shenai | cb92148 | 2016-04-15 13:00:11 -0500 | [diff] [blame] | 559 | static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len) |
| 560 | { |
| 561 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
| 562 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
| 563 | int ret; |
| 564 | |
| 565 | if (!tdev) |
| 566 | return -ENODEV; |
| 567 | |
| 568 | ret = pci_set_vpd_size(tdev, len); |
| 569 | pci_dev_put(tdev); |
| 570 | return ret; |
| 571 | } |
| 572 | |
Mark Rustad | 932c435 | 2015-07-13 11:40:02 -0700 | [diff] [blame] | 573 | static const struct pci_vpd_ops pci_vpd_f0_ops = { |
| 574 | .read = pci_vpd_f0_read, |
| 575 | .write = pci_vpd_f0_write, |
Hariprasad Shenai | cb92148 | 2016-04-15 13:00:11 -0500 | [diff] [blame] | 576 | .set_size = pci_vpd_f0_set_size, |
Mark Rustad | 932c435 | 2015-07-13 11:40:02 -0700 | [diff] [blame] | 577 | }; |
| 578 | |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 579 | int pci_vpd_init(struct pci_dev *dev) |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 580 | { |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 581 | struct pci_vpd *vpd; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 582 | u8 cap; |
| 583 | |
| 584 | cap = pci_find_capability(dev, PCI_CAP_ID_VPD); |
| 585 | if (!cap) |
| 586 | return -ENODEV; |
Mark Rustad | 932c435 | 2015-07-13 11:40:02 -0700 | [diff] [blame] | 587 | |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 588 | vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC); |
| 589 | if (!vpd) |
| 590 | return -ENOMEM; |
| 591 | |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 592 | vpd->len = PCI_VPD_MAX_SIZE; |
Mark Rustad | 932c435 | 2015-07-13 11:40:02 -0700 | [diff] [blame] | 593 | if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 594 | vpd->ops = &pci_vpd_f0_ops; |
Mark Rustad | 932c435 | 2015-07-13 11:40:02 -0700 | [diff] [blame] | 595 | else |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 596 | vpd->ops = &pci_vpd_ops; |
Stephen Hemminger | 1120f8b | 2008-12-18 09:17:16 -0800 | [diff] [blame] | 597 | mutex_init(&vpd->lock); |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 598 | vpd->cap = cap; |
Bjorn Helgaas | c556388 | 2016-02-22 14:04:07 -0600 | [diff] [blame] | 599 | vpd->busy = 0; |
Hannes Reinecke | 104daa7 | 2016-02-15 09:42:01 +0100 | [diff] [blame] | 600 | vpd->valid = 0; |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 601 | dev->vpd = vpd; |
Ben Hutchings | 94e6108 | 2008-03-05 16:52:39 +0000 | [diff] [blame] | 602 | return 0; |
| 603 | } |
| 604 | |
Bjorn Helgaas | 6437907 | 2016-02-22 13:58:06 -0600 | [diff] [blame] | 605 | void pci_vpd_release(struct pci_dev *dev) |
| 606 | { |
Bjorn Helgaas | 408641e | 2016-02-22 14:09:52 -0600 | [diff] [blame] | 607 | kfree(dev->vpd); |
Bjorn Helgaas | 6437907 | 2016-02-22 13:58:06 -0600 | [diff] [blame] | 608 | } |
| 609 | |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 610 | /** |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 611 | * pci_cfg_access_lock - Lock PCI config reads/writes |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 612 | * @dev: pci device struct |
| 613 | * |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 614 | * When access is locked, any userspace reads or writes to config |
| 615 | * space and concurrent lock requests will sleep until access is |
| 616 | * allowed via pci_cfg_access_unlocked again. |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 617 | */ |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 618 | void pci_cfg_access_lock(struct pci_dev *dev) |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 619 | { |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 620 | might_sleep(); |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 621 | |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 622 | raw_spin_lock_irq(&pci_lock); |
| 623 | if (dev->block_cfg_access) |
| 624 | pci_wait_cfg(dev); |
| 625 | dev->block_cfg_access = 1; |
| 626 | raw_spin_unlock_irq(&pci_lock); |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 627 | } |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 628 | EXPORT_SYMBOL_GPL(pci_cfg_access_lock); |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 629 | |
| 630 | /** |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 631 | * pci_cfg_access_trylock - try to lock PCI config reads/writes |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 632 | * @dev: pci device struct |
| 633 | * |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 634 | * Same as pci_cfg_access_lock, but will return 0 if access is |
| 635 | * already locked, 1 otherwise. This function can be used from |
| 636 | * atomic contexts. |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 637 | */ |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 638 | bool pci_cfg_access_trylock(struct pci_dev *dev) |
| 639 | { |
| 640 | unsigned long flags; |
| 641 | bool locked = true; |
| 642 | |
| 643 | raw_spin_lock_irqsave(&pci_lock, flags); |
| 644 | if (dev->block_cfg_access) |
| 645 | locked = false; |
| 646 | else |
| 647 | dev->block_cfg_access = 1; |
| 648 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
| 649 | |
| 650 | return locked; |
| 651 | } |
| 652 | EXPORT_SYMBOL_GPL(pci_cfg_access_trylock); |
| 653 | |
| 654 | /** |
| 655 | * pci_cfg_access_unlock - Unlock PCI config reads/writes |
| 656 | * @dev: pci device struct |
| 657 | * |
| 658 | * This function allows PCI config accesses to resume. |
| 659 | */ |
| 660 | void pci_cfg_access_unlock(struct pci_dev *dev) |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 661 | { |
| 662 | unsigned long flags; |
| 663 | |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 664 | raw_spin_lock_irqsave(&pci_lock, flags); |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 665 | |
| 666 | /* This indicates a problem in the caller, but we don't need |
| 667 | * to kill them, unlike a double-block above. */ |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 668 | WARN_ON(!dev->block_cfg_access); |
Matthew Wilcox | 7ea7e98 | 2006-10-19 09:41:28 -0600 | [diff] [blame] | 669 | |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 670 | dev->block_cfg_access = 0; |
Thomas Gleixner | 511dd98 | 2010-02-17 14:35:19 +0000 | [diff] [blame] | 671 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
Bjorn Helgaas | df0c2d4 | 2017-10-07 22:37:34 +0000 | [diff] [blame] | 672 | |
| 673 | wake_up_all(&pci_cfg_wait); |
Brian King | e04b0ea | 2005-09-27 01:21:55 -0700 | [diff] [blame] | 674 | } |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 675 | EXPORT_SYMBOL_GPL(pci_cfg_access_unlock); |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 676 | |
| 677 | static inline int pcie_cap_version(const struct pci_dev *dev) |
| 678 | { |
Myron Stowe | 1c531d8 | 2013-01-25 17:55:45 -0700 | [diff] [blame] | 679 | return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 680 | } |
| 681 | |
Bjorn Helgaas | ffb4d60 | 2015-06-24 16:05:54 -0500 | [diff] [blame] | 682 | static bool pcie_downstream_port(const struct pci_dev *dev) |
| 683 | { |
| 684 | int type = pci_pcie_type(dev); |
| 685 | |
| 686 | return type == PCI_EXP_TYPE_ROOT_PORT || |
| 687 | type == PCI_EXP_TYPE_DOWNSTREAM; |
| 688 | } |
| 689 | |
Yinghai Lu | 7a1562d | 2014-11-11 12:09:46 -0800 | [diff] [blame] | 690 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev) |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 691 | { |
| 692 | int type = pci_pcie_type(dev); |
| 693 | |
Bjorn Helgaas | c8b303d | 2013-08-28 11:33:53 -0600 | [diff] [blame] | 694 | return type == PCI_EXP_TYPE_ENDPOINT || |
Bjorn Helgaas | d3694d4 | 2013-08-27 09:54:40 -0600 | [diff] [blame] | 695 | type == PCI_EXP_TYPE_LEG_END || |
| 696 | type == PCI_EXP_TYPE_ROOT_PORT || |
| 697 | type == PCI_EXP_TYPE_UPSTREAM || |
| 698 | type == PCI_EXP_TYPE_DOWNSTREAM || |
| 699 | type == PCI_EXP_TYPE_PCI_BRIDGE || |
| 700 | type == PCI_EXP_TYPE_PCIE_BRIDGE; |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 701 | } |
| 702 | |
| 703 | static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) |
| 704 | { |
Bjorn Helgaas | ffb4d60 | 2015-06-24 16:05:54 -0500 | [diff] [blame] | 705 | return pcie_downstream_port(dev) && |
Bjorn Helgaas | 6d3a174 | 2013-08-28 12:01:03 -0600 | [diff] [blame] | 706 | pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) |
| 710 | { |
| 711 | int type = pci_pcie_type(dev); |
| 712 | |
Bjorn Helgaas | c8b303d | 2013-08-28 11:33:53 -0600 | [diff] [blame] | 713 | return type == PCI_EXP_TYPE_ROOT_PORT || |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 714 | type == PCI_EXP_TYPE_RC_EC; |
| 715 | } |
| 716 | |
| 717 | static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) |
| 718 | { |
| 719 | if (!pci_is_pcie(dev)) |
| 720 | return false; |
| 721 | |
| 722 | switch (pos) { |
Alex Williamson | 969daa3 | 2013-02-14 11:35:42 -0700 | [diff] [blame] | 723 | case PCI_EXP_FLAGS: |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 724 | return true; |
| 725 | case PCI_EXP_DEVCAP: |
| 726 | case PCI_EXP_DEVCTL: |
| 727 | case PCI_EXP_DEVSTA: |
Bjorn Helgaas | fed2451 | 2013-08-28 12:03:42 -0600 | [diff] [blame] | 728 | return true; |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 729 | case PCI_EXP_LNKCAP: |
| 730 | case PCI_EXP_LNKCTL: |
| 731 | case PCI_EXP_LNKSTA: |
| 732 | return pcie_cap_has_lnkctl(dev); |
| 733 | case PCI_EXP_SLTCAP: |
| 734 | case PCI_EXP_SLTCTL: |
| 735 | case PCI_EXP_SLTSTA: |
| 736 | return pcie_cap_has_sltctl(dev); |
| 737 | case PCI_EXP_RTCTL: |
| 738 | case PCI_EXP_RTCAP: |
| 739 | case PCI_EXP_RTSTA: |
| 740 | return pcie_cap_has_rtctl(dev); |
| 741 | case PCI_EXP_DEVCAP2: |
| 742 | case PCI_EXP_DEVCTL2: |
| 743 | case PCI_EXP_LNKCAP2: |
| 744 | case PCI_EXP_LNKCTL2: |
| 745 | case PCI_EXP_LNKSTA2: |
| 746 | return pcie_cap_version(dev) > 1; |
| 747 | default: |
| 748 | return false; |
| 749 | } |
| 750 | } |
| 751 | |
| 752 | /* |
| 753 | * Note that these accessor functions are only for the "PCI Express |
| 754 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the |
| 755 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) |
| 756 | */ |
| 757 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) |
| 758 | { |
| 759 | int ret; |
| 760 | |
| 761 | *val = 0; |
| 762 | if (pos & 1) |
| 763 | return -EINVAL; |
| 764 | |
| 765 | if (pcie_capability_reg_implemented(dev, pos)) { |
| 766 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); |
| 767 | /* |
| 768 | * Reset *val to 0 if pci_read_config_word() fails, it may |
| 769 | * have been written as 0xFFFF if hardware error happens |
| 770 | * during pci_read_config_word(). |
| 771 | */ |
| 772 | if (ret) |
| 773 | *val = 0; |
| 774 | return ret; |
| 775 | } |
| 776 | |
| 777 | /* |
| 778 | * For Functions that do not implement the Slot Capabilities, |
| 779 | * Slot Status, and Slot Control registers, these spaces must |
| 780 | * be hardwired to 0b, with the exception of the Presence Detect |
| 781 | * State bit in the Slot Status register of Downstream Ports, |
| 782 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) |
| 783 | */ |
Bjorn Helgaas | ffb4d60 | 2015-06-24 16:05:54 -0500 | [diff] [blame] | 784 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
| 785 | pos == PCI_EXP_SLTSTA) |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 786 | *val = PCI_EXP_SLTSTA_PDS; |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 787 | |
| 788 | return 0; |
| 789 | } |
| 790 | EXPORT_SYMBOL(pcie_capability_read_word); |
| 791 | |
| 792 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) |
| 793 | { |
| 794 | int ret; |
| 795 | |
| 796 | *val = 0; |
| 797 | if (pos & 3) |
| 798 | return -EINVAL; |
| 799 | |
| 800 | if (pcie_capability_reg_implemented(dev, pos)) { |
| 801 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
| 802 | /* |
| 803 | * Reset *val to 0 if pci_read_config_dword() fails, it may |
| 804 | * have been written as 0xFFFFFFFF if hardware error happens |
| 805 | * during pci_read_config_dword(). |
| 806 | */ |
| 807 | if (ret) |
| 808 | *val = 0; |
| 809 | return ret; |
| 810 | } |
| 811 | |
Bjorn Helgaas | ffb4d60 | 2015-06-24 16:05:54 -0500 | [diff] [blame] | 812 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
| 813 | pos == PCI_EXP_SLTSTA) |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 814 | *val = PCI_EXP_SLTSTA_PDS; |
Jiang Liu | 8c0d3a0 | 2012-07-24 17:20:05 +0800 | [diff] [blame] | 815 | |
| 816 | return 0; |
| 817 | } |
| 818 | EXPORT_SYMBOL(pcie_capability_read_dword); |
| 819 | |
| 820 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) |
| 821 | { |
| 822 | if (pos & 1) |
| 823 | return -EINVAL; |
| 824 | |
| 825 | if (!pcie_capability_reg_implemented(dev, pos)) |
| 826 | return 0; |
| 827 | |
| 828 | return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); |
| 829 | } |
| 830 | EXPORT_SYMBOL(pcie_capability_write_word); |
| 831 | |
| 832 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) |
| 833 | { |
| 834 | if (pos & 3) |
| 835 | return -EINVAL; |
| 836 | |
| 837 | if (!pcie_capability_reg_implemented(dev, pos)) |
| 838 | return 0; |
| 839 | |
| 840 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
| 841 | } |
| 842 | EXPORT_SYMBOL(pcie_capability_write_dword); |
| 843 | |
| 844 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, |
| 845 | u16 clear, u16 set) |
| 846 | { |
| 847 | int ret; |
| 848 | u16 val; |
| 849 | |
| 850 | ret = pcie_capability_read_word(dev, pos, &val); |
| 851 | if (!ret) { |
| 852 | val &= ~clear; |
| 853 | val |= set; |
| 854 | ret = pcie_capability_write_word(dev, pos, val); |
| 855 | } |
| 856 | |
| 857 | return ret; |
| 858 | } |
| 859 | EXPORT_SYMBOL(pcie_capability_clear_and_set_word); |
| 860 | |
| 861 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, |
| 862 | u32 clear, u32 set) |
| 863 | { |
| 864 | int ret; |
| 865 | u32 val; |
| 866 | |
| 867 | ret = pcie_capability_read_dword(dev, pos, &val); |
| 868 | if (!ret) { |
| 869 | val &= ~clear; |
| 870 | val |= set; |
| 871 | ret = pcie_capability_write_dword(dev, pos, val); |
| 872 | } |
| 873 | |
| 874 | return ret; |
| 875 | } |
| 876 | EXPORT_SYMBOL(pcie_capability_clear_and_set_dword); |