R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | #include <dt-bindings/pinctrl/dra.h> |
| 12 | |
| 13 | #include "skeleton.dtsi" |
| 14 | |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 15 | #define MAX_SOURCES 400 |
| 16 | #define DIRECT_IRQ(irq) (MAX_SOURCES + irq) |
| 17 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 18 | / { |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <1>; |
| 21 | |
| 22 | compatible = "ti,dra7xx"; |
| 23 | interrupt-parent = <&gic>; |
| 24 | |
| 25 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 26 | i2c0 = &i2c1; |
| 27 | i2c1 = &i2c2; |
| 28 | i2c2 = &i2c3; |
| 29 | i2c3 = &i2c4; |
| 30 | i2c4 = &i2c5; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 31 | serial0 = &uart1; |
| 32 | serial1 = &uart2; |
| 33 | serial2 = &uart3; |
| 34 | serial3 = &uart4; |
| 35 | serial4 = &uart5; |
| 36 | serial5 = &uart6; |
Nishanth Menon | 065bd7f | 2014-10-21 11:18:15 -0500 | [diff] [blame] | 37 | serial6 = &uart7; |
| 38 | serial7 = &uart8; |
| 39 | serial8 = &uart9; |
| 40 | serial9 = &uart10; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 41 | ethernet0 = &cpsw_emac0; |
| 42 | ethernet1 = &cpsw_emac1; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 43 | d_can0 = &dcan1; |
| 44 | d_can1 = &dcan2; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 45 | }; |
| 46 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 47 | timer { |
| 48 | compatible = "arm,armv7-timer"; |
| 49 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 50 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 51 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 52 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| 53 | }; |
| 54 | |
| 55 | gic: interrupt-controller@48211000 { |
| 56 | compatible = "arm,cortex-a15-gic"; |
| 57 | interrupt-controller; |
| 58 | #interrupt-cells = <3>; |
R Sricharan | 5130063 | 2014-06-26 12:55:30 +0530 | [diff] [blame] | 59 | arm,routable-irqs = <192>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 60 | reg = <0x48211000 0x1000>, |
| 61 | <0x48212000 0x1000>, |
| 62 | <0x48214000 0x2000>, |
| 63 | <0x48216000 0x2000>; |
| 64 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 65 | }; |
| 66 | |
| 67 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 68 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 69 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 70 | */ |
| 71 | soc { |
| 72 | compatible = "ti,omap-infra"; |
| 73 | mpu { |
| 74 | compatible = "ti,omap5-mpu"; |
| 75 | ti,hwmods = "mpu"; |
| 76 | }; |
| 77 | }; |
| 78 | |
| 79 | /* |
| 80 | * XXX: Use a flat representation of the SOC interconnect. |
| 81 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 82 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 83 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 84 | * hierarchy. |
| 85 | */ |
| 86 | ocp { |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 87 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 88 | #address-cells = <1>; |
| 89 | #size-cells = <1>; |
| 90 | ranges; |
| 91 | ti,hwmods = "l3_main_1", "l3_main_2"; |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 92 | reg = <0x44000000 0x1000000>, |
| 93 | <0x45000000 0x1000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 94 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 95 | <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 96 | |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 97 | prm: prm@4ae06000 { |
| 98 | compatible = "ti,dra7-prm"; |
| 99 | reg = <0x4ae06000 0x3000>; |
Nishanth Menon | 5081ce6 | 2014-08-22 09:03:50 -0500 | [diff] [blame] | 100 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 101 | |
| 102 | prm_clocks: clocks { |
| 103 | #address-cells = <1>; |
| 104 | #size-cells = <0>; |
| 105 | }; |
| 106 | |
| 107 | prm_clockdomains: clockdomains { |
| 108 | }; |
| 109 | }; |
| 110 | |
Kishon Vijay Abraham I | 18dcd79 | 2014-07-14 16:12:23 +0530 | [diff] [blame] | 111 | axi@0 { |
| 112 | compatible = "simple-bus"; |
| 113 | #size-cells = <1>; |
| 114 | #address-cells = <1>; |
| 115 | ranges = <0x51000000 0x51000000 0x3000 |
| 116 | 0x0 0x20000000 0x10000000>; |
| 117 | pcie@51000000 { |
| 118 | compatible = "ti,dra7-pcie"; |
| 119 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; |
| 120 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 121 | interrupts = <0 232 0x4>, <0 233 0x4>; |
| 122 | #address-cells = <3>; |
| 123 | #size-cells = <2>; |
| 124 | device_type = "pci"; |
| 125 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 126 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; |
| 127 | #interrupt-cells = <1>; |
| 128 | num-lanes = <1>; |
| 129 | ti,hwmods = "pcie1"; |
| 130 | phys = <&pcie1_phy>; |
| 131 | phy-names = "pcie-phy0"; |
| 132 | interrupt-map-mask = <0 0 0 7>; |
| 133 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, |
| 134 | <0 0 0 2 &pcie1_intc 2>, |
| 135 | <0 0 0 3 &pcie1_intc 3>, |
| 136 | <0 0 0 4 &pcie1_intc 4>; |
| 137 | pcie1_intc: interrupt-controller { |
| 138 | interrupt-controller; |
| 139 | #address-cells = <0>; |
| 140 | #interrupt-cells = <1>; |
| 141 | }; |
| 142 | }; |
| 143 | }; |
| 144 | |
| 145 | axi@1 { |
| 146 | compatible = "simple-bus"; |
| 147 | #size-cells = <1>; |
| 148 | #address-cells = <1>; |
| 149 | ranges = <0x51800000 0x51800000 0x3000 |
| 150 | 0x0 0x30000000 0x10000000>; |
| 151 | status = "disabled"; |
| 152 | pcie@51000000 { |
| 153 | compatible = "ti,dra7-pcie"; |
| 154 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; |
| 155 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 156 | interrupts = <0 355 0x4>, <0 356 0x4>; |
| 157 | #address-cells = <3>; |
| 158 | #size-cells = <2>; |
| 159 | device_type = "pci"; |
| 160 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 161 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; |
| 162 | #interrupt-cells = <1>; |
| 163 | num-lanes = <1>; |
| 164 | ti,hwmods = "pcie2"; |
| 165 | phys = <&pcie2_phy>; |
| 166 | phy-names = "pcie-phy0"; |
| 167 | interrupt-map-mask = <0 0 0 7>; |
| 168 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, |
| 169 | <0 0 0 2 &pcie2_intc 2>, |
| 170 | <0 0 0 3 &pcie2_intc 3>, |
| 171 | <0 0 0 4 &pcie2_intc 4>; |
| 172 | pcie2_intc: interrupt-controller { |
| 173 | interrupt-controller; |
| 174 | #address-cells = <0>; |
| 175 | #interrupt-cells = <1>; |
| 176 | }; |
| 177 | }; |
| 178 | }; |
| 179 | |
Keerthy | f7397ed | 2015-03-23 14:39:38 -0500 | [diff] [blame^] | 180 | bandgap: bandgap@4a0021e0 { |
| 181 | reg = <0x4a0021e0 0xc |
| 182 | 0x4a00232c 0xc |
| 183 | 0x4a002380 0x2c |
| 184 | 0x4a0023C0 0x3c |
| 185 | 0x4a002564 0x8 |
| 186 | 0x4a002574 0x50>; |
| 187 | compatible = "ti,dra752-bandgap"; |
| 188 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| 189 | #thermal-sensor-cells = <1>; |
| 190 | }; |
| 191 | |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 192 | cm_core_aon: cm_core_aon@4a005000 { |
| 193 | compatible = "ti,dra7-cm-core-aon"; |
| 194 | reg = <0x4a005000 0x2000>; |
| 195 | |
| 196 | cm_core_aon_clocks: clocks { |
| 197 | #address-cells = <1>; |
| 198 | #size-cells = <0>; |
| 199 | }; |
| 200 | |
| 201 | cm_core_aon_clockdomains: clockdomains { |
| 202 | }; |
| 203 | }; |
| 204 | |
| 205 | cm_core: cm_core@4a008000 { |
| 206 | compatible = "ti,dra7-cm-core"; |
| 207 | reg = <0x4a008000 0x3000>; |
| 208 | |
| 209 | cm_core_clocks: clocks { |
| 210 | #address-cells = <1>; |
| 211 | #size-cells = <0>; |
| 212 | }; |
| 213 | |
| 214 | cm_core_clockdomains: clockdomains { |
| 215 | }; |
| 216 | }; |
| 217 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 218 | counter32k: counter@4ae04000 { |
| 219 | compatible = "ti,omap-counter32k"; |
| 220 | reg = <0x4ae04000 0x40>; |
| 221 | ti,hwmods = "counter_32k"; |
| 222 | }; |
| 223 | |
Roger Quadros | ae3c0f7 | 2014-09-03 17:21:45 +0300 | [diff] [blame] | 224 | dra7_ctrl_core: ctrl_core@4a002000 { |
| 225 | compatible = "syscon"; |
| 226 | reg = <0x4a002000 0x6d0>; |
| 227 | }; |
| 228 | |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 229 | dra7_ctrl_general: tisyscon@4a002e00 { |
| 230 | compatible = "syscon"; |
| 231 | reg = <0x4a002e00 0x7c>; |
| 232 | }; |
| 233 | |
| 234 | pbias_regulator: pbias_regulator { |
| 235 | compatible = "ti,pbias-omap"; |
| 236 | reg = <0 0x4>; |
| 237 | syscon = <&dra7_ctrl_general>; |
| 238 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 239 | regulator-name = "pbias_mmc_omap5"; |
| 240 | regulator-min-microvolt = <1800000>; |
| 241 | regulator-max-microvolt = <3000000>; |
| 242 | }; |
| 243 | }; |
| 244 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 245 | dra7_pmx_core: pinmux@4a003400 { |
Nishanth Menon | 817c037 | 2014-05-22 23:47:46 -0500 | [diff] [blame] | 246 | compatible = "ti,dra7-padconf", "pinctrl-single"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 247 | reg = <0x4a003400 0x0464>; |
| 248 | #address-cells = <1>; |
| 249 | #size-cells = <0>; |
Nishanth Menon | 817c037 | 2014-05-22 23:47:46 -0500 | [diff] [blame] | 250 | #interrupt-cells = <1>; |
| 251 | interrupt-controller; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 252 | pinctrl-single,register-width = <32>; |
| 253 | pinctrl-single,function-mask = <0x3fffffff>; |
| 254 | }; |
| 255 | |
| 256 | sdma: dma-controller@4a056000 { |
| 257 | compatible = "ti,omap4430-sdma"; |
| 258 | reg = <0x4a056000 0x1000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 259 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 260 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 261 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 262 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 263 | #dma-cells = <1>; |
| 264 | #dma-channels = <32>; |
| 265 | #dma-requests = <127>; |
| 266 | }; |
| 267 | |
| 268 | gpio1: gpio@4ae10000 { |
| 269 | compatible = "ti,omap4-gpio"; |
| 270 | reg = <0x4ae10000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 271 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 272 | ti,hwmods = "gpio1"; |
| 273 | gpio-controller; |
| 274 | #gpio-cells = <2>; |
| 275 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 276 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 277 | }; |
| 278 | |
| 279 | gpio2: gpio@48055000 { |
| 280 | compatible = "ti,omap4-gpio"; |
| 281 | reg = <0x48055000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 282 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 283 | ti,hwmods = "gpio2"; |
| 284 | gpio-controller; |
| 285 | #gpio-cells = <2>; |
| 286 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 287 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 288 | }; |
| 289 | |
| 290 | gpio3: gpio@48057000 { |
| 291 | compatible = "ti,omap4-gpio"; |
| 292 | reg = <0x48057000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 293 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 294 | ti,hwmods = "gpio3"; |
| 295 | gpio-controller; |
| 296 | #gpio-cells = <2>; |
| 297 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 298 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 299 | }; |
| 300 | |
| 301 | gpio4: gpio@48059000 { |
| 302 | compatible = "ti,omap4-gpio"; |
| 303 | reg = <0x48059000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 304 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 305 | ti,hwmods = "gpio4"; |
| 306 | gpio-controller; |
| 307 | #gpio-cells = <2>; |
| 308 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 309 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 310 | }; |
| 311 | |
| 312 | gpio5: gpio@4805b000 { |
| 313 | compatible = "ti,omap4-gpio"; |
| 314 | reg = <0x4805b000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 315 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 316 | ti,hwmods = "gpio5"; |
| 317 | gpio-controller; |
| 318 | #gpio-cells = <2>; |
| 319 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 320 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 321 | }; |
| 322 | |
| 323 | gpio6: gpio@4805d000 { |
| 324 | compatible = "ti,omap4-gpio"; |
| 325 | reg = <0x4805d000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 326 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 327 | ti,hwmods = "gpio6"; |
| 328 | gpio-controller; |
| 329 | #gpio-cells = <2>; |
| 330 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 331 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 332 | }; |
| 333 | |
| 334 | gpio7: gpio@48051000 { |
| 335 | compatible = "ti,omap4-gpio"; |
| 336 | reg = <0x48051000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 337 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 338 | ti,hwmods = "gpio7"; |
| 339 | gpio-controller; |
| 340 | #gpio-cells = <2>; |
| 341 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 342 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 343 | }; |
| 344 | |
| 345 | gpio8: gpio@48053000 { |
| 346 | compatible = "ti,omap4-gpio"; |
| 347 | reg = <0x48053000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 348 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 349 | ti,hwmods = "gpio8"; |
| 350 | gpio-controller; |
| 351 | #gpio-cells = <2>; |
| 352 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 353 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 354 | }; |
| 355 | |
| 356 | uart1: serial@4806a000 { |
| 357 | compatible = "ti,omap4-uart"; |
| 358 | reg = <0x4806a000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 359 | interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 360 | ti,hwmods = "uart1"; |
| 361 | clock-frequency = <48000000>; |
| 362 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 363 | dmas = <&sdma 49>, <&sdma 50>; |
| 364 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 365 | }; |
| 366 | |
| 367 | uart2: serial@4806c000 { |
| 368 | compatible = "ti,omap4-uart"; |
| 369 | reg = <0x4806c000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 370 | interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 371 | ti,hwmods = "uart2"; |
| 372 | clock-frequency = <48000000>; |
| 373 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 374 | dmas = <&sdma 51>, <&sdma 52>; |
| 375 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 376 | }; |
| 377 | |
| 378 | uart3: serial@48020000 { |
| 379 | compatible = "ti,omap4-uart"; |
| 380 | reg = <0x48020000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 381 | interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 382 | ti,hwmods = "uart3"; |
| 383 | clock-frequency = <48000000>; |
| 384 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 385 | dmas = <&sdma 53>, <&sdma 54>; |
| 386 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 387 | }; |
| 388 | |
| 389 | uart4: serial@4806e000 { |
| 390 | compatible = "ti,omap4-uart"; |
| 391 | reg = <0x4806e000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 392 | interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 393 | ti,hwmods = "uart4"; |
| 394 | clock-frequency = <48000000>; |
| 395 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 396 | dmas = <&sdma 55>, <&sdma 56>; |
| 397 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 398 | }; |
| 399 | |
| 400 | uart5: serial@48066000 { |
| 401 | compatible = "ti,omap4-uart"; |
| 402 | reg = <0x48066000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 403 | interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 404 | ti,hwmods = "uart5"; |
| 405 | clock-frequency = <48000000>; |
| 406 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 407 | dmas = <&sdma 63>, <&sdma 64>; |
| 408 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 409 | }; |
| 410 | |
| 411 | uart6: serial@48068000 { |
| 412 | compatible = "ti,omap4-uart"; |
| 413 | reg = <0x48068000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 414 | interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 415 | ti,hwmods = "uart6"; |
| 416 | clock-frequency = <48000000>; |
| 417 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 418 | dmas = <&sdma 79>, <&sdma 80>; |
| 419 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 420 | }; |
| 421 | |
| 422 | uart7: serial@48420000 { |
| 423 | compatible = "ti,omap4-uart"; |
| 424 | reg = <0x48420000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 425 | interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 426 | ti,hwmods = "uart7"; |
| 427 | clock-frequency = <48000000>; |
| 428 | status = "disabled"; |
| 429 | }; |
| 430 | |
| 431 | uart8: serial@48422000 { |
| 432 | compatible = "ti,omap4-uart"; |
| 433 | reg = <0x48422000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 434 | interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 435 | ti,hwmods = "uart8"; |
| 436 | clock-frequency = <48000000>; |
| 437 | status = "disabled"; |
| 438 | }; |
| 439 | |
| 440 | uart9: serial@48424000 { |
| 441 | compatible = "ti,omap4-uart"; |
| 442 | reg = <0x48424000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 443 | interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 444 | ti,hwmods = "uart9"; |
| 445 | clock-frequency = <48000000>; |
| 446 | status = "disabled"; |
| 447 | }; |
| 448 | |
| 449 | uart10: serial@4ae2b000 { |
| 450 | compatible = "ti,omap4-uart"; |
| 451 | reg = <0x4ae2b000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 452 | interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 453 | ti,hwmods = "uart10"; |
| 454 | clock-frequency = <48000000>; |
| 455 | status = "disabled"; |
| 456 | }; |
| 457 | |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 458 | mailbox1: mailbox@4a0f4000 { |
| 459 | compatible = "ti,omap4-mailbox"; |
| 460 | reg = <0x4a0f4000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 461 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| 462 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 463 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 464 | ti,hwmods = "mailbox1"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 465 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 466 | ti,mbox-num-users = <3>; |
| 467 | ti,mbox-num-fifos = <8>; |
| 468 | status = "disabled"; |
| 469 | }; |
| 470 | |
| 471 | mailbox2: mailbox@4883a000 { |
| 472 | compatible = "ti,omap4-mailbox"; |
| 473 | reg = <0x4883a000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 474 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| 475 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
| 476 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, |
| 477 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 478 | ti,hwmods = "mailbox2"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 479 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 480 | ti,mbox-num-users = <4>; |
| 481 | ti,mbox-num-fifos = <12>; |
| 482 | status = "disabled"; |
| 483 | }; |
| 484 | |
| 485 | mailbox3: mailbox@4883c000 { |
| 486 | compatible = "ti,omap4-mailbox"; |
| 487 | reg = <0x4883c000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 488 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
| 489 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, |
| 490 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, |
| 491 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 492 | ti,hwmods = "mailbox3"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 493 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 494 | ti,mbox-num-users = <4>; |
| 495 | ti,mbox-num-fifos = <12>; |
| 496 | status = "disabled"; |
| 497 | }; |
| 498 | |
| 499 | mailbox4: mailbox@4883e000 { |
| 500 | compatible = "ti,omap4-mailbox"; |
| 501 | reg = <0x4883e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 502 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| 503 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| 504 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| 505 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 506 | ti,hwmods = "mailbox4"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 507 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 508 | ti,mbox-num-users = <4>; |
| 509 | ti,mbox-num-fifos = <12>; |
| 510 | status = "disabled"; |
| 511 | }; |
| 512 | |
| 513 | mailbox5: mailbox@48840000 { |
| 514 | compatible = "ti,omap4-mailbox"; |
| 515 | reg = <0x48840000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 516 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| 517 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| 518 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| 519 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 520 | ti,hwmods = "mailbox5"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 521 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 522 | ti,mbox-num-users = <4>; |
| 523 | ti,mbox-num-fifos = <12>; |
| 524 | status = "disabled"; |
| 525 | }; |
| 526 | |
| 527 | mailbox6: mailbox@48842000 { |
| 528 | compatible = "ti,omap4-mailbox"; |
| 529 | reg = <0x48842000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 530 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 531 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| 532 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| 533 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 534 | ti,hwmods = "mailbox6"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 535 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 536 | ti,mbox-num-users = <4>; |
| 537 | ti,mbox-num-fifos = <12>; |
| 538 | status = "disabled"; |
| 539 | }; |
| 540 | |
| 541 | mailbox7: mailbox@48844000 { |
| 542 | compatible = "ti,omap4-mailbox"; |
| 543 | reg = <0x48844000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 544 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| 545 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| 546 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, |
| 547 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 548 | ti,hwmods = "mailbox7"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 549 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 550 | ti,mbox-num-users = <4>; |
| 551 | ti,mbox-num-fifos = <12>; |
| 552 | status = "disabled"; |
| 553 | }; |
| 554 | |
| 555 | mailbox8: mailbox@48846000 { |
| 556 | compatible = "ti,omap4-mailbox"; |
| 557 | reg = <0x48846000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 558 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| 559 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| 560 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, |
| 561 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 562 | ti,hwmods = "mailbox8"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 563 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 564 | ti,mbox-num-users = <4>; |
| 565 | ti,mbox-num-fifos = <12>; |
| 566 | status = "disabled"; |
| 567 | }; |
| 568 | |
| 569 | mailbox9: mailbox@4885e000 { |
| 570 | compatible = "ti,omap4-mailbox"; |
| 571 | reg = <0x4885e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 572 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| 573 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| 574 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, |
| 575 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 576 | ti,hwmods = "mailbox9"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 577 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 578 | ti,mbox-num-users = <4>; |
| 579 | ti,mbox-num-fifos = <12>; |
| 580 | status = "disabled"; |
| 581 | }; |
| 582 | |
| 583 | mailbox10: mailbox@48860000 { |
| 584 | compatible = "ti,omap4-mailbox"; |
| 585 | reg = <0x48860000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 586 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| 587 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, |
| 588 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, |
| 589 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 590 | ti,hwmods = "mailbox10"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 591 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 592 | ti,mbox-num-users = <4>; |
| 593 | ti,mbox-num-fifos = <12>; |
| 594 | status = "disabled"; |
| 595 | }; |
| 596 | |
| 597 | mailbox11: mailbox@48862000 { |
| 598 | compatible = "ti,omap4-mailbox"; |
| 599 | reg = <0x48862000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 600 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
| 601 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| 602 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, |
| 603 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 604 | ti,hwmods = "mailbox11"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 605 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 606 | ti,mbox-num-users = <4>; |
| 607 | ti,mbox-num-fifos = <12>; |
| 608 | status = "disabled"; |
| 609 | }; |
| 610 | |
| 611 | mailbox12: mailbox@48864000 { |
| 612 | compatible = "ti,omap4-mailbox"; |
| 613 | reg = <0x48864000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 614 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
| 615 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, |
| 616 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| 617 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 618 | ti,hwmods = "mailbox12"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 619 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 620 | ti,mbox-num-users = <4>; |
| 621 | ti,mbox-num-fifos = <12>; |
| 622 | status = "disabled"; |
| 623 | }; |
| 624 | |
| 625 | mailbox13: mailbox@48802000 { |
| 626 | compatible = "ti,omap4-mailbox"; |
| 627 | reg = <0x48802000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 628 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| 629 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
| 630 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, |
| 631 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 632 | ti,hwmods = "mailbox13"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 633 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 634 | ti,mbox-num-users = <4>; |
| 635 | ti,mbox-num-fifos = <12>; |
| 636 | status = "disabled"; |
| 637 | }; |
| 638 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 639 | timer1: timer@4ae18000 { |
| 640 | compatible = "ti,omap5430-timer"; |
| 641 | reg = <0x4ae18000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 642 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 643 | ti,hwmods = "timer1"; |
| 644 | ti,timer-alwon; |
| 645 | }; |
| 646 | |
| 647 | timer2: timer@48032000 { |
| 648 | compatible = "ti,omap5430-timer"; |
| 649 | reg = <0x48032000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 650 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 651 | ti,hwmods = "timer2"; |
| 652 | }; |
| 653 | |
| 654 | timer3: timer@48034000 { |
| 655 | compatible = "ti,omap5430-timer"; |
| 656 | reg = <0x48034000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 657 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 658 | ti,hwmods = "timer3"; |
| 659 | }; |
| 660 | |
| 661 | timer4: timer@48036000 { |
| 662 | compatible = "ti,omap5430-timer"; |
| 663 | reg = <0x48036000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 664 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 665 | ti,hwmods = "timer4"; |
| 666 | }; |
| 667 | |
| 668 | timer5: timer@48820000 { |
| 669 | compatible = "ti,omap5430-timer"; |
| 670 | reg = <0x48820000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 671 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 672 | ti,hwmods = "timer5"; |
| 673 | ti,timer-dsp; |
| 674 | }; |
| 675 | |
| 676 | timer6: timer@48822000 { |
| 677 | compatible = "ti,omap5430-timer"; |
| 678 | reg = <0x48822000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 679 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 680 | ti,hwmods = "timer6"; |
| 681 | ti,timer-dsp; |
| 682 | ti,timer-pwm; |
| 683 | }; |
| 684 | |
| 685 | timer7: timer@48824000 { |
| 686 | compatible = "ti,omap5430-timer"; |
| 687 | reg = <0x48824000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 688 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 689 | ti,hwmods = "timer7"; |
| 690 | ti,timer-dsp; |
| 691 | }; |
| 692 | |
| 693 | timer8: timer@48826000 { |
| 694 | compatible = "ti,omap5430-timer"; |
| 695 | reg = <0x48826000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 696 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 697 | ti,hwmods = "timer8"; |
| 698 | ti,timer-dsp; |
| 699 | ti,timer-pwm; |
| 700 | }; |
| 701 | |
| 702 | timer9: timer@4803e000 { |
| 703 | compatible = "ti,omap5430-timer"; |
| 704 | reg = <0x4803e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 705 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 706 | ti,hwmods = "timer9"; |
| 707 | }; |
| 708 | |
| 709 | timer10: timer@48086000 { |
| 710 | compatible = "ti,omap5430-timer"; |
| 711 | reg = <0x48086000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 712 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 713 | ti,hwmods = "timer10"; |
| 714 | }; |
| 715 | |
| 716 | timer11: timer@48088000 { |
| 717 | compatible = "ti,omap5430-timer"; |
| 718 | reg = <0x48088000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 719 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 720 | ti,hwmods = "timer11"; |
| 721 | ti,timer-pwm; |
| 722 | }; |
| 723 | |
| 724 | timer13: timer@48828000 { |
| 725 | compatible = "ti,omap5430-timer"; |
| 726 | reg = <0x48828000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 727 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 728 | ti,hwmods = "timer13"; |
| 729 | status = "disabled"; |
| 730 | }; |
| 731 | |
| 732 | timer14: timer@4882a000 { |
| 733 | compatible = "ti,omap5430-timer"; |
| 734 | reg = <0x4882a000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 735 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 736 | ti,hwmods = "timer14"; |
| 737 | status = "disabled"; |
| 738 | }; |
| 739 | |
| 740 | timer15: timer@4882c000 { |
| 741 | compatible = "ti,omap5430-timer"; |
| 742 | reg = <0x4882c000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 743 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 744 | ti,hwmods = "timer15"; |
| 745 | status = "disabled"; |
| 746 | }; |
| 747 | |
| 748 | timer16: timer@4882e000 { |
| 749 | compatible = "ti,omap5430-timer"; |
| 750 | reg = <0x4882e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 751 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 752 | ti,hwmods = "timer16"; |
| 753 | status = "disabled"; |
| 754 | }; |
| 755 | |
| 756 | wdt2: wdt@4ae14000 { |
Lokesh Vutla | be66883 | 2014-11-12 10:54:15 +0530 | [diff] [blame] | 757 | compatible = "ti,omap3-wdt"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 758 | reg = <0x4ae14000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 759 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 760 | ti,hwmods = "wd_timer2"; |
| 761 | }; |
| 762 | |
Suman Anna | dbd7c19 | 2014-01-13 18:26:46 -0600 | [diff] [blame] | 763 | hwspinlock: spinlock@4a0f6000 { |
| 764 | compatible = "ti,omap4-hwspinlock"; |
| 765 | reg = <0x4a0f6000 0x1000>; |
| 766 | ti,hwmods = "spinlock"; |
| 767 | #hwlock-cells = <1>; |
| 768 | }; |
| 769 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 770 | dmm@4e000000 { |
| 771 | compatible = "ti,omap5-dmm"; |
| 772 | reg = <0x4e000000 0x800>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 773 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 774 | ti,hwmods = "dmm"; |
| 775 | }; |
| 776 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 777 | i2c1: i2c@48070000 { |
| 778 | compatible = "ti,omap4-i2c"; |
| 779 | reg = <0x48070000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 780 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 781 | #address-cells = <1>; |
| 782 | #size-cells = <0>; |
| 783 | ti,hwmods = "i2c1"; |
| 784 | status = "disabled"; |
| 785 | }; |
| 786 | |
| 787 | i2c2: i2c@48072000 { |
| 788 | compatible = "ti,omap4-i2c"; |
| 789 | reg = <0x48072000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 790 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 791 | #address-cells = <1>; |
| 792 | #size-cells = <0>; |
| 793 | ti,hwmods = "i2c2"; |
| 794 | status = "disabled"; |
| 795 | }; |
| 796 | |
| 797 | i2c3: i2c@48060000 { |
| 798 | compatible = "ti,omap4-i2c"; |
| 799 | reg = <0x48060000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 800 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 801 | #address-cells = <1>; |
| 802 | #size-cells = <0>; |
| 803 | ti,hwmods = "i2c3"; |
| 804 | status = "disabled"; |
| 805 | }; |
| 806 | |
| 807 | i2c4: i2c@4807a000 { |
| 808 | compatible = "ti,omap4-i2c"; |
| 809 | reg = <0x4807a000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 810 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 811 | #address-cells = <1>; |
| 812 | #size-cells = <0>; |
| 813 | ti,hwmods = "i2c4"; |
| 814 | status = "disabled"; |
| 815 | }; |
| 816 | |
| 817 | i2c5: i2c@4807c000 { |
| 818 | compatible = "ti,omap4-i2c"; |
| 819 | reg = <0x4807c000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 820 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 821 | #address-cells = <1>; |
| 822 | #size-cells = <0>; |
| 823 | ti,hwmods = "i2c5"; |
| 824 | status = "disabled"; |
| 825 | }; |
| 826 | |
| 827 | mmc1: mmc@4809c000 { |
| 828 | compatible = "ti,omap4-hsmmc"; |
| 829 | reg = <0x4809c000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 830 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 831 | ti,hwmods = "mmc1"; |
| 832 | ti,dual-volt; |
| 833 | ti,needs-special-reset; |
| 834 | dmas = <&sdma 61>, <&sdma 62>; |
| 835 | dma-names = "tx", "rx"; |
| 836 | status = "disabled"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 837 | pbias-supply = <&pbias_mmc_reg>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 838 | }; |
| 839 | |
| 840 | mmc2: mmc@480b4000 { |
| 841 | compatible = "ti,omap4-hsmmc"; |
| 842 | reg = <0x480b4000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 843 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 844 | ti,hwmods = "mmc2"; |
| 845 | ti,needs-special-reset; |
| 846 | dmas = <&sdma 47>, <&sdma 48>; |
| 847 | dma-names = "tx", "rx"; |
| 848 | status = "disabled"; |
| 849 | }; |
| 850 | |
| 851 | mmc3: mmc@480ad000 { |
| 852 | compatible = "ti,omap4-hsmmc"; |
| 853 | reg = <0x480ad000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 854 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 855 | ti,hwmods = "mmc3"; |
| 856 | ti,needs-special-reset; |
| 857 | dmas = <&sdma 77>, <&sdma 78>; |
| 858 | dma-names = "tx", "rx"; |
| 859 | status = "disabled"; |
| 860 | }; |
| 861 | |
| 862 | mmc4: mmc@480d1000 { |
| 863 | compatible = "ti,omap4-hsmmc"; |
| 864 | reg = <0x480d1000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 865 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 866 | ti,hwmods = "mmc4"; |
| 867 | ti,needs-special-reset; |
| 868 | dmas = <&sdma 57>, <&sdma 58>; |
| 869 | dma-names = "tx", "rx"; |
| 870 | status = "disabled"; |
| 871 | }; |
| 872 | |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 873 | abb_mpu: regulator-abb-mpu { |
| 874 | compatible = "ti,abb-v3"; |
| 875 | regulator-name = "abb_mpu"; |
| 876 | #address-cells = <0>; |
| 877 | #size-cells = <0>; |
| 878 | clocks = <&sys_clkin1>; |
| 879 | ti,settling-time = <50>; |
| 880 | ti,clock-cycles = <16>; |
| 881 | |
| 882 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
| 883 | <0x4ae06014 0x4>, <0x4a003b20 0x8>, |
| 884 | <0x4ae0c158 0x4>; |
| 885 | reg-names = "setup-address", "control-address", |
| 886 | "int-address", "efuse-address", |
| 887 | "ldo-address"; |
| 888 | ti,tranxdone-status-mask = <0x80>; |
| 889 | /* LDOVBBMPU_FBB_MUX_CTRL */ |
| 890 | ti,ldovbb-override-mask = <0x400>; |
| 891 | /* LDOVBBMPU_FBB_VSET_OUT */ |
| 892 | ti,ldovbb-vset-mask = <0x1F>; |
| 893 | |
| 894 | /* |
| 895 | * NOTE: only FBB mode used but actual vset will |
| 896 | * determine final biasing |
| 897 | */ |
| 898 | ti,abb_info = < |
| 899 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 900 | 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 901 | 1160000 0 0x4 0 0x02000000 0x01F00000 |
| 902 | 1210000 0 0x8 0 0x02000000 0x01F00000 |
| 903 | >; |
| 904 | }; |
| 905 | |
| 906 | abb_ivahd: regulator-abb-ivahd { |
| 907 | compatible = "ti,abb-v3"; |
| 908 | regulator-name = "abb_ivahd"; |
| 909 | #address-cells = <0>; |
| 910 | #size-cells = <0>; |
| 911 | clocks = <&sys_clkin1>; |
| 912 | ti,settling-time = <50>; |
| 913 | ti,clock-cycles = <16>; |
| 914 | |
| 915 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
| 916 | <0x4ae06010 0x4>, <0x4a0025cc 0x8>, |
| 917 | <0x4a002470 0x4>; |
| 918 | reg-names = "setup-address", "control-address", |
| 919 | "int-address", "efuse-address", |
| 920 | "ldo-address"; |
| 921 | ti,tranxdone-status-mask = <0x40000000>; |
| 922 | /* LDOVBBIVA_FBB_MUX_CTRL */ |
| 923 | ti,ldovbb-override-mask = <0x400>; |
| 924 | /* LDOVBBIVA_FBB_VSET_OUT */ |
| 925 | ti,ldovbb-vset-mask = <0x1F>; |
| 926 | |
| 927 | /* |
| 928 | * NOTE: only FBB mode used but actual vset will |
| 929 | * determine final biasing |
| 930 | */ |
| 931 | ti,abb_info = < |
| 932 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 933 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 934 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 935 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 936 | >; |
| 937 | }; |
| 938 | |
| 939 | abb_dspeve: regulator-abb-dspeve { |
| 940 | compatible = "ti,abb-v3"; |
| 941 | regulator-name = "abb_dspeve"; |
| 942 | #address-cells = <0>; |
| 943 | #size-cells = <0>; |
| 944 | clocks = <&sys_clkin1>; |
| 945 | ti,settling-time = <50>; |
| 946 | ti,clock-cycles = <16>; |
| 947 | |
| 948 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
| 949 | <0x4ae06010 0x4>, <0x4a0025e0 0x8>, |
| 950 | <0x4a00246c 0x4>; |
| 951 | reg-names = "setup-address", "control-address", |
| 952 | "int-address", "efuse-address", |
| 953 | "ldo-address"; |
| 954 | ti,tranxdone-status-mask = <0x20000000>; |
| 955 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ |
| 956 | ti,ldovbb-override-mask = <0x400>; |
| 957 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ |
| 958 | ti,ldovbb-vset-mask = <0x1F>; |
| 959 | |
| 960 | /* |
| 961 | * NOTE: only FBB mode used but actual vset will |
| 962 | * determine final biasing |
| 963 | */ |
| 964 | ti,abb_info = < |
| 965 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 966 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 967 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 968 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 969 | >; |
| 970 | }; |
| 971 | |
| 972 | abb_gpu: regulator-abb-gpu { |
| 973 | compatible = "ti,abb-v3"; |
| 974 | regulator-name = "abb_gpu"; |
| 975 | #address-cells = <0>; |
| 976 | #size-cells = <0>; |
| 977 | clocks = <&sys_clkin1>; |
| 978 | ti,settling-time = <50>; |
| 979 | ti,clock-cycles = <16>; |
| 980 | |
| 981 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
| 982 | <0x4ae06010 0x4>, <0x4a003b08 0x8>, |
| 983 | <0x4ae0c154 0x4>; |
| 984 | reg-names = "setup-address", "control-address", |
| 985 | "int-address", "efuse-address", |
| 986 | "ldo-address"; |
| 987 | ti,tranxdone-status-mask = <0x10000000>; |
| 988 | /* LDOVBBGPU_FBB_MUX_CTRL */ |
| 989 | ti,ldovbb-override-mask = <0x400>; |
| 990 | /* LDOVBBGPU_FBB_VSET_OUT */ |
| 991 | ti,ldovbb-vset-mask = <0x1F>; |
| 992 | |
| 993 | /* |
| 994 | * NOTE: only FBB mode used but actual vset will |
| 995 | * determine final biasing |
| 996 | */ |
| 997 | ti,abb_info = < |
| 998 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 999 | 1090000 0 0x0 0 0x02000000 0x01F00000 |
| 1000 | 1210000 0 0x4 0 0x02000000 0x01F00000 |
| 1001 | 1280000 0 0x8 0 0x02000000 0x01F00000 |
| 1002 | >; |
| 1003 | }; |
| 1004 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1005 | mcspi1: spi@48098000 { |
| 1006 | compatible = "ti,omap4-mcspi"; |
| 1007 | reg = <0x48098000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1008 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1009 | #address-cells = <1>; |
| 1010 | #size-cells = <0>; |
| 1011 | ti,hwmods = "mcspi1"; |
| 1012 | ti,spi-num-cs = <4>; |
| 1013 | dmas = <&sdma 35>, |
| 1014 | <&sdma 36>, |
| 1015 | <&sdma 37>, |
| 1016 | <&sdma 38>, |
| 1017 | <&sdma 39>, |
| 1018 | <&sdma 40>, |
| 1019 | <&sdma 41>, |
| 1020 | <&sdma 42>; |
| 1021 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 1022 | "tx2", "rx2", "tx3", "rx3"; |
| 1023 | status = "disabled"; |
| 1024 | }; |
| 1025 | |
| 1026 | mcspi2: spi@4809a000 { |
| 1027 | compatible = "ti,omap4-mcspi"; |
| 1028 | reg = <0x4809a000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1029 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1030 | #address-cells = <1>; |
| 1031 | #size-cells = <0>; |
| 1032 | ti,hwmods = "mcspi2"; |
| 1033 | ti,spi-num-cs = <2>; |
| 1034 | dmas = <&sdma 43>, |
| 1035 | <&sdma 44>, |
| 1036 | <&sdma 45>, |
| 1037 | <&sdma 46>; |
| 1038 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 1039 | status = "disabled"; |
| 1040 | }; |
| 1041 | |
| 1042 | mcspi3: spi@480b8000 { |
| 1043 | compatible = "ti,omap4-mcspi"; |
| 1044 | reg = <0x480b8000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1045 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1046 | #address-cells = <1>; |
| 1047 | #size-cells = <0>; |
| 1048 | ti,hwmods = "mcspi3"; |
| 1049 | ti,spi-num-cs = <2>; |
| 1050 | dmas = <&sdma 15>, <&sdma 16>; |
| 1051 | dma-names = "tx0", "rx0"; |
| 1052 | status = "disabled"; |
| 1053 | }; |
| 1054 | |
| 1055 | mcspi4: spi@480ba000 { |
| 1056 | compatible = "ti,omap4-mcspi"; |
| 1057 | reg = <0x480ba000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1058 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1059 | #address-cells = <1>; |
| 1060 | #size-cells = <0>; |
| 1061 | ti,hwmods = "mcspi4"; |
| 1062 | ti,spi-num-cs = <1>; |
| 1063 | dmas = <&sdma 70>, <&sdma 71>; |
| 1064 | dma-names = "tx0", "rx0"; |
| 1065 | status = "disabled"; |
| 1066 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1067 | |
| 1068 | qspi: qspi@4b300000 { |
| 1069 | compatible = "ti,dra7xxx-qspi"; |
| 1070 | reg = <0x4b300000 0x100>; |
| 1071 | reg-names = "qspi_base"; |
| 1072 | #address-cells = <1>; |
| 1073 | #size-cells = <0>; |
| 1074 | ti,hwmods = "qspi"; |
| 1075 | clocks = <&qspi_gfclk_div>; |
| 1076 | clock-names = "fck"; |
| 1077 | num-cs = <4>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1078 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1079 | status = "disabled"; |
| 1080 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1081 | |
| 1082 | omap_control_sata: control-phy@4a002374 { |
| 1083 | compatible = "ti,control-phy-pipe3"; |
| 1084 | reg = <0x4a002374 0x4>; |
| 1085 | reg-names = "power"; |
| 1086 | clocks = <&sys_clkin1>; |
| 1087 | clock-names = "sysclk"; |
| 1088 | }; |
| 1089 | |
| 1090 | /* OCP2SCP3 */ |
| 1091 | ocp2scp@4a090000 { |
| 1092 | compatible = "ti,omap-ocp2scp"; |
| 1093 | #address-cells = <1>; |
| 1094 | #size-cells = <1>; |
| 1095 | ranges; |
| 1096 | reg = <0x4a090000 0x20>; |
| 1097 | ti,hwmods = "ocp2scp3"; |
| 1098 | sata_phy: phy@4A096000 { |
| 1099 | compatible = "ti,phy-pipe3-sata"; |
| 1100 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 1101 | <0x4A096400 0x64>, /* phy_tx */ |
| 1102 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 1103 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1104 | ctrl-module = <&omap_control_sata>; |
| 1105 | clocks = <&sys_clkin1>; |
| 1106 | clock-names = "sysclk"; |
| 1107 | #phy-cells = <0>; |
| 1108 | }; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1109 | |
| 1110 | pcie1_phy: pciephy@4a094000 { |
| 1111 | compatible = "ti,phy-pipe3-pcie"; |
| 1112 | reg = <0x4a094000 0x80>, /* phy_rx */ |
| 1113 | <0x4a094400 0x64>; /* phy_tx */ |
| 1114 | reg-names = "phy_rx", "phy_tx"; |
| 1115 | ctrl-module = <&omap_control_pcie1phy>; |
| 1116 | clocks = <&dpll_pcie_ref_ck>, |
| 1117 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1118 | <&optfclk_pciephy1_32khz>, |
| 1119 | <&optfclk_pciephy1_clk>, |
| 1120 | <&optfclk_pciephy1_div_clk>, |
| 1121 | <&optfclk_pciephy_div>; |
| 1122 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1123 | "wkupclk", "refclk", |
| 1124 | "div-clk", "phy-div"; |
| 1125 | #phy-cells = <0>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1126 | ti,hwmods = "pcie1-phy"; |
| 1127 | }; |
| 1128 | |
| 1129 | pcie2_phy: pciephy@4a095000 { |
| 1130 | compatible = "ti,phy-pipe3-pcie"; |
| 1131 | reg = <0x4a095000 0x80>, /* phy_rx */ |
| 1132 | <0x4a095400 0x64>; /* phy_tx */ |
| 1133 | reg-names = "phy_rx", "phy_tx"; |
| 1134 | ctrl-module = <&omap_control_pcie2phy>; |
| 1135 | clocks = <&dpll_pcie_ref_ck>, |
| 1136 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1137 | <&optfclk_pciephy2_32khz>, |
| 1138 | <&optfclk_pciephy2_clk>, |
| 1139 | <&optfclk_pciephy2_div_clk>, |
| 1140 | <&optfclk_pciephy_div>; |
| 1141 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1142 | "wkupclk", "refclk", |
| 1143 | "div-clk", "phy-div"; |
| 1144 | #phy-cells = <0>; |
| 1145 | ti,hwmods = "pcie2-phy"; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1146 | status = "disabled"; |
| 1147 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1148 | }; |
| 1149 | |
| 1150 | sata: sata@4a141100 { |
| 1151 | compatible = "snps,dwc-ahci"; |
| 1152 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1153 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1154 | phys = <&sata_phy>; |
| 1155 | phy-names = "sata-phy"; |
| 1156 | clocks = <&sata_ref_clk>; |
| 1157 | ti,hwmods = "sata"; |
| 1158 | }; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1159 | |
Kishon Vijay Abraham I | d1ff66b | 2014-07-14 16:12:21 +0530 | [diff] [blame] | 1160 | omap_control_pcie1phy: control-phy@0x4a003c40 { |
| 1161 | compatible = "ti,control-phy-pcie"; |
| 1162 | reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1163 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1164 | clocks = <&sys_clkin1>; |
| 1165 | clock-names = "sysclk"; |
| 1166 | }; |
| 1167 | |
| 1168 | omap_control_pcie2phy: control-pcie@0x4a003c44 { |
| 1169 | compatible = "ti,control-phy-pcie"; |
| 1170 | reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1171 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1172 | clocks = <&sys_clkin1>; |
| 1173 | clock-names = "sysclk"; |
| 1174 | status = "disabled"; |
| 1175 | }; |
| 1176 | |
Lokesh Vutla | bc07831 | 2014-11-19 17:53:08 +0530 | [diff] [blame] | 1177 | rtc@48838000 { |
| 1178 | compatible = "ti,am3352-rtc"; |
| 1179 | reg = <0x48838000 0x100>; |
| 1180 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, |
| 1181 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; |
| 1182 | ti,hwmods = "rtcss"; |
| 1183 | clocks = <&sys_32k_ck>; |
| 1184 | }; |
| 1185 | |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1186 | omap_control_usb2phy1: control-phy@4a002300 { |
| 1187 | compatible = "ti,control-phy-usb2"; |
| 1188 | reg = <0x4a002300 0x4>; |
| 1189 | reg-names = "power"; |
| 1190 | }; |
| 1191 | |
| 1192 | omap_control_usb3phy1: control-phy@4a002370 { |
| 1193 | compatible = "ti,control-phy-pipe3"; |
| 1194 | reg = <0x4a002370 0x4>; |
| 1195 | reg-names = "power"; |
| 1196 | }; |
| 1197 | |
| 1198 | omap_control_usb2phy2: control-phy@0x4a002e74 { |
| 1199 | compatible = "ti,control-phy-usb2-dra7"; |
| 1200 | reg = <0x4a002e74 0x4>; |
| 1201 | reg-names = "power"; |
| 1202 | }; |
| 1203 | |
| 1204 | /* OCP2SCP1 */ |
| 1205 | ocp2scp@4a080000 { |
| 1206 | compatible = "ti,omap-ocp2scp"; |
| 1207 | #address-cells = <1>; |
| 1208 | #size-cells = <1>; |
| 1209 | ranges; |
| 1210 | reg = <0x4a080000 0x20>; |
| 1211 | ti,hwmods = "ocp2scp1"; |
| 1212 | |
| 1213 | usb2_phy1: phy@4a084000 { |
| 1214 | compatible = "ti,omap-usb2"; |
| 1215 | reg = <0x4a084000 0x400>; |
| 1216 | ctrl-module = <&omap_control_usb2phy1>; |
| 1217 | clocks = <&usb_phy1_always_on_clk32k>, |
| 1218 | <&usb_otg_ss1_refclk960m>; |
| 1219 | clock-names = "wkupclk", |
| 1220 | "refclk"; |
| 1221 | #phy-cells = <0>; |
| 1222 | }; |
| 1223 | |
| 1224 | usb2_phy2: phy@4a085000 { |
| 1225 | compatible = "ti,omap-usb2"; |
| 1226 | reg = <0x4a085000 0x400>; |
| 1227 | ctrl-module = <&omap_control_usb2phy2>; |
| 1228 | clocks = <&usb_phy2_always_on_clk32k>, |
| 1229 | <&usb_otg_ss2_refclk960m>; |
| 1230 | clock-names = "wkupclk", |
| 1231 | "refclk"; |
| 1232 | #phy-cells = <0>; |
| 1233 | }; |
| 1234 | |
| 1235 | usb3_phy1: phy@4a084400 { |
| 1236 | compatible = "ti,omap-usb3"; |
| 1237 | reg = <0x4a084400 0x80>, |
| 1238 | <0x4a084800 0x64>, |
| 1239 | <0x4a084c00 0x40>; |
| 1240 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1241 | ctrl-module = <&omap_control_usb3phy1>; |
| 1242 | clocks = <&usb_phy3_always_on_clk32k>, |
| 1243 | <&sys_clkin1>, |
| 1244 | <&usb_otg_ss1_refclk960m>; |
| 1245 | clock-names = "wkupclk", |
| 1246 | "sysclk", |
| 1247 | "refclk"; |
| 1248 | #phy-cells = <0>; |
| 1249 | }; |
| 1250 | }; |
| 1251 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1252 | omap_dwc3_1: omap_dwc3_1@48880000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1253 | compatible = "ti,dwc3"; |
| 1254 | ti,hwmods = "usb_otg_ss1"; |
| 1255 | reg = <0x48880000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1256 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1257 | #address-cells = <1>; |
| 1258 | #size-cells = <1>; |
| 1259 | utmi-mode = <2>; |
| 1260 | ranges; |
| 1261 | usb1: usb@48890000 { |
| 1262 | compatible = "snps,dwc3"; |
| 1263 | reg = <0x48890000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1264 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1265 | phys = <&usb2_phy1>, <&usb3_phy1>; |
| 1266 | phy-names = "usb2-phy", "usb3-phy"; |
| 1267 | tx-fifo-resize; |
| 1268 | maximum-speed = "super-speed"; |
| 1269 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1270 | snps,dis_u3_susphy_quirk; |
| 1271 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1272 | }; |
| 1273 | }; |
| 1274 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1275 | omap_dwc3_2: omap_dwc3_2@488c0000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1276 | compatible = "ti,dwc3"; |
| 1277 | ti,hwmods = "usb_otg_ss2"; |
| 1278 | reg = <0x488c0000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1279 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1280 | #address-cells = <1>; |
| 1281 | #size-cells = <1>; |
| 1282 | utmi-mode = <2>; |
| 1283 | ranges; |
| 1284 | usb2: usb@488d0000 { |
| 1285 | compatible = "snps,dwc3"; |
| 1286 | reg = <0x488d0000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1287 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1288 | phys = <&usb2_phy2>; |
| 1289 | phy-names = "usb2-phy"; |
| 1290 | tx-fifo-resize; |
| 1291 | maximum-speed = "high-speed"; |
| 1292 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1293 | snps,dis_u3_susphy_quirk; |
| 1294 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1295 | }; |
| 1296 | }; |
| 1297 | |
| 1298 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1299 | omap_dwc3_3: omap_dwc3_3@48900000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1300 | compatible = "ti,dwc3"; |
| 1301 | ti,hwmods = "usb_otg_ss3"; |
| 1302 | reg = <0x48900000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1303 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1304 | #address-cells = <1>; |
| 1305 | #size-cells = <1>; |
| 1306 | utmi-mode = <2>; |
| 1307 | ranges; |
| 1308 | status = "disabled"; |
| 1309 | usb3: usb@48910000 { |
| 1310 | compatible = "snps,dwc3"; |
| 1311 | reg = <0x48910000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1312 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1313 | tx-fifo-resize; |
| 1314 | maximum-speed = "high-speed"; |
| 1315 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1316 | snps,dis_u3_susphy_quirk; |
| 1317 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1318 | }; |
| 1319 | }; |
| 1320 | |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1321 | elm: elm@48078000 { |
| 1322 | compatible = "ti,am3352-elm"; |
| 1323 | reg = <0x48078000 0xfc0>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1324 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1325 | ti,hwmods = "elm"; |
| 1326 | status = "disabled"; |
| 1327 | }; |
| 1328 | |
| 1329 | gpmc: gpmc@50000000 { |
| 1330 | compatible = "ti,am3352-gpmc"; |
| 1331 | ti,hwmods = "gpmc"; |
| 1332 | reg = <0x50000000 0x37c>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1333 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1334 | gpmc,num-cs = <8>; |
| 1335 | gpmc,num-waitpins = <2>; |
| 1336 | #address-cells = <2>; |
| 1337 | #size-cells = <1>; |
| 1338 | status = "disabled"; |
| 1339 | }; |
Peter Ujfalusi | 2ca0945 | 2014-05-07 13:20:48 +0300 | [diff] [blame] | 1340 | |
| 1341 | atl: atl@4843c000 { |
| 1342 | compatible = "ti,dra7-atl"; |
| 1343 | reg = <0x4843c000 0x3ff>; |
| 1344 | ti,hwmods = "atl"; |
| 1345 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, |
| 1346 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; |
| 1347 | clocks = <&atl_gfclk_mux>; |
| 1348 | clock-names = "fck"; |
| 1349 | status = "disabled"; |
| 1350 | }; |
Olof Johansson | 412a9bb | 2014-07-18 22:16:15 -0700 | [diff] [blame] | 1351 | |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1352 | crossbar_mpu: crossbar@4a020000 { |
| 1353 | compatible = "ti,irq-crossbar"; |
| 1354 | reg = <0x4a002a48 0x130>; |
| 1355 | ti,max-irqs = <160>; |
| 1356 | ti,max-crossbar-sources = <MAX_SOURCES>; |
| 1357 | ti,reg-size = <2>; |
| 1358 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; |
| 1359 | ti,irqs-skip = <10 133 139 140>; |
| 1360 | ti,irqs-safe-map = <0>; |
| 1361 | }; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1362 | |
| 1363 | mac: ethernet@4a100000 { |
| 1364 | compatible = "ti,cpsw"; |
| 1365 | ti,hwmods = "gmac"; |
| 1366 | clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; |
| 1367 | clock-names = "fck", "cpts"; |
| 1368 | cpdma_channels = <8>; |
| 1369 | ale_entries = <1024>; |
| 1370 | bd_ram_size = <0x2000>; |
| 1371 | no_bd_ram = <0>; |
| 1372 | rx_descs = <64>; |
| 1373 | mac_control = <0x20>; |
| 1374 | slaves = <2>; |
| 1375 | active_slave = <0>; |
| 1376 | cpts_clock_mult = <0x80000000>; |
| 1377 | cpts_clock_shift = <29>; |
| 1378 | reg = <0x48484000 0x1000 |
| 1379 | 0x48485200 0x2E00>; |
| 1380 | #address-cells = <1>; |
| 1381 | #size-cells = <1>; |
| 1382 | /* |
| 1383 | * rx_thresh_pend |
| 1384 | * rx_pend |
| 1385 | * tx_pend |
| 1386 | * misc_pend |
| 1387 | */ |
| 1388 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| 1389 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| 1390 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| 1391 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; |
| 1392 | ranges; |
| 1393 | status = "disabled"; |
| 1394 | |
| 1395 | davinci_mdio: mdio@48485000 { |
| 1396 | compatible = "ti,davinci_mdio"; |
| 1397 | #address-cells = <1>; |
| 1398 | #size-cells = <0>; |
| 1399 | ti,hwmods = "davinci_mdio"; |
| 1400 | bus_freq = <1000000>; |
| 1401 | reg = <0x48485000 0x100>; |
| 1402 | }; |
| 1403 | |
| 1404 | cpsw_emac0: slave@48480200 { |
| 1405 | /* Filled in by U-Boot */ |
| 1406 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1407 | }; |
| 1408 | |
| 1409 | cpsw_emac1: slave@48480300 { |
| 1410 | /* Filled in by U-Boot */ |
| 1411 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1412 | }; |
| 1413 | |
| 1414 | phy_sel: cpsw-phy-sel@4a002554 { |
| 1415 | compatible = "ti,dra7xx-cpsw-phy-sel"; |
| 1416 | reg= <0x4a002554 0x4>; |
| 1417 | reg-names = "gmii-sel"; |
| 1418 | }; |
| 1419 | }; |
| 1420 | |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1421 | dcan1: can@481cc000 { |
| 1422 | compatible = "ti,dra7-d_can"; |
| 1423 | ti,hwmods = "dcan1"; |
| 1424 | reg = <0x4ae3c000 0x2000>; |
| 1425 | syscon-raminit = <&dra7_ctrl_core 0x558 0>; |
| 1426 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| 1427 | clocks = <&dcan1_sys_clk_mux>; |
| 1428 | status = "disabled"; |
| 1429 | }; |
| 1430 | |
| 1431 | dcan2: can@481d0000 { |
| 1432 | compatible = "ti,dra7-d_can"; |
| 1433 | ti,hwmods = "dcan2"; |
| 1434 | reg = <0x48480000 0x2000>; |
| 1435 | syscon-raminit = <&dra7_ctrl_core 0x558 1>; |
| 1436 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| 1437 | clocks = <&sys_clkin1>; |
| 1438 | status = "disabled"; |
| 1439 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1440 | }; |
Keerthy | f7397ed | 2015-03-23 14:39:38 -0500 | [diff] [blame^] | 1441 | |
| 1442 | thermal_zones: thermal-zones { |
| 1443 | #include "omap4-cpu-thermal.dtsi" |
| 1444 | #include "omap5-gpu-thermal.dtsi" |
| 1445 | #include "omap5-core-thermal.dtsi" |
| 1446 | }; |
| 1447 | |
| 1448 | }; |
| 1449 | |
| 1450 | &cpu_thermal { |
| 1451 | polling-delay = <500>; /* milliseconds */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1452 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 1453 | |
| 1454 | /include/ "dra7xx-clocks.dtsi" |