Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Jerome Glisse <glisse@freedesktop.org> |
| 29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> |
| 30 | * Dave Airlie |
| 31 | */ |
| 32 | #include <ttm/ttm_bo_api.h> |
| 33 | #include <ttm/ttm_bo_driver.h> |
| 34 | #include <ttm/ttm_placement.h> |
| 35 | #include <ttm/ttm_module.h> |
Pauli Nieminen | 8d7cddc | 2010-04-01 12:44:59 +0000 | [diff] [blame] | 36 | #include <ttm/ttm_page_alloc.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | #include <drm/drmP.h> |
| 38 | #include <drm/radeon_drm.h> |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 39 | #include <linux/seq_file.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 40 | #include <linux/slab.h> |
Chris Metcalf | 4cfe762 | 2013-02-01 13:44:33 -0500 | [diff] [blame] | 41 | #include <linux/swiotlb.h> |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 42 | #include <linux/swap.h> |
| 43 | #include <linux/pagemap.h> |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 44 | #include <linux/debugfs.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 45 | #include "radeon_reg.h" |
| 46 | #include "radeon.h" |
| 47 | |
| 48 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) |
| 49 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 50 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 51 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 52 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 53 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
| 54 | { |
| 55 | struct radeon_mman *mman; |
| 56 | struct radeon_device *rdev; |
| 57 | |
| 58 | mman = container_of(bdev, struct radeon_mman, bdev); |
| 59 | rdev = container_of(mman, struct radeon_device, mman); |
| 60 | return rdev; |
| 61 | } |
| 62 | |
| 63 | |
| 64 | /* |
| 65 | * Global memory. |
| 66 | */ |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 67 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 68 | { |
| 69 | return ttm_mem_global_init(ref->object); |
| 70 | } |
| 71 | |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 72 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 73 | { |
| 74 | ttm_mem_global_release(ref->object); |
| 75 | } |
| 76 | |
| 77 | static int radeon_ttm_global_init(struct radeon_device *rdev) |
| 78 | { |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 79 | struct drm_global_reference *global_ref; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 80 | int r; |
| 81 | |
| 82 | rdev->mman.mem_global_referenced = false; |
| 83 | global_ref = &rdev->mman.mem_global_ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 84 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 85 | global_ref->size = sizeof(struct ttm_mem_global); |
| 86 | global_ref->init = &radeon_ttm_mem_global_init; |
| 87 | global_ref->release = &radeon_ttm_mem_global_release; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 88 | r = drm_global_item_ref(global_ref); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 89 | if (r != 0) { |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 90 | DRM_ERROR("Failed setting up TTM memory accounting " |
| 91 | "subsystem.\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 92 | return r; |
| 93 | } |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 94 | |
| 95 | rdev->mman.bo_global_ref.mem_glob = |
| 96 | rdev->mman.mem_global_ref.object; |
| 97 | global_ref = &rdev->mman.bo_global_ref.ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 98 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
Thomas Hellstrom | 7f5f4db | 2009-08-20 10:29:08 +0200 | [diff] [blame] | 99 | global_ref->size = sizeof(struct ttm_bo_global); |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 100 | global_ref->init = &ttm_bo_global_init; |
| 101 | global_ref->release = &ttm_bo_global_release; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 102 | r = drm_global_item_ref(global_ref); |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 103 | if (r != 0) { |
| 104 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 105 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 106 | return r; |
| 107 | } |
| 108 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | rdev->mman.mem_global_referenced = true; |
| 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | static void radeon_ttm_global_fini(struct radeon_device *rdev) |
| 114 | { |
| 115 | if (rdev->mman.mem_global_referenced) { |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 116 | drm_global_item_unref(&rdev->mman.bo_global_ref.ref); |
| 117 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 118 | rdev->mman.mem_global_referenced = false; |
| 119 | } |
| 120 | } |
| 121 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 122 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
| 123 | { |
| 124 | return 0; |
| 125 | } |
| 126 | |
| 127 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, |
| 128 | struct ttm_mem_type_manager *man) |
| 129 | { |
| 130 | struct radeon_device *rdev; |
| 131 | |
| 132 | rdev = radeon_get_rdev(bdev); |
| 133 | |
| 134 | switch (type) { |
| 135 | case TTM_PL_SYSTEM: |
| 136 | /* System memory */ |
| 137 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
| 138 | man->available_caching = TTM_PL_MASK_CACHING; |
| 139 | man->default_caching = TTM_PL_FLAG_CACHED; |
| 140 | break; |
| 141 | case TTM_PL_TT: |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 142 | man->func = &ttm_bo_manager_func; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 143 | man->gpu_offset = rdev->mc.gtt_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 144 | man->available_caching = TTM_PL_MASK_CACHING; |
| 145 | man->default_caching = TTM_PL_FLAG_CACHED; |
Michel Dänzer | 55c9327 | 2009-06-15 16:56:11 +0200 | [diff] [blame] | 146 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
Daniel Vetter | a7fb8a2 | 2015-09-09 16:45:52 +0200 | [diff] [blame] | 147 | #if IS_ENABLED(CONFIG_AGP) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 148 | if (rdev->flags & RADEON_IS_AGP) { |
Daniel Vetter | d990675 | 2013-12-11 11:34:35 +0100 | [diff] [blame] | 149 | if (!rdev->ddev->agp) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 150 | DRM_ERROR("AGP is not enabled for memory type %u\n", |
| 151 | (unsigned)type); |
| 152 | return -EINVAL; |
| 153 | } |
Michel Dänzer | 55c9327 | 2009-06-15 16:56:11 +0200 | [diff] [blame] | 154 | if (!rdev->ddev->agp->cant_use_aperture) |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 155 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 156 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
| 157 | TTM_PL_FLAG_WC; |
| 158 | man->default_caching = TTM_PL_FLAG_WC; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 159 | } |
Jerome Glisse | 0c321c7 | 2010-04-07 10:21:27 +0000 | [diff] [blame] | 160 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | break; |
| 162 | case TTM_PL_VRAM: |
| 163 | /* "On-card" video ram */ |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 164 | man->func = &ttm_bo_manager_func; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 165 | man->gpu_offset = rdev->mc.vram_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 166 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 167 | TTM_MEMTYPE_FLAG_MAPPABLE; |
| 168 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; |
| 169 | man->default_caching = TTM_PL_FLAG_WC; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 170 | break; |
| 171 | default: |
| 172 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); |
| 173 | return -EINVAL; |
| 174 | } |
| 175 | return 0; |
| 176 | } |
| 177 | |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 178 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
| 179 | struct ttm_placement *placement) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 180 | { |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 181 | static struct ttm_place placements = { |
| 182 | .fpfn = 0, |
| 183 | .lpfn = 0, |
| 184 | .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM |
| 185 | }; |
| 186 | |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 187 | struct radeon_bo *rbo; |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 188 | |
| 189 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 190 | placement->placement = &placements; |
| 191 | placement->busy_placement = &placements; |
| 192 | placement->num_placement = 1; |
| 193 | placement->num_busy_placement = 1; |
| 194 | return; |
| 195 | } |
| 196 | rbo = container_of(bo, struct radeon_bo, tbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 197 | switch (bo->mem.mem_type) { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 198 | case TTM_PL_VRAM: |
Alex Deucher | 5e5c21c | 2014-12-03 00:03:49 -0500 | [diff] [blame] | 199 | if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) |
Dave Airlie | 9270eb1 | 2010-01-13 09:21:49 +1000 | [diff] [blame] | 200 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
Michel Dänzer | 2a85aed | 2014-10-09 18:55:04 +0900 | [diff] [blame] | 201 | else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && |
| 202 | bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { |
| 203 | unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
| 204 | int i; |
| 205 | |
| 206 | /* Try evicting to the CPU inaccessible part of VRAM |
| 207 | * first, but only set GTT as busy placement, so this |
| 208 | * BO will be evicted to GTT rather than causing other |
| 209 | * BOs to be evicted from VRAM |
| 210 | */ |
| 211 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | |
| 212 | RADEON_GEM_DOMAIN_GTT); |
| 213 | rbo->placement.num_busy_placement = 0; |
| 214 | for (i = 0; i < rbo->placement.num_placement; i++) { |
| 215 | if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { |
| 216 | if (rbo->placements[0].fpfn < fpfn) |
| 217 | rbo->placements[0].fpfn = fpfn; |
| 218 | } else { |
| 219 | rbo->placement.busy_placement = |
| 220 | &rbo->placements[i]; |
| 221 | rbo->placement.num_busy_placement = 1; |
| 222 | } |
| 223 | } |
| 224 | } else |
Dave Airlie | 9270eb1 | 2010-01-13 09:21:49 +1000 | [diff] [blame] | 225 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 226 | break; |
| 227 | case TTM_PL_TT: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 228 | default: |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 229 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 230 | } |
Jerome Glisse | eaa5fd1 | 2009-12-09 21:57:37 +0100 | [diff] [blame] | 231 | *placement = rbo->placement; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) |
| 235 | { |
David Herrmann | acb4652 | 2013-08-25 18:28:59 +0200 | [diff] [blame] | 236 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
| 237 | |
| 238 | return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | static void radeon_move_null(struct ttm_buffer_object *bo, |
| 242 | struct ttm_mem_reg *new_mem) |
| 243 | { |
| 244 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 245 | |
| 246 | BUG_ON(old_mem->mm_node != NULL); |
| 247 | *old_mem = *new_mem; |
| 248 | new_mem->mm_node = NULL; |
| 249 | } |
| 250 | |
| 251 | static int radeon_move_blit(struct ttm_buffer_object *bo, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 252 | bool evict, bool no_wait_gpu, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 253 | struct ttm_mem_reg *new_mem, |
| 254 | struct ttm_mem_reg *old_mem) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 255 | { |
| 256 | struct radeon_device *rdev; |
| 257 | uint64_t old_start, new_start; |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 258 | struct radeon_fence *fence; |
Christian König | 57d20a4 | 2014-09-04 20:01:53 +0200 | [diff] [blame] | 259 | unsigned num_pages; |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 260 | int r, ridx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 261 | |
| 262 | rdev = radeon_get_rdev(bo->bdev); |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 263 | ridx = radeon_copy_ring_index(rdev); |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 264 | old_start = old_mem->start << PAGE_SHIFT; |
| 265 | new_start = new_mem->start << PAGE_SHIFT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 266 | |
| 267 | switch (old_mem->mem_type) { |
| 268 | case TTM_PL_VRAM: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 269 | old_start += rdev->mc.vram_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 270 | break; |
| 271 | case TTM_PL_TT: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 272 | old_start += rdev->mc.gtt_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 273 | break; |
| 274 | default: |
| 275 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); |
| 276 | return -EINVAL; |
| 277 | } |
| 278 | switch (new_mem->mem_type) { |
| 279 | case TTM_PL_VRAM: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 280 | new_start += rdev->mc.vram_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | break; |
| 282 | case TTM_PL_TT: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 283 | new_start += rdev->mc.gtt_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 284 | break; |
| 285 | default: |
| 286 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); |
| 287 | return -EINVAL; |
| 288 | } |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 289 | if (!rdev->ring[ridx].ready) { |
Alex Deucher | 3000bf3 | 2012-01-05 22:11:07 -0500 | [diff] [blame] | 290 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 291 | return -EINVAL; |
| 292 | } |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 293 | |
| 294 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); |
| 295 | |
Christian König | 57d20a4 | 2014-09-04 20:01:53 +0200 | [diff] [blame] | 296 | num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
| 297 | fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv); |
| 298 | if (IS_ERR(fence)) |
| 299 | return PTR_ERR(fence); |
| 300 | |
Maarten Lankhorst | f2c24b8 | 2014-04-02 17:14:48 +0200 | [diff] [blame] | 301 | r = ttm_bo_move_accel_cleanup(bo, &fence->base, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 302 | evict, no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | radeon_fence_unref(&fence); |
| 304 | return r; |
| 305 | } |
| 306 | |
| 307 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 308 | bool evict, bool interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 309 | bool no_wait_gpu, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | struct ttm_mem_reg *new_mem) |
| 311 | { |
| 312 | struct radeon_device *rdev; |
| 313 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 314 | struct ttm_mem_reg tmp_mem; |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 315 | struct ttm_place placements; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 316 | struct ttm_placement placement; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 317 | int r; |
| 318 | |
| 319 | rdev = radeon_get_rdev(bo->bdev); |
| 320 | tmp_mem = *new_mem; |
| 321 | tmp_mem.mm_node = NULL; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 322 | placement.num_placement = 1; |
| 323 | placement.placement = &placements; |
| 324 | placement.num_busy_placement = 1; |
| 325 | placement.busy_placement = &placements; |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 326 | placements.fpfn = 0; |
| 327 | placements.lpfn = 0; |
| 328 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 329 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 330 | interruptible, no_wait_gpu); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 331 | if (unlikely(r)) { |
| 332 | return r; |
| 333 | } |
Dave Airlie | df67bed | 2009-10-30 13:31:26 +1000 | [diff] [blame] | 334 | |
| 335 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); |
| 336 | if (unlikely(r)) { |
| 337 | goto out_cleanup; |
| 338 | } |
| 339 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 340 | r = ttm_tt_bind(bo->ttm, &tmp_mem); |
| 341 | if (unlikely(r)) { |
| 342 | goto out_cleanup; |
| 343 | } |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 344 | r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 345 | if (unlikely(r)) { |
| 346 | goto out_cleanup; |
| 347 | } |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 348 | r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 349 | out_cleanup: |
Ben Skeggs | 42311ff | 2010-08-04 12:07:08 +1000 | [diff] [blame] | 350 | ttm_bo_mem_put(bo, &tmp_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 351 | return r; |
| 352 | } |
| 353 | |
| 354 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 355 | bool evict, bool interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 356 | bool no_wait_gpu, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 357 | struct ttm_mem_reg *new_mem) |
| 358 | { |
| 359 | struct radeon_device *rdev; |
| 360 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 361 | struct ttm_mem_reg tmp_mem; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 362 | struct ttm_placement placement; |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 363 | struct ttm_place placements; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 364 | int r; |
| 365 | |
| 366 | rdev = radeon_get_rdev(bo->bdev); |
| 367 | tmp_mem = *new_mem; |
| 368 | tmp_mem.mm_node = NULL; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 369 | placement.num_placement = 1; |
| 370 | placement.placement = &placements; |
| 371 | placement.num_busy_placement = 1; |
| 372 | placement.busy_placement = &placements; |
Christian König | f1217ed | 2014-08-27 13:16:04 +0200 | [diff] [blame] | 373 | placements.fpfn = 0; |
| 374 | placements.lpfn = 0; |
| 375 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 376 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, |
| 377 | interruptible, no_wait_gpu); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 378 | if (unlikely(r)) { |
| 379 | return r; |
| 380 | } |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 381 | r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 382 | if (unlikely(r)) { |
| 383 | goto out_cleanup; |
| 384 | } |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 385 | r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 386 | if (unlikely(r)) { |
| 387 | goto out_cleanup; |
| 388 | } |
| 389 | out_cleanup: |
Ben Skeggs | 42311ff | 2010-08-04 12:07:08 +1000 | [diff] [blame] | 390 | ttm_bo_mem_put(bo, &tmp_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 391 | return r; |
| 392 | } |
| 393 | |
| 394 | static int radeon_bo_move(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 395 | bool evict, bool interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 396 | bool no_wait_gpu, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 397 | struct ttm_mem_reg *new_mem) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 398 | { |
| 399 | struct radeon_device *rdev; |
| 400 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 401 | int r; |
| 402 | |
| 403 | rdev = radeon_get_rdev(bo->bdev); |
| 404 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { |
| 405 | radeon_move_null(bo, new_mem); |
| 406 | return 0; |
| 407 | } |
| 408 | if ((old_mem->mem_type == TTM_PL_TT && |
| 409 | new_mem->mem_type == TTM_PL_SYSTEM) || |
| 410 | (old_mem->mem_type == TTM_PL_SYSTEM && |
| 411 | new_mem->mem_type == TTM_PL_TT)) { |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 412 | /* bind is enough */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 413 | radeon_move_null(bo, new_mem); |
| 414 | return 0; |
| 415 | } |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 416 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
| 417 | rdev->asic->copy.copy == NULL) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 418 | /* use memcpy */ |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 419 | goto memcpy; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 420 | } |
| 421 | |
| 422 | if (old_mem->mem_type == TTM_PL_VRAM && |
| 423 | new_mem->mem_type == TTM_PL_SYSTEM) { |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 424 | r = radeon_move_vram_ram(bo, evict, interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 425 | no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 426 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
| 427 | new_mem->mem_type == TTM_PL_VRAM) { |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 428 | r = radeon_move_ram_vram(bo, evict, interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 429 | no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 430 | } else { |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 431 | r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 432 | } |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 433 | |
| 434 | if (r) { |
| 435 | memcpy: |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 436 | r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); |
Marek Olšák | 67e8e3f | 2014-03-02 00:56:18 +0100 | [diff] [blame] | 437 | if (r) { |
| 438 | return r; |
| 439 | } |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 440 | } |
Marek Olšák | 67e8e3f | 2014-03-02 00:56:18 +0100 | [diff] [blame] | 441 | |
| 442 | /* update statistics */ |
| 443 | atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); |
| 444 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 445 | } |
| 446 | |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 447 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
| 448 | { |
| 449 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; |
| 450 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
| 451 | |
| 452 | mem->bus.addr = NULL; |
| 453 | mem->bus.offset = 0; |
| 454 | mem->bus.size = mem->num_pages << PAGE_SHIFT; |
| 455 | mem->bus.base = 0; |
| 456 | mem->bus.is_iomem = false; |
| 457 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) |
| 458 | return -EINVAL; |
| 459 | switch (mem->mem_type) { |
| 460 | case TTM_PL_SYSTEM: |
| 461 | /* system memory */ |
| 462 | return 0; |
| 463 | case TTM_PL_TT: |
Daniel Vetter | a7fb8a2 | 2015-09-09 16:45:52 +0200 | [diff] [blame] | 464 | #if IS_ENABLED(CONFIG_AGP) |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 465 | if (rdev->flags & RADEON_IS_AGP) { |
| 466 | /* RADEON_IS_AGP is set only if AGP is active */ |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 467 | mem->bus.offset = mem->start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 468 | mem->bus.base = rdev->mc.agp_base; |
Michel Dänzer | 365048f | 2010-05-19 12:46:22 +0200 | [diff] [blame] | 469 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 470 | } |
| 471 | #endif |
| 472 | break; |
| 473 | case TTM_PL_VRAM: |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 474 | mem->bus.offset = mem->start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 475 | /* check if it's visible */ |
| 476 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) |
| 477 | return -EINVAL; |
| 478 | mem->bus.base = rdev->mc.aper_base; |
| 479 | mem->bus.is_iomem = true; |
Jay Estabrook | ffb57c4 | 2011-07-06 23:57:13 +0000 | [diff] [blame] | 480 | #ifdef __alpha__ |
| 481 | /* |
| 482 | * Alpha: use bus.addr to hold the ioremap() return, |
| 483 | * so we can modify bus.base below. |
| 484 | */ |
| 485 | if (mem->placement & TTM_PL_FLAG_WC) |
| 486 | mem->bus.addr = |
| 487 | ioremap_wc(mem->bus.base + mem->bus.offset, |
| 488 | mem->bus.size); |
| 489 | else |
| 490 | mem->bus.addr = |
| 491 | ioremap_nocache(mem->bus.base + mem->bus.offset, |
| 492 | mem->bus.size); |
| 493 | |
| 494 | /* |
| 495 | * Alpha: Use just the bus offset plus |
| 496 | * the hose/domain memory base for bus.base. |
| 497 | * It then can be used to build PTEs for VRAM |
| 498 | * access, as done in ttm_bo_vm_fault(). |
| 499 | */ |
| 500 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + |
| 501 | rdev->ddev->hose->dense_mem_base; |
| 502 | #endif |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 503 | break; |
| 504 | default: |
| 505 | return -EINVAL; |
| 506 | } |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
| 511 | { |
| 512 | } |
| 513 | |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 514 | /* |
| 515 | * TTM backend functions. |
| 516 | */ |
| 517 | struct radeon_ttm_tt { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 518 | struct ttm_dma_tt ttm; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 519 | struct radeon_device *rdev; |
| 520 | u64 offset; |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 521 | |
| 522 | uint64_t userptr; |
| 523 | struct mm_struct *usermm; |
| 524 | uint32_t userflags; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 525 | }; |
| 526 | |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 527 | /* prepare the sg table with the user pages */ |
| 528 | static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm) |
| 529 | { |
| 530 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); |
| 531 | struct radeon_ttm_tt *gtt = (void *)ttm; |
| 532 | unsigned pinned = 0, nents; |
| 533 | int r; |
| 534 | |
| 535 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); |
| 536 | enum dma_data_direction direction = write ? |
| 537 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; |
| 538 | |
| 539 | if (current->mm != gtt->usermm) |
| 540 | return -EPERM; |
| 541 | |
Christian König | ddd00e3 | 2014-08-07 09:36:01 +0200 | [diff] [blame] | 542 | if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { |
| 543 | /* check that we only pin down anonymous memory |
| 544 | to prevent problems with writeback */ |
| 545 | unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; |
| 546 | struct vm_area_struct *vma; |
| 547 | vma = find_vma(gtt->usermm, gtt->userptr); |
| 548 | if (!vma || vma->vm_file || vma->vm_end < end) |
| 549 | return -EPERM; |
| 550 | } |
| 551 | |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 552 | do { |
| 553 | unsigned num_pages = ttm->num_pages - pinned; |
| 554 | uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; |
| 555 | struct page **pages = ttm->pages + pinned; |
| 556 | |
| 557 | r = get_user_pages(current, current->mm, userptr, num_pages, |
| 558 | write, 0, pages, NULL); |
| 559 | if (r < 0) |
| 560 | goto release_pages; |
| 561 | |
| 562 | pinned += r; |
| 563 | |
| 564 | } while (pinned < ttm->num_pages); |
| 565 | |
| 566 | r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, |
| 567 | ttm->num_pages << PAGE_SHIFT, |
| 568 | GFP_KERNEL); |
| 569 | if (r) |
| 570 | goto release_sg; |
| 571 | |
| 572 | r = -ENOMEM; |
| 573 | nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); |
| 574 | if (nents != ttm->sg->nents) |
| 575 | goto release_sg; |
| 576 | |
| 577 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, |
| 578 | gtt->ttm.dma_address, ttm->num_pages); |
| 579 | |
| 580 | return 0; |
| 581 | |
| 582 | release_sg: |
| 583 | kfree(ttm->sg); |
| 584 | |
| 585 | release_pages: |
| 586 | release_pages(ttm->pages, pinned, 0); |
| 587 | return r; |
| 588 | } |
| 589 | |
| 590 | static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) |
| 591 | { |
| 592 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); |
| 593 | struct radeon_ttm_tt *gtt = (void *)ttm; |
monk.liu | db12973 | 2015-05-05 09:24:17 +0200 | [diff] [blame] | 594 | struct sg_page_iter sg_iter; |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 595 | |
| 596 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); |
| 597 | enum dma_data_direction direction = write ? |
| 598 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; |
| 599 | |
Christian König | 863653f | 2015-03-31 17:36:57 +0200 | [diff] [blame] | 600 | /* double check that we don't free the table twice */ |
| 601 | if (!ttm->sg->sgl) |
| 602 | return; |
| 603 | |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 604 | /* free the sg table and pages again */ |
| 605 | dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); |
| 606 | |
monk.liu | db12973 | 2015-05-05 09:24:17 +0200 | [diff] [blame] | 607 | for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { |
| 608 | struct page *page = sg_page_iter_page(&sg_iter); |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 609 | if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) |
| 610 | set_page_dirty(page); |
| 611 | |
| 612 | mark_page_accessed(page); |
| 613 | page_cache_release(page); |
| 614 | } |
| 615 | |
| 616 | sg_free_table(ttm->sg); |
| 617 | } |
| 618 | |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 619 | static int radeon_ttm_backend_bind(struct ttm_tt *ttm, |
| 620 | struct ttm_mem_reg *bo_mem) |
| 621 | { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 622 | struct radeon_ttm_tt *gtt = (void*)ttm; |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 623 | uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | |
| 624 | RADEON_GART_PAGE_WRITE; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 625 | int r; |
| 626 | |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 627 | if (gtt->userptr) { |
| 628 | radeon_ttm_tt_pin_userptr(ttm); |
| 629 | flags &= ~RADEON_GART_PAGE_WRITE; |
| 630 | } |
| 631 | |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 632 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
| 633 | if (!ttm->num_pages) { |
| 634 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", |
| 635 | ttm->num_pages, bo_mem, ttm); |
| 636 | } |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 637 | if (ttm->caching_state == tt_cached) |
| 638 | flags |= RADEON_GART_PAGE_SNOOP; |
| 639 | r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, |
| 640 | ttm->pages, gtt->ttm.dma_address, flags); |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 641 | if (r) { |
| 642 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", |
| 643 | ttm->num_pages, (unsigned)gtt->offset); |
| 644 | return r; |
| 645 | } |
| 646 | return 0; |
| 647 | } |
| 648 | |
| 649 | static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) |
| 650 | { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 651 | struct radeon_ttm_tt *gtt = (void *)ttm; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 652 | |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 653 | radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 654 | |
| 655 | if (gtt->userptr) |
| 656 | radeon_ttm_tt_unpin_userptr(ttm); |
| 657 | |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 658 | return 0; |
| 659 | } |
| 660 | |
| 661 | static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) |
| 662 | { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 663 | struct radeon_ttm_tt *gtt = (void *)ttm; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 664 | |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 665 | ttm_dma_tt_fini(>t->ttm); |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 666 | kfree(gtt); |
| 667 | } |
| 668 | |
| 669 | static struct ttm_backend_func radeon_backend_func = { |
| 670 | .bind = &radeon_ttm_backend_bind, |
| 671 | .unbind = &radeon_ttm_backend_unbind, |
| 672 | .destroy = &radeon_ttm_backend_destroy, |
| 673 | }; |
| 674 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 675 | static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 676 | unsigned long size, uint32_t page_flags, |
| 677 | struct page *dummy_read_page) |
| 678 | { |
| 679 | struct radeon_device *rdev; |
| 680 | struct radeon_ttm_tt *gtt; |
| 681 | |
| 682 | rdev = radeon_get_rdev(bdev); |
Daniel Vetter | a7fb8a2 | 2015-09-09 16:45:52 +0200 | [diff] [blame] | 683 | #if IS_ENABLED(CONFIG_AGP) |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 684 | if (rdev->flags & RADEON_IS_AGP) { |
| 685 | return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, |
| 686 | size, page_flags, dummy_read_page); |
| 687 | } |
| 688 | #endif |
| 689 | |
| 690 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); |
| 691 | if (gtt == NULL) { |
| 692 | return NULL; |
| 693 | } |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 694 | gtt->ttm.ttm.func = &radeon_backend_func; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 695 | gtt->rdev = rdev; |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 696 | if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { |
| 697 | kfree(gtt); |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 698 | return NULL; |
| 699 | } |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 700 | return >t->ttm.ttm; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 701 | } |
| 702 | |
Christian König | 3840a65 | 2014-09-17 04:00:05 -0600 | [diff] [blame] | 703 | static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm) |
| 704 | { |
| 705 | if (!ttm || ttm->func != &radeon_backend_func) |
| 706 | return NULL; |
| 707 | return (struct radeon_ttm_tt *)ttm; |
| 708 | } |
| 709 | |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 710 | static int radeon_ttm_tt_populate(struct ttm_tt *ttm) |
| 711 | { |
Christian König | 3840a65 | 2014-09-17 04:00:05 -0600 | [diff] [blame] | 712 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 713 | struct radeon_device *rdev; |
| 714 | unsigned i; |
| 715 | int r; |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 716 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 717 | |
| 718 | if (ttm->state != tt_unpopulated) |
| 719 | return 0; |
| 720 | |
Christian König | 3840a65 | 2014-09-17 04:00:05 -0600 | [diff] [blame] | 721 | if (gtt && gtt->userptr) { |
Maninder Singh | 69ee241 | 2015-06-19 09:35:23 +0530 | [diff] [blame] | 722 | ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 723 | if (!ttm->sg) |
| 724 | return -ENOMEM; |
| 725 | |
| 726 | ttm->page_flags |= TTM_PAGE_FLAG_SG; |
| 727 | ttm->state = tt_unbound; |
| 728 | return 0; |
| 729 | } |
| 730 | |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 731 | if (slave && ttm->sg) { |
| 732 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, |
| 733 | gtt->ttm.dma_address, ttm->num_pages); |
| 734 | ttm->state = tt_unbound; |
| 735 | return 0; |
| 736 | } |
| 737 | |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 738 | rdev = radeon_get_rdev(ttm->bdev); |
Daniel Vetter | a7fb8a2 | 2015-09-09 16:45:52 +0200 | [diff] [blame] | 739 | #if IS_ENABLED(CONFIG_AGP) |
Jerome Glisse | dea7e0a | 2012-01-03 17:37:37 -0500 | [diff] [blame] | 740 | if (rdev->flags & RADEON_IS_AGP) { |
| 741 | return ttm_agp_tt_populate(ttm); |
| 742 | } |
| 743 | #endif |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 744 | |
| 745 | #ifdef CONFIG_SWIOTLB |
| 746 | if (swiotlb_nr_tbl()) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 747 | return ttm_dma_populate(>t->ttm, rdev->dev); |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 748 | } |
| 749 | #endif |
| 750 | |
| 751 | r = ttm_pool_populate(ttm); |
| 752 | if (r) { |
| 753 | return r; |
| 754 | } |
| 755 | |
| 756 | for (i = 0; i < ttm->num_pages; i++) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 757 | gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], |
| 758 | 0, PAGE_SIZE, |
| 759 | PCI_DMA_BIDIRECTIONAL); |
| 760 | if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 761 | while (--i) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 762 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 763 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 764 | gtt->ttm.dma_address[i] = 0; |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 765 | } |
| 766 | ttm_pool_unpopulate(ttm); |
| 767 | return -EFAULT; |
| 768 | } |
| 769 | } |
| 770 | return 0; |
| 771 | } |
| 772 | |
| 773 | static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) |
| 774 | { |
| 775 | struct radeon_device *rdev; |
Christian König | 3840a65 | 2014-09-17 04:00:05 -0600 | [diff] [blame] | 776 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 777 | unsigned i; |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 778 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
| 779 | |
Christian König | 3840a65 | 2014-09-17 04:00:05 -0600 | [diff] [blame] | 780 | if (gtt && gtt->userptr) { |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 781 | kfree(ttm->sg); |
| 782 | ttm->page_flags &= ~TTM_PAGE_FLAG_SG; |
| 783 | return; |
| 784 | } |
| 785 | |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 786 | if (slave) |
| 787 | return; |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 788 | |
| 789 | rdev = radeon_get_rdev(ttm->bdev); |
Daniel Vetter | a7fb8a2 | 2015-09-09 16:45:52 +0200 | [diff] [blame] | 790 | #if IS_ENABLED(CONFIG_AGP) |
Jerome Glisse | dea7e0a | 2012-01-03 17:37:37 -0500 | [diff] [blame] | 791 | if (rdev->flags & RADEON_IS_AGP) { |
| 792 | ttm_agp_tt_unpopulate(ttm); |
| 793 | return; |
| 794 | } |
| 795 | #endif |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 796 | |
| 797 | #ifdef CONFIG_SWIOTLB |
| 798 | if (swiotlb_nr_tbl()) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 799 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 800 | return; |
| 801 | } |
| 802 | #endif |
| 803 | |
| 804 | for (i = 0; i < ttm->num_pages; i++) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 805 | if (gtt->ttm.dma_address[i]) { |
| 806 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 807 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 808 | } |
| 809 | } |
| 810 | |
| 811 | ttm_pool_unpopulate(ttm); |
| 812 | } |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 813 | |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 814 | int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
| 815 | uint32_t flags) |
| 816 | { |
Christian König | 3840a65 | 2014-09-17 04:00:05 -0600 | [diff] [blame] | 817 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 818 | |
| 819 | if (gtt == NULL) |
| 820 | return -EINVAL; |
| 821 | |
| 822 | gtt->userptr = addr; |
| 823 | gtt->usermm = current->mm; |
| 824 | gtt->userflags = flags; |
| 825 | return 0; |
| 826 | } |
| 827 | |
| 828 | bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm) |
| 829 | { |
Christian König | 3840a65 | 2014-09-17 04:00:05 -0600 | [diff] [blame] | 830 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 831 | |
| 832 | if (gtt == NULL) |
| 833 | return false; |
| 834 | |
| 835 | return !!gtt->userptr; |
| 836 | } |
| 837 | |
| 838 | bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm) |
| 839 | { |
Christian König | 3840a65 | 2014-09-17 04:00:05 -0600 | [diff] [blame] | 840 | struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 841 | |
| 842 | if (gtt == NULL) |
| 843 | return false; |
| 844 | |
| 845 | return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); |
| 846 | } |
| 847 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 848 | static struct ttm_bo_driver radeon_bo_driver = { |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 849 | .ttm_tt_create = &radeon_ttm_tt_create, |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 850 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
| 851 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 852 | .invalidate_caches = &radeon_invalidate_caches, |
| 853 | .init_mem_type = &radeon_init_mem_type, |
| 854 | .evict_flags = &radeon_evict_flags, |
| 855 | .move = &radeon_bo_move, |
| 856 | .verify_access = &radeon_verify_access, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 857 | .move_notify = &radeon_bo_move_notify, |
| 858 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 859 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
| 860 | .io_mem_free = &radeon_ttm_io_mem_free, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 861 | }; |
| 862 | |
| 863 | int radeon_ttm_init(struct radeon_device *rdev) |
| 864 | { |
| 865 | int r; |
| 866 | |
| 867 | r = radeon_ttm_global_init(rdev); |
| 868 | if (r) { |
| 869 | return r; |
| 870 | } |
| 871 | /* No others user of address space so set it to 0 */ |
| 872 | r = ttm_bo_device_init(&rdev->mman.bdev, |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 873 | rdev->mman.bo_global_ref.ref.object, |
David Herrmann | 44d847b | 2013-08-13 19:10:30 +0200 | [diff] [blame] | 874 | &radeon_bo_driver, |
| 875 | rdev->ddev->anon_inode->i_mapping, |
| 876 | DRM_FILE_PAGE_OFFSET, |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 877 | rdev->need_dma32); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 878 | if (r) { |
| 879 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); |
| 880 | return r; |
| 881 | } |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 882 | rdev->mman.initialized = true; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 883 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 884 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 885 | if (r) { |
| 886 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
| 887 | return r; |
| 888 | } |
Lauri Kasanen | 14eedc3 | 2014-02-28 20:50:23 +0200 | [diff] [blame] | 889 | /* Change the size here instead of the init above so only lpfn is affected */ |
| 890 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
| 891 | |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 892 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
Maarten Lankhorst | 831b696 | 2014-09-18 14:11:56 +0200 | [diff] [blame] | 893 | RADEON_GEM_DOMAIN_VRAM, 0, NULL, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 894 | NULL, &rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 895 | if (r) { |
| 896 | return r; |
| 897 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 898 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
| 899 | if (r) |
| 900 | return r; |
| 901 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); |
| 902 | radeon_bo_unreserve(rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 903 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 904 | radeon_bo_unref(&rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 905 | return r; |
| 906 | } |
| 907 | DRM_INFO("radeon: %uM of VRAM memory ready\n", |
Niels Ole Salscheider | fc98603 | 2013-05-18 21:19:23 +0200 | [diff] [blame] | 908 | (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 909 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 910 | rdev->mc.gtt_size >> PAGE_SHIFT); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 911 | if (r) { |
| 912 | DRM_ERROR("Failed initializing GTT heap.\n"); |
| 913 | return r; |
| 914 | } |
| 915 | DRM_INFO("radeon: %uM of GTT memory ready.\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 916 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 917 | |
| 918 | r = radeon_ttm_debugfs_init(rdev); |
| 919 | if (r) { |
| 920 | DRM_ERROR("Failed to init debugfs\n"); |
| 921 | return r; |
| 922 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 923 | return 0; |
| 924 | } |
| 925 | |
| 926 | void radeon_ttm_fini(struct radeon_device *rdev) |
| 927 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 928 | int r; |
| 929 | |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 930 | if (!rdev->mman.initialized) |
| 931 | return; |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 932 | radeon_ttm_debugfs_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 933 | if (rdev->stollen_vga_memory) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 934 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
| 935 | if (r == 0) { |
| 936 | radeon_bo_unpin(rdev->stollen_vga_memory); |
| 937 | radeon_bo_unreserve(rdev->stollen_vga_memory); |
| 938 | } |
| 939 | radeon_bo_unref(&rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 940 | } |
| 941 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
| 942 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); |
| 943 | ttm_bo_device_release(&rdev->mman.bdev); |
| 944 | radeon_gart_fini(rdev); |
| 945 | radeon_ttm_global_fini(rdev); |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 946 | rdev->mman.initialized = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 947 | DRM_INFO("radeon: ttm finalized\n"); |
| 948 | } |
| 949 | |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 950 | /* this should only be called at bootup or when userspace |
| 951 | * isn't running */ |
| 952 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) |
| 953 | { |
| 954 | struct ttm_mem_type_manager *man; |
| 955 | |
| 956 | if (!rdev->mman.initialized) |
| 957 | return; |
| 958 | |
| 959 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; |
| 960 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ |
| 961 | man->size = size >> PAGE_SHIFT; |
| 962 | } |
| 963 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 964 | static struct vm_operations_struct radeon_ttm_vm_ops; |
Alexey Dobriyan | f0f37e2 | 2009-09-27 22:29:37 +0400 | [diff] [blame] | 965 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 966 | |
| 967 | static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 968 | { |
| 969 | struct ttm_buffer_object *bo; |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 970 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 971 | int r; |
| 972 | |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 973 | bo = (struct ttm_buffer_object *)vma->vm_private_data; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 974 | if (bo == NULL) { |
| 975 | return VM_FAULT_NOPAGE; |
| 976 | } |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 977 | rdev = radeon_get_rdev(bo->bdev); |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 978 | down_read(&rdev->pm.mclk_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 979 | r = ttm_vm_ops->fault(vma, vmf); |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 980 | up_read(&rdev->pm.mclk_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 981 | return r; |
| 982 | } |
| 983 | |
| 984 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) |
| 985 | { |
| 986 | struct drm_file *file_priv; |
| 987 | struct radeon_device *rdev; |
| 988 | int r; |
| 989 | |
| 990 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { |
Daniel Vetter | 884c6da | 2014-09-23 15:46:47 +0200 | [diff] [blame] | 991 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 992 | } |
| 993 | |
Joe Perches | 40b3be3 | 2010-09-04 18:52:42 -0700 | [diff] [blame] | 994 | file_priv = filp->private_data; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 995 | rdev = file_priv->minor->dev->dev_private; |
| 996 | if (rdev == NULL) { |
| 997 | return -EINVAL; |
| 998 | } |
| 999 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); |
| 1000 | if (unlikely(r != 0)) { |
| 1001 | return r; |
| 1002 | } |
| 1003 | if (unlikely(ttm_vm_ops == NULL)) { |
| 1004 | ttm_vm_ops = vma->vm_ops; |
| 1005 | radeon_ttm_vm_ops = *ttm_vm_ops; |
| 1006 | radeon_ttm_vm_ops.fault = &radeon_ttm_fault; |
| 1007 | } |
| 1008 | vma->vm_ops = &radeon_ttm_vm_ops; |
| 1009 | return 0; |
| 1010 | } |
| 1011 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 1012 | #if defined(CONFIG_DEBUG_FS) |
Christian König | 893d6e6 | 2013-12-12 09:42:40 +0100 | [diff] [blame] | 1013 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 1014 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
| 1015 | { |
| 1016 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
Christian König | 893d6e6 | 2013-12-12 09:42:40 +0100 | [diff] [blame] | 1017 | unsigned ttm_pl = *(int *)node->info_ent->data; |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 1018 | struct drm_device *dev = node->minor->dev; |
| 1019 | struct radeon_device *rdev = dev->dev_private; |
Christian König | 893d6e6 | 2013-12-12 09:42:40 +0100 | [diff] [blame] | 1020 | struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 1021 | int ret; |
| 1022 | struct ttm_bo_global *glob = rdev->mman.bdev.glob; |
| 1023 | |
| 1024 | spin_lock(&glob->lru_lock); |
| 1025 | ret = drm_mm_dump_table(m, mm); |
| 1026 | spin_unlock(&glob->lru_lock); |
| 1027 | return ret; |
| 1028 | } |
Christian König | 893d6e6 | 2013-12-12 09:42:40 +0100 | [diff] [blame] | 1029 | |
| 1030 | static int ttm_pl_vram = TTM_PL_VRAM; |
| 1031 | static int ttm_pl_tt = TTM_PL_TT; |
| 1032 | |
| 1033 | static struct drm_info_list radeon_ttm_debugfs_list[] = { |
| 1034 | {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, |
| 1035 | {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, |
| 1036 | {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, |
| 1037 | #ifdef CONFIG_SWIOTLB |
| 1038 | {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} |
| 1039 | #endif |
| 1040 | }; |
| 1041 | |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 1042 | static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) |
| 1043 | { |
| 1044 | struct radeon_device *rdev = inode->i_private; |
| 1045 | i_size_write(inode, rdev->mc.mc_vram_size); |
| 1046 | filep->private_data = inode->i_private; |
| 1047 | return 0; |
| 1048 | } |
| 1049 | |
| 1050 | static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, |
| 1051 | size_t size, loff_t *pos) |
| 1052 | { |
| 1053 | struct radeon_device *rdev = f->private_data; |
| 1054 | ssize_t result = 0; |
| 1055 | int r; |
| 1056 | |
| 1057 | if (size & 0x3 || *pos & 0x3) |
| 1058 | return -EINVAL; |
| 1059 | |
| 1060 | while (size) { |
| 1061 | unsigned long flags; |
| 1062 | uint32_t value; |
| 1063 | |
| 1064 | if (*pos >= rdev->mc.mc_vram_size) |
| 1065 | return result; |
| 1066 | |
| 1067 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); |
| 1068 | WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); |
| 1069 | if (rdev->family >= CHIP_CEDAR) |
| 1070 | WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); |
| 1071 | value = RREG32(RADEON_MM_DATA); |
| 1072 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); |
| 1073 | |
| 1074 | r = put_user(value, (uint32_t *)buf); |
| 1075 | if (r) |
| 1076 | return r; |
| 1077 | |
| 1078 | result += 4; |
| 1079 | buf += 4; |
| 1080 | *pos += 4; |
| 1081 | size -= 4; |
| 1082 | } |
| 1083 | |
| 1084 | return result; |
| 1085 | } |
| 1086 | |
| 1087 | static const struct file_operations radeon_ttm_vram_fops = { |
| 1088 | .owner = THIS_MODULE, |
| 1089 | .open = radeon_ttm_vram_open, |
| 1090 | .read = radeon_ttm_vram_read, |
| 1091 | .llseek = default_llseek |
| 1092 | }; |
| 1093 | |
Christian König | dd66d20 | 2013-12-18 21:07:40 +0100 | [diff] [blame] | 1094 | static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) |
| 1095 | { |
| 1096 | struct radeon_device *rdev = inode->i_private; |
| 1097 | i_size_write(inode, rdev->mc.gtt_size); |
| 1098 | filep->private_data = inode->i_private; |
| 1099 | return 0; |
| 1100 | } |
| 1101 | |
| 1102 | static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, |
| 1103 | size_t size, loff_t *pos) |
| 1104 | { |
| 1105 | struct radeon_device *rdev = f->private_data; |
| 1106 | ssize_t result = 0; |
| 1107 | int r; |
| 1108 | |
| 1109 | while (size) { |
| 1110 | loff_t p = *pos / PAGE_SIZE; |
| 1111 | unsigned off = *pos & ~PAGE_MASK; |
Paul Bolle | 0d997b6 | 2014-03-04 10:34:48 +0100 | [diff] [blame] | 1112 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); |
Christian König | dd66d20 | 2013-12-18 21:07:40 +0100 | [diff] [blame] | 1113 | struct page *page; |
| 1114 | void *ptr; |
| 1115 | |
| 1116 | if (p >= rdev->gart.num_cpu_pages) |
| 1117 | return result; |
| 1118 | |
| 1119 | page = rdev->gart.pages[p]; |
| 1120 | if (page) { |
| 1121 | ptr = kmap(page); |
| 1122 | ptr += off; |
| 1123 | |
| 1124 | r = copy_to_user(buf, ptr, cur_size); |
| 1125 | kunmap(rdev->gart.pages[p]); |
| 1126 | } else |
| 1127 | r = clear_user(buf, cur_size); |
| 1128 | |
| 1129 | if (r) |
| 1130 | return -EFAULT; |
| 1131 | |
| 1132 | result += cur_size; |
| 1133 | buf += cur_size; |
| 1134 | *pos += cur_size; |
| 1135 | size -= cur_size; |
| 1136 | } |
| 1137 | |
| 1138 | return result; |
| 1139 | } |
| 1140 | |
| 1141 | static const struct file_operations radeon_ttm_gtt_fops = { |
| 1142 | .owner = THIS_MODULE, |
| 1143 | .open = radeon_ttm_gtt_open, |
| 1144 | .read = radeon_ttm_gtt_read, |
| 1145 | .llseek = default_llseek |
| 1146 | }; |
| 1147 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 1148 | #endif |
| 1149 | |
| 1150 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) |
| 1151 | { |
Mikael Pettersson | f4e45d0 | 2009-09-28 18:27:23 +0200 | [diff] [blame] | 1152 | #if defined(CONFIG_DEBUG_FS) |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 1153 | unsigned count; |
| 1154 | |
| 1155 | struct drm_minor *minor = rdev->ddev->primary; |
| 1156 | struct dentry *ent, *root = minor->debugfs_root; |
| 1157 | |
| 1158 | ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root, |
| 1159 | rdev, &radeon_ttm_vram_fops); |
| 1160 | if (IS_ERR(ent)) |
| 1161 | return PTR_ERR(ent); |
| 1162 | rdev->mman.vram = ent; |
| 1163 | |
Christian König | dd66d20 | 2013-12-18 21:07:40 +0100 | [diff] [blame] | 1164 | ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root, |
| 1165 | rdev, &radeon_ttm_gtt_fops); |
| 1166 | if (IS_ERR(ent)) |
| 1167 | return PTR_ERR(ent); |
| 1168 | rdev->mman.gtt = ent; |
| 1169 | |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 1170 | count = ARRAY_SIZE(radeon_ttm_debugfs_list); |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 1171 | |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 1172 | #ifdef CONFIG_SWIOTLB |
Christian König | 893d6e6 | 2013-12-12 09:42:40 +0100 | [diff] [blame] | 1173 | if (!swiotlb_nr_tbl()) |
| 1174 | --count; |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 1175 | #endif |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 1176 | |
Christian König | 893d6e6 | 2013-12-12 09:42:40 +0100 | [diff] [blame] | 1177 | return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); |
| 1178 | #else |
| 1179 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 1180 | return 0; |
Christian König | 893d6e6 | 2013-12-12 09:42:40 +0100 | [diff] [blame] | 1181 | #endif |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 1182 | } |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 1183 | |
| 1184 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) |
| 1185 | { |
| 1186 | #if defined(CONFIG_DEBUG_FS) |
| 1187 | |
| 1188 | debugfs_remove(rdev->mman.vram); |
| 1189 | rdev->mman.vram = NULL; |
Christian König | dd66d20 | 2013-12-18 21:07:40 +0100 | [diff] [blame] | 1190 | |
| 1191 | debugfs_remove(rdev->mman.gtt); |
| 1192 | rdev->mman.gtt = NULL; |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 1193 | #endif |
| 1194 | } |