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Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02002 * Copyright (c) 2015-2017 QLogic Corporation
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003 *
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020031 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <linux/io.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/mutex.h>
41#include <linux/pci.h>
42#include <linux/slab.h>
43#include <linux/string.h>
Yuval Mintza91eb522016-06-03 14:35:32 +030044#include <linux/vmalloc.h>
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020045#include <linux/etherdevice.h>
46#include <linux/qed/qed_chain.h>
47#include <linux/qed/qed_if.h>
48#include "qed.h"
49#include "qed_cxt.h"
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -040050#include "qed_dcbx.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020051#include "qed_dev_api.h"
Arun Easi1e128c82017-02-15 06:28:22 -080052#include "qed_fcoe.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020053#include "qed_hsi.h"
54#include "qed_hw.h"
55#include "qed_init_ops.h"
56#include "qed_int.h"
Yuval Mintzfc831822016-12-01 00:21:06 -080057#include "qed_iscsi.h"
Yuval Mintz0a7fb112016-10-01 21:59:55 +030058#include "qed_ll2.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020059#include "qed_mcp.h"
Yuval Mintz1d6cff42016-12-01 00:21:07 -080060#include "qed_ooo.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020061#include "qed_reg_addr.h"
62#include "qed_sp.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030063#include "qed_sriov.h"
Yuval Mintz0b55e272016-05-11 16:36:15 +030064#include "qed_vf.h"
Kalderon, Michalb71b9af2017-06-21 16:22:45 +030065#include "qed_rdma.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020066
Wei Yongjun0caf5b22016-08-02 13:49:00 +000067static DEFINE_SPINLOCK(qm_lock);
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -040068
Ram Amrani51ff1722016-10-01 21:59:57 +030069#define QED_MIN_DPIS (4)
70#define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
71
Rahul Verma15582962017-04-06 15:58:29 +030072static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
73 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
Ram Amranic2035ee2016-03-02 20:26:00 +020074{
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030075 u32 bar_reg = (bar_id == BAR_ID_0 ?
76 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
77 u32 val;
Ram Amranic2035ee2016-03-02 20:26:00 +020078
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030079 if (IS_VF(p_hwfn->cdev))
Mintz, Yuval1a850bf2017-06-04 13:31:07 +030080 return qed_vf_hw_bar_size(p_hwfn, bar_id);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030081
Rahul Verma15582962017-04-06 15:58:29 +030082 val = qed_rd(p_hwfn, p_ptt, bar_reg);
Ram Amranic2035ee2016-03-02 20:26:00 +020083 if (val)
84 return 1 << (val + 15);
85
86 /* Old MFW initialized above registered only conditionally */
87 if (p_hwfn->cdev->num_hwfns > 1) {
88 DP_INFO(p_hwfn,
89 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
90 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
91 } else {
92 DP_INFO(p_hwfn,
93 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
94 return 512 * 1024;
95 }
96}
97
Yuval Mintz1a635e42016-08-15 10:42:43 +030098void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020099{
100 u32 i;
101
102 cdev->dp_level = dp_level;
103 cdev->dp_module = dp_module;
104 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
105 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
106
107 p_hwfn->dp_level = dp_level;
108 p_hwfn->dp_module = dp_module;
109 }
110}
111
112void qed_init_struct(struct qed_dev *cdev)
113{
114 u8 i;
115
116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
117 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
118
119 p_hwfn->cdev = cdev;
120 p_hwfn->my_id = i;
121 p_hwfn->b_active = false;
122
123 mutex_init(&p_hwfn->dmae_info.mutex);
124 }
125
126 /* hwfn 0 is always active */
127 cdev->hwfns[0].b_active = true;
128
129 /* set the default cache alignment to 128 */
130 cdev->cache_shift = 7;
131}
132
133static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
134{
135 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
136
137 kfree(qm_info->qm_pq_params);
138 qm_info->qm_pq_params = NULL;
139 kfree(qm_info->qm_vport_params);
140 qm_info->qm_vport_params = NULL;
141 kfree(qm_info->qm_port_params);
142 qm_info->qm_port_params = NULL;
Manish Choprabcd197c2016-04-26 10:56:08 -0400143 kfree(qm_info->wfq_data);
144 qm_info->wfq_data = NULL;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200145}
146
147void qed_resc_free(struct qed_dev *cdev)
148{
149 int i;
150
Mintz, Yuval0db711b2017-06-04 13:31:00 +0300151 if (IS_VF(cdev)) {
152 for_each_hwfn(cdev, i)
153 qed_l2_free(&cdev->hwfns[i]);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300154 return;
Mintz, Yuval0db711b2017-06-04 13:31:00 +0300155 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300156
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200157 kfree(cdev->fw_data);
158 cdev->fw_data = NULL;
159
160 kfree(cdev->reset_stats);
Tomer Tayar3587cb82017-05-21 12:10:56 +0300161 cdev->reset_stats = NULL;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200162
163 for_each_hwfn(cdev, i) {
164 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
165
166 qed_cxt_mngr_free(p_hwfn);
167 qed_qm_info_free(p_hwfn);
168 qed_spq_free(p_hwfn);
Tomer Tayar3587cb82017-05-21 12:10:56 +0300169 qed_eq_free(p_hwfn);
170 qed_consq_free(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200171 qed_int_free(p_hwfn);
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300172#ifdef CONFIG_QED_LL2
Tomer Tayar3587cb82017-05-21 12:10:56 +0300173 qed_ll2_free(p_hwfn);
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300174#endif
Arun Easi1e128c82017-02-15 06:28:22 -0800175 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
Tomer Tayar3587cb82017-05-21 12:10:56 +0300176 qed_fcoe_free(p_hwfn);
Arun Easi1e128c82017-02-15 06:28:22 -0800177
Yuval Mintz1d6cff42016-12-01 00:21:07 -0800178 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
Tomer Tayar3587cb82017-05-21 12:10:56 +0300179 qed_iscsi_free(p_hwfn);
180 qed_ooo_free(p_hwfn);
Yuval Mintz1d6cff42016-12-01 00:21:07 -0800181 }
Yuval Mintz32a47e72016-05-11 16:36:12 +0300182 qed_iov_free(p_hwfn);
Mintz, Yuval0db711b2017-06-04 13:31:00 +0300183 qed_l2_free(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200184 qed_dmae_info_free(p_hwfn);
sudarsana.kalluru@cavium.com270837b2017-04-20 22:31:16 -0700185 qed_dcbx_info_free(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200186 }
187}
188
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300189/******************** QM initialization *******************/
190#define ACTIVE_TCS_BMAP 0x9f
191#define ACTIVE_TCS_BMAP_4PORT_K2 0xf
192
193/* determines the physical queue flags for a given PF. */
194static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200195{
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300196 u32 flags;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200197
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300198 /* common flags */
199 flags = PQ_FLAGS_LB;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200200
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300201 /* feature flags */
202 if (IS_QED_SRIOV(p_hwfn->cdev))
203 flags |= PQ_FLAGS_VFS;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200204
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300205 /* protocol flags */
206 switch (p_hwfn->hw_info.personality) {
207 case QED_PCI_ETH:
208 flags |= PQ_FLAGS_MCOS;
209 break;
210 case QED_PCI_FCOE:
211 flags |= PQ_FLAGS_OFLD;
212 break;
213 case QED_PCI_ISCSI:
214 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
215 break;
216 case QED_PCI_ETH_ROCE:
217 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
218 break;
Kalderon, Michal93c45982017-07-02 10:29:32 +0300219 case QED_PCI_ETH_IWARP:
220 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
221 PQ_FLAGS_OFLD;
222 break;
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300223 default:
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200224 DP_ERR(p_hwfn,
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300225 "unknown personality %d\n", p_hwfn->hw_info.personality);
226 return 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200227 }
228
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300229 return flags;
230}
231
232/* Getters for resource amounts necessary for qm initialization */
233u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
234{
235 return p_hwfn->hw_info.num_hw_tc;
236}
237
238u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
239{
240 return IS_QED_SRIOV(p_hwfn->cdev) ?
241 p_hwfn->cdev->p_iov_info->total_vfs : 0;
242}
243
244#define NUM_DEFAULT_RLS 1
245
246u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
247{
248 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
249
250 /* num RLs can't exceed resource amount of rls or vports */
251 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
252 RESC_NUM(p_hwfn, QED_VPORT));
253
254 /* Make sure after we reserve there's something left */
255 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
256 return 0;
257
258 /* subtract rls necessary for VFs and one default one for the PF */
259 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
260
261 return num_pf_rls;
262}
263
264u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
265{
266 u32 pq_flags = qed_get_pq_flags(p_hwfn);
267
268 /* all pqs share the same vport, except for vfs and pf_rl pqs */
269 return (!!(PQ_FLAGS_RLS & pq_flags)) *
270 qed_init_qm_get_num_pf_rls(p_hwfn) +
271 (!!(PQ_FLAGS_VFS & pq_flags)) *
272 qed_init_qm_get_num_vfs(p_hwfn) + 1;
273}
274
275/* calc amount of PQs according to the requested flags */
276u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
277{
278 u32 pq_flags = qed_get_pq_flags(p_hwfn);
279
280 return (!!(PQ_FLAGS_RLS & pq_flags)) *
281 qed_init_qm_get_num_pf_rls(p_hwfn) +
282 (!!(PQ_FLAGS_MCOS & pq_flags)) *
283 qed_init_qm_get_num_tcs(p_hwfn) +
284 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
285 (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
286 (!!(PQ_FLAGS_LLT & pq_flags)) +
287 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
288}
289
290/* initialize the top level QM params */
291static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
292{
293 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
294 bool four_port;
295
296 /* pq and vport bases for this PF */
297 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
298 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
299
300 /* rate limiting and weighted fair queueing are always enabled */
Gustavo A. R. Silvac7281d52018-03-22 15:08:49 -0500301 qm_info->vport_rl_en = true;
302 qm_info->vport_wfq_en = true;
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300303
304 /* TC config is different for AH 4 port */
Tomer Tayar78cea9f2017-05-23 09:41:22 +0300305 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300306
307 /* in AH 4 port we have fewer TCs per port */
308 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
309 NUM_OF_PHYS_TCS;
310
311 /* unless MFW indicated otherwise, ooo_tc == 3 for
312 * AH 4-port and 4 otherwise.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200313 */
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300314 if (!qm_info->ooo_tc)
315 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
316 DCBX_TCP_OOO_TC;
317}
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200318
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300319/* initialize qm vport params */
320static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
321{
322 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
323 u8 i;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200324
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300325 /* all vports participate in weighted fair queueing */
326 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
327 qm_info->qm_vport_params[i].vport_wfq = 1;
328}
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200329
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300330/* initialize qm port params */
331static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
332{
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200333 /* Initialize qm port parameters */
Tomer Tayar78cea9f2017-05-23 09:41:22 +0300334 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300335
336 /* indicate how ooo and high pri traffic is dealt with */
337 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
338 ACTIVE_TCS_BMAP_4PORT_K2 :
339 ACTIVE_TCS_BMAP;
340
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200341 for (i = 0; i < num_ports; i++) {
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300342 struct init_qm_port_params *p_qm_port =
343 &p_hwfn->qm_info.qm_port_params[i];
344
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200345 p_qm_port->active = 1;
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300346 p_qm_port->active_phys_tcs = active_phys_tcs;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200347 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
348 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
349 }
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300350}
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200351
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300352/* Reset the params which must be reset for qm init. QM init may be called as
353 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
354 * params may be affected by the init but would simply recalculate to the same
355 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
356 * affected as these amounts stay the same.
357 */
358static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
359{
360 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200361
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300362 qm_info->num_pqs = 0;
363 qm_info->num_vports = 0;
364 qm_info->num_pf_rls = 0;
365 qm_info->num_vf_pqs = 0;
366 qm_info->first_vf_pq = 0;
367 qm_info->first_mcos_pq = 0;
368 qm_info->first_rl_pq = 0;
369}
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200370
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300371static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
372{
373 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
374
375 qm_info->num_vports++;
376
377 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
378 DP_ERR(p_hwfn,
379 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
380 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
381}
382
383/* initialize a single pq and manage qm_info resources accounting.
384 * The pq_init_flags param determines whether the PQ is rate limited
385 * (for VF or PF) and whether a new vport is allocated to the pq or not
386 * (i.e. vport will be shared).
387 */
388
389/* flags for pq init */
390#define PQ_INIT_SHARE_VPORT (1 << 0)
391#define PQ_INIT_PF_RL (1 << 1)
392#define PQ_INIT_VF_RL (1 << 2)
393
394/* defines for pq init */
395#define PQ_INIT_DEFAULT_WRR_GROUP 1
396#define PQ_INIT_DEFAULT_TC 0
397#define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
398
399static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
400 struct qed_qm_info *qm_info,
401 u8 tc, u32 pq_init_flags)
402{
403 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
404
405 if (pq_idx > max_pq)
406 DP_ERR(p_hwfn,
407 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
408
409 /* init pq params */
Michal Kalderon50bc60c2018-03-28 11:42:16 +0300410 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300411 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
412 qm_info->num_vports;
413 qm_info->qm_pq_params[pq_idx].tc_id = tc;
414 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
415 qm_info->qm_pq_params[pq_idx].rl_valid =
416 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
417
418 /* qm params accounting */
419 qm_info->num_pqs++;
420 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
421 qm_info->num_vports++;
422
423 if (pq_init_flags & PQ_INIT_PF_RL)
424 qm_info->num_pf_rls++;
425
426 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
427 DP_ERR(p_hwfn,
428 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
429 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
430
431 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
432 DP_ERR(p_hwfn,
433 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
434 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
435}
436
437/* get pq index according to PQ_FLAGS */
438static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
439 u32 pq_flags)
440{
441 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
442
443 /* Can't have multiple flags set here */
444 if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
445 goto err;
446
447 switch (pq_flags) {
448 case PQ_FLAGS_RLS:
449 return &qm_info->first_rl_pq;
450 case PQ_FLAGS_MCOS:
451 return &qm_info->first_mcos_pq;
452 case PQ_FLAGS_LB:
453 return &qm_info->pure_lb_pq;
454 case PQ_FLAGS_OOO:
455 return &qm_info->ooo_pq;
456 case PQ_FLAGS_ACK:
457 return &qm_info->pure_ack_pq;
458 case PQ_FLAGS_OFLD:
459 return &qm_info->offload_pq;
460 case PQ_FLAGS_LLT:
461 return &qm_info->low_latency_pq;
462 case PQ_FLAGS_VFS:
463 return &qm_info->first_vf_pq;
464 default:
465 goto err;
466 }
467
468err:
469 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
470 return NULL;
471}
472
473/* save pq index in qm info */
474static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
475 u32 pq_flags, u16 pq_val)
476{
477 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
478
479 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
480}
481
482/* get tx pq index, with the PQ TX base already set (ready for context init) */
483u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
484{
485 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
486
487 return *base_pq_idx + CM_TX_PQ_BASE;
488}
489
490u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
491{
492 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
493
494 if (tc > max_tc)
495 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
496
497 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
498}
499
500u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
501{
502 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
503
504 if (vf > max_vf)
505 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
506
507 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
508}
509
510u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
511{
512 u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
513
514 if (rl > max_rl)
515 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
516
517 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
518}
519
520/* Functions for creating specific types of pqs */
521static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
522{
523 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
524
525 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
526 return;
527
528 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
529 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
530}
531
532static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
533{
534 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
535
536 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
537 return;
538
539 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
540 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
541}
542
543static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
544{
545 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
546
547 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
548 return;
549
550 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
551 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
552}
553
554static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
555{
556 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
557
558 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
559 return;
560
561 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
562 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
563}
564
565static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
566{
567 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
568
569 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
570 return;
571
572 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
573 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
574}
575
576static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
577{
578 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
579 u8 tc_idx;
580
581 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
582 return;
583
584 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
585 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
586 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
587}
588
589static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
590{
591 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
592 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
593
594 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
595 return;
596
597 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300598 qm_info->num_vf_pqs = num_vfs;
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300599 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
600 qed_init_qm_pq(p_hwfn,
601 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
602}
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200603
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300604static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
605{
606 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
607 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
Manish Chopraa64b02d2016-04-26 10:56:10 -0400608
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300609 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
610 return;
611
612 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
613 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
614 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
615}
616
617static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
618{
619 /* rate limited pqs, must come first (FW assumption) */
620 qed_init_qm_rl_pqs(p_hwfn);
621
622 /* pqs for multi cos */
623 qed_init_qm_mcos_pqs(p_hwfn);
624
625 /* pure loopback pq */
626 qed_init_qm_lb_pq(p_hwfn);
627
628 /* out of order pq */
629 qed_init_qm_ooo_pq(p_hwfn);
630
631 /* pure ack pq */
632 qed_init_qm_pure_ack_pq(p_hwfn);
633
634 /* pq for offloaded protocol */
635 qed_init_qm_offload_pq(p_hwfn);
636
637 /* low latency pq */
638 qed_init_qm_low_latency_pq(p_hwfn);
639
640 /* done sharing vports */
641 qed_init_qm_advance_vport(p_hwfn);
642
643 /* pqs for vfs */
644 qed_init_qm_vf_pqs(p_hwfn);
645}
646
647/* compare values of getters against resources amounts */
648static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
649{
650 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
651 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
652 return -EINVAL;
653 }
654
655 if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
656 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
657 return -EINVAL;
658 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200659
660 return 0;
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300661}
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200662
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300663static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
664{
665 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
666 struct init_qm_vport_params *vport;
667 struct init_qm_port_params *port;
668 struct init_qm_pq_params *pq;
669 int i, tc;
670
671 /* top level params */
672 DP_VERBOSE(p_hwfn,
673 NETIF_MSG_HW,
674 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
675 qm_info->start_pq,
676 qm_info->start_vport,
677 qm_info->pure_lb_pq,
678 qm_info->offload_pq, qm_info->pure_ack_pq);
679 DP_VERBOSE(p_hwfn,
680 NETIF_MSG_HW,
681 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
682 qm_info->ooo_pq,
683 qm_info->first_vf_pq,
684 qm_info->num_pqs,
685 qm_info->num_vf_pqs,
686 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
687 DP_VERBOSE(p_hwfn,
688 NETIF_MSG_HW,
689 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
690 qm_info->pf_rl_en,
691 qm_info->pf_wfq_en,
692 qm_info->vport_rl_en,
693 qm_info->vport_wfq_en,
694 qm_info->pf_wfq,
695 qm_info->pf_rl,
696 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
697
698 /* port table */
Tomer Tayar78cea9f2017-05-23 09:41:22 +0300699 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300700 port = &(qm_info->qm_port_params[i]);
701 DP_VERBOSE(p_hwfn,
702 NETIF_MSG_HW,
703 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
704 i,
705 port->active,
706 port->active_phys_tcs,
707 port->num_pbf_cmd_lines,
708 port->num_btb_blocks, port->reserved);
709 }
710
711 /* vport table */
712 for (i = 0; i < qm_info->num_vports; i++) {
713 vport = &(qm_info->qm_vport_params[i]);
714 DP_VERBOSE(p_hwfn,
715 NETIF_MSG_HW,
716 "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
717 qm_info->start_vport + i,
718 vport->vport_rl, vport->vport_wfq);
719 for (tc = 0; tc < NUM_OF_TCS; tc++)
720 DP_VERBOSE(p_hwfn,
721 NETIF_MSG_HW,
722 "%d ", vport->first_tx_pq_id[tc]);
723 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
724 }
725
726 /* pq table */
727 for (i = 0; i < qm_info->num_pqs; i++) {
728 pq = &(qm_info->qm_pq_params[i]);
729 DP_VERBOSE(p_hwfn,
730 NETIF_MSG_HW,
Michal Kalderon50bc60c2018-03-28 11:42:16 +0300731 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300732 qm_info->start_pq + i,
Michal Kalderon50bc60c2018-03-28 11:42:16 +0300733 pq->port_id,
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300734 pq->vport_id,
735 pq->tc_id, pq->wrr_group, pq->rl_valid);
736 }
737}
738
739static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
740{
741 /* reset params required for init run */
742 qed_init_qm_reset_params(p_hwfn);
743
744 /* init QM top level params */
745 qed_init_qm_params(p_hwfn);
746
747 /* init QM port params */
748 qed_init_qm_port_params(p_hwfn);
749
750 /* init QM vport params */
751 qed_init_qm_vport_params(p_hwfn);
752
753 /* init QM physical queue params */
754 qed_init_qm_pq_params(p_hwfn);
755
756 /* display all that init */
757 qed_dp_init_qm_params(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200758}
759
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400760/* This function reconfigures the QM pf on the fly.
761 * For this purpose we:
762 * 1. reconfigure the QM database
Tomer Tayara2e76992017-12-27 19:30:05 +0200763 * 2. set new values to runtime array
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400764 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
765 * 4. activate init tool in QM_PF stage
766 * 5. send an sdm_qm_cmd through rbc interface to release the QM
767 */
768int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
769{
770 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
771 bool b_rc;
772 int rc;
773
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400774 /* initialize qed's qm data structure */
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300775 qed_init_qm_info(p_hwfn);
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400776
777 /* stop PF's qm queues */
778 spin_lock_bh(&qm_lock);
779 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
780 qm_info->start_pq, qm_info->num_pqs);
781 spin_unlock_bh(&qm_lock);
782 if (!b_rc)
783 return -EINVAL;
784
785 /* clear the QM_PF runtime phase leftovers from previous init */
786 qed_init_clear_rt_data(p_hwfn);
787
788 /* prepare QM portion of runtime array */
Tomer Tayarda090912017-12-27 19:30:07 +0200789 qed_qm_init_pf(p_hwfn, p_ptt, false);
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400790
791 /* activate init tool on runtime array */
792 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
793 p_hwfn->hw_info.hw_mode);
794 if (rc)
795 return rc;
796
797 /* start PF's qm queues */
798 spin_lock_bh(&qm_lock);
799 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
800 qm_info->start_pq, qm_info->num_pqs);
801 spin_unlock_bh(&qm_lock);
802 if (!b_rc)
803 return -EINVAL;
804
805 return 0;
806}
807
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300808static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
809{
810 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
811 int rc;
812
813 rc = qed_init_qm_sanity(p_hwfn);
814 if (rc)
815 goto alloc_err;
816
817 qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
818 qed_init_qm_get_num_pqs(p_hwfn),
819 GFP_KERNEL);
820 if (!qm_info->qm_pq_params)
821 goto alloc_err;
822
823 qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
824 qed_init_qm_get_num_vports(p_hwfn),
825 GFP_KERNEL);
826 if (!qm_info->qm_vport_params)
827 goto alloc_err;
828
Wei Yongjun2f7878c2017-04-25 07:07:18 +0000829 qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
Tomer Tayar78cea9f2017-05-23 09:41:22 +0300830 p_hwfn->cdev->num_ports_in_engine,
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300831 GFP_KERNEL);
832 if (!qm_info->qm_port_params)
833 goto alloc_err;
834
835 qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
836 qed_init_qm_get_num_vports(p_hwfn),
837 GFP_KERNEL);
838 if (!qm_info->wfq_data)
839 goto alloc_err;
840
841 return 0;
842
843alloc_err:
844 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
845 qed_qm_info_free(p_hwfn);
846 return -ENOMEM;
847}
848
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200849int qed_resc_alloc(struct qed_dev *cdev)
850{
Ram Amranif9dc4d12017-04-03 12:21:13 +0300851 u32 rdma_tasks, excess_tasks;
Ram Amranif9dc4d12017-04-03 12:21:13 +0300852 u32 line_count;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200853 int i, rc = 0;
854
Mintz, Yuval0db711b2017-06-04 13:31:00 +0300855 if (IS_VF(cdev)) {
856 for_each_hwfn(cdev, i) {
857 rc = qed_l2_alloc(&cdev->hwfns[i]);
858 if (rc)
859 return rc;
860 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300861 return rc;
Mintz, Yuval0db711b2017-06-04 13:31:00 +0300862 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300863
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200864 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
865 if (!cdev->fw_data)
866 return -ENOMEM;
867
868 for_each_hwfn(cdev, i) {
869 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300870 u32 n_eqes, num_cons;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200871
872 /* First allocate the context manager structure */
873 rc = qed_cxt_mngr_alloc(p_hwfn);
874 if (rc)
875 goto alloc_err;
876
877 /* Set the HW cid/tid numbers (in the contest manager)
878 * Must be done prior to any further computations.
879 */
Ram Amranif9dc4d12017-04-03 12:21:13 +0300880 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200881 if (rc)
882 goto alloc_err;
883
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300884 rc = qed_alloc_qm_data(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200885 if (rc)
886 goto alloc_err;
887
Ariel Eliorb5a9ee72017-04-03 12:21:09 +0300888 /* init qm info */
889 qed_init_qm_info(p_hwfn);
890
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200891 /* Compute the ILT client partition */
Ram Amranif9dc4d12017-04-03 12:21:13 +0300892 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
893 if (rc) {
894 DP_NOTICE(p_hwfn,
895 "too many ILT lines; re-computing with less lines\n");
896 /* In case there are not enough ILT lines we reduce the
897 * number of RDMA tasks and re-compute.
898 */
899 excess_tasks =
900 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
901 if (!excess_tasks)
902 goto alloc_err;
903
904 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
905 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
906 if (rc)
907 goto alloc_err;
908
909 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
910 if (rc) {
911 DP_ERR(p_hwfn,
912 "failed ILT compute. Requested too many lines: %u\n",
913 line_count);
914
915 goto alloc_err;
916 }
917 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200918
919 /* CID map / ILT shadow table / T2
920 * The talbes sizes are determined by the computations above
921 */
922 rc = qed_cxt_tables_alloc(p_hwfn);
923 if (rc)
924 goto alloc_err;
925
926 /* SPQ, must follow ILT because initializes SPQ context */
927 rc = qed_spq_alloc(p_hwfn);
928 if (rc)
929 goto alloc_err;
930
931 /* SP status block allocation */
932 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
933 RESERVED_PTT_DPC);
934
935 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
936 if (rc)
937 goto alloc_err;
938
Yuval Mintz32a47e72016-05-11 16:36:12 +0300939 rc = qed_iov_alloc(p_hwfn);
940 if (rc)
941 goto alloc_err;
942
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200943 /* EQ */
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300944 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
Kalderon, Michalc851a9d2017-07-02 10:29:21 +0300945 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
Kalderon, Michal67b40dc2017-07-02 10:29:22 +0300946 enum protocol_type rdma_proto;
947
948 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
949 rdma_proto = PROTOCOLID_ROCE;
950 else
951 rdma_proto = PROTOCOLID_IWARP;
952
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300953 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
Kalderon, Michal67b40dc2017-07-02 10:29:22 +0300954 rdma_proto,
Yuval Mintz8c93bea2016-10-13 22:57:03 +0300955 NULL) * 2;
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300956 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
957 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
958 num_cons =
959 qed_cxt_get_proto_cid_count(p_hwfn,
Yuval Mintz8c93bea2016-10-13 22:57:03 +0300960 PROTOCOLID_ISCSI,
961 NULL);
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300962 n_eqes += 2 * num_cons;
963 }
964
965 if (n_eqes > 0xFFFF) {
966 DP_ERR(p_hwfn,
967 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
968 n_eqes, 0xFFFF);
Tomer Tayar3587cb82017-05-21 12:10:56 +0300969 goto alloc_no_mem;
Dan Carpenter9b15acb2015-11-05 11:41:28 +0300970 }
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300971
Tomer Tayar3587cb82017-05-21 12:10:56 +0300972 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
973 if (rc)
974 goto alloc_err;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200975
Tomer Tayar3587cb82017-05-21 12:10:56 +0300976 rc = qed_consq_alloc(p_hwfn);
977 if (rc)
978 goto alloc_err;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200979
Mintz, Yuval0db711b2017-06-04 13:31:00 +0300980 rc = qed_l2_alloc(p_hwfn);
981 if (rc)
982 goto alloc_err;
983
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300984#ifdef CONFIG_QED_LL2
985 if (p_hwfn->using_ll2) {
Tomer Tayar3587cb82017-05-21 12:10:56 +0300986 rc = qed_ll2_alloc(p_hwfn);
987 if (rc)
988 goto alloc_err;
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300989 }
990#endif
Arun Easi1e128c82017-02-15 06:28:22 -0800991
992 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
Tomer Tayar3587cb82017-05-21 12:10:56 +0300993 rc = qed_fcoe_alloc(p_hwfn);
994 if (rc)
995 goto alloc_err;
Arun Easi1e128c82017-02-15 06:28:22 -0800996 }
997
Yuval Mintzfc831822016-12-01 00:21:06 -0800998 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
Tomer Tayar3587cb82017-05-21 12:10:56 +0300999 rc = qed_iscsi_alloc(p_hwfn);
1000 if (rc)
1001 goto alloc_err;
1002 rc = qed_ooo_alloc(p_hwfn);
1003 if (rc)
1004 goto alloc_err;
Yuval Mintzfc831822016-12-01 00:21:06 -08001005 }
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001006
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001007 /* DMA info initialization */
1008 rc = qed_dmae_info_alloc(p_hwfn);
Joe Perches2591c282016-09-04 14:24:03 -07001009 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001010 goto alloc_err;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001011
1012 /* DCBX initialization */
1013 rc = qed_dcbx_info_alloc(p_hwfn);
Joe Perches2591c282016-09-04 14:24:03 -07001014 if (rc)
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001015 goto alloc_err;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001016 }
1017
1018 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -07001019 if (!cdev->reset_stats)
Yuval Mintz83aeb932016-08-15 10:42:44 +03001020 goto alloc_no_mem;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001021
1022 return 0;
1023
Yuval Mintzdbb799c2016-06-03 14:35:35 +03001024alloc_no_mem:
1025 rc = -ENOMEM;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001026alloc_err:
1027 qed_resc_free(cdev);
1028 return rc;
1029}
1030
1031void qed_resc_setup(struct qed_dev *cdev)
1032{
1033 int i;
1034
Mintz, Yuval0db711b2017-06-04 13:31:00 +03001035 if (IS_VF(cdev)) {
1036 for_each_hwfn(cdev, i)
1037 qed_l2_setup(&cdev->hwfns[i]);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001038 return;
Mintz, Yuval0db711b2017-06-04 13:31:00 +03001039 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001040
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001041 for_each_hwfn(cdev, i) {
1042 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1043
1044 qed_cxt_mngr_setup(p_hwfn);
1045 qed_spq_setup(p_hwfn);
Tomer Tayar3587cb82017-05-21 12:10:56 +03001046 qed_eq_setup(p_hwfn);
1047 qed_consq_setup(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001048
1049 /* Read shadow of current MFW mailbox */
1050 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1051 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1052 p_hwfn->mcp_info->mfw_mb_cur,
1053 p_hwfn->mcp_info->mfw_mb_length);
1054
1055 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
Yuval Mintz32a47e72016-05-11 16:36:12 +03001056
Mintz, Yuval0db711b2017-06-04 13:31:00 +03001057 qed_l2_setup(p_hwfn);
Mintz, Yuval1ee240e2017-06-01 15:29:11 +03001058 qed_iov_setup(p_hwfn);
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001059#ifdef CONFIG_QED_LL2
1060 if (p_hwfn->using_ll2)
Tomer Tayar3587cb82017-05-21 12:10:56 +03001061 qed_ll2_setup(p_hwfn);
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001062#endif
Arun Easi1e128c82017-02-15 06:28:22 -08001063 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
Tomer Tayar3587cb82017-05-21 12:10:56 +03001064 qed_fcoe_setup(p_hwfn);
Arun Easi1e128c82017-02-15 06:28:22 -08001065
Yuval Mintz1d6cff42016-12-01 00:21:07 -08001066 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
Tomer Tayar3587cb82017-05-21 12:10:56 +03001067 qed_iscsi_setup(p_hwfn);
1068 qed_ooo_setup(p_hwfn);
Yuval Mintz1d6cff42016-12-01 00:21:07 -08001069 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001070 }
1071}
1072
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001073#define FINAL_CLEANUP_POLL_CNT (100)
1074#define FINAL_CLEANUP_POLL_TIME (10)
1075int qed_final_cleanup(struct qed_hwfn *p_hwfn,
Yuval Mintz0b55e272016-05-11 16:36:15 +03001076 struct qed_ptt *p_ptt, u16 id, bool is_vf)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001077{
1078 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1079 int rc = -EBUSY;
1080
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001081 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1082 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001083
Yuval Mintz0b55e272016-05-11 16:36:15 +03001084 if (is_vf)
1085 id += 0x10;
1086
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001087 command |= X_FINAL_CLEANUP_AGG_INT <<
1088 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1089 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1090 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1091 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001092
1093 /* Make sure notification is not set before initiating final cleanup */
1094 if (REG_RD(p_hwfn, addr)) {
Yuval Mintz1a635e42016-08-15 10:42:43 +03001095 DP_NOTICE(p_hwfn,
1096 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001097 REG_WR(p_hwfn, addr, 0);
1098 }
1099
1100 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1101 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1102 id, command);
1103
1104 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1105
1106 /* Poll until completion */
1107 while (!REG_RD(p_hwfn, addr) && count--)
1108 msleep(FINAL_CLEANUP_POLL_TIME);
1109
1110 if (REG_RD(p_hwfn, addr))
1111 rc = 0;
1112 else
1113 DP_NOTICE(p_hwfn,
1114 "Failed to receive FW final cleanup notification\n");
1115
1116 /* Cleanup afterwards */
1117 REG_WR(p_hwfn, addr, 0);
1118
1119 return rc;
1120}
1121
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001122static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001123{
1124 int hw_mode = 0;
1125
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001126 if (QED_IS_BB_B0(p_hwfn->cdev)) {
1127 hw_mode |= 1 << MODE_BB;
1128 } else if (QED_IS_AH(p_hwfn->cdev)) {
1129 hw_mode |= 1 << MODE_K2;
1130 } else {
1131 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1132 p_hwfn->cdev->type);
1133 return -EINVAL;
1134 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001135
Tomer Tayar78cea9f2017-05-23 09:41:22 +03001136 switch (p_hwfn->cdev->num_ports_in_engine) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001137 case 1:
1138 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1139 break;
1140 case 2:
1141 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1142 break;
1143 case 4:
1144 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1145 break;
1146 default:
1147 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
Tomer Tayar78cea9f2017-05-23 09:41:22 +03001148 p_hwfn->cdev->num_ports_in_engine);
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001149 return -EINVAL;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001150 }
1151
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07001152 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001153 hw_mode |= 1 << MODE_MF_SD;
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07001154 else
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001155 hw_mode |= 1 << MODE_MF_SI;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001156
1157 hw_mode |= 1 << MODE_ASIC;
1158
Yuval Mintz1af9dcf2016-05-26 11:01:22 +03001159 if (p_hwfn->cdev->num_hwfns > 1)
1160 hw_mode |= 1 << MODE_100G;
1161
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001162 p_hwfn->hw_info.hw_mode = hw_mode;
Yuval Mintz1af9dcf2016-05-26 11:01:22 +03001163
1164 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1165 "Configuring function for hw_mode: 0x%08x\n",
1166 p_hwfn->hw_info.hw_mode);
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001167
1168 return 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001169}
1170
1171/* Init run time data for all PFs on an engine. */
1172static void qed_init_cau_rt_data(struct qed_dev *cdev)
1173{
1174 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
Mintz, Yuvald0315482017-06-01 15:29:04 +03001175 int i, igu_sb_id;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001176
1177 for_each_hwfn(cdev, i) {
1178 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1179 struct qed_igu_info *p_igu_info;
1180 struct qed_igu_block *p_block;
1181 struct cau_sb_entry sb_entry;
1182
1183 p_igu_info = p_hwfn->hw_info.p_igu_info;
1184
Mintz, Yuvald0315482017-06-01 15:29:04 +03001185 for (igu_sb_id = 0;
1186 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1187 p_block = &p_igu_info->entry[igu_sb_id];
1188
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001189 if (!p_block->is_pf)
1190 continue;
1191
1192 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
Yuval Mintz1a635e42016-08-15 10:42:43 +03001193 p_block->function_id, 0, 0);
Mintz, Yuvald0315482017-06-01 15:29:04 +03001194 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1195 sb_entry);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001196 }
1197 }
1198}
1199
Tomer Tayar60afed72017-04-06 15:58:30 +03001200static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1201 struct qed_ptt *p_ptt)
1202{
1203 u32 val, wr_mbs, cache_line_size;
1204
1205 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1206 switch (val) {
1207 case 0:
1208 wr_mbs = 128;
1209 break;
1210 case 1:
1211 wr_mbs = 256;
1212 break;
1213 case 2:
1214 wr_mbs = 512;
1215 break;
1216 default:
1217 DP_INFO(p_hwfn,
1218 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1219 val);
1220 return;
1221 }
1222
1223 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1224 switch (cache_line_size) {
1225 case 32:
1226 val = 0;
1227 break;
1228 case 64:
1229 val = 1;
1230 break;
1231 case 128:
1232 val = 2;
1233 break;
1234 case 256:
1235 val = 3;
1236 break;
1237 default:
1238 DP_INFO(p_hwfn,
1239 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1240 cache_line_size);
1241 }
1242
1243 if (L1_CACHE_BYTES > wr_mbs)
1244 DP_INFO(p_hwfn,
1245 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1246 L1_CACHE_BYTES, wr_mbs);
1247
1248 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
Mintz, Yuvalfc6575b2017-05-29 09:53:14 +03001249 if (val > 0) {
1250 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1251 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1252 }
Tomer Tayar60afed72017-04-06 15:58:30 +03001253}
1254
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001255static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
Yuval Mintz1a635e42016-08-15 10:42:43 +03001256 struct qed_ptt *p_ptt, int hw_mode)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001257{
1258 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1259 struct qed_qm_common_rt_init_params params;
1260 struct qed_dev *cdev = p_hwfn->cdev;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001261 u8 vf_id, max_num_vfs;
Yuval Mintzdbb799c2016-06-03 14:35:35 +03001262 u16 num_pfs, pf_id;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001263 u32 concrete_fid;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001264 int rc = 0;
1265
1266 qed_init_cau_rt_data(cdev);
1267
1268 /* Program GTT windows */
1269 qed_gtt_init(p_hwfn);
1270
1271 if (p_hwfn->mcp_info) {
1272 if (p_hwfn->mcp_info->func_info.bandwidth_max)
Gustavo A. R. Silvac7281d52018-03-22 15:08:49 -05001273 qm_info->pf_rl_en = true;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001274 if (p_hwfn->mcp_info->func_info.bandwidth_min)
Gustavo A. R. Silvac7281d52018-03-22 15:08:49 -05001275 qm_info->pf_wfq_en = true;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001276 }
1277
1278 memset(&params, 0, sizeof(params));
Tomer Tayar78cea9f2017-05-23 09:41:22 +03001279 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001280 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1281 params.pf_rl_en = qm_info->pf_rl_en;
1282 params.pf_wfq_en = qm_info->pf_wfq_en;
1283 params.vport_rl_en = qm_info->vport_rl_en;
1284 params.vport_wfq_en = qm_info->vport_wfq_en;
1285 params.port_params = qm_info->qm_port_params;
1286
1287 qed_qm_common_rt_init(p_hwfn, &params);
1288
1289 qed_cxt_hw_init_common(p_hwfn);
1290
Tomer Tayar60afed72017-04-06 15:58:30 +03001291 qed_init_cache_line_size(p_hwfn, p_ptt);
1292
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001293 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001294 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001295 return rc;
1296
1297 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1298 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1299
Yuval Mintzdbb799c2016-06-03 14:35:35 +03001300 if (QED_IS_BB(p_hwfn->cdev)) {
1301 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1302 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1303 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1304 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1305 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1306 }
1307 /* pretend to original PF */
1308 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1309 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001310
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001311 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1312 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001313 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1314 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1315 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001316 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1317 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1318 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001319 }
1320 /* pretend to original PF */
1321 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1322
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001323 return rc;
1324}
1325
Ram Amrani51ff1722016-10-01 21:59:57 +03001326static int
1327qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1328 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1329{
Ram Amrani107392b2017-04-30 11:49:09 +03001330 u32 dpi_bit_shift, dpi_count, dpi_page_size;
Ram Amrani51ff1722016-10-01 21:59:57 +03001331 u32 min_dpis;
Ram Amrani107392b2017-04-30 11:49:09 +03001332 u32 n_wids;
Ram Amrani51ff1722016-10-01 21:59:57 +03001333
1334 /* Calculate DPI size */
Ram Amrani107392b2017-04-30 11:49:09 +03001335 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1336 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1337 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
Ram Amrani51ff1722016-10-01 21:59:57 +03001338 dpi_bit_shift = ilog2(dpi_page_size / 4096);
Ram Amrani51ff1722016-10-01 21:59:57 +03001339 dpi_count = pwm_region_size / dpi_page_size;
1340
1341 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1342 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1343
1344 p_hwfn->dpi_size = dpi_page_size;
1345 p_hwfn->dpi_count = dpi_count;
1346
1347 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1348
1349 if (dpi_count < min_dpis)
1350 return -EINVAL;
1351
1352 return 0;
1353}
1354
1355enum QED_ROCE_EDPM_MODE {
1356 QED_ROCE_EDPM_MODE_ENABLE = 0,
1357 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1358 QED_ROCE_EDPM_MODE_DISABLE = 2,
1359};
1360
1361static int
1362qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1363{
1364 u32 pwm_regsize, norm_regsize;
1365 u32 non_pwm_conn, min_addr_reg1;
Ram Amrani20b1bd92017-04-30 11:49:10 +03001366 u32 db_bar_size, n_cpus = 1;
Ram Amrani51ff1722016-10-01 21:59:57 +03001367 u32 roce_edpm_mode;
1368 u32 pf_dems_shift;
1369 int rc = 0;
1370 u8 cond;
1371
Rahul Verma15582962017-04-06 15:58:29 +03001372 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
Ram Amrani51ff1722016-10-01 21:59:57 +03001373 if (p_hwfn->cdev->num_hwfns > 1)
1374 db_bar_size /= 2;
1375
1376 /* Calculate doorbell regions */
1377 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1378 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1379 NULL) +
1380 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1381 NULL);
Ram Amrania82dadb2017-05-09 15:07:50 +03001382 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
Ram Amrani51ff1722016-10-01 21:59:57 +03001383 min_addr_reg1 = norm_regsize / 4096;
1384 pwm_regsize = db_bar_size - norm_regsize;
1385
1386 /* Check that the normal and PWM sizes are valid */
1387 if (db_bar_size < norm_regsize) {
1388 DP_ERR(p_hwfn->cdev,
1389 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1390 db_bar_size, norm_regsize);
1391 return -EINVAL;
1392 }
1393
1394 if (pwm_regsize < QED_MIN_PWM_REGION) {
1395 DP_ERR(p_hwfn->cdev,
1396 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1397 pwm_regsize,
1398 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1399 return -EINVAL;
1400 }
1401
1402 /* Calculate number of DPIs */
1403 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1404 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1405 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1406 /* Either EDPM is mandatory, or we are attempting to allocate a
1407 * WID per CPU.
1408 */
Ram Amranic2dedf82017-02-20 22:43:33 +02001409 n_cpus = num_present_cpus();
Ram Amrani51ff1722016-10-01 21:59:57 +03001410 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1411 }
1412
1413 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1414 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1415 if (cond || p_hwfn->dcbx_no_edpm) {
1416 /* Either EDPM is disabled from user configuration, or it is
1417 * disabled via DCBx, or it is not mandatory and we failed to
1418 * allocated a WID per CPU.
1419 */
1420 n_cpus = 1;
1421 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1422
1423 if (cond)
1424 qed_rdma_dpm_bar(p_hwfn, p_ptt);
1425 }
1426
Ram Amrani20b1bd92017-04-30 11:49:10 +03001427 p_hwfn->wid_count = (u16) n_cpus;
1428
Ram Amrani51ff1722016-10-01 21:59:57 +03001429 DP_INFO(p_hwfn,
1430 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1431 norm_regsize,
1432 pwm_regsize,
1433 p_hwfn->dpi_size,
1434 p_hwfn->dpi_count,
1435 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1436 "disabled" : "enabled");
1437
1438 if (rc) {
1439 DP_ERR(p_hwfn,
1440 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1441 p_hwfn->dpi_count,
1442 p_hwfn->pf_params.rdma_pf_params.min_dpis);
1443 return -EINVAL;
1444 }
1445
1446 p_hwfn->dpi_start_offset = norm_regsize;
1447
1448 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1449 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1450 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1451 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1452
1453 return 0;
1454}
1455
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001456static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
Yuval Mintz1a635e42016-08-15 10:42:43 +03001457 struct qed_ptt *p_ptt, int hw_mode)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001458{
Mintz, Yuvalfc6575b2017-05-29 09:53:14 +03001459 int rc = 0;
1460
1461 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1462 if (rc)
1463 return rc;
1464
1465 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1466
1467 return 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001468}
1469
1470static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1471 struct qed_ptt *p_ptt,
Chopra, Manish199684302017-04-24 10:00:44 -07001472 struct qed_tunnel_info *p_tunn,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001473 int hw_mode,
1474 bool b_hw_start,
1475 enum qed_int_mode int_mode,
1476 bool allow_npar_tx_switch)
1477{
1478 u8 rel_pf_id = p_hwfn->rel_pf_id;
1479 int rc = 0;
1480
1481 if (p_hwfn->mcp_info) {
1482 struct qed_mcp_function_info *p_info;
1483
1484 p_info = &p_hwfn->mcp_info->func_info;
1485 if (p_info->bandwidth_min)
1486 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1487
1488 /* Update rate limit once we'll actually have a link */
Manish Chopra4b01e512016-04-26 10:56:09 -04001489 p_hwfn->qm_info.pf_rl = 100000;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001490 }
1491
Rahul Verma15582962017-04-06 15:58:29 +03001492 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001493
1494 qed_int_igu_init_rt(p_hwfn);
1495
1496 /* Set VLAN in NIG if needed */
Yuval Mintz1a635e42016-08-15 10:42:43 +03001497 if (hw_mode & BIT(MODE_MF_SD)) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001498 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1499 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1500 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1501 p_hwfn->hw_info.ovlan);
1502 }
1503
1504 /* Enable classification by MAC if needed */
Yuval Mintz1a635e42016-08-15 10:42:43 +03001505 if (hw_mode & BIT(MODE_MF_SI)) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001506 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1507 "Configuring TAGMAC_CLS_TYPE\n");
1508 STORE_RT_REG(p_hwfn,
1509 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1510 }
1511
Tomer Tayara2e76992017-12-27 19:30:05 +02001512 /* Protocol Configuration */
Yuval Mintzdbb799c2016-06-03 14:35:35 +03001513 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1514 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
Arun Easi1e128c82017-02-15 06:28:22 -08001515 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1516 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001517 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1518
1519 /* Cleanup chip from previous driver if such remains exist */
Yuval Mintz0b55e272016-05-11 16:36:15 +03001520 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001521 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001522 return rc;
1523
Tomer Tayarda090912017-12-27 19:30:07 +02001524 /* Sanity check before the PF init sequence that uses DMAE */
1525 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1526 if (rc)
1527 return rc;
1528
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001529 /* PF Init sequence */
1530 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1531 if (rc)
1532 return rc;
1533
1534 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1535 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1536 if (rc)
1537 return rc;
1538
1539 /* Pure runtime initializations - directly to the HW */
1540 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1541
Ram Amrani51ff1722016-10-01 21:59:57 +03001542 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1543 if (rc)
1544 return rc;
1545
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001546 if (b_hw_start) {
1547 /* enable interrupts */
1548 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1549
1550 /* send function start command */
Manish Chopra4f646752017-05-23 09:41:20 +03001551 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
Yuval Mintz831bfb0e2016-05-11 16:36:25 +03001552 allow_npar_tx_switch);
Arun Easi1e128c82017-02-15 06:28:22 -08001553 if (rc) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001554 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
Arun Easi1e128c82017-02-15 06:28:22 -08001555 return rc;
1556 }
1557 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1558 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1559 qed_wr(p_hwfn, p_ptt,
1560 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1561 0x100);
1562 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001563 }
1564 return rc;
1565}
1566
1567static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1568 struct qed_ptt *p_ptt,
1569 u8 enable)
1570{
1571 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1572
1573 /* Change PF in PXP */
1574 qed_wr(p_hwfn, p_ptt,
1575 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1576
1577 /* wait until value is set - try for 1 second every 50us */
1578 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1579 val = qed_rd(p_hwfn, p_ptt,
1580 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1581 if (val == set_val)
1582 break;
1583
1584 usleep_range(50, 60);
1585 }
1586
1587 if (val != set_val) {
1588 DP_NOTICE(p_hwfn,
1589 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1590 return -EAGAIN;
1591 }
1592
1593 return 0;
1594}
1595
1596static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1597 struct qed_ptt *p_main_ptt)
1598{
1599 /* Read shadow of current MFW mailbox */
1600 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1601 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
Yuval Mintz1a635e42016-08-15 10:42:43 +03001602 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001603}
1604
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001605static void
1606qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1607 struct qed_drv_load_params *p_drv_load)
1608{
1609 memset(p_load_req, 0, sizeof(*p_load_req));
1610
1611 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1612 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1613 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1614 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1615 p_load_req->override_force_load = p_drv_load->override_force_load;
1616}
1617
Chopra, Manisheaf3c0c2017-04-24 10:00:49 -07001618static int qed_vf_start(struct qed_hwfn *p_hwfn,
1619 struct qed_hw_init_params *p_params)
1620{
1621 if (p_params->p_tunn) {
1622 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1623 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1624 }
1625
Gustavo A. R. Silvac7281d52018-03-22 15:08:49 -05001626 p_hwfn->b_int_enabled = true;
Chopra, Manisheaf3c0c2017-04-24 10:00:49 -07001627
1628 return 0;
1629}
1630
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001631int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001632{
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001633 struct qed_load_req_params load_req_params;
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02001634 u32 load_code, param, drv_mb_param;
1635 bool b_default_mtu = true;
1636 struct qed_hwfn *p_hwfn;
1637 int rc = 0, mfw_rc, i;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001638
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001639 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
Sudarsana Reddy Kallurubb13ace2016-05-26 11:01:23 +03001640 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1641 return -EINVAL;
1642 }
1643
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001644 if (IS_PF(cdev)) {
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001645 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001646 if (rc)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001647 return rc;
1648 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001649
1650 for_each_hwfn(cdev, i) {
1651 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1652
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02001653 /* If management didn't provide a default, set one of our own */
1654 if (!p_hwfn->hw_info.mtu) {
1655 p_hwfn->hw_info.mtu = 1500;
1656 b_default_mtu = false;
1657 }
1658
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001659 if (IS_VF(cdev)) {
Chopra, Manisheaf3c0c2017-04-24 10:00:49 -07001660 qed_vf_start(p_hwfn, p_params);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001661 continue;
1662 }
1663
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001664 /* Enable DMAE in PXP */
1665 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1666
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001667 rc = qed_calc_hw_mode(p_hwfn);
1668 if (rc)
1669 return rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001670
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001671 qed_fill_load_req_params(&load_req_params,
1672 p_params->p_drv_load_params);
1673 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1674 &load_req_params);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001675 if (rc) {
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001676 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001677 return rc;
1678 }
1679
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001680 load_code = load_req_params.load_code;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001681 DP_VERBOSE(p_hwfn, QED_MSG_SP,
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001682 "Load request was sent. Load code: 0x%x\n",
1683 load_code);
1684
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -07001685 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
1686
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001687 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001688
1689 p_hwfn->first_on_engine = (load_code ==
1690 FW_MSG_CODE_DRV_LOAD_ENGINE);
1691
1692 switch (load_code) {
1693 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1694 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1695 p_hwfn->hw_info.hw_mode);
1696 if (rc)
1697 break;
1698 /* Fall into */
1699 case FW_MSG_CODE_DRV_LOAD_PORT:
1700 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1701 p_hwfn->hw_info.hw_mode);
1702 if (rc)
1703 break;
1704
1705 /* Fall into */
1706 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1707 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001708 p_params->p_tunn,
1709 p_hwfn->hw_info.hw_mode,
1710 p_params->b_hw_start,
1711 p_params->int_mode,
1712 p_params->allow_npar_tx_switch);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001713 break;
1714 default:
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001715 DP_NOTICE(p_hwfn,
1716 "Unexpected load code [0x%08x]", load_code);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001717 rc = -EINVAL;
1718 break;
1719 }
1720
1721 if (rc)
1722 DP_NOTICE(p_hwfn,
1723 "init phase failed for loadcode 0x%x (rc %d)\n",
1724 load_code, rc);
1725
1726 /* ACK mfw regardless of success or failure of initialization */
1727 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1728 DRV_MSG_CODE_LOAD_DONE,
1729 0, &load_code, &param);
1730 if (rc)
1731 return rc;
1732 if (mfw_rc) {
1733 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1734 return mfw_rc;
1735 }
1736
Tomer Tayarfc561c82017-05-23 09:41:21 +03001737 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1738 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1739 DP_NOTICE(p_hwfn,
1740 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1741
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001742 /* send DCBX attention request command */
1743 DP_VERBOSE(p_hwfn,
1744 QED_MSG_DCB,
1745 "sending phony dcbx set command to trigger DCBx attention handling\n");
1746 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1747 DRV_MSG_CODE_SET_DCBX,
1748 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1749 &load_code, &param);
1750 if (mfw_rc) {
1751 DP_NOTICE(p_hwfn,
1752 "Failed to send DCBX attention request\n");
1753 return mfw_rc;
1754 }
1755
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001756 p_hwfn->hw_init_done = true;
1757 }
1758
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02001759 if (IS_PF(cdev)) {
1760 p_hwfn = QED_LEADING_HWFN(cdev);
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001761 drv_mb_param = STORM_FW_VERSION;
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02001762 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1763 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1764 drv_mb_param, &load_code, &param);
1765 if (rc)
1766 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1767
1768 if (!b_default_mtu) {
1769 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1770 p_hwfn->hw_info.mtu);
1771 if (rc)
1772 DP_INFO(p_hwfn,
1773 "Failed to update default mtu\n");
1774 }
1775
1776 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1777 p_hwfn->p_main_ptt,
1778 QED_OV_DRIVER_STATE_DISABLED);
1779 if (rc)
1780 DP_INFO(p_hwfn, "Failed to update driver state\n");
1781
1782 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1783 QED_OV_ESWITCH_VEB);
1784 if (rc)
1785 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1786 }
1787
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001788 return 0;
1789}
1790
1791#define QED_HW_STOP_RETRY_LIMIT (10)
Yuval Mintz1a635e42016-08-15 10:42:43 +03001792static void qed_hw_timers_stop(struct qed_dev *cdev,
1793 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
Yuval Mintz8c925c42016-03-02 20:26:03 +02001794{
1795 int i;
1796
1797 /* close timers */
1798 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1799 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1800
1801 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1802 if ((!qed_rd(p_hwfn, p_ptt,
1803 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
Yuval Mintz1a635e42016-08-15 10:42:43 +03001804 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
Yuval Mintz8c925c42016-03-02 20:26:03 +02001805 break;
1806
1807 /* Dependent on number of connection/tasks, possibly
1808 * 1ms sleep is required between polls
1809 */
1810 usleep_range(1000, 2000);
1811 }
1812
1813 if (i < QED_HW_STOP_RETRY_LIMIT)
1814 return;
1815
1816 DP_NOTICE(p_hwfn,
1817 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1818 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1819 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1820}
1821
1822void qed_hw_timers_stop_all(struct qed_dev *cdev)
1823{
1824 int j;
1825
1826 for_each_hwfn(cdev, j) {
1827 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1828 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1829
1830 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1831 }
1832}
1833
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001834int qed_hw_stop(struct qed_dev *cdev)
1835{
Tomer Tayar12263372017-03-28 15:12:50 +03001836 struct qed_hwfn *p_hwfn;
1837 struct qed_ptt *p_ptt;
1838 int rc, rc2 = 0;
Yuval Mintz8c925c42016-03-02 20:26:03 +02001839 int j;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001840
1841 for_each_hwfn(cdev, j) {
Tomer Tayar12263372017-03-28 15:12:50 +03001842 p_hwfn = &cdev->hwfns[j];
1843 p_ptt = p_hwfn->p_main_ptt;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001844
1845 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1846
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001847 if (IS_VF(cdev)) {
Yuval Mintz0b55e272016-05-11 16:36:15 +03001848 qed_vf_pf_int_cleanup(p_hwfn);
Tomer Tayar12263372017-03-28 15:12:50 +03001849 rc = qed_vf_pf_reset(p_hwfn);
1850 if (rc) {
1851 DP_NOTICE(p_hwfn,
1852 "qed_vf_pf_reset failed. rc = %d.\n",
1853 rc);
1854 rc2 = -EINVAL;
1855 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001856 continue;
1857 }
1858
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001859 /* mark the hw as uninitialized... */
1860 p_hwfn->hw_init_done = false;
1861
Tomer Tayar12263372017-03-28 15:12:50 +03001862 /* Send unload command to MCP */
1863 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1864 if (rc) {
Yuval Mintz8c925c42016-03-02 20:26:03 +02001865 DP_NOTICE(p_hwfn,
Tomer Tayar12263372017-03-28 15:12:50 +03001866 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1867 rc);
1868 rc2 = -EINVAL;
1869 }
1870
1871 qed_slowpath_irq_sync(p_hwfn);
1872
1873 /* After this point no MFW attentions are expected, e.g. prevent
1874 * race between pf stop and dcbx pf update.
1875 */
1876 rc = qed_sp_pf_stop(p_hwfn);
1877 if (rc) {
1878 DP_NOTICE(p_hwfn,
1879 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1880 rc);
1881 rc2 = -EINVAL;
1882 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001883
1884 qed_wr(p_hwfn, p_ptt,
1885 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1886
1887 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1888 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1889 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1890 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1891 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1892
Yuval Mintz8c925c42016-03-02 20:26:03 +02001893 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001894
1895 /* Disable Attention Generation */
1896 qed_int_igu_disable_int(p_hwfn, p_ptt);
1897
1898 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1899 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1900
1901 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1902
1903 /* Need to wait 1ms to guarantee SBs are cleared */
1904 usleep_range(1000, 2000);
Tomer Tayar12263372017-03-28 15:12:50 +03001905
1906 /* Disable PF in HW blocks */
1907 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1908 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1909
1910 qed_mcp_unload_done(p_hwfn, p_ptt);
1911 if (rc) {
1912 DP_NOTICE(p_hwfn,
1913 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1914 rc);
1915 rc2 = -EINVAL;
1916 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001917 }
1918
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001919 if (IS_PF(cdev)) {
Tomer Tayar12263372017-03-28 15:12:50 +03001920 p_hwfn = QED_LEADING_HWFN(cdev);
1921 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1922
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001923 /* Disable DMAE in PXP - in CMT, this should only be done for
1924 * first hw-function, and only after all transactions have
1925 * stopped for all active hw-functions.
1926 */
Tomer Tayar12263372017-03-28 15:12:50 +03001927 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1928 if (rc) {
1929 DP_NOTICE(p_hwfn,
1930 "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1931 rc2 = -EINVAL;
1932 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001933 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001934
Tomer Tayar12263372017-03-28 15:12:50 +03001935 return rc2;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001936}
1937
Rahul Verma15582962017-04-06 15:58:29 +03001938int qed_hw_stop_fastpath(struct qed_dev *cdev)
Manish Chopracee4d262015-10-26 11:02:28 +02001939{
Yuval Mintz8c925c42016-03-02 20:26:03 +02001940 int j;
Manish Chopracee4d262015-10-26 11:02:28 +02001941
1942 for_each_hwfn(cdev, j) {
1943 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
Rahul Verma15582962017-04-06 15:58:29 +03001944 struct qed_ptt *p_ptt;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001945
1946 if (IS_VF(cdev)) {
1947 qed_vf_pf_int_cleanup(p_hwfn);
1948 continue;
1949 }
Rahul Verma15582962017-04-06 15:58:29 +03001950 p_ptt = qed_ptt_acquire(p_hwfn);
1951 if (!p_ptt)
1952 return -EAGAIN;
Manish Chopracee4d262015-10-26 11:02:28 +02001953
1954 DP_VERBOSE(p_hwfn,
Yuval Mintz1a635e42016-08-15 10:42:43 +03001955 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
Manish Chopracee4d262015-10-26 11:02:28 +02001956
1957 qed_wr(p_hwfn, p_ptt,
1958 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1959
1960 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1961 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1962 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1963 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1964 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1965
Manish Chopracee4d262015-10-26 11:02:28 +02001966 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1967
1968 /* Need to wait 1ms to guarantee SBs are cleared */
1969 usleep_range(1000, 2000);
Rahul Verma15582962017-04-06 15:58:29 +03001970 qed_ptt_release(p_hwfn, p_ptt);
Manish Chopracee4d262015-10-26 11:02:28 +02001971 }
Rahul Verma15582962017-04-06 15:58:29 +03001972
1973 return 0;
Manish Chopracee4d262015-10-26 11:02:28 +02001974}
1975
Rahul Verma15582962017-04-06 15:58:29 +03001976int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
Manish Chopracee4d262015-10-26 11:02:28 +02001977{
Rahul Verma15582962017-04-06 15:58:29 +03001978 struct qed_ptt *p_ptt;
1979
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001980 if (IS_VF(p_hwfn->cdev))
Rahul Verma15582962017-04-06 15:58:29 +03001981 return 0;
1982
1983 p_ptt = qed_ptt_acquire(p_hwfn);
1984 if (!p_ptt)
1985 return -EAGAIN;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001986
Michal Kalderonf855df22017-05-23 09:41:25 +03001987 /* If roce info is allocated it means roce is initialized and should
1988 * be enabled in searcher.
1989 */
1990 if (p_hwfn->p_rdma_info &&
1991 p_hwfn->b_rdma_enabled_in_prs)
1992 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
1993
Manish Chopracee4d262015-10-26 11:02:28 +02001994 /* Re-open incoming traffic */
Rahul Verma15582962017-04-06 15:58:29 +03001995 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1996 qed_ptt_release(p_hwfn, p_ptt);
1997
1998 return 0;
Manish Chopracee4d262015-10-26 11:02:28 +02001999}
2000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002001/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2002static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2003{
2004 qed_ptt_pool_free(p_hwfn);
2005 kfree(p_hwfn->hw_info.p_igu_info);
Tomer Tayar3587cb82017-05-21 12:10:56 +03002006 p_hwfn->hw_info.p_igu_info = NULL;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002007}
2008
2009/* Setup bar access */
Yuval Mintz12e09c62016-03-02 20:26:01 +02002010static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002011{
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002012 /* clear indirect access */
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002013 if (QED_IS_AH(p_hwfn->cdev)) {
2014 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2015 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2016 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2017 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2018 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2019 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2020 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2021 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2022 } else {
2023 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2024 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2025 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2026 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2027 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2028 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2029 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2030 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2031 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002032
2033 /* Clean Previous errors if such exist */
2034 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
Yuval Mintz1a635e42016-08-15 10:42:43 +03002035 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002036
2037 /* enable internal target-read */
2038 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2039 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002040}
2041
2042static void get_function_id(struct qed_hwfn *p_hwfn)
2043{
2044 /* ME Register */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002045 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2046 PXP_PF_ME_OPAQUE_ADDR);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002047
2048 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2049
2050 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2051 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2052 PXP_CONCRETE_FID_PFID);
2053 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2054 PXP_CONCRETE_FID_PORT);
Yuval Mintz525ef5c2016-08-15 10:42:45 +03002055
2056 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2057 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2058 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002059}
2060
Yuval Mintz25c089d2015-10-26 11:02:26 +02002061static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2062{
2063 u32 *feat_num = p_hwfn->hw_info.feat_num;
Mintz, Yuvalebbdcc62017-06-01 15:29:10 +03002064 struct qed_sb_cnt_info sb_cnt;
Mintz, Yuval810bb1f2017-03-23 15:50:19 +02002065 u32 non_l2_sbs = 0;
Yuval Mintz25c089d2015-10-26 11:02:26 +02002066
Mintz, Yuvalebbdcc62017-06-01 15:29:10 +03002067 memset(&sb_cnt, 0, sizeof(sb_cnt));
2068 qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2069
Yuval Mintz0189efb2016-10-13 22:57:02 +03002070 if (IS_ENABLED(CONFIG_QED_RDMA) &&
Kalderon, Michalc851a9d2017-07-02 10:29:21 +03002071 QED_IS_RDMA_PERSONALITY(p_hwfn)) {
Yuval Mintz0189efb2016-10-13 22:57:02 +03002072 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2073 * the status blocks equally between L2 / RoCE but with
2074 * consideration as to how many l2 queues / cnqs we have.
2075 */
Ram Amrani51ff1722016-10-01 21:59:57 +03002076 feat_num[QED_RDMA_CNQ] =
Mintz, Yuvalebbdcc62017-06-01 15:29:10 +03002077 min_t(u32, sb_cnt.cnt / 2,
Ram Amrani51ff1722016-10-01 21:59:57 +03002078 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
Mintz, Yuval810bb1f2017-03-23 15:50:19 +02002079
2080 non_l2_sbs = feat_num[QED_RDMA_CNQ];
Ram Amrani51ff1722016-10-01 21:59:57 +03002081 }
Kalderon, Michalc851a9d2017-07-02 10:29:21 +03002082 if (QED_IS_L2_PERSONALITY(p_hwfn)) {
Mintz, Yuvaldec26532017-03-23 15:50:20 +02002083 /* Start by allocating VF queues, then PF's */
Mintz, Yuvaldec26532017-03-23 15:50:20 +02002084 feat_num[QED_VF_L2_QUE] = min_t(u32,
2085 RESC_NUM(p_hwfn, QED_L2_QUEUE),
Mintz, Yuvalebbdcc62017-06-01 15:29:10 +03002086 sb_cnt.iov_cnt);
Mintz, Yuvaldec26532017-03-23 15:50:20 +02002087 feat_num[QED_PF_L2_QUE] = min_t(u32,
Mintz, Yuvalebbdcc62017-06-01 15:29:10 +03002088 sb_cnt.cnt - non_l2_sbs,
Mintz, Yuvaldec26532017-03-23 15:50:20 +02002089 RESC_NUM(p_hwfn,
2090 QED_L2_QUEUE) -
2091 FEAT_NUM(p_hwfn,
2092 QED_VF_L2_QUE));
2093 }
Mintz, Yuval5a1f9652016-10-31 07:14:26 +02002094
Kalderon, Michalc851a9d2017-07-02 10:29:21 +03002095 if (QED_IS_FCOE_PERSONALITY(p_hwfn))
Mintz, Yuval3c5da942017-06-02 08:58:31 +03002096 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt,
2097 RESC_NUM(p_hwfn,
2098 QED_CMDQS_CQS));
2099
Kalderon, Michalc851a9d2017-07-02 10:29:21 +03002100 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
Mintz, Yuvalebbdcc62017-06-01 15:29:10 +03002101 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
Mintz, Yuval08737a32017-04-06 15:58:33 +03002102 RESC_NUM(p_hwfn,
2103 QED_CMDQS_CQS));
Mintz, Yuval5a1f9652016-10-31 07:14:26 +02002104 DP_VERBOSE(p_hwfn,
2105 NETIF_MSG_PROBE,
Mintz, Yuval3c5da942017-06-02 08:58:31 +03002106 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
Mintz, Yuval5a1f9652016-10-31 07:14:26 +02002107 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2108 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2109 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
Mintz, Yuval3c5da942017-06-02 08:58:31 +03002110 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
Mintz, Yuval08737a32017-04-06 15:58:33 +03002111 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
Mintz, Yuvalebbdcc62017-06-01 15:29:10 +03002112 (int)sb_cnt.cnt);
Yuval Mintz25c089d2015-10-26 11:02:26 +02002113}
2114
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002115const char *qed_hw_get_resc_name(enum qed_resources res_id)
Tomer Tayar2edbff82016-10-31 07:14:27 +02002116{
2117 switch (res_id) {
Tomer Tayar2edbff82016-10-31 07:14:27 +02002118 case QED_L2_QUEUE:
2119 return "L2_QUEUE";
2120 case QED_VPORT:
2121 return "VPORT";
2122 case QED_RSS_ENG:
2123 return "RSS_ENG";
2124 case QED_PQ:
2125 return "PQ";
2126 case QED_RL:
2127 return "RL";
2128 case QED_MAC:
2129 return "MAC";
2130 case QED_VLAN:
2131 return "VLAN";
2132 case QED_RDMA_CNQ_RAM:
2133 return "RDMA_CNQ_RAM";
2134 case QED_ILT:
2135 return "ILT";
2136 case QED_LL2_QUEUE:
2137 return "LL2_QUEUE";
2138 case QED_CMDQS_CQS:
2139 return "CMDQS_CQS";
2140 case QED_RDMA_STATS_QUEUE:
2141 return "RDMA_STATS_QUEUE";
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002142 case QED_BDQ:
2143 return "BDQ";
2144 case QED_SB:
2145 return "SB";
Tomer Tayar2edbff82016-10-31 07:14:27 +02002146 default:
2147 return "UNKNOWN_RESOURCE";
2148 }
2149}
2150
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002151static int
2152__qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2153 struct qed_ptt *p_ptt,
2154 enum qed_resources res_id,
2155 u32 resc_max_val, u32 *p_mcp_resp)
Tomer Tayar2edbff82016-10-31 07:14:27 +02002156{
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002157 int rc;
2158
2159 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2160 resc_max_val, p_mcp_resp);
2161 if (rc) {
2162 DP_NOTICE(p_hwfn,
2163 "MFW response failure for a max value setting of resource %d [%s]\n",
2164 res_id, qed_hw_get_resc_name(res_id));
2165 return rc;
2166 }
2167
2168 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2169 DP_INFO(p_hwfn,
2170 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2171 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2172
2173 return 0;
2174}
2175
2176static int
2177qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2178{
2179 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2180 u32 resc_max_val, mcp_resp;
2181 u8 res_id;
2182 int rc;
2183
2184 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2185 switch (res_id) {
2186 case QED_LL2_QUEUE:
2187 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2188 break;
2189 case QED_RDMA_CNQ_RAM:
2190 /* No need for a case for QED_CMDQS_CQS since
2191 * CNQ/CMDQS are the same resource.
2192 */
Tomer Tayarda090912017-12-27 19:30:07 +02002193 resc_max_val = NUM_OF_GLOBAL_QUEUES;
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002194 break;
2195 case QED_RDMA_STATS_QUEUE:
2196 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2197 : RDMA_NUM_STATISTIC_COUNTERS_BB;
2198 break;
2199 case QED_BDQ:
2200 resc_max_val = BDQ_NUM_RESOURCES;
2201 break;
2202 default:
2203 continue;
2204 }
2205
2206 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2207 resc_max_val, &mcp_resp);
2208 if (rc)
2209 return rc;
2210
2211 /* There's no point to continue to the next resource if the
2212 * command is not supported by the MFW.
2213 * We do continue if the command is supported but the resource
2214 * is unknown to the MFW. Such a resource will be later
2215 * configured with the default allocation values.
2216 */
2217 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2218 return -EINVAL;
2219 }
2220
2221 return 0;
2222}
2223
2224static
2225int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2226 enum qed_resources res_id,
2227 u32 *p_resc_num, u32 *p_resc_start)
2228{
2229 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2230 bool b_ah = QED_IS_AH(p_hwfn->cdev);
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002231
2232 switch (res_id) {
2233 case QED_L2_QUEUE:
2234 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2235 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2236 break;
2237 case QED_VPORT:
2238 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2239 MAX_NUM_VPORTS_BB) / num_funcs;
2240 break;
2241 case QED_RSS_ENG:
2242 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2243 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2244 break;
2245 case QED_PQ:
2246 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2247 MAX_QM_TX_QUEUES_BB) / num_funcs;
2248 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
2249 break;
2250 case QED_RL:
2251 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2252 break;
2253 case QED_MAC:
2254 case QED_VLAN:
2255 /* Each VFC resource can accommodate both a MAC and a VLAN */
2256 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2257 break;
2258 case QED_ILT:
2259 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2260 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2261 break;
2262 case QED_LL2_QUEUE:
2263 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2264 break;
2265 case QED_RDMA_CNQ_RAM:
2266 case QED_CMDQS_CQS:
2267 /* CNQ/CMDQS are the same resource */
Tomer Tayarda090912017-12-27 19:30:07 +02002268 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002269 break;
2270 case QED_RDMA_STATS_QUEUE:
2271 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2272 RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2273 break;
2274 case QED_BDQ:
2275 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2276 p_hwfn->hw_info.personality != QED_PCI_FCOE)
2277 *p_resc_num = 0;
2278 else
2279 *p_resc_num = 1;
2280 break;
2281 case QED_SB:
Mintz, Yuvalebbdcc62017-06-01 15:29:10 +03002282 /* Since we want its value to reflect whether MFW supports
2283 * the new scheme, have a default of 0.
2284 */
2285 *p_resc_num = 0;
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002286 break;
2287 default:
2288 return -EINVAL;
2289 }
2290
2291 switch (res_id) {
2292 case QED_BDQ:
2293 if (!*p_resc_num)
2294 *p_resc_start = 0;
Tomer Tayar78cea9f2017-05-23 09:41:22 +03002295 else if (p_hwfn->cdev->num_ports_in_engine == 4)
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002296 *p_resc_start = p_hwfn->port_id;
2297 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2298 *p_resc_start = p_hwfn->port_id;
2299 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2300 *p_resc_start = p_hwfn->port_id + 2;
2301 break;
2302 default:
2303 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2304 break;
2305 }
2306
2307 return 0;
2308}
2309
2310static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2311 enum qed_resources res_id)
2312{
2313 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2314 u32 mcp_resp, *p_resc_num, *p_resc_start;
Tomer Tayar2edbff82016-10-31 07:14:27 +02002315 int rc;
2316
2317 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2318 p_resc_start = &RESC_START(p_hwfn, res_id);
2319
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002320 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2321 &dflt_resc_start);
2322 if (rc) {
Tomer Tayar2edbff82016-10-31 07:14:27 +02002323 DP_ERR(p_hwfn,
2324 "Failed to get default amount for resource %d [%s]\n",
2325 res_id, qed_hw_get_resc_name(res_id));
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002326 return rc;
Tomer Tayar2edbff82016-10-31 07:14:27 +02002327 }
2328
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002329 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2330 &mcp_resp, p_resc_num, p_resc_start);
Tomer Tayar2edbff82016-10-31 07:14:27 +02002331 if (rc) {
2332 DP_NOTICE(p_hwfn,
2333 "MFW response failure for an allocation request for resource %d [%s]\n",
2334 res_id, qed_hw_get_resc_name(res_id));
2335 return rc;
2336 }
2337
2338 /* Default driver values are applied in the following cases:
2339 * - The resource allocation MB command is not supported by the MFW
2340 * - There is an internal error in the MFW while processing the request
2341 * - The resource ID is unknown to the MFW
2342 */
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002343 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2344 DP_INFO(p_hwfn,
2345 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2346 res_id,
2347 qed_hw_get_resc_name(res_id),
2348 mcp_resp, dflt_resc_num, dflt_resc_start);
Tomer Tayar2edbff82016-10-31 07:14:27 +02002349 *p_resc_num = dflt_resc_num;
2350 *p_resc_start = dflt_resc_start;
2351 goto out;
2352 }
2353
Tomer Tayar2edbff82016-10-31 07:14:27 +02002354out:
2355 /* PQs have to divide by 8 [that's the HW granularity].
2356 * Reduce number so it would fit.
2357 */
2358 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2359 DP_INFO(p_hwfn,
2360 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2361 *p_resc_num,
2362 (*p_resc_num) & ~0x7,
2363 *p_resc_start, (*p_resc_start) & ~0x7);
2364 *p_resc_num &= ~0x7;
2365 *p_resc_start &= ~0x7;
2366 }
2367
2368 return 0;
2369}
2370
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002371static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002372{
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002373 int rc;
2374 u8 res_id;
2375
2376 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2377 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2378 if (rc)
2379 return rc;
2380 }
2381
2382 return 0;
2383}
2384
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002385static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2386{
2387 struct qed_resc_unlock_params resc_unlock_params;
2388 struct qed_resc_lock_params resc_lock_params;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002389 bool b_ah = QED_IS_AH(p_hwfn->cdev);
Tomer Tayar2edbff82016-10-31 07:14:27 +02002390 u8 res_id;
2391 int rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002392
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002393 /* Setting the max values of the soft resources and the following
2394 * resources allocation queries should be atomic. Since several PFs can
2395 * run in parallel - a resource lock is needed.
2396 * If either the resource lock or resource set value commands are not
2397 * supported - skip the the max values setting, release the lock if
2398 * needed, and proceed to the queries. Other failures, including a
2399 * failure to acquire the lock, will cause this function to fail.
2400 */
sudarsana.kalluru@cavium.comf470f222017-04-26 09:00:49 -07002401 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2402 QED_RESC_LOCK_RESC_ALLOC, false);
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002403
2404 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2405 if (rc && rc != -EINVAL) {
2406 return rc;
2407 } else if (rc == -EINVAL) {
2408 DP_INFO(p_hwfn,
2409 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2410 } else if (!rc && !resc_lock_params.b_granted) {
2411 DP_NOTICE(p_hwfn,
2412 "Failed to acquire the resource lock for the resource allocation commands\n");
2413 return -EBUSY;
2414 } else {
2415 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2416 if (rc && rc != -EINVAL) {
2417 DP_NOTICE(p_hwfn,
2418 "Failed to set the max values of the soft resources\n");
2419 goto unlock_and_exit;
2420 } else if (rc == -EINVAL) {
2421 DP_INFO(p_hwfn,
2422 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2423 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2424 &resc_unlock_params);
2425 if (rc)
2426 DP_INFO(p_hwfn,
2427 "Failed to release the resource lock for the resource allocation commands\n");
2428 }
2429 }
2430
2431 rc = qed_hw_set_resc_info(p_hwfn);
2432 if (rc)
2433 goto unlock_and_exit;
2434
2435 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2436 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
Tomer Tayar2edbff82016-10-31 07:14:27 +02002437 if (rc)
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002438 DP_INFO(p_hwfn,
2439 "Failed to release the resource lock for the resource allocation commands\n");
Tomer Tayar2edbff82016-10-31 07:14:27 +02002440 }
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002441
2442 /* Sanity for ILT */
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002443 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2444 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002445 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2446 RESC_START(p_hwfn, QED_ILT),
2447 RESC_END(p_hwfn, QED_ILT) - 1);
2448 return -EINVAL;
2449 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002450
Mintz, Yuvalebbdcc62017-06-01 15:29:10 +03002451 /* This will also learn the number of SBs from MFW */
2452 if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2453 return -EINVAL;
2454
Yuval Mintz25c089d2015-10-26 11:02:26 +02002455 qed_hw_set_feat(p_hwfn);
2456
Tomer Tayar2edbff82016-10-31 07:14:27 +02002457 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2458 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2459 qed_hw_get_resc_name(res_id),
2460 RESC_NUM(p_hwfn, res_id),
2461 RESC_START(p_hwfn, res_id));
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002462
2463 return 0;
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002464
2465unlock_and_exit:
2466 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2467 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2468 return rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002469}
2470
Yuval Mintz1a635e42016-08-15 10:42:43 +03002471static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002472{
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002473 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
Arun Easi1e128c82017-02-15 06:28:22 -08002474 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -07002475 struct qed_mcp_link_capabilities *p_caps;
Yuval Mintzcc875c22015-10-26 11:02:31 +02002476 struct qed_mcp_link_params *link;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002477
2478 /* Read global nvm_cfg address */
2479 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2480
2481 /* Verify MCP has initialized it */
2482 if (!nvm_cfg_addr) {
2483 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2484 return -EINVAL;
2485 }
2486
2487 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2488 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2489
Yuval Mintzcc875c22015-10-26 11:02:31 +02002490 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2491 offsetof(struct nvm_cfg1, glob) +
2492 offsetof(struct nvm_cfg1_glob, core_cfg);
2493
2494 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2495
2496 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2497 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002498 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002499 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2500 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002501 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002502 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2503 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002504 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002505 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2506 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002507 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002508 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2509 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002510 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002511 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2512 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002513 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002514 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2515 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002516 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002517 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2518 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002519 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002520 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2521 break;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002522 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2523 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2524 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002525 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002526 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2527 break;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002528 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2529 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2530 break;
Yuval Mintzcc875c22015-10-26 11:02:31 +02002531 default:
Yuval Mintz1a635e42016-08-15 10:42:43 +03002532 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
Yuval Mintzcc875c22015-10-26 11:02:31 +02002533 break;
2534 }
2535
Yuval Mintzcc875c22015-10-26 11:02:31 +02002536 /* Read default link configuration */
2537 link = &p_hwfn->mcp_info->link_input;
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -07002538 p_caps = &p_hwfn->mcp_info->link_capabilities;
Yuval Mintzcc875c22015-10-26 11:02:31 +02002539 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2540 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2541 link_temp = qed_rd(p_hwfn, p_ptt,
2542 port_cfg_addr +
2543 offsetof(struct nvm_cfg1_port, speed_cap_mask));
Yuval Mintz83aeb932016-08-15 10:42:44 +03002544 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2545 link->speed.advertised_speeds = link_temp;
Yuval Mintzcc875c22015-10-26 11:02:31 +02002546
Yuval Mintz83aeb932016-08-15 10:42:44 +03002547 link_temp = link->speed.advertised_speeds;
2548 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
Yuval Mintzcc875c22015-10-26 11:02:31 +02002549
2550 link_temp = qed_rd(p_hwfn, p_ptt,
2551 port_cfg_addr +
2552 offsetof(struct nvm_cfg1_port, link_settings));
2553 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2554 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2555 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2556 link->speed.autoneg = true;
2557 break;
2558 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2559 link->speed.forced_speed = 1000;
2560 break;
2561 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2562 link->speed.forced_speed = 10000;
2563 break;
2564 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2565 link->speed.forced_speed = 25000;
2566 break;
2567 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2568 link->speed.forced_speed = 40000;
2569 break;
2570 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2571 link->speed.forced_speed = 50000;
2572 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002573 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02002574 link->speed.forced_speed = 100000;
2575 break;
2576 default:
Yuval Mintz1a635e42016-08-15 10:42:43 +03002577 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
Yuval Mintzcc875c22015-10-26 11:02:31 +02002578 }
2579
sudarsana.kalluru@cavium.com34f91992017-05-04 08:15:04 -07002580 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2581 link->speed.autoneg;
2582
Yuval Mintzcc875c22015-10-26 11:02:31 +02002583 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2584 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2585 link->pause.autoneg = !!(link_temp &
2586 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2587 link->pause.forced_rx = !!(link_temp &
2588 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2589 link->pause.forced_tx = !!(link_temp &
2590 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2591 link->loopback_mode = 0;
2592
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -07002593 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
2594 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
2595 offsetof(struct nvm_cfg1_port, ext_phy));
2596 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
2597 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
2598 p_caps->default_eee = QED_MCP_EEE_ENABLED;
2599 link->eee.enable = true;
2600 switch (link_temp) {
2601 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
2602 p_caps->default_eee = QED_MCP_EEE_DISABLED;
2603 link->eee.enable = false;
2604 break;
2605 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
2606 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
2607 break;
2608 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
2609 p_caps->eee_lpi_timer =
2610 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
2611 break;
2612 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
2613 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
2614 break;
2615 }
2616
2617 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
2618 link->eee.tx_lpi_enable = link->eee.enable;
2619 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
2620 } else {
2621 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
2622 }
2623
2624 DP_VERBOSE(p_hwfn,
2625 NETIF_MSG_LINK,
2626 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
2627 link->speed.forced_speed,
2628 link->speed.advertised_speeds,
2629 link->speed.autoneg,
2630 link->pause.autoneg,
2631 p_caps->default_eee, p_caps->eee_lpi_timer);
Yuval Mintzcc875c22015-10-26 11:02:31 +02002632
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002633 /* Read Multi-function information from shmem */
2634 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2635 offsetof(struct nvm_cfg1, glob) +
2636 offsetof(struct nvm_cfg1_glob, generic_cont0);
2637
2638 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2639
2640 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2641 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2642
2643 switch (mf_mode) {
2644 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07002645 p_hwfn->cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002646 break;
2647 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07002648 p_hwfn->cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2649 BIT(QED_MF_LLH_PROTO_CLSS) |
2650 BIT(QED_MF_LL2_NON_UNICAST) |
2651 BIT(QED_MF_INTER_PF_SWITCH);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002652 break;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002653 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07002654 p_hwfn->cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2655 BIT(QED_MF_LLH_PROTO_CLSS) |
2656 BIT(QED_MF_LL2_NON_UNICAST);
2657 if (QED_IS_BB(p_hwfn->cdev))
2658 p_hwfn->cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002659 break;
2660 }
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07002661
2662 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2663 p_hwfn->cdev->mf_bits);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002664
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002665 /* Read Multi-function information from shmem */
2666 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2667 offsetof(struct nvm_cfg1, glob) +
2668 offsetof(struct nvm_cfg1_glob, device_capabilities);
2669
2670 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2671 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2672 __set_bit(QED_DEV_CAP_ETH,
2673 &p_hwfn->hw_info.device_capabilities);
Arun Easi1e128c82017-02-15 06:28:22 -08002674 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2675 __set_bit(QED_DEV_CAP_FCOE,
2676 &p_hwfn->hw_info.device_capabilities);
Yuval Mintzc5ac9312016-06-03 14:35:34 +03002677 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2678 __set_bit(QED_DEV_CAP_ISCSI,
2679 &p_hwfn->hw_info.device_capabilities);
2680 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2681 __set_bit(QED_DEV_CAP_ROCE,
2682 &p_hwfn->hw_info.device_capabilities);
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002683
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002684 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2685}
2686
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002687static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2688{
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002689 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2690 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002691 struct qed_dev *cdev = p_hwfn->cdev;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002692
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002693 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002694
2695 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2696 * in the other bits are selected.
2697 * Bits 1-15 are for functions 1-15, respectively, and their value is
2698 * '0' only for enabled functions (function 0 always exists and
2699 * enabled).
2700 * In case of CMT, only the "even" functions are enabled, and thus the
2701 * number of functions for both hwfns is learnt from the same bits.
2702 */
2703 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2704
2705 if (reg_function_hide & 0x1) {
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002706 if (QED_IS_BB(cdev)) {
2707 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2708 num_funcs = 0;
2709 eng_mask = 0xaaaa;
2710 } else {
2711 num_funcs = 1;
2712 eng_mask = 0x5554;
2713 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002714 } else {
2715 num_funcs = 1;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002716 eng_mask = 0xfffe;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002717 }
2718
2719 /* Get the number of the enabled functions on the engine */
2720 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2721 while (tmp) {
2722 if (tmp & 0x1)
2723 num_funcs++;
2724 tmp >>= 0x1;
2725 }
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002726
2727 /* Get the PF index within the enabled functions */
2728 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2729 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2730 while (tmp) {
2731 if (tmp & 0x1)
2732 enabled_func_idx--;
2733 tmp >>= 0x1;
2734 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002735 }
2736
2737 p_hwfn->num_funcs_on_engine = num_funcs;
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002738 p_hwfn->enabled_func_idx = enabled_func_idx;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002739
2740 DP_VERBOSE(p_hwfn,
2741 NETIF_MSG_PROBE,
Yuval Mintz525ef5c2016-08-15 10:42:45 +03002742 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002743 p_hwfn->rel_pf_id,
2744 p_hwfn->abs_pf_id,
Yuval Mintz525ef5c2016-08-15 10:42:45 +03002745 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002746}
2747
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002748static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2749 struct qed_ptt *p_ptt)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002750{
2751 u32 port_mode;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002752
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002753 port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002754
2755 if (port_mode < 3) {
Tomer Tayar78cea9f2017-05-23 09:41:22 +03002756 p_hwfn->cdev->num_ports_in_engine = 1;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002757 } else if (port_mode <= 5) {
Tomer Tayar78cea9f2017-05-23 09:41:22 +03002758 p_hwfn->cdev->num_ports_in_engine = 2;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002759 } else {
2760 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
Tomer Tayar78cea9f2017-05-23 09:41:22 +03002761 p_hwfn->cdev->num_ports_in_engine);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002762
Tomer Tayar78cea9f2017-05-23 09:41:22 +03002763 /* Default num_ports_in_engine to something */
2764 p_hwfn->cdev->num_ports_in_engine = 1;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002765 }
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002766}
2767
2768static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2769 struct qed_ptt *p_ptt)
2770{
2771 u32 port;
2772 int i;
2773
Tomer Tayar78cea9f2017-05-23 09:41:22 +03002774 p_hwfn->cdev->num_ports_in_engine = 0;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002775
2776 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2777 port = qed_rd(p_hwfn, p_ptt,
2778 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2779 if (port & 1)
Tomer Tayar78cea9f2017-05-23 09:41:22 +03002780 p_hwfn->cdev->num_ports_in_engine++;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002781 }
2782
Tomer Tayar78cea9f2017-05-23 09:41:22 +03002783 if (!p_hwfn->cdev->num_ports_in_engine) {
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002784 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2785
2786 /* Default num_ports_in_engine to something */
Tomer Tayar78cea9f2017-05-23 09:41:22 +03002787 p_hwfn->cdev->num_ports_in_engine = 1;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002788 }
2789}
2790
2791static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2792{
2793 if (QED_IS_BB(p_hwfn->cdev))
2794 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2795 else
2796 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2797}
2798
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -07002799static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2800{
2801 struct qed_mcp_link_capabilities *p_caps;
2802 u32 eee_status;
2803
2804 p_caps = &p_hwfn->mcp_info->link_capabilities;
2805 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
2806 return;
2807
2808 p_caps->eee_speed_caps = 0;
2809 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
2810 offsetof(struct public_port, eee_status));
2811 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
2812 EEE_SUPPORTED_SPEED_OFFSET;
2813
2814 if (eee_status & EEE_1G_SUPPORTED)
2815 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
2816 if (eee_status & EEE_10G_ADV)
2817 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
2818}
2819
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002820static int
2821qed_get_hw_info(struct qed_hwfn *p_hwfn,
2822 struct qed_ptt *p_ptt,
2823 enum qed_pci_personality personality)
2824{
2825 int rc;
2826
2827 /* Since all information is common, only first hwfns should do this */
2828 if (IS_LEAD_HWFN(p_hwfn)) {
2829 rc = qed_iov_hw_info(p_hwfn);
2830 if (rc)
2831 return rc;
2832 }
2833
2834 qed_hw_info_port_num(p_hwfn, p_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002835
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -07002836 qed_mcp_get_capabilities(p_hwfn, p_ptt);
2837
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002838 qed_hw_get_nvm_info(p_hwfn, p_ptt);
2839
2840 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2841 if (rc)
2842 return rc;
2843
2844 if (qed_mcp_is_init(p_hwfn))
2845 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2846 p_hwfn->mcp_info->func_info.mac);
2847 else
2848 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2849
2850 if (qed_mcp_is_init(p_hwfn)) {
2851 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2852 p_hwfn->hw_info.ovlan =
2853 p_hwfn->mcp_info->func_info.ovlan;
2854
2855 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -07002856
2857 qed_get_eee_caps(p_hwfn, p_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002858 }
2859
2860 if (qed_mcp_is_init(p_hwfn)) {
2861 enum qed_pci_personality protocol;
2862
2863 protocol = p_hwfn->mcp_info->func_info.protocol;
2864 p_hwfn->hw_info.personality = protocol;
2865 }
2866
Ariel Eliorb5a9ee72017-04-03 12:21:09 +03002867 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2868 p_hwfn->hw_info.num_active_tc = 1;
2869
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002870 qed_get_num_funcs(p_hwfn, p_ptt);
2871
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02002872 if (qed_mcp_is_init(p_hwfn))
2873 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2874
Tomer Tayar9c8517c2017-03-28 15:12:55 +03002875 return qed_hw_get_resc(p_hwfn, p_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002876}
2877
Rahul Verma15582962017-04-06 15:58:29 +03002878static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002879{
Rahul Verma15582962017-04-06 15:58:29 +03002880 struct qed_dev *cdev = p_hwfn->cdev;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002881 u16 device_id_mask;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002882 u32 tmp;
2883
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002884 /* Read Vendor Id / Device Id */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002885 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2886 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2887
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002888 /* Determine type */
2889 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2890 switch (device_id_mask) {
2891 case QED_DEV_ID_MASK_BB:
2892 cdev->type = QED_DEV_TYPE_BB;
2893 break;
2894 case QED_DEV_ID_MASK_AH:
2895 cdev->type = QED_DEV_TYPE_AH;
2896 break;
2897 default:
2898 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2899 return -EBUSY;
2900 }
2901
Rahul Verma15582962017-04-06 15:58:29 +03002902 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2903 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2904
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002905 MASK_FIELD(CHIP_REV, cdev->chip_rev);
2906
2907 /* Learn number of HW-functions */
Rahul Verma15582962017-04-06 15:58:29 +03002908 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002909
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002910 if (tmp & (1 << p_hwfn->rel_pf_id)) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002911 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2912 cdev->num_hwfns = 2;
2913 } else {
2914 cdev->num_hwfns = 1;
2915 }
2916
Rahul Verma15582962017-04-06 15:58:29 +03002917 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002918 MISCS_REG_CHIP_TEST_REG) >> 4;
2919 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
Rahul Verma15582962017-04-06 15:58:29 +03002920 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002921 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2922
2923 DP_INFO(cdev->hwfns,
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002924 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2925 QED_IS_BB(cdev) ? "BB" : "AH",
2926 'A' + cdev->chip_rev,
2927 (int)cdev->chip_metal,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002928 cdev->chip_num, cdev->chip_rev,
2929 cdev->chip_bond_id, cdev->chip_metal);
Yuval Mintz12e09c62016-03-02 20:26:01 +02002930
Yuval Mintz12e09c62016-03-02 20:26:01 +02002931 return 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002932}
2933
Sudarsana Reddy Kalluru43645ce2018-03-28 05:14:19 -07002934static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
2935{
2936 kfree(p_hwfn->nvm_info.image_att);
2937 p_hwfn->nvm_info.image_att = NULL;
2938}
2939
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002940static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2941 void __iomem *p_regview,
2942 void __iomem *p_doorbells,
2943 enum qed_pci_personality personality)
2944{
2945 int rc = 0;
2946
2947 /* Split PCI bars evenly between hwfns */
2948 p_hwfn->regview = p_regview;
2949 p_hwfn->doorbells = p_doorbells;
2950
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002951 if (IS_VF(p_hwfn->cdev))
2952 return qed_vf_hw_prepare(p_hwfn);
2953
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002954 /* Validate that chip access is feasible */
2955 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2956 DP_ERR(p_hwfn,
2957 "Reading the ME register returns all Fs; Preventing further chip access\n");
2958 return -EINVAL;
2959 }
2960
2961 get_function_id(p_hwfn);
2962
Yuval Mintz12e09c62016-03-02 20:26:01 +02002963 /* Allocate PTT pool */
2964 rc = qed_ptt_pool_alloc(p_hwfn);
Joe Perches2591c282016-09-04 14:24:03 -07002965 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002966 goto err0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002967
Yuval Mintz12e09c62016-03-02 20:26:01 +02002968 /* Allocate the main PTT */
2969 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2970
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002971 /* First hwfn learns basic information, e.g., number of hwfns */
Yuval Mintz12e09c62016-03-02 20:26:01 +02002972 if (!p_hwfn->my_id) {
Rahul Verma15582962017-04-06 15:58:29 +03002973 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
Yuval Mintz1a635e42016-08-15 10:42:43 +03002974 if (rc)
Yuval Mintz12e09c62016-03-02 20:26:01 +02002975 goto err1;
2976 }
2977
2978 qed_hw_hwfn_prepare(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002979
2980 /* Initialize MCP structure */
2981 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2982 if (rc) {
2983 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2984 goto err1;
2985 }
2986
2987 /* Read the device configuration information from the HW and SHMEM */
2988 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2989 if (rc) {
2990 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2991 goto err2;
2992 }
2993
Mintz, Yuval18a69e32017-03-28 15:12:53 +03002994 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2995 * is called as it sets the ports number in an engine.
2996 */
2997 if (IS_LEAD_HWFN(p_hwfn)) {
2998 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
2999 if (rc)
3000 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3001 }
3002
Sudarsana Reddy Kalluru43645ce2018-03-28 05:14:19 -07003003 /* NVRAM info initialization and population */
3004 if (IS_LEAD_HWFN(p_hwfn)) {
3005 rc = qed_mcp_nvm_info_populate(p_hwfn);
3006 if (rc) {
3007 DP_NOTICE(p_hwfn,
3008 "Failed to populate nvm info shadow\n");
3009 goto err2;
3010 }
3011 }
3012
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003013 /* Allocate the init RT array and initialize the init-ops engine */
3014 rc = qed_init_alloc(p_hwfn);
Joe Perches2591c282016-09-04 14:24:03 -07003015 if (rc)
Sudarsana Reddy Kalluru43645ce2018-03-28 05:14:19 -07003016 goto err3;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003017
3018 return rc;
Sudarsana Reddy Kalluru43645ce2018-03-28 05:14:19 -07003019err3:
3020 if (IS_LEAD_HWFN(p_hwfn))
3021 qed_nvm_info_free(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003022err2:
Yuval Mintz32a47e72016-05-11 16:36:12 +03003023 if (IS_LEAD_HWFN(p_hwfn))
3024 qed_iov_free_hw_info(p_hwfn->cdev);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003025 qed_mcp_free(p_hwfn);
3026err1:
3027 qed_hw_hwfn_free(p_hwfn);
3028err0:
3029 return rc;
3030}
3031
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003032int qed_hw_prepare(struct qed_dev *cdev,
3033 int personality)
3034{
Ariel Eliorc78df142015-12-07 06:25:58 -05003035 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3036 int rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003037
3038 /* Store the precompiled init data ptrs */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003039 if (IS_PF(cdev))
3040 qed_init_iro_array(cdev);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003041
3042 /* Initialize the first hwfn - will learn number of hwfns */
Ariel Eliorc78df142015-12-07 06:25:58 -05003043 rc = qed_hw_prepare_single(p_hwfn,
3044 cdev->regview,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003045 cdev->doorbells, personality);
3046 if (rc)
3047 return rc;
3048
Ariel Eliorc78df142015-12-07 06:25:58 -05003049 personality = p_hwfn->hw_info.personality;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003050
3051 /* Initialize the rest of the hwfns */
Ariel Eliorc78df142015-12-07 06:25:58 -05003052 if (cdev->num_hwfns > 1) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003053 void __iomem *p_regview, *p_doorbell;
Ariel Eliorc78df142015-12-07 06:25:58 -05003054 u8 __iomem *addr;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003055
Ariel Eliorc78df142015-12-07 06:25:58 -05003056 /* adjust bar offset for second engine */
Rahul Verma15582962017-04-06 15:58:29 +03003057 addr = cdev->regview +
3058 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3059 BAR_ID_0) / 2;
Ariel Eliorc78df142015-12-07 06:25:58 -05003060 p_regview = addr;
3061
Rahul Verma15582962017-04-06 15:58:29 +03003062 addr = cdev->doorbells +
3063 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3064 BAR_ID_1) / 2;
Ariel Eliorc78df142015-12-07 06:25:58 -05003065 p_doorbell = addr;
3066
3067 /* prepare second hw function */
3068 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003069 p_doorbell, personality);
Ariel Eliorc78df142015-12-07 06:25:58 -05003070
3071 /* in case of error, need to free the previously
3072 * initiliazed hwfn 0.
3073 */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003074 if (rc) {
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003075 if (IS_PF(cdev)) {
3076 qed_init_free(p_hwfn);
Sudarsana Reddy Kalluru43645ce2018-03-28 05:14:19 -07003077 qed_nvm_info_free(p_hwfn);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003078 qed_mcp_free(p_hwfn);
3079 qed_hw_hwfn_free(p_hwfn);
3080 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003081 }
3082 }
3083
Ariel Eliorc78df142015-12-07 06:25:58 -05003084 return rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003085}
3086
3087void qed_hw_remove(struct qed_dev *cdev)
3088{
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02003089 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003090 int i;
3091
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02003092 if (IS_PF(cdev))
3093 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3094 QED_OV_DRIVER_STATE_NOT_LOADED);
3095
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003096 for_each_hwfn(cdev, i) {
3097 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3098
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003099 if (IS_VF(cdev)) {
Yuval Mintz0b55e272016-05-11 16:36:15 +03003100 qed_vf_pf_release(p_hwfn);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003101 continue;
3102 }
3103
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003104 qed_init_free(p_hwfn);
3105 qed_hw_hwfn_free(p_hwfn);
3106 qed_mcp_free(p_hwfn);
3107 }
Yuval Mintz32a47e72016-05-11 16:36:12 +03003108
3109 qed_iov_free_hw_info(cdev);
Sudarsana Reddy Kalluru43645ce2018-03-28 05:14:19 -07003110
3111 qed_nvm_info_free(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003112}
3113
Yuval Mintza91eb522016-06-03 14:35:32 +03003114static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3115 struct qed_chain *p_chain)
3116{
3117 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3118 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3119 struct qed_chain_next *p_next;
3120 u32 size, i;
3121
3122 if (!p_virt)
3123 return;
3124
3125 size = p_chain->elem_size * p_chain->usable_per_page;
3126
3127 for (i = 0; i < p_chain->page_cnt; i++) {
3128 if (!p_virt)
3129 break;
3130
3131 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3132 p_virt_next = p_next->next_virt;
3133 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3134
3135 dma_free_coherent(&cdev->pdev->dev,
3136 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3137
3138 p_virt = p_virt_next;
3139 p_phys = p_phys_next;
3140 }
3141}
3142
3143static void qed_chain_free_single(struct qed_dev *cdev,
3144 struct qed_chain *p_chain)
3145{
3146 if (!p_chain->p_virt_addr)
3147 return;
3148
3149 dma_free_coherent(&cdev->pdev->dev,
3150 QED_CHAIN_PAGE_SIZE,
3151 p_chain->p_virt_addr, p_chain->p_phys_addr);
3152}
3153
3154static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3155{
3156 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3157 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
Mintz, Yuval6d937ac2016-11-29 16:47:01 +02003158 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
Yuval Mintza91eb522016-06-03 14:35:32 +03003159
3160 if (!pp_virt_addr_tbl)
3161 return;
3162
Mintz, Yuval6d937ac2016-11-29 16:47:01 +02003163 if (!p_pbl_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03003164 goto out;
3165
3166 for (i = 0; i < page_cnt; i++) {
3167 if (!pp_virt_addr_tbl[i])
3168 break;
3169
3170 dma_free_coherent(&cdev->pdev->dev,
3171 QED_CHAIN_PAGE_SIZE,
3172 pp_virt_addr_tbl[i],
3173 *(dma_addr_t *)p_pbl_virt);
3174
3175 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3176 }
3177
3178 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
Mintz, Yuval1a4a6972017-06-20 16:00:00 +03003179
3180 if (!p_chain->b_external_pbl)
3181 dma_free_coherent(&cdev->pdev->dev,
3182 pbl_size,
3183 p_chain->pbl_sp.p_virt_table,
3184 p_chain->pbl_sp.p_phys_table);
Yuval Mintza91eb522016-06-03 14:35:32 +03003185out:
3186 vfree(p_chain->pbl.pp_virt_addr_tbl);
Mintz, Yuval1a4a6972017-06-20 16:00:00 +03003187 p_chain->pbl.pp_virt_addr_tbl = NULL;
Yuval Mintza91eb522016-06-03 14:35:32 +03003188}
3189
3190void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3191{
3192 switch (p_chain->mode) {
3193 case QED_CHAIN_MODE_NEXT_PTR:
3194 qed_chain_free_next_ptr(cdev, p_chain);
3195 break;
3196 case QED_CHAIN_MODE_SINGLE:
3197 qed_chain_free_single(cdev, p_chain);
3198 break;
3199 case QED_CHAIN_MODE_PBL:
3200 qed_chain_free_pbl(cdev, p_chain);
3201 break;
3202 }
3203}
3204
3205static int
3206qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3207 enum qed_chain_cnt_type cnt_type,
3208 size_t elem_size, u32 page_cnt)
3209{
3210 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3211
3212 /* The actual chain size can be larger than the maximal possible value
3213 * after rounding up the requested elements number to pages, and after
3214 * taking into acount the unusuable elements (next-ptr elements).
3215 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3216 * size/capacity fields are of a u32 type.
3217 */
3218 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
Tomer Tayar3ef310a2017-03-14 15:25:59 +02003219 chain_size > ((u32)U16_MAX + 1)) ||
3220 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
Yuval Mintza91eb522016-06-03 14:35:32 +03003221 DP_NOTICE(cdev,
3222 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3223 chain_size);
3224 return -EINVAL;
3225 }
3226
3227 return 0;
3228}
3229
3230static int
3231qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3232{
3233 void *p_virt = NULL, *p_virt_prev = NULL;
3234 dma_addr_t p_phys = 0;
3235 u32 i;
3236
3237 for (i = 0; i < p_chain->page_cnt; i++) {
3238 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3239 QED_CHAIN_PAGE_SIZE,
3240 &p_phys, GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -07003241 if (!p_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03003242 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03003243
3244 if (i == 0) {
3245 qed_chain_init_mem(p_chain, p_virt, p_phys);
3246 qed_chain_reset(p_chain);
3247 } else {
3248 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3249 p_virt, p_phys);
3250 }
3251
3252 p_virt_prev = p_virt;
3253 }
3254 /* Last page's next element should point to the beginning of the
3255 * chain.
3256 */
3257 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3258 p_chain->p_virt_addr,
3259 p_chain->p_phys_addr);
3260
3261 return 0;
3262}
3263
3264static int
3265qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3266{
3267 dma_addr_t p_phys = 0;
3268 void *p_virt = NULL;
3269
3270 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3271 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -07003272 if (!p_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03003273 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03003274
3275 qed_chain_init_mem(p_chain, p_virt, p_phys);
3276 qed_chain_reset(p_chain);
3277
3278 return 0;
3279}
3280
Mintz, Yuval1a4a6972017-06-20 16:00:00 +03003281static int
3282qed_chain_alloc_pbl(struct qed_dev *cdev,
3283 struct qed_chain *p_chain,
3284 struct qed_chain_ext_pbl *ext_pbl)
Yuval Mintza91eb522016-06-03 14:35:32 +03003285{
3286 u32 page_cnt = p_chain->page_cnt, size, i;
3287 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3288 void **pp_virt_addr_tbl = NULL;
3289 u8 *p_pbl_virt = NULL;
3290 void *p_virt = NULL;
3291
3292 size = page_cnt * sizeof(*pp_virt_addr_tbl);
Joe Perches2591c282016-09-04 14:24:03 -07003293 pp_virt_addr_tbl = vzalloc(size);
3294 if (!pp_virt_addr_tbl)
Yuval Mintza91eb522016-06-03 14:35:32 +03003295 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03003296
3297 /* The allocation of the PBL table is done with its full size, since it
3298 * is expected to be successive.
3299 * qed_chain_init_pbl_mem() is called even in a case of an allocation
3300 * failure, since pp_virt_addr_tbl was previously allocated, and it
3301 * should be saved to allow its freeing during the error flow.
3302 */
3303 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
Mintz, Yuval1a4a6972017-06-20 16:00:00 +03003304
3305 if (!ext_pbl) {
3306 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3307 size, &p_pbl_phys, GFP_KERNEL);
3308 } else {
3309 p_pbl_virt = ext_pbl->p_pbl_virt;
3310 p_pbl_phys = ext_pbl->p_pbl_phys;
3311 p_chain->b_external_pbl = true;
3312 }
3313
Yuval Mintza91eb522016-06-03 14:35:32 +03003314 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3315 pp_virt_addr_tbl);
Joe Perches2591c282016-09-04 14:24:03 -07003316 if (!p_pbl_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03003317 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03003318
3319 for (i = 0; i < page_cnt; i++) {
3320 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3321 QED_CHAIN_PAGE_SIZE,
3322 &p_phys, GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -07003323 if (!p_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03003324 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03003325
3326 if (i == 0) {
3327 qed_chain_init_mem(p_chain, p_virt, p_phys);
3328 qed_chain_reset(p_chain);
3329 }
3330
3331 /* Fill the PBL table with the physical address of the page */
3332 *(dma_addr_t *)p_pbl_virt = p_phys;
3333 /* Keep the virtual address of the page */
3334 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3335
3336 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3337 }
3338
3339 return 0;
3340}
3341
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003342int qed_chain_alloc(struct qed_dev *cdev,
3343 enum qed_chain_use_mode intended_use,
3344 enum qed_chain_mode mode,
Yuval Mintza91eb522016-06-03 14:35:32 +03003345 enum qed_chain_cnt_type cnt_type,
Mintz, Yuval1a4a6972017-06-20 16:00:00 +03003346 u32 num_elems,
3347 size_t elem_size,
3348 struct qed_chain *p_chain,
3349 struct qed_chain_ext_pbl *ext_pbl)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003350{
Yuval Mintza91eb522016-06-03 14:35:32 +03003351 u32 page_cnt;
3352 int rc = 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003353
3354 if (mode == QED_CHAIN_MODE_SINGLE)
3355 page_cnt = 1;
3356 else
3357 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3358
Yuval Mintza91eb522016-06-03 14:35:32 +03003359 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3360 if (rc) {
3361 DP_NOTICE(cdev,
Joe Perches2591c282016-09-04 14:24:03 -07003362 "Cannot allocate a chain with the given arguments:\n");
3363 DP_NOTICE(cdev,
Yuval Mintza91eb522016-06-03 14:35:32 +03003364 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3365 intended_use, mode, cnt_type, num_elems, elem_size);
3366 return rc;
3367 }
3368
3369 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3370 mode, cnt_type);
3371
3372 switch (mode) {
3373 case QED_CHAIN_MODE_NEXT_PTR:
3374 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3375 break;
3376 case QED_CHAIN_MODE_SINGLE:
3377 rc = qed_chain_alloc_single(cdev, p_chain);
3378 break;
3379 case QED_CHAIN_MODE_PBL:
Mintz, Yuval1a4a6972017-06-20 16:00:00 +03003380 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
Yuval Mintza91eb522016-06-03 14:35:32 +03003381 break;
3382 }
3383 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003384 goto nomem;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003385
3386 return 0;
3387
3388nomem:
Yuval Mintza91eb522016-06-03 14:35:32 +03003389 qed_chain_free(cdev, p_chain);
3390 return rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003391}
3392
Yuval Mintza91eb522016-06-03 14:35:32 +03003393int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
Manish Chopracee4d262015-10-26 11:02:28 +02003394{
3395 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3396 u16 min, max;
3397
Yuval Mintza91eb522016-06-03 14:35:32 +03003398 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
Manish Chopracee4d262015-10-26 11:02:28 +02003399 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3400 DP_NOTICE(p_hwfn,
3401 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3402 src_id, min, max);
3403
3404 return -EINVAL;
3405 }
3406
3407 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3408
3409 return 0;
3410}
3411
Yuval Mintz1a635e42016-08-15 10:42:43 +03003412int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
Manish Chopracee4d262015-10-26 11:02:28 +02003413{
3414 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3415 u8 min, max;
3416
3417 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3418 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3419 DP_NOTICE(p_hwfn,
3420 "vport id [%d] is not valid, available indices [%d - %d]\n",
3421 src_id, min, max);
3422
3423 return -EINVAL;
3424 }
3425
3426 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3427
3428 return 0;
3429}
3430
Yuval Mintz1a635e42016-08-15 10:42:43 +03003431int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
Manish Chopracee4d262015-10-26 11:02:28 +02003432{
3433 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3434 u8 min, max;
3435
3436 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3437 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3438 DP_NOTICE(p_hwfn,
3439 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3440 src_id, min, max);
3441
3442 return -EINVAL;
3443 }
3444
3445 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3446
3447 return 0;
3448}
Manish Choprabcd197c2016-04-26 10:56:08 -04003449
Yuval Mintz0a7fb112016-10-01 21:59:55 +03003450static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3451 u8 *p_filter)
3452{
3453 *p_high = p_filter[1] | (p_filter[0] << 8);
3454 *p_low = p_filter[5] | (p_filter[4] << 8) |
3455 (p_filter[3] << 16) | (p_filter[2] << 24);
3456}
3457
3458int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3459 struct qed_ptt *p_ptt, u8 *p_filter)
3460{
3461 u32 high = 0, low = 0, en;
3462 int i;
3463
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07003464 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
Yuval Mintz0a7fb112016-10-01 21:59:55 +03003465 return 0;
3466
3467 qed_llh_mac_to_filter(&high, &low, p_filter);
3468
3469 /* Find a free entry and utilize it */
3470 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3471 en = qed_rd(p_hwfn, p_ptt,
3472 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3473 if (en)
3474 continue;
3475 qed_wr(p_hwfn, p_ptt,
3476 NIG_REG_LLH_FUNC_FILTER_VALUE +
3477 2 * i * sizeof(u32), low);
3478 qed_wr(p_hwfn, p_ptt,
3479 NIG_REG_LLH_FUNC_FILTER_VALUE +
3480 (2 * i + 1) * sizeof(u32), high);
3481 qed_wr(p_hwfn, p_ptt,
3482 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3483 qed_wr(p_hwfn, p_ptt,
3484 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3485 i * sizeof(u32), 0);
3486 qed_wr(p_hwfn, p_ptt,
3487 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3488 break;
3489 }
3490 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3491 DP_NOTICE(p_hwfn,
3492 "Failed to find an empty LLH filter to utilize\n");
3493 return -EINVAL;
3494 }
3495
3496 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3497 "mac: %pM is added at %d\n",
3498 p_filter, i);
3499
3500 return 0;
3501}
3502
3503void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3504 struct qed_ptt *p_ptt, u8 *p_filter)
3505{
3506 u32 high = 0, low = 0;
3507 int i;
3508
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07003509 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
Yuval Mintz0a7fb112016-10-01 21:59:55 +03003510 return;
3511
3512 qed_llh_mac_to_filter(&high, &low, p_filter);
3513
3514 /* Find the entry and clean it */
3515 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3516 if (qed_rd(p_hwfn, p_ptt,
3517 NIG_REG_LLH_FUNC_FILTER_VALUE +
3518 2 * i * sizeof(u32)) != low)
3519 continue;
3520 if (qed_rd(p_hwfn, p_ptt,
3521 NIG_REG_LLH_FUNC_FILTER_VALUE +
3522 (2 * i + 1) * sizeof(u32)) != high)
3523 continue;
3524
3525 qed_wr(p_hwfn, p_ptt,
3526 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3527 qed_wr(p_hwfn, p_ptt,
3528 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3529 qed_wr(p_hwfn, p_ptt,
3530 NIG_REG_LLH_FUNC_FILTER_VALUE +
3531 (2 * i + 1) * sizeof(u32), 0);
3532
3533 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3534 "mac: %pM is removed from %d\n",
3535 p_filter, i);
3536 break;
3537 }
3538 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3539 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3540}
3541
Arun Easi1e128c82017-02-15 06:28:22 -08003542int
3543qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3544 struct qed_ptt *p_ptt,
3545 u16 source_port_or_eth_type,
3546 u16 dest_port, enum qed_llh_port_filter_type_t type)
3547{
3548 u32 high = 0, low = 0, en;
3549 int i;
3550
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07003551 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
Arun Easi1e128c82017-02-15 06:28:22 -08003552 return 0;
3553
3554 switch (type) {
3555 case QED_LLH_FILTER_ETHERTYPE:
3556 high = source_port_or_eth_type;
3557 break;
3558 case QED_LLH_FILTER_TCP_SRC_PORT:
3559 case QED_LLH_FILTER_UDP_SRC_PORT:
3560 low = source_port_or_eth_type << 16;
3561 break;
3562 case QED_LLH_FILTER_TCP_DEST_PORT:
3563 case QED_LLH_FILTER_UDP_DEST_PORT:
3564 low = dest_port;
3565 break;
3566 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3567 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3568 low = (source_port_or_eth_type << 16) | dest_port;
3569 break;
3570 default:
3571 DP_NOTICE(p_hwfn,
3572 "Non valid LLH protocol filter type %d\n", type);
3573 return -EINVAL;
3574 }
3575 /* Find a free entry and utilize it */
3576 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3577 en = qed_rd(p_hwfn, p_ptt,
3578 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3579 if (en)
3580 continue;
3581 qed_wr(p_hwfn, p_ptt,
3582 NIG_REG_LLH_FUNC_FILTER_VALUE +
3583 2 * i * sizeof(u32), low);
3584 qed_wr(p_hwfn, p_ptt,
3585 NIG_REG_LLH_FUNC_FILTER_VALUE +
3586 (2 * i + 1) * sizeof(u32), high);
3587 qed_wr(p_hwfn, p_ptt,
3588 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3589 qed_wr(p_hwfn, p_ptt,
3590 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3591 i * sizeof(u32), 1 << type);
3592 qed_wr(p_hwfn, p_ptt,
3593 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3594 break;
3595 }
3596 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3597 DP_NOTICE(p_hwfn,
3598 "Failed to find an empty LLH filter to utilize\n");
3599 return -EINVAL;
3600 }
3601 switch (type) {
3602 case QED_LLH_FILTER_ETHERTYPE:
3603 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3604 "ETH type %x is added at %d\n",
3605 source_port_or_eth_type, i);
3606 break;
3607 case QED_LLH_FILTER_TCP_SRC_PORT:
3608 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3609 "TCP src port %x is added at %d\n",
3610 source_port_or_eth_type, i);
3611 break;
3612 case QED_LLH_FILTER_UDP_SRC_PORT:
3613 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3614 "UDP src port %x is added at %d\n",
3615 source_port_or_eth_type, i);
3616 break;
3617 case QED_LLH_FILTER_TCP_DEST_PORT:
3618 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3619 "TCP dst port %x is added at %d\n", dest_port, i);
3620 break;
3621 case QED_LLH_FILTER_UDP_DEST_PORT:
3622 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3623 "UDP dst port %x is added at %d\n", dest_port, i);
3624 break;
3625 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3626 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3627 "TCP src/dst ports %x/%x are added at %d\n",
3628 source_port_or_eth_type, dest_port, i);
3629 break;
3630 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3631 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3632 "UDP src/dst ports %x/%x are added at %d\n",
3633 source_port_or_eth_type, dest_port, i);
3634 break;
3635 }
3636 return 0;
3637}
3638
3639void
3640qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3641 struct qed_ptt *p_ptt,
3642 u16 source_port_or_eth_type,
3643 u16 dest_port,
3644 enum qed_llh_port_filter_type_t type)
3645{
3646 u32 high = 0, low = 0;
3647 int i;
3648
Sudarsana Reddy Kalluru0bc5fe82018-05-05 18:42:59 -07003649 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
Arun Easi1e128c82017-02-15 06:28:22 -08003650 return;
3651
3652 switch (type) {
3653 case QED_LLH_FILTER_ETHERTYPE:
3654 high = source_port_or_eth_type;
3655 break;
3656 case QED_LLH_FILTER_TCP_SRC_PORT:
3657 case QED_LLH_FILTER_UDP_SRC_PORT:
3658 low = source_port_or_eth_type << 16;
3659 break;
3660 case QED_LLH_FILTER_TCP_DEST_PORT:
3661 case QED_LLH_FILTER_UDP_DEST_PORT:
3662 low = dest_port;
3663 break;
3664 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3665 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3666 low = (source_port_or_eth_type << 16) | dest_port;
3667 break;
3668 default:
3669 DP_NOTICE(p_hwfn,
3670 "Non valid LLH protocol filter type %d\n", type);
3671 return;
3672 }
3673
3674 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3675 if (!qed_rd(p_hwfn, p_ptt,
3676 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3677 continue;
3678 if (!qed_rd(p_hwfn, p_ptt,
3679 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3680 continue;
3681 if (!(qed_rd(p_hwfn, p_ptt,
3682 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3683 i * sizeof(u32)) & BIT(type)))
3684 continue;
3685 if (qed_rd(p_hwfn, p_ptt,
3686 NIG_REG_LLH_FUNC_FILTER_VALUE +
3687 2 * i * sizeof(u32)) != low)
3688 continue;
3689 if (qed_rd(p_hwfn, p_ptt,
3690 NIG_REG_LLH_FUNC_FILTER_VALUE +
3691 (2 * i + 1) * sizeof(u32)) != high)
3692 continue;
3693
3694 qed_wr(p_hwfn, p_ptt,
3695 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3696 qed_wr(p_hwfn, p_ptt,
3697 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3698 qed_wr(p_hwfn, p_ptt,
3699 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3700 i * sizeof(u32), 0);
3701 qed_wr(p_hwfn, p_ptt,
3702 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3703 qed_wr(p_hwfn, p_ptt,
3704 NIG_REG_LLH_FUNC_FILTER_VALUE +
3705 (2 * i + 1) * sizeof(u32), 0);
3706 break;
3707 }
3708
3709 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3710 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3711}
3712
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003713static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3714 u32 hw_addr, void *p_eth_qzone,
3715 size_t eth_qzone_size, u8 timeset)
3716{
3717 struct coalescing_timeset *p_coal_timeset;
3718
3719 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3720 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3721 return -EINVAL;
3722 }
3723
3724 p_coal_timeset = p_eth_qzone;
Rahul Verma477f2d12017-07-26 06:07:13 -07003725 memset(p_eth_qzone, 0, eth_qzone_size);
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003726 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3727 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3728 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3729
3730 return 0;
3731}
3732
Rahul Verma477f2d12017-07-26 06:07:13 -07003733int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
3734{
3735 struct qed_queue_cid *p_cid = p_handle;
3736 struct qed_hwfn *p_hwfn;
3737 struct qed_ptt *p_ptt;
3738 int rc = 0;
3739
3740 p_hwfn = p_cid->p_owner;
3741
3742 if (IS_VF(p_hwfn->cdev))
3743 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
3744
3745 p_ptt = qed_ptt_acquire(p_hwfn);
3746 if (!p_ptt)
3747 return -EAGAIN;
3748
3749 if (rx_coal) {
3750 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
3751 if (rc)
3752 goto out;
3753 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
3754 }
3755
3756 if (tx_coal) {
3757 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
3758 if (rc)
3759 goto out;
3760 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
3761 }
3762out:
3763 qed_ptt_release(p_hwfn, p_ptt);
3764 return rc;
3765}
3766
3767int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
3768 struct qed_ptt *p_ptt,
3769 u16 coalesce, struct qed_queue_cid *p_cid)
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003770{
3771 struct ustorm_eth_queue_zone eth_qzone;
3772 u8 timeset, timer_res;
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003773 u32 address;
3774 int rc;
3775
3776 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3777 if (coalesce <= 0x7F) {
3778 timer_res = 0;
3779 } else if (coalesce <= 0xFF) {
3780 timer_res = 1;
3781 } else if (coalesce <= 0x1FF) {
3782 timer_res = 2;
3783 } else {
3784 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3785 return -EINVAL;
3786 }
3787 timeset = (u8)(coalesce >> timer_res);
3788
Rahul Verma477f2d12017-07-26 06:07:13 -07003789 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3790 p_cid->sb_igu_id, false);
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003791 if (rc)
3792 goto out;
3793
Rahul Verma477f2d12017-07-26 06:07:13 -07003794 address = BAR0_MAP_REG_USDM_RAM +
3795 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003796
3797 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3798 sizeof(struct ustorm_eth_queue_zone), timeset);
3799 if (rc)
3800 goto out;
3801
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003802out:
3803 return rc;
3804}
3805
Rahul Verma477f2d12017-07-26 06:07:13 -07003806int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
3807 struct qed_ptt *p_ptt,
3808 u16 coalesce, struct qed_queue_cid *p_cid)
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003809{
3810 struct xstorm_eth_queue_zone eth_qzone;
3811 u8 timeset, timer_res;
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003812 u32 address;
3813 int rc;
3814
3815 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3816 if (coalesce <= 0x7F) {
3817 timer_res = 0;
3818 } else if (coalesce <= 0xFF) {
3819 timer_res = 1;
3820 } else if (coalesce <= 0x1FF) {
3821 timer_res = 2;
3822 } else {
3823 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3824 return -EINVAL;
3825 }
3826 timeset = (u8)(coalesce >> timer_res);
3827
Rahul Verma477f2d12017-07-26 06:07:13 -07003828 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3829 p_cid->sb_igu_id, true);
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003830 if (rc)
3831 goto out;
3832
Rahul Verma477f2d12017-07-26 06:07:13 -07003833 address = BAR0_MAP_REG_XSDM_RAM +
3834 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003835
3836 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3837 sizeof(struct xstorm_eth_queue_zone), timeset);
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04003838out:
3839 return rc;
3840}
3841
Manish Choprabcd197c2016-04-26 10:56:08 -04003842/* Calculate final WFQ values for all vports and configure them.
3843 * After this configuration each vport will have
3844 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3845 */
3846static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3847 struct qed_ptt *p_ptt,
3848 u32 min_pf_rate)
3849{
3850 struct init_qm_vport_params *vport_params;
3851 int i;
3852
3853 vport_params = p_hwfn->qm_info.qm_vport_params;
3854
3855 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3856 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3857
3858 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3859 min_pf_rate;
3860 qed_init_vport_wfq(p_hwfn, p_ptt,
3861 vport_params[i].first_tx_pq_id,
3862 vport_params[i].vport_wfq);
3863 }
3864}
3865
3866static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3867 u32 min_pf_rate)
3868
3869{
3870 int i;
3871
3872 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3873 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3874}
3875
3876static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3877 struct qed_ptt *p_ptt,
3878 u32 min_pf_rate)
3879{
3880 struct init_qm_vport_params *vport_params;
3881 int i;
3882
3883 vport_params = p_hwfn->qm_info.qm_vport_params;
3884
3885 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3886 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3887 qed_init_vport_wfq(p_hwfn, p_ptt,
3888 vport_params[i].first_tx_pq_id,
3889 vport_params[i].vport_wfq);
3890 }
3891}
3892
3893/* This function performs several validations for WFQ
3894 * configuration and required min rate for a given vport
3895 * 1. req_rate must be greater than one percent of min_pf_rate.
3896 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3897 * rates to get less than one percent of min_pf_rate.
3898 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3899 */
3900static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
Yuval Mintz1a635e42016-08-15 10:42:43 +03003901 u16 vport_id, u32 req_rate, u32 min_pf_rate)
Manish Choprabcd197c2016-04-26 10:56:08 -04003902{
3903 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3904 int non_requested_count = 0, req_count = 0, i, num_vports;
3905
3906 num_vports = p_hwfn->qm_info.num_vports;
3907
3908 /* Accounting for the vports which are configured for WFQ explicitly */
3909 for (i = 0; i < num_vports; i++) {
3910 u32 tmp_speed;
3911
3912 if ((i != vport_id) &&
3913 p_hwfn->qm_info.wfq_data[i].configured) {
3914 req_count++;
3915 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3916 total_req_min_rate += tmp_speed;
3917 }
3918 }
3919
3920 /* Include current vport data as well */
3921 req_count++;
3922 total_req_min_rate += req_rate;
3923 non_requested_count = num_vports - req_count;
3924
3925 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3926 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3927 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3928 vport_id, req_rate, min_pf_rate);
3929 return -EINVAL;
3930 }
3931
3932 if (num_vports > QED_WFQ_UNIT) {
3933 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3934 "Number of vports is greater than %d\n",
3935 QED_WFQ_UNIT);
3936 return -EINVAL;
3937 }
3938
3939 if (total_req_min_rate > min_pf_rate) {
3940 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3941 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3942 total_req_min_rate, min_pf_rate);
3943 return -EINVAL;
3944 }
3945
3946 total_left_rate = min_pf_rate - total_req_min_rate;
3947
3948 left_rate_per_vp = total_left_rate / non_requested_count;
3949 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
3950 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3951 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3952 left_rate_per_vp, min_pf_rate);
3953 return -EINVAL;
3954 }
3955
3956 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3957 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3958
3959 for (i = 0; i < num_vports; i++) {
3960 if (p_hwfn->qm_info.wfq_data[i].configured)
3961 continue;
3962
3963 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3964 }
3965
3966 return 0;
3967}
3968
Yuval Mintz733def62016-05-11 16:36:22 +03003969static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3970 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3971{
3972 struct qed_mcp_link_state *p_link;
3973 int rc = 0;
3974
3975 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3976
3977 if (!p_link->min_pf_rate) {
3978 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3979 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3980 return rc;
3981 }
3982
3983 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3984
Yuval Mintz1a635e42016-08-15 10:42:43 +03003985 if (!rc)
Yuval Mintz733def62016-05-11 16:36:22 +03003986 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3987 p_link->min_pf_rate);
3988 else
3989 DP_NOTICE(p_hwfn,
3990 "Validation failed while configuring min rate\n");
3991
3992 return rc;
3993}
3994
Manish Choprabcd197c2016-04-26 10:56:08 -04003995static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3996 struct qed_ptt *p_ptt,
3997 u32 min_pf_rate)
3998{
3999 bool use_wfq = false;
4000 int rc = 0;
4001 u16 i;
4002
4003 /* Validate all pre configured vports for wfq */
4004 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4005 u32 rate;
4006
4007 if (!p_hwfn->qm_info.wfq_data[i].configured)
4008 continue;
4009
4010 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4011 use_wfq = true;
4012
4013 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4014 if (rc) {
4015 DP_NOTICE(p_hwfn,
4016 "WFQ validation failed while configuring min rate\n");
4017 break;
4018 }
4019 }
4020
4021 if (!rc && use_wfq)
4022 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4023 else
4024 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4025
4026 return rc;
4027}
4028
Yuval Mintz733def62016-05-11 16:36:22 +03004029/* Main API for qed clients to configure vport min rate.
4030 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4031 * rate - Speed in Mbps needs to be assigned to a given vport.
4032 */
4033int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4034{
4035 int i, rc = -EINVAL;
4036
4037 /* Currently not supported; Might change in future */
4038 if (cdev->num_hwfns > 1) {
4039 DP_NOTICE(cdev,
4040 "WFQ configuration is not supported for this device\n");
4041 return rc;
4042 }
4043
4044 for_each_hwfn(cdev, i) {
4045 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4046 struct qed_ptt *p_ptt;
4047
4048 p_ptt = qed_ptt_acquire(p_hwfn);
4049 if (!p_ptt)
4050 return -EBUSY;
4051
4052 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4053
Yuval Mintzd572c432016-07-27 14:45:23 +03004054 if (rc) {
Yuval Mintz733def62016-05-11 16:36:22 +03004055 qed_ptt_release(p_hwfn, p_ptt);
4056 return rc;
4057 }
4058
4059 qed_ptt_release(p_hwfn, p_ptt);
4060 }
4061
4062 return rc;
4063}
4064
Manish Choprabcd197c2016-04-26 10:56:08 -04004065/* API to configure WFQ from mcp link change */
Mintz, Yuval6f437d42017-02-27 11:06:33 +02004066void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4067 struct qed_ptt *p_ptt, u32 min_pf_rate)
Manish Choprabcd197c2016-04-26 10:56:08 -04004068{
4069 int i;
4070
Yuval Mintz3e7cfce2016-05-26 11:01:24 +03004071 if (cdev->num_hwfns > 1) {
4072 DP_VERBOSE(cdev,
4073 NETIF_MSG_LINK,
4074 "WFQ configuration is not supported for this device\n");
4075 return;
4076 }
4077
Manish Choprabcd197c2016-04-26 10:56:08 -04004078 for_each_hwfn(cdev, i) {
4079 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4080
Mintz, Yuval6f437d42017-02-27 11:06:33 +02004081 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
Manish Choprabcd197c2016-04-26 10:56:08 -04004082 min_pf_rate);
4083 }
4084}
Manish Chopra4b01e512016-04-26 10:56:09 -04004085
4086int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4087 struct qed_ptt *p_ptt,
4088 struct qed_mcp_link_state *p_link,
4089 u8 max_bw)
4090{
4091 int rc = 0;
4092
4093 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4094
4095 if (!p_link->line_speed && (max_bw != 100))
4096 return rc;
4097
4098 p_link->speed = (p_link->line_speed * max_bw) / 100;
4099 p_hwfn->qm_info.pf_rl = p_link->speed;
4100
4101 /* Since the limiter also affects Tx-switched traffic, we don't want it
4102 * to limit such traffic in case there's no actual limit.
4103 * In that case, set limit to imaginary high boundary.
4104 */
4105 if (max_bw == 100)
4106 p_hwfn->qm_info.pf_rl = 100000;
4107
4108 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4109 p_hwfn->qm_info.pf_rl);
4110
4111 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4112 "Configured MAX bandwidth to be %08x Mb/sec\n",
4113 p_link->speed);
4114
4115 return rc;
4116}
4117
4118/* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4119int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4120{
4121 int i, rc = -EINVAL;
4122
4123 if (max_bw < 1 || max_bw > 100) {
4124 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4125 return rc;
4126 }
4127
4128 for_each_hwfn(cdev, i) {
4129 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4130 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4131 struct qed_mcp_link_state *p_link;
4132 struct qed_ptt *p_ptt;
4133
4134 p_link = &p_lead->mcp_info->link_output;
4135
4136 p_ptt = qed_ptt_acquire(p_hwfn);
4137 if (!p_ptt)
4138 return -EBUSY;
4139
4140 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4141 p_link, max_bw);
4142
4143 qed_ptt_release(p_hwfn, p_ptt);
4144
4145 if (rc)
4146 break;
4147 }
4148
4149 return rc;
4150}
Manish Chopraa64b02d2016-04-26 10:56:10 -04004151
4152int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4153 struct qed_ptt *p_ptt,
4154 struct qed_mcp_link_state *p_link,
4155 u8 min_bw)
4156{
4157 int rc = 0;
4158
4159 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4160 p_hwfn->qm_info.pf_wfq = min_bw;
4161
4162 if (!p_link->line_speed)
4163 return rc;
4164
4165 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4166
4167 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4168
4169 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4170 "Configured MIN bandwidth to be %d Mb/sec\n",
4171 p_link->min_pf_rate);
4172
4173 return rc;
4174}
4175
4176/* Main API to configure PF min bandwidth where bw range is [1-100] */
4177int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4178{
4179 int i, rc = -EINVAL;
4180
4181 if (min_bw < 1 || min_bw > 100) {
4182 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4183 return rc;
4184 }
4185
4186 for_each_hwfn(cdev, i) {
4187 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4188 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4189 struct qed_mcp_link_state *p_link;
4190 struct qed_ptt *p_ptt;
4191
4192 p_link = &p_lead->mcp_info->link_output;
4193
4194 p_ptt = qed_ptt_acquire(p_hwfn);
4195 if (!p_ptt)
4196 return -EBUSY;
4197
4198 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4199 p_link, min_bw);
4200 if (rc) {
4201 qed_ptt_release(p_hwfn, p_ptt);
4202 return rc;
4203 }
4204
4205 if (p_link->min_pf_rate) {
4206 u32 min_rate = p_link->min_pf_rate;
4207
4208 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4209 p_ptt,
4210 min_rate);
4211 }
4212
4213 qed_ptt_release(p_hwfn, p_ptt);
4214 }
4215
4216 return rc;
4217}
Yuval Mintz733def62016-05-11 16:36:22 +03004218
4219void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4220{
4221 struct qed_mcp_link_state *p_link;
4222
4223 p_link = &p_hwfn->mcp_info->link_output;
4224
4225 if (p_link->min_pf_rate)
4226 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4227 p_link->min_pf_rate);
4228
4229 memset(p_hwfn->qm_info.wfq_data, 0,
4230 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4231}
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02004232
4233int qed_device_num_engines(struct qed_dev *cdev)
4234{
4235 return QED_IS_BB(cdev) ? 2 : 1;
4236}
sudarsana.kalluru@cavium.comdb82f702017-04-26 09:00:50 -07004237
4238static int qed_device_num_ports(struct qed_dev *cdev)
4239{
4240 /* in CMT always only one port */
4241 if (cdev->num_hwfns > 1)
4242 return 1;
4243
Tomer Tayar78cea9f2017-05-23 09:41:22 +03004244 return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
sudarsana.kalluru@cavium.comdb82f702017-04-26 09:00:50 -07004245}
4246
4247int qed_device_get_port_id(struct qed_dev *cdev)
4248{
4249 return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4250}
Kalderon, Michal456a5842017-07-02 10:29:27 +03004251
4252void qed_set_fw_mac_addr(__le16 *fw_msb,
4253 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4254{
4255 ((u8 *)fw_msb)[0] = mac[1];
4256 ((u8 *)fw_msb)[1] = mac[0];
4257 ((u8 *)fw_mid)[0] = mac[3];
4258 ((u8 *)fw_mid)[1] = mac[2];
4259 ((u8 *)fw_lsb)[0] = mac[5];
4260 ((u8 *)fw_lsb)[1] = mac[4];
4261}