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Jiri Slabyfa1c1142007-08-12 17:33:16 +02001/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
Jiri Slabyfa1c1142007-08-12 17:33:16 +020043#include <linux/module.h>
44#include <linux/delay.h>
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000045#include <linux/dma-mapping.h>
Jiri Slaby274c7c32008-07-15 17:44:20 +020046#include <linux/hardirq.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020047#include <linux/if.h>
Jiri Slaby274c7c32008-07-15 17:44:20 +020048#include <linux/io.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020049#include <linux/netdevice.h>
50#include <linux/cache.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020051#include <linux/ethtool.h>
52#include <linux/uaccess.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090053#include <linux/slab.h>
Ben Greearb1ae1ed2010-09-30 12:22:58 -070054#include <linux/etherdevice.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020055
56#include <net/ieee80211_radiotap.h>
57
58#include <asm/unaligned.h>
59
60#include "base.h"
61#include "reg.h"
62#include "debug.h"
Bruno Randolf2111ac02010-04-02 18:44:08 +090063#include "ani.h"
Jiri Slabyfa1c1142007-08-12 17:33:16 +020064
Bob Copeland0e472252011-01-24 23:32:55 -050065#define CREATE_TRACE_POINTS
66#include "trace.h"
67
John W. Linville18cb6e32011-01-05 09:39:59 -050068int ath5k_modparam_nohwcrypt;
69module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
Bob Copeland9ad9a262008-10-29 08:30:54 -040070MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
Jiri Slabyfa1c1142007-08-12 17:33:16 +020071
Bob Copeland42639fc2009-03-30 08:05:29 -040072static int modparam_all_channels;
Bob Copeland46802a42009-04-15 07:57:34 -040073module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
Bob Copeland42639fc2009-03-30 08:05:29 -040074MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
75
Nick Kossifidisa99168e2011-06-02 03:09:48 +030076static int modparam_fastchanswitch;
77module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
78MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
79
80
Jiri Slabyfa1c1142007-08-12 17:33:16 +020081/* Module info */
82MODULE_AUTHOR("Jiri Slaby");
83MODULE_AUTHOR("Nick Kossifidis");
84MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
85MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
86MODULE_LICENSE("Dual BSD/GPL");
Jiri Slabyfa1c1142007-08-12 17:33:16 +020087
Felix Fietkau132b1c32010-12-02 10:26:56 +010088static int ath5k_init(struct ieee80211_hw *hw);
Pavel Roskine0d687b2011-07-14 20:21:55 -040089static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
Nick Kossifidis8aec7af2010-11-23 21:39:28 +020090 bool skip_pcu);
Jiri Slabyfa1c1142007-08-12 17:33:16 +020091
Jiri Slabyfa1c1142007-08-12 17:33:16 +020092/* Known SREVs */
Jiri Slaby2c91108c2009-03-07 10:26:41 +010093static const struct ath5k_srev_name srev_names[] = {
Felix Fietkaua0b907e2010-12-02 10:27:16 +010094#ifdef CONFIG_ATHEROS_AR231X
95 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
96 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
97 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
98 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
99 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
100 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
101 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
102#else
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300103 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
104 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
105 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
106 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
107 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
108 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
109 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
110 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
111 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
112 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
113 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
114 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
115 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
116 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
117 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
118 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
119 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
120 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
Felix Fietkaua0b907e2010-12-02 10:27:16 +0100121#endif
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300122 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200123 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
124 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300125 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200126 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
127 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
128 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300129 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200130 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
131 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300132 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
133 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
134 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300135 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200136 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
Felix Fietkaua0b907e2010-12-02 10:27:16 +0100137#ifdef CONFIG_ATHEROS_AR231X
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140#endif
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200141 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
142};
143
Jiri Slaby2c91108c2009-03-07 10:26:41 +0100144static const struct ieee80211_rate ath5k_rates[] = {
Bruno Randolf63266a62008-07-30 17:12:58 +0200145 { .bitrate = 10,
146 .hw_value = ATH5K_RATE_CODE_1M, },
147 { .bitrate = 20,
148 .hw_value = ATH5K_RATE_CODE_2M,
149 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
150 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
151 { .bitrate = 55,
152 .hw_value = ATH5K_RATE_CODE_5_5M,
153 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
154 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
155 { .bitrate = 110,
156 .hw_value = ATH5K_RATE_CODE_11M,
157 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
159 { .bitrate = 60,
160 .hw_value = ATH5K_RATE_CODE_6M,
161 .flags = 0 },
162 { .bitrate = 90,
163 .hw_value = ATH5K_RATE_CODE_9M,
164 .flags = 0 },
165 { .bitrate = 120,
166 .hw_value = ATH5K_RATE_CODE_12M,
167 .flags = 0 },
168 { .bitrate = 180,
169 .hw_value = ATH5K_RATE_CODE_18M,
170 .flags = 0 },
171 { .bitrate = 240,
172 .hw_value = ATH5K_RATE_CODE_24M,
173 .flags = 0 },
174 { .bitrate = 360,
175 .hw_value = ATH5K_RATE_CODE_36M,
176 .flags = 0 },
177 { .bitrate = 480,
178 .hw_value = ATH5K_RATE_CODE_48M,
179 .flags = 0 },
180 { .bitrate = 540,
181 .hw_value = ATH5K_RATE_CODE_54M,
182 .flags = 0 },
183 /* XR missing */
184};
185
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200186static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
187{
188 u64 tsf = ath5k_hw_get_tsf64(ah);
189
190 if ((tsf & 0x7fff) < rstamp)
191 tsf -= 0x8000;
192
193 return (tsf & ~0x7fff) | rstamp;
194}
195
Felix Fietkaue5b046d2010-12-02 10:27:01 +0100196const char *
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200197ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
198{
199 const char *name = "xxxxx";
200 unsigned int i;
201
202 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
203 if (srev_names[i].sr_type != type)
204 continue;
Nick Kossifidis75d0edb2008-09-29 01:24:44 +0300205
206 if ((val & 0xf0) == srev_names[i].sr_val)
207 name = srev_names[i].sr_name;
208
209 if ((val & 0xff) == srev_names[i].sr_val) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200210 name = srev_names[i].sr_name;
211 break;
212 }
213 }
214
215 return name;
216}
Luis R. Rodrigueze5aa8472009-09-10 16:55:11 -0700217static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
218{
219 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
220 return ath5k_hw_reg_read(ah, reg_offset);
221}
222
223static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
224{
225 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
226 ath5k_hw_reg_write(ah, val, reg_offset);
227}
228
229static const struct ath_ops ath5k_common_ops = {
230 .read = ath5k_ioread32,
231 .write = ath5k_iowrite32,
232};
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200233
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200234/***********************\
235* Driver Initialization *
236\***********************/
237
Bob Copelandf769c362009-03-30 22:30:31 -0400238static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
239{
240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
Pavel Roskine0d687b2011-07-14 20:21:55 -0400241 struct ath5k_hw *ah = hw->priv;
242 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
Bob Copelandf769c362009-03-30 22:30:31 -0400243
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700244 return ath_reg_notifier_apply(wiphy, request, regulatory);
Bob Copelandf769c362009-03-30 22:30:31 -0400245}
246
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200247/********************\
248* Channel/mode setup *
249\********************/
250
251/*
Bob Copeland42639fc2009-03-30 08:05:29 -0400252 * Returns true for the channel numbers used without all_channels modparam.
253 */
Bruno Randolf410e6122011-01-19 18:20:57 +0900254static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
Bob Copeland42639fc2009-03-30 08:05:29 -0400255{
Bruno Randolf410e6122011-01-19 18:20:57 +0900256 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
257 return true;
258
259 return /* UNII 1,2 */
260 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
Bob Copeland42639fc2009-03-30 08:05:29 -0400261 /* midband */
262 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
263 /* UNII-3 */
Bruno Randolf410e6122011-01-19 18:20:57 +0900264 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
265 /* 802.11j 5.030-5.080 GHz (20MHz) */
266 (chan == 8 || chan == 12 || chan == 16) ||
267 /* 802.11j 4.9GHz (20MHz) */
268 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
Bob Copeland42639fc2009-03-30 08:05:29 -0400269}
270
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200271static unsigned int
Bruno Randolf97d9c3a2011-01-19 18:20:52 +0900272ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
273 unsigned int mode, unsigned int max)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200274{
Bruno Randolf2b1351a2011-01-21 12:19:52 +0900275 unsigned int count, size, chfreq, freq, ch;
Bruno Randolf90c02d72011-01-19 18:20:36 +0900276 enum ieee80211_band band;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200277
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200278 switch (mode) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500279 case AR5K_MODE_11A:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200280 /* 1..220, but 2GHz frequencies are filtered by check_channel */
Bruno Randolf97d9c3a2011-01-19 18:20:52 +0900281 size = 220;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200282 chfreq = CHANNEL_5GHZ;
Bruno Randolf90c02d72011-01-19 18:20:36 +0900283 band = IEEE80211_BAND_5GHZ;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200284 break;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500285 case AR5K_MODE_11B:
286 case AR5K_MODE_11G:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500287 size = 26;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200288 chfreq = CHANNEL_2GHZ;
Bruno Randolf90c02d72011-01-19 18:20:36 +0900289 band = IEEE80211_BAND_2GHZ;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200290 break;
291 default:
Pavel Roskine0d687b2011-07-14 20:21:55 -0400292 ATH5K_WARN(ah, "bad mode, not copying channels\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200293 return 0;
294 }
295
Bruno Randolf2b1351a2011-01-21 12:19:52 +0900296 count = 0;
297 for (ch = 1; ch <= size && count < max; ch++) {
Bruno Randolf90c02d72011-01-19 18:20:36 +0900298 freq = ieee80211_channel_to_frequency(ch, band);
299
300 if (freq == 0) /* mapping failed - not a standard channel */
301 continue;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500302
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200303 /* Check if channel is supported by the chipset */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500304 if (!ath5k_channel_ok(ah, freq, chfreq))
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200305 continue;
306
Bruno Randolf410e6122011-01-19 18:20:57 +0900307 if (!modparam_all_channels &&
308 !ath5k_is_standard_channel(ch, band))
Bob Copeland42639fc2009-03-30 08:05:29 -0400309 continue;
310
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500311 /* Write channel info and increment counter */
312 channels[count].center_freq = freq;
Bruno Randolf90c02d72011-01-19 18:20:36 +0900313 channels[count].band = band;
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500314 switch (mode) {
315 case AR5K_MODE_11A:
316 case AR5K_MODE_11G:
317 channels[count].hw_value = chfreq | CHANNEL_OFDM;
318 break;
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500319 case AR5K_MODE_11B:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500320 channels[count].hw_value = CHANNEL_B;
321 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200322
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200323 count++;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200324 }
325
326 return count;
327}
328
Bruno Randolf63266a62008-07-30 17:12:58 +0200329static void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400330ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
Bruno Randolf63266a62008-07-30 17:12:58 +0200331{
332 u8 i;
333
334 for (i = 0; i < AR5K_MAX_RATES; i++)
Pavel Roskine0d687b2011-07-14 20:21:55 -0400335 ah->rate_idx[b->band][i] = -1;
Bruno Randolf63266a62008-07-30 17:12:58 +0200336
337 for (i = 0; i < b->n_bitrates; i++) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400338 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
Bruno Randolf63266a62008-07-30 17:12:58 +0200339 if (b->bitrates[i].hw_value_short)
Pavel Roskine0d687b2011-07-14 20:21:55 -0400340 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
Bruno Randolf63266a62008-07-30 17:12:58 +0200341 }
342}
343
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200344static int
Bruno Randolf63266a62008-07-30 17:12:58 +0200345ath5k_setup_bands(struct ieee80211_hw *hw)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200346{
Pavel Roskine0d687b2011-07-14 20:21:55 -0400347 struct ath5k_hw *ah = hw->priv;
Bruno Randolf63266a62008-07-30 17:12:58 +0200348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
350 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200351
Pavel Roskine0d687b2011-07-14 20:21:55 -0400352 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(ah->channels);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200354
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500355 /* 2GHz band */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400356 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
Bruno Randolf63266a62008-07-30 17:12:58 +0200357 sband->band = IEEE80211_BAND_2GHZ;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400358 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200359
Pavel Roskine0d687b2011-07-14 20:21:55 -0400360 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
Bruno Randolf63266a62008-07-30 17:12:58 +0200361 /* G mode */
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200365
Pavel Roskine0d687b2011-07-14 20:21:55 -0400366 sband->channels = ah->channels;
Bruno Randolf08105692011-01-19 18:20:47 +0900367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
Bruno Randolf63266a62008-07-30 17:12:58 +0200368 AR5K_MODE_11G, max_c);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500369
370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
Bruno Randolf63266a62008-07-30 17:12:58 +0200371 count_c = sband->n_channels;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500372 max_c -= count_c;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400373 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
Bruno Randolf63266a62008-07-30 17:12:58 +0200374 /* B mode */
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500378
Bruno Randolf63266a62008-07-30 17:12:58 +0200379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
381 * fix them up here:
382 */
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
389 }
390 }
391
Pavel Roskine0d687b2011-07-14 20:21:55 -0400392 sband->channels = ah->channels;
Bruno Randolf08105692011-01-19 18:20:47 +0900393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
Bruno Randolf63266a62008-07-30 17:12:58 +0200394 AR5K_MODE_11B, max_c);
395
396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
398 max_c -= count_c;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500399 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400400 ath5k_setup_rate_idx(ah, sband);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500401
Bruno Randolf63266a62008-07-30 17:12:58 +0200402 /* 5GHz band, A mode */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400403 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
404 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500405 sband->band = IEEE80211_BAND_5GHZ;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400406 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
Bruno Randolf63266a62008-07-30 17:12:58 +0200407
408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
411
Pavel Roskine0d687b2011-07-14 20:21:55 -0400412 sband->channels = &ah->channels[count_c];
Bruno Randolf08105692011-01-19 18:20:47 +0900413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500414 AR5K_MODE_11A, max_c);
415
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
417 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400418 ath5k_setup_rate_idx(ah, sband);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500419
Pavel Roskine0d687b2011-07-14 20:21:55 -0400420 ath5k_debug_dump_bands(ah);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500421
422 return 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200423}
424
425/*
Joerg Alberte30eb4a2009-08-05 01:52:07 +0200426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
Bob Copelandbe009372009-01-22 08:44:16 -0500429 *
Pavel Roskine0d687b2011-07-14 20:21:55 -0400430 * Called with ah->lock.
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200431 */
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900432int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400433ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200434{
Pavel Roskine0d687b2011-07-14 20:21:55 -0400435 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf8d67a032010-06-16 19:11:12 +0900436 "channel set, resetting (%u -> %u MHz)\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -0400437 ah->curchan->center_freq, chan->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200438
Joerg Alberte30eb4a2009-08-05 01:52:07 +0200439 /*
440 * To switch channels clear any pending DMA operations;
441 * wait long enough for the RX fifo to drain, reset the
442 * hardware at the new frequency, and then re-enable
443 * the relevant bits of the h/w.
444 */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400445 return ath5k_reset(ah, chan, true);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200446}
447
Ben Greeare4b0b322011-03-03 14:39:05 -0800448void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700449{
Ben Greeare4b0b322011-03-03 14:39:05 -0800450 struct ath5k_vif_iter_data *iter_data = data;
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700451 int i;
Ben Greear62c58fb2010-10-08 12:01:15 -0700452 struct ath5k_vif *avf = (void *)vif->drv_priv;
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700453
454 if (iter_data->hw_macaddr)
455 for (i = 0; i < ETH_ALEN; i++)
456 iter_data->mask[i] &=
457 ~(iter_data->hw_macaddr[i] ^ mac[i]);
458
459 if (!iter_data->found_active) {
460 iter_data->found_active = true;
461 memcpy(iter_data->active_mac, mac, ETH_ALEN);
462 }
463
464 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
465 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
466 iter_data->need_set_hw_addr = false;
467
468 if (!iter_data->any_assoc) {
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700469 if (avf->assoc)
470 iter_data->any_assoc = true;
471 }
Ben Greear62c58fb2010-10-08 12:01:15 -0700472
473 /* Calculate combined mode - when APs are active, operate in AP mode.
474 * Otherwise use the mode of the new interface. This can currently
475 * only deal with combinations of APs and STAs. Only one ad-hoc
Ben Greear7afbb2f2010-11-10 11:43:51 -0800476 * interfaces is allowed.
Ben Greear62c58fb2010-10-08 12:01:15 -0700477 */
478 if (avf->opmode == NL80211_IFTYPE_AP)
479 iter_data->opmode = NL80211_IFTYPE_AP;
Ben Greeare4b0b322011-03-03 14:39:05 -0800480 else {
481 if (avf->opmode == NL80211_IFTYPE_STATION)
482 iter_data->n_stas++;
Ben Greear62c58fb2010-10-08 12:01:15 -0700483 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
484 iter_data->opmode = avf->opmode;
Ben Greeare4b0b322011-03-03 14:39:05 -0800485 }
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700486}
487
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900488void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400489ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900490 struct ieee80211_vif *vif)
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700491{
Pavel Roskine0d687b2011-07-14 20:21:55 -0400492 struct ath_common *common = ath5k_hw_common(ah);
Ben Greeare4b0b322011-03-03 14:39:05 -0800493 struct ath5k_vif_iter_data iter_data;
494 u32 rfilt;
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700495
496 /*
497 * Use the hardware MAC address as reference, the hardware uses it
498 * together with the BSSID mask when matching addresses.
499 */
500 iter_data.hw_macaddr = common->macaddr;
501 memset(&iter_data.mask, 0xff, ETH_ALEN);
502 iter_data.found_active = false;
503 iter_data.need_set_hw_addr = true;
Ben Greear62c58fb2010-10-08 12:01:15 -0700504 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
Ben Greeare4b0b322011-03-03 14:39:05 -0800505 iter_data.n_stas = 0;
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700506
507 if (vif)
Ben Greeare4b0b322011-03-03 14:39:05 -0800508 ath5k_vif_iter(&iter_data, vif->addr, vif);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700509
510 /* Get list of all active MAC addresses */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400511 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700512 &iter_data);
Pavel Roskine0d687b2011-07-14 20:21:55 -0400513 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700514
Pavel Roskine0d687b2011-07-14 20:21:55 -0400515 ah->opmode = iter_data.opmode;
516 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
Ben Greear62c58fb2010-10-08 12:01:15 -0700517 /* Nothing active, default to station mode */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400518 ah->opmode = NL80211_IFTYPE_STATION;
Ben Greear62c58fb2010-10-08 12:01:15 -0700519
Pavel Roskine0d687b2011-07-14 20:21:55 -0400520 ath5k_hw_set_opmode(ah, ah->opmode);
521 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
522 ah->opmode, ath_opmode_to_string(ah->opmode));
Ben Greear62c58fb2010-10-08 12:01:15 -0700523
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700524 if (iter_data.need_set_hw_addr && iter_data.found_active)
Pavel Roskine0d687b2011-07-14 20:21:55 -0400525 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700526
Pavel Roskine0d687b2011-07-14 20:21:55 -0400527 if (ath5k_hw_hasbssidmask(ah))
528 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700529
Ben Greeare4b0b322011-03-03 14:39:05 -0800530 /* Set up RX Filter */
531 if (iter_data.n_stas > 1) {
532 /* If you have multiple STA interfaces connected to
533 * different APs, ARPs are not received (most of the time?)
Pavel Roskin6a2a0e72011-07-09 00:17:51 -0400534 * Enabling PROMISC appears to fix that problem.
Ben Greeare4b0b322011-03-03 14:39:05 -0800535 */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400536 ah->filter_flags |= AR5K_RX_FILTER_PROM;
Ben Greeare4b0b322011-03-03 14:39:05 -0800537 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200538
Pavel Roskine0d687b2011-07-14 20:21:55 -0400539 rfilt = ah->filter_flags;
540 ath5k_hw_set_rx_filter(ah, rfilt);
541 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200542}
543
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500544static inline int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400545ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
Bruno Randolf63266a62008-07-30 17:12:58 +0200546{
Bob Copelandb7266042009-03-02 21:55:18 -0500547 int rix;
548
549 /* return base rate on errors */
550 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
551 "hw_rix out of bounds: %x\n", hw_rix))
552 return 0;
553
Pavel Roskine0d687b2011-07-14 20:21:55 -0400554 rix = ah->rate_idx[ah->curchan->band][hw_rix];
Bob Copelandb7266042009-03-02 21:55:18 -0500555 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
556 rix = 0;
557
558 return rix;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500559}
560
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200561/***************\
562* Buffers setup *
563\***************/
564
Bob Copelandb6ea0352009-01-10 14:42:54 -0500565static
Pavel Roskine0d687b2011-07-14 20:21:55 -0400566struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
Bob Copelandb6ea0352009-01-10 14:42:54 -0500567{
Pavel Roskine0d687b2011-07-14 20:21:55 -0400568 struct ath_common *common = ath5k_hw_common(ah);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500569 struct sk_buff *skb;
Bob Copelandb6ea0352009-01-10 14:42:54 -0500570
571 /*
572 * Allocate buffer with headroom_needed space for the
573 * fake physical layer header at the start.
574 */
Luis R. Rodriguezdb719712009-09-10 11:20:57 -0700575 skb = ath_rxbuf_alloc(common,
Luis R. Rodriguezdd849782009-11-04 09:44:50 -0800576 common->rx_bufsize,
Luis R. Rodriguezaeb63cf2009-08-12 09:57:00 -0700577 GFP_ATOMIC);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500578
579 if (!skb) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400580 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
Luis R. Rodriguezdd849782009-11-04 09:44:50 -0800581 common->rx_bufsize);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500582 return NULL;
583 }
Bob Copelandb6ea0352009-01-10 14:42:54 -0500584
Pavel Roskine0d687b2011-07-14 20:21:55 -0400585 *skb_addr = dma_map_single(ah->dev,
Luis R. Rodriguezcc861f72009-11-04 09:11:34 -0800586 skb->data, common->rx_bufsize,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +0100587 DMA_FROM_DEVICE);
588
Pavel Roskine0d687b2011-07-14 20:21:55 -0400589 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
590 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500591 dev_kfree_skb(skb);
592 return NULL;
593 }
594 return skb;
595}
596
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200597static int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400598ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200599{
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200600 struct sk_buff *skb = bf->skb;
601 struct ath5k_desc *ds;
Bruno Randolfb5eae9f2010-05-19 10:18:16 +0900602 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200603
Bob Copelandb6ea0352009-01-10 14:42:54 -0500604 if (!skb) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400605 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500606 if (!skb)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200607 return -ENOMEM;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200608 bf->skb = skb;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200609 }
610
611 /*
612 * Setup descriptors. For receive we always terminate
613 * the descriptor list with a self-linked entry so we'll
614 * not get overrun under high load (as can happen with a
615 * 5212 when ANI processing enables PHY error frames).
616 *
Bruno Randolfbeade632010-06-16 19:11:25 +0900617 * To ensure the last descriptor is self-linked we create
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200618 * each descriptor as self-linked and add it to the end. As
619 * each additional descriptor is added the previous self-linked
Bruno Randolfbeade632010-06-16 19:11:25 +0900620 * entry is "fixed" naturally. This should be safe even
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200621 * if DMA is happening. When processing RX interrupts we
622 * never remove/process the last, self-linked, entry on the
Bruno Randolfbeade632010-06-16 19:11:25 +0900623 * descriptor list. This ensures the hardware always has
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200624 * someplace to write a new frame.
625 */
626 ds = bf->desc;
627 ds->ds_link = bf->daddr; /* link to self */
628 ds->ds_data = bf->skbaddr;
Bruno Randolfa6668192010-06-16 19:12:01 +0900629 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
Bruno Randolf0452d4a2010-06-16 19:11:35 +0900630 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400631 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
Bruno Randolfb5eae9f2010-05-19 10:18:16 +0900632 return ret;
Bruno Randolf0452d4a2010-06-16 19:11:35 +0900633 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200634
Pavel Roskine0d687b2011-07-14 20:21:55 -0400635 if (ah->rxlink != NULL)
636 *ah->rxlink = bf->daddr;
637 ah->rxlink = &ds->ds_link;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200638 return 0;
639}
640
Bob Copeland2ac29272010-02-09 13:06:54 -0500641static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
642{
643 struct ieee80211_hdr *hdr;
644 enum ath5k_pkt_type htype;
645 __le16 fc;
646
647 hdr = (struct ieee80211_hdr *)skb->data;
648 fc = hdr->frame_control;
649
650 if (ieee80211_is_beacon(fc))
651 htype = AR5K_PKT_TYPE_BEACON;
652 else if (ieee80211_is_probe_resp(fc))
653 htype = AR5K_PKT_TYPE_PROBE_RESP;
654 else if (ieee80211_is_atim(fc))
655 htype = AR5K_PKT_TYPE_ATIM;
656 else if (ieee80211_is_pspoll(fc))
657 htype = AR5K_PKT_TYPE_PSPOLL;
658 else
659 htype = AR5K_PKT_TYPE_NORMAL;
660
661 return htype;
662}
663
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200664static int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400665ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
Benoit Papillault8127fbd2010-02-27 23:05:26 +0100666 struct ath5k_txq *txq, int padsize)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200667{
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200668 struct ath5k_desc *ds = bf->desc;
669 struct sk_buff *skb = bf->skb;
Johannes Berga888d522008-05-26 16:43:39 +0200670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200671 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
Felix Fietkau2f7fe872008-10-05 18:05:48 +0200672 struct ieee80211_rate *rate;
673 unsigned int mrr_rate[3], mrr_tries[3];
674 int i, ret;
Bob Copeland8902ff42009-01-22 08:44:20 -0500675 u16 hw_rate;
Bob Copeland07c1e852009-01-22 08:44:21 -0500676 u16 cts_rate = 0;
677 u16 duration = 0;
Bob Copeland8902ff42009-01-22 08:44:20 -0500678 u8 rc_flags;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200679
680 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
Johannes Berge039fa42008-05-15 12:55:29 +0200681
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200682 /* XXX endianness */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400683 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +0100684 DMA_TO_DEVICE);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200685
Pavel Roskine0d687b2011-07-14 20:21:55 -0400686 rate = ieee80211_get_tx_rate(ah->hw, info);
John W. Linvilled8e1ba72010-08-24 15:27:34 -0400687 if (!rate) {
688 ret = -EINVAL;
689 goto err_unmap;
690 }
Bob Copeland8902ff42009-01-22 08:44:20 -0500691
Johannes Berge039fa42008-05-15 12:55:29 +0200692 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200693 flags |= AR5K_TXDESC_NOACK;
694
Bob Copeland8902ff42009-01-22 08:44:20 -0500695 rc_flags = info->control.rates[0].flags;
696 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
697 rate->hw_value_short : rate->hw_value;
698
Bruno Randolf281c56d2008-02-05 18:44:55 +0900699 pktlen = skb->len;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200700
Nick Kossifidis8f655dd2009-03-15 22:20:35 +0200701 /* FIXME: If we are in g mode and rate is a CCK rate
702 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
703 * from tx power (value is in dB units already) */
Bob Copeland362695e2009-02-15 12:06:12 -0500704 if (info->control.hw_key) {
705 keyidx = info->control.hw_key->hw_key_idx;
706 pktlen += info->control.hw_key->icv_len;
707 }
Bob Copeland07c1e852009-01-22 08:44:21 -0500708 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
709 flags |= AR5K_TXDESC_RTSENA;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400710 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
711 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700712 info->control.vif, pktlen, info));
Bob Copeland07c1e852009-01-22 08:44:21 -0500713 }
714 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
715 flags |= AR5K_TXDESC_CTSENA;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400716 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
717 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700718 info->control.vif, pktlen, info));
Bob Copeland07c1e852009-01-22 08:44:21 -0500719 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200720 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
Benoit Papillault8127fbd2010-02-27 23:05:26 +0100721 ieee80211_get_hdrlen_from_skb(skb), padsize,
Bob Copeland2ac29272010-02-09 13:06:54 -0500722 get_hw_packet_type(skb),
Pavel Roskine0d687b2011-07-14 20:21:55 -0400723 (ah->power_level * 2),
Bob Copeland8902ff42009-01-22 08:44:20 -0500724 hw_rate,
Nick Kossifidis2bed03e2009-04-30 15:55:49 -0400725 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
Bob Copeland07c1e852009-01-22 08:44:21 -0500726 cts_rate, duration);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200727 if (ret)
728 goto err_unmap;
729
Felix Fietkau2f7fe872008-10-05 18:05:48 +0200730 memset(mrr_rate, 0, sizeof(mrr_rate));
731 memset(mrr_tries, 0, sizeof(mrr_tries));
732 for (i = 0; i < 3; i++) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400733 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
Felix Fietkau2f7fe872008-10-05 18:05:48 +0200734 if (!rate)
735 break;
736
737 mrr_rate[i] = rate->hw_value;
Johannes Berge6a98542008-10-21 12:40:02 +0200738 mrr_tries[i] = info->control.rates[i + 1].count;
Felix Fietkau2f7fe872008-10-05 18:05:48 +0200739 }
740
Bruno Randolfa6668192010-06-16 19:12:01 +0900741 ath5k_hw_setup_mrr_tx_desc(ah, ds,
Felix Fietkau2f7fe872008-10-05 18:05:48 +0200742 mrr_rate[0], mrr_tries[0],
743 mrr_rate[1], mrr_tries[1],
744 mrr_rate[2], mrr_tries[2]);
745
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200746 ds->ds_link = 0;
747 ds->ds_data = bf->skbaddr;
748
749 spin_lock_bh(&txq->lock);
750 list_add_tail(&bf->list, &txq->q);
Bruno Randolf925e0b02010-09-17 11:36:35 +0900751 txq->txq_len++;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200752 if (txq->link == NULL) /* is this first packet? */
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300753 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200754 else /* no, so only link it */
755 *txq->link = bf->daddr;
756
757 txq->link = &ds->ds_link;
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300758 ath5k_hw_start_tx_dma(ah, txq->qnum);
Jiri Slaby274c7c32008-07-15 17:44:20 +0200759 mmiowb();
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200760 spin_unlock_bh(&txq->lock);
761
762 return 0;
763err_unmap:
Pavel Roskine0d687b2011-07-14 20:21:55 -0400764 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200765 return ret;
766}
767
768/*******************\
769* Descriptors setup *
770\*******************/
771
772static int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400773ath5k_desc_alloc(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200774{
775 struct ath5k_desc *ds;
776 struct ath5k_buf *bf;
777 dma_addr_t da;
778 unsigned int i;
779 int ret;
780
781 /* allocate descriptors */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400782 ah->desc_len = sizeof(struct ath5k_desc) *
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200783 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
Felix Fietkauaeae4ac2010-12-02 10:26:51 +0100784
Pavel Roskine0d687b2011-07-14 20:21:55 -0400785 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
786 &ah->desc_daddr, GFP_KERNEL);
787 if (ah->desc == NULL) {
788 ATH5K_ERR(ah, "can't allocate descriptors\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200789 ret = -ENOMEM;
790 goto err;
791 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400792 ds = ah->desc;
793 da = ah->desc_daddr;
794 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
795 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200796
797 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
798 sizeof(struct ath5k_buf), GFP_KERNEL);
799 if (bf == NULL) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400800 ATH5K_ERR(ah, "can't allocate bufptr\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200801 ret = -ENOMEM;
802 goto err_free;
803 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400804 ah->bufptr = bf;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200805
Pavel Roskine0d687b2011-07-14 20:21:55 -0400806 INIT_LIST_HEAD(&ah->rxbuf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200807 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
808 bf->desc = ds;
809 bf->daddr = da;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400810 list_add_tail(&bf->list, &ah->rxbuf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200811 }
812
Pavel Roskine0d687b2011-07-14 20:21:55 -0400813 INIT_LIST_HEAD(&ah->txbuf);
814 ah->txbuf_len = ATH_TXBUF;
Pavel Roskine4bbf2f2011-07-07 18:14:13 -0400815 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200816 bf->desc = ds;
817 bf->daddr = da;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400818 list_add_tail(&bf->list, &ah->txbuf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200819 }
820
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700821 /* beacon buffers */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400822 INIT_LIST_HEAD(&ah->bcbuf);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700823 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
824 bf->desc = ds;
825 bf->daddr = da;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400826 list_add_tail(&bf->list, &ah->bcbuf);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700827 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200828
829 return 0;
830err_free:
Pavel Roskine0d687b2011-07-14 20:21:55 -0400831 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200832err:
Pavel Roskine0d687b2011-07-14 20:21:55 -0400833 ah->desc = NULL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200834 return ret;
835}
836
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900837void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400838ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900839{
840 BUG_ON(!bf);
841 if (!bf->skb)
842 return;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400843 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900844 DMA_TO_DEVICE);
845 dev_kfree_skb_any(bf->skb);
846 bf->skb = NULL;
847 bf->skbaddr = 0;
848 bf->desc->ds_data = 0;
849}
850
851void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400852ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900853{
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900854 struct ath_common *common = ath5k_hw_common(ah);
855
856 BUG_ON(!bf);
857 if (!bf->skb)
858 return;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400859 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900860 DMA_FROM_DEVICE);
861 dev_kfree_skb_any(bf->skb);
862 bf->skb = NULL;
863 bf->skbaddr = 0;
864 bf->desc->ds_data = 0;
865}
866
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200867static void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400868ath5k_desc_free(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200869{
870 struct ath5k_buf *bf;
871
Pavel Roskine0d687b2011-07-14 20:21:55 -0400872 list_for_each_entry(bf, &ah->txbuf, list)
873 ath5k_txbuf_free_skb(ah, bf);
874 list_for_each_entry(bf, &ah->rxbuf, list)
875 ath5k_rxbuf_free_skb(ah, bf);
876 list_for_each_entry(bf, &ah->bcbuf, list)
877 ath5k_txbuf_free_skb(ah, bf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200878
879 /* Free memory associated with all descriptors */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400880 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
881 ah->desc = NULL;
882 ah->desc_daddr = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200883
Pavel Roskine0d687b2011-07-14 20:21:55 -0400884 kfree(ah->bufptr);
885 ah->bufptr = NULL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200886}
887
888
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200889/**************\
890* Queues setup *
891\**************/
892
893static struct ath5k_txq *
Pavel Roskine0d687b2011-07-14 20:21:55 -0400894ath5k_txq_setup(struct ath5k_hw *ah,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200895 int qtype, int subtype)
896{
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200897 struct ath5k_txq *txq;
898 struct ath5k_txq_info qi = {
899 .tqi_subtype = subtype,
Bruno Randolfde8af452010-09-17 11:37:12 +0900900 /* XXX: default values not correct for B and XR channels,
901 * but who cares? */
902 .tqi_aifs = AR5K_TUNE_AIFS,
903 .tqi_cw_min = AR5K_TUNE_CWMIN,
904 .tqi_cw_max = AR5K_TUNE_CWMAX
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200905 };
906 int qnum;
907
908 /*
909 * Enable interrupts only for EOL and DESC conditions.
910 * We mark tx descriptors to receive a DESC interrupt
Bob Copelanda180a132010-08-15 13:03:12 -0400911 * when a tx queue gets deep; otherwise we wait for the
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200912 * EOL to reap descriptors. Note that this is done to
913 * reduce interrupt load and this only defers reaping
914 * descriptors, never transmitting frames. Aside from
915 * reducing interrupts this also permits more concurrency.
916 * The only potential downside is if the tx queue backs
917 * up in which case the top half of the kernel may backup
918 * due to a lack of tx descriptors.
919 */
920 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
921 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
922 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
923 if (qnum < 0) {
924 /*
925 * NB: don't print a message, this happens
926 * normally on parts with too few tx queues
927 */
928 return ERR_PTR(qnum);
929 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400930 if (qnum >= ARRAY_SIZE(ah->txqs)) {
931 ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
932 qnum, ARRAY_SIZE(ah->txqs));
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200933 ath5k_hw_release_tx_queue(ah, qnum);
934 return ERR_PTR(-EINVAL);
935 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400936 txq = &ah->txqs[qnum];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200937 if (!txq->setup) {
938 txq->qnum = qnum;
939 txq->link = NULL;
940 INIT_LIST_HEAD(&txq->q);
941 spin_lock_init(&txq->lock);
942 txq->setup = true;
Bruno Randolf925e0b02010-09-17 11:36:35 +0900943 txq->txq_len = 0;
John W. Linville81266ba2011-03-07 16:32:59 -0500944 txq->txq_max = ATH5K_TXQ_LEN_MAX;
Bruno Randolf4edd7612010-09-17 11:36:56 +0900945 txq->txq_poll_mark = false;
Bruno Randolf923e5b32010-09-17 11:37:02 +0900946 txq->txq_stuck = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200947 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400948 return &ah->txqs[qnum];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200949}
950
951static int
952ath5k_beaconq_setup(struct ath5k_hw *ah)
953{
954 struct ath5k_txq_info qi = {
Bruno Randolfde8af452010-09-17 11:37:12 +0900955 /* XXX: default values not correct for B and XR channels,
956 * but who cares? */
957 .tqi_aifs = AR5K_TUNE_AIFS,
958 .tqi_cw_min = AR5K_TUNE_CWMIN,
959 .tqi_cw_max = AR5K_TUNE_CWMAX,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200960 /* NB: for dynamic turbo, don't enable any other interrupts */
961 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
962 };
963
964 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
965}
966
967static int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400968ath5k_beaconq_config(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200969{
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200970 struct ath5k_txq_info qi;
971 int ret;
972
Pavel Roskine0d687b2011-07-14 20:21:55 -0400973 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200974 if (ret)
Bob Copelanda951ae22010-01-20 23:51:04 -0500975 goto err;
976
Pavel Roskine0d687b2011-07-14 20:21:55 -0400977 if (ah->opmode == NL80211_IFTYPE_AP ||
978 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200979 /*
980 * Always burst out beacon and CAB traffic
981 * (aifs = cwmin = cwmax = 0)
982 */
983 qi.tqi_aifs = 0;
984 qi.tqi_cw_min = 0;
985 qi.tqi_cw_max = 0;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400986 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
Bruno Randolf6d91e1d2008-01-19 18:18:41 +0900987 /*
988 * Adhoc mode; backoff between 0 and (2 * cw_min).
989 */
990 qi.tqi_aifs = 0;
991 qi.tqi_cw_min = 0;
Bruno Randolfde8af452010-09-17 11:37:12 +0900992 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200993 }
994
Pavel Roskine0d687b2011-07-14 20:21:55 -0400995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf6d91e1d2008-01-19 18:18:41 +0900996 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
997 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
998
Pavel Roskine0d687b2011-07-14 20:21:55 -0400999 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001000 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001001 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001002 "hardware queue!\n", __func__);
Bob Copelanda951ae22010-01-20 23:51:04 -05001003 goto err;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001004 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04001005 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
Bob Copelanda951ae22010-01-20 23:51:04 -05001006 if (ret)
1007 goto err;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001008
Bob Copelanda951ae22010-01-20 23:51:04 -05001009 /* reconfigure cabq with ready time to 80% of beacon_interval */
1010 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1011 if (ret)
1012 goto err;
1013
Pavel Roskine0d687b2011-07-14 20:21:55 -04001014 qi.tqi_ready_time = (ah->bintval * 80) / 100;
Bob Copelanda951ae22010-01-20 23:51:04 -05001015 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1016 if (ret)
1017 goto err;
1018
1019 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1020err:
1021 return ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001022}
1023
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001024/**
1025 * ath5k_drain_tx_buffs - Empty tx buffers
1026 *
Pavel Roskine0d687b2011-07-14 20:21:55 -04001027 * @ah The &struct ath5k_hw
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001028 *
1029 * Empty tx buffers from all queues in preparation
1030 * of a reset or during shutdown.
1031 *
1032 * NB: this assumes output has been stopped and
1033 * we do not need to block ath5k_tx_tasklet
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001034 */
1035static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001036ath5k_drain_tx_buffs(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001037{
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001038 struct ath5k_txq *txq;
1039 struct ath5k_buf *bf, *bf0;
1040 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001041
Pavel Roskine0d687b2011-07-14 20:21:55 -04001042 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1043 if (ah->txqs[i].setup) {
1044 txq = &ah->txqs[i];
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001045 spin_lock_bh(&txq->lock);
1046 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001047 ath5k_debug_printtxbuf(ah, bf);
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001048
Pavel Roskine0d687b2011-07-14 20:21:55 -04001049 ath5k_txbuf_free_skb(ah, bf);
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001050
Pavel Roskine0d687b2011-07-14 20:21:55 -04001051 spin_lock_bh(&ah->txbuflock);
1052 list_move_tail(&bf->list, &ah->txbuf);
1053 ah->txbuf_len++;
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001054 txq->txq_len--;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001055 spin_unlock_bh(&ah->txbuflock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001056 }
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001057 txq->link = NULL;
1058 txq->txq_poll_mark = false;
1059 spin_unlock_bh(&txq->lock);
1060 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001061 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001062}
1063
1064static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001065ath5k_txq_release(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001066{
Pavel Roskine0d687b2011-07-14 20:21:55 -04001067 struct ath5k_txq *txq = ah->txqs;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001068 unsigned int i;
1069
Pavel Roskine0d687b2011-07-14 20:21:55 -04001070 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001071 if (txq->setup) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001072 ath5k_hw_release_tx_queue(ah, txq->qnum);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001073 txq->setup = false;
1074 }
1075}
1076
1077
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001078/*************\
1079* RX Handling *
1080\*************/
1081
1082/*
1083 * Enable the receive h/w following a reset.
1084 */
1085static int
Pavel Roskine0d687b2011-07-14 20:21:55 -04001086ath5k_rx_start(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001087{
Luis R. Rodriguezdb719712009-09-10 11:20:57 -07001088 struct ath_common *common = ath5k_hw_common(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001089 struct ath5k_buf *bf;
1090 int ret;
1091
Nick Kossifidisb6127982010-08-15 13:03:11 -04001092 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001093
Pavel Roskine0d687b2011-07-14 20:21:55 -04001094 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
Luis R. Rodriguezcc861f72009-11-04 09:11:34 -08001095 common->cachelsz, common->rx_bufsize);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001096
Pavel Roskine0d687b2011-07-14 20:21:55 -04001097 spin_lock_bh(&ah->rxbuflock);
1098 ah->rxlink = NULL;
1099 list_for_each_entry(bf, &ah->rxbuf, list) {
1100 ret = ath5k_rxbuf_setup(ah, bf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001101 if (ret != 0) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001102 spin_unlock_bh(&ah->rxbuflock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001103 goto err;
1104 }
1105 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04001106 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
Bob Copeland26925042009-04-15 07:57:36 -04001107 ath5k_hw_set_rxdp(ah, bf->daddr);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001108 spin_unlock_bh(&ah->rxbuflock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001109
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001110 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001111 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001112 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1113
1114 return 0;
1115err:
1116 return ret;
1117}
1118
1119/*
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001120 * Disable the receive logic on PCU (DRU)
1121 * In preparation for a shutdown.
1122 *
1123 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1124 * does.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001125 */
1126static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001127ath5k_rx_stop(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001128{
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001129
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001130 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001131 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001132
Pavel Roskine0d687b2011-07-14 20:21:55 -04001133 ath5k_debug_printrxbuffs(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001134}
1135
1136static unsigned int
Pavel Roskine0d687b2011-07-14 20:21:55 -04001137ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
Bruno Randolf8a89f062010-06-16 19:11:51 +09001138 struct ath5k_rx_status *rs)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001139{
Luis R. Rodriguezdc1e0012009-11-04 17:47:31 -08001140 struct ath_common *common = ath5k_hw_common(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001141 struct ieee80211_hdr *hdr = (void *)skb->data;
Harvey Harrison798ee982008-07-15 18:44:02 -07001142 unsigned int keyix, hlen;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001143
Bruno Randolfb47f4072008-03-05 18:35:45 +09001144 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1145 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001146 return RX_FLAG_DECRYPTED;
1147
1148 /* Apparently when a default key is used to decrypt the packet
1149 the hw does not set the index used to decrypt. In such cases
1150 get the index from the packet. */
Harvey Harrison798ee982008-07-15 18:44:02 -07001151 hlen = ieee80211_hdrlen(hdr->frame_control);
Harvey Harrison24b56e72008-06-14 23:33:38 -07001152 if (ieee80211_has_protected(hdr->frame_control) &&
1153 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1154 skb->len >= hlen + 4) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001155 keyix = skb->data[hlen + 3] >> 6;
1156
Luis R. Rodriguezdc1e0012009-11-04 17:47:31 -08001157 if (test_bit(keyix, common->keymap))
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001158 return RX_FLAG_DECRYPTED;
1159 }
1160
1161 return 0;
1162}
1163
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001164
1165static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001166ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001167 struct ieee80211_rx_status *rxs)
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001168{
Pavel Roskine0d687b2011-07-14 20:21:55 -04001169 struct ath_common *common = ath5k_hw_common(ah);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001170 u64 tsf, bc_tstamp;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001171 u32 hw_tu;
1172 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1173
Harvey Harrison24b56e72008-06-14 23:33:38 -07001174 if (ieee80211_is_beacon(mgmt->frame_control) &&
Pavel Roskin38c07b42008-02-26 17:59:14 -05001175 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
Luis R. Rodriguez954fece2009-09-10 10:51:33 -07001176 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001177 /*
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001178 * Received an IBSS beacon with the same BSSID. Hardware *must*
1179 * have updated the local TSF. We have to work around various
1180 * hardware bugs, though...
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001181 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001182 tsf = ath5k_hw_get_tsf64(ah);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001183 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1184 hw_tu = TSF_TO_TU(tsf);
1185
Pavel Roskine0d687b2011-07-14 20:21:55 -04001186 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001187 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
John W. Linville06501d22008-04-01 17:38:47 -04001188 (unsigned long long)bc_tstamp,
1189 (unsigned long long)rxs->mactime,
1190 (unsigned long long)(rxs->mactime - bc_tstamp),
1191 (unsigned long long)tsf);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001192
1193 /*
1194 * Sometimes the HW will give us a wrong tstamp in the rx
1195 * status, causing the timestamp extension to go wrong.
1196 * (This seems to happen especially with beacon frames bigger
1197 * than 78 byte (incl. FCS))
1198 * But we know that the receive timestamp must be later than the
1199 * timestamp of the beacon since HW must have synced to that.
1200 *
1201 * NOTE: here we assume mactime to be after the frame was
1202 * received, not like mac80211 which defines it at the start.
1203 */
1204 if (bc_tstamp > rxs->mactime) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001205 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001206 "fixing mactime from %llx to %llx\n",
John W. Linville06501d22008-04-01 17:38:47 -04001207 (unsigned long long)rxs->mactime,
1208 (unsigned long long)tsf);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001209 rxs->mactime = tsf;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001210 }
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001211
1212 /*
1213 * Local TSF might have moved higher than our beacon timers,
1214 * in that case we have to update them to continue sending
1215 * beacons. This also takes care of synchronizing beacon sending
1216 * times with other stations.
1217 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001218 if (hw_tu >= ah->nexttbtt)
1219 ath5k_beacon_update_timers(ah, bc_tstamp);
Bruno Randolf7f896122010-09-27 12:22:21 +09001220
1221 /* Check if the beacon timers are still correct, because a TSF
1222 * update might have created a window between them - for a
1223 * longer description see the comment of this function: */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001224 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1225 ath5k_beacon_update_timers(ah, bc_tstamp);
1226 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf7f896122010-09-27 12:22:21 +09001227 "fixed beacon timers after beacon receive\n");
1228 }
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001229 }
1230}
1231
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001232static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001233ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001234{
1235 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001236 struct ath_common *common = ath5k_hw_common(ah);
1237
1238 /* only beacons from our BSSID */
1239 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1240 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1241 return;
1242
Bruno Randolfeef39be2010-11-16 10:58:43 +09001243 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001244
1245 /* in IBSS mode we should keep RSSI statistics per neighbour */
1246 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1247}
1248
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001249/*
Bob Copelanda180a132010-08-15 13:03:12 -04001250 * Compute padding position. skb must contain an IEEE 802.11 frame
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001251 */
1252static int ath5k_common_padpos(struct sk_buff *skb)
1253{
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001254 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001255 __le16 frame_control = hdr->frame_control;
1256 int padpos = 24;
1257
Pavel Roskind2c7f772011-07-07 18:14:07 -04001258 if (ieee80211_has_a4(frame_control))
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001259 padpos += ETH_ALEN;
Pavel Roskind2c7f772011-07-07 18:14:07 -04001260
1261 if (ieee80211_is_data_qos(frame_control))
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001262 padpos += IEEE80211_QOS_CTL_LEN;
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001263
1264 return padpos;
1265}
1266
1267/*
Bob Copelanda180a132010-08-15 13:03:12 -04001268 * This function expects an 802.11 frame and returns the number of
1269 * bytes added, or -1 if we don't have enough header room.
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001270 */
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001271static int ath5k_add_padding(struct sk_buff *skb)
1272{
1273 int padpos = ath5k_common_padpos(skb);
1274 int padsize = padpos & 3;
1275
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001276 if (padsize && skb->len > padpos) {
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001277
1278 if (skb_headroom(skb) < padsize)
1279 return -1;
1280
1281 skb_push(skb, padsize);
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001282 memmove(skb->data, skb->data + padsize, padpos);
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001283 return padsize;
1284 }
1285
1286 return 0;
1287}
1288
1289/*
Bob Copelanda180a132010-08-15 13:03:12 -04001290 * The MAC header is padded to have 32-bit boundary if the
1291 * packet payload is non-zero. The general calculation for
1292 * padsize would take into account odd header lengths:
1293 * padsize = 4 - (hdrlen & 3); however, since only
1294 * even-length headers are used, padding can only be 0 or 2
1295 * bytes and we can optimize this a bit. We must not try to
1296 * remove padding from short control frames that do not have a
1297 * payload.
1298 *
1299 * This function expects an 802.11 frame and returns the number of
1300 * bytes removed.
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001301 */
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001302static int ath5k_remove_padding(struct sk_buff *skb)
1303{
1304 int padpos = ath5k_common_padpos(skb);
1305 int padsize = padpos & 3;
1306
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001307 if (padsize && skb->len >= padpos + padsize) {
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001308 memmove(skb->data + padsize, skb->data, padpos);
1309 skb_pull(skb, padsize);
1310 return padsize;
1311 }
1312
1313 return 0;
1314}
1315
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001316static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001317ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
Bruno Randolf8a89f062010-06-16 19:11:51 +09001318 struct ath5k_rx_status *rs)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001319{
Bob Copeland1c5256b2009-08-24 23:00:32 -04001320 struct ieee80211_rx_status *rxs;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001321
Bruno Randolf8a89f062010-06-16 19:11:51 +09001322 ath5k_remove_padding(skb);
1323
1324 rxs = IEEE80211_SKB_RXCB(skb);
1325
1326 rxs->flag = 0;
1327 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1328 rxs->flag |= RX_FLAG_MMIC_ERROR;
1329
1330 /*
1331 * always extend the mac timestamp, since this information is
1332 * also needed for proper IBSS merging.
1333 *
1334 * XXX: it might be too late to do it here, since rs_tstamp is
1335 * 15bit only. that means TSF extension has to be done within
1336 * 32768usec (about 32ms). it might be necessary to move this to
1337 * the interrupt handler, like it is done in madwifi.
1338 *
1339 * Unfortunately we don't know when the hardware takes the rx
1340 * timestamp (beginning of phy frame, data frame, end of rx?).
1341 * The only thing we know is that it is hardware specific...
1342 * On AR5213 it seems the rx timestamp is at the end of the
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04001343 * frame, but I'm not sure.
Bruno Randolf8a89f062010-06-16 19:11:51 +09001344 *
1345 * NOTE: mac80211 defines mactime at the beginning of the first
1346 * data symbol. Since we don't have any time references it's
1347 * impossible to comply to that. This affects IBSS merge only
1348 * right now, so it's not too bad...
1349 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001350 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
Johannes Berg6ebacbb2011-02-23 15:06:08 +01001351 rxs->flag |= RX_FLAG_MACTIME_MPDU;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001352
Pavel Roskine0d687b2011-07-14 20:21:55 -04001353 rxs->freq = ah->curchan->center_freq;
1354 rxs->band = ah->curchan->band;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001355
Pavel Roskine0d687b2011-07-14 20:21:55 -04001356 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001357
1358 rxs->antenna = rs->rs_antenna;
1359
1360 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001361 ah->stats.antenna_rx[rs->rs_antenna]++;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001362 else
Pavel Roskine0d687b2011-07-14 20:21:55 -04001363 ah->stats.antenna_rx[0]++; /* invalid */
Bruno Randolf8a89f062010-06-16 19:11:51 +09001364
Pavel Roskine0d687b2011-07-14 20:21:55 -04001365 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1366 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001367
1368 if (rxs->rate_idx >= 0 && rs->rs_rate ==
Pavel Roskine0d687b2011-07-14 20:21:55 -04001369 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
Bruno Randolf8a89f062010-06-16 19:11:51 +09001370 rxs->flag |= RX_FLAG_SHORTPRE;
1371
Pavel Roskine0d687b2011-07-14 20:21:55 -04001372 trace_ath5k_rx(ah, skb);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001373
Pavel Roskine0d687b2011-07-14 20:21:55 -04001374 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001375
1376 /* check beacons in IBSS mode */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001377 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1378 ath5k_check_ibss_tsf(ah, skb, rxs);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001379
Pavel Roskine0d687b2011-07-14 20:21:55 -04001380 ieee80211_rx(ah->hw, skb);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001381}
1382
Bruno Randolf02a78b42010-06-16 19:11:56 +09001383/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1384 *
1385 * Check if we want to further process this frame or not. Also update
1386 * statistics. Return true if we want this frame, false if not.
1387 */
1388static bool
Pavel Roskine0d687b2011-07-14 20:21:55 -04001389ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
Bruno Randolf02a78b42010-06-16 19:11:56 +09001390{
Pavel Roskine0d687b2011-07-14 20:21:55 -04001391 ah->stats.rx_all_count++;
1392 ah->stats.rx_bytes_count += rs->rs_datalen;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001393
1394 if (unlikely(rs->rs_status)) {
1395 if (rs->rs_status & AR5K_RXERR_CRC)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001396 ah->stats.rxerr_crc++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001397 if (rs->rs_status & AR5K_RXERR_FIFO)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001398 ah->stats.rxerr_fifo++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001399 if (rs->rs_status & AR5K_RXERR_PHY) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001400 ah->stats.rxerr_phy++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001401 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001402 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001403 return false;
1404 }
1405 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1406 /*
1407 * Decrypt error. If the error occurred
1408 * because there was no hardware key, then
1409 * let the frame through so the upper layers
1410 * can process it. This is necessary for 5210
1411 * parts which have no way to setup a ``clear''
1412 * key cache entry.
1413 *
1414 * XXX do key cache faulting
1415 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001416 ah->stats.rxerr_decrypt++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001417 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1418 !(rs->rs_status & AR5K_RXERR_CRC))
1419 return true;
1420 }
1421 if (rs->rs_status & AR5K_RXERR_MIC) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001422 ah->stats.rxerr_mic++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001423 return true;
1424 }
1425
Bob Copeland23538c22010-08-15 13:03:13 -04001426 /* reject any frames with non-crypto errors */
1427 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
Bruno Randolf02a78b42010-06-16 19:11:56 +09001428 return false;
1429 }
1430
1431 if (unlikely(rs->rs_more)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001432 ah->stats.rxerr_jumbo++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001433 return false;
1434 }
1435 return true;
1436}
1437
Bruno Randolf8a89f062010-06-16 19:11:51 +09001438static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001439ath5k_set_current_imask(struct ath5k_hw *ah)
Felix Fietkauc266c712011-04-10 18:32:19 +02001440{
Pavel Roskin4fc54012011-07-07 18:14:25 -04001441 enum ath5k_int imask;
Felix Fietkauc266c712011-04-10 18:32:19 +02001442 unsigned long flags;
1443
Pavel Roskine0d687b2011-07-14 20:21:55 -04001444 spin_lock_irqsave(&ah->irqlock, flags);
1445 imask = ah->imask;
1446 if (ah->rx_pending)
Felix Fietkauc266c712011-04-10 18:32:19 +02001447 imask &= ~AR5K_INT_RX_ALL;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001448 if (ah->tx_pending)
Felix Fietkauc266c712011-04-10 18:32:19 +02001449 imask &= ~AR5K_INT_TX_ALL;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001450 ath5k_hw_set_imr(ah, imask);
1451 spin_unlock_irqrestore(&ah->irqlock, flags);
Felix Fietkauc266c712011-04-10 18:32:19 +02001452}
1453
1454static void
Bruno Randolf8a89f062010-06-16 19:11:51 +09001455ath5k_tasklet_rx(unsigned long data)
1456{
Bruno Randolfb47f4072008-03-05 18:35:45 +09001457 struct ath5k_rx_status rs = {};
Bob Copelandb6ea0352009-01-10 14:42:54 -05001458 struct sk_buff *skb, *next_skb;
1459 dma_addr_t next_skb_addr;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001460 struct ath5k_hw *ah = (void *)data;
Luis R. Rodriguezcc861f72009-11-04 09:11:34 -08001461 struct ath_common *common = ath5k_hw_common(ah);
Bob Copelandc57ca812009-04-15 07:57:35 -04001462 struct ath5k_buf *bf;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001463 struct ath5k_desc *ds;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001464 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001465
Pavel Roskine0d687b2011-07-14 20:21:55 -04001466 spin_lock(&ah->rxbuflock);
1467 if (list_empty(&ah->rxbuf)) {
1468 ATH5K_WARN(ah, "empty rx buf pool\n");
Jiri Slaby3a0f2c82008-07-15 17:44:18 +02001469 goto unlock;
1470 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001471 do {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001472 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001473 BUG_ON(bf->skb == NULL);
1474 skb = bf->skb;
1475 ds = bf->desc;
1476
Bob Copelandc57ca812009-04-15 07:57:35 -04001477 /* bail if HW is still using self-linked descriptor */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001478 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
Bob Copelandc57ca812009-04-15 07:57:35 -04001479 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001480
Pavel Roskine0d687b2011-07-14 20:21:55 -04001481 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001482 if (unlikely(ret == -EINPROGRESS))
1483 break;
1484 else if (unlikely(ret)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001485 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1486 ah->stats.rxerr_proc++;
Bruno Randolfb16062f2010-06-16 19:11:46 +09001487 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001488 }
1489
Pavel Roskine0d687b2011-07-14 20:21:55 -04001490 if (ath5k_receive_frame_ok(ah, &rs)) {
1491 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
Bruno Randolf76443952010-03-09 16:56:00 +09001492
Bruno Randolf02a78b42010-06-16 19:11:56 +09001493 /*
1494 * If we can't replace bf->skb with a new skb under
1495 * memory pressure, just skip this packet
1496 */
1497 if (!next_skb)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001498 goto next;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001499
Pavel Roskine0d687b2011-07-14 20:21:55 -04001500 dma_unmap_single(ah->dev, bf->skbaddr,
Bruno Randolf02a78b42010-06-16 19:11:56 +09001501 common->rx_bufsize,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001502 DMA_FROM_DEVICE);
Bruno Randolf02a78b42010-06-16 19:11:56 +09001503
1504 skb_put(skb, rs.rs_datalen);
1505
Pavel Roskine0d687b2011-07-14 20:21:55 -04001506 ath5k_receive_frame(ah, skb, &rs);
Bruno Randolf02a78b42010-06-16 19:11:56 +09001507
1508 bf->skb = next_skb;
1509 bf->skbaddr = next_skb_addr;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001510 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001511next:
Pavel Roskine0d687b2011-07-14 20:21:55 -04001512 list_move_tail(&bf->list, &ah->rxbuf);
1513 } while (ath5k_rxbuf_setup(ah, bf) == 0);
Jiri Slaby3a0f2c82008-07-15 17:44:18 +02001514unlock:
Pavel Roskine0d687b2011-07-14 20:21:55 -04001515 spin_unlock(&ah->rxbuflock);
1516 ah->rx_pending = false;
1517 ath5k_set_current_imask(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001518}
1519
1520
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001521/*************\
1522* TX Handling *
1523\*************/
1524
Johannes Berg7bb45682011-02-24 14:42:06 +01001525void
Bruno Randolfcd2c5482010-12-22 19:20:32 +09001526ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1527 struct ath5k_txq *txq)
Bob Copeland8a63fac2010-09-17 12:45:07 +09001528{
Pavel Roskine0d687b2011-07-14 20:21:55 -04001529 struct ath5k_hw *ah = hw->priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09001530 struct ath5k_buf *bf;
1531 unsigned long flags;
1532 int padsize;
1533
Pavel Roskine0d687b2011-07-14 20:21:55 -04001534 trace_ath5k_tx(ah, skb, txq);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001535
1536 /*
1537 * The hardware expects the header padded to 4 byte boundaries.
1538 * If this is not the case, we add the padding after the header.
1539 */
1540 padsize = ath5k_add_padding(skb);
1541 if (padsize < 0) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001542 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
Bob Copeland8a63fac2010-09-17 12:45:07 +09001543 " headroom to pad");
1544 goto drop_packet;
1545 }
1546
Felix Fietkau4e868792011-07-12 09:02:05 +08001547 if (txq->txq_len >= txq->txq_max &&
1548 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
Bruno Randolf925e0b02010-09-17 11:36:35 +09001549 ieee80211_stop_queue(hw, txq->qnum);
1550
Pavel Roskine0d687b2011-07-14 20:21:55 -04001551 spin_lock_irqsave(&ah->txbuflock, flags);
1552 if (list_empty(&ah->txbuf)) {
1553 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1554 spin_unlock_irqrestore(&ah->txbuflock, flags);
Bruno Randolf651d9372010-09-17 11:36:46 +09001555 ieee80211_stop_queues(hw);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001556 goto drop_packet;
1557 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04001558 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001559 list_del(&bf->list);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001560 ah->txbuf_len--;
1561 if (list_empty(&ah->txbuf))
Bob Copeland8a63fac2010-09-17 12:45:07 +09001562 ieee80211_stop_queues(hw);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001563 spin_unlock_irqrestore(&ah->txbuflock, flags);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001564
1565 bf->skb = skb;
1566
Pavel Roskine0d687b2011-07-14 20:21:55 -04001567 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
Bob Copeland8a63fac2010-09-17 12:45:07 +09001568 bf->skb = NULL;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001569 spin_lock_irqsave(&ah->txbuflock, flags);
1570 list_add_tail(&bf->list, &ah->txbuf);
1571 ah->txbuf_len++;
1572 spin_unlock_irqrestore(&ah->txbuflock, flags);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001573 goto drop_packet;
1574 }
Johannes Berg7bb45682011-02-24 14:42:06 +01001575 return;
Bob Copeland8a63fac2010-09-17 12:45:07 +09001576
1577drop_packet:
1578 dev_kfree_skb_any(skb);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001579}
1580
Bruno Randolf14404012010-09-17 11:36:51 +09001581static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001582ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
Bob Copeland0e472252011-01-24 23:32:55 -05001583 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
Bruno Randolf14404012010-09-17 11:36:51 +09001584{
1585 struct ieee80211_tx_info *info;
Felix Fietkaued895082011-04-10 18:32:17 +02001586 u8 tries[3];
Bruno Randolf14404012010-09-17 11:36:51 +09001587 int i;
1588
Pavel Roskine0d687b2011-07-14 20:21:55 -04001589 ah->stats.tx_all_count++;
1590 ah->stats.tx_bytes_count += skb->len;
Bruno Randolf14404012010-09-17 11:36:51 +09001591 info = IEEE80211_SKB_CB(skb);
1592
Felix Fietkaued895082011-04-10 18:32:17 +02001593 tries[0] = info->status.rates[0].count;
1594 tries[1] = info->status.rates[1].count;
1595 tries[2] = info->status.rates[2].count;
1596
Bruno Randolf14404012010-09-17 11:36:51 +09001597 ieee80211_tx_info_clear_status(info);
Felix Fietkaued895082011-04-10 18:32:17 +02001598
1599 for (i = 0; i < ts->ts_final_idx; i++) {
Bruno Randolf14404012010-09-17 11:36:51 +09001600 struct ieee80211_tx_rate *r =
1601 &info->status.rates[i];
1602
Felix Fietkaued895082011-04-10 18:32:17 +02001603 r->count = tries[i];
Bruno Randolf14404012010-09-17 11:36:51 +09001604 }
1605
Felix Fietkaued895082011-04-10 18:32:17 +02001606 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
Felix Fietkau6d7b97b2011-04-09 21:37:14 +02001607 info->status.rates[ts->ts_final_idx + 1].idx = -1;
Bruno Randolf14404012010-09-17 11:36:51 +09001608
1609 if (unlikely(ts->ts_status)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001610 ah->stats.ack_fail++;
Bruno Randolf14404012010-09-17 11:36:51 +09001611 if (ts->ts_status & AR5K_TXERR_FILT) {
1612 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001613 ah->stats.txerr_filt++;
Bruno Randolf14404012010-09-17 11:36:51 +09001614 }
1615 if (ts->ts_status & AR5K_TXERR_XRETRY)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001616 ah->stats.txerr_retry++;
Bruno Randolf14404012010-09-17 11:36:51 +09001617 if (ts->ts_status & AR5K_TXERR_FIFO)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001618 ah->stats.txerr_fifo++;
Bruno Randolf14404012010-09-17 11:36:51 +09001619 } else {
1620 info->flags |= IEEE80211_TX_STAT_ACK;
1621 info->status.ack_signal = ts->ts_rssi;
Felix Fietkau6d7b97b2011-04-09 21:37:14 +02001622
1623 /* count the successful attempt as well */
1624 info->status.rates[ts->ts_final_idx].count++;
Bruno Randolf14404012010-09-17 11:36:51 +09001625 }
1626
1627 /*
1628 * Remove MAC header padding before giving the frame
1629 * back to mac80211.
1630 */
1631 ath5k_remove_padding(skb);
1632
1633 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001634 ah->stats.antenna_tx[ts->ts_antenna]++;
Bruno Randolf14404012010-09-17 11:36:51 +09001635 else
Pavel Roskine0d687b2011-07-14 20:21:55 -04001636 ah->stats.antenna_tx[0]++; /* invalid */
Bruno Randolf14404012010-09-17 11:36:51 +09001637
Pavel Roskine0d687b2011-07-14 20:21:55 -04001638 trace_ath5k_tx_complete(ah, skb, txq, ts);
1639 ieee80211_tx_status(ah->hw, skb);
Bruno Randolf14404012010-09-17 11:36:51 +09001640}
Bob Copeland8a63fac2010-09-17 12:45:07 +09001641
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001642static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001643ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001644{
Bruno Randolfb47f4072008-03-05 18:35:45 +09001645 struct ath5k_tx_status ts = {};
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001646 struct ath5k_buf *bf, *bf0;
1647 struct ath5k_desc *ds;
1648 struct sk_buff *skb;
Bruno Randolf14404012010-09-17 11:36:51 +09001649 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001650
1651 spin_lock(&txq->lock);
1652 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
Bruno Randolf23413292010-09-17 11:37:07 +09001653
1654 txq->txq_poll_mark = false;
1655
1656 /* skb might already have been processed last time. */
1657 if (bf->skb != NULL) {
1658 ds = bf->desc;
1659
Pavel Roskine0d687b2011-07-14 20:21:55 -04001660 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
Bruno Randolf23413292010-09-17 11:37:07 +09001661 if (unlikely(ret == -EINPROGRESS))
1662 break;
1663 else if (unlikely(ret)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001664 ATH5K_ERR(ah,
Bruno Randolf23413292010-09-17 11:37:07 +09001665 "error %d while processing "
1666 "queue %u\n", ret, txq->qnum);
1667 break;
1668 }
1669
1670 skb = bf->skb;
1671 bf->skb = NULL;
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001672
Pavel Roskine0d687b2011-07-14 20:21:55 -04001673 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001674 DMA_TO_DEVICE);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001675 ath5k_tx_frame_completed(ah, skb, txq, &ts);
Bruno Randolf23413292010-09-17 11:37:07 +09001676 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001677
Bob Copelanda05988b2010-04-07 23:55:58 -04001678 /*
1679 * It's possible that the hardware can say the buffer is
1680 * completed when it hasn't yet loaded the ds_link from
Bruno Randolf23413292010-09-17 11:37:07 +09001681 * host memory and moved on.
1682 * Always keep the last descriptor to avoid HW races...
Bob Copelanda05988b2010-04-07 23:55:58 -04001683 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001684 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1685 spin_lock(&ah->txbuflock);
1686 list_move_tail(&bf->list, &ah->txbuf);
1687 ah->txbuf_len++;
Bruno Randolf23413292010-09-17 11:37:07 +09001688 txq->txq_len--;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001689 spin_unlock(&ah->txbuflock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001690 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001691 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001692 spin_unlock(&txq->lock);
Bruno Randolf4198a8d2010-10-05 13:27:17 +09001693 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001694 ieee80211_wake_queue(ah->hw, txq->qnum);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001695}
1696
1697static void
1698ath5k_tasklet_tx(unsigned long data)
1699{
Bob Copeland8784d2e2009-07-29 17:32:28 -04001700 int i;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001701 struct ath5k_hw *ah = (void *)data;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001702
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001703 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001704 if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i)))
1705 ath5k_tx_processq(ah, &ah->txqs[i]);
Felix Fietkauc266c712011-04-10 18:32:19 +02001706
Pavel Roskine0d687b2011-07-14 20:21:55 -04001707 ah->tx_pending = false;
1708 ath5k_set_current_imask(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001709}
1710
1711
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001712/*****************\
1713* Beacon handling *
1714\*****************/
1715
1716/*
1717 * Setup the beacon frame for transmit.
1718 */
1719static int
Pavel Roskine0d687b2011-07-14 20:21:55 -04001720ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001721{
1722 struct sk_buff *skb = bf->skb;
Johannes Berga888d522008-05-26 16:43:39 +02001723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001724 struct ath5k_desc *ds;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001725 int ret = 0;
1726 u8 antenna;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001727 u32 flags;
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001728 const int padsize = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001729
Pavel Roskine0d687b2011-07-14 20:21:55 -04001730 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001731 DMA_TO_DEVICE);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001732 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001733 "skbaddr %llx\n", skb, skb->data, skb->len,
1734 (unsigned long long)bf->skbaddr);
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001735
Pavel Roskine0d687b2011-07-14 20:21:55 -04001736 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1737 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001738 return -EIO;
1739 }
1740
1741 ds = bf->desc;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001742 antenna = ah->ah_tx_ant;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001743
1744 flags = AR5K_TXDESC_NOACK;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001745 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001746 ds->ds_link = bf->daddr; /* self-linked */
1747 flags |= AR5K_TXDESC_VEOL;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001748 } else
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001749 ds->ds_link = 0;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001750
1751 /*
1752 * If we use multiple antennas on AP and use
1753 * the Sectored AP scenario, switch antenna every
1754 * 4 beacons to make sure everybody hears our AP.
1755 * When a client tries to associate, hw will keep
1756 * track of the tx antenna to be used for this client
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04001757 * automatically, based on ACKed packets.
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001758 *
1759 * Note: AP still listens and transmits RTS on the
1760 * default antenna which is supposed to be an omni.
1761 *
1762 * Note2: On sectored scenarios it's possible to have
Bob Copelanda180a132010-08-15 13:03:12 -04001763 * multiple antennas (1 omni -- the default -- and 14
1764 * sectors), so if we choose to actually support this
1765 * mode, we need to allow the user to set how many antennas
1766 * we have and tweak the code below to send beacons
1767 * on all of them.
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001768 */
1769 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001770 antenna = ah->bsent & 4 ? 2 : 1;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001771
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001772
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001773 /* FIXME: If we are in g mode and rate is a CCK rate
1774 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1775 * from tx power (value is in dB units already) */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001776 ds->ds_data = bf->skbaddr;
Bruno Randolf281c56d2008-02-05 18:44:55 +09001777 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001778 ieee80211_get_hdrlen_from_skb(skb), padsize,
Pavel Roskine0d687b2011-07-14 20:21:55 -04001779 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
1780 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
Johannes Berg2e92e6f2008-05-15 12:55:27 +02001781 1, AR5K_TXKEYIX_INVALID,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001782 antenna, flags, 0, 0);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001783 if (ret)
1784 goto err_unmap;
1785
1786 return 0;
1787err_unmap:
Pavel Roskine0d687b2011-07-14 20:21:55 -04001788 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001789 return ret;
1790}
1791
1792/*
Bob Copeland8a63fac2010-09-17 12:45:07 +09001793 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1794 * this is called only once at config_bss time, for AP we do it every
1795 * SWBA interrupt so that the TIM will reflect buffered frames.
1796 *
1797 * Called with the beacon lock.
1798 */
Bruno Randolfcd2c5482010-12-22 19:20:32 +09001799int
Bob Copeland8a63fac2010-09-17 12:45:07 +09001800ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1801{
1802 int ret;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001803 struct ath5k_hw *ah = hw->priv;
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001804 struct ath5k_vif *avf = (void *)vif->drv_priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09001805 struct sk_buff *skb;
1806
1807 if (WARN_ON(!vif)) {
1808 ret = -EINVAL;
1809 goto out;
1810 }
1811
1812 skb = ieee80211_beacon_get(hw, vif);
1813
1814 if (!skb) {
1815 ret = -ENOMEM;
1816 goto out;
1817 }
1818
Pavel Roskine0d687b2011-07-14 20:21:55 -04001819 ath5k_txbuf_free_skb(ah, avf->bbuf);
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001820 avf->bbuf->skb = skb;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001821 ret = ath5k_beacon_setup(ah, avf->bbuf);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001822 if (ret)
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001823 avf->bbuf->skb = NULL;
Bob Copeland8a63fac2010-09-17 12:45:07 +09001824out:
1825 return ret;
1826}
1827
1828/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001829 * Transmit a beacon frame at SWBA. Dynamic updates to the
1830 * frame contents are done as needed and the slot time is
1831 * also adjusted based on current state.
1832 *
Bob Copeland5faaff72010-07-13 11:32:40 -04001833 * This is called from software irq context (beacontq tasklets)
1834 * or user context from ath5k_beacon_config.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001835 */
1836static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001837ath5k_beacon_send(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001838{
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001839 struct ieee80211_vif *vif;
1840 struct ath5k_vif *avf;
1841 struct ath5k_buf *bf;
Bob Copelandcec8db22009-07-04 12:59:51 -04001842 struct sk_buff *skb;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001843
Pavel Roskine0d687b2011-07-14 20:21:55 -04001844 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001845
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001846 /*
1847 * Check if the previous beacon has gone out. If
Bob Copelanda180a132010-08-15 13:03:12 -04001848 * not, don't don't try to post another: skip this
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001849 * period and wait for the next. Missed beacons
1850 * indicate a problem and should not occur. If we
1851 * miss too many consecutive beacons reset the device.
1852 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001853 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1854 ah->bmisscount++;
1855 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1856 "missed %u consecutive beacons\n", ah->bmisscount);
1857 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1858 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001859 "stuck beacon time (%u missed)\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -04001860 ah->bmisscount);
1861 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf8d67a032010-06-16 19:11:12 +09001862 "stuck beacon, resetting\n");
Pavel Roskine0d687b2011-07-14 20:21:55 -04001863 ieee80211_queue_work(ah->hw, &ah->reset_work);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001864 }
1865 return;
1866 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04001867 if (unlikely(ah->bmisscount != 0)) {
1868 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001869 "resume beacon xmit after %u misses\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -04001870 ah->bmisscount);
1871 ah->bmisscount = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001872 }
1873
Pavel Roskine0d687b2011-07-14 20:21:55 -04001874 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) ||
1875 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001876 u64 tsf = ath5k_hw_get_tsf64(ah);
1877 u32 tsftu = TSF_TO_TU(tsf);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001878 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1879 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1880 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001881 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -04001882 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001883 } else /* only one interface */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001884 vif = ah->bslot[0];
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001885
1886 if (!vif)
1887 return;
1888
1889 avf = (void *)vif->drv_priv;
1890 bf = avf->bbuf;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001891 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1892 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1893 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001894 return;
1895 }
1896
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001897 /*
1898 * Stop any current dma and put the new frame on the queue.
1899 * This should never fail since we check above that no frames
1900 * are still pending on the queue.
1901 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001902 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1903 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001904 /* NB: hw still stops DMA, so proceed */
1905 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001906
Javier Cardonad82b5772010-12-07 13:35:55 -08001907 /* refresh the beacon for AP or MESH mode */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001908 if (ah->opmode == NL80211_IFTYPE_AP ||
1909 ah->opmode == NL80211_IFTYPE_MESH_POINT)
1910 ath5k_beacon_update(ah->hw, vif);
Bob Copeland1071db82009-05-18 10:59:52 -04001911
Pavel Roskine0d687b2011-07-14 20:21:55 -04001912 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
Bob Copeland0e472252011-01-24 23:32:55 -05001913
Pavel Roskine0d687b2011-07-14 20:21:55 -04001914 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1915 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1916 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1917 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001918
Pavel Roskine0d687b2011-07-14 20:21:55 -04001919 skb = ieee80211_get_buffered_bc(ah->hw, vif);
Bob Copelandcec8db22009-07-04 12:59:51 -04001920 while (skb) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001921 ath5k_tx_queue(ah->hw, skb, ah->cabq);
Felix Fietkau4e868792011-07-12 09:02:05 +08001922
Pavel Roskine0d687b2011-07-14 20:21:55 -04001923 if (ah->cabq->txq_len >= ah->cabq->txq_max)
Felix Fietkau4e868792011-07-12 09:02:05 +08001924 break;
1925
Pavel Roskine0d687b2011-07-14 20:21:55 -04001926 skb = ieee80211_get_buffered_bc(ah->hw, vif);
Bob Copelandcec8db22009-07-04 12:59:51 -04001927 }
1928
Pavel Roskine0d687b2011-07-14 20:21:55 -04001929 ah->bsent++;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001930}
1931
Bruno Randolf9804b982008-01-19 18:17:59 +09001932/**
1933 * ath5k_beacon_update_timers - update beacon timers
1934 *
Pavel Roskine0d687b2011-07-14 20:21:55 -04001935 * @ah: struct ath5k_hw pointer we are operating on
Bruno Randolf9804b982008-01-19 18:17:59 +09001936 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1937 * beacon timer update based on the current HW TSF.
1938 *
1939 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1940 * of a received beacon or the current local hardware TSF and write it to the
1941 * beacon timer registers.
1942 *
1943 * This is called in a variety of situations, e.g. when a beacon is received,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001944 * when a TSF update has been detected, but also when an new IBSS is created or
Bruno Randolf9804b982008-01-19 18:17:59 +09001945 * when we otherwise know we have to update the timers, but we keep it in this
1946 * function to have it all together in one place.
1947 */
Bruno Randolfcd2c5482010-12-22 19:20:32 +09001948void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001949ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001950{
Bruno Randolf9804b982008-01-19 18:17:59 +09001951 u32 nexttbtt, intval, hw_tu, bc_tu;
1952 u64 hw_tsf;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001953
Pavel Roskine0d687b2011-07-14 20:21:55 -04001954 intval = ah->bintval & AR5K_BEACON_PERIOD;
1955 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) {
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001956 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1957 if (intval < 15)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001958 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001959 intval);
1960 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001961 if (WARN_ON(!intval))
1962 return;
1963
Bruno Randolf9804b982008-01-19 18:17:59 +09001964 /* beacon TSF converted to TU */
1965 bc_tu = TSF_TO_TU(bc_tsf);
1966
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001967 /* current TSF converted to TU */
Bruno Randolf9804b982008-01-19 18:17:59 +09001968 hw_tsf = ath5k_hw_get_tsf64(ah);
1969 hw_tu = TSF_TO_TU(hw_tsf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001970
Pavel Roskin633d0062011-07-07 18:14:01 -04001971#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
Bruno Randolf11f21df2010-09-27 12:22:26 +09001972 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001973 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
Bruno Randolf11f21df2010-09-27 12:22:26 +09001974 * configuration we need to make sure it is bigger than that. */
1975
Bruno Randolf9804b982008-01-19 18:17:59 +09001976 if (bc_tsf == -1) {
1977 /*
1978 * no beacons received, called internally.
1979 * just need to refresh timers based on HW TSF.
1980 */
1981 nexttbtt = roundup(hw_tu + FUDGE, intval);
1982 } else if (bc_tsf == 0) {
1983 /*
1984 * no beacon received, probably called by ath5k_reset_tsf().
1985 * reset TSF to start with 0.
1986 */
1987 nexttbtt = intval;
1988 intval |= AR5K_BEACON_RESET_TSF;
1989 } else if (bc_tsf > hw_tsf) {
1990 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001991 * beacon received, SW merge happened but HW TSF not yet updated.
Bruno Randolf9804b982008-01-19 18:17:59 +09001992 * not possible to reconfigure timers yet, but next time we
1993 * receive a beacon with the same BSSID, the hardware will
1994 * automatically update the TSF and then we need to reconfigure
1995 * the timers.
1996 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001997 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf9804b982008-01-19 18:17:59 +09001998 "need to wait for HW TSF sync\n");
1999 return;
2000 } else {
2001 /*
2002 * most important case for beacon synchronization between STA.
2003 *
2004 * beacon received and HW TSF has been already updated by HW.
2005 * update next TBTT based on the TSF of the beacon, but make
2006 * sure it is ahead of our local TSF timer.
2007 */
2008 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2009 }
2010#undef FUDGE
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002011
Pavel Roskine0d687b2011-07-14 20:21:55 -04002012 ah->nexttbtt = nexttbtt;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002013
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002014 intval |= AR5K_BEACON_ENA;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002015 ath5k_hw_init_beacon(ah, nexttbtt, intval);
Bruno Randolf9804b982008-01-19 18:17:59 +09002016
2017 /*
2018 * debugging output last in order to preserve the time critical aspect
2019 * of this function
2020 */
2021 if (bc_tsf == -1)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002022 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf9804b982008-01-19 18:17:59 +09002023 "reconfigured timers based on HW TSF\n");
2024 else if (bc_tsf == 0)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002025 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf9804b982008-01-19 18:17:59 +09002026 "reset HW TSF and timers\n");
2027 else
Pavel Roskine0d687b2011-07-14 20:21:55 -04002028 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf9804b982008-01-19 18:17:59 +09002029 "updated timers based on beacon TSF\n");
2030
Pavel Roskine0d687b2011-07-14 20:21:55 -04002031 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
David Miller04f93a82008-02-15 16:08:59 -08002032 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2033 (unsigned long long) bc_tsf,
2034 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002035 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
Bruno Randolf9804b982008-01-19 18:17:59 +09002036 intval & AR5K_BEACON_PERIOD,
2037 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2038 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002039}
2040
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002041/**
2042 * ath5k_beacon_config - Configure the beacon queues and interrupts
2043 *
Pavel Roskine0d687b2011-07-14 20:21:55 -04002044 * @ah: struct ath5k_hw pointer we are operating on
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002045 *
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002046 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
Bruno Randolf6ba81c22008-03-05 18:36:26 +09002047 * interrupts to detect TSF updates only.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002048 */
Bruno Randolfcd2c5482010-12-22 19:20:32 +09002049void
Pavel Roskine0d687b2011-07-14 20:21:55 -04002050ath5k_beacon_config(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002051{
Bob Copelandb5f03952009-02-15 12:06:10 -05002052 unsigned long flags;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002053
Pavel Roskine0d687b2011-07-14 20:21:55 -04002054 spin_lock_irqsave(&ah->block, flags);
2055 ah->bmisscount = 0;
2056 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002057
Pavel Roskine0d687b2011-07-14 20:21:55 -04002058 if (ah->enable_beacon) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002059 /*
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002060 * In IBSS mode we use a self-linked tx descriptor and let the
2061 * hardware send the beacons automatically. We have to load it
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002062 * only once here.
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002063 * We use the SWBA interrupt only to keep track of the beacon
Bruno Randolf6ba81c22008-03-05 18:36:26 +09002064 * timers in order to detect automatic TSF updates.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002065 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002066 ath5k_beaconq_config(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002067
Pavel Roskine0d687b2011-07-14 20:21:55 -04002068 ah->imask |= AR5K_INT_SWBA;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002069
Pavel Roskine0d687b2011-07-14 20:21:55 -04002070 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
Bob Copeland21800492009-07-04 12:59:52 -04002071 if (ath5k_hw_hasveol(ah))
Pavel Roskine0d687b2011-07-14 20:21:55 -04002072 ath5k_beacon_send(ah);
Jiri Slabyda966bc2008-10-12 22:54:10 +02002073 } else
Pavel Roskine0d687b2011-07-14 20:21:55 -04002074 ath5k_beacon_update_timers(ah, -1);
Bob Copeland21800492009-07-04 12:59:52 -04002075 } else {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002076 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002077 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002078
Pavel Roskine0d687b2011-07-14 20:21:55 -04002079 ath5k_hw_set_imr(ah, ah->imask);
Bob Copeland21800492009-07-04 12:59:52 -04002080 mmiowb();
Pavel Roskine0d687b2011-07-14 20:21:55 -04002081 spin_unlock_irqrestore(&ah->block, flags);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002082}
2083
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002084static void ath5k_tasklet_beacon(unsigned long data)
2085{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002086 struct ath5k_hw *ah = (struct ath5k_hw *) data;
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002087
2088 /*
2089 * Software beacon alert--time to send a beacon.
2090 *
2091 * In IBSS mode we use this interrupt just to
2092 * keep track of the next TBTT (target beacon
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04002093 * transmission time) in order to detect whether
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002094 * automatic TSF updates happened.
2095 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002096 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04002097 /* XXX: only if VEOL supported */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002098 u64 tsf = ath5k_hw_get_tsf64(ah);
2099 ah->nexttbtt += ah->bintval;
2100 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002101 "SWBA nexttbtt: %x hw_tu: %x "
2102 "TSF: %llx\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -04002103 ah->nexttbtt,
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002104 TSF_TO_TU(tsf),
2105 (unsigned long long) tsf);
2106 } else {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002107 spin_lock(&ah->block);
2108 ath5k_beacon_send(ah);
2109 spin_unlock(&ah->block);
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002110 }
2111}
2112
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002113
2114/********************\
2115* Interrupt handling *
2116\********************/
2117
Bruno Randolf6a8a3f62010-03-25 14:49:19 +09002118static void
2119ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2120{
Bruno Randolf2111ac02010-04-02 18:44:08 +09002121 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2122 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2123 /* run ANI only when full calibration is not active */
2124 ah->ah_cal_next_ani = jiffies +
2125 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002126 tasklet_schedule(&ah->ani_tasklet);
Bruno Randolf2111ac02010-04-02 18:44:08 +09002127
2128 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
Bruno Randolf6a8a3f62010-03-25 14:49:19 +09002129 ah->ah_cal_next_full = jiffies +
2130 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002131 tasklet_schedule(&ah->calib);
Bruno Randolf6a8a3f62010-03-25 14:49:19 +09002132 }
2133 /* we could use SWI to generate enough interrupts to meet our
2134 * calibration interval requirements, if necessary:
2135 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2136}
2137
Felix Fietkauc266c712011-04-10 18:32:19 +02002138static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04002139ath5k_schedule_rx(struct ath5k_hw *ah)
Felix Fietkauc266c712011-04-10 18:32:19 +02002140{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002141 ah->rx_pending = true;
2142 tasklet_schedule(&ah->rxtq);
Felix Fietkauc266c712011-04-10 18:32:19 +02002143}
2144
2145static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04002146ath5k_schedule_tx(struct ath5k_hw *ah)
Felix Fietkauc266c712011-04-10 18:32:19 +02002147{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002148 ah->tx_pending = true;
2149 tasklet_schedule(&ah->txtq);
Felix Fietkauc266c712011-04-10 18:32:19 +02002150}
2151
Pavel Roskinf5cbc8b2011-06-15 18:03:22 -04002152static irqreturn_t
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002153ath5k_intr(int irq, void *dev_id)
2154{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002155 struct ath5k_hw *ah = dev_id;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002156 enum ath5k_int status;
2157 unsigned int counter = 1000;
2158
Pavel Roskine0d687b2011-07-14 20:21:55 -04002159 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
Felix Fietkau4cebb342010-12-02 10:27:21 +01002160 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2161 !ath5k_hw_is_intr_pending(ah))))
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002162 return IRQ_NONE;
2163
2164 do {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002165 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002166 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2167 status, ah->imask);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002168 if (unlikely(status & AR5K_INT_FATAL)) {
2169 /*
2170 * Fatal errors are unrecoverable.
2171 * Typically these are caused by DMA errors.
2172 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002173 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf8d67a032010-06-16 19:11:12 +09002174 "fatal int, resetting\n");
Pavel Roskine0d687b2011-07-14 20:21:55 -04002175 ieee80211_queue_work(ah->hw, &ah->reset_work);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002176 } else if (unlikely(status & AR5K_INT_RXORN)) {
Bruno Randolf87d77c42010-04-12 16:38:52 +09002177 /*
2178 * Receive buffers are full. Either the bus is busy or
2179 * the CPU is not fast enough to process all received
2180 * frames.
2181 * Older chipsets need a reset to come out of this
2182 * condition, but we treat it as RX for newer chips.
2183 * We don't know exactly which versions need a reset -
2184 * this guess is copied from the HAL.
2185 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002186 ah->stats.rxorn_intr++;
Bruno Randolf8d67a032010-06-16 19:11:12 +09002187 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002188 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf8d67a032010-06-16 19:11:12 +09002189 "rx overrun, resetting\n");
Pavel Roskine0d687b2011-07-14 20:21:55 -04002190 ieee80211_queue_work(ah->hw, &ah->reset_work);
Pavel Roskind2c7f772011-07-07 18:14:07 -04002191 } else
Pavel Roskine0d687b2011-07-14 20:21:55 -04002192 ath5k_schedule_rx(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002193 } else {
Pavel Roskind2c7f772011-07-07 18:14:07 -04002194 if (status & AR5K_INT_SWBA)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002195 tasklet_hi_schedule(&ah->beacontq);
Pavel Roskind2c7f772011-07-07 18:14:07 -04002196
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002197 if (status & AR5K_INT_RXEOL) {
2198 /*
2199 * NB: the hardware should re-read the link when
2200 * RXE bit is written, but it doesn't work at
2201 * least on older hardware revs.
2202 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002203 ah->stats.rxeol_intr++;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002204 }
2205 if (status & AR5K_INT_TXURN) {
2206 /* bump tx trigger level */
2207 ath5k_hw_update_tx_triglevel(ah, true);
2208 }
Nick Kossifidis4c674c62008-10-26 20:40:25 +02002209 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
Pavel Roskine0d687b2011-07-14 20:21:55 -04002210 ath5k_schedule_rx(ah);
Nick Kossifidis4c674c62008-10-26 20:40:25 +02002211 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2212 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
Pavel Roskine0d687b2011-07-14 20:21:55 -04002213 ath5k_schedule_tx(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002214 if (status & AR5K_INT_BMISS) {
Nick Kossifidis1e3e6e82009-02-09 06:15:42 +02002215 /* TODO */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002216 }
2217 if (status & AR5K_INT_MIB) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002218 ah->stats.mib_intr++;
Bruno Randolf495391d2010-03-25 14:49:36 +09002219 ath5k_hw_update_mib_counters(ah);
Bruno Randolf2111ac02010-04-02 18:44:08 +09002220 ath5k_ani_mib_intr(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002221 }
Tobias Doerffele6a3b612009-06-09 17:33:27 +02002222 if (status & AR5K_INT_GPIO)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002223 tasklet_schedule(&ah->rf_kill.toggleq);
Bob Copelanda6ae0712009-06-09 23:43:11 -04002224
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002225 }
Felix Fietkau4cebb342010-12-02 10:27:21 +01002226
2227 if (ath5k_get_bus_type(ah) == ATH_AHB)
2228 break;
2229
Bob Copeland2516baa2009-04-27 22:18:10 -04002230 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002231
Pavel Roskine0d687b2011-07-14 20:21:55 -04002232 if (ah->rx_pending || ah->tx_pending)
2233 ath5k_set_current_imask(ah);
Felix Fietkauc266c712011-04-10 18:32:19 +02002234
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002235 if (unlikely(!counter))
Pavel Roskine0d687b2011-07-14 20:21:55 -04002236 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002237
Bruno Randolf6a8a3f62010-03-25 14:49:19 +09002238 ath5k_intr_calibration_poll(ah);
Nick Kossifidis6e2206622009-08-10 03:31:31 +03002239
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002240 return IRQ_HANDLED;
2241}
2242
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002243/*
2244 * Periodically recalibrate the PHY to account
2245 * for temperature/environment changes.
2246 */
2247static void
Nick Kossifidis6e2206622009-08-10 03:31:31 +03002248ath5k_tasklet_calibrate(unsigned long data)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002249{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002250 struct ath5k_hw *ah = (void *)data;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002251
Nick Kossifidis6e2206622009-08-10 03:31:31 +03002252 /* Only full calibration for now */
Bruno Randolfe65e1d72010-03-25 14:49:09 +09002253 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
Nick Kossifidis6e2206622009-08-10 03:31:31 +03002254
Pavel Roskine0d687b2011-07-14 20:21:55 -04002255 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2256 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2257 ah->curchan->hw_value);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002258
Nick Kossifidis6f3b4142009-02-09 06:03:41 +02002259 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002260 /*
2261 * Rfgain is out of bounds, reset the chip
2262 * to load new gain values.
2263 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002264 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2265 ieee80211_queue_work(ah->hw, &ah->reset_work);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002266 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04002267 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2268 ATH5K_ERR(ah, "calibration of channel %u failed\n",
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05002269 ieee80211_frequency_to_channel(
Pavel Roskine0d687b2011-07-14 20:21:55 -04002270 ah->curchan->center_freq));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002271
Bruno Randolf0e8e02d2010-05-19 10:31:05 +09002272 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
Bruno Randolf651d9372010-09-17 11:36:46 +09002273 * doesn't.
2274 * TODO: We should stop TX here, so that it doesn't interfere.
2275 * Note that stopping the queues is not enough to stop TX! */
Bruno Randolfafe86282010-05-19 10:31:10 +09002276 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2277 ah->ah_cal_next_nf = jiffies +
2278 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
Bruno Randolfafe86282010-05-19 10:31:10 +09002279 ath5k_hw_update_noise_floor(ah);
Bruno Randolfafe86282010-05-19 10:31:10 +09002280 }
Nick Kossifidis6e2206622009-08-10 03:31:31 +03002281
Bruno Randolfe65e1d72010-03-25 14:49:09 +09002282 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002283}
2284
2285
Bruno Randolf2111ac02010-04-02 18:44:08 +09002286static void
2287ath5k_tasklet_ani(unsigned long data)
2288{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002289 struct ath5k_hw *ah = (void *)data;
Bruno Randolf2111ac02010-04-02 18:44:08 +09002290
2291 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2292 ath5k_ani_calibration(ah);
2293 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002294}
2295
2296
Bruno Randolf4edd7612010-09-17 11:36:56 +09002297static void
2298ath5k_tx_complete_poll_work(struct work_struct *work)
2299{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002300 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002301 tx_complete_work.work);
2302 struct ath5k_txq *txq;
2303 int i;
2304 bool needreset = false;
2305
Pavel Roskine0d687b2011-07-14 20:21:55 -04002306 mutex_lock(&ah->lock);
Bob Copeland599b13a2011-01-18 08:06:43 -05002307
Pavel Roskine0d687b2011-07-14 20:21:55 -04002308 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2309 if (ah->txqs[i].setup) {
2310 txq = &ah->txqs[i];
Bruno Randolf4edd7612010-09-17 11:36:56 +09002311 spin_lock_bh(&txq->lock);
Bruno Randolf23413292010-09-17 11:37:07 +09002312 if (txq->txq_len > 1) {
Bruno Randolf4edd7612010-09-17 11:36:56 +09002313 if (txq->txq_poll_mark) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002314 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002315 "TX queue stuck %d\n",
2316 txq->qnum);
2317 needreset = true;
Bruno Randolf923e5b32010-09-17 11:37:02 +09002318 txq->txq_stuck++;
Bruno Randolf4edd7612010-09-17 11:36:56 +09002319 spin_unlock_bh(&txq->lock);
2320 break;
2321 } else {
2322 txq->txq_poll_mark = true;
2323 }
2324 }
2325 spin_unlock_bh(&txq->lock);
2326 }
2327 }
2328
2329 if (needreset) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002330 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002331 "TX queues stuck, resetting\n");
Pavel Roskine0d687b2011-07-14 20:21:55 -04002332 ath5k_reset(ah, NULL, true);
Bruno Randolf4edd7612010-09-17 11:36:56 +09002333 }
2334
Pavel Roskine0d687b2011-07-14 20:21:55 -04002335 mutex_unlock(&ah->lock);
Bob Copeland599b13a2011-01-18 08:06:43 -05002336
Pavel Roskine0d687b2011-07-14 20:21:55 -04002337 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002338 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2339}
2340
2341
Bob Copeland8a63fac2010-09-17 12:45:07 +09002342/*************************\
2343* Initialization routines *
2344\*************************/
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002345
Pavel Roskin25380d82011-07-07 18:13:42 -04002346int __devinit
Pavel Roskine0d687b2011-07-14 20:21:55 -04002347ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
Felix Fietkau132b1c32010-12-02 10:26:56 +01002348{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002349 struct ieee80211_hw *hw = ah->hw;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002350 struct ath_common *common;
2351 int ret;
2352 int csz;
2353
2354 /* Initialize driver private data */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002355 SET_IEEE80211_DEV(hw, ah->dev);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002356 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
Nick Kossifidisb9e61f12010-12-03 06:12:39 +02002357 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2358 IEEE80211_HW_SIGNAL_DBM |
2359 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002360
2361 hw->wiphy->interface_modes =
2362 BIT(NL80211_IFTYPE_AP) |
2363 BIT(NL80211_IFTYPE_STATION) |
2364 BIT(NL80211_IFTYPE_ADHOC) |
2365 BIT(NL80211_IFTYPE_MESH_POINT);
2366
Bruno Randolf3de135d2010-12-16 11:30:33 +09002367 /* both antennas can be configured as RX or TX */
2368 hw->wiphy->available_antennas_tx = 0x3;
2369 hw->wiphy->available_antennas_rx = 0x3;
2370
Felix Fietkau132b1c32010-12-02 10:26:56 +01002371 hw->extra_tx_headroom = 2;
2372 hw->channel_change_time = 5000;
2373
2374 /*
2375 * Mark the device as detached to avoid processing
2376 * interrupts until setup is complete.
2377 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002378 __set_bit(ATH_STAT_INVALID, ah->status);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002379
Pavel Roskine0d687b2011-07-14 20:21:55 -04002380 ah->opmode = NL80211_IFTYPE_STATION;
2381 ah->bintval = 1000;
2382 mutex_init(&ah->lock);
2383 spin_lock_init(&ah->rxbuflock);
2384 spin_lock_init(&ah->txbuflock);
2385 spin_lock_init(&ah->block);
2386 spin_lock_init(&ah->irqlock);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002387
2388 /* Setup interrupt handler */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002389 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002390 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002391 ATH5K_ERR(ah, "request_irq failed\n");
Felix Fietkau132b1c32010-12-02 10:26:56 +01002392 goto err;
2393 }
2394
Pavel Roskine0d687b2011-07-14 20:21:55 -04002395 common = ath5k_hw_common(ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002396 common->ops = &ath5k_common_ops;
2397 common->bus_ops = bus_ops;
Pavel Roskine0d687b2011-07-14 20:21:55 -04002398 common->ah = ah;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002399 common->hw = hw;
Pavel Roskine0d687b2011-07-14 20:21:55 -04002400 common->priv = ah;
Felix Fietkau26d16d22011-07-12 09:02:01 +08002401 common->clockrate = 40;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002402
2403 /*
2404 * Cache line size is used to size and align various
2405 * structures used to communicate with the hardware.
2406 */
2407 ath5k_read_cachesize(common, &csz);
2408 common->cachelsz = csz << 2; /* convert to bytes */
2409
2410 spin_lock_init(&common->cc_lock);
2411
2412 /* Initialize device */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002413 ret = ath5k_hw_init(ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002414 if (ret)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002415 goto err_irq;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002416
2417 /* set up multi-rate retry capabilities */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002418 if (ah->ah_version == AR5K_AR5212) {
Felix Fietkau132b1c32010-12-02 10:26:56 +01002419 hw->max_rates = 4;
Bruno Randolf76a9f6f2011-01-28 16:52:11 +09002420 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2421 AR5K_INIT_RETRY_LONG);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002422 }
2423
2424 hw->vif_data_size = sizeof(struct ath5k_vif);
2425
2426 /* Finish private driver data initialization */
2427 ret = ath5k_init(hw);
2428 if (ret)
2429 goto err_ah;
2430
Pavel Roskine0d687b2011-07-14 20:21:55 -04002431 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2432 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2433 ah->ah_mac_srev,
2434 ah->ah_phy_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002435
Pavel Roskine0d687b2011-07-14 20:21:55 -04002436 if (!ah->ah_single_chip) {
Felix Fietkau132b1c32010-12-02 10:26:56 +01002437 /* Single chip radio (!RF5111) */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002438 if (ah->ah_radio_5ghz_revision &&
2439 !ah->ah_radio_2ghz_revision) {
Felix Fietkau132b1c32010-12-02 10:26:56 +01002440 /* No 5GHz support -> report 2GHz radio */
2441 if (!test_bit(AR5K_MODE_11A,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002442 ah->ah_capabilities.cap_mode)) {
2443 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
Felix Fietkau132b1c32010-12-02 10:26:56 +01002444 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002445 ah->ah_radio_5ghz_revision),
2446 ah->ah_radio_5ghz_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002447 /* No 2GHz support (5110 and some
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04002448 * 5GHz only cards) -> report 5GHz radio */
Felix Fietkau132b1c32010-12-02 10:26:56 +01002449 } else if (!test_bit(AR5K_MODE_11B,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002450 ah->ah_capabilities.cap_mode)) {
2451 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
Felix Fietkau132b1c32010-12-02 10:26:56 +01002452 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002453 ah->ah_radio_5ghz_revision),
2454 ah->ah_radio_5ghz_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002455 /* Multiband radio */
2456 } else {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002457 ATH5K_INFO(ah, "RF%s multiband radio found"
Felix Fietkau132b1c32010-12-02 10:26:56 +01002458 " (0x%x)\n",
2459 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002460 ah->ah_radio_5ghz_revision),
2461 ah->ah_radio_5ghz_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002462 }
2463 }
2464 /* Multi chip radio (RF5111 - RF2111) ->
2465 * report both 2GHz/5GHz radios */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002466 else if (ah->ah_radio_5ghz_revision &&
2467 ah->ah_radio_2ghz_revision) {
2468 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
Felix Fietkau132b1c32010-12-02 10:26:56 +01002469 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002470 ah->ah_radio_5ghz_revision),
2471 ah->ah_radio_5ghz_revision);
2472 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
Felix Fietkau132b1c32010-12-02 10:26:56 +01002473 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002474 ah->ah_radio_2ghz_revision),
2475 ah->ah_radio_2ghz_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002476 }
2477 }
2478
Pavel Roskine0d687b2011-07-14 20:21:55 -04002479 ath5k_debug_init_device(ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002480
2481 /* ready to process interrupts */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002482 __clear_bit(ATH_STAT_INVALID, ah->status);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002483
2484 return 0;
2485err_ah:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002486 ath5k_hw_deinit(ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002487err_irq:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002488 free_irq(ah->irq, ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002489err:
2490 return ret;
2491}
2492
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002493static int
Pavel Roskine0d687b2011-07-14 20:21:55 -04002494ath5k_stop_locked(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002495{
Bob Copelandcec8db22009-07-04 12:59:51 -04002496
Pavel Roskine0d687b2011-07-14 20:21:55 -04002497 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2498 test_bit(ATH_STAT_INVALID, ah->status));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002499
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002500 /*
Bob Copeland8a63fac2010-09-17 12:45:07 +09002501 * Shutdown the hardware and driver:
2502 * stop output from above
2503 * disable interrupts
2504 * turn off timers
2505 * turn off the radio
2506 * clear transmit machinery
2507 * clear receive machinery
2508 * drain and release tx queues
2509 * reclaim beacon resources
2510 * power down hardware
2511 *
2512 * Note that some of this work is not possible if the
2513 * hardware is gone (invalid).
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002514 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002515 ieee80211_stop_queues(ah->hw);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002516
Pavel Roskine0d687b2011-07-14 20:21:55 -04002517 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2518 ath5k_led_off(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002519 ath5k_hw_set_imr(ah, 0);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002520 synchronize_irq(ah->irq);
2521 ath5k_rx_stop(ah);
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02002522 ath5k_hw_dma_stop(ah);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002523 ath5k_drain_tx_buffs(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002524 ath5k_hw_phy_disable(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002525 }
2526
Bob Copeland8a63fac2010-09-17 12:45:07 +09002527 return 0;
2528}
2529
Pavel Roskinfabba042011-07-21 13:36:28 -04002530int ath5k_start(struct ieee80211_hw *hw)
Bob Copeland8a63fac2010-09-17 12:45:07 +09002531{
Pavel Roskinfabba042011-07-21 13:36:28 -04002532 struct ath5k_hw *ah = hw->priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002533 struct ath_common *common = ath5k_hw_common(ah);
2534 int ret, i;
2535
Pavel Roskine0d687b2011-07-14 20:21:55 -04002536 mutex_lock(&ah->lock);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002537
Pavel Roskine0d687b2011-07-14 20:21:55 -04002538 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002539
2540 /*
2541 * Stop anything previously setup. This is safe
2542 * no matter this is the first time through or not.
2543 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002544 ath5k_stop_locked(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002545
2546 /*
2547 * The basic interface to setting the hardware in a good
2548 * state is ``reset''. On return the hardware is known to
2549 * be powered up and with interrupts disabled. This must
2550 * be followed by initialization of the appropriate bits
2551 * and then setup of the interrupt mask.
2552 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002553 ah->curchan = ah->hw->conf.channel;
2554 ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
Bob Copeland8a63fac2010-09-17 12:45:07 +09002555 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2556 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2557
Pavel Roskine0d687b2011-07-14 20:21:55 -04002558 ret = ath5k_reset(ah, NULL, false);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002559 if (ret)
2560 goto done;
2561
2562 ath5k_rfkill_hw_start(ah);
2563
2564 /*
2565 * Reset the key cache since some parts do not reset the
2566 * contents on initial power up or resume from suspend.
2567 */
2568 for (i = 0; i < common->keymax; i++)
2569 ath_hw_keyreset(common, (u16) i);
2570
Nick Kossifidis61cde032010-11-23 21:12:23 +02002571 /* Use higher rates for acks instead of base
2572 * rate */
2573 ah->ah_ack_bitrate_high = true;
Ben Greearb1ae1ed2010-09-30 12:22:58 -07002574
Pavel Roskine0d687b2011-07-14 20:21:55 -04002575 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2576 ah->bslot[i] = NULL;
Ben Greearb1ae1ed2010-09-30 12:22:58 -07002577
Bob Copeland8a63fac2010-09-17 12:45:07 +09002578 ret = 0;
2579done:
2580 mmiowb();
Pavel Roskine0d687b2011-07-14 20:21:55 -04002581 mutex_unlock(&ah->lock);
Bruno Randolf4edd7612010-09-17 11:36:56 +09002582
Pavel Roskine0d687b2011-07-14 20:21:55 -04002583 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002584 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2585
Bob Copeland8a63fac2010-09-17 12:45:07 +09002586 return ret;
2587}
2588
Pavel Roskine0d687b2011-07-14 20:21:55 -04002589static void ath5k_stop_tasklets(struct ath5k_hw *ah)
Bob Copeland8a63fac2010-09-17 12:45:07 +09002590{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002591 ah->rx_pending = false;
2592 ah->tx_pending = false;
2593 tasklet_kill(&ah->rxtq);
2594 tasklet_kill(&ah->txtq);
2595 tasklet_kill(&ah->calib);
2596 tasklet_kill(&ah->beacontq);
2597 tasklet_kill(&ah->ani_tasklet);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002598}
2599
2600/*
2601 * Stop the device, grabbing the top-level lock to protect
2602 * against concurrent entry through ath5k_init (which can happen
2603 * if another thread does a system call and the thread doing the
2604 * stop is preempted).
2605 */
Pavel Roskinfabba042011-07-21 13:36:28 -04002606void ath5k_stop(struct ieee80211_hw *hw)
Bob Copeland8a63fac2010-09-17 12:45:07 +09002607{
Pavel Roskinfabba042011-07-21 13:36:28 -04002608 struct ath5k_hw *ah = hw->priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002609 int ret;
2610
Pavel Roskine0d687b2011-07-14 20:21:55 -04002611 mutex_lock(&ah->lock);
2612 ret = ath5k_stop_locked(ah);
2613 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
Bob Copeland8a63fac2010-09-17 12:45:07 +09002614 /*
2615 * Don't set the card in full sleep mode!
2616 *
2617 * a) When the device is in this state it must be carefully
2618 * woken up or references to registers in the PCI clock
2619 * domain may freeze the bus (and system). This varies
2620 * by chip and is mostly an issue with newer parts
2621 * (madwifi sources mentioned srev >= 0x78) that go to
2622 * sleep more quickly.
2623 *
2624 * b) On older chips full sleep results a weird behaviour
2625 * during wakeup. I tested various cards with srev < 0x78
2626 * and they don't wake up after module reload, a second
2627 * module reload is needed to bring the card up again.
2628 *
2629 * Until we figure out what's going on don't enable
2630 * full chip reset on any chip (this is what Legacy HAL
2631 * and Sam's HAL do anyway). Instead Perform a full reset
2632 * on the device (same as initial state after attach) and
2633 * leave it idle (keep MAC/BB on warm reset) */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002634 ret = ath5k_hw_on_hold(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002635
Pavel Roskine0d687b2011-07-14 20:21:55 -04002636 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bob Copeland8a63fac2010-09-17 12:45:07 +09002637 "putting device to sleep\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002638 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002639
Bob Copeland8a63fac2010-09-17 12:45:07 +09002640 mmiowb();
Pavel Roskine0d687b2011-07-14 20:21:55 -04002641 mutex_unlock(&ah->lock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002642
Pavel Roskine0d687b2011-07-14 20:21:55 -04002643 ath5k_stop_tasklets(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002644
Pavel Roskine0d687b2011-07-14 20:21:55 -04002645 cancel_delayed_work_sync(&ah->tx_complete_work);
Bruno Randolf4edd7612010-09-17 11:36:56 +09002646
Pavel Roskine0d687b2011-07-14 20:21:55 -04002647 ath5k_rfkill_hw_stop(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002648}
2649
Bob Copeland209d889b2009-05-07 08:09:08 -04002650/*
2651 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2652 * and change to the given channel.
Bob Copeland5faaff72010-07-13 11:32:40 -04002653 *
Pavel Roskine0d687b2011-07-14 20:21:55 -04002654 * This should be called with ah->lock.
Bob Copeland209d889b2009-05-07 08:09:08 -04002655 */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002656static int
Pavel Roskine0d687b2011-07-14 20:21:55 -04002657ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
Nick Kossifidis8aec7af2010-11-23 21:39:28 +02002658 bool skip_pcu)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002659{
Bruno Randolff15a4bb2010-12-16 16:22:20 +09002660 struct ath_common *common = ath5k_hw_common(ah);
Nick Kossifidis344b54b2010-12-03 06:07:13 +02002661 int ret, ani_mode;
Nick Kossifidisa99168e2011-06-02 03:09:48 +03002662 bool fast;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002663
Pavel Roskine0d687b2011-07-14 20:21:55 -04002664 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002665
Bob Copeland450464d2010-07-13 11:32:41 -04002666 ath5k_hw_set_imr(ah, 0);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002667 synchronize_irq(ah->irq);
2668 ath5k_stop_tasklets(ah);
Bob Copeland450464d2010-07-13 11:32:41 -04002669
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002670 /* Save ani mode and disable ANI during
Nick Kossifidis344b54b2010-12-03 06:07:13 +02002671 * reset. If we don't we might get false
2672 * PHY error interrupts. */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002673 ani_mode = ah->ani_state.ani_mode;
Nick Kossifidis344b54b2010-12-03 06:07:13 +02002674 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2675
Nick Kossifidis19252ec2010-12-03 06:05:19 +02002676 /* We are going to empty hw queues
2677 * so we should also free any remaining
2678 * tx buffers */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002679 ath5k_drain_tx_buffs(ah);
Bruno Randolf930a7622011-01-19 18:21:13 +09002680 if (chan)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002681 ah->curchan = chan;
Nick Kossifidisa99168e2011-06-02 03:09:48 +03002682
2683 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2684
Pavel Roskine0d687b2011-07-14 20:21:55 -04002685 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002686 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002687 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002688 goto err;
2689 }
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002690
Pavel Roskine0d687b2011-07-14 20:21:55 -04002691 ret = ath5k_rx_start(ah);
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002692 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002693 ATH5K_ERR(ah, "can't start recv logic\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002694 goto err;
2695 }
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002696
Nick Kossifidis344b54b2010-12-03 06:07:13 +02002697 ath5k_ani_init(ah, ani_mode);
Bruno Randolf2111ac02010-04-02 18:44:08 +09002698
Felix Fietkaufe00deb2011-07-12 09:02:02 +08002699 ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100);
Bruno Randolfac559522010-05-19 10:30:55 +09002700 ah->ah_cal_next_ani = jiffies;
Bruno Randolfafe86282010-05-19 10:31:10 +09002701 ah->ah_cal_next_nf = jiffies;
Bruno Randolf5dcc03f2010-12-02 19:12:31 +09002702 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
Bruno Randolfafe86282010-05-19 10:31:10 +09002703
Bruno Randolff15a4bb2010-12-16 16:22:20 +09002704 /* clear survey data and cycle counters */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002705 memset(&ah->survey, 0, sizeof(ah->survey));
Bob Copelandbb007552010-12-26 12:10:05 -05002706 spin_lock_bh(&common->cc_lock);
Bruno Randolff15a4bb2010-12-16 16:22:20 +09002707 ath_hw_cycle_counters_update(common);
2708 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2709 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
Bob Copelandbb007552010-12-26 12:10:05 -05002710 spin_unlock_bh(&common->cc_lock);
Bruno Randolff15a4bb2010-12-16 16:22:20 +09002711
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002712 /*
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002713 * Change channels and update the h/w rate map if we're switching;
2714 * e.g. 11a to 11b/g.
2715 *
2716 * We may be doing a reset in response to an ioctl that changes the
2717 * channel so update any state that might change as a result.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002718 *
2719 * XXX needed?
2720 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002721/* ath5k_chan_change(ah, c); */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002722
Pavel Roskine0d687b2011-07-14 20:21:55 -04002723 ath5k_beacon_config(ah);
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002724 /* intrs are enabled by ath5k_beacon_config */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002725
Pavel Roskine0d687b2011-07-14 20:21:55 -04002726 ieee80211_wake_queues(ah->hw);
Bruno Randolf397f3852010-05-19 10:30:49 +09002727
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002728 return 0;
2729err:
2730 return ret;
2731}
2732
Bob Copeland5faaff72010-07-13 11:32:40 -04002733static void ath5k_reset_work(struct work_struct *work)
2734{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002735 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
Bob Copeland5faaff72010-07-13 11:32:40 -04002736 reset_work);
2737
Pavel Roskine0d687b2011-07-14 20:21:55 -04002738 mutex_lock(&ah->lock);
2739 ath5k_reset(ah, NULL, true);
2740 mutex_unlock(&ah->lock);
Bob Copeland5faaff72010-07-13 11:32:40 -04002741}
2742
Pavel Roskin25380d82011-07-07 18:13:42 -04002743static int __devinit
Felix Fietkau132b1c32010-12-02 10:26:56 +01002744ath5k_init(struct ieee80211_hw *hw)
Bob Copeland8a63fac2010-09-17 12:45:07 +09002745{
Felix Fietkau132b1c32010-12-02 10:26:56 +01002746
Pavel Roskine0d687b2011-07-14 20:21:55 -04002747 struct ath5k_hw *ah = hw->priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002748 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
Bruno Randolf925e0b02010-09-17 11:36:35 +09002749 struct ath5k_txq *txq;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002750 u8 mac[ETH_ALEN] = {};
2751 int ret;
2752
Bob Copeland8a63fac2010-09-17 12:45:07 +09002753
2754 /*
2755 * Check if the MAC has multi-rate retry support.
2756 * We do this by trying to setup a fake extended
2757 * descriptor. MACs that don't have support will
2758 * return false w/o doing anything. MACs that do
2759 * support it will return true w/o doing anything.
2760 */
2761 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2762
2763 if (ret < 0)
2764 goto err;
2765 if (ret > 0)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002766 __set_bit(ATH_STAT_MRRETRY, ah->status);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002767
2768 /*
2769 * Collect the channel list. The 802.11 layer
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04002770 * is responsible for filtering this list based
Bob Copeland8a63fac2010-09-17 12:45:07 +09002771 * on settings like the phy mode and regulatory
2772 * domain restrictions.
2773 */
2774 ret = ath5k_setup_bands(hw);
2775 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002776 ATH5K_ERR(ah, "can't get channels\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002777 goto err;
2778 }
2779
Bob Copeland8a63fac2010-09-17 12:45:07 +09002780 /*
2781 * Allocate tx+rx descriptors and populate the lists.
2782 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002783 ret = ath5k_desc_alloc(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002784 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002785 ATH5K_ERR(ah, "can't allocate descriptors\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002786 goto err;
2787 }
2788
2789 /*
2790 * Allocate hardware transmit queues: one queue for
2791 * beacon frames and one data queue for each QoS
2792 * priority. Note that hw functions handle resetting
2793 * these queues at the needed time.
2794 */
2795 ret = ath5k_beaconq_setup(ah);
2796 if (ret < 0) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002797 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002798 goto err_desc;
2799 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04002800 ah->bhalq = ret;
2801 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2802 if (IS_ERR(ah->cabq)) {
2803 ATH5K_ERR(ah, "can't setup cab queue\n");
2804 ret = PTR_ERR(ah->cabq);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002805 goto err_bhal;
2806 }
2807
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002808 /* 5211 and 5212 usually support 10 queues but we better rely on the
2809 * capability information */
2810 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2811 /* This order matches mac80211's queue priority, so we can
2812 * directly use the mac80211 queue number without any mapping */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002813 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002814 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002815 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002816 ret = PTR_ERR(txq);
2817 goto err_queues;
2818 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04002819 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002820 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002821 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002822 ret = PTR_ERR(txq);
2823 goto err_queues;
2824 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04002825 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002826 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002827 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002828 ret = PTR_ERR(txq);
2829 goto err_queues;
2830 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04002831 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002832 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002833 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002834 ret = PTR_ERR(txq);
2835 goto err_queues;
2836 }
2837 hw->queues = 4;
2838 } else {
2839 /* older hardware (5210) can only support one data queue */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002840 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002841 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002842 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002843 ret = PTR_ERR(txq);
2844 goto err_queues;
2845 }
2846 hw->queues = 1;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002847 }
2848
Pavel Roskine0d687b2011-07-14 20:21:55 -04002849 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2850 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
2851 tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah);
2852 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2853 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002854
Pavel Roskine0d687b2011-07-14 20:21:55 -04002855 INIT_WORK(&ah->reset_work, ath5k_reset_work);
2856 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002857
Felix Fietkaufa9bfd62011-04-13 21:56:44 +02002858 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002859 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002860 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002861 goto err_queues;
2862 }
2863
2864 SET_IEEE80211_PERM_ADDR(hw, mac);
2865 /* All MAC address bits matter for ACKs */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002866 ath5k_update_bssid_mask_and_opmode(ah, NULL);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002867
2868 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2869 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2870 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002871 ATH5K_ERR(ah, "can't initialize regulatory system\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002872 goto err_queues;
2873 }
2874
2875 ret = ieee80211_register_hw(hw);
2876 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002877 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002878 goto err_queues;
2879 }
2880
2881 if (!ath_is_world_regd(regulatory))
2882 regulatory_hint(hw->wiphy, regulatory->alpha2);
2883
Pavel Roskine0d687b2011-07-14 20:21:55 -04002884 ath5k_init_leds(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002885
Pavel Roskine0d687b2011-07-14 20:21:55 -04002886 ath5k_sysfs_register(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002887
2888 return 0;
2889err_queues:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002890 ath5k_txq_release(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002891err_bhal:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002892 ath5k_hw_release_tx_queue(ah, ah->bhalq);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002893err_desc:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002894 ath5k_desc_free(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002895err:
2896 return ret;
2897}
2898
Felix Fietkau132b1c32010-12-02 10:26:56 +01002899void
Pavel Roskine0d687b2011-07-14 20:21:55 -04002900ath5k_deinit_softc(struct ath5k_hw *ah)
Bob Copeland8a63fac2010-09-17 12:45:07 +09002901{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002902 struct ieee80211_hw *hw = ah->hw;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002903
2904 /*
2905 * NB: the order of these is important:
2906 * o call the 802.11 layer before detaching ath5k_hw to
2907 * ensure callbacks into the driver to delete global
2908 * key cache entries can be handled
2909 * o reclaim the tx queue data structures after calling
2910 * the 802.11 layer as we'll get called back to reclaim
2911 * node state and potentially want to use them
2912 * o to cleanup the tx queues the hal is called, so detach
2913 * it last
2914 * XXX: ??? detach ath5k_hw ???
2915 * Other than that, it's straightforward...
2916 */
2917 ieee80211_unregister_hw(hw);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002918 ath5k_desc_free(ah);
2919 ath5k_txq_release(ah);
2920 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2921 ath5k_unregister_leds(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002922
Pavel Roskine0d687b2011-07-14 20:21:55 -04002923 ath5k_sysfs_unregister(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002924 /*
2925 * NB: can't reclaim these until after ieee80211_ifdetach
2926 * returns because we'll get called back to reclaim node
2927 * state and potentially want to use them.
2928 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002929 ath5k_hw_deinit(ah);
2930 free_irq(ah->irq, ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002931}
2932
Bruno Randolfcd2c5482010-12-22 19:20:32 +09002933bool
Pavel Roskine0d687b2011-07-14 20:21:55 -04002934ath5k_any_vif_assoc(struct ath5k_hw *ah)
Ben Greearb1ae1ed2010-09-30 12:22:58 -07002935{
Ben Greeare4b0b322011-03-03 14:39:05 -08002936 struct ath5k_vif_iter_data iter_data;
Ben Greearb1ae1ed2010-09-30 12:22:58 -07002937 iter_data.hw_macaddr = NULL;
2938 iter_data.any_assoc = false;
2939 iter_data.need_set_hw_addr = false;
2940 iter_data.found_active = true;
2941
Pavel Roskine0d687b2011-07-14 20:21:55 -04002942 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
Ben Greearb1ae1ed2010-09-30 12:22:58 -07002943 &iter_data);
2944 return iter_data.any_assoc;
2945}
2946
Bruno Randolfcd2c5482010-12-22 19:20:32 +09002947void
Pavel Roskinf5cbc8b2011-06-15 18:03:22 -04002948ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
Martin Xu02969b32008-11-24 10:49:27 +08002949{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002950 struct ath5k_hw *ah = hw->priv;
Martin Xu02969b32008-11-24 10:49:27 +08002951 u32 rfilt;
2952 rfilt = ath5k_hw_get_rx_filter(ah);
2953 if (enable)
2954 rfilt |= AR5K_RX_FILTER_BEACON;
2955 else
2956 rfilt &= ~AR5K_RX_FILTER_BEACON;
2957 ath5k_hw_set_rx_filter(ah, rfilt);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002958 ah->filter_flags = rfilt;
Martin Xu02969b32008-11-24 10:49:27 +08002959}