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Florian Fainelli80105be2014-04-24 18:08:57 -07001/*
2 * Broadcom BCM7xxx System Port Ethernet MAC driver
3 *
4 * Copyright (C) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/netdevice.h>
18#include <linux/etherdevice.h>
19#include <linux/platform_device.h>
20#include <linux/of.h>
21#include <linux/of_net.h>
22#include <linux/of_mdio.h>
23#include <linux/phy.h>
24#include <linux/phy_fixed.h>
Andrew Lunnc6e970a2017-03-28 23:45:06 +020025#include <net/dsa.h>
Florian Fainelli80105be2014-04-24 18:08:57 -070026#include <net/ip.h>
27#include <net/ipv6.h>
28
29#include "bcmsysport.h"
30
31/* I/O accessors register helpers */
32#define BCM_SYSPORT_IO_MACRO(name, offset) \
33static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \
34{ \
Florian Fainellif1dd1992017-08-29 13:35:15 -070035 u32 reg = readl_relaxed(priv->base + offset + off); \
Florian Fainelli80105be2014-04-24 18:08:57 -070036 return reg; \
37} \
38static inline void name##_writel(struct bcm_sysport_priv *priv, \
39 u32 val, u32 off) \
40{ \
Florian Fainellif1dd1992017-08-29 13:35:15 -070041 writel_relaxed(val, priv->base + offset + off); \
Florian Fainelli80105be2014-04-24 18:08:57 -070042} \
43
44BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
45BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET);
46BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET);
Florian Fainelli44a45242017-01-20 11:08:27 -080047BCM_SYSPORT_IO_MACRO(gib, SYS_PORT_GIB_OFFSET);
Florian Fainelli80105be2014-04-24 18:08:57 -070048BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET);
Florian Fainelli80105be2014-04-24 18:08:57 -070049BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET);
50BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET);
51BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET);
52BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET);
53BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET);
54
Florian Fainelli44a45242017-01-20 11:08:27 -080055/* On SYSTEMPORT Lite, any register after RDMA_STATUS has the exact
56 * same layout, except it has been moved by 4 bytes up, *sigh*
57 */
58static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off)
59{
60 if (priv->is_lite && off >= RDMA_STATUS)
61 off += 4;
Florian Fainellif1dd1992017-08-29 13:35:15 -070062 return readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off);
Florian Fainelli44a45242017-01-20 11:08:27 -080063}
64
65static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off)
66{
67 if (priv->is_lite && off >= RDMA_STATUS)
68 off += 4;
Florian Fainellif1dd1992017-08-29 13:35:15 -070069 writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off);
Florian Fainelli44a45242017-01-20 11:08:27 -080070}
71
72static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit)
73{
74 if (!priv->is_lite) {
75 return BIT(bit);
76 } else {
77 if (bit >= ACB_ALGO)
78 return BIT(bit + 1);
79 else
80 return BIT(bit);
81 }
82}
83
Florian Fainelli80105be2014-04-24 18:08:57 -070084/* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
85 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
86 */
87#define BCM_SYSPORT_INTR_L2(which) \
88static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
89 u32 mask) \
90{ \
Florian Fainelli80105be2014-04-24 18:08:57 -070091 priv->irq##which##_mask &= ~(mask); \
Florian Fainelli9a0a5c42016-08-24 14:21:41 -070092 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
Florian Fainelli80105be2014-04-24 18:08:57 -070093} \
94static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
95 u32 mask) \
96{ \
97 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
98 priv->irq##which##_mask |= (mask); \
99} \
100
101BCM_SYSPORT_INTR_L2(0)
102BCM_SYSPORT_INTR_L2(1)
103
104/* Register accesses to GISB/RBUS registers are expensive (few hundred
105 * nanoseconds), so keep the check for 64-bits explicit here to save
106 * one register write per-packet on 32-bits platforms.
107 */
108static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,
109 void __iomem *d,
110 dma_addr_t addr)
111{
112#ifdef CONFIG_PHYS_ADDR_T_64BIT
Florian Fainellif1dd1992017-08-29 13:35:15 -0700113 writel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700114 d + DESC_ADDR_HI_STATUS_LEN);
Florian Fainelli80105be2014-04-24 18:08:57 -0700115#endif
Florian Fainellif1dd1992017-08-29 13:35:15 -0700116 writel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO);
Florian Fainelli80105be2014-04-24 18:08:57 -0700117}
118
119static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700120 struct dma_desc *desc,
121 unsigned int port)
Florian Fainelli80105be2014-04-24 18:08:57 -0700122{
123 /* Ports are latched, so write upper address first */
124 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port));
125 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port));
126}
127
128/* Ethtool operations */
Florian Fainelli80105be2014-04-24 18:08:57 -0700129static int bcm_sysport_set_rx_csum(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700130 netdev_features_t wanted)
Florian Fainelli80105be2014-04-24 18:08:57 -0700131{
132 struct bcm_sysport_priv *priv = netdev_priv(dev);
133 u32 reg;
134
Florian Fainelli9d34c1c2014-07-01 21:08:39 -0700135 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
Florian Fainelli80105be2014-04-24 18:08:57 -0700136 reg = rxchk_readl(priv, RXCHK_CONTROL);
Florian Fainelli9d34c1c2014-07-01 21:08:39 -0700137 if (priv->rx_chk_en)
Florian Fainelli80105be2014-04-24 18:08:57 -0700138 reg |= RXCHK_EN;
139 else
140 reg &= ~RXCHK_EN;
141
142 /* If UniMAC forwards CRC, we need to skip over it to get
143 * a valid CHK bit to be set in the per-packet status word
144 */
Florian Fainelli9d34c1c2014-07-01 21:08:39 -0700145 if (priv->rx_chk_en && priv->crc_fwd)
Florian Fainelli80105be2014-04-24 18:08:57 -0700146 reg |= RXCHK_SKIP_FCS;
147 else
148 reg &= ~RXCHK_SKIP_FCS;
149
Florian Fainellid09d3032014-08-28 15:11:03 -0700150 /* If Broadcom tags are enabled (e.g: using a switch), make
151 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
152 * tag after the Ethernet MAC Source Address.
153 */
154 if (netdev_uses_dsa(dev))
155 reg |= RXCHK_BRCM_TAG_EN;
156 else
157 reg &= ~RXCHK_BRCM_TAG_EN;
158
Florian Fainelli80105be2014-04-24 18:08:57 -0700159 rxchk_writel(priv, reg, RXCHK_CONTROL);
160
161 return 0;
162}
163
164static int bcm_sysport_set_tx_csum(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700165 netdev_features_t wanted)
Florian Fainelli80105be2014-04-24 18:08:57 -0700166{
167 struct bcm_sysport_priv *priv = netdev_priv(dev);
168 u32 reg;
169
170 /* Hardware transmit checksum requires us to enable the Transmit status
171 * block prepended to the packet contents
172 */
173 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
174 reg = tdma_readl(priv, TDMA_CONTROL);
175 if (priv->tsb_en)
Florian Fainelli44a45242017-01-20 11:08:27 -0800176 reg |= tdma_control_bit(priv, TSB_EN);
Florian Fainelli80105be2014-04-24 18:08:57 -0700177 else
Florian Fainelli44a45242017-01-20 11:08:27 -0800178 reg &= ~tdma_control_bit(priv, TSB_EN);
Florian Fainelli80105be2014-04-24 18:08:57 -0700179 tdma_writel(priv, reg, TDMA_CONTROL);
180
181 return 0;
182}
183
184static int bcm_sysport_set_features(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700185 netdev_features_t features)
Florian Fainelli80105be2014-04-24 18:08:57 -0700186{
187 netdev_features_t changed = features ^ dev->features;
188 netdev_features_t wanted = dev->wanted_features;
189 int ret = 0;
190
191 if (changed & NETIF_F_RXCSUM)
192 ret = bcm_sysport_set_rx_csum(dev, wanted);
193 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
194 ret = bcm_sysport_set_tx_csum(dev, wanted);
195
196 return ret;
197}
198
199/* Hardware counters must be kept in sync because the order/offset
200 * is important here (order in structure declaration = order in hardware)
201 */
202static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = {
203 /* general stats */
kiki good10377ba2017-08-04 00:07:45 +0100204 STAT_NETDEV64(rx_packets),
205 STAT_NETDEV64(tx_packets),
206 STAT_NETDEV64(rx_bytes),
207 STAT_NETDEV64(tx_bytes),
Florian Fainelli80105be2014-04-24 18:08:57 -0700208 STAT_NETDEV(rx_errors),
209 STAT_NETDEV(tx_errors),
210 STAT_NETDEV(rx_dropped),
211 STAT_NETDEV(tx_dropped),
212 STAT_NETDEV(multicast),
213 /* UniMAC RSV counters */
214 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
215 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
216 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
217 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
218 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
219 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
220 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
221 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
222 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
223 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
224 STAT_MIB_RX("rx_pkts", mib.rx.pkt),
225 STAT_MIB_RX("rx_bytes", mib.rx.bytes),
226 STAT_MIB_RX("rx_multicast", mib.rx.mca),
227 STAT_MIB_RX("rx_broadcast", mib.rx.bca),
228 STAT_MIB_RX("rx_fcs", mib.rx.fcs),
229 STAT_MIB_RX("rx_control", mib.rx.cf),
230 STAT_MIB_RX("rx_pause", mib.rx.pf),
231 STAT_MIB_RX("rx_unknown", mib.rx.uo),
232 STAT_MIB_RX("rx_align", mib.rx.aln),
233 STAT_MIB_RX("rx_outrange", mib.rx.flr),
234 STAT_MIB_RX("rx_code", mib.rx.cde),
235 STAT_MIB_RX("rx_carrier", mib.rx.fcr),
236 STAT_MIB_RX("rx_oversize", mib.rx.ovr),
237 STAT_MIB_RX("rx_jabber", mib.rx.jbr),
238 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
239 STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
240 STAT_MIB_RX("rx_unicast", mib.rx.uc),
241 STAT_MIB_RX("rx_ppp", mib.rx.ppp),
242 STAT_MIB_RX("rx_crc", mib.rx.rcrc),
243 /* UniMAC TSV counters */
244 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
245 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
246 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
247 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
248 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
249 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
250 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
251 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
252 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
253 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
254 STAT_MIB_TX("tx_pkts", mib.tx.pkts),
255 STAT_MIB_TX("tx_multicast", mib.tx.mca),
256 STAT_MIB_TX("tx_broadcast", mib.tx.bca),
257 STAT_MIB_TX("tx_pause", mib.tx.pf),
258 STAT_MIB_TX("tx_control", mib.tx.cf),
259 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
260 STAT_MIB_TX("tx_oversize", mib.tx.ovr),
261 STAT_MIB_TX("tx_defer", mib.tx.drf),
262 STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
263 STAT_MIB_TX("tx_single_col", mib.tx.scl),
264 STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
265 STAT_MIB_TX("tx_late_col", mib.tx.lcl),
266 STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
267 STAT_MIB_TX("tx_frags", mib.tx.frg),
268 STAT_MIB_TX("tx_total_col", mib.tx.ncl),
269 STAT_MIB_TX("tx_jabber", mib.tx.jbr),
270 STAT_MIB_TX("tx_bytes", mib.tx.bytes),
271 STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
272 STAT_MIB_TX("tx_unicast", mib.tx.uc),
273 /* UniMAC RUNT counters */
274 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
275 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
276 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
277 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
278 /* RXCHK misc statistics */
279 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
280 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700281 RXCHK_OTHER_DISC_CNTR),
Florian Fainelli80105be2014-04-24 18:08:57 -0700282 /* RBUF misc statistics */
283 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
284 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
Florian Fainelli55ff4ea2015-02-28 18:09:17 -0800285 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
286 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
287 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
Florian Fainelli30defeb2017-03-23 10:36:46 -0700288 /* Per TX-queue statistics are dynamically appended */
Florian Fainelli80105be2014-04-24 18:08:57 -0700289};
290
291#define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats)
292
293static void bcm_sysport_get_drvinfo(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700294 struct ethtool_drvinfo *info)
Florian Fainelli80105be2014-04-24 18:08:57 -0700295{
296 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
297 strlcpy(info->version, "0.1", sizeof(info->version));
298 strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
Florian Fainelli80105be2014-04-24 18:08:57 -0700299}
300
301static u32 bcm_sysport_get_msglvl(struct net_device *dev)
302{
303 struct bcm_sysport_priv *priv = netdev_priv(dev);
304
305 return priv->msg_enable;
306}
307
308static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable)
309{
310 struct bcm_sysport_priv *priv = netdev_priv(dev);
311
312 priv->msg_enable = enable;
313}
314
Florian Fainelli44a45242017-01-20 11:08:27 -0800315static inline bool bcm_sysport_lite_stat_valid(enum bcm_sysport_stat_type type)
316{
317 switch (type) {
318 case BCM_SYSPORT_STAT_NETDEV:
kiki good10377ba2017-08-04 00:07:45 +0100319 case BCM_SYSPORT_STAT_NETDEV64:
Florian Fainelli44a45242017-01-20 11:08:27 -0800320 case BCM_SYSPORT_STAT_RXCHK:
321 case BCM_SYSPORT_STAT_RBUF:
322 case BCM_SYSPORT_STAT_SOFT:
323 return true;
324 default:
325 return false;
326 }
327}
328
Florian Fainelli80105be2014-04-24 18:08:57 -0700329static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set)
330{
Florian Fainelli44a45242017-01-20 11:08:27 -0800331 struct bcm_sysport_priv *priv = netdev_priv(dev);
332 const struct bcm_sysport_stats *s;
333 unsigned int i, j;
334
Florian Fainelli80105be2014-04-24 18:08:57 -0700335 switch (string_set) {
336 case ETH_SS_STATS:
Florian Fainelli44a45242017-01-20 11:08:27 -0800337 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
338 s = &bcm_sysport_gstrings_stats[i];
339 if (priv->is_lite &&
340 !bcm_sysport_lite_stat_valid(s->type))
341 continue;
342 j++;
343 }
Florian Fainelli30defeb2017-03-23 10:36:46 -0700344 /* Include per-queue statistics */
345 return j + dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT;
Florian Fainelli80105be2014-04-24 18:08:57 -0700346 default:
347 return -EOPNOTSUPP;
348 }
349}
350
351static void bcm_sysport_get_strings(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700352 u32 stringset, u8 *data)
Florian Fainelli80105be2014-04-24 18:08:57 -0700353{
Florian Fainelli44a45242017-01-20 11:08:27 -0800354 struct bcm_sysport_priv *priv = netdev_priv(dev);
355 const struct bcm_sysport_stats *s;
Florian Fainelli30defeb2017-03-23 10:36:46 -0700356 char buf[128];
Florian Fainelli44a45242017-01-20 11:08:27 -0800357 int i, j;
Florian Fainelli80105be2014-04-24 18:08:57 -0700358
359 switch (stringset) {
360 case ETH_SS_STATS:
Florian Fainelli44a45242017-01-20 11:08:27 -0800361 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
362 s = &bcm_sysport_gstrings_stats[i];
363 if (priv->is_lite &&
364 !bcm_sysport_lite_stat_valid(s->type))
365 continue;
366
367 memcpy(data + j * ETH_GSTRING_LEN, s->stat_string,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700368 ETH_GSTRING_LEN);
Florian Fainelli44a45242017-01-20 11:08:27 -0800369 j++;
Florian Fainelli80105be2014-04-24 18:08:57 -0700370 }
Florian Fainelli30defeb2017-03-23 10:36:46 -0700371
372 for (i = 0; i < dev->num_tx_queues; i++) {
373 snprintf(buf, sizeof(buf), "txq%d_packets", i);
374 memcpy(data + j * ETH_GSTRING_LEN, buf,
375 ETH_GSTRING_LEN);
376 j++;
377
378 snprintf(buf, sizeof(buf), "txq%d_bytes", i);
379 memcpy(data + j * ETH_GSTRING_LEN, buf,
380 ETH_GSTRING_LEN);
381 j++;
382 }
Florian Fainelli80105be2014-04-24 18:08:57 -0700383 break;
384 default:
385 break;
386 }
387}
388
389static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv)
390{
391 int i, j = 0;
392
393 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
394 const struct bcm_sysport_stats *s;
395 u8 offset = 0;
396 u32 val = 0;
397 char *p;
398
399 s = &bcm_sysport_gstrings_stats[i];
400 switch (s->type) {
401 case BCM_SYSPORT_STAT_NETDEV:
kiki good10377ba2017-08-04 00:07:45 +0100402 case BCM_SYSPORT_STAT_NETDEV64:
Florian Fainelli55ff4ea2015-02-28 18:09:17 -0800403 case BCM_SYSPORT_STAT_SOFT:
Florian Fainelli80105be2014-04-24 18:08:57 -0700404 continue;
405 case BCM_SYSPORT_STAT_MIB_RX:
406 case BCM_SYSPORT_STAT_MIB_TX:
407 case BCM_SYSPORT_STAT_RUNT:
Florian Fainelli44a45242017-01-20 11:08:27 -0800408 if (priv->is_lite)
409 continue;
410
Florian Fainelli80105be2014-04-24 18:08:57 -0700411 if (s->type != BCM_SYSPORT_STAT_MIB_RX)
412 offset = UMAC_MIB_STAT_OFFSET;
413 val = umac_readl(priv, UMAC_MIB_START + j + offset);
414 break;
415 case BCM_SYSPORT_STAT_RXCHK:
416 val = rxchk_readl(priv, s->reg_offset);
417 if (val == ~0)
418 rxchk_writel(priv, 0, s->reg_offset);
419 break;
420 case BCM_SYSPORT_STAT_RBUF:
421 val = rbuf_readl(priv, s->reg_offset);
422 if (val == ~0)
423 rbuf_writel(priv, 0, s->reg_offset);
424 break;
425 }
426
427 j += s->stat_sizeof;
428 p = (char *)priv + s->stat_offset;
429 *(u32 *)p = val;
430 }
431
432 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
433}
434
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700435static void bcm_sysport_update_tx_stats(struct bcm_sysport_priv *priv,
436 u64 *tx_bytes, u64 *tx_packets)
437{
438 struct bcm_sysport_tx_ring *ring;
439 u64 bytes = 0, packets = 0;
440 unsigned int start;
441 unsigned int q;
442
443 for (q = 0; q < priv->netdev->num_tx_queues; q++) {
444 ring = &priv->tx_rings[q];
445 do {
446 start = u64_stats_fetch_begin_irq(&priv->syncp);
447 bytes = ring->bytes;
448 packets = ring->packets;
449 } while (u64_stats_fetch_retry_irq(&priv->syncp, start));
450
451 *tx_bytes += bytes;
452 *tx_packets += packets;
453 }
454}
455
Florian Fainelli80105be2014-04-24 18:08:57 -0700456static void bcm_sysport_get_stats(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700457 struct ethtool_stats *stats, u64 *data)
Florian Fainelli80105be2014-04-24 18:08:57 -0700458{
459 struct bcm_sysport_priv *priv = netdev_priv(dev);
kiki good10377ba2017-08-04 00:07:45 +0100460 struct bcm_sysport_stats64 *stats64 = &priv->stats64;
461 struct u64_stats_sync *syncp = &priv->syncp;
Florian Fainelli30defeb2017-03-23 10:36:46 -0700462 struct bcm_sysport_tx_ring *ring;
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700463 u64 tx_bytes = 0, tx_packets = 0;
kiki good10377ba2017-08-04 00:07:45 +0100464 unsigned int start;
Florian Fainelli44a45242017-01-20 11:08:27 -0800465 int i, j;
Florian Fainelli80105be2014-04-24 18:08:57 -0700466
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700467 if (netif_running(dev)) {
Florian Fainelli80105be2014-04-24 18:08:57 -0700468 bcm_sysport_update_mib_counters(priv);
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700469 bcm_sysport_update_tx_stats(priv, &tx_bytes, &tx_packets);
470 stats64->tx_bytes = tx_bytes;
471 stats64->tx_packets = tx_packets;
472 }
Florian Fainelli80105be2014-04-24 18:08:57 -0700473
Florian Fainelli44a45242017-01-20 11:08:27 -0800474 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
Florian Fainelli80105be2014-04-24 18:08:57 -0700475 const struct bcm_sysport_stats *s;
476 char *p;
477
478 s = &bcm_sysport_gstrings_stats[i];
479 if (s->type == BCM_SYSPORT_STAT_NETDEV)
480 p = (char *)&dev->stats;
kiki good10377ba2017-08-04 00:07:45 +0100481 else if (s->type == BCM_SYSPORT_STAT_NETDEV64)
482 p = (char *)stats64;
Florian Fainelli80105be2014-04-24 18:08:57 -0700483 else
484 p = (char *)priv;
kiki good10377ba2017-08-04 00:07:45 +0100485
Florian Fainelli50ddfba2017-08-08 14:45:09 -0700486 if (priv->is_lite && !bcm_sysport_lite_stat_valid(s->type))
487 continue;
Florian Fainelli80105be2014-04-24 18:08:57 -0700488 p += s->stat_offset;
kiki good10377ba2017-08-04 00:07:45 +0100489
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700490 if (s->stat_sizeof == sizeof(u64) &&
491 s->type == BCM_SYSPORT_STAT_NETDEV64) {
kiki good10377ba2017-08-04 00:07:45 +0100492 do {
493 start = u64_stats_fetch_begin_irq(syncp);
494 data[i] = *(u64 *)p;
495 } while (u64_stats_fetch_retry_irq(syncp, start));
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700496 } else
kiki good10377ba2017-08-04 00:07:45 +0100497 data[i] = *(u32 *)p;
Florian Fainelli44a45242017-01-20 11:08:27 -0800498 j++;
Florian Fainelli80105be2014-04-24 18:08:57 -0700499 }
Florian Fainelli30defeb2017-03-23 10:36:46 -0700500
501 /* For SYSTEMPORT Lite since we have holes in our statistics, j would
502 * be equal to BCM_SYSPORT_STATS_LEN at the end of the loop, but it
503 * needs to point to how many total statistics we have minus the
504 * number of per TX queue statistics
505 */
506 j = bcm_sysport_get_sset_count(dev, ETH_SS_STATS) -
507 dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT;
508
509 for (i = 0; i < dev->num_tx_queues; i++) {
510 ring = &priv->tx_rings[i];
511 data[j] = ring->packets;
512 j++;
513 data[j] = ring->bytes;
514 j++;
515 }
Florian Fainelli80105be2014-04-24 18:08:57 -0700516}
517
Florian Fainelli83e82f42014-07-01 21:08:40 -0700518static void bcm_sysport_get_wol(struct net_device *dev,
519 struct ethtool_wolinfo *wol)
520{
521 struct bcm_sysport_priv *priv = netdev_priv(dev);
522 u32 reg;
523
524 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE;
525 wol->wolopts = priv->wolopts;
526
527 if (!(priv->wolopts & WAKE_MAGICSECURE))
528 return;
529
530 /* Return the programmed SecureOn password */
531 reg = umac_readl(priv, UMAC_PSW_MS);
532 put_unaligned_be16(reg, &wol->sopass[0]);
533 reg = umac_readl(priv, UMAC_PSW_LS);
534 put_unaligned_be32(reg, &wol->sopass[2]);
535}
536
537static int bcm_sysport_set_wol(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700538 struct ethtool_wolinfo *wol)
Florian Fainelli83e82f42014-07-01 21:08:40 -0700539{
540 struct bcm_sysport_priv *priv = netdev_priv(dev);
541 struct device *kdev = &priv->pdev->dev;
542 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE;
543
544 if (!device_can_wakeup(kdev))
545 return -ENOTSUPP;
546
547 if (wol->wolopts & ~supported)
548 return -EINVAL;
549
550 /* Program the SecureOn password */
551 if (wol->wolopts & WAKE_MAGICSECURE) {
552 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]),
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700553 UMAC_PSW_MS);
Florian Fainelli83e82f42014-07-01 21:08:40 -0700554 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]),
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700555 UMAC_PSW_LS);
Florian Fainelli83e82f42014-07-01 21:08:40 -0700556 }
557
558 /* Flag the device and relevant IRQ as wakeup capable */
559 if (wol->wolopts) {
560 device_set_wakeup_enable(kdev, 1);
Florian Fainelli61b423a2014-10-10 10:51:54 -0700561 if (priv->wol_irq_disabled)
562 enable_irq_wake(priv->wol_irq);
Florian Fainelli83e82f42014-07-01 21:08:40 -0700563 priv->wol_irq_disabled = 0;
564 } else {
565 device_set_wakeup_enable(kdev, 0);
566 /* Avoid unbalanced disable_irq_wake calls */
567 if (!priv->wol_irq_disabled)
568 disable_irq_wake(priv->wol_irq);
569 priv->wol_irq_disabled = 1;
570 }
571
572 priv->wolopts = wol->wolopts;
573
574 return 0;
575}
576
Florian Fainellia8cdfbd2018-03-28 15:15:37 -0700577static void bcm_sysport_set_rx_coalesce(struct bcm_sysport_priv *priv,
578 u32 usecs, u32 pkts)
Florian Fainellib6e0e872018-03-22 18:19:32 -0700579{
580 u32 reg;
581
582 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
583 reg &= ~(RDMA_INTR_THRESH_MASK |
584 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT);
Florian Fainellia8cdfbd2018-03-28 15:15:37 -0700585 reg |= pkts;
586 reg |= DIV_ROUND_UP(usecs * 1000, 8192) << RDMA_TIMEOUT_SHIFT;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700587 rdma_writel(priv, reg, RDMA_MBDONE_INTR);
588}
589
Florian Fainellifd41f2b2018-03-28 15:15:36 -0700590static void bcm_sysport_set_tx_coalesce(struct bcm_sysport_tx_ring *ring,
591 struct ethtool_coalesce *ec)
Florian Fainellib6e0e872018-03-22 18:19:32 -0700592{
593 struct bcm_sysport_priv *priv = ring->priv;
594 u32 reg;
595
596 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(ring->index));
597 reg &= ~(RING_INTR_THRESH_MASK |
598 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
Florian Fainellifd41f2b2018-03-28 15:15:36 -0700599 reg |= ec->tx_max_coalesced_frames;
600 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
Florian Fainellib6e0e872018-03-22 18:19:32 -0700601 RING_TIMEOUT_SHIFT;
602 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(ring->index));
603}
604
Florian Fainellib1a15e82015-05-11 15:12:41 -0700605static int bcm_sysport_get_coalesce(struct net_device *dev,
606 struct ethtool_coalesce *ec)
607{
608 struct bcm_sysport_priv *priv = netdev_priv(dev);
609 u32 reg;
610
611 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
612
613 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
614 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
615
Florian Fainellid0634862015-05-11 15:12:42 -0700616 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
617
618 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000;
619 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700620 ec->use_adaptive_rx_coalesce = priv->dim.use_dim;
Florian Fainellid0634862015-05-11 15:12:42 -0700621
Florian Fainellib1a15e82015-05-11 15:12:41 -0700622 return 0;
623}
624
625static int bcm_sysport_set_coalesce(struct net_device *dev,
626 struct ethtool_coalesce *ec)
627{
628 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainellia8cdfbd2018-03-28 15:15:37 -0700629 struct net_dim_cq_moder moder;
630 u32 usecs, pkts;
Florian Fainellib1a15e82015-05-11 15:12:41 -0700631 unsigned int i;
Florian Fainellib1a15e82015-05-11 15:12:41 -0700632
Florian Fainellid0634862015-05-11 15:12:42 -0700633 /* Base system clock is 125Mhz, DMA timeout is this reference clock
634 * divided by 1024, which yield roughly 8.192 us, our maximum value has
635 * to fit in the RING_TIMEOUT_MASK (16 bits).
Florian Fainellib1a15e82015-05-11 15:12:41 -0700636 */
637 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
Florian Fainellid0634862015-05-11 15:12:42 -0700638 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 ||
639 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK ||
640 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1)
Florian Fainellib1a15e82015-05-11 15:12:41 -0700641 return -EINVAL;
642
Florian Fainellid0634862015-05-11 15:12:42 -0700643 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) ||
Florian Fainellifd41f2b2018-03-28 15:15:36 -0700644 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) ||
645 ec->use_adaptive_tx_coalesce)
Florian Fainellib1a15e82015-05-11 15:12:41 -0700646 return -EINVAL;
647
Florian Fainellifd41f2b2018-03-28 15:15:36 -0700648 for (i = 0; i < dev->num_tx_queues; i++)
649 bcm_sysport_set_tx_coalesce(&priv->tx_rings[i], ec);
Florian Fainellib1a15e82015-05-11 15:12:41 -0700650
Florian Fainellia8cdfbd2018-03-28 15:15:37 -0700651 priv->rx_coalesce_usecs = ec->rx_coalesce_usecs;
652 priv->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
653 usecs = priv->rx_coalesce_usecs;
654 pkts = priv->rx_max_coalesced_frames;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700655
Florian Fainellia8cdfbd2018-03-28 15:15:37 -0700656 if (ec->use_adaptive_rx_coalesce && !priv->dim.use_dim) {
657 moder = net_dim_get_def_profile(priv->dim.dim.mode);
658 usecs = moder.usec;
659 pkts = moder.pkts;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700660 }
Florian Fainellia8cdfbd2018-03-28 15:15:37 -0700661
Florian Fainellib6e0e872018-03-22 18:19:32 -0700662 priv->dim.use_dim = ec->use_adaptive_rx_coalesce;
Florian Fainellia8cdfbd2018-03-28 15:15:37 -0700663
664 /* Apply desired coalescing parameters */
665 bcm_sysport_set_rx_coalesce(priv, usecs, pkts);
Florian Fainellid0634862015-05-11 15:12:42 -0700666
Florian Fainellib1a15e82015-05-11 15:12:41 -0700667 return 0;
668}
669
Florian Fainelli80105be2014-04-24 18:08:57 -0700670static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
671{
Florian Fainellic45182e2017-08-24 15:20:41 -0700672 dev_consume_skb_any(cb->skb);
Florian Fainelli80105be2014-04-24 18:08:57 -0700673 cb->skb = NULL;
674 dma_unmap_addr_set(cb, dma_addr, 0);
675}
676
Florian Fainellic73b0182015-05-28 15:24:43 -0700677static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv,
678 struct bcm_sysport_cb *cb)
Florian Fainelli80105be2014-04-24 18:08:57 -0700679{
680 struct device *kdev = &priv->pdev->dev;
681 struct net_device *ndev = priv->netdev;
Florian Fainellic73b0182015-05-28 15:24:43 -0700682 struct sk_buff *skb, *rx_skb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700683 dma_addr_t mapping;
Florian Fainelli80105be2014-04-24 18:08:57 -0700684
Florian Fainellic73b0182015-05-28 15:24:43 -0700685 /* Allocate a new SKB for a new packet */
686 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH);
687 if (!skb) {
688 priv->mib.alloc_rx_buff_failed++;
Florian Fainelli80105be2014-04-24 18:08:57 -0700689 netif_err(priv, rx_err, ndev, "SKB alloc failed\n");
Florian Fainellic73b0182015-05-28 15:24:43 -0700690 return NULL;
Florian Fainelli80105be2014-04-24 18:08:57 -0700691 }
692
Florian Fainellic73b0182015-05-28 15:24:43 -0700693 mapping = dma_map_single(kdev, skb->data,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700694 RX_BUF_LENGTH, DMA_FROM_DEVICE);
Florian Fainellic73b0182015-05-28 15:24:43 -0700695 if (dma_mapping_error(kdev, mapping)) {
Florian Fainelli60b4ea12014-11-19 10:29:55 -0800696 priv->mib.rx_dma_failed++;
Florian Fainellic73b0182015-05-28 15:24:43 -0700697 dev_kfree_skb_any(skb);
Florian Fainelli80105be2014-04-24 18:08:57 -0700698 netif_err(priv, rx_err, ndev, "DMA mapping failure\n");
Florian Fainellic73b0182015-05-28 15:24:43 -0700699 return NULL;
Florian Fainelli80105be2014-04-24 18:08:57 -0700700 }
701
Florian Fainellic73b0182015-05-28 15:24:43 -0700702 /* Grab the current SKB on the ring */
703 rx_skb = cb->skb;
704 if (likely(rx_skb))
705 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
706 RX_BUF_LENGTH, DMA_FROM_DEVICE);
707
708 /* Put the new SKB on the ring */
709 cb->skb = skb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700710 dma_unmap_addr_set(cb, dma_addr, mapping);
Florian Fainellibaf387a2015-05-28 15:24:42 -0700711 dma_desc_set_addr(priv, cb->bd_addr, mapping);
Florian Fainelli80105be2014-04-24 18:08:57 -0700712
713 netif_dbg(priv, rx_status, ndev, "RX refill\n");
714
Florian Fainellic73b0182015-05-28 15:24:43 -0700715 /* Return the current SKB to the caller */
716 return rx_skb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700717}
718
719static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv)
720{
721 struct bcm_sysport_cb *cb;
Florian Fainellic73b0182015-05-28 15:24:43 -0700722 struct sk_buff *skb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700723 unsigned int i;
724
725 for (i = 0; i < priv->num_rx_bds; i++) {
Florian Fainellibaf387a2015-05-28 15:24:42 -0700726 cb = &priv->rx_cbs[i];
Florian Fainellic73b0182015-05-28 15:24:43 -0700727 skb = bcm_sysport_rx_refill(priv, cb);
728 if (skb)
729 dev_kfree_skb(skb);
730 if (!cb->skb)
731 return -ENOMEM;
Florian Fainelli80105be2014-04-24 18:08:57 -0700732 }
733
Florian Fainellic73b0182015-05-28 15:24:43 -0700734 return 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700735}
736
737/* Poll the hardware for up to budget packets to process */
738static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv,
739 unsigned int budget)
740{
kiki good10377ba2017-08-04 00:07:45 +0100741 struct bcm_sysport_stats64 *stats64 = &priv->stats64;
Florian Fainelli80105be2014-04-24 18:08:57 -0700742 struct net_device *ndev = priv->netdev;
743 unsigned int processed = 0, to_process;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700744 unsigned int processed_bytes = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700745 struct bcm_sysport_cb *cb;
746 struct sk_buff *skb;
747 unsigned int p_index;
748 u16 len, status;
Paul Gortmaker3afc5572014-05-30 15:39:30 -0400749 struct bcm_rsb *rsb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700750
Florian Fainelli6baa7852017-03-23 10:36:47 -0700751 /* Clear status before servicing to reduce spurious interrupts */
752 intrl2_0_writel(priv, INTRL2_0_RDMA_MBDONE, INTRL2_CPU_CLEAR);
753
Florian Fainelli44a45242017-01-20 11:08:27 -0800754 /* Determine how much we should process since last call, SYSTEMPORT Lite
755 * groups the producer and consumer indexes into the same 32-bit
756 * which we access using RDMA_CONS_INDEX
757 */
758 if (!priv->is_lite)
759 p_index = rdma_readl(priv, RDMA_PROD_INDEX);
760 else
761 p_index = rdma_readl(priv, RDMA_CONS_INDEX);
Florian Fainelli80105be2014-04-24 18:08:57 -0700762 p_index &= RDMA_PROD_INDEX_MASK;
763
Florian Fainellie9d7af72017-03-23 10:36:48 -0700764 to_process = (p_index - priv->rx_c_index) & RDMA_CONS_INDEX_MASK;
Florian Fainelli80105be2014-04-24 18:08:57 -0700765
766 netif_dbg(priv, rx_status, ndev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700767 "p_index=%d rx_c_index=%d to_process=%d\n",
768 p_index, priv->rx_c_index, to_process);
Florian Fainelli80105be2014-04-24 18:08:57 -0700769
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700770 while ((processed < to_process) && (processed < budget)) {
Florian Fainelli80105be2014-04-24 18:08:57 -0700771 cb = &priv->rx_cbs[priv->rx_read_ptr];
Florian Fainellic73b0182015-05-28 15:24:43 -0700772 skb = bcm_sysport_rx_refill(priv, cb);
Florian Fainellife24ba02014-09-08 11:37:51 -0700773
Florian Fainellife24ba02014-09-08 11:37:51 -0700774
775 /* We do not have a backing SKB, so we do not a corresponding
776 * DMA mapping for this incoming packet since
777 * bcm_sysport_rx_refill always either has both skb and mapping
778 * or none.
779 */
780 if (unlikely(!skb)) {
781 netif_err(priv, rx_err, ndev, "out of memory!\n");
782 ndev->stats.rx_dropped++;
783 ndev->stats.rx_errors++;
Florian Fainellic73b0182015-05-28 15:24:43 -0700784 goto next;
Florian Fainellife24ba02014-09-08 11:37:51 -0700785 }
786
Florian Fainelli80105be2014-04-24 18:08:57 -0700787 /* Extract the Receive Status Block prepended */
Paul Gortmaker3afc5572014-05-30 15:39:30 -0400788 rsb = (struct bcm_rsb *)skb->data;
Florian Fainelli80105be2014-04-24 18:08:57 -0700789 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK;
790 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) &
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700791 DESC_STATUS_MASK;
Florian Fainelli80105be2014-04-24 18:08:57 -0700792
Florian Fainelli80105be2014-04-24 18:08:57 -0700793 netif_dbg(priv, rx_status, ndev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700794 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
795 p_index, priv->rx_c_index, priv->rx_read_ptr,
796 len, status);
Florian Fainelli80105be2014-04-24 18:08:57 -0700797
Florian Fainelli25977ac2015-05-28 15:24:44 -0700798 if (unlikely(len > RX_BUF_LENGTH)) {
799 netif_err(priv, rx_status, ndev, "oversized packet\n");
800 ndev->stats.rx_length_errors++;
801 ndev->stats.rx_errors++;
802 dev_kfree_skb_any(skb);
803 goto next;
804 }
805
Florian Fainelli80105be2014-04-24 18:08:57 -0700806 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
807 netif_err(priv, rx_status, ndev, "fragmented packet!\n");
808 ndev->stats.rx_dropped++;
809 ndev->stats.rx_errors++;
Florian Fainellic73b0182015-05-28 15:24:43 -0700810 dev_kfree_skb_any(skb);
811 goto next;
Florian Fainelli80105be2014-04-24 18:08:57 -0700812 }
813
814 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) {
815 netif_err(priv, rx_err, ndev, "error packet\n");
Florian Fainelliad51c612014-06-05 10:22:16 -0700816 if (status & RX_STATUS_OVFLOW)
Florian Fainelli80105be2014-04-24 18:08:57 -0700817 ndev->stats.rx_over_errors++;
818 ndev->stats.rx_dropped++;
819 ndev->stats.rx_errors++;
Florian Fainellic73b0182015-05-28 15:24:43 -0700820 dev_kfree_skb_any(skb);
821 goto next;
Florian Fainelli80105be2014-04-24 18:08:57 -0700822 }
823
824 skb_put(skb, len);
825
826 /* Hardware validated our checksum */
827 if (likely(status & DESC_L4_CSUM))
828 skb->ip_summed = CHECKSUM_UNNECESSARY;
829
Florian Fainellie0ea05d2014-06-05 10:22:17 -0700830 /* Hardware pre-pends packets with 2bytes before Ethernet
831 * header plus we have the Receive Status Block, strip off all
832 * of this from the SKB.
Florian Fainelli80105be2014-04-24 18:08:57 -0700833 */
834 skb_pull(skb, sizeof(*rsb) + 2);
835 len -= (sizeof(*rsb) + 2);
Florian Fainellib6e0e872018-03-22 18:19:32 -0700836 processed_bytes += len;
Florian Fainelli80105be2014-04-24 18:08:57 -0700837
838 /* UniMAC may forward CRC */
839 if (priv->crc_fwd) {
840 skb_trim(skb, len - ETH_FCS_LEN);
841 len -= ETH_FCS_LEN;
842 }
843
844 skb->protocol = eth_type_trans(skb, ndev);
845 ndev->stats.rx_packets++;
846 ndev->stats.rx_bytes += len;
kiki good10377ba2017-08-04 00:07:45 +0100847 u64_stats_update_begin(&priv->syncp);
848 stats64->rx_packets++;
849 stats64->rx_bytes += len;
850 u64_stats_update_end(&priv->syncp);
Florian Fainelli80105be2014-04-24 18:08:57 -0700851
852 napi_gro_receive(&priv->napi, skb);
Florian Fainellic73b0182015-05-28 15:24:43 -0700853next:
854 processed++;
855 priv->rx_read_ptr++;
856
857 if (priv->rx_read_ptr == priv->num_rx_bds)
858 priv->rx_read_ptr = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700859 }
860
Florian Fainellib6e0e872018-03-22 18:19:32 -0700861 priv->dim.packets = processed;
862 priv->dim.bytes = processed_bytes;
863
Florian Fainelli80105be2014-04-24 18:08:57 -0700864 return processed;
865}
866
Florian Fainelli30defeb2017-03-23 10:36:46 -0700867static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_tx_ring *ring,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700868 struct bcm_sysport_cb *cb,
869 unsigned int *bytes_compl,
870 unsigned int *pkts_compl)
Florian Fainelli80105be2014-04-24 18:08:57 -0700871{
Florian Fainelli30defeb2017-03-23 10:36:46 -0700872 struct bcm_sysport_priv *priv = ring->priv;
Florian Fainelli80105be2014-04-24 18:08:57 -0700873 struct device *kdev = &priv->pdev->dev;
Florian Fainelli80105be2014-04-24 18:08:57 -0700874
875 if (cb->skb) {
Florian Fainelli80105be2014-04-24 18:08:57 -0700876 *bytes_compl += cb->skb->len;
877 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700878 dma_unmap_len(cb, dma_len),
879 DMA_TO_DEVICE);
Florian Fainelli80105be2014-04-24 18:08:57 -0700880 (*pkts_compl)++;
881 bcm_sysport_free_cb(cb);
882 /* SKB fragment */
883 } else if (dma_unmap_addr(cb, dma_addr)) {
kiki good10377ba2017-08-04 00:07:45 +0100884 *bytes_compl += dma_unmap_len(cb, dma_len);
Florian Fainelli80105be2014-04-24 18:08:57 -0700885 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr),
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700886 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE);
Florian Fainelli80105be2014-04-24 18:08:57 -0700887 dma_unmap_addr_set(cb, dma_addr, 0);
888 }
889}
890
891/* Reclaim queued SKBs for transmission completion, lockless version */
892static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
893 struct bcm_sysport_tx_ring *ring)
894{
Florian Fainelli80105be2014-04-24 18:08:57 -0700895 unsigned int pkts_compl = 0, bytes_compl = 0;
kiki good10377ba2017-08-04 00:07:45 +0100896 struct net_device *ndev = priv->netdev;
Florian Fainelli484d8022018-03-13 14:45:07 -0700897 unsigned int txbds_processed = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700898 struct bcm_sysport_cb *cb;
Florian Fainelli484d8022018-03-13 14:45:07 -0700899 unsigned int txbds_ready;
900 unsigned int c_index;
Florian Fainelli80105be2014-04-24 18:08:57 -0700901 u32 hw_ind;
902
Florian Fainelli6baa7852017-03-23 10:36:47 -0700903 /* Clear status before servicing to reduce spurious interrupts */
904 if (!ring->priv->is_lite)
905 intrl2_1_writel(ring->priv, BIT(ring->index), INTRL2_CPU_CLEAR);
906 else
907 intrl2_0_writel(ring->priv, BIT(ring->index +
908 INTRL2_0_TDMA_MBDONE_SHIFT), INTRL2_CPU_CLEAR);
909
Florian Fainelli80105be2014-04-24 18:08:57 -0700910 /* Compute how many descriptors have been processed since last call */
911 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
912 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
Florian Fainelli484d8022018-03-13 14:45:07 -0700913 txbds_ready = (c_index - ring->c_index) & RING_CONS_INDEX_MASK;
Florian Fainelli80105be2014-04-24 18:08:57 -0700914
915 netif_dbg(priv, tx_done, ndev,
Florian Fainelli484d8022018-03-13 14:45:07 -0700916 "ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
917 ring->index, ring->c_index, c_index, txbds_ready);
Florian Fainelli80105be2014-04-24 18:08:57 -0700918
Florian Fainelli484d8022018-03-13 14:45:07 -0700919 while (txbds_processed < txbds_ready) {
920 cb = &ring->cbs[ring->clean_index];
Florian Fainelli30defeb2017-03-23 10:36:46 -0700921 bcm_sysport_tx_reclaim_one(ring, cb, &bytes_compl, &pkts_compl);
Florian Fainelli80105be2014-04-24 18:08:57 -0700922
923 ring->desc_count++;
Florian Fainelli484d8022018-03-13 14:45:07 -0700924 txbds_processed++;
925
926 if (likely(ring->clean_index < ring->size - 1))
927 ring->clean_index++;
928 else
929 ring->clean_index = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700930 }
931
kiki good10377ba2017-08-04 00:07:45 +0100932 u64_stats_update_begin(&priv->syncp);
933 ring->packets += pkts_compl;
934 ring->bytes += bytes_compl;
935 u64_stats_update_end(&priv->syncp);
936
Florian Fainelli80105be2014-04-24 18:08:57 -0700937 ring->c_index = c_index;
938
Florian Fainelli80105be2014-04-24 18:08:57 -0700939 netif_dbg(priv, tx_done, ndev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700940 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
941 ring->index, ring->c_index, pkts_compl, bytes_compl);
Florian Fainelli80105be2014-04-24 18:08:57 -0700942
943 return pkts_compl;
944}
945
946/* Locked version of the per-ring TX reclaim routine */
947static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
948 struct bcm_sysport_tx_ring *ring)
949{
Florian Fainelli148d3d02017-01-12 12:09:09 -0800950 struct netdev_queue *txq;
Florian Fainelli80105be2014-04-24 18:08:57 -0700951 unsigned int released;
Florian Fainellid8498082014-06-05 10:22:15 -0700952 unsigned long flags;
Florian Fainelli80105be2014-04-24 18:08:57 -0700953
Florian Fainelli148d3d02017-01-12 12:09:09 -0800954 txq = netdev_get_tx_queue(priv->netdev, ring->index);
955
Florian Fainellid8498082014-06-05 10:22:15 -0700956 spin_lock_irqsave(&ring->lock, flags);
Florian Fainelli80105be2014-04-24 18:08:57 -0700957 released = __bcm_sysport_tx_reclaim(priv, ring);
Florian Fainelli148d3d02017-01-12 12:09:09 -0800958 if (released)
959 netif_tx_wake_queue(txq);
960
Florian Fainellid8498082014-06-05 10:22:15 -0700961 spin_unlock_irqrestore(&ring->lock, flags);
Florian Fainelli80105be2014-04-24 18:08:57 -0700962
963 return released;
964}
965
Florian Fainelli148d3d02017-01-12 12:09:09 -0800966/* Locked version of the per-ring TX reclaim, but does not wake the queue */
967static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv,
968 struct bcm_sysport_tx_ring *ring)
969{
970 unsigned long flags;
971
972 spin_lock_irqsave(&ring->lock, flags);
973 __bcm_sysport_tx_reclaim(priv, ring);
974 spin_unlock_irqrestore(&ring->lock, flags);
975}
976
Florian Fainelli80105be2014-04-24 18:08:57 -0700977static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget)
978{
979 struct bcm_sysport_tx_ring *ring =
980 container_of(napi, struct bcm_sysport_tx_ring, napi);
981 unsigned int work_done = 0;
982
983 work_done = bcm_sysport_tx_reclaim(ring->priv, ring);
984
Florian Fainelli16f62d92014-06-26 10:06:46 -0700985 if (work_done == 0) {
Florian Fainelli80105be2014-04-24 18:08:57 -0700986 napi_complete(napi);
987 /* re-enable TX interrupt */
Florian Fainelli44a45242017-01-20 11:08:27 -0800988 if (!ring->priv->is_lite)
989 intrl2_1_mask_clear(ring->priv, BIT(ring->index));
990 else
991 intrl2_0_mask_clear(ring->priv, BIT(ring->index +
992 INTRL2_0_TDMA_MBDONE_SHIFT));
Florian Fainelli9dfa9a22014-11-12 15:40:43 -0800993
994 return 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700995 }
996
Florian Fainelli9dfa9a22014-11-12 15:40:43 -0800997 return budget;
Florian Fainelli80105be2014-04-24 18:08:57 -0700998}
999
1000static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv)
1001{
1002 unsigned int q;
1003
1004 for (q = 0; q < priv->netdev->num_tx_queues; q++)
1005 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]);
1006}
1007
1008static int bcm_sysport_poll(struct napi_struct *napi, int budget)
1009{
1010 struct bcm_sysport_priv *priv =
1011 container_of(napi, struct bcm_sysport_priv, napi);
Florian Fainellib6e0e872018-03-22 18:19:32 -07001012 struct net_dim_sample dim_sample;
Florian Fainelli80105be2014-04-24 18:08:57 -07001013 unsigned int work_done = 0;
1014
1015 work_done = bcm_sysport_desc_rx(priv, budget);
1016
1017 priv->rx_c_index += work_done;
1018 priv->rx_c_index &= RDMA_CONS_INDEX_MASK;
Florian Fainelli44a45242017-01-20 11:08:27 -08001019
1020 /* SYSTEMPORT Lite groups the producer/consumer index, producer is
1021 * maintained by HW, but writes to it will be ignore while RDMA
1022 * is active
1023 */
1024 if (!priv->is_lite)
1025 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX);
1026 else
1027 rdma_writel(priv, priv->rx_c_index << 16, RDMA_CONS_INDEX);
Florian Fainelli80105be2014-04-24 18:08:57 -07001028
1029 if (work_done < budget) {
Florian Fainellic82f47e2016-04-20 11:37:09 -07001030 napi_complete_done(napi, work_done);
Florian Fainelli80105be2014-04-24 18:08:57 -07001031 /* re-enable RX interrupts */
1032 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE);
1033 }
1034
Florian Fainellib6e0e872018-03-22 18:19:32 -07001035 if (priv->dim.use_dim) {
1036 net_dim_sample(priv->dim.event_ctr, priv->dim.packets,
1037 priv->dim.bytes, &dim_sample);
1038 net_dim(&priv->dim.dim, dim_sample);
1039 }
1040
Florian Fainelli80105be2014-04-24 18:08:57 -07001041 return work_done;
1042}
1043
Florian Fainelli83e82f42014-07-01 21:08:40 -07001044static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv)
1045{
1046 u32 reg;
1047
1048 /* Stop monitoring MPD interrupt */
1049 intrl2_0_mask_set(priv, INTRL2_0_MPD);
1050
1051 /* Clear the MagicPacket detection logic */
1052 reg = umac_readl(priv, UMAC_MPD_CTRL);
1053 reg &= ~MPD_EN;
1054 umac_writel(priv, reg, UMAC_MPD_CTRL);
1055
1056 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n");
1057}
Florian Fainelli80105be2014-04-24 18:08:57 -07001058
Florian Fainellib6e0e872018-03-22 18:19:32 -07001059static void bcm_sysport_dim_work(struct work_struct *work)
1060{
1061 struct net_dim *dim = container_of(work, struct net_dim, work);
1062 struct bcm_sysport_net_dim *ndim =
1063 container_of(dim, struct bcm_sysport_net_dim, dim);
1064 struct bcm_sysport_priv *priv =
1065 container_of(ndim, struct bcm_sysport_priv, dim);
1066 struct net_dim_cq_moder cur_profile =
1067 net_dim_get_profile(dim->mode, dim->profile_ix);
1068
Florian Fainellia8cdfbd2018-03-28 15:15:37 -07001069 bcm_sysport_set_rx_coalesce(priv, cur_profile.usec, cur_profile.pkts);
Florian Fainellib6e0e872018-03-22 18:19:32 -07001070 dim->state = NET_DIM_START_MEASURE;
1071}
1072
Florian Fainelli80105be2014-04-24 18:08:57 -07001073/* RX and misc interrupt routine */
1074static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id)
1075{
1076 struct net_device *dev = dev_id;
1077 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainelli44a45242017-01-20 11:08:27 -08001078 struct bcm_sysport_tx_ring *txr;
1079 unsigned int ring, ring_bit;
Florian Fainelli80105be2014-04-24 18:08:57 -07001080
1081 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
1082 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1083 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1084
1085 if (unlikely(priv->irq0_stat == 0)) {
1086 netdev_warn(priv->netdev, "spurious RX interrupt\n");
1087 return IRQ_NONE;
1088 }
1089
1090 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) {
Florian Fainellib6e0e872018-03-22 18:19:32 -07001091 priv->dim.event_ctr++;
Florian Fainelli80105be2014-04-24 18:08:57 -07001092 if (likely(napi_schedule_prep(&priv->napi))) {
1093 /* disable RX interrupts */
1094 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE);
Florian Fainelliba909502016-04-20 11:37:08 -07001095 __napi_schedule_irqoff(&priv->napi);
Florian Fainelli80105be2014-04-24 18:08:57 -07001096 }
1097 }
1098
1099 /* TX ring is full, perform a full reclaim since we do not know
1100 * which one would trigger this interrupt
1101 */
1102 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL)
1103 bcm_sysport_tx_reclaim_all(priv);
1104
Florian Fainelli83e82f42014-07-01 21:08:40 -07001105 if (priv->irq0_stat & INTRL2_0_MPD) {
1106 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n");
1107 bcm_sysport_resume_from_wol(priv);
1108 }
1109
Florian Fainelli44a45242017-01-20 11:08:27 -08001110 if (!priv->is_lite)
1111 goto out;
1112
1113 for (ring = 0; ring < dev->num_tx_queues; ring++) {
1114 ring_bit = BIT(ring + INTRL2_0_TDMA_MBDONE_SHIFT);
1115 if (!(priv->irq0_stat & ring_bit))
1116 continue;
1117
1118 txr = &priv->tx_rings[ring];
1119
1120 if (likely(napi_schedule_prep(&txr->napi))) {
1121 intrl2_0_mask_set(priv, ring_bit);
1122 __napi_schedule(&txr->napi);
1123 }
1124 }
1125out:
Florian Fainelli80105be2014-04-24 18:08:57 -07001126 return IRQ_HANDLED;
1127}
1128
1129/* TX interrupt service routine */
1130static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id)
1131{
1132 struct net_device *dev = dev_id;
1133 struct bcm_sysport_priv *priv = netdev_priv(dev);
1134 struct bcm_sysport_tx_ring *txr;
1135 unsigned int ring;
1136
1137 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
1138 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
1139 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1140
1141 if (unlikely(priv->irq1_stat == 0)) {
1142 netdev_warn(priv->netdev, "spurious TX interrupt\n");
1143 return IRQ_NONE;
1144 }
1145
1146 for (ring = 0; ring < dev->num_tx_queues; ring++) {
1147 if (!(priv->irq1_stat & BIT(ring)))
1148 continue;
1149
1150 txr = &priv->tx_rings[ring];
1151
1152 if (likely(napi_schedule_prep(&txr->napi))) {
1153 intrl2_1_mask_set(priv, BIT(ring));
Florian Fainelliba909502016-04-20 11:37:08 -07001154 __napi_schedule_irqoff(&txr->napi);
Florian Fainelli80105be2014-04-24 18:08:57 -07001155 }
1156 }
1157
1158 return IRQ_HANDLED;
1159}
1160
Florian Fainelli83e82f42014-07-01 21:08:40 -07001161static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id)
1162{
1163 struct bcm_sysport_priv *priv = dev_id;
1164
1165 pm_wakeup_event(&priv->pdev->dev, 0);
1166
1167 return IRQ_HANDLED;
1168}
1169
Florian Fainelli6cec4f52015-07-31 11:42:55 -07001170#ifdef CONFIG_NET_POLL_CONTROLLER
1171static void bcm_sysport_poll_controller(struct net_device *dev)
1172{
1173 struct bcm_sysport_priv *priv = netdev_priv(dev);
1174
1175 disable_irq(priv->irq0);
1176 bcm_sysport_rx_isr(priv->irq0, priv);
1177 enable_irq(priv->irq0);
1178
Florian Fainelli44a45242017-01-20 11:08:27 -08001179 if (!priv->is_lite) {
1180 disable_irq(priv->irq1);
1181 bcm_sysport_tx_isr(priv->irq1, priv);
1182 enable_irq(priv->irq1);
1183 }
Florian Fainelli6cec4f52015-07-31 11:42:55 -07001184}
1185#endif
1186
Florian Fainellie87474a2014-10-02 09:43:16 -07001187static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb,
1188 struct net_device *dev)
Florian Fainelli80105be2014-04-24 18:08:57 -07001189{
1190 struct sk_buff *nskb;
Paul Gortmaker3afc5572014-05-30 15:39:30 -04001191 struct bcm_tsb *tsb;
Florian Fainelli80105be2014-04-24 18:08:57 -07001192 u32 csum_info;
1193 u8 ip_proto;
1194 u16 csum_start;
1195 u16 ip_ver;
1196
1197 /* Re-allocate SKB if needed */
1198 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) {
1199 nskb = skb_realloc_headroom(skb, sizeof(*tsb));
1200 dev_kfree_skb(skb);
1201 if (!nskb) {
1202 dev->stats.tx_errors++;
1203 dev->stats.tx_dropped++;
Florian Fainellie87474a2014-10-02 09:43:16 -07001204 return NULL;
Florian Fainelli80105be2014-04-24 18:08:57 -07001205 }
1206 skb = nskb;
1207 }
1208
Johannes Bergd58ff352017-06-16 14:29:23 +02001209 tsb = skb_push(skb, sizeof(*tsb));
Florian Fainelli80105be2014-04-24 18:08:57 -07001210 /* Zero-out TSB by default */
1211 memset(tsb, 0, sizeof(*tsb));
1212
1213 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1214 ip_ver = htons(skb->protocol);
1215 switch (ip_ver) {
1216 case ETH_P_IP:
1217 ip_proto = ip_hdr(skb)->protocol;
1218 break;
1219 case ETH_P_IPV6:
1220 ip_proto = ipv6_hdr(skb)->nexthdr;
1221 break;
1222 default:
Florian Fainellie87474a2014-10-02 09:43:16 -07001223 return skb;
Florian Fainelli80105be2014-04-24 18:08:57 -07001224 }
1225
1226 /* Get the checksum offset and the L4 (transport) offset */
1227 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb);
1228 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK;
1229 csum_info |= (csum_start << L4_PTR_SHIFT);
1230
1231 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1232 csum_info |= L4_LENGTH_VALID;
1233 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1234 csum_info |= L4_UDP;
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001235 } else {
Florian Fainelli80105be2014-04-24 18:08:57 -07001236 csum_info = 0;
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001237 }
Florian Fainelli80105be2014-04-24 18:08:57 -07001238
1239 tsb->l4_ptr_dest_map = csum_info;
1240 }
1241
Florian Fainellie87474a2014-10-02 09:43:16 -07001242 return skb;
Florian Fainelli80105be2014-04-24 18:08:57 -07001243}
1244
1245static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb,
1246 struct net_device *dev)
1247{
1248 struct bcm_sysport_priv *priv = netdev_priv(dev);
1249 struct device *kdev = &priv->pdev->dev;
1250 struct bcm_sysport_tx_ring *ring;
1251 struct bcm_sysport_cb *cb;
1252 struct netdev_queue *txq;
1253 struct dma_desc *desc;
Florian Fainellidab531b2014-05-14 19:32:14 -07001254 unsigned int skb_len;
Florian Fainellid8498082014-06-05 10:22:15 -07001255 unsigned long flags;
Florian Fainelli80105be2014-04-24 18:08:57 -07001256 dma_addr_t mapping;
1257 u32 len_status;
1258 u16 queue;
1259 int ret;
1260
1261 queue = skb_get_queue_mapping(skb);
1262 txq = netdev_get_tx_queue(dev, queue);
1263 ring = &priv->tx_rings[queue];
1264
Florian Fainellid8498082014-06-05 10:22:15 -07001265 /* lock against tx reclaim in BH context and TX ring full interrupt */
1266 spin_lock_irqsave(&ring->lock, flags);
Florian Fainelli80105be2014-04-24 18:08:57 -07001267 if (unlikely(ring->desc_count == 0)) {
1268 netif_tx_stop_queue(txq);
1269 netdev_err(dev, "queue %d awake and ring full!\n", queue);
1270 ret = NETDEV_TX_BUSY;
1271 goto out;
1272 }
1273
Florian Fainelli38e5a852017-01-03 16:34:49 -08001274 /* Insert TSB and checksum infos */
1275 if (priv->tsb_en) {
1276 skb = bcm_sysport_insert_tsb(skb, dev);
1277 if (!skb) {
1278 ret = NETDEV_TX_OK;
1279 goto out;
1280 }
1281 }
1282
Florian Fainellibb7da332017-01-03 16:34:48 -08001283 skb_len = skb->len;
Florian Fainellidab531b2014-05-14 19:32:14 -07001284
1285 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
Florian Fainelli80105be2014-04-24 18:08:57 -07001286 if (dma_mapping_error(kdev, mapping)) {
Florian Fainelli60b4ea12014-11-19 10:29:55 -08001287 priv->mib.tx_dma_failed++;
Florian Fainelli80105be2014-04-24 18:08:57 -07001288 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001289 skb->data, skb_len);
Florian Fainelli80105be2014-04-24 18:08:57 -07001290 ret = NETDEV_TX_OK;
1291 goto out;
1292 }
1293
1294 /* Remember the SKB for future freeing */
1295 cb = &ring->cbs[ring->curr_desc];
1296 cb->skb = skb;
1297 dma_unmap_addr_set(cb, dma_addr, mapping);
Florian Fainellidab531b2014-05-14 19:32:14 -07001298 dma_unmap_len_set(cb, dma_len, skb_len);
Florian Fainelli80105be2014-04-24 18:08:57 -07001299
1300 /* Fetch a descriptor entry from our pool */
1301 desc = ring->desc_cpu;
1302
1303 desc->addr_lo = lower_32_bits(mapping);
1304 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK;
Florian Fainellidab531b2014-05-14 19:32:14 -07001305 len_status |= (skb_len << DESC_LEN_SHIFT);
Florian Fainelli80105be2014-04-24 18:08:57 -07001306 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) <<
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001307 DESC_STATUS_SHIFT;
Florian Fainelli80105be2014-04-24 18:08:57 -07001308 if (skb->ip_summed == CHECKSUM_PARTIAL)
1309 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT);
1310
1311 ring->curr_desc++;
1312 if (ring->curr_desc == ring->size)
1313 ring->curr_desc = 0;
1314 ring->desc_count--;
1315
1316 /* Ensure write completion of the descriptor status/length
1317 * in DRAM before the System Port WRITE_PORT register latches
1318 * the value
1319 */
1320 wmb();
1321 desc->addr_status_len = len_status;
1322 wmb();
1323
1324 /* Write this descriptor address to the RING write port */
1325 tdma_port_write_desc_addr(priv, desc, ring->index);
1326
1327 /* Check ring space and update SW control flow */
1328 if (ring->desc_count == 0)
1329 netif_tx_stop_queue(txq);
1330
1331 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001332 ring->index, ring->desc_count, ring->curr_desc);
Florian Fainelli80105be2014-04-24 18:08:57 -07001333
1334 ret = NETDEV_TX_OK;
1335out:
Florian Fainellid8498082014-06-05 10:22:15 -07001336 spin_unlock_irqrestore(&ring->lock, flags);
Florian Fainelli80105be2014-04-24 18:08:57 -07001337 return ret;
1338}
1339
1340static void bcm_sysport_tx_timeout(struct net_device *dev)
1341{
1342 netdev_warn(dev, "transmit timeout!\n");
1343
Florian Westphal860e9532016-05-03 16:33:13 +02001344 netif_trans_update(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07001345 dev->stats.tx_errors++;
1346
1347 netif_tx_wake_all_queues(dev);
1348}
1349
1350/* phylib adjust link callback */
1351static void bcm_sysport_adj_link(struct net_device *dev)
1352{
1353 struct bcm_sysport_priv *priv = netdev_priv(dev);
Philippe Reynes715a0222016-06-19 20:39:08 +02001354 struct phy_device *phydev = dev->phydev;
Florian Fainelli80105be2014-04-24 18:08:57 -07001355 unsigned int changed = 0;
1356 u32 cmd_bits = 0, reg;
1357
1358 if (priv->old_link != phydev->link) {
1359 changed = 1;
1360 priv->old_link = phydev->link;
1361 }
1362
1363 if (priv->old_duplex != phydev->duplex) {
1364 changed = 1;
1365 priv->old_duplex = phydev->duplex;
1366 }
1367
Florian Fainelli44a45242017-01-20 11:08:27 -08001368 if (priv->is_lite)
1369 goto out;
1370
Florian Fainelli80105be2014-04-24 18:08:57 -07001371 switch (phydev->speed) {
1372 case SPEED_2500:
1373 cmd_bits = CMD_SPEED_2500;
1374 break;
1375 case SPEED_1000:
1376 cmd_bits = CMD_SPEED_1000;
1377 break;
1378 case SPEED_100:
1379 cmd_bits = CMD_SPEED_100;
1380 break;
1381 case SPEED_10:
1382 cmd_bits = CMD_SPEED_10;
1383 break;
1384 default:
1385 break;
1386 }
1387 cmd_bits <<= CMD_SPEED_SHIFT;
1388
1389 if (phydev->duplex == DUPLEX_HALF)
1390 cmd_bits |= CMD_HD_EN;
1391
1392 if (priv->old_pause != phydev->pause) {
1393 changed = 1;
1394 priv->old_pause = phydev->pause;
1395 }
1396
1397 if (!phydev->pause)
1398 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
1399
Florian Fainelli4a804c02014-09-02 11:17:07 -07001400 if (!changed)
1401 return;
1402
1403 if (phydev->link) {
Florian Fainellid5e32cc2014-05-14 19:32:13 -07001404 reg = umac_readl(priv, UMAC_CMD);
1405 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
Florian Fainelli80105be2014-04-24 18:08:57 -07001406 CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
1407 CMD_TX_PAUSE_IGNORE);
Florian Fainellid5e32cc2014-05-14 19:32:13 -07001408 reg |= cmd_bits;
1409 umac_writel(priv, reg, UMAC_CMD);
Florian Fainellid5e32cc2014-05-14 19:32:13 -07001410 }
Florian Fainelli44a45242017-01-20 11:08:27 -08001411out:
1412 if (changed)
1413 phy_print_status(phydev);
Florian Fainelli80105be2014-04-24 18:08:57 -07001414}
1415
Florian Fainellia8cdfbd2018-03-28 15:15:37 -07001416static void bcm_sysport_init_dim(struct bcm_sysport_priv *priv,
Florian Fainellib6e0e872018-03-22 18:19:32 -07001417 void (*cb)(struct work_struct *work))
1418{
Florian Fainellia8cdfbd2018-03-28 15:15:37 -07001419 struct bcm_sysport_net_dim *dim = &priv->dim;
1420
Florian Fainellib6e0e872018-03-22 18:19:32 -07001421 INIT_WORK(&dim->dim.work, cb);
1422 dim->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1423 dim->event_ctr = 0;
1424 dim->packets = 0;
1425 dim->bytes = 0;
1426}
1427
Florian Fainellia8cdfbd2018-03-28 15:15:37 -07001428static void bcm_sysport_init_rx_coalesce(struct bcm_sysport_priv *priv)
1429{
1430 struct bcm_sysport_net_dim *dim = &priv->dim;
1431 struct net_dim_cq_moder moder;
1432 u32 usecs, pkts;
1433
1434 usecs = priv->rx_coalesce_usecs;
1435 pkts = priv->rx_max_coalesced_frames;
1436
1437 /* If DIM was enabled, re-apply default parameters */
1438 if (dim->use_dim) {
1439 moder = net_dim_get_def_profile(dim->dim.mode);
1440 usecs = moder.usec;
1441 pkts = moder.pkts;
1442 }
1443
1444 bcm_sysport_set_rx_coalesce(priv, usecs, pkts);
1445}
1446
Florian Fainelli80105be2014-04-24 18:08:57 -07001447static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
1448 unsigned int index)
1449{
1450 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1451 struct device *kdev = &priv->pdev->dev;
1452 size_t size;
1453 void *p;
1454 u32 reg;
1455
1456 /* Simple descriptors partitioning for now */
1457 size = 256;
1458
1459 /* We just need one DMA descriptor which is DMA-able, since writing to
1460 * the port will allocate a new descriptor in its internal linked-list
1461 */
Florian Fainelli3e8fc382014-10-31 15:51:34 -07001462 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma,
1463 GFP_KERNEL);
Florian Fainelli80105be2014-04-24 18:08:57 -07001464 if (!p) {
1465 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n");
1466 return -ENOMEM;
1467 }
1468
Florian Fainelli40a8a312014-07-09 17:36:47 -07001469 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL);
Florian Fainelli80105be2014-04-24 18:08:57 -07001470 if (!ring->cbs) {
Florian Fainellic2062ee2017-08-24 16:01:13 -07001471 dma_free_coherent(kdev, sizeof(struct dma_desc),
1472 ring->desc_cpu, ring->desc_dma);
Florian Fainelli80105be2014-04-24 18:08:57 -07001473 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1474 return -ENOMEM;
1475 }
1476
1477 /* Initialize SW view of the ring */
1478 spin_lock_init(&ring->lock);
1479 ring->priv = priv;
Eric Dumazetd64b5e82015-11-18 06:31:00 -08001480 netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64);
Florian Fainelli80105be2014-04-24 18:08:57 -07001481 ring->index = index;
1482 ring->size = size;
Florian Fainelli484d8022018-03-13 14:45:07 -07001483 ring->clean_index = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -07001484 ring->alloc_size = ring->size;
1485 ring->desc_cpu = p;
1486 ring->desc_count = ring->size;
1487 ring->curr_desc = 0;
1488
1489 /* Initialize HW ring */
1490 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index));
1491 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index));
1492 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index));
1493 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index));
Florian Fainellid1565762017-10-11 10:57:50 -07001494
1495 /* Configure QID and port mapping */
1496 reg = tdma_readl(priv, TDMA_DESC_RING_MAPPING(index));
1497 reg &= ~(RING_QID_MASK | RING_PORT_ID_MASK << RING_PORT_ID_SHIFT);
Florian Fainelli3ded76a2017-11-01 11:29:47 -07001498 if (ring->inspect) {
1499 reg |= ring->switch_queue & RING_QID_MASK;
1500 reg |= ring->switch_port << RING_PORT_ID_SHIFT;
1501 } else {
1502 reg |= RING_IGNORE_STATUS;
1503 }
Florian Fainellid1565762017-10-11 10:57:50 -07001504 tdma_writel(priv, reg, TDMA_DESC_RING_MAPPING(index));
Florian Fainelli80105be2014-04-24 18:08:57 -07001505 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index));
1506
Florian Fainelli723934f2017-10-11 10:57:52 -07001507 /* Enable ACB algorithm 2 */
1508 reg = tdma_readl(priv, TDMA_CONTROL);
1509 reg |= tdma_control_bit(priv, ACB_ALGO);
1510 tdma_writel(priv, reg, TDMA_CONTROL);
1511
Florian Fainelli487234c2017-09-01 17:32:34 -07001512 /* Do not use tdma_control_bit() here because TSB_SWAP1 collides
1513 * with the original definition of ACB_ALGO
1514 */
1515 reg = tdma_readl(priv, TDMA_CONTROL);
1516 if (priv->is_lite)
1517 reg &= ~BIT(TSB_SWAP1);
1518 /* Set a correct TSB format based on host endian */
1519 if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
1520 reg |= tdma_control_bit(priv, TSB_SWAP0);
1521 else
1522 reg &= ~tdma_control_bit(priv, TSB_SWAP0);
1523 tdma_writel(priv, reg, TDMA_CONTROL);
1524
Florian Fainelli80105be2014-04-24 18:08:57 -07001525 /* Program the number of descriptors as MAX_THRESHOLD and half of
1526 * its size for the hysteresis trigger
1527 */
1528 tdma_writel(priv, ring->size |
1529 1 << RING_HYST_THRESH_SHIFT,
1530 TDMA_DESC_RING_MAX_HYST(index));
1531
1532 /* Enable the ring queue in the arbiter */
1533 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN);
1534 reg |= (1 << index);
1535 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN);
1536
1537 napi_enable(&ring->napi);
1538
1539 netif_dbg(priv, hw, priv->netdev,
Florian Fainellid1565762017-10-11 10:57:50 -07001540 "TDMA cfg, size=%d, desc_cpu=%p switch q=%d,port=%d\n",
1541 ring->size, ring->desc_cpu, ring->switch_queue,
1542 ring->switch_port);
Florian Fainelli80105be2014-04-24 18:08:57 -07001543
1544 return 0;
1545}
1546
1547static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001548 unsigned int index)
Florian Fainelli80105be2014-04-24 18:08:57 -07001549{
1550 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1551 struct device *kdev = &priv->pdev->dev;
1552 u32 reg;
1553
1554 /* Caller should stop the TDMA engine */
1555 reg = tdma_readl(priv, TDMA_STATUS);
1556 if (!(reg & TDMA_DISABLED))
1557 netdev_warn(priv->netdev, "TDMA not stopped!\n");
1558
Florian Fainelli914adb52014-10-31 15:51:35 -07001559 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could
1560 * fail, so by checking this pointer we know whether the TX ring was
1561 * fully initialized or not.
1562 */
1563 if (!ring->cbs)
1564 return;
1565
Florian Fainelli80105be2014-04-24 18:08:57 -07001566 napi_disable(&ring->napi);
1567 netif_napi_del(&ring->napi);
1568
Florian Fainelli148d3d02017-01-12 12:09:09 -08001569 bcm_sysport_tx_clean(priv, ring);
Florian Fainelli80105be2014-04-24 18:08:57 -07001570
1571 kfree(ring->cbs);
1572 ring->cbs = NULL;
1573
1574 if (ring->desc_dma) {
Florian Fainelli3e8fc382014-10-31 15:51:34 -07001575 dma_free_coherent(kdev, sizeof(struct dma_desc),
1576 ring->desc_cpu, ring->desc_dma);
Florian Fainelli80105be2014-04-24 18:08:57 -07001577 ring->desc_dma = 0;
1578 }
1579 ring->size = 0;
1580 ring->alloc_size = 0;
1581
1582 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n");
1583}
1584
1585/* RDMA helper */
1586static inline int rdma_enable_set(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001587 unsigned int enable)
Florian Fainelli80105be2014-04-24 18:08:57 -07001588{
1589 unsigned int timeout = 1000;
1590 u32 reg;
1591
1592 reg = rdma_readl(priv, RDMA_CONTROL);
1593 if (enable)
1594 reg |= RDMA_EN;
1595 else
1596 reg &= ~RDMA_EN;
1597 rdma_writel(priv, reg, RDMA_CONTROL);
1598
1599 /* Poll for RMDA disabling completion */
1600 do {
1601 reg = rdma_readl(priv, RDMA_STATUS);
1602 if (!!(reg & RDMA_DISABLED) == !enable)
1603 return 0;
1604 usleep_range(1000, 2000);
1605 } while (timeout-- > 0);
1606
1607 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n");
1608
1609 return -ETIMEDOUT;
1610}
1611
1612/* TDMA helper */
1613static inline int tdma_enable_set(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001614 unsigned int enable)
Florian Fainelli80105be2014-04-24 18:08:57 -07001615{
1616 unsigned int timeout = 1000;
1617 u32 reg;
1618
1619 reg = tdma_readl(priv, TDMA_CONTROL);
1620 if (enable)
Florian Fainelli44a45242017-01-20 11:08:27 -08001621 reg |= tdma_control_bit(priv, TDMA_EN);
Florian Fainelli80105be2014-04-24 18:08:57 -07001622 else
Florian Fainelli44a45242017-01-20 11:08:27 -08001623 reg &= ~tdma_control_bit(priv, TDMA_EN);
Florian Fainelli80105be2014-04-24 18:08:57 -07001624 tdma_writel(priv, reg, TDMA_CONTROL);
1625
1626 /* Poll for TMDA disabling completion */
1627 do {
1628 reg = tdma_readl(priv, TDMA_STATUS);
1629 if (!!(reg & TDMA_DISABLED) == !enable)
1630 return 0;
1631
1632 usleep_range(1000, 2000);
1633 } while (timeout-- > 0);
1634
1635 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n");
1636
1637 return -ETIMEDOUT;
1638}
1639
1640static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
1641{
Florian Fainellibaf387a2015-05-28 15:24:42 -07001642 struct bcm_sysport_cb *cb;
Florian Fainelli80105be2014-04-24 18:08:57 -07001643 u32 reg;
1644 int ret;
Florian Fainellibaf387a2015-05-28 15:24:42 -07001645 int i;
Florian Fainelli80105be2014-04-24 18:08:57 -07001646
1647 /* Initialize SW view of the RX ring */
Florian Fainelli44a45242017-01-20 11:08:27 -08001648 priv->num_rx_bds = priv->num_rx_desc_words / WORDS_PER_DESC;
Florian Fainelli80105be2014-04-24 18:08:57 -07001649 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
Florian Fainelli80105be2014-04-24 18:08:57 -07001650 priv->rx_c_index = 0;
1651 priv->rx_read_ptr = 0;
Florian Fainelli40a8a312014-07-09 17:36:47 -07001652 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb),
1653 GFP_KERNEL);
Florian Fainelli80105be2014-04-24 18:08:57 -07001654 if (!priv->rx_cbs) {
1655 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1656 return -ENOMEM;
1657 }
1658
Florian Fainellibaf387a2015-05-28 15:24:42 -07001659 for (i = 0; i < priv->num_rx_bds; i++) {
1660 cb = priv->rx_cbs + i;
1661 cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
1662 }
1663
Florian Fainelli80105be2014-04-24 18:08:57 -07001664 ret = bcm_sysport_alloc_rx_bufs(priv);
1665 if (ret) {
1666 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
1667 return ret;
1668 }
1669
1670 /* Initialize HW, ensure RDMA is disabled */
1671 reg = rdma_readl(priv, RDMA_STATUS);
1672 if (!(reg & RDMA_DISABLED))
1673 rdma_enable_set(priv, 0);
1674
1675 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO);
1676 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI);
1677 rdma_writel(priv, 0, RDMA_PROD_INDEX);
1678 rdma_writel(priv, 0, RDMA_CONS_INDEX);
1679 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT |
1680 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE);
1681 /* Operate the queue in ring mode */
1682 rdma_writel(priv, 0, RDMA_START_ADDR_HI);
1683 rdma_writel(priv, 0, RDMA_START_ADDR_LO);
1684 rdma_writel(priv, 0, RDMA_END_ADDR_HI);
Florian Fainelli44a45242017-01-20 11:08:27 -08001685 rdma_writel(priv, priv->num_rx_desc_words - 1, RDMA_END_ADDR_LO);
Florian Fainelli80105be2014-04-24 18:08:57 -07001686
Florian Fainelli80105be2014-04-24 18:08:57 -07001687 netif_dbg(priv, hw, priv->netdev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001688 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
1689 priv->num_rx_bds, priv->rx_bds);
Florian Fainelli80105be2014-04-24 18:08:57 -07001690
1691 return 0;
1692}
1693
1694static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv)
1695{
1696 struct bcm_sysport_cb *cb;
1697 unsigned int i;
1698 u32 reg;
1699
1700 /* Caller should ensure RDMA is disabled */
1701 reg = rdma_readl(priv, RDMA_STATUS);
1702 if (!(reg & RDMA_DISABLED))
1703 netdev_warn(priv->netdev, "RDMA not stopped!\n");
1704
1705 for (i = 0; i < priv->num_rx_bds; i++) {
1706 cb = &priv->rx_cbs[i];
1707 if (dma_unmap_addr(cb, dma_addr))
1708 dma_unmap_single(&priv->pdev->dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001709 dma_unmap_addr(cb, dma_addr),
1710 RX_BUF_LENGTH, DMA_FROM_DEVICE);
Florian Fainelli80105be2014-04-24 18:08:57 -07001711 bcm_sysport_free_cb(cb);
1712 }
1713
1714 kfree(priv->rx_cbs);
1715 priv->rx_cbs = NULL;
1716
1717 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n");
1718}
1719
1720static void bcm_sysport_set_rx_mode(struct net_device *dev)
1721{
1722 struct bcm_sysport_priv *priv = netdev_priv(dev);
1723 u32 reg;
1724
Florian Fainelli44a45242017-01-20 11:08:27 -08001725 if (priv->is_lite)
1726 return;
1727
Florian Fainelli80105be2014-04-24 18:08:57 -07001728 reg = umac_readl(priv, UMAC_CMD);
1729 if (dev->flags & IFF_PROMISC)
1730 reg |= CMD_PROMISC;
1731 else
1732 reg &= ~CMD_PROMISC;
1733 umac_writel(priv, reg, UMAC_CMD);
1734
1735 /* No support for ALLMULTI */
1736 if (dev->flags & IFF_ALLMULTI)
1737 return;
1738}
1739
1740static inline void umac_enable_set(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001741 u32 mask, unsigned int enable)
Florian Fainelli80105be2014-04-24 18:08:57 -07001742{
1743 u32 reg;
1744
Florian Fainelli44a45242017-01-20 11:08:27 -08001745 if (!priv->is_lite) {
1746 reg = umac_readl(priv, UMAC_CMD);
1747 if (enable)
1748 reg |= mask;
1749 else
1750 reg &= ~mask;
1751 umac_writel(priv, reg, UMAC_CMD);
1752 } else {
1753 reg = gib_readl(priv, GIB_CONTROL);
1754 if (enable)
1755 reg |= mask;
1756 else
1757 reg &= ~mask;
1758 gib_writel(priv, reg, GIB_CONTROL);
1759 }
Florian Fainelli00b91c62014-05-15 14:33:53 -07001760
1761 /* UniMAC stops on a packet boundary, wait for a full-sized packet
1762 * to be processed (1 msec).
1763 */
1764 if (enable == 0)
1765 usleep_range(1000, 2000);
Florian Fainelli80105be2014-04-24 18:08:57 -07001766}
1767
Florian Fainelli412bce82014-06-26 10:06:45 -07001768static inline void umac_reset(struct bcm_sysport_priv *priv)
Florian Fainelli80105be2014-04-24 18:08:57 -07001769{
Florian Fainelli80105be2014-04-24 18:08:57 -07001770 u32 reg;
Florian Fainelli80105be2014-04-24 18:08:57 -07001771
Florian Fainelli44a45242017-01-20 11:08:27 -08001772 if (priv->is_lite)
1773 return;
1774
Florian Fainelli412bce82014-06-26 10:06:45 -07001775 reg = umac_readl(priv, UMAC_CMD);
1776 reg |= CMD_SW_RESET;
1777 umac_writel(priv, reg, UMAC_CMD);
1778 udelay(10);
1779 reg = umac_readl(priv, UMAC_CMD);
1780 reg &= ~CMD_SW_RESET;
1781 umac_writel(priv, reg, UMAC_CMD);
Florian Fainelli80105be2014-04-24 18:08:57 -07001782}
1783
1784static void umac_set_hw_addr(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001785 unsigned char *addr)
Florian Fainelli80105be2014-04-24 18:08:57 -07001786{
Florian Fainelli44a45242017-01-20 11:08:27 -08001787 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
1788 addr[3];
1789 u32 mac1 = (addr[4] << 8) | addr[5];
1790
1791 if (!priv->is_lite) {
1792 umac_writel(priv, mac0, UMAC_MAC0);
1793 umac_writel(priv, mac1, UMAC_MAC1);
1794 } else {
1795 gib_writel(priv, mac0, GIB_MAC0);
1796 gib_writel(priv, mac1, GIB_MAC1);
1797 }
Florian Fainelli80105be2014-04-24 18:08:57 -07001798}
1799
1800static void topctrl_flush(struct bcm_sysport_priv *priv)
1801{
1802 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1803 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1804 mdelay(1);
1805 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
1806 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
1807}
1808
Florian Fainellifb3b5962014-12-08 15:59:18 -08001809static int bcm_sysport_change_mac(struct net_device *dev, void *p)
1810{
1811 struct bcm_sysport_priv *priv = netdev_priv(dev);
1812 struct sockaddr *addr = p;
1813
1814 if (!is_valid_ether_addr(addr->sa_data))
1815 return -EINVAL;
1816
1817 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1818
1819 /* interface is disabled, changes to MAC will be reflected on next
1820 * open call
1821 */
1822 if (!netif_running(dev))
1823 return 0;
1824
1825 umac_set_hw_addr(priv, dev->dev_addr);
1826
1827 return 0;
1828}
1829
kiki good10377ba2017-08-04 00:07:45 +01001830static void bcm_sysport_get_stats64(struct net_device *dev,
1831 struct rtnl_link_stats64 *stats)
Florian Fainelli30defeb2017-03-23 10:36:46 -07001832{
1833 struct bcm_sysport_priv *priv = netdev_priv(dev);
kiki good10377ba2017-08-04 00:07:45 +01001834 struct bcm_sysport_stats64 *stats64 = &priv->stats64;
kiki good10377ba2017-08-04 00:07:45 +01001835 unsigned int start;
Florian Fainelli30defeb2017-03-23 10:36:46 -07001836
kiki good10377ba2017-08-04 00:07:45 +01001837 netdev_stats_to_stats64(stats, &dev->stats);
1838
Florian Fainelli8ecb1a22017-09-18 16:31:30 -07001839 bcm_sysport_update_tx_stats(priv, &stats->tx_bytes,
1840 &stats->tx_packets);
kiki good10377ba2017-08-04 00:07:45 +01001841
1842 do {
1843 start = u64_stats_fetch_begin_irq(&priv->syncp);
1844 stats->rx_packets = stats64->rx_packets;
1845 stats->rx_bytes = stats64->rx_bytes;
1846 } while (u64_stats_fetch_retry_irq(&priv->syncp, start));
Florian Fainelli30defeb2017-03-23 10:36:46 -07001847}
1848
Florian Fainellib02e6d92014-07-01 21:08:37 -07001849static void bcm_sysport_netif_start(struct net_device *dev)
1850{
1851 struct bcm_sysport_priv *priv = netdev_priv(dev);
1852
1853 /* Enable NAPI */
Florian Fainellia8cdfbd2018-03-28 15:15:37 -07001854 bcm_sysport_init_dim(priv, bcm_sysport_dim_work);
1855 bcm_sysport_init_rx_coalesce(priv);
Florian Fainellib02e6d92014-07-01 21:08:37 -07001856 napi_enable(&priv->napi);
1857
Florian Fainelli8edf0042014-10-28 11:12:00 -07001858 /* Enable RX interrupt and TX ring full interrupt */
1859 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1860
Philippe Reynes715a0222016-06-19 20:39:08 +02001861 phy_start(dev->phydev);
Florian Fainellib02e6d92014-07-01 21:08:37 -07001862
Florian Fainelli44a45242017-01-20 11:08:27 -08001863 /* Enable TX interrupts for the TXQs */
1864 if (!priv->is_lite)
1865 intrl2_1_mask_clear(priv, 0xffffffff);
1866 else
1867 intrl2_0_mask_clear(priv, INTRL2_0_TDMA_MBDONE_MASK);
Florian Fainellib02e6d92014-07-01 21:08:37 -07001868
1869 /* Last call before we start the real business */
1870 netif_tx_start_all_queues(dev);
1871}
1872
Florian Fainelli40755a02014-07-01 21:08:38 -07001873static void rbuf_init(struct bcm_sysport_priv *priv)
1874{
1875 u32 reg;
1876
1877 reg = rbuf_readl(priv, RBUF_CONTROL);
1878 reg |= RBUF_4B_ALGN | RBUF_RSB_EN;
Florian Fainelli44a45242017-01-20 11:08:27 -08001879 /* Set a correct RSB format on SYSTEMPORT Lite */
Florian Fainelli389a06b2017-08-29 13:35:17 -07001880 if (priv->is_lite)
Florian Fainelli44a45242017-01-20 11:08:27 -08001881 reg &= ~RBUF_RSB_SWAP1;
Florian Fainelli389a06b2017-08-29 13:35:17 -07001882
1883 /* Set a correct RSB format based on host endian */
1884 if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
Florian Fainelli44a45242017-01-20 11:08:27 -08001885 reg |= RBUF_RSB_SWAP0;
Florian Fainelli389a06b2017-08-29 13:35:17 -07001886 else
1887 reg &= ~RBUF_RSB_SWAP0;
Florian Fainelli40755a02014-07-01 21:08:38 -07001888 rbuf_writel(priv, reg, RBUF_CONTROL);
1889}
1890
Florian Fainelli44a45242017-01-20 11:08:27 -08001891static inline void bcm_sysport_mask_all_intrs(struct bcm_sysport_priv *priv)
1892{
1893 intrl2_0_mask_set(priv, 0xffffffff);
1894 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1895 if (!priv->is_lite) {
1896 intrl2_1_mask_set(priv, 0xffffffff);
1897 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1898 }
1899}
1900
1901static inline void gib_set_pad_extension(struct bcm_sysport_priv *priv)
1902{
Florian Fainelli93824c82017-11-02 16:08:40 -07001903 u32 reg;
Florian Fainelli44a45242017-01-20 11:08:27 -08001904
Florian Fainelli93824c82017-11-02 16:08:40 -07001905 reg = gib_readl(priv, GIB_CONTROL);
1906 /* Include Broadcom tag in pad extension and fix up IPG_LENGTH */
Florian Fainelli44a45242017-01-20 11:08:27 -08001907 if (netdev_uses_dsa(priv->netdev)) {
Florian Fainelli44a45242017-01-20 11:08:27 -08001908 reg &= ~(GIB_PAD_EXTENSION_MASK << GIB_PAD_EXTENSION_SHIFT);
1909 reg |= ENET_BRCM_TAG_LEN << GIB_PAD_EXTENSION_SHIFT;
Florian Fainelli44a45242017-01-20 11:08:27 -08001910 }
Florian Fainelli93824c82017-11-02 16:08:40 -07001911 reg &= ~(GIB_IPG_LEN_MASK << GIB_IPG_LEN_SHIFT);
1912 reg |= 12 << GIB_IPG_LEN_SHIFT;
1913 gib_writel(priv, reg, GIB_CONTROL);
Florian Fainelli44a45242017-01-20 11:08:27 -08001914}
1915
Florian Fainelli80105be2014-04-24 18:08:57 -07001916static int bcm_sysport_open(struct net_device *dev)
1917{
1918 struct bcm_sysport_priv *priv = netdev_priv(dev);
Philippe Reynes715a0222016-06-19 20:39:08 +02001919 struct phy_device *phydev;
Florian Fainelli80105be2014-04-24 18:08:57 -07001920 unsigned int i;
Florian Fainelli80105be2014-04-24 18:08:57 -07001921 int ret;
1922
1923 /* Reset UniMAC */
Florian Fainelli412bce82014-06-26 10:06:45 -07001924 umac_reset(priv);
Florian Fainelli80105be2014-04-24 18:08:57 -07001925
1926 /* Flush TX and RX FIFOs at TOPCTRL level */
1927 topctrl_flush(priv);
1928
1929 /* Disable the UniMAC RX/TX */
Florian Fainelli18e21b02014-07-01 21:08:36 -07001930 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
Florian Fainelli80105be2014-04-24 18:08:57 -07001931
1932 /* Enable RBUF 2bytes alignment and Receive Status Block */
Florian Fainelli40755a02014-07-01 21:08:38 -07001933 rbuf_init(priv);
Florian Fainelli80105be2014-04-24 18:08:57 -07001934
1935 /* Set maximum frame length */
Florian Fainelli44a45242017-01-20 11:08:27 -08001936 if (!priv->is_lite)
1937 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1938 else
1939 gib_set_pad_extension(priv);
Florian Fainelli80105be2014-04-24 18:08:57 -07001940
1941 /* Set MAC address */
1942 umac_set_hw_addr(priv, dev->dev_addr);
1943
1944 /* Read CRC forward */
Florian Fainelli44a45242017-01-20 11:08:27 -08001945 if (!priv->is_lite)
1946 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
1947 else
1948 priv->crc_fwd = !!(gib_readl(priv, GIB_CONTROL) &
1949 GIB_FCS_STRIP);
Florian Fainelli80105be2014-04-24 18:08:57 -07001950
Philippe Reynes715a0222016-06-19 20:39:08 +02001951 phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
1952 0, priv->phy_interface);
1953 if (!phydev) {
Florian Fainelli80105be2014-04-24 18:08:57 -07001954 netdev_err(dev, "could not attach to PHY\n");
1955 return -ENODEV;
1956 }
1957
1958 /* Reset house keeping link status */
1959 priv->old_duplex = -1;
1960 priv->old_link = -1;
1961 priv->old_pause = -1;
1962
1963 /* mask all interrupts and request them */
Florian Fainelli44a45242017-01-20 11:08:27 -08001964 bcm_sysport_mask_all_intrs(priv);
Florian Fainelli80105be2014-04-24 18:08:57 -07001965
1966 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev);
1967 if (ret) {
1968 netdev_err(dev, "failed to request RX interrupt\n");
1969 goto out_phy_disconnect;
1970 }
1971
Florian Fainelli44a45242017-01-20 11:08:27 -08001972 if (!priv->is_lite) {
1973 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0,
1974 dev->name, dev);
1975 if (ret) {
1976 netdev_err(dev, "failed to request TX interrupt\n");
1977 goto out_free_irq0;
1978 }
Florian Fainelli80105be2014-04-24 18:08:57 -07001979 }
1980
1981 /* Initialize both hardware and software ring */
1982 for (i = 0; i < dev->num_tx_queues; i++) {
1983 ret = bcm_sysport_init_tx_ring(priv, i);
1984 if (ret) {
1985 netdev_err(dev, "failed to initialize TX ring %d\n",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001986 i);
Florian Fainelli80105be2014-04-24 18:08:57 -07001987 goto out_free_tx_ring;
1988 }
1989 }
1990
1991 /* Initialize linked-list */
1992 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
1993
1994 /* Initialize RX ring */
1995 ret = bcm_sysport_init_rx_ring(priv);
1996 if (ret) {
1997 netdev_err(dev, "failed to initialize RX ring\n");
1998 goto out_free_rx_ring;
1999 }
2000
2001 /* Turn on RDMA */
2002 ret = rdma_enable_set(priv, 1);
2003 if (ret)
2004 goto out_free_rx_ring;
2005
Florian Fainelli80105be2014-04-24 18:08:57 -07002006 /* Turn on TDMA */
2007 ret = tdma_enable_set(priv, 1);
2008 if (ret)
2009 goto out_clear_rx_int;
2010
Florian Fainelli80105be2014-04-24 18:08:57 -07002011 /* Turn on UniMAC TX/RX */
Florian Fainelli18e21b02014-07-01 21:08:36 -07002012 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1);
Florian Fainelli80105be2014-04-24 18:08:57 -07002013
Florian Fainellib02e6d92014-07-01 21:08:37 -07002014 bcm_sysport_netif_start(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002015
2016 return 0;
2017
2018out_clear_rx_int:
2019 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
2020out_free_rx_ring:
2021 bcm_sysport_fini_rx_ring(priv);
2022out_free_tx_ring:
2023 for (i = 0; i < dev->num_tx_queues; i++)
2024 bcm_sysport_fini_tx_ring(priv, i);
Florian Fainelli44a45242017-01-20 11:08:27 -08002025 if (!priv->is_lite)
2026 free_irq(priv->irq1, dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002027out_free_irq0:
2028 free_irq(priv->irq0, dev);
2029out_phy_disconnect:
Philippe Reynes715a0222016-06-19 20:39:08 +02002030 phy_disconnect(phydev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002031 return ret;
2032}
2033
Florian Fainellib02e6d92014-07-01 21:08:37 -07002034static void bcm_sysport_netif_stop(struct net_device *dev)
Florian Fainelli80105be2014-04-24 18:08:57 -07002035{
2036 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002037
2038 /* stop all software from updating hardware */
2039 netif_tx_stop_all_queues(dev);
2040 napi_disable(&priv->napi);
Florian Fainellib6e0e872018-03-22 18:19:32 -07002041 cancel_work_sync(&priv->dim.dim.work);
Philippe Reynes715a0222016-06-19 20:39:08 +02002042 phy_stop(dev->phydev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002043
2044 /* mask all interrupts */
Florian Fainelli44a45242017-01-20 11:08:27 -08002045 bcm_sysport_mask_all_intrs(priv);
Florian Fainellib02e6d92014-07-01 21:08:37 -07002046}
2047
2048static int bcm_sysport_stop(struct net_device *dev)
2049{
2050 struct bcm_sysport_priv *priv = netdev_priv(dev);
2051 unsigned int i;
2052 int ret;
2053
2054 bcm_sysport_netif_stop(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002055
2056 /* Disable UniMAC RX */
Florian Fainelli18e21b02014-07-01 21:08:36 -07002057 umac_enable_set(priv, CMD_RX_EN, 0);
Florian Fainelli80105be2014-04-24 18:08:57 -07002058
2059 ret = tdma_enable_set(priv, 0);
2060 if (ret) {
2061 netdev_err(dev, "timeout disabling RDMA\n");
2062 return ret;
2063 }
2064
2065 /* Wait for a maximum packet size to be drained */
2066 usleep_range(2000, 3000);
2067
2068 ret = rdma_enable_set(priv, 0);
2069 if (ret) {
2070 netdev_err(dev, "timeout disabling TDMA\n");
2071 return ret;
2072 }
2073
2074 /* Disable UniMAC TX */
Florian Fainelli18e21b02014-07-01 21:08:36 -07002075 umac_enable_set(priv, CMD_TX_EN, 0);
Florian Fainelli80105be2014-04-24 18:08:57 -07002076
2077 /* Free RX/TX rings SW structures */
2078 for (i = 0; i < dev->num_tx_queues; i++)
2079 bcm_sysport_fini_tx_ring(priv, i);
2080 bcm_sysport_fini_rx_ring(priv);
2081
2082 free_irq(priv->irq0, dev);
Florian Fainelli44a45242017-01-20 11:08:27 -08002083 if (!priv->is_lite)
2084 free_irq(priv->irq1, dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002085
2086 /* Disconnect from PHY */
Philippe Reynes715a0222016-06-19 20:39:08 +02002087 phy_disconnect(dev->phydev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002088
2089 return 0;
2090}
2091
Julia Lawallc1ab0e92016-08-31 09:30:48 +02002092static const struct ethtool_ops bcm_sysport_ethtool_ops = {
Florian Fainelli80105be2014-04-24 18:08:57 -07002093 .get_drvinfo = bcm_sysport_get_drvinfo,
2094 .get_msglevel = bcm_sysport_get_msglvl,
2095 .set_msglevel = bcm_sysport_set_msglvl,
2096 .get_link = ethtool_op_get_link,
2097 .get_strings = bcm_sysport_get_strings,
2098 .get_ethtool_stats = bcm_sysport_get_stats,
2099 .get_sset_count = bcm_sysport_get_sset_count,
Florian Fainelli83e82f42014-07-01 21:08:40 -07002100 .get_wol = bcm_sysport_get_wol,
2101 .set_wol = bcm_sysport_set_wol,
Florian Fainellib1a15e82015-05-11 15:12:41 -07002102 .get_coalesce = bcm_sysport_get_coalesce,
2103 .set_coalesce = bcm_sysport_set_coalesce,
Philippe Reynes697666e2016-06-19 20:39:09 +02002104 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2105 .set_link_ksettings = phy_ethtool_set_link_ksettings,
Florian Fainelli80105be2014-04-24 18:08:57 -07002106};
2107
Florian Fainellid1565762017-10-11 10:57:50 -07002108static u16 bcm_sysport_select_queue(struct net_device *dev, struct sk_buff *skb,
2109 void *accel_priv,
2110 select_queue_fallback_t fallback)
2111{
2112 struct bcm_sysport_priv *priv = netdev_priv(dev);
2113 u16 queue = skb_get_queue_mapping(skb);
2114 struct bcm_sysport_tx_ring *tx_ring;
2115 unsigned int q, port;
2116
2117 if (!netdev_uses_dsa(dev))
2118 return fallback(dev, skb);
2119
2120 /* DSA tagging layer will have configured the correct queue */
2121 q = BRCM_TAG_GET_QUEUE(queue);
2122 port = BRCM_TAG_GET_PORT(queue);
2123 tx_ring = priv->ring_map[q + port * priv->per_port_num_tx_queues];
2124
Florian Fainellie83b1712017-10-20 15:59:30 -07002125 if (unlikely(!tx_ring))
2126 return fallback(dev, skb);
2127
Florian Fainellid1565762017-10-11 10:57:50 -07002128 return tx_ring->index;
2129}
2130
Florian Fainellic0c21452017-10-25 18:01:05 -07002131static const struct net_device_ops bcm_sysport_netdev_ops = {
2132 .ndo_start_xmit = bcm_sysport_xmit,
2133 .ndo_tx_timeout = bcm_sysport_tx_timeout,
2134 .ndo_open = bcm_sysport_open,
2135 .ndo_stop = bcm_sysport_stop,
2136 .ndo_set_features = bcm_sysport_set_features,
2137 .ndo_set_rx_mode = bcm_sysport_set_rx_mode,
2138 .ndo_set_mac_address = bcm_sysport_change_mac,
2139#ifdef CONFIG_NET_POLL_CONTROLLER
2140 .ndo_poll_controller = bcm_sysport_poll_controller,
2141#endif
2142 .ndo_get_stats64 = bcm_sysport_get_stats64,
2143 .ndo_select_queue = bcm_sysport_select_queue,
2144};
2145
Florian Fainellid1565762017-10-11 10:57:50 -07002146static int bcm_sysport_map_queues(struct net_device *dev,
2147 struct dsa_notifier_register_info *info)
2148{
2149 struct bcm_sysport_priv *priv = netdev_priv(dev);
2150 struct bcm_sysport_tx_ring *ring;
2151 struct net_device *slave_dev;
2152 unsigned int num_tx_queues;
2153 unsigned int q, start, port;
2154
2155 /* We can't be setting up queue inspection for non directly attached
2156 * switches
2157 */
2158 if (info->switch_number)
2159 return 0;
2160
Florian Fainellic0c21452017-10-25 18:01:05 -07002161 if (dev->netdev_ops != &bcm_sysport_netdev_ops)
2162 return 0;
2163
Florian Fainellid1565762017-10-11 10:57:50 -07002164 port = info->port_number;
2165 slave_dev = info->info.dev;
2166
2167 /* On SYSTEMPORT Lite we have twice as less queues, so we cannot do a
2168 * 1:1 mapping, we can only do a 2:1 mapping. By reducing the number of
2169 * per-port (slave_dev) network devices queue, we achieve just that.
2170 * This need to happen now before any slave network device is used such
2171 * it accurately reflects the number of real TX queues.
2172 */
2173 if (priv->is_lite)
2174 netif_set_real_num_tx_queues(slave_dev,
2175 slave_dev->num_tx_queues / 2);
2176 num_tx_queues = slave_dev->real_num_tx_queues;
2177
2178 if (priv->per_port_num_tx_queues &&
2179 priv->per_port_num_tx_queues != num_tx_queues)
2180 netdev_warn(slave_dev, "asymetric number of per-port queues\n");
2181
2182 priv->per_port_num_tx_queues = num_tx_queues;
2183
2184 start = find_first_zero_bit(&priv->queue_bitmap, dev->num_tx_queues);
2185 for (q = 0; q < num_tx_queues; q++) {
2186 ring = &priv->tx_rings[q + start];
2187
2188 /* Just remember the mapping actual programming done
2189 * during bcm_sysport_init_tx_ring
2190 */
2191 ring->switch_queue = q;
2192 ring->switch_port = port;
Florian Fainelli3ded76a2017-11-01 11:29:47 -07002193 ring->inspect = true;
Florian Fainellid1565762017-10-11 10:57:50 -07002194 priv->ring_map[q + port * num_tx_queues] = ring;
2195
2196 /* Set all queues as being used now */
2197 set_bit(q + start, &priv->queue_bitmap);
2198 }
2199
2200 return 0;
2201}
2202
2203static int bcm_sysport_dsa_notifier(struct notifier_block *unused,
2204 unsigned long event, void *ptr)
2205{
2206 struct dsa_notifier_register_info *info;
2207
2208 if (event != DSA_PORT_REGISTER)
2209 return NOTIFY_DONE;
2210
2211 info = ptr;
2212
2213 return notifier_from_errno(bcm_sysport_map_queues(info->master, info));
2214}
2215
Florian Fainelli80105be2014-04-24 18:08:57 -07002216#define REV_FMT "v%2x.%02x"
2217
Florian Fainelli44a45242017-01-20 11:08:27 -08002218static const struct bcm_sysport_hw_params bcm_sysport_params[] = {
2219 [SYSTEMPORT] = {
2220 .is_lite = false,
2221 .num_rx_desc_words = SP_NUM_HW_RX_DESC_WORDS,
2222 },
2223 [SYSTEMPORT_LITE] = {
2224 .is_lite = true,
2225 .num_rx_desc_words = SP_LT_NUM_HW_RX_DESC_WORDS,
2226 },
2227};
2228
2229static const struct of_device_id bcm_sysport_of_match[] = {
2230 { .compatible = "brcm,systemportlite-v1.00",
2231 .data = &bcm_sysport_params[SYSTEMPORT_LITE] },
2232 { .compatible = "brcm,systemport-v1.00",
2233 .data = &bcm_sysport_params[SYSTEMPORT] },
2234 { .compatible = "brcm,systemport",
2235 .data = &bcm_sysport_params[SYSTEMPORT] },
2236 { /* sentinel */ }
2237};
2238MODULE_DEVICE_TABLE(of, bcm_sysport_of_match);
2239
Florian Fainelli80105be2014-04-24 18:08:57 -07002240static int bcm_sysport_probe(struct platform_device *pdev)
2241{
Florian Fainelli44a45242017-01-20 11:08:27 -08002242 const struct bcm_sysport_hw_params *params;
2243 const struct of_device_id *of_id = NULL;
Florian Fainelli80105be2014-04-24 18:08:57 -07002244 struct bcm_sysport_priv *priv;
2245 struct device_node *dn;
2246 struct net_device *dev;
2247 const void *macaddr;
2248 struct resource *r;
2249 u32 txq, rxq;
2250 int ret;
2251
2252 dn = pdev->dev.of_node;
2253 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Florian Fainelli44a45242017-01-20 11:08:27 -08002254 of_id = of_match_node(bcm_sysport_of_match, dn);
2255 if (!of_id || !of_id->data)
2256 return -EINVAL;
2257
2258 /* Fairly quickly we need to know the type of adapter we have */
2259 params = of_id->data;
Florian Fainelli80105be2014-04-24 18:08:57 -07002260
2261 /* Read the Transmit/Receive Queue properties */
2262 if (of_property_read_u32(dn, "systemport,num-txq", &txq))
2263 txq = TDMA_NUM_RINGS;
2264 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq))
2265 rxq = 1;
2266
Florian Fainelli7b78be42017-01-20 11:08:26 -08002267 /* Sanity check the number of transmit queues */
2268 if (!txq || txq > TDMA_NUM_RINGS)
2269 return -EINVAL;
2270
Florian Fainelli80105be2014-04-24 18:08:57 -07002271 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq);
2272 if (!dev)
2273 return -ENOMEM;
2274
2275 /* Initialize private members */
2276 priv = netdev_priv(dev);
2277
Florian Fainelli7b78be42017-01-20 11:08:26 -08002278 /* Allocate number of TX rings */
2279 priv->tx_rings = devm_kcalloc(&pdev->dev, txq,
2280 sizeof(struct bcm_sysport_tx_ring),
2281 GFP_KERNEL);
2282 if (!priv->tx_rings)
2283 return -ENOMEM;
2284
Florian Fainelli44a45242017-01-20 11:08:27 -08002285 priv->is_lite = params->is_lite;
2286 priv->num_rx_desc_words = params->num_rx_desc_words;
2287
Florian Fainelli80105be2014-04-24 18:08:57 -07002288 priv->irq0 = platform_get_irq(pdev, 0);
Florian Fainellid31353c2017-06-01 18:02:39 -07002289 if (!priv->is_lite) {
Florian Fainelli44a45242017-01-20 11:08:27 -08002290 priv->irq1 = platform_get_irq(pdev, 1);
Florian Fainellid31353c2017-06-01 18:02:39 -07002291 priv->wol_irq = platform_get_irq(pdev, 2);
2292 } else {
2293 priv->wol_irq = platform_get_irq(pdev, 1);
2294 }
Florian Fainelli44a45242017-01-20 11:08:27 -08002295 if (priv->irq0 <= 0 || (priv->irq1 <= 0 && !priv->is_lite)) {
Florian Fainelli80105be2014-04-24 18:08:57 -07002296 dev_err(&pdev->dev, "invalid interrupts\n");
2297 ret = -EINVAL;
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002298 goto err_free_netdev;
Florian Fainelli80105be2014-04-24 18:08:57 -07002299 }
2300
Jingoo Han126e6122014-05-14 12:15:42 +09002301 priv->base = devm_ioremap_resource(&pdev->dev, r);
2302 if (IS_ERR(priv->base)) {
2303 ret = PTR_ERR(priv->base);
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002304 goto err_free_netdev;
Florian Fainelli80105be2014-04-24 18:08:57 -07002305 }
2306
2307 priv->netdev = dev;
2308 priv->pdev = pdev;
2309
2310 priv->phy_interface = of_get_phy_mode(dn);
2311 /* Default to GMII interface mode */
2312 if (priv->phy_interface < 0)
2313 priv->phy_interface = PHY_INTERFACE_MODE_GMII;
2314
Florian Fainelli186534a2014-05-22 09:47:46 -07002315 /* In the case of a fixed PHY, the DT node associated
2316 * to the PHY is the Ethernet MAC DT node.
2317 */
2318 if (of_phy_is_fixed_link(dn)) {
2319 ret = of_phy_register_fixed_link(dn);
2320 if (ret) {
2321 dev_err(&pdev->dev, "failed to register fixed PHY\n");
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002322 goto err_free_netdev;
Florian Fainelli186534a2014-05-22 09:47:46 -07002323 }
2324
2325 priv->phy_dn = dn;
2326 }
2327
Florian Fainelli80105be2014-04-24 18:08:57 -07002328 /* Initialize netdevice members */
2329 macaddr = of_get_mac_address(dn);
2330 if (!macaddr || !is_valid_ether_addr(macaddr)) {
2331 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
Vaishali Thakkaradb35052015-07-08 10:49:30 +05302332 eth_hw_addr_random(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002333 } else {
2334 ether_addr_copy(dev->dev_addr, macaddr);
2335 }
2336
2337 SET_NETDEV_DEV(dev, &pdev->dev);
2338 dev_set_drvdata(&pdev->dev, dev);
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00002339 dev->ethtool_ops = &bcm_sysport_ethtool_ops;
Florian Fainelli80105be2014-04-24 18:08:57 -07002340 dev->netdev_ops = &bcm_sysport_netdev_ops;
2341 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64);
2342
2343 /* HW supported features, none enabled by default */
2344 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
2345 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2346
Florian Fainelli83e82f42014-07-01 21:08:40 -07002347 /* Request the WOL interrupt and advertise suspend if available */
2348 priv->wol_irq_disabled = 1;
2349 ret = devm_request_irq(&pdev->dev, priv->wol_irq,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07002350 bcm_sysport_wol_isr, 0, dev->name, priv);
Florian Fainelli83e82f42014-07-01 21:08:40 -07002351 if (!ret)
2352 device_set_wakeup_capable(&pdev->dev, 1);
2353
Florian Fainelli80105be2014-04-24 18:08:57 -07002354 /* Set the needed headroom once and for all */
Paul Gortmaker3afc5572014-05-30 15:39:30 -04002355 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8);
2356 dev->needed_headroom += sizeof(struct bcm_tsb);
Florian Fainelli80105be2014-04-24 18:08:57 -07002357
Florian Fainellif532e742014-06-05 10:22:18 -07002358 /* libphy will adjust the link state accordingly */
2359 netif_carrier_off(dev);
2360
Florian Fainellia8cdfbd2018-03-28 15:15:37 -07002361 priv->rx_max_coalesced_frames = 1;
kiki good10377ba2017-08-04 00:07:45 +01002362 u64_stats_init(&priv->syncp);
2363
Florian Fainellid1565762017-10-11 10:57:50 -07002364 priv->dsa_notifier.notifier_call = bcm_sysport_dsa_notifier;
2365
2366 ret = register_dsa_notifier(&priv->dsa_notifier);
2367 if (ret) {
2368 dev_err(&pdev->dev, "failed to register DSA notifier\n");
2369 goto err_deregister_fixed_link;
2370 }
2371
Florian Fainelli80105be2014-04-24 18:08:57 -07002372 ret = register_netdev(dev);
2373 if (ret) {
2374 dev_err(&pdev->dev, "failed to register net_device\n");
Florian Fainellid1565762017-10-11 10:57:50 -07002375 goto err_deregister_notifier;
Florian Fainelli80105be2014-04-24 18:08:57 -07002376 }
2377
2378 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
2379 dev_info(&pdev->dev,
Florian Fainelli44a45242017-01-20 11:08:27 -08002380 "Broadcom SYSTEMPORT%s" REV_FMT
Florian Fainelli23acb2f2014-07-09 17:36:46 -07002381 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
Florian Fainelli44a45242017-01-20 11:08:27 -08002382 priv->is_lite ? " Lite" : "",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07002383 (priv->rev >> 8) & 0xff, priv->rev & 0xff,
2384 priv->base, priv->irq0, priv->irq1, txq, rxq);
Florian Fainelli80105be2014-04-24 18:08:57 -07002385
2386 return 0;
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002387
Florian Fainellid1565762017-10-11 10:57:50 -07002388err_deregister_notifier:
2389 unregister_dsa_notifier(&priv->dsa_notifier);
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002390err_deregister_fixed_link:
2391 if (of_phy_is_fixed_link(dn))
2392 of_phy_deregister_fixed_link(dn);
2393err_free_netdev:
Florian Fainelli80105be2014-04-24 18:08:57 -07002394 free_netdev(dev);
2395 return ret;
2396}
2397
2398static int bcm_sysport_remove(struct platform_device *pdev)
2399{
2400 struct net_device *dev = dev_get_drvdata(&pdev->dev);
Florian Fainellid1565762017-10-11 10:57:50 -07002401 struct bcm_sysport_priv *priv = netdev_priv(dev);
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002402 struct device_node *dn = pdev->dev.of_node;
Florian Fainelli80105be2014-04-24 18:08:57 -07002403
2404 /* Not much to do, ndo_close has been called
2405 * and we use managed allocations
2406 */
Florian Fainellid1565762017-10-11 10:57:50 -07002407 unregister_dsa_notifier(&priv->dsa_notifier);
Florian Fainelli80105be2014-04-24 18:08:57 -07002408 unregister_netdev(dev);
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002409 if (of_phy_is_fixed_link(dn))
2410 of_phy_deregister_fixed_link(dn);
Florian Fainelli80105be2014-04-24 18:08:57 -07002411 free_netdev(dev);
2412 dev_set_drvdata(&pdev->dev, NULL);
2413
2414 return 0;
2415}
2416
Florian Fainelli40755a02014-07-01 21:08:38 -07002417#ifdef CONFIG_PM_SLEEP
Florian Fainelli83e82f42014-07-01 21:08:40 -07002418static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv)
2419{
2420 struct net_device *ndev = priv->netdev;
2421 unsigned int timeout = 1000;
2422 u32 reg;
2423
2424 /* Password has already been programmed */
2425 reg = umac_readl(priv, UMAC_MPD_CTRL);
2426 reg |= MPD_EN;
2427 reg &= ~PSW_EN;
2428 if (priv->wolopts & WAKE_MAGICSECURE)
2429 reg |= PSW_EN;
2430 umac_writel(priv, reg, UMAC_MPD_CTRL);
2431
2432 /* Make sure RBUF entered WoL mode as result */
2433 do {
2434 reg = rbuf_readl(priv, RBUF_STATUS);
2435 if (reg & RBUF_WOL_MODE)
2436 break;
2437
2438 udelay(10);
2439 } while (timeout-- > 0);
2440
2441 /* Do not leave the UniMAC RBUF matching only MPD packets */
2442 if (!timeout) {
2443 reg = umac_readl(priv, UMAC_MPD_CTRL);
2444 reg &= ~MPD_EN;
2445 umac_writel(priv, reg, UMAC_MPD_CTRL);
2446 netif_err(priv, wol, ndev, "failed to enter WOL mode\n");
2447 return -ETIMEDOUT;
2448 }
2449
2450 /* UniMAC receive needs to be turned on */
2451 umac_enable_set(priv, CMD_RX_EN, 1);
2452
2453 /* Enable the interrupt wake-up source */
2454 intrl2_0_mask_clear(priv, INTRL2_0_MPD);
2455
2456 netif_dbg(priv, wol, ndev, "entered WOL mode\n");
2457
2458 return 0;
2459}
2460
Florian Fainelli40755a02014-07-01 21:08:38 -07002461static int bcm_sysport_suspend(struct device *d)
2462{
2463 struct net_device *dev = dev_get_drvdata(d);
2464 struct bcm_sysport_priv *priv = netdev_priv(dev);
2465 unsigned int i;
Florian Fainelli83e82f42014-07-01 21:08:40 -07002466 int ret = 0;
Florian Fainelli40755a02014-07-01 21:08:38 -07002467 u32 reg;
2468
2469 if (!netif_running(dev))
2470 return 0;
2471
2472 bcm_sysport_netif_stop(dev);
2473
Philippe Reynes715a0222016-06-19 20:39:08 +02002474 phy_suspend(dev->phydev);
Florian Fainelli40755a02014-07-01 21:08:38 -07002475
2476 netif_device_detach(dev);
2477
2478 /* Disable UniMAC RX */
2479 umac_enable_set(priv, CMD_RX_EN, 0);
2480
2481 ret = rdma_enable_set(priv, 0);
2482 if (ret) {
2483 netdev_err(dev, "RDMA timeout!\n");
2484 return ret;
2485 }
2486
2487 /* Disable RXCHK if enabled */
Florian Fainelli9d34c1c2014-07-01 21:08:39 -07002488 if (priv->rx_chk_en) {
Florian Fainelli40755a02014-07-01 21:08:38 -07002489 reg = rxchk_readl(priv, RXCHK_CONTROL);
2490 reg &= ~RXCHK_EN;
2491 rxchk_writel(priv, reg, RXCHK_CONTROL);
2492 }
2493
2494 /* Flush RX pipe */
Florian Fainelli83e82f42014-07-01 21:08:40 -07002495 if (!priv->wolopts)
2496 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
Florian Fainelli40755a02014-07-01 21:08:38 -07002497
2498 ret = tdma_enable_set(priv, 0);
2499 if (ret) {
2500 netdev_err(dev, "TDMA timeout!\n");
2501 return ret;
2502 }
2503
2504 /* Wait for a packet boundary */
2505 usleep_range(2000, 3000);
2506
2507 umac_enable_set(priv, CMD_TX_EN, 0);
2508
2509 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
2510
2511 /* Free RX/TX rings SW structures */
2512 for (i = 0; i < dev->num_tx_queues; i++)
2513 bcm_sysport_fini_tx_ring(priv, i);
2514 bcm_sysport_fini_rx_ring(priv);
2515
Florian Fainelli83e82f42014-07-01 21:08:40 -07002516 /* Get prepared for Wake-on-LAN */
2517 if (device_may_wakeup(d) && priv->wolopts)
2518 ret = bcm_sysport_suspend_to_wol(priv);
2519
2520 return ret;
Florian Fainelli40755a02014-07-01 21:08:38 -07002521}
2522
2523static int bcm_sysport_resume(struct device *d)
2524{
2525 struct net_device *dev = dev_get_drvdata(d);
2526 struct bcm_sysport_priv *priv = netdev_priv(dev);
2527 unsigned int i;
2528 u32 reg;
2529 int ret;
2530
2531 if (!netif_running(dev))
2532 return 0;
2533
Florian Fainelli704d33e2014-10-28 11:12:01 -07002534 umac_reset(priv);
2535
Florian Fainelli83e82f42014-07-01 21:08:40 -07002536 /* We may have been suspended and never received a WOL event that
2537 * would turn off MPD detection, take care of that now
2538 */
2539 bcm_sysport_resume_from_wol(priv);
2540
Florian Fainelli40755a02014-07-01 21:08:38 -07002541 /* Initialize both hardware and software ring */
2542 for (i = 0; i < dev->num_tx_queues; i++) {
2543 ret = bcm_sysport_init_tx_ring(priv, i);
2544 if (ret) {
2545 netdev_err(dev, "failed to initialize TX ring %d\n",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07002546 i);
Florian Fainelli40755a02014-07-01 21:08:38 -07002547 goto out_free_tx_rings;
2548 }
2549 }
2550
2551 /* Initialize linked-list */
2552 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
2553
2554 /* Initialize RX ring */
2555 ret = bcm_sysport_init_rx_ring(priv);
2556 if (ret) {
2557 netdev_err(dev, "failed to initialize RX ring\n");
2558 goto out_free_rx_ring;
2559 }
2560
2561 netif_device_attach(dev);
2562
Florian Fainelli40755a02014-07-01 21:08:38 -07002563 /* RX pipe enable */
2564 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
2565
2566 ret = rdma_enable_set(priv, 1);
2567 if (ret) {
2568 netdev_err(dev, "failed to enable RDMA\n");
2569 goto out_free_rx_ring;
2570 }
2571
2572 /* Enable rxhck */
Florian Fainelli9d34c1c2014-07-01 21:08:39 -07002573 if (priv->rx_chk_en) {
Florian Fainelli40755a02014-07-01 21:08:38 -07002574 reg = rxchk_readl(priv, RXCHK_CONTROL);
2575 reg |= RXCHK_EN;
2576 rxchk_writel(priv, reg, RXCHK_CONTROL);
2577 }
2578
2579 rbuf_init(priv);
2580
2581 /* Set maximum frame length */
Florian Fainelli44a45242017-01-20 11:08:27 -08002582 if (!priv->is_lite)
2583 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2584 else
2585 gib_set_pad_extension(priv);
Florian Fainelli40755a02014-07-01 21:08:38 -07002586
2587 /* Set MAC address */
2588 umac_set_hw_addr(priv, dev->dev_addr);
2589
2590 umac_enable_set(priv, CMD_RX_EN, 1);
2591
2592 /* TX pipe enable */
2593 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
2594
2595 umac_enable_set(priv, CMD_TX_EN, 1);
2596
2597 ret = tdma_enable_set(priv, 1);
2598 if (ret) {
2599 netdev_err(dev, "TDMA timeout!\n");
2600 goto out_free_rx_ring;
2601 }
2602
Philippe Reynes715a0222016-06-19 20:39:08 +02002603 phy_resume(dev->phydev);
Florian Fainelli40755a02014-07-01 21:08:38 -07002604
2605 bcm_sysport_netif_start(dev);
2606
2607 return 0;
2608
2609out_free_rx_ring:
2610 bcm_sysport_fini_rx_ring(priv);
2611out_free_tx_rings:
2612 for (i = 0; i < dev->num_tx_queues; i++)
2613 bcm_sysport_fini_tx_ring(priv, i);
2614 return ret;
2615}
2616#endif
2617
2618static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops,
2619 bcm_sysport_suspend, bcm_sysport_resume);
2620
Florian Fainelli80105be2014-04-24 18:08:57 -07002621static struct platform_driver bcm_sysport_driver = {
2622 .probe = bcm_sysport_probe,
2623 .remove = bcm_sysport_remove,
2624 .driver = {
2625 .name = "brcm-systemport",
Florian Fainelli80105be2014-04-24 18:08:57 -07002626 .of_match_table = bcm_sysport_of_match,
Florian Fainelli40755a02014-07-01 21:08:38 -07002627 .pm = &bcm_sysport_pm_ops,
Florian Fainelli80105be2014-04-24 18:08:57 -07002628 },
2629};
2630module_platform_driver(bcm_sysport_driver);
2631
2632MODULE_AUTHOR("Broadcom Corporation");
2633MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
2634MODULE_ALIAS("platform:brcm-systemport");
2635MODULE_LICENSE("GPL");