blob: 532e7933d606fdbdde77aacdb2de746f249d2bf2 [file] [log] [blame]
Ingo Molnar9f4c8152008-01-30 13:33:41 +01001/*
2 * Copyright 2002 Andi Kleen, SuSE Labs.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Thanks to Ben LaHaise for precious feedback.
Ingo Molnar9f4c8152008-01-30 13:33:41 +01004 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005#include <linux/highmem.h>
Ingo Molnar81922062008-01-30 13:34:04 +01006#include <linux/bootmem.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#include <linux/module.h>
Ingo Molnar9f4c8152008-01-30 13:33:41 +01008#include <linux/sched.h>
Ingo Molnar9f4c8152008-01-30 13:33:41 +01009#include <linux/mm.h>
Thomas Gleixner76ebd052008-02-09 23:24:09 +010010#include <linux/interrupt.h>
Thomas Gleixneree7ae7a2008-04-17 17:40:45 +020011#include <linux/seq_file.h>
12#include <linux/debugfs.h>
Tejun Heoe59a1bb2009-06-22 11:56:24 +090013#include <linux/pfn.h>
Tejun Heo8c4bfc62009-07-04 08:10:59 +090014#include <linux/percpu.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/gfp.h>
Ingo Molnar9f4c8152008-01-30 13:33:41 +010016
Thomas Gleixner950f9d92008-01-30 13:34:06 +010017#include <asm/e820.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <asm/processor.h>
19#include <asm/tlbflush.h>
Dave Jonesf8af0952006-01-06 00:12:10 -080020#include <asm/sections.h>
Jeremy Fitzhardinge93dbda72009-02-26 17:35:44 -080021#include <asm/setup.h>
Ingo Molnar9f4c8152008-01-30 13:33:41 +010022#include <asm/uaccess.h>
23#include <asm/pgalloc.h>
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +010024#include <asm/proto.h>
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -070025#include <asm/pat.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Ingo Molnar9df84992008-02-04 16:48:09 +010027/*
28 * The current flushing context - we pass it instead of 5 arguments:
29 */
Thomas Gleixner72e458d2008-02-04 16:48:07 +010030struct cpa_data {
Shaohua Lid75586a2008-08-21 10:46:06 +080031 unsigned long *vaddr;
Thomas Gleixner72e458d2008-02-04 16:48:07 +010032 pgprot_t mask_set;
33 pgprot_t mask_clr;
Thomas Gleixner65e074d2008-02-04 16:48:07 +010034 int numpages;
Shaohua Lid75586a2008-08-21 10:46:06 +080035 int flags;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +010036 unsigned long pfn;
Andi Kleenc9caa022008-03-12 03:53:29 +010037 unsigned force_split : 1;
Shaohua Lid75586a2008-08-21 10:46:06 +080038 int curpage;
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -070039 struct page **pages;
Thomas Gleixner72e458d2008-02-04 16:48:07 +010040};
41
Suresh Siddhaad5ca552008-09-23 14:00:42 -070042/*
43 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
44 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
45 * entries change the page attribute in parallel to some other cpu
46 * splitting a large page entry along with changing the attribute.
47 */
48static DEFINE_SPINLOCK(cpa_lock);
49
Shaohua Lid75586a2008-08-21 10:46:06 +080050#define CPA_FLUSHTLB 1
51#define CPA_ARRAY 2
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -070052#define CPA_PAGES_ARRAY 4
Shaohua Lid75586a2008-08-21 10:46:06 +080053
Thomas Gleixner65280e62008-05-05 16:35:21 +020054#ifdef CONFIG_PROC_FS
Andi Kleence0c0e52008-05-02 11:46:49 +020055static unsigned long direct_pages_count[PG_LEVEL_NUM];
56
Thomas Gleixner65280e62008-05-05 16:35:21 +020057void update_page_count(int level, unsigned long pages)
Andi Kleence0c0e52008-05-02 11:46:49 +020058{
Andi Kleence0c0e52008-05-02 11:46:49 +020059 unsigned long flags;
Thomas Gleixner65280e62008-05-05 16:35:21 +020060
Andi Kleence0c0e52008-05-02 11:46:49 +020061 /* Protect against CPA */
62 spin_lock_irqsave(&pgd_lock, flags);
63 direct_pages_count[level] += pages;
64 spin_unlock_irqrestore(&pgd_lock, flags);
Andi Kleence0c0e52008-05-02 11:46:49 +020065}
66
Thomas Gleixner65280e62008-05-05 16:35:21 +020067static void split_page_count(int level)
68{
69 direct_pages_count[level]--;
70 direct_pages_count[level - 1] += PTRS_PER_PTE;
71}
72
Alexey Dobriyane1759c22008-10-15 23:50:22 +040073void arch_report_meminfo(struct seq_file *m)
Thomas Gleixner65280e62008-05-05 16:35:21 +020074{
Hugh Dickinsb9c3bfc2008-11-06 12:05:40 +000075 seq_printf(m, "DirectMap4k: %8lu kB\n",
Hugh Dickinsa06de632008-08-15 13:58:32 +010076 direct_pages_count[PG_LEVEL_4K] << 2);
77#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
Hugh Dickinsb9c3bfc2008-11-06 12:05:40 +000078 seq_printf(m, "DirectMap2M: %8lu kB\n",
Hugh Dickinsa06de632008-08-15 13:58:32 +010079 direct_pages_count[PG_LEVEL_2M] << 11);
80#else
Hugh Dickinsb9c3bfc2008-11-06 12:05:40 +000081 seq_printf(m, "DirectMap4M: %8lu kB\n",
Hugh Dickinsa06de632008-08-15 13:58:32 +010082 direct_pages_count[PG_LEVEL_2M] << 12);
83#endif
Thomas Gleixner65280e62008-05-05 16:35:21 +020084#ifdef CONFIG_X86_64
Hugh Dickinsa06de632008-08-15 13:58:32 +010085 if (direct_gbpages)
Hugh Dickinsb9c3bfc2008-11-06 12:05:40 +000086 seq_printf(m, "DirectMap1G: %8lu kB\n",
Hugh Dickinsa06de632008-08-15 13:58:32 +010087 direct_pages_count[PG_LEVEL_1G] << 20);
Thomas Gleixner65280e62008-05-05 16:35:21 +020088#endif
Thomas Gleixner65280e62008-05-05 16:35:21 +020089}
90#else
91static inline void split_page_count(int level) { }
92#endif
93
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +010094#ifdef CONFIG_X86_64
95
96static inline unsigned long highmap_start_pfn(void)
97{
98 return __pa(_text) >> PAGE_SHIFT;
99}
100
101static inline unsigned long highmap_end_pfn(void)
102{
Jeremy Fitzhardinge93dbda72009-02-26 17:35:44 -0800103 return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100104}
105
106#endif
107
Ingo Molnar92cb54a2008-02-13 14:37:52 +0100108#ifdef CONFIG_DEBUG_PAGEALLOC
109# define debug_pagealloc 1
110#else
111# define debug_pagealloc 0
112#endif
113
Arjan van de Vened724be2008-01-30 13:34:04 +0100114static inline int
115within(unsigned long addr, unsigned long start, unsigned long end)
Ingo Molnar687c4822008-01-30 13:34:04 +0100116{
Arjan van de Vened724be2008-01-30 13:34:04 +0100117 return addr >= start && addr < end;
118}
119
120/*
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100121 * Flushing functions
122 */
Thomas Gleixnercd8ddf12008-01-30 13:34:08 +0100123
Thomas Gleixnercd8ddf12008-01-30 13:34:08 +0100124/**
125 * clflush_cache_range - flush a cache range with clflush
126 * @addr: virtual start address
127 * @size: number of bytes to flush
128 *
129 * clflush is an unordered instruction which needs fencing with mfence
130 * to avoid ordering issues.
131 */
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100132void clflush_cache_range(void *vaddr, unsigned int size)
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100133{
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100134 void *vend = vaddr + size - 1;
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100135
Thomas Gleixnercd8ddf12008-01-30 13:34:08 +0100136 mb();
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100137
138 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
139 clflush(vaddr);
140 /*
141 * Flush any possible final partial cacheline:
142 */
143 clflush(vend);
144
Thomas Gleixnercd8ddf12008-01-30 13:34:08 +0100145 mb();
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100146}
Eric Anholte517a5e2009-09-10 17:48:48 -0700147EXPORT_SYMBOL_GPL(clflush_cache_range);
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100148
Thomas Gleixneraf1e6842008-01-30 13:34:08 +0100149static void __cpa_flush_all(void *arg)
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100150{
Andi Kleen6bb83832008-02-04 16:48:06 +0100151 unsigned long cache = (unsigned long)arg;
152
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100153 /*
154 * Flush all to work around Errata in early athlons regarding
155 * large page flushing.
156 */
157 __flush_tlb_all();
158
venkatesh.pallipadi@intel.com0b827532009-05-22 13:23:37 -0700159 if (cache && boot_cpu_data.x86 >= 4)
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100160 wbinvd();
161}
162
Andi Kleen6bb83832008-02-04 16:48:06 +0100163static void cpa_flush_all(unsigned long cache)
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100164{
165 BUG_ON(irqs_disabled());
166
Jens Axboe15c8b6c2008-05-09 09:39:44 +0200167 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100168}
169
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100170static void __cpa_flush_range(void *arg)
171{
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100172 /*
173 * We could optimize that further and do individual per page
174 * tlb invalidates for a low number of pages. Caveat: we must
175 * flush the high aliases on 64bit as well.
176 */
177 __flush_tlb_all();
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100178}
179
Andi Kleen6bb83832008-02-04 16:48:06 +0100180static void cpa_flush_range(unsigned long start, int numpages, int cache)
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100181{
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100182 unsigned int i, level;
183 unsigned long addr;
184
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100185 BUG_ON(irqs_disabled());
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100186 WARN_ON(PAGE_ALIGN(start) != start);
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100187
Jens Axboe15c8b6c2008-05-09 09:39:44 +0200188 on_each_cpu(__cpa_flush_range, NULL, 1);
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100189
Andi Kleen6bb83832008-02-04 16:48:06 +0100190 if (!cache)
191 return;
192
Thomas Gleixner3b233e52008-01-30 13:34:08 +0100193 /*
194 * We only need to flush on one CPU,
195 * clflush is a MESI-coherent instruction that
196 * will cause all other CPUs to flush the same
197 * cachelines:
198 */
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100199 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
200 pte_t *pte = lookup_address(addr, &level);
201
202 /*
203 * Only flush present addresses:
204 */
Thomas Gleixner7bfb72e2008-02-04 16:48:08 +0100205 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100206 clflush_cache_range((void *) addr, PAGE_SIZE);
207 }
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100208}
209
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700210static void cpa_flush_array(unsigned long *start, int numpages, int cache,
211 int in_flags, struct page **pages)
Shaohua Lid75586a2008-08-21 10:46:06 +0800212{
213 unsigned int i, level;
Pallipadi, Venkatesh21717872009-05-26 10:33:35 -0700214 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
Shaohua Lid75586a2008-08-21 10:46:06 +0800215
216 BUG_ON(irqs_disabled());
217
Pallipadi, Venkatesh21717872009-05-26 10:33:35 -0700218 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
Shaohua Lid75586a2008-08-21 10:46:06 +0800219
Pallipadi, Venkatesh21717872009-05-26 10:33:35 -0700220 if (!cache || do_wbinvd)
Shaohua Lid75586a2008-08-21 10:46:06 +0800221 return;
222
Shaohua Lid75586a2008-08-21 10:46:06 +0800223 /*
224 * We only need to flush on one CPU,
225 * clflush is a MESI-coherent instruction that
226 * will cause all other CPUs to flush the same
227 * cachelines:
228 */
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700229 for (i = 0; i < numpages; i++) {
230 unsigned long addr;
231 pte_t *pte;
232
233 if (in_flags & CPA_PAGES_ARRAY)
234 addr = (unsigned long)page_address(pages[i]);
235 else
236 addr = start[i];
237
238 pte = lookup_address(addr, &level);
Shaohua Lid75586a2008-08-21 10:46:06 +0800239
240 /*
241 * Only flush present addresses:
242 */
243 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700244 clflush_cache_range((void *)addr, PAGE_SIZE);
Shaohua Lid75586a2008-08-21 10:46:06 +0800245 }
246}
247
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100248/*
Arjan van de Vened724be2008-01-30 13:34:04 +0100249 * Certain areas of memory on x86 require very specific protection flags,
250 * for example the BIOS area or kernel text. Callers don't always get this
251 * right (again, ioremap() on BIOS memory is not uncommon) so this function
252 * checks and fixes these known static required protection bits.
253 */
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100254static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
255 unsigned long pfn)
Arjan van de Vened724be2008-01-30 13:34:04 +0100256{
257 pgprot_t forbidden = __pgprot(0);
258
Ingo Molnar687c4822008-01-30 13:34:04 +0100259 /*
Arjan van de Vened724be2008-01-30 13:34:04 +0100260 * The BIOS area between 640k and 1Mb needs to be executable for
261 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
Ingo Molnar687c4822008-01-30 13:34:04 +0100262 */
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100263 if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
Arjan van de Vened724be2008-01-30 13:34:04 +0100264 pgprot_val(forbidden) |= _PAGE_NX;
265
266 /*
267 * The kernel text needs to be executable for obvious reasons
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100268 * Does not cover __inittext since that is gone later on. On
269 * 64bit we do not enforce !NX on the low mapping
Arjan van de Vened724be2008-01-30 13:34:04 +0100270 */
271 if (within(address, (unsigned long)_text, (unsigned long)_etext))
272 pgprot_val(forbidden) |= _PAGE_NX;
Arjan van de Vencc0f21b2008-02-04 16:48:05 +0100273
Arjan van de Vencc0f21b2008-02-04 16:48:05 +0100274 /*
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100275 * The .rodata section needs to be read-only. Using the pfn
276 * catches all aliases.
Arjan van de Vencc0f21b2008-02-04 16:48:05 +0100277 */
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100278 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
279 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
Arjan van de Vencc0f21b2008-02-04 16:48:05 +0100280 pgprot_val(forbidden) |= _PAGE_RW;
Arjan van de Vened724be2008-01-30 13:34:04 +0100281
Suresh Siddha55ca3cc2009-10-28 18:46:57 -0800282#if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
Suresh Siddha74e08172009-10-14 14:46:56 -0700283 /*
Suresh Siddha502f6602009-10-28 18:46:56 -0800284 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
285 * kernel text mappings for the large page aligned text, rodata sections
286 * will be always read-only. For the kernel identity mappings covering
287 * the holes caused by this alignment can be anything that user asks.
Suresh Siddha74e08172009-10-14 14:46:56 -0700288 *
289 * This will preserve the large page mappings for kernel text/data
290 * at no extra cost.
291 */
Suresh Siddha502f6602009-10-28 18:46:56 -0800292 if (kernel_set_to_readonly &&
293 within(address, (unsigned long)_text,
Suresh Siddha281ff332010-02-18 11:51:40 -0800294 (unsigned long)__end_rodata_hpage_align)) {
295 unsigned int level;
296
297 /*
298 * Don't enforce the !RW mapping for the kernel text mapping,
299 * if the current mapping is already using small page mapping.
300 * No need to work hard to preserve large page mappings in this
301 * case.
302 *
303 * This also fixes the Linux Xen paravirt guest boot failure
304 * (because of unexpected read-only mappings for kernel identity
305 * mappings). In this paravirt guest case, the kernel text
306 * mapping and the kernel identity mapping share the same
307 * page-table pages. Thus we can't really use different
308 * protections for the kernel text and identity mappings. Also,
309 * these shared mappings are made of small page mappings.
310 * Thus this don't enforce !RW mapping for small page kernel
311 * text mapping logic will help Linux Xen parvirt guest boot
312 * aswell.
313 */
314 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
315 pgprot_val(forbidden) |= _PAGE_RW;
316 }
Suresh Siddha74e08172009-10-14 14:46:56 -0700317#endif
318
Arjan van de Vened724be2008-01-30 13:34:04 +0100319 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
Ingo Molnar687c4822008-01-30 13:34:04 +0100320
321 return prot;
322}
323
Thomas Gleixner9a14aef2008-02-04 16:48:07 +0100324/*
325 * Lookup the page table entry for a virtual address. Return a pointer
326 * to the entry and the level of the mapping.
327 *
328 * Note: We return pud and pmd either when the entry is marked large
329 * or when the present bit is not set. Otherwise we would return a
330 * pointer to a nonexisting mapping.
331 */
Harvey Harrisonda7bfc52008-02-09 23:24:08 +0100332pte_t *lookup_address(unsigned long address, unsigned int *level)
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100333{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334 pgd_t *pgd = pgd_offset_k(address);
335 pud_t *pud;
336 pmd_t *pmd;
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100337
Thomas Gleixner30551bb2008-01-30 13:34:04 +0100338 *level = PG_LEVEL_NONE;
339
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 if (pgd_none(*pgd))
341 return NULL;
Ingo Molnar9df84992008-02-04 16:48:09 +0100342
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 pud = pud_offset(pgd, address);
344 if (pud_none(*pud))
345 return NULL;
Andi Kleenc2f71ee2008-02-04 16:48:09 +0100346
347 *level = PG_LEVEL_1G;
348 if (pud_large(*pud) || !pud_present(*pud))
349 return (pte_t *)pud;
350
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 pmd = pmd_offset(pud, address);
352 if (pmd_none(*pmd))
353 return NULL;
Thomas Gleixner30551bb2008-01-30 13:34:04 +0100354
355 *level = PG_LEVEL_2M;
Thomas Gleixner9a14aef2008-02-04 16:48:07 +0100356 if (pmd_large(*pmd) || !pmd_present(*pmd))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 return (pte_t *)pmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358
Thomas Gleixner30551bb2008-01-30 13:34:04 +0100359 *level = PG_LEVEL_4K;
Ingo Molnar9df84992008-02-04 16:48:09 +0100360
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100361 return pte_offset_kernel(pmd, address);
362}
Pekka Paalanen75bb8832008-05-12 21:20:56 +0200363EXPORT_SYMBOL_GPL(lookup_address);
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100364
Ingo Molnar9df84992008-02-04 16:48:09 +0100365/*
366 * Set the new pmd in all the pgds we know about:
367 */
Ingo Molnar9a3dc782008-01-30 13:33:57 +0100368static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100369{
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100370 /* change init_mm */
371 set_pte_atomic(kpte, pte);
Ingo Molnar44af6c42008-01-30 13:34:03 +0100372#ifdef CONFIG_X86_32
Ingo Molnare4b71dc2008-01-30 13:34:04 +0100373 if (!SHARED_KERNEL_PMD) {
Ingo Molnar44af6c42008-01-30 13:34:03 +0100374 struct page *page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375
Jeremy Fitzhardingee3ed9102008-01-30 13:34:11 +0100376 list_for_each_entry(page, &pgd_list, lru) {
Ingo Molnar44af6c42008-01-30 13:34:03 +0100377 pgd_t *pgd;
378 pud_t *pud;
379 pmd_t *pmd;
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100380
Ingo Molnar44af6c42008-01-30 13:34:03 +0100381 pgd = (pgd_t *)page_address(page) + pgd_index(address);
382 pud = pud_offset(pgd, address);
383 pmd = pmd_offset(pud, address);
384 set_pte_atomic((pte_t *)pmd, pte);
385 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 }
Ingo Molnar44af6c42008-01-30 13:34:03 +0100387#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388}
389
Ingo Molnar9df84992008-02-04 16:48:09 +0100390static int
391try_preserve_large_page(pte_t *kpte, unsigned long address,
392 struct cpa_data *cpa)
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100393{
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100394 unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100395 pte_t new_pte, old_pte, *tmp;
396 pgprot_t old_prot, new_prot;
Thomas Gleixnerfac84932008-02-09 23:24:09 +0100397 int i, do_split = 1;
Harvey Harrisonda7bfc52008-02-09 23:24:08 +0100398 unsigned int level;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100399
Andi Kleenc9caa022008-03-12 03:53:29 +0100400 if (cpa->force_split)
401 return 1;
402
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100403 spin_lock_irqsave(&pgd_lock, flags);
404 /*
405 * Check for races, another CPU might have split this page
406 * up already:
407 */
408 tmp = lookup_address(address, &level);
409 if (tmp != kpte)
410 goto out_unlock;
411
412 switch (level) {
413 case PG_LEVEL_2M:
Andi Kleen31422c52008-02-04 16:48:08 +0100414 psize = PMD_PAGE_SIZE;
415 pmask = PMD_PAGE_MASK;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100416 break;
Andi Kleenf07333f2008-02-04 16:48:09 +0100417#ifdef CONFIG_X86_64
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100418 case PG_LEVEL_1G:
Andi Kleen5d3c8b22008-02-13 16:20:35 +0100419 psize = PUD_PAGE_SIZE;
420 pmask = PUD_PAGE_MASK;
Andi Kleenf07333f2008-02-04 16:48:09 +0100421 break;
422#endif
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100423 default:
Ingo Molnarbeaff632008-02-04 16:48:09 +0100424 do_split = -EINVAL;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100425 goto out_unlock;
426 }
427
428 /*
429 * Calculate the number of pages, which fit into this large
430 * page starting at address:
431 */
432 nextpage_addr = (address + psize) & pmask;
433 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100434 if (numpages < cpa->numpages)
435 cpa->numpages = numpages;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100436
437 /*
438 * We are safe now. Check whether the new pgprot is the same:
439 */
440 old_pte = *kpte;
441 old_prot = new_prot = pte_pgprot(old_pte);
442
443 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
444 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100445
446 /*
447 * old_pte points to the large page base address. So we need
448 * to add the offset of the virtual address:
449 */
450 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
451 cpa->pfn = pfn;
452
453 new_prot = static_protections(new_prot, address, pfn);
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100454
455 /*
Thomas Gleixnerfac84932008-02-09 23:24:09 +0100456 * We need to check the full range, whether
457 * static_protection() requires a different pgprot for one of
458 * the pages in the range we try to preserve:
459 */
460 addr = address + PAGE_SIZE;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100461 pfn++;
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100462 for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100463 pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
Thomas Gleixnerfac84932008-02-09 23:24:09 +0100464
465 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
466 goto out_unlock;
467 }
468
469 /*
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100470 * If there are no changes, return. maxpages has been updated
471 * above:
472 */
473 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
Ingo Molnarbeaff632008-02-04 16:48:09 +0100474 do_split = 0;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100475 goto out_unlock;
476 }
477
478 /*
479 * We need to change the attributes. Check, whether we can
480 * change the large page in one go. We request a split, when
481 * the address is not aligned and the number of pages is
482 * smaller than the number of pages in the large page. Note
483 * that we limited the number of possible pages already to
484 * the number of pages in the large page.
485 */
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100486 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100487 /*
488 * The address is aligned and the number of pages
489 * covers the full page.
490 */
491 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
492 __set_pmd_pte(kpte, address, new_pte);
Shaohua Lid75586a2008-08-21 10:46:06 +0800493 cpa->flags |= CPA_FLUSHTLB;
Ingo Molnarbeaff632008-02-04 16:48:09 +0100494 do_split = 0;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100495 }
496
497out_unlock:
498 spin_unlock_irqrestore(&pgd_lock, flags);
Ingo Molnar9df84992008-02-04 16:48:09 +0100499
Ingo Molnarbeaff632008-02-04 16:48:09 +0100500 return do_split;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100501}
502
Ingo Molnar7afe15b2008-01-30 13:33:57 +0100503static int split_large_page(pte_t *kpte, unsigned long address)
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100504{
Thomas Gleixner7b610ee2008-02-04 16:48:10 +0100505 unsigned long flags, pfn, pfninc = 1;
Ingo Molnar86f03982008-01-30 13:34:09 +0100506 unsigned int i, level;
Ingo Molnar9df84992008-02-04 16:48:09 +0100507 pte_t *pbase, *tmp;
508 pgprot_t ref_prot;
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700509 struct page *base;
510
511 if (!debug_pagealloc)
512 spin_unlock(&cpa_lock);
Vegard Nossum9e730232009-02-22 11:28:25 +0100513 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700514 if (!debug_pagealloc)
515 spin_lock(&cpa_lock);
Suresh Siddha8311eb82008-09-23 14:00:41 -0700516 if (!base)
517 return -ENOMEM;
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100518
Ingo Molnar9a3dc782008-01-30 13:33:57 +0100519 spin_lock_irqsave(&pgd_lock, flags);
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100520 /*
521 * Check for races, another CPU might have split this page
522 * up for us already:
523 */
524 tmp = lookup_address(address, &level);
Ingo Molnar6ce9fc12008-02-04 16:48:08 +0100525 if (tmp != kpte)
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100526 goto out_unlock;
527
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100528 pbase = (pte_t *)page_address(base);
Jeremy Fitzhardinge6944a9c2008-03-17 16:37:01 -0700529 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
Thomas Gleixner07cf89c2008-02-04 16:48:08 +0100530 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
Ingo Molnar7a5714e2009-02-20 17:44:21 +0100531 /*
532 * If we ever want to utilize the PAT bit, we need to
533 * update this function to make sure it's converted from
534 * bit 12 to bit 7 when we cross from the 2MB level to
535 * the 4K level:
536 */
537 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100538
Andi Kleenf07333f2008-02-04 16:48:09 +0100539#ifdef CONFIG_X86_64
540 if (level == PG_LEVEL_1G) {
541 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
542 pgprot_val(ref_prot) |= _PAGE_PSE;
Andi Kleenf07333f2008-02-04 16:48:09 +0100543 }
544#endif
545
Thomas Gleixner63c1dcf2008-02-04 16:48:05 +0100546 /*
547 * Get the target pfn from the original entry:
548 */
549 pfn = pte_pfn(*kpte);
Andi Kleenf07333f2008-02-04 16:48:09 +0100550 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
Thomas Gleixner63c1dcf2008-02-04 16:48:05 +0100551 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100552
Andi Kleence0c0e52008-05-02 11:46:49 +0200553 if (address >= (unsigned long)__va(0) &&
Yinghai Luf361a452008-07-10 20:38:26 -0700554 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
555 split_page_count(level);
556
557#ifdef CONFIG_X86_64
558 if (address >= (unsigned long)__va(1UL<<32) &&
Thomas Gleixner65280e62008-05-05 16:35:21 +0200559 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
560 split_page_count(level);
Yinghai Luf361a452008-07-10 20:38:26 -0700561#endif
Andi Kleence0c0e52008-05-02 11:46:49 +0200562
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100563 /*
Ingo Molnar07a66d72009-02-20 08:04:13 +0100564 * Install the new, split up pagetable.
Huang, Ying4c881ca2008-01-30 13:34:04 +0100565 *
Ingo Molnar07a66d72009-02-20 08:04:13 +0100566 * We use the standard kernel pagetable protections for the new
567 * pagetable protections, the actual ptes set above control the
568 * primary protection behavior:
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100569 */
Ingo Molnar07a66d72009-02-20 08:04:13 +0100570 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
Ingo Molnar211b3d02009-03-10 22:31:03 +0100571
572 /*
573 * Intel Atom errata AAH41 workaround.
574 *
575 * The real fix should be in hw or in a microcode update, but
576 * we also probabilistically try to reduce the window of having
577 * a large TLB mixed with 4K TLBs while instruction fetches are
578 * going on.
579 */
580 __flush_tlb_all();
581
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100582 base = NULL;
583
584out_unlock:
Thomas Gleixnereb5b5f02008-02-09 23:24:09 +0100585 /*
586 * If we dropped out via the lookup_address check under
587 * pgd_lock then stick the page back into the pool:
588 */
Suresh Siddha8311eb82008-09-23 14:00:41 -0700589 if (base)
590 __free_page(base);
Ingo Molnar9a3dc782008-01-30 13:33:57 +0100591 spin_unlock_irqrestore(&pgd_lock, flags);
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100592
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100593 return 0;
594}
595
Suresh Siddhaa1e46212009-01-20 14:20:21 -0800596static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
597 int primary)
598{
599 /*
600 * Ignore all non primary paths.
601 */
602 if (!primary)
603 return 0;
604
605 /*
606 * Ignore the NULL PTE for kernel identity mapping, as it is expected
607 * to have holes.
608 * Also set numpages to '1' indicating that we processed cpa req for
609 * one virtual address page and its pfn. TBD: numpages can be set based
610 * on the initial value and the level returned by lookup_address().
611 */
612 if (within(vaddr, PAGE_OFFSET,
613 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
614 cpa->numpages = 1;
615 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
616 return 0;
617 } else {
618 WARN(1, KERN_WARNING "CPA: called for zero pte. "
619 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
620 *cpa->vaddr);
621
622 return -EFAULT;
623 }
624}
625
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100626static int __change_page_attr(struct cpa_data *cpa, int primary)
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100627{
Shaohua Lid75586a2008-08-21 10:46:06 +0800628 unsigned long address;
Harvey Harrisonda7bfc52008-02-09 23:24:08 +0100629 int do_split, err;
630 unsigned int level;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100631 pte_t *kpte, old_pte;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632
Thomas Hellstrom8523acf2009-08-03 09:25:45 +0200633 if (cpa->flags & CPA_PAGES_ARRAY) {
634 struct page *page = cpa->pages[cpa->curpage];
635 if (unlikely(PageHighMem(page)))
636 return 0;
637 address = (unsigned long)page_address(page);
638 } else if (cpa->flags & CPA_ARRAY)
Shaohua Lid75586a2008-08-21 10:46:06 +0800639 address = cpa->vaddr[cpa->curpage];
640 else
641 address = *cpa->vaddr;
Ingo Molnar97f99fe2008-01-30 13:33:55 +0100642repeat:
Ingo Molnarf0646e42008-01-30 13:33:43 +0100643 kpte = lookup_address(address, &level);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644 if (!kpte)
Suresh Siddhaa1e46212009-01-20 14:20:21 -0800645 return __cpa_process_fault(cpa, address, primary);
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100646
647 old_pte = *kpte;
Suresh Siddhaa1e46212009-01-20 14:20:21 -0800648 if (!pte_val(old_pte))
649 return __cpa_process_fault(cpa, address, primary);
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100650
Thomas Gleixner30551bb2008-01-30 13:34:04 +0100651 if (level == PG_LEVEL_4K) {
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100652 pte_t new_pte;
Arjan van de Ven626c2c92008-02-04 16:48:05 +0100653 pgprot_t new_prot = pte_pgprot(old_pte);
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100654 unsigned long pfn = pte_pfn(old_pte);
Thomas Gleixnera72a08a2008-01-30 13:34:07 +0100655
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100656 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
657 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
Ingo Molnar86f03982008-01-30 13:34:09 +0100658
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100659 new_prot = static_protections(new_prot, address, pfn);
Ingo Molnar86f03982008-01-30 13:34:09 +0100660
Arjan van de Ven626c2c92008-02-04 16:48:05 +0100661 /*
662 * We need to keep the pfn from the existing PTE,
663 * after all we're only going to change it's attributes
664 * not the memory it points to
665 */
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100666 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
667 cpa->pfn = pfn;
Thomas Gleixnerf4ae5da2008-02-04 16:48:07 +0100668 /*
669 * Do we really change anything ?
670 */
671 if (pte_val(old_pte) != pte_val(new_pte)) {
672 set_pte_atomic(kpte, new_pte);
Shaohua Lid75586a2008-08-21 10:46:06 +0800673 cpa->flags |= CPA_FLUSHTLB;
Thomas Gleixnerf4ae5da2008-02-04 16:48:07 +0100674 }
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100675 cpa->numpages = 1;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100676 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677 }
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100678
679 /*
680 * Check, whether we can keep the large page intact
681 * and just change the pte:
682 */
Ingo Molnarbeaff632008-02-04 16:48:09 +0100683 do_split = try_preserve_large_page(kpte, address, cpa);
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100684 /*
685 * When the range fits into the existing large page,
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100686 * return. cp->numpages and cpa->tlbflush have been updated in
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100687 * try_large_page:
688 */
Ingo Molnar87f7f8f2008-02-04 16:48:10 +0100689 if (do_split <= 0)
690 return do_split;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100691
692 /*
693 * We have to split the large page:
694 */
Ingo Molnar87f7f8f2008-02-04 16:48:10 +0100695 err = split_large_page(kpte, address);
696 if (!err) {
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700697 /*
698 * Do a global flush tlb after splitting the large page
699 * and before we do the actual change page attribute in the PTE.
700 *
701 * With out this, we violate the TLB application note, that says
702 * "The TLBs may contain both ordinary and large-page
703 * translations for a 4-KByte range of linear addresses. This
704 * may occur if software modifies the paging structures so that
705 * the page size used for the address range changes. If the two
706 * translations differ with respect to page frame or attributes
707 * (e.g., permissions), processor behavior is undefined and may
708 * be implementation-specific."
709 *
710 * We do this global tlb flush inside the cpa_lock, so that we
711 * don't allow any other cpu, with stale tlb entries change the
712 * page attribute in parallel, that also falls into the
713 * just split large page entry.
714 */
715 flush_tlb_all();
Ingo Molnar87f7f8f2008-02-04 16:48:10 +0100716 goto repeat;
717 }
Ingo Molnarbeaff632008-02-04 16:48:09 +0100718
Ingo Molnar87f7f8f2008-02-04 16:48:10 +0100719 return err;
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100720}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100722static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
723
724static int cpa_process_alias(struct cpa_data *cpa)
Ingo Molnar44af6c42008-01-30 13:34:03 +0100725{
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100726 struct cpa_data alias_cpa;
Tejun Heo992f4c12009-06-22 11:56:24 +0900727 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
Tejun Heoe933a732009-08-14 15:00:53 +0900728 unsigned long vaddr;
Tejun Heo992f4c12009-06-22 11:56:24 +0900729 int ret;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100730
Yinghai Lu965194c2008-07-12 14:31:28 -0700731 if (cpa->pfn >= max_pfn_mapped)
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100732 return 0;
733
Yinghai Luf361a452008-07-10 20:38:26 -0700734#ifdef CONFIG_X86_64
Yinghai Lu965194c2008-07-12 14:31:28 -0700735 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
Yinghai Luf361a452008-07-10 20:38:26 -0700736 return 0;
737#endif
Thomas Gleixnerf34b4392008-02-15 22:17:57 +0100738 /*
739 * No need to redo, when the primary call touched the direct
740 * mapping already:
741 */
Thomas Hellstrom8523acf2009-08-03 09:25:45 +0200742 if (cpa->flags & CPA_PAGES_ARRAY) {
743 struct page *page = cpa->pages[cpa->curpage];
744 if (unlikely(PageHighMem(page)))
745 return 0;
746 vaddr = (unsigned long)page_address(page);
747 } else if (cpa->flags & CPA_ARRAY)
Shaohua Lid75586a2008-08-21 10:46:06 +0800748 vaddr = cpa->vaddr[cpa->curpage];
749 else
750 vaddr = *cpa->vaddr;
751
752 if (!(within(vaddr, PAGE_OFFSET,
Suresh Siddhaa1e46212009-01-20 14:20:21 -0800753 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100754
Thomas Gleixnerf34b4392008-02-15 22:17:57 +0100755 alias_cpa = *cpa;
Tejun Heo992f4c12009-06-22 11:56:24 +0900756 alias_cpa.vaddr = &laddr;
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700757 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
Shaohua Lid75586a2008-08-21 10:46:06 +0800758
Thomas Gleixnerf34b4392008-02-15 22:17:57 +0100759 ret = __change_page_attr_set_clr(&alias_cpa, 0);
Tejun Heo992f4c12009-06-22 11:56:24 +0900760 if (ret)
761 return ret;
Thomas Gleixnerf34b4392008-02-15 22:17:57 +0100762 }
Ingo Molnar44af6c42008-01-30 13:34:03 +0100763
Arjan van de Ven488fd992008-01-30 13:34:07 +0100764#ifdef CONFIG_X86_64
Thomas Gleixner08797502008-01-30 13:34:09 +0100765 /*
Tejun Heo992f4c12009-06-22 11:56:24 +0900766 * If the primary call didn't touch the high mapping already
767 * and the physical address is inside the kernel map, we need
Thomas Gleixner08797502008-01-30 13:34:09 +0100768 * to touch the high mapped kernel as well:
769 */
Tejun Heo992f4c12009-06-22 11:56:24 +0900770 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
771 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
772 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
773 __START_KERNEL_map - phys_base;
774 alias_cpa = *cpa;
775 alias_cpa.vaddr = &temp_cpa_vaddr;
776 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
Thomas Gleixner08797502008-01-30 13:34:09 +0100777
Tejun Heo992f4c12009-06-22 11:56:24 +0900778 /*
779 * The high mapping range is imprecise, so ignore the
780 * return value.
781 */
782 __change_page_attr_set_clr(&alias_cpa, 0);
783 }
Thomas Gleixner08797502008-01-30 13:34:09 +0100784#endif
Tejun Heo992f4c12009-06-22 11:56:24 +0900785
786 return 0;
Ingo Molnar44af6c42008-01-30 13:34:03 +0100787}
788
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100789static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
Thomas Gleixnerff314522008-01-30 13:34:08 +0100790{
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100791 int ret, numpages = cpa->numpages;
Thomas Gleixnerff314522008-01-30 13:34:08 +0100792
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100793 while (numpages) {
794 /*
795 * Store the remaining nr of pages for the large page
796 * preservation check.
797 */
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100798 cpa->numpages = numpages;
Shaohua Lid75586a2008-08-21 10:46:06 +0800799 /* for array changes, we can't use large page */
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700800 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
Shaohua Lid75586a2008-08-21 10:46:06 +0800801 cpa->numpages = 1;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100802
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700803 if (!debug_pagealloc)
804 spin_lock(&cpa_lock);
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100805 ret = __change_page_attr(cpa, checkalias);
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700806 if (!debug_pagealloc)
807 spin_unlock(&cpa_lock);
Thomas Gleixnerff314522008-01-30 13:34:08 +0100808 if (ret)
809 return ret;
Thomas Gleixnerff314522008-01-30 13:34:08 +0100810
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100811 if (checkalias) {
812 ret = cpa_process_alias(cpa);
813 if (ret)
814 return ret;
815 }
816
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100817 /*
818 * Adjust the number of pages with the result of the
819 * CPA operation. Either a large page has been
820 * preserved or a single page update happened.
821 */
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100822 BUG_ON(cpa->numpages > numpages);
823 numpages -= cpa->numpages;
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700824 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
Shaohua Lid75586a2008-08-21 10:46:06 +0800825 cpa->curpage++;
826 else
827 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
828
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100829 }
Thomas Gleixnerff314522008-01-30 13:34:08 +0100830 return 0;
831}
832
Andi Kleen6bb83832008-02-04 16:48:06 +0100833static inline int cache_attr(pgprot_t attr)
834{
835 return pgprot_val(attr) &
836 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
837}
838
Shaohua Lid75586a2008-08-21 10:46:06 +0800839static int change_page_attr_set_clr(unsigned long *addr, int numpages,
Andi Kleenc9caa022008-03-12 03:53:29 +0100840 pgprot_t mask_set, pgprot_t mask_clr,
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700841 int force_split, int in_flag,
842 struct page **pages)
Thomas Gleixnerff314522008-01-30 13:34:08 +0100843{
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100844 struct cpa_data cpa;
Ingo Molnarcacf8902008-08-21 13:46:33 +0200845 int ret, cache, checkalias;
Jack Steinerfa526d02009-09-03 12:56:02 -0500846 unsigned long baddr = 0;
Thomas Gleixner331e4062008-02-04 16:48:06 +0100847
848 /*
849 * Check, if we are requested to change a not supported
850 * feature:
851 */
852 mask_set = canon_pgprot(mask_set);
853 mask_clr = canon_pgprot(mask_clr);
Andi Kleenc9caa022008-03-12 03:53:29 +0100854 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
Thomas Gleixner331e4062008-02-04 16:48:06 +0100855 return 0;
856
Thomas Gleixner69b14152008-02-13 11:04:50 +0100857 /* Ensure we are PAGE_SIZE aligned */
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700858 if (in_flag & CPA_ARRAY) {
Shaohua Lid75586a2008-08-21 10:46:06 +0800859 int i;
860 for (i = 0; i < numpages; i++) {
861 if (addr[i] & ~PAGE_MASK) {
862 addr[i] &= PAGE_MASK;
863 WARN_ON_ONCE(1);
864 }
865 }
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700866 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
867 /*
868 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
869 * No need to cehck in that case
870 */
871 if (*addr & ~PAGE_MASK) {
872 *addr &= PAGE_MASK;
873 /*
874 * People should not be passing in unaligned addresses:
875 */
876 WARN_ON_ONCE(1);
877 }
Jack Steinerfa526d02009-09-03 12:56:02 -0500878 /*
879 * Save address for cache flush. *addr is modified in the call
880 * to __change_page_attr_set_clr() below.
881 */
882 baddr = *addr;
Thomas Gleixner69b14152008-02-13 11:04:50 +0100883 }
884
Nick Piggin5843d9a2008-08-01 03:15:21 +0200885 /* Must avoid aliasing mappings in the highmem code */
886 kmap_flush_unused();
887
Nick Piggindb64fe02008-10-18 20:27:03 -0700888 vm_unmap_aliases();
889
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100890 cpa.vaddr = addr;
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700891 cpa.pages = pages;
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100892 cpa.numpages = numpages;
893 cpa.mask_set = mask_set;
894 cpa.mask_clr = mask_clr;
Shaohua Lid75586a2008-08-21 10:46:06 +0800895 cpa.flags = 0;
896 cpa.curpage = 0;
Andi Kleenc9caa022008-03-12 03:53:29 +0100897 cpa.force_split = force_split;
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100898
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700899 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
900 cpa.flags |= in_flag;
Shaohua Lid75586a2008-08-21 10:46:06 +0800901
Thomas Gleixneraf96e442008-02-15 21:49:46 +0100902 /* No alias checking for _NX bit modifications */
903 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
904
905 ret = __change_page_attr_set_clr(&cpa, checkalias);
Thomas Gleixnerff314522008-01-30 13:34:08 +0100906
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100907 /*
Thomas Gleixnerf4ae5da2008-02-04 16:48:07 +0100908 * Check whether we really changed something:
909 */
Shaohua Lid75586a2008-08-21 10:46:06 +0800910 if (!(cpa.flags & CPA_FLUSHTLB))
Shaohua Li1ac2f7d2008-08-04 14:51:24 +0800911 goto out;
Ingo Molnarcacf8902008-08-21 13:46:33 +0200912
Thomas Gleixnerf4ae5da2008-02-04 16:48:07 +0100913 /*
Andi Kleen6bb83832008-02-04 16:48:06 +0100914 * No need to flush, when we did not set any of the caching
915 * attributes:
916 */
917 cache = cache_attr(mask_set);
918
919 /*
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100920 * On success we use clflush, when the CPU supports it to
921 * avoid the wbindv. If the CPU does not support it and in the
Thomas Gleixneraf1e6842008-01-30 13:34:08 +0100922 * error case we fall back to cpa_flush_all (which uses
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100923 * wbindv):
924 */
Shaohua Lid75586a2008-08-21 10:46:06 +0800925 if (!ret && cpu_has_clflush) {
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700926 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
927 cpa_flush_array(addr, numpages, cache,
928 cpa.flags, pages);
929 } else
Jack Steinerfa526d02009-09-03 12:56:02 -0500930 cpa_flush_range(baddr, numpages, cache);
Shaohua Lid75586a2008-08-21 10:46:06 +0800931 } else
Andi Kleen6bb83832008-02-04 16:48:06 +0100932 cpa_flush_all(cache);
Ingo Molnarcacf8902008-08-21 13:46:33 +0200933
Thomas Gleixner76ebd052008-02-09 23:24:09 +0100934out:
Thomas Gleixnerff314522008-01-30 13:34:08 +0100935 return ret;
936}
937
Shaohua Lid75586a2008-08-21 10:46:06 +0800938static inline int change_page_attr_set(unsigned long *addr, int numpages,
939 pgprot_t mask, int array)
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100940{
Shaohua Lid75586a2008-08-21 10:46:06 +0800941 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700942 (array ? CPA_ARRAY : 0), NULL);
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100943}
944
Shaohua Lid75586a2008-08-21 10:46:06 +0800945static inline int change_page_attr_clear(unsigned long *addr, int numpages,
946 pgprot_t mask, int array)
Thomas Gleixner72932c72008-01-30 13:34:08 +0100947{
Shaohua Lid75586a2008-08-21 10:46:06 +0800948 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700949 (array ? CPA_ARRAY : 0), NULL);
Thomas Gleixner72932c72008-01-30 13:34:08 +0100950}
951
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -0700952static inline int cpa_set_pages_array(struct page **pages, int numpages,
953 pgprot_t mask)
954{
955 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
956 CPA_PAGES_ARRAY, pages);
957}
958
959static inline int cpa_clear_pages_array(struct page **pages, int numpages,
960 pgprot_t mask)
961{
962 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
963 CPA_PAGES_ARRAY, pages);
964}
965
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -0700966int _set_memory_uc(unsigned long addr, int numpages)
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100967{
Suresh Siddhade33c442008-04-25 17:07:22 -0700968 /*
969 * for now UC MINUS. see comments in ioremap_nocache()
970 */
Shaohua Lid75586a2008-08-21 10:46:06 +0800971 return change_page_attr_set(&addr, numpages,
972 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100973}
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -0700974
975int set_memory_uc(unsigned long addr, int numpages)
976{
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -0700977 int ret;
978
Suresh Siddhade33c442008-04-25 17:07:22 -0700979 /*
980 * for now UC MINUS. see comments in ioremap_nocache()
981 */
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -0700982 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
983 _PAGE_CACHE_UC_MINUS, NULL);
984 if (ret)
985 goto out_err;
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -0700986
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -0700987 ret = _set_memory_uc(addr, numpages);
988 if (ret)
989 goto out_free;
990
991 return 0;
992
993out_free:
994 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
995out_err:
996 return ret;
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -0700997}
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100998EXPORT_SYMBOL(set_memory_uc);
999
Pauli Nieminen4f646252010-04-01 12:45:01 +00001000int _set_memory_array(unsigned long *addr, int addrinarray,
1001 unsigned long new_type)
Shaohua Lid75586a2008-08-21 10:46:06 +08001002{
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001003 int i, j;
1004 int ret;
1005
Shaohua Lid75586a2008-08-21 10:46:06 +08001006 /*
1007 * for now UC MINUS. see comments in ioremap_nocache()
1008 */
1009 for (i = 0; i < addrinarray; i++) {
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001010 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
Pauli Nieminen4f646252010-04-01 12:45:01 +00001011 new_type, NULL);
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001012 if (ret)
1013 goto out_free;
Shaohua Lid75586a2008-08-21 10:46:06 +08001014 }
1015
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001016 ret = change_page_attr_set(addr, addrinarray,
Shaohua Lid75586a2008-08-21 10:46:06 +08001017 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
Pauli Nieminen4f646252010-04-01 12:45:01 +00001018
1019 if (!ret && new_type == _PAGE_CACHE_WC)
1020 ret = change_page_attr_set_clr(addr, addrinarray,
1021 __pgprot(_PAGE_CACHE_WC),
1022 __pgprot(_PAGE_CACHE_MASK),
1023 0, CPA_ARRAY, NULL);
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001024 if (ret)
1025 goto out_free;
Rene Hermanc5e147c2008-08-22 01:02:20 +02001026
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001027 return 0;
1028
1029out_free:
1030 for (j = 0; j < i; j++)
1031 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1032
1033 return ret;
Shaohua Lid75586a2008-08-21 10:46:06 +08001034}
Pauli Nieminen4f646252010-04-01 12:45:01 +00001035
1036int set_memory_array_uc(unsigned long *addr, int addrinarray)
1037{
1038 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
1039}
Shaohua Lid75586a2008-08-21 10:46:06 +08001040EXPORT_SYMBOL(set_memory_array_uc);
1041
Pauli Nieminen4f646252010-04-01 12:45:01 +00001042int set_memory_array_wc(unsigned long *addr, int addrinarray)
1043{
1044 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
1045}
1046EXPORT_SYMBOL(set_memory_array_wc);
1047
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001048int _set_memory_wc(unsigned long addr, int numpages)
1049{
venkatesh.pallipadi@intel.com3869c4a2009-04-09 14:26:50 -07001050 int ret;
Pallipadi, Venkateshbdc63402009-07-30 14:43:19 -07001051 unsigned long addr_copy = addr;
1052
venkatesh.pallipadi@intel.com3869c4a2009-04-09 14:26:50 -07001053 ret = change_page_attr_set(&addr, numpages,
1054 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
venkatesh.pallipadi@intel.com3869c4a2009-04-09 14:26:50 -07001055 if (!ret) {
Pallipadi, Venkateshbdc63402009-07-30 14:43:19 -07001056 ret = change_page_attr_set_clr(&addr_copy, numpages,
1057 __pgprot(_PAGE_CACHE_WC),
1058 __pgprot(_PAGE_CACHE_MASK),
1059 0, 0, NULL);
venkatesh.pallipadi@intel.com3869c4a2009-04-09 14:26:50 -07001060 }
1061 return ret;
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001062}
1063
1064int set_memory_wc(unsigned long addr, int numpages)
1065{
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001066 int ret;
1067
Andreas Herrmann499f8f82008-06-10 16:06:21 +02001068 if (!pat_enabled)
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001069 return set_memory_uc(addr, numpages);
1070
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001071 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1072 _PAGE_CACHE_WC, NULL);
1073 if (ret)
1074 goto out_err;
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001075
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001076 ret = _set_memory_wc(addr, numpages);
1077 if (ret)
1078 goto out_free;
1079
1080 return 0;
1081
1082out_free:
1083 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1084out_err:
1085 return ret;
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001086}
1087EXPORT_SYMBOL(set_memory_wc);
1088
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -07001089int _set_memory_wb(unsigned long addr, int numpages)
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001090{
Shaohua Lid75586a2008-08-21 10:46:06 +08001091 return change_page_attr_clear(&addr, numpages,
1092 __pgprot(_PAGE_CACHE_MASK), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001093}
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -07001094
1095int set_memory_wb(unsigned long addr, int numpages)
1096{
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001097 int ret;
1098
1099 ret = _set_memory_wb(addr, numpages);
1100 if (ret)
1101 return ret;
1102
venkatesh.pallipadi@intel.comc15238d2008-08-20 16:45:51 -07001103 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001104 return 0;
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -07001105}
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001106EXPORT_SYMBOL(set_memory_wb);
1107
Shaohua Lid75586a2008-08-21 10:46:06 +08001108int set_memory_array_wb(unsigned long *addr, int addrinarray)
1109{
1110 int i;
venkatesh.pallipadi@intel.coma5593e02009-04-09 14:26:48 -07001111 int ret;
1112
1113 ret = change_page_attr_clear(addr, addrinarray,
1114 __pgprot(_PAGE_CACHE_MASK), 1);
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001115 if (ret)
1116 return ret;
Shaohua Lid75586a2008-08-21 10:46:06 +08001117
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001118 for (i = 0; i < addrinarray; i++)
1119 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
Rene Hermanc5e147c2008-08-22 01:02:20 +02001120
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001121 return 0;
Shaohua Lid75586a2008-08-21 10:46:06 +08001122}
1123EXPORT_SYMBOL(set_memory_array_wb);
1124
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001125int set_memory_x(unsigned long addr, int numpages)
1126{
H. Peter Anvin583140a2009-11-13 15:28:15 -08001127 if (!(__supported_pte_mask & _PAGE_NX))
1128 return 0;
1129
Shaohua Lid75586a2008-08-21 10:46:06 +08001130 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001131}
1132EXPORT_SYMBOL(set_memory_x);
1133
1134int set_memory_nx(unsigned long addr, int numpages)
1135{
H. Peter Anvin583140a2009-11-13 15:28:15 -08001136 if (!(__supported_pte_mask & _PAGE_NX))
1137 return 0;
1138
Shaohua Lid75586a2008-08-21 10:46:06 +08001139 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001140}
1141EXPORT_SYMBOL(set_memory_nx);
1142
1143int set_memory_ro(unsigned long addr, int numpages)
1144{
Shaohua Lid75586a2008-08-21 10:46:06 +08001145 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001146}
Bruce Allana03352d2008-09-29 20:19:22 -07001147EXPORT_SYMBOL_GPL(set_memory_ro);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001148
1149int set_memory_rw(unsigned long addr, int numpages)
1150{
Shaohua Lid75586a2008-08-21 10:46:06 +08001151 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001152}
Bruce Allana03352d2008-09-29 20:19:22 -07001153EXPORT_SYMBOL_GPL(set_memory_rw);
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001154
1155int set_memory_np(unsigned long addr, int numpages)
1156{
Shaohua Lid75586a2008-08-21 10:46:06 +08001157 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001158}
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001159
Andi Kleenc9caa022008-03-12 03:53:29 +01001160int set_memory_4k(unsigned long addr, int numpages)
1161{
Shaohua Lid75586a2008-08-21 10:46:06 +08001162 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -07001163 __pgprot(0), 1, 0, NULL);
Andi Kleenc9caa022008-03-12 03:53:29 +01001164}
1165
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001166int set_pages_uc(struct page *page, int numpages)
1167{
1168 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001169
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001170 return set_memory_uc(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001171}
1172EXPORT_SYMBOL(set_pages_uc);
1173
Pauli Nieminen4f646252010-04-01 12:45:01 +00001174static int _set_pages_array(struct page **pages, int addrinarray,
1175 unsigned long new_type)
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001176{
1177 unsigned long start;
1178 unsigned long end;
1179 int i;
1180 int free_idx;
Pauli Nieminen4f646252010-04-01 12:45:01 +00001181 int ret;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001182
1183 for (i = 0; i < addrinarray; i++) {
Thomas Hellstrom8523acf2009-08-03 09:25:45 +02001184 if (PageHighMem(pages[i]))
1185 continue;
1186 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001187 end = start + PAGE_SIZE;
Pauli Nieminen4f646252010-04-01 12:45:01 +00001188 if (reserve_memtype(start, end, new_type, NULL))
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001189 goto err_out;
1190 }
1191
Pauli Nieminen4f646252010-04-01 12:45:01 +00001192 ret = cpa_set_pages_array(pages, addrinarray,
1193 __pgprot(_PAGE_CACHE_UC_MINUS));
1194 if (!ret && new_type == _PAGE_CACHE_WC)
1195 ret = change_page_attr_set_clr(NULL, addrinarray,
1196 __pgprot(_PAGE_CACHE_WC),
1197 __pgprot(_PAGE_CACHE_MASK),
1198 0, CPA_PAGES_ARRAY, pages);
1199 if (ret)
1200 goto err_out;
1201 return 0; /* Success */
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001202err_out:
1203 free_idx = i;
1204 for (i = 0; i < free_idx; i++) {
Thomas Hellstrom8523acf2009-08-03 09:25:45 +02001205 if (PageHighMem(pages[i]))
1206 continue;
1207 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001208 end = start + PAGE_SIZE;
1209 free_memtype(start, end);
1210 }
1211 return -EINVAL;
1212}
Pauli Nieminen4f646252010-04-01 12:45:01 +00001213
1214int set_pages_array_uc(struct page **pages, int addrinarray)
1215{
1216 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
1217}
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001218EXPORT_SYMBOL(set_pages_array_uc);
1219
Pauli Nieminen4f646252010-04-01 12:45:01 +00001220int set_pages_array_wc(struct page **pages, int addrinarray)
1221{
1222 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
1223}
1224EXPORT_SYMBOL(set_pages_array_wc);
1225
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001226int set_pages_wb(struct page *page, int numpages)
1227{
1228 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001229
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001230 return set_memory_wb(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001231}
1232EXPORT_SYMBOL(set_pages_wb);
1233
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001234int set_pages_array_wb(struct page **pages, int addrinarray)
1235{
1236 int retval;
1237 unsigned long start;
1238 unsigned long end;
1239 int i;
1240
1241 retval = cpa_clear_pages_array(pages, addrinarray,
1242 __pgprot(_PAGE_CACHE_MASK));
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001243 if (retval)
1244 return retval;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001245
1246 for (i = 0; i < addrinarray; i++) {
Thomas Hellstrom8523acf2009-08-03 09:25:45 +02001247 if (PageHighMem(pages[i]))
1248 continue;
1249 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001250 end = start + PAGE_SIZE;
1251 free_memtype(start, end);
1252 }
1253
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001254 return 0;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001255}
1256EXPORT_SYMBOL(set_pages_array_wb);
1257
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001258int set_pages_x(struct page *page, int numpages)
1259{
1260 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001261
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001262 return set_memory_x(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001263}
1264EXPORT_SYMBOL(set_pages_x);
1265
1266int set_pages_nx(struct page *page, int numpages)
1267{
1268 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001269
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001270 return set_memory_nx(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001271}
1272EXPORT_SYMBOL(set_pages_nx);
1273
1274int set_pages_ro(struct page *page, int numpages)
1275{
1276 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001277
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001278 return set_memory_ro(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001279}
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001280
1281int set_pages_rw(struct page *page, int numpages)
1282{
1283 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001284
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001285 return set_memory_rw(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001286}
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001287
Linus Torvalds1da177e2005-04-16 15:20:36 -07001288#ifdef CONFIG_DEBUG_PAGEALLOC
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001289
1290static int __set_pages_p(struct page *page, int numpages)
1291{
Shaohua Lid75586a2008-08-21 10:46:06 +08001292 unsigned long tempaddr = (unsigned long) page_address(page);
1293 struct cpa_data cpa = { .vaddr = &tempaddr,
Thomas Gleixner72e458d2008-02-04 16:48:07 +01001294 .numpages = numpages,
1295 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
Shaohua Lid75586a2008-08-21 10:46:06 +08001296 .mask_clr = __pgprot(0),
1297 .flags = 0};
Thomas Gleixner72932c72008-01-30 13:34:08 +01001298
Suresh Siddha55121b42008-09-23 14:00:40 -07001299 /*
1300 * No alias checking needed for setting present flag. otherwise,
1301 * we may need to break large pages for 64-bit kernel text
1302 * mappings (this adds to complexity if we want to do this from
1303 * atomic context especially). Let's keep it simple!
1304 */
1305 return __change_page_attr_set_clr(&cpa, 0);
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001306}
1307
1308static int __set_pages_np(struct page *page, int numpages)
1309{
Shaohua Lid75586a2008-08-21 10:46:06 +08001310 unsigned long tempaddr = (unsigned long) page_address(page);
1311 struct cpa_data cpa = { .vaddr = &tempaddr,
Thomas Gleixner72e458d2008-02-04 16:48:07 +01001312 .numpages = numpages,
1313 .mask_set = __pgprot(0),
Shaohua Lid75586a2008-08-21 10:46:06 +08001314 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1315 .flags = 0};
Thomas Gleixner72932c72008-01-30 13:34:08 +01001316
Suresh Siddha55121b42008-09-23 14:00:40 -07001317 /*
1318 * No alias checking needed for setting not present flag. otherwise,
1319 * we may need to break large pages for 64-bit kernel text
1320 * mappings (this adds to complexity if we want to do this from
1321 * atomic context especially). Let's keep it simple!
1322 */
1323 return __change_page_attr_set_clr(&cpa, 0);
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001324}
1325
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326void kernel_map_pages(struct page *page, int numpages, int enable)
1327{
1328 if (PageHighMem(page))
1329 return;
Ingo Molnar9f4c8152008-01-30 13:33:41 +01001330 if (!enable) {
Ingo Molnarf9b84042006-06-27 02:54:49 -07001331 debug_check_no_locks_freed(page_address(page),
1332 numpages * PAGE_SIZE);
Ingo Molnar9f4c8152008-01-30 13:33:41 +01001333 }
Ingo Molnarde5097c2006-01-09 15:59:21 -08001334
Ingo Molnar9f4c8152008-01-30 13:33:41 +01001335 /*
Ingo Molnar12d6f212008-01-30 13:33:58 +01001336 * If page allocator is not up yet then do not call c_p_a():
1337 */
1338 if (!debug_pagealloc_enabled)
1339 return;
1340
1341 /*
Ingo Molnarf8d84062008-02-13 14:09:53 +01001342 * The return value is ignored as the calls cannot fail.
Suresh Siddha55121b42008-09-23 14:00:40 -07001343 * Large pages for identity mappings are not used at boot time
1344 * and hence no memory allocations during large page split.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001345 */
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001346 if (enable)
1347 __set_pages_p(page, numpages);
1348 else
1349 __set_pages_np(page, numpages);
Ingo Molnar9f4c8152008-01-30 13:33:41 +01001350
1351 /*
Ingo Molnare4b71dc2008-01-30 13:34:04 +01001352 * We should perform an IPI and flush all tlbs,
1353 * but that can deadlock->flush only current cpu:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354 */
1355 __flush_tlb_all();
1356}
Rafael J. Wysocki8a235ef2008-02-20 01:47:44 +01001357
1358#ifdef CONFIG_HIBERNATION
1359
1360bool kernel_page_present(struct page *page)
1361{
1362 unsigned int level;
1363 pte_t *pte;
1364
1365 if (PageHighMem(page))
1366 return false;
1367
1368 pte = lookup_address((unsigned long)page_address(page), &level);
1369 return (pte_val(*pte) & _PAGE_PRESENT);
1370}
1371
1372#endif /* CONFIG_HIBERNATION */
1373
1374#endif /* CONFIG_DEBUG_PAGEALLOC */
Arjan van de Vend1028a12008-01-30 13:34:07 +01001375
1376/*
1377 * The testcases use internal knowledge of the implementation that shouldn't
1378 * be exposed to the rest of the kernel. Include these directly here.
1379 */
1380#ifdef CONFIG_CPA_DEBUG
1381#include "pageattr-test.c"
1382#endif