Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "disassembler_arm.h" |
| 18 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 19 | #include <iostream> |
| 20 | |
Elliott Hughes | 0f3c553 | 2012-03-30 14:51:51 -0700 | [diff] [blame] | 21 | #include "logging.h" |
| 22 | #include "stringprintf.h" |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 23 | #include "thread.h" |
Elliott Hughes | 0f3c553 | 2012-03-30 14:51:51 -0700 | [diff] [blame] | 24 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 25 | namespace art { |
| 26 | namespace arm { |
| 27 | |
| 28 | DisassemblerArm::DisassemblerArm() { |
| 29 | } |
| 30 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 31 | void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { |
| 32 | if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { |
| 33 | for (const uint8_t* cur = begin; cur < end; cur += 4) { |
| 34 | DumpArm(os, cur); |
| 35 | } |
| 36 | } else { |
| 37 | // remove thumb specifier bits |
| 38 | begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); |
| 39 | end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1); |
| 40 | for (const uint8_t* cur = begin; cur < end;) { |
| 41 | cur += DumpThumb16(os, cur); |
| 42 | } |
| 43 | } |
| 44 | } |
| 45 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 46 | static const char* kConditionCodeNames[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 47 | "eq", // 0000 - equal |
| 48 | "ne", // 0001 - not-equal |
| 49 | "cs", // 0010 - carry-set, greater than, equal or unordered |
| 50 | "cc", // 0011 - carry-clear, less than |
| 51 | "mi", // 0100 - minus, negative |
| 52 | "pl", // 0101 - plus, positive or zero |
| 53 | "vs", // 0110 - overflow |
| 54 | "vc", // 0111 - no overflow |
| 55 | "hi", // 1000 - unsigned higher |
| 56 | "ls", // 1001 - unsigned lower or same |
| 57 | "ge", // 1010 - signed greater than or equal |
| 58 | "lt", // 1011 - signed less than |
| 59 | "gt", // 1100 - signed greater than |
| 60 | "le", // 1101 - signed less than or equal |
| 61 | "", // 1110 - always |
| 62 | "nv", // 1111 - never (mostly obsolete, but might be a clue that we're mistranslating) |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { |
| 66 | if (cond < 15) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 67 | os << kConditionCodeNames[cond]; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 68 | } else { |
| 69 | os << "Unexpected condition: " << cond; |
| 70 | } |
| 71 | } |
| 72 | |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 73 | void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) { |
| 74 | os << imm32 << " (" << reinterpret_cast<const void*>(instr_ptr + imm32) << ")"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | static uint32_t ReadU16(const uint8_t* ptr) { |
| 78 | return ptr[0] | (ptr[1] << 8); |
| 79 | } |
| 80 | |
| 81 | static uint32_t ReadU32(const uint8_t* ptr) { |
| 82 | return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); |
| 83 | } |
| 84 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 85 | static const char* kDataProcessingOperations[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 86 | "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", |
| 87 | "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn", |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 88 | }; |
| 89 | |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 90 | static const char* kThumbDataProcessingOperations[] = { |
| 91 | "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", |
| 92 | "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn", |
| 93 | }; |
| 94 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 95 | struct ArmRegister { |
| 96 | ArmRegister(uint32_t r) : r(r) { CHECK_LE(r, 15U); } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 97 | ArmRegister(uint32_t instruction, uint32_t at_bit) : r((instruction >> at_bit) & 0xf) { CHECK_LE(r, 15U); } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 98 | uint32_t r; |
| 99 | }; |
| 100 | std::ostream& operator<<(std::ostream& os, const ArmRegister& r) { |
| 101 | if (r.r == 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 102 | os << "sp"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 103 | } else if (r.r == 14) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 104 | os << "lr"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 105 | } else if (r.r == 15) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 106 | os << "pc"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 107 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 108 | os << "r" << r.r; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 109 | } |
| 110 | return os; |
| 111 | } |
| 112 | |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 113 | struct ThumbRegister : ArmRegister { |
| 114 | ThumbRegister(uint16_t instruction, uint16_t at_bit) : ArmRegister((instruction >> at_bit) & 0x7) {} |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 115 | }; |
| 116 | |
| 117 | struct Rm { |
| 118 | Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {} |
| 119 | uint32_t shift; |
| 120 | ArmRegister rm; |
| 121 | }; |
| 122 | std::ostream& operator<<(std::ostream& os, const Rm& r) { |
| 123 | os << r.rm; |
| 124 | if (r.shift != 0) { |
| 125 | os << "-shift-" << r.shift; // TODO |
| 126 | } |
| 127 | return os; |
| 128 | } |
| 129 | |
| 130 | struct Imm12 { |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 131 | Imm12(uint32_t instruction) { |
| 132 | uint32_t rotate = ((instruction >> 8) & 0xf); |
| 133 | uint32_t imm = (instruction & 0xff); |
| 134 | value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate))); |
| 135 | } |
| 136 | uint32_t value; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 137 | }; |
| 138 | std::ostream& operator<<(std::ostream& os, const Imm12& rhs) { |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 139 | os << "#" << rhs.value; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 140 | return os; |
| 141 | } |
| 142 | |
| 143 | struct RegisterList { |
| 144 | RegisterList(uint32_t instruction) : register_list(instruction & 0xffff) {} |
| 145 | uint32_t register_list; |
| 146 | }; |
| 147 | std::ostream& operator<<(std::ostream& os, const RegisterList& rhs) { |
| 148 | if (rhs.register_list == 0) { |
| 149 | os << "<no register list?>"; |
| 150 | return os; |
| 151 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 152 | os << "{"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 153 | bool first = true; |
| 154 | for (size_t i = 0; i < 16; i++) { |
| 155 | if ((rhs.register_list & (1 << i)) != 0) { |
| 156 | if (first) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 157 | first = false; |
| 158 | } else { |
| 159 | os << ", "; |
| 160 | } |
| 161 | os << ArmRegister(i); |
| 162 | } |
| 163 | } |
| 164 | os << "}"; |
| 165 | return os; |
| 166 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 167 | |
| 168 | void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 169 | uint32_t instruction = ReadU32(instr_ptr); |
| 170 | uint32_t cond = (instruction >> 28) & 0xf; |
| 171 | uint32_t op1 = (instruction >> 25) & 0x7; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 172 | std::string opcode; |
| 173 | std::string suffixes; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 174 | std::ostringstream args; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 175 | switch (op1) { |
| 176 | case 0: |
| 177 | case 1: // Data processing instructions. |
| 178 | { |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 179 | if ((instruction & 0x0ff000f0) == 0x01200070) { // BKPT |
| 180 | opcode = "bkpt"; |
| 181 | uint32_t imm12 = (instruction >> 8) & 0xfff; |
| 182 | uint32_t imm4 = (instruction & 0xf); |
| 183 | args << '#' << ((imm12 << 4) | imm4); |
| 184 | break; |
| 185 | } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 186 | if ((instruction & 0x0fffffd0) == 0x012fff10) { // BX and BLX (register) |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 187 | opcode = (((instruction >> 5) & 1) ? "blx" : "bx"); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 188 | args << ArmRegister(instruction & 0xf); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 189 | break; |
| 190 | } |
| 191 | bool i = (instruction & (1 << 25)) != 0; |
| 192 | bool s = (instruction & (1 << 20)) != 0; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 193 | uint32_t op = (instruction >> 21) & 0xf; |
| 194 | opcode = kDataProcessingOperations[op]; |
| 195 | bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN. |
| 196 | if (implicit_s) { |
| 197 | // Rd is unused (and not shown), and we don't show the 's' suffix either. |
| 198 | } else { |
| 199 | if (s) { |
| 200 | suffixes += 's'; |
| 201 | } |
| 202 | args << ArmRegister(instruction, 12) << ", "; |
| 203 | } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 204 | if (i) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 205 | args << ArmRegister(instruction, 16) << ", " << Imm12(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 206 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 207 | args << Rm(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 208 | } |
| 209 | } |
| 210 | break; |
| 211 | case 2: // Load/store word and unsigned byte. |
| 212 | { |
| 213 | bool p = (instruction & (1 << 24)) != 0; |
| 214 | bool b = (instruction & (1 << 22)) != 0; |
| 215 | bool w = (instruction & (1 << 21)) != 0; |
| 216 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 217 | opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : "")); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 218 | args << ArmRegister(instruction, 12) << ", "; |
| 219 | ArmRegister rn(instruction, 16); |
| 220 | if (rn.r == 0xf) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 221 | UNIMPLEMENTED(FATAL) << "literals"; |
| 222 | } else { |
| 223 | bool wback = !p || w; |
| 224 | if (p && !wback) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 225 | args << "[" << rn << ", " << Imm12(instruction) << "]"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 226 | } else if (p && wback) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 227 | args << "[" << rn << ", " << Imm12(instruction) << "]!"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 228 | } else if (!p && wback) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 229 | args << "[" << rn << "], " << Imm12(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 230 | } else { |
| 231 | LOG(FATAL) << p << " " << w; |
| 232 | } |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 233 | if (rn.r == 9) { |
| 234 | args << " ; "; |
| 235 | Thread::DumpThreadOffset(args, Imm12(instruction).value, 4); |
| 236 | } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 237 | } |
| 238 | } |
| 239 | break; |
| 240 | case 4: // Load/store multiple. |
| 241 | { |
| 242 | bool p = (instruction & (1 << 24)) != 0; |
| 243 | bool u = (instruction & (1 << 23)) != 0; |
| 244 | bool w = (instruction & (1 << 21)) != 0; |
| 245 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 246 | opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a')); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 247 | args << ArmRegister(instruction, 16) << (w ? "!" : "") << ", " << RegisterList(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 248 | } |
| 249 | break; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 250 | case 5: // Branch/branch with link. |
| 251 | { |
| 252 | bool bl = (instruction & (1 << 24)) != 0; |
| 253 | opcode = (bl ? "bl" : "b"); |
| 254 | uint32_t imm32 = (instruction & 0xffffff) << 2; |
| 255 | DumpBranchTarget(args, instr_ptr + 8, imm32); |
| 256 | } |
| 257 | break; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 258 | default: |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 259 | opcode = "???"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 260 | break; |
| 261 | } |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 262 | opcode += kConditionCodeNames[cond]; |
| 263 | opcode += suffixes; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 264 | // TODO: a more complete ARM disassembler could generate wider opcodes. |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame^] | 265 | os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instruction, opcode.c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) { |
| 269 | uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2); |
| 270 | // |111|1 1|1000000|0000|1111110000000000| |
| 271 | // |5 3|2 1|0987654|3 0|5 0 5 0| |
| 272 | // |---|---|-------|----|----------------| |
| 273 | // |332|2 2|2222222|1111|1111110000000000| |
| 274 | // |1 9|8 7|6543210|9 6|5 0 5 0| |
| 275 | // |---|---|-------|----|----------------| |
| 276 | // |111|op1| op2 | | | |
| 277 | uint32_t op1 = (instr >> 27) & 3; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 278 | if (op1 == 0) { |
| 279 | return DumpThumb16(os, instr_ptr); |
| 280 | } |
| 281 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 282 | uint32_t op2 = (instr >> 20) & 0x7F; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 283 | std::ostringstream opcode; |
| 284 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 285 | switch (op1) { |
| 286 | case 0: |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 287 | break; |
| 288 | case 1: |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 289 | if ((op2 & 0x64) == 0) { // 00x x0xx |
| 290 | // |111|11|10|00|0|00|0000|1111110000000000| |
| 291 | // |5 3|21|09|87|6|54|3 0|5 0 5 0| |
| 292 | // |---|--|--|--|-|--|----|----------------| |
| 293 | // |332|22|22|22|2|22|1111|1111110000000000| |
| 294 | // |1 9|87|65|43|2|10|9 6|5 0 5 0| |
| 295 | // |---|--|--|--|-|--|----|----------------| |
| 296 | // |111|01|00|op|0|WL| Rn | | |
| 297 | // |111|01| op2 | | | |
| 298 | // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr |
| 299 | // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr |
| 300 | // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr |
| 301 | // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr |
| 302 | uint32_t op = (instr >> 23) & 3; |
| 303 | uint32_t W = (instr >> 21) & 1; |
| 304 | uint32_t L = (instr >> 20) & 1; |
| 305 | ArmRegister Rn(instr, 16); |
| 306 | if (op == 1 || op == 2) { |
| 307 | if (op == 1) { |
| 308 | if (L == 0) { |
| 309 | opcode << "stm"; |
| 310 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 311 | } else { |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 312 | if (Rn.r != 13) { |
| 313 | opcode << "ldm"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 314 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 315 | } else { |
| 316 | opcode << "pop"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 317 | } |
| 318 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 319 | } else { |
| 320 | if (L == 0) { |
| 321 | if (Rn.r != 13) { |
| 322 | opcode << "stmdb"; |
| 323 | args << Rn << (W == 0 ? "" : "!") << ", "; |
| 324 | } else { |
| 325 | opcode << "push"; |
| 326 | } |
| 327 | } else { |
| 328 | opcode << "ldmdb"; |
| 329 | args << Rn << (W == 0 ? "" : "!") << ", "; |
| 330 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 331 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 332 | args << RegisterList(instr); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 333 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 334 | } else if ((op2 & 0x60) == 0x20) { // 01x xxxx |
| 335 | // Data-processing (shifted register) |
| 336 | // |111|1110|0000|0|0000|1111|1100|0000|0000| |
| 337 | // |5 3|2109|8765|4|3 0|5 |10 8|7 5 |3 0| |
| 338 | // |---|----|----|-|----|----|----|----|----| |
| 339 | // |332|2222|2222|2|1111|1111|1100|0000|0000| |
| 340 | // |1 9|8765|4321|0|9 6|5 |10 8|7 5 |3 0| |
| 341 | // |---|----|----|-|----|----|----|----|----| |
| 342 | // |111|0101| op3|S| Rn | | Rd | | Rm | |
| 343 | uint32_t op3 = (instr >> 21) & 0xF; |
| 344 | uint32_t S = (instr >> 20) & 1; |
| 345 | uint32_t Rn = (instr >> 16) & 0xF; |
| 346 | ArmRegister Rd(instr, 8); |
| 347 | ArmRegister Rm(instr, 0); |
| 348 | switch (op3) { |
| 349 | case 0x0: |
| 350 | if (Rn != 0xF) { |
| 351 | opcode << "and"; |
| 352 | } else { |
| 353 | opcode << "tst"; |
| 354 | S = 0; // don't print 's' |
| 355 | } |
| 356 | break; |
| 357 | case 0x1: opcode << "bic"; break; |
| 358 | case 0x2: |
| 359 | if (Rn != 0xF) { |
| 360 | opcode << "orr"; |
| 361 | } else { |
| 362 | opcode << "mov"; |
| 363 | } |
| 364 | break; |
| 365 | case 0x3: |
| 366 | if (Rn != 0xF) { |
| 367 | opcode << "orn"; |
| 368 | } else { |
| 369 | opcode << "mvn"; |
| 370 | } |
| 371 | break; |
| 372 | case 0x4: |
| 373 | if (Rn != 0xF) { |
| 374 | opcode << "eor"; |
| 375 | } else { |
| 376 | opcode << "teq"; |
| 377 | S = 0; // don't print 's' |
| 378 | } |
| 379 | break; |
| 380 | case 0x6: opcode << "pkh"; break; |
| 381 | case 0x8: |
| 382 | if (Rn != 0xF) { |
| 383 | opcode << "add"; |
| 384 | } else { |
| 385 | opcode << "cmn"; |
| 386 | S = 0; // don't print 's' |
| 387 | } |
| 388 | break; |
| 389 | case 0xA: opcode << "adc"; break; |
| 390 | case 0xB: opcode << "sbc"; break; |
| 391 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 392 | |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 393 | if (S == 1) { |
| 394 | opcode << "s"; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 395 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 396 | opcode << ".w"; |
| 397 | args << Rd << ", " << Rm; |
| 398 | } else if ((op2 & 0x40) == 0x40) { // 1xx xxxx |
| 399 | // Co-processor instructions |
| 400 | // |111|1|11|000000|0000|1111|1100|000|0 |0000| |
| 401 | // |5 3|2|10|987654|3 0|54 2|10 8|7 5|4 | 0| |
| 402 | // |---|-|--|------|----|----|----|---|---|----| |
| 403 | // |332|2|22|222222|1111|1111|1100|000|0 |0000| |
| 404 | // |1 9|8|76|543210|9 6|54 2|10 8|7 5|4 | 0| |
| 405 | // |---|-|--|------|----|----|----|---|---|----| |
| 406 | // |111| |11| op3 | Rn | |copr| |op4| | |
| 407 | uint32_t op3 = (instr >> 20) & 0x3F; |
| 408 | uint32_t coproc = (instr >> 8) & 0xF; |
| 409 | uint32_t op4 = (instr >> 4) & 0x1; |
| 410 | if ((op3 & 0x30) == 0x20 && op4 == 0) { // 10 xxxx ... 0 |
| 411 | if ((coproc & 0xE) == 0xA) { |
| 412 | // VFP data-processing instructions |
| 413 | // |111|1|1100|0000|0000|1111|110|0|00 |0|0|0000| |
| 414 | // |5 3|2|1098|7654|3 0|54 2|10 |8|76 |5|4|3 0| |
| 415 | // |---|-|----|----|----|----|---|-|----|-|-|----| |
| 416 | // |332|2|2222|2222|1111|1111|110|0|00 |0|0|0000| |
| 417 | // |1 9|8|7654|3210|9 6|54 2|109|8|76 |5|4|3 0| |
| 418 | // |---|-|----|----|----|----|---|-|----|-|-|----| |
| 419 | // |111|T|1110|opc1|opc2| |101| |opc3| | | | |
| 420 | // 111 0 1110|1111 0100 1110 101 0 01 1 0 1001 - eef4ea69 |
| 421 | uint32_t opc1 = (instr >> 20) & 0xF; |
| 422 | uint32_t opc2 = (instr >> 16) & 0xF; |
| 423 | //uint32_t opc3 = (instr >> 6) & 0x3; |
| 424 | if ((opc1 & 0xB) == 0xB) { // 1x11 |
| 425 | // Other VFP data-processing instructions. |
| 426 | switch (opc2) { |
| 427 | case 0x4: case 0x5: { // Vector compare |
| 428 | // 1110 11101 D 11 0100 dddd 101 sE1M0 mmmm |
| 429 | uint32_t D = (instr >> 22) & 0x1; |
| 430 | uint32_t Vd = (instr >> 12) & 0xF; |
| 431 | uint32_t sz = (instr >> 8) & 1; |
| 432 | uint32_t E = (instr >> 7) & 1; |
| 433 | uint32_t M = (instr >> 5) & 1; |
| 434 | uint32_t Vm = instr & 0xF; |
| 435 | bool dp_operation = sz == 1; |
| 436 | opcode << (E == 0 ? "vcmp" : "vcmpe"); |
| 437 | opcode << (dp_operation ? ".f64" : ".f32"); |
| 438 | if (dp_operation) { |
| 439 | args << "f" << ((D << 4) | Vd) << ", " << "f" << ((M << 4) | Vm); |
| 440 | } else { |
| 441 | args << "f" << ((Vd << 1) | D) << ", " << "f" << ((Vm << 1) | M); |
| 442 | } |
| 443 | break; |
| 444 | } |
| 445 | } |
| 446 | } |
| 447 | } |
| 448 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 449 | } |
| 450 | break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 451 | case 2: |
| 452 | if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) { |
| 453 | // Data-processing (modified immediate) |
| 454 | // |111|11|10|0000|0|0000|1|111|1100|00000000| |
| 455 | // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0| |
| 456 | // |---|--|--|----|-|----|-|---|----|--------| |
| 457 | // |332|22|22|2222|2|1111|1|111|1100|00000000| |
| 458 | // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0| |
| 459 | // |---|--|--|----|-|----|-|---|----|--------| |
| 460 | // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii| |
| 461 | // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 462 | uint32_t i = (instr >> 26) & 1; |
| 463 | uint32_t op3 = (instr >> 21) & 0xF; |
| 464 | uint32_t S = (instr >> 20) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 465 | ArmRegister Rn(instr, 16); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 466 | uint32_t imm3 = (instr >> 12) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 467 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 468 | uint32_t imm8 = instr & 0xFF; |
| 469 | int32_t imm32 = (i << 12) | (imm3 << 8) | imm8; |
| 470 | switch (op3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 471 | case 0x0: opcode << "and"; break; |
| 472 | case 0x1: opcode << "bic"; break; |
| 473 | case 0x2: opcode << "orr"; break; |
| 474 | case 0x3: opcode << "orn"; break; |
| 475 | case 0x4: opcode << "eor"; break; |
| 476 | case 0x8: opcode << "add"; break; |
| 477 | case 0xA: opcode << "adc"; break; |
| 478 | case 0xB: opcode << "sbc"; break; |
| 479 | case 0xD: opcode << "sub"; break; |
| 480 | case 0xE: opcode << "rsb"; break; |
| 481 | default: opcode << "UNKNOWN DPMI-" << op3; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 482 | } |
| 483 | if (S == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 484 | opcode << "s"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 485 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 486 | args << Rd << ", " << Rn << ", ThumbExpand(" << imm32 << ")"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 487 | } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) { |
| 488 | // Data-processing (plain binary immediate) |
| 489 | // |111|11|10|00000|0000|1|111110000000000| |
| 490 | // |5 3|21|09|87654|3 0|5|4 0 5 0| |
| 491 | // |---|--|--|-----|----|-|---------------| |
| 492 | // |332|22|22|22222|1111|1|111110000000000| |
| 493 | // |1 9|87|65|43210|9 6|5|4 0 5 0| |
| 494 | // |---|--|--|-----|----|-|---------------| |
| 495 | // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx| |
| 496 | uint32_t op3 = (instr >> 20) & 0x1F; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 497 | switch (op3) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 498 | case 0x00: { |
| 499 | ArmRegister Rd(instr, 8); |
| 500 | ArmRegister Rn(instr, 16); |
| 501 | uint32_t i = (instr >> 26) & 1; |
| 502 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 503 | uint32_t imm8 = instr & 0xFF; |
| 504 | uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; |
| 505 | if (Rn.r != 0xF) { |
| 506 | opcode << "addw"; |
| 507 | args << Rd << ", " << Rn << ", #" << imm12; |
| 508 | } else { |
| 509 | opcode << "adr"; |
| 510 | args << Rd << ", "; |
| 511 | DumpBranchTarget(args, instr_ptr + 4, imm12); |
| 512 | } |
| 513 | break; |
| 514 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 515 | case 0x04: { |
| 516 | // MOVW Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 517 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 518 | uint32_t i = (instr >> 26) & 1; |
| 519 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 520 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 521 | uint32_t Rn = (instr >> 16) & 0xF; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 522 | uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 523 | opcode << "movw"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 524 | args << Rd << ", #" << imm16; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 525 | break; |
| 526 | } |
| 527 | case 0x0A: { |
| 528 | // SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 529 | ArmRegister Rd(instr, 8); |
| 530 | ArmRegister Rn(instr, 16); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 531 | uint32_t i = (instr >> 26) & 1; |
| 532 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 533 | uint32_t imm8 = instr & 0xFF; |
| 534 | uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 535 | opcode << "sub.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 536 | args << Rd << ", " << Rn << ", #" << imm12; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 537 | break; |
| 538 | } |
| 539 | default: |
| 540 | break; |
| 541 | } |
| 542 | } else { |
| 543 | // Branches and miscellaneous control |
| 544 | // |111|11|1000000|0000|1|111|1100|00000000| |
| 545 | // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0| |
| 546 | // |---|--|-------|----|-|---|----|--------| |
| 547 | // |332|22|2222222|1111|1|111|1100|00000000| |
| 548 | // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0| |
| 549 | // |---|--|-------|----|-|---|----|--------| |
| 550 | // |111|10| op2 | |1|op3|op4 | | |
| 551 | |
| 552 | uint32_t op3 = (instr >> 12) & 7; |
| 553 | //uint32_t op4 = (instr >> 8) & 0xF; |
| 554 | switch (op3) { |
| 555 | case 0: |
| 556 | if ((op2 & 0x38) != 0x38) { |
| 557 | // Conditional branch |
| 558 | // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000| |
| 559 | // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0| |
| 560 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 561 | // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000| |
| 562 | // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0| |
| 563 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 564 | // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 | |
| 565 | uint32_t S = (instr >> 26) & 1; |
| 566 | uint32_t J2 = (instr >> 11) & 1; |
| 567 | uint32_t J1 = (instr >> 13) & 1; |
| 568 | uint32_t imm6 = (instr >> 16) & 0x3F; |
| 569 | uint32_t imm11 = instr & 0x7FF; |
| 570 | uint32_t cond = (instr >> 22) & 0xF; |
| 571 | int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
| 572 | imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 573 | opcode << "b"; |
| 574 | DumpCond(opcode, cond); |
| 575 | opcode << ".w"; |
| 576 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 577 | } |
| 578 | break; |
| 579 | case 2: |
| 580 | case 1: case 3: |
| 581 | break; |
| 582 | case 4: case 6: case 5: case 7: { |
| 583 | // BL, BLX (immediate) |
| 584 | // |111|11|1|0000000000|11|1 |1|1 |10000000000| |
| 585 | // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0| |
| 586 | // |---|--|-|----------|--|--|-|--|-----------| |
| 587 | // |332|22|2|2222221111|11|1 |1|1 |10000000000| |
| 588 | // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0| |
| 589 | // |---|--|-|----------|--|--|-|--|-----------| |
| 590 | // |111|10|S| imm10 |11|J1|L|J2| imm11 | |
| 591 | uint32_t S = (instr >> 26) & 1; |
| 592 | uint32_t J2 = (instr >> 11) & 1; |
| 593 | uint32_t L = (instr >> 12) & 1; |
| 594 | uint32_t J1 = (instr >> 13) & 1; |
| 595 | uint32_t imm10 = (instr >> 16) & 0x3FF; |
| 596 | uint32_t imm11 = instr & 0x7FF; |
| 597 | if (L == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 598 | opcode << "bx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 599 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 600 | opcode << "blx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 601 | } |
| 602 | uint32_t I1 = ~(J1 ^ S); |
| 603 | uint32_t I2 = ~(J2 ^ S); |
| 604 | int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
| 605 | imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate. |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 606 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 607 | break; |
| 608 | } |
| 609 | } |
| 610 | } |
| 611 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 612 | case 3: |
| 613 | switch (op2) { |
| 614 | case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0 |
| 615 | case 0x08: case 0x0A: case 0x0C: case 0x0E: { |
| 616 | // Store single data item |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 617 | // |111|11|100|000|0|0000|1111|110000|000000| |
| 618 | // |5 3|21|098|765|4|3 0|5 2|10 6|5 0| |
| 619 | // |---|--|---|---|-|----|----|------|------| |
| 620 | // |332|22|222|222|2|1111|1111|110000|000000| |
| 621 | // |1 9|87|654|321|0|9 6|5 2|10 6|5 0| |
| 622 | // |---|--|---|---|-|----|----|------|------| |
| 623 | // |111|11|000|op3|0| | | op4 | | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 624 | uint32_t op3 = (instr >> 21) & 7; |
| 625 | //uint32_t op4 = (instr >> 6) & 0x3F; |
| 626 | switch (op3) { |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 627 | case 0x0: case 0x4: { |
| 628 | // STRB Rt,[Rn,#+/-imm8] - 111 11 00 0 0 00 0 nnnn tttt 1 PUWii ii iiii |
| 629 | // STRB Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 00 0 nnnn tttt 0 00000 ii mmmm |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 630 | ArmRegister Rn(instr, 16); |
| 631 | ArmRegister Rt(instr, 12); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 632 | opcode << "strb"; |
| 633 | if ((instr & 0x800) != 0) { |
| 634 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 635 | args << Rt << ", [" << Rn << ",#" << imm8 << "]"; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 636 | } else { |
| 637 | uint32_t imm2 = (instr >> 4) & 3; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 638 | ArmRegister Rm(instr, 0); |
| 639 | args << Rt << ", [" << Rn << ", " << Rm; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 640 | if (imm2 != 0) { |
| 641 | args << ", " << "lsl #" << imm2; |
| 642 | } |
| 643 | args << "]"; |
| 644 | } |
| 645 | break; |
| 646 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 647 | case 0x2: case 0x6: { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 648 | ArmRegister Rn(instr, 16); |
| 649 | ArmRegister Rt(instr, 12); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 650 | if (op3 == 2) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 651 | if ((instr & 0x800) != 0) { |
| 652 | // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii |
| 653 | uint32_t P = (instr >> 10) & 1; |
| 654 | uint32_t U = (instr >> 9) & 1; |
| 655 | uint32_t W = (instr >> 8) & 1; |
| 656 | uint32_t imm8 = instr & 0xFF; |
| 657 | int32_t imm32 = (imm8 << 24) >> 24; // sign-extend imm8 |
| 658 | if (Rn.r == 13 && P == 1 && U == 0 && W == 1 && imm32 == 4) { |
| 659 | opcode << "push"; |
| 660 | args << Rt; |
| 661 | } else if (Rn.r == 15 || (P == 0 && W == 0)) { |
| 662 | opcode << "UNDEFINED"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 663 | } else { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 664 | if (P == 1 && U == 1 && W == 0) { |
| 665 | opcode << "strt"; |
| 666 | } else { |
| 667 | opcode << "str"; |
| 668 | } |
| 669 | args << Rt << ", [" << Rn; |
| 670 | if (P == 0 && W == 1) { |
| 671 | args << "], #" << imm32; |
| 672 | } else { |
| 673 | args << ", #" << imm32 << "]"; |
| 674 | if (W == 1) { |
| 675 | args << "!"; |
| 676 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 677 | } |
| 678 | } |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 679 | } else { |
| 680 | // STR Rt, [Rn, Rm, LSL #imm2] - 111 11 000 010 0 nnnn tttt 000000iimmmm |
| 681 | ArmRegister Rn(instr, 16); |
| 682 | ArmRegister Rt(instr, 12); |
| 683 | ArmRegister Rm(instr, 0); |
| 684 | uint32_t imm2 = (instr >> 4) & 3; |
| 685 | opcode << "str.w"; |
| 686 | args << Rt << ", [" << Rn << ", " << Rm; |
| 687 | if (imm2 != 0) { |
| 688 | args << ", lsl #" << imm2; |
| 689 | } |
| 690 | args << "]"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 691 | } |
| 692 | } else if (op3 == 6) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 693 | // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 694 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 695 | opcode << "str.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 696 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 697 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 698 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 699 | } |
| 700 | } |
| 701 | |
| 702 | break; |
| 703 | } |
| 704 | case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101 |
| 705 | // Load word |
| 706 | // |111|11|10|0 0|00|0|0000|1111|110000|000000| |
| 707 | // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0| |
| 708 | // |---|--|--|---|--|-|----|----|------|------| |
| 709 | // |332|22|22|2 2|22|2|1111|1111|110000|000000| |
| 710 | // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0| |
| 711 | // |---|--|--|---|--|-|----|----|------|------| |
| 712 | // |111|11|00|op3|10|1| Rn | Rt | op4 | | |
| 713 | // |111|11| op2 | | | imm12 | |
| 714 | uint32_t op3 = (instr >> 23) & 3; |
| 715 | uint32_t op4 = (instr >> 6) & 0x3F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 716 | ArmRegister Rn(instr, 16); |
| 717 | ArmRegister Rt(instr, 12); |
| 718 | if (op3 == 1 || Rn.r == 15) { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 719 | // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii |
| 720 | // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii |
| 721 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 722 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 723 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 724 | if (Rn.r == 9) { |
| 725 | args << " ; "; |
| 726 | Thread::DumpThreadOffset(args, imm12, 4); |
Ian Rogers | 5b9b1bc | 2012-04-09 22:51:43 -0700 | [diff] [blame] | 727 | } else if (Rn.r == 15) { |
| 728 | intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr); |
| 729 | lit_adr = RoundDown(lit_adr, 4) + 4 + imm12; |
| 730 | args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr)); |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 731 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 732 | } else if (op4 == 0) { |
| 733 | // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm |
| 734 | uint32_t imm2 = (instr >> 4) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 735 | ArmRegister rm(instr, 0); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 736 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 737 | args << Rt << ", [" << Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 738 | if (imm2 != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 739 | args << ", lsl #" << imm2; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 740 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 741 | args << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 742 | } else { |
| 743 | // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii |
| 744 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 745 | opcode << "ldrt"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 746 | args << Rt << ", [" << Rn << ", #" << imm8 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 747 | } |
| 748 | break; |
| 749 | } |
| 750 | } |
| 751 | default: |
| 752 | break; |
| 753 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 754 | os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 755 | return 4; |
| 756 | } |
| 757 | |
| 758 | size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) { |
| 759 | uint16_t instr = ReadU16(instr_ptr); |
| 760 | bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800); |
| 761 | if (is_32bit) { |
| 762 | return DumpThumb32(os, instr_ptr); |
| 763 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 764 | std::ostringstream opcode; |
| 765 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 766 | uint16_t opcode1 = instr >> 10; |
| 767 | if (opcode1 < 0x10) { |
| 768 | // shift (immediate), add, subtract, move, and compare |
| 769 | uint16_t opcode2 = instr >> 9; |
| 770 | switch (opcode2) { |
| 771 | case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: |
| 772 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 773 | // Logical shift left - 00 000xx xxxxxxxxx |
| 774 | // Logical shift right - 00 001xx xxxxxxxxx |
| 775 | // Arithmetic shift right - 00 010xx xxxxxxxxx |
| 776 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 777 | ThumbRegister rm(instr, 3); |
| 778 | ThumbRegister Rd(instr, 7); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 779 | if (opcode2 <= 3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 780 | opcode << "lsls"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 781 | } else if (opcode2 <= 7) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 782 | opcode << "lsrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 783 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 784 | opcode << "asrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 785 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 786 | args << Rd << ", " << rm << ", #" << imm5; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 787 | break; |
| 788 | } |
| 789 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 790 | // Add register - 00 01100 mmm nnn ddd |
| 791 | // Sub register - 00 01101 mmm nnn ddd |
| 792 | // Add 3-bit immediate - 00 01110 iii nnn ddd |
| 793 | // Sub 3-bit immediate - 00 01111 iii nnn ddd |
| 794 | uint16_t imm3_or_Rm = (instr >> 6) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 795 | ThumbRegister Rn(instr, 3); |
| 796 | ThumbRegister Rd(instr, 0); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 797 | if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 798 | opcode << "mov"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 799 | } else { |
| 800 | if ((opcode2 & 1) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 801 | opcode << "adds"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 802 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 803 | opcode << "subs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 804 | } |
| 805 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 806 | args << Rd << ", " << Rn; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 807 | if ((opcode2 & 2) == 0) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 808 | ArmRegister Rm(imm3_or_Rm); |
| 809 | args << ", " << Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 810 | } else if (imm3_or_Rm != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 811 | args << ", #" << imm3_or_Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 812 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 813 | break; |
| 814 | } |
| 815 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 816 | case 0x14: case 0x15: case 0x16: case 0x17: |
| 817 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 818 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: { |
| 819 | // MOVS Rd, #imm8 - 00100 ddd iiiiiiii |
| 820 | // CMP Rn, #imm8 - 00101 nnn iiiiiiii |
| 821 | // ADDS Rn, #imm8 - 00110 nnn iiiiiiii |
| 822 | // SUBS Rn, #imm8 - 00111 nnn iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 823 | ThumbRegister Rn(instr, 8); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 824 | uint16_t imm8 = instr & 0xFF; |
| 825 | switch (opcode2 >> 2) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 826 | case 4: opcode << "movs"; break; |
| 827 | case 5: opcode << "cmp"; break; |
| 828 | case 6: opcode << "adds"; break; |
| 829 | case 7: opcode << "subs"; break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 830 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 831 | args << Rn << ", #" << imm8; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 832 | break; |
| 833 | } |
| 834 | default: |
| 835 | break; |
| 836 | } |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 837 | } else if (opcode1 == 0x10) { |
| 838 | // Data-processing |
| 839 | uint16_t opcode2 = (instr >> 6) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 840 | ThumbRegister rm(instr, 3); |
| 841 | ThumbRegister rdn(instr, 0); |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 842 | opcode << kThumbDataProcessingOperations[opcode2]; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 843 | args << rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 844 | } else if (opcode1 == 0x11) { |
| 845 | // Special data instructions and branch and exchange |
| 846 | uint16_t opcode2 = (instr >> 6) & 0x0F; |
| 847 | switch (opcode2) { |
| 848 | case 0x0: case 0x1: case 0x2: case 0x3: { |
| 849 | // Add low registers - 010001 0000 xxxxxx |
| 850 | // Add high registers - 010001 0001/001x xxxxxx |
| 851 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 852 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 853 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 854 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 855 | opcode << "add"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 856 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 857 | break; |
| 858 | } |
| 859 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 860 | // Move low registers - 010001 1000 xxxxxx |
| 861 | // Move high registers - 010001 1001/101x xxxxxx |
| 862 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 863 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 864 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 865 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 866 | opcode << "mov"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 867 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 868 | break; |
| 869 | } |
| 870 | case 0x5: case 0x6: case 0x7: { |
| 871 | // Compare high registers - 010001 0101/011x xxxxxx |
| 872 | uint16_t N = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 873 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 874 | uint16_t Rn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 875 | ArmRegister N_Rn((N << 3) | Rn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 876 | opcode << "cmp"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 877 | args << N_Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 878 | break; |
| 879 | } |
| 880 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 881 | // Branch and exchange - 010001 110x xxxxxx |
| 882 | // Branch with link and exchange - 010001 111x xxxxxx |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 883 | ArmRegister rm(instr, 3); |
| 884 | opcode << ((opcode2 & 0x2) == 0 ? "bx" : "blx"); |
| 885 | args << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 886 | break; |
| 887 | } |
| 888 | default: |
| 889 | break; |
| 890 | } |
| 891 | } else if ((instr & 0xF000) == 0xB000) { |
| 892 | // Miscellaneous 16-bit instructions |
| 893 | uint16_t opcode2 = (instr >> 5) & 0x7F; |
| 894 | switch (opcode2) { |
| 895 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: { |
| 896 | // Add immediate to SP - 1011 00000 ii iiiii |
| 897 | // Subtract immediate from SP - 1011 00001 ii iiiii |
| 898 | int imm7 = instr & 0x7F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 899 | opcode << ((opcode2 & 4) == 0 ? "add" : "sub"); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 900 | args << "sp, sp, #" << (imm7 << 2); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 901 | break; |
| 902 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 903 | case 0x08: case 0x09: case 0x0A: case 0x0B: // 0001xxx |
| 904 | case 0x0C: case 0x0D: case 0x0E: case 0x0F: { |
| 905 | // CBNZ, CBZ |
| 906 | uint16_t op = (instr >> 11) & 1; |
| 907 | uint16_t i = (instr >> 9) & 1; |
| 908 | uint16_t imm5 = (instr >> 3) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 909 | ThumbRegister Rn(instr, 0); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 910 | opcode << (op != 0 ? "cbnz" : "cbz"); |
| 911 | uint32_t imm32 = (i << 7) | (imm5 << 1); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 912 | args << Rn << ", "; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 913 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
| 914 | break; |
| 915 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 916 | case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx |
| 917 | case 0x7C: case 0x7D: case 0x7E: case 0x7F: { |
| 918 | // If-Then, and hints |
| 919 | uint16_t opA = (instr >> 4) & 0xF; |
| 920 | uint16_t opB = instr & 0xF; |
| 921 | if (opB == 0) { |
| 922 | switch (opA) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 923 | case 0: opcode << "nop"; break; |
| 924 | case 1: opcode << "yield"; break; |
| 925 | case 2: opcode << "wfe"; break; |
| 926 | case 3: opcode << "sev"; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 927 | default: break; |
| 928 | } |
| 929 | } else { |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 930 | uint32_t first_cond = opA; |
| 931 | uint32_t mask = opB; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 932 | opcode << "it"; |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 933 | |
| 934 | // Flesh out the base "it" opcode with the specific collection of 't's and 'e's, |
| 935 | // and store up the actual condition codes we'll want to add to the next few opcodes. |
| 936 | size_t count = 3 - CTZ(mask); |
| 937 | it_conditions_.resize(count + 2); // Plus the implicit 't', plus the "" for the IT itself. |
| 938 | for (size_t i = 0; i < count; ++i) { |
| 939 | bool positive_cond = ((first_cond & 1) != 0); |
| 940 | bool positive_mask = ((mask & (1 << (3 - i))) != 0); |
| 941 | if (positive_mask == positive_cond) { |
| 942 | opcode << 't'; |
| 943 | it_conditions_[i] = kConditionCodeNames[first_cond]; |
| 944 | } else { |
| 945 | opcode << 'e'; |
| 946 | it_conditions_[i] = kConditionCodeNames[first_cond ^ 1]; |
| 947 | } |
| 948 | } |
| 949 | it_conditions_[count] = kConditionCodeNames[first_cond]; // The implicit 't'. |
| 950 | |
| 951 | it_conditions_[count + 1] = ""; // No condition code for the IT itself... |
| 952 | DumpCond(args, first_cond); // ...because it's considered an argument. |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 953 | } |
| 954 | break; |
| 955 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 956 | default: |
| 957 | break; |
| 958 | } |
| 959 | } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) || |
| 960 | ((instr & 0xE000) == 0x8000)) { |
| 961 | // Load/store single data item |
| 962 | uint16_t opA = instr >> 12; |
| 963 | //uint16_t opB = (instr >> 9) & 7; |
| 964 | switch (opA) { |
| 965 | case 0x6: { |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 966 | // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt |
| 967 | // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 968 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 969 | ThumbRegister Rn(instr, 3); |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 970 | ThumbRegister Rt(instr, 0); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 971 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 972 | args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 973 | break; |
| 974 | } |
| 975 | case 0x9: { |
| 976 | // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii |
| 977 | // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii |
| 978 | uint16_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 979 | ThumbRegister Rt(instr, 8); |
| 980 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 981 | args << Rt << ", [sp, #" << (imm8 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 982 | break; |
| 983 | } |
| 984 | default: |
| 985 | break; |
| 986 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 987 | } else if (opcode1 == 0x38 || opcode1 == 0x39) { |
| 988 | uint16_t imm11 = instr & 0x7FFF; |
| 989 | int32_t imm32 = imm11 << 1; |
| 990 | imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 991 | opcode << "b"; |
| 992 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 993 | } |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 994 | |
| 995 | // Apply any IT-block conditions to the opcode if necessary. |
| 996 | if (!it_conditions_.empty()) { |
| 997 | opcode << it_conditions_.back(); |
| 998 | it_conditions_.pop_back(); |
| 999 | } |
| 1000 | |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1001 | os << StringPrintf("\t\t\t%p: %04x \t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1002 | } |
| 1003 | return 2; |
| 1004 | } |
| 1005 | |
| 1006 | } // namespace arm |
| 1007 | } // namespace art |