Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
Summer Qin | 60a23fd | 2018-03-02 15:51:14 +0800 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __PLATFORM_DEF_H__ |
| 8 | #define __PLATFORM_DEF_H__ |
| 9 | |
Roberto Vargas | 638b034 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 10 | /* Enable the dynamic translation tables library. */ |
| 11 | #ifdef AARCH32 |
| 12 | # if defined(IMAGE_BL32) && RESET_TO_SP_MIN |
| 13 | # define PLAT_XLAT_TABLES_DYNAMIC 1 |
| 14 | # endif |
| 15 | #else |
| 16 | # if defined(IMAGE_BL31) && RESET_TO_BL31 |
| 17 | # define PLAT_XLAT_TABLES_DYNAMIC 1 |
| 18 | # endif |
| 19 | #endif /* AARCH32 */ |
| 20 | |
| 21 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 22 | #include <arm_def.h> |
| 23 | #include <board_arm_def.h> |
| 24 | #include <board_css_def.h> |
| 25 | #include <common_def.h> |
| 26 | #include <css_def.h> |
Qixiang Xu | 9b1eae9 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 27 | #if TRUSTED_BOARD_BOOT |
| 28 | #include <mbedtls_config.h> |
| 29 | #endif |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 30 | #include <soc_css_def.h> |
| 31 | #include <tzc400.h> |
| 32 | #include <v2m_def.h> |
Sandrine Bailleux | edfda10 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 33 | #include "../juno_def.h" |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 34 | |
Soby Mathew | 0108047 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 35 | /* Required platform porting definitions */ |
Soby Mathew | 5f3a603 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 36 | /* Juno supports system power domain */ |
| 37 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 38 | #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ |
Soby Mathew | 0108047 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 39 | JUNO_CLUSTER_COUNT + \ |
Soby Mathew | 5f3a603 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 40 | PLATFORM_CORE_COUNT) |
Soby Mathew | 0108047 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 41 | #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ |
| 42 | JUNO_CLUSTER1_CORE_COUNT) |
| 43 | |
Soby Mathew | e60f2af | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 44 | /* Cryptocell HW Base address */ |
| 45 | #define PLAT_CRYPTOCELL_BASE 0x60050000 |
| 46 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 47 | /* |
Soby Mathew | 5f3a603 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 48 | * Other platform porting definitions are provided by included headers |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 49 | */ |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 50 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 51 | /* |
| 52 | * Required ARM standard platform porting definitions |
| 53 | */ |
Soby Mathew | 0108047 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 54 | #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 55 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 56 | /* Use the bypass address */ |
| 57 | #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 58 | |
Chris Kay | d7ecac7 | 2018-05-10 14:27:45 +0100 | [diff] [blame^] | 59 | #define NSRAM_BASE 0x2e000000 |
| 60 | #define NSRAM_SIZE 0x00008000 /* 32KB */ |
| 61 | |
Roberto Vargas | 638b034 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 62 | /* virtual address used by dynamic mem_protect for chunk_base */ |
| 63 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000 |
| 64 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 65 | /* |
| 66 | * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB |
| 67 | * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of |
| 68 | * flash |
| 69 | */ |
Juan Castillo | 01df3c1 | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 70 | #if TRUSTED_BOARD_BOOT |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 71 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 |
| 72 | #else |
| 73 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 |
Juan Castillo | 01df3c1 | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 74 | #endif /* TRUSTED_BOARD_BOOT */ |
| 75 | |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 76 | /* |
Antonio Nino Diaz | 0289970 | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 77 | * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 78 | * defined for ARM development platforms. |
| 79 | */ |
Antonio Nino Diaz | 0289970 | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 80 | #if ARM_BOARD_OPTIMISE_MEM |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 81 | /* |
| 82 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 83 | * plat_arm_mmap array defined for each BL stage. |
| 84 | */ |
Masahiro Yamada | 3d8256b | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 85 | #ifdef IMAGE_BL1 |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 86 | # define PLAT_ARM_MMAP_ENTRIES 7 |
| 87 | # define MAX_XLAT_TABLES 4 |
| 88 | #endif |
| 89 | |
Masahiro Yamada | 3d8256b | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 90 | #ifdef IMAGE_BL2 |
Summer Qin | 54661cd | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 91 | #ifdef SPD_opteed |
Roberto Vargas | b09ba05 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 92 | # define PLAT_ARM_MMAP_ENTRIES 11 |
Roberto Vargas | f145403 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 93 | # define MAX_XLAT_TABLES 5 |
Summer Qin | 54661cd | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 94 | #else |
Roberto Vargas | b09ba05 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 95 | # define PLAT_ARM_MMAP_ENTRIES 10 |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 96 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 97 | #endif |
Summer Qin | 54661cd | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 98 | #endif |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 99 | |
Masahiro Yamada | 3d8256b | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 100 | #ifdef IMAGE_BL2U |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 101 | # define PLAT_ARM_MMAP_ENTRIES 4 |
| 102 | # define MAX_XLAT_TABLES 3 |
| 103 | #endif |
| 104 | |
Masahiro Yamada | 3d8256b | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 105 | #ifdef IMAGE_BL31 |
Roberto Vargas | b09ba05 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 106 | # define PLAT_ARM_MMAP_ENTRIES 7 |
Roberto Vargas | f145403 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 107 | # define MAX_XLAT_TABLES 3 |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 108 | #endif |
| 109 | |
Masahiro Yamada | 3d8256b | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 110 | #ifdef IMAGE_BL32 |
Roberto Vargas | 638b034 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 111 | # define PLAT_ARM_MMAP_ENTRIES 6 |
Yatharth Kochar | 6f24934 | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 112 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | c64a044 | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 113 | #endif |
| 114 | |
Antonio Nino Diaz | 0289970 | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 115 | /* |
| 116 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 117 | * plus a little space for growth. |
| 118 | */ |
| 119 | #if TRUSTED_BOARD_BOOT |
Qixiang Xu | ddfd38e | 2017-08-24 14:28:08 +0800 | [diff] [blame] | 120 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 |
Antonio Nino Diaz | 0289970 | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 121 | #else |
| 122 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 |
| 123 | #endif |
| 124 | |
| 125 | /* |
| 126 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 127 | * little space for growth. |
| 128 | */ |
| 129 | #if TRUSTED_BOARD_BOOT |
Qixiang Xu | 9b1eae9 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 130 | #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA |
Amit Daniel Kachhap | 83a2376 | 2018-03-23 11:56:23 +0530 | [diff] [blame] | 131 | # define PLAT_ARM_MAX_BL2_SIZE 0x20000 |
| 132 | #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA |
| 133 | # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 |
Qixiang Xu | 9b1eae9 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 134 | #else |
Amit Daniel Kachhap | 83a2376 | 2018-03-23 11:56:23 +0530 | [diff] [blame] | 135 | # define PLAT_ARM_MAX_BL2_SIZE 0x1C000 |
Qixiang Xu | 9b1eae9 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 136 | #endif |
Antonio Nino Diaz | 0289970 | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 137 | #else |
Amit Daniel Kachhap | 83a2376 | 2018-03-23 11:56:23 +0530 | [diff] [blame] | 138 | # define PLAT_ARM_MAX_BL2_SIZE 0xE000 |
Antonio Nino Diaz | 0289970 | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 139 | #endif |
| 140 | |
| 141 | /* |
| 142 | * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a |
| 143 | * little space for growth. |
Qixiang Xu | ddfd38e | 2017-08-24 14:28:08 +0800 | [diff] [blame] | 144 | * SCP_BL2 image is loaded into the space BL31 -> BL1_RW_BASE. |
| 145 | * For TBB use case, PLAT_ARM_MAX_BL1_RW_SIZE has been increased and therefore |
| 146 | * PLAT_ARM_MAX_BL31_SIZE has been increased to ensure SCP_BL2 has the same |
| 147 | * space available. |
Antonio Nino Diaz | 0289970 | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 148 | */ |
Qixiang Xu | ddfd38e | 2017-08-24 14:28:08 +0800 | [diff] [blame] | 149 | #define PLAT_ARM_MAX_BL31_SIZE 0x1E000 |
Antonio Nino Diaz | 0289970 | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 150 | |
Soby Mathew | 5744e87 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 151 | #if JUNO_AARCH32_EL3_RUNTIME |
| 152 | /* |
| 153 | * PLAT_ARM_MAX_BL32_SIZE is calculated for SP_MIN as the AArch32 Secure |
| 154 | * Payload. We also need to take care of SCP_BL2 size as well, as the SCP_BL2 |
| 155 | * is loaded into the space BL32 -> BL1_RW_BASE |
| 156 | */ |
| 157 | # define PLAT_ARM_MAX_BL32_SIZE 0x1E000 |
| 158 | #endif |
| 159 | |
Soby Mathew | bea363a | 2017-08-22 14:06:19 +0100 | [diff] [blame] | 160 | /* |
| 161 | * Since free SRAM space is scant, enable the ASSERTION message size |
| 162 | * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). |
| 163 | */ |
| 164 | #define PLAT_LOG_LEVEL_ASSERT 40 |
| 165 | |
Antonio Nino Diaz | 0289970 | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 166 | #endif /* ARM_BOARD_OPTIMISE_MEM */ |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 167 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 168 | /* CCI related constants */ |
| 169 | #define PLAT_ARM_CCI_BASE 0x2c090000 |
| 170 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 171 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 |
| 172 | |
Vikram Kanigiri | ecf70f7 | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 173 | /* System timer related constants */ |
| 174 | #define PLAT_ARM_NSTIMER_FRAME_ID 1 |
| 175 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 176 | /* TZC related constants */ |
Vikram Kanigiri | ecf70f7 | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 177 | #define PLAT_ARM_TZC_BASE 0x2a4a0000 |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 178 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 179 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ |
| 180 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ |
| 181 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ |
| 182 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ |
| 183 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ |
| 184 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ |
| 185 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ |
| 186 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ |
| 187 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ |
| 188 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) |
Juan Castillo | 1217d28 | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 189 | |
| 190 | /* |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 191 | * Required ARM CSS based platform porting definitions |
Juan Castillo | 1217d28 | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 192 | */ |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 193 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 194 | /* GIC related constants (no GICR in GIC-400) */ |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 195 | #define PLAT_ARM_GICD_BASE 0x2c010000 |
| 196 | #define PLAT_ARM_GICC_BASE 0x2c02f000 |
| 197 | #define PLAT_ARM_GICH_BASE 0x2c04f000 |
| 198 | #define PLAT_ARM_GICV_BASE 0x2c06f000 |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 199 | |
Vikram Kanigiri | ecf70f7 | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 200 | /* MHU related constants */ |
| 201 | #define PLAT_CSS_MHU_BASE 0x2b1f0000 |
| 202 | |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 203 | /* |
Vikram Kanigiri | 8e083ec | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 204 | * Base address of the first memory region used for communication between AP |
| 205 | * and SCP. Used by the BOM and SCPI protocols. |
Soby Mathew | 18e279e | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 206 | */ |
| 207 | #if !CSS_USE_SCMI_SDS_DRIVER |
| 208 | /* |
Vikram Kanigiri | 8e083ec | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 209 | * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which |
| 210 | * means the SCP/AP configuration data gets overwritten when the AP initiates |
| 211 | * communication with the SCP. The configuration data is expected to be a |
| 212 | * 32-bit word on all CSS platforms. On Juno, part of this configuration is |
| 213 | * which CPU is the primary, according to the shift and mask definitions below. |
| 214 | */ |
| 215 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) |
| 216 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 217 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 |
Soby Mathew | 18e279e | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 218 | #endif |
Vikram Kanigiri | 8e083ec | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 219 | |
| 220 | /* |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 221 | * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current |
| 222 | * SCP_BL2 size plus a little space for growth. |
| 223 | */ |
Soby Mathew | 6c401f3 | 2017-06-13 17:59:17 +0100 | [diff] [blame] | 224 | #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000 |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 225 | |
| 226 | /* |
Yatharth Kochar | 53d703a | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 227 | * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current |
| 228 | * SCP_BL2U size plus a little space for growth. |
| 229 | */ |
Soby Mathew | 6c401f3 | 2017-06-13 17:59:17 +0100 | [diff] [blame] | 230 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 |
Yatharth Kochar | 53d703a | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 231 | |
Jeenu Viswambharan | b2c363b | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 232 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 233 | CSS_G1S_IRQ_PROPS(grp), \ |
| 234 | ARM_G1S_IRQ_PROPS(grp), \ |
| 235 | INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
| 236 | grp, GIC_INTR_CFG_LEVEL), \ |
| 237 | INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
| 238 | grp, GIC_INTR_CFG_LEVEL), \ |
| 239 | INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
| 240 | grp, GIC_INTR_CFG_LEVEL), \ |
| 241 | INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
| 242 | grp, GIC_INTR_CFG_LEVEL), \ |
| 243 | INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
| 244 | grp, GIC_INTR_CFG_LEVEL), \ |
| 245 | INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ |
| 246 | grp, GIC_INTR_CFG_LEVEL), \ |
| 247 | INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ |
| 248 | grp, GIC_INTR_CFG_LEVEL), \ |
| 249 | INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
| 250 | grp, GIC_INTR_CFG_LEVEL) |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 251 | |
Jeenu Viswambharan | b2c363b | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 252 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 253 | |
Juan Castillo | 1217d28 | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 254 | /* |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 255 | * Required ARM CSS SoC based platform porting definitions |
Juan Castillo | 1217d28 | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 256 | */ |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 257 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 258 | /* CSS SoC NIC-400 Global Programmers View (GPV) */ |
| 259 | #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 260 | |
Jeenu Viswambharan | 7bdf0c1 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 261 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 262 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
| 263 | |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 264 | #endif /* __PLATFORM_DEF_H__ */ |