Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1 | //===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 10 | #include <stdlib.h> |
| 11 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 12 | #include "EmulateInstructionARM.h" |
Greg Clayton | 8482ded | 2011-02-01 00:04:43 +0000 | [diff] [blame] | 13 | #include "lldb/Core/ConstString.h" |
| 14 | |
Greg Clayton | f29a08f | 2011-02-09 17:41:27 +0000 | [diff] [blame] | 15 | #include "Plugins/Process/Utility/ARMDefines.h" |
| 16 | #include "Plugins/Process/Utility/ARMUtils.h" |
| 17 | #include "Utility/ARM_DWARF_Registers.h" |
| 18 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 19 | #include "llvm/Support/MathExtras.h" // for SignExtend32 template function |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 20 | // and CountTrailingZeros_32 function |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 21 | |
| 22 | using namespace lldb; |
| 23 | using namespace lldb_private; |
| 24 | |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 25 | static inline uint32_t Align(uint32_t val, uint32_t alignment) |
| 26 | { |
| 27 | return alignment * (val / alignment); |
| 28 | } |
| 29 | |
Johnny Chen | 0e00af2 | 2011-02-10 19:40:42 +0000 | [diff] [blame] | 30 | //---------------------------------------------------------------------- |
| 31 | // |
| 32 | // ITSession implementation |
| 33 | // |
| 34 | //---------------------------------------------------------------------- |
| 35 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 36 | // A8.6.50 |
| 37 | // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition. |
| 38 | static unsigned short CountITSize(unsigned ITMask) { |
| 39 | // First count the trailing zeros of the IT mask. |
| 40 | unsigned TZ = llvm::CountTrailingZeros_32(ITMask); |
| 41 | if (TZ > 3) |
| 42 | { |
| 43 | printf("Encoding error: IT Mask '0000'\n"); |
| 44 | return 0; |
| 45 | } |
| 46 | return (4 - TZ); |
| 47 | } |
| 48 | |
| 49 | // Init ITState. Note that at least one bit is always 1 in mask. |
| 50 | bool ITSession::InitIT(unsigned short bits7_0) |
| 51 | { |
| 52 | ITCounter = CountITSize(Bits32(bits7_0, 3, 0)); |
| 53 | if (ITCounter == 0) |
| 54 | return false; |
| 55 | |
| 56 | // A8.6.50 IT |
| 57 | unsigned short FirstCond = Bits32(bits7_0, 7, 4); |
| 58 | if (FirstCond == 0xF) |
| 59 | { |
| 60 | printf("Encoding error: IT FirstCond '1111'\n"); |
| 61 | return false; |
| 62 | } |
| 63 | if (FirstCond == 0xE && ITCounter != 1) |
| 64 | { |
| 65 | printf("Encoding error: IT FirstCond '1110' && Mask != '1000'\n"); |
| 66 | return false; |
| 67 | } |
| 68 | |
| 69 | ITState = bits7_0; |
| 70 | return true; |
| 71 | } |
| 72 | |
| 73 | // Update ITState if necessary. |
| 74 | void ITSession::ITAdvance() |
| 75 | { |
| 76 | assert(ITCounter); |
| 77 | --ITCounter; |
| 78 | if (ITCounter == 0) |
| 79 | ITState = 0; |
| 80 | else |
| 81 | { |
| 82 | unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1; |
| 83 | SetBits32(ITState, 4, 0, NewITState4_0); |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | // Return true if we're inside an IT Block. |
| 88 | bool ITSession::InITBlock() |
| 89 | { |
| 90 | return ITCounter != 0; |
| 91 | } |
| 92 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 93 | // Return true if we're the last instruction inside an IT Block. |
| 94 | bool ITSession::LastInITBlock() |
| 95 | { |
| 96 | return ITCounter == 1; |
| 97 | } |
| 98 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 99 | // Get condition bits for the current thumb instruction. |
| 100 | uint32_t ITSession::GetCond() |
| 101 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 102 | if (InITBlock()) |
| 103 | return Bits32(ITState, 7, 4); |
| 104 | else |
| 105 | return COND_AL; |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 106 | } |
| 107 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 108 | // ARM constants used during decoding |
| 109 | #define REG_RD 0 |
| 110 | #define LDM_REGLIST 1 |
| 111 | #define PC_REG 15 |
| 112 | #define PC_REGLIST_BIT 0x8000 |
| 113 | |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 114 | #define ARMv4 (1u << 0) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 115 | #define ARMv4T (1u << 1) |
| 116 | #define ARMv5T (1u << 2) |
| 117 | #define ARMv5TE (1u << 3) |
| 118 | #define ARMv5TEJ (1u << 4) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 119 | #define ARMv6 (1u << 5) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 120 | #define ARMv6K (1u << 6) |
| 121 | #define ARMv6T2 (1u << 7) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 122 | #define ARMv7 (1u << 8) |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 123 | #define ARMv8 (1u << 9) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 124 | #define ARMvAll (0xffffffffu) |
| 125 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 126 | #define ARMV4T_ABOVE (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
| 127 | #define ARMV5_ABOVE (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
| 128 | #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv8) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 129 | |
Johnny Chen | 0e00af2 | 2011-02-10 19:40:42 +0000 | [diff] [blame] | 130 | //---------------------------------------------------------------------- |
| 131 | // |
| 132 | // EmulateInstructionARM implementation |
| 133 | // |
| 134 | //---------------------------------------------------------------------- |
| 135 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 136 | void |
| 137 | EmulateInstructionARM::Initialize () |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 138 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 139 | } |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 140 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 141 | void |
| 142 | EmulateInstructionARM::Terminate () |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 143 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 144 | } |
| 145 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 146 | // Write "bits (32) UNKNOWN" to memory address "address". Helper function for many ARM instructions. |
| 147 | bool |
| 148 | EmulateInstructionARM::WriteBits32UnknownToMemory (addr_t address) |
| 149 | { |
| 150 | EmulateInstruction::Context context = { EmulateInstruction::eContextWriteMemoryRandomBits, |
| 151 | address, |
| 152 | 0, |
| 153 | 0 }; |
| 154 | |
| 155 | uint32_t random_data = rand (); |
| 156 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 157 | |
| 158 | if (!WriteMemoryUnsigned (context, address, random_data, addr_byte_size)) |
| 159 | return false; |
| 160 | |
| 161 | return true; |
| 162 | } |
| 163 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 164 | // Write "bits (32) UNKNOWN" to register n. Helper function for many ARM instructions. |
| 165 | bool |
| 166 | EmulateInstructionARM::WriteBits32Unknown (int n) |
| 167 | { |
| 168 | EmulateInstruction::Context context = { EmulateInstruction::eContextWriteRegisterRandomBits, |
| 169 | eRegisterKindDWARF, |
| 170 | dwarf_r0 + n, |
| 171 | 0 }; |
| 172 | |
Johnny Chen | 62ff6f5 | 2011-02-11 18:11:22 +0000 | [diff] [blame] | 173 | bool success; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 174 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 175 | |
| 176 | if (!success) |
| 177 | return false; |
| 178 | |
| 179 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 180 | return false; |
| 181 | |
| 182 | return true; |
| 183 | } |
| 184 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 185 | // Push Multiple Registers stores multiple registers to the stack, storing to |
| 186 | // consecutive memory locations ending just below the address in SP, and updates |
| 187 | // SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 188 | bool |
| 189 | EmulateInstructionARM::EmulatePush (ARMEncoding encoding) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 190 | { |
| 191 | #if 0 |
| 192 | // ARM pseudo code... |
| 193 | if (ConditionPassed()) |
| 194 | { |
| 195 | EncodingSpecificOperations(); |
| 196 | NullCheckIfThumbEE(13); |
| 197 | address = SP - 4*BitCount(registers); |
| 198 | |
| 199 | for (i = 0 to 14) |
| 200 | { |
| 201 | if (registers<i> == ’1’) |
| 202 | { |
| 203 | if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1 |
| 204 | MemA[address,4] = bits(32) UNKNOWN; |
| 205 | else |
| 206 | MemA[address,4] = R[i]; |
| 207 | address = address + 4; |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | if (registers<15> == ’1’) // Only possible for encoding A1 or A2 |
| 212 | MemA[address,4] = PCStoreValue(); |
| 213 | |
| 214 | SP = SP - 4*BitCount(registers); |
| 215 | } |
| 216 | #endif |
| 217 | |
| 218 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 219 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 220 | if (!success) |
| 221 | return false; |
| 222 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 223 | if (ConditionPassed()) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 224 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 225 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 226 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 227 | if (!success) |
| 228 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 229 | uint32_t registers = 0; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 230 | uint32_t Rt; // the source register |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 231 | switch (encoding) { |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 232 | case eEncodingT1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 233 | registers = Bits32(opcode, 7, 0); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 234 | // The M bit represents LR. |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 235 | if (Bit32(opcode, 8)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 236 | registers |= (1u << 14); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 237 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 238 | if (BitCount(registers) < 1) |
| 239 | return false; |
| 240 | break; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 241 | case eEncodingT2: |
| 242 | // Ignore bits 15 & 13. |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 243 | registers = Bits32(opcode, 15, 0) & ~0xa000; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 244 | // if BitCount(registers) < 2 then UNPREDICTABLE; |
| 245 | if (BitCount(registers) < 2) |
| 246 | return false; |
| 247 | break; |
| 248 | case eEncodingT3: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 249 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 250 | // if BadReg(t) then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 251 | if (BadReg(Rt)) |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 252 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 253 | registers = (1u << Rt); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 254 | break; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 255 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 256 | registers = Bits32(opcode, 15, 0); |
Johnny Chen | a33d484 | 2011-01-24 22:25:48 +0000 | [diff] [blame] | 257 | // Instead of return false, let's handle the following case as well, |
| 258 | // which amounts to pushing one reg onto the full descending stacks. |
| 259 | // if BitCount(register_list) < 2 then SEE STMDB / STMFD; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 260 | break; |
| 261 | case eEncodingA2: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 262 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 263 | // if t == 13 then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 264 | if (Rt == dwarf_sp) |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 265 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 266 | registers = (1u << Rt); |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 267 | break; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 268 | default: |
| 269 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 270 | } |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 271 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 272 | addr_t addr = sp - sp_offset; |
| 273 | uint32_t i; |
| 274 | |
| 275 | EmulateInstruction::Context context = { EmulateInstruction::eContextPushRegisterOnStack, eRegisterKindDWARF, 0, 0 }; |
| 276 | for (i=0; i<15; ++i) |
| 277 | { |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 278 | if (BitIsSet (registers, i)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 279 | { |
| 280 | context.arg1 = dwarf_r0 + i; // arg1 in the context is the DWARF register number |
| 281 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 282 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, context.arg1, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 283 | if (!success) |
| 284 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 285 | if (!WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 286 | return false; |
| 287 | addr += addr_byte_size; |
| 288 | } |
| 289 | } |
| 290 | |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 291 | if (BitIsSet (registers, 15)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 292 | { |
| 293 | context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 294 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 295 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 296 | if (!success) |
| 297 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 298 | if (!WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 299 | return false; |
| 300 | } |
| 301 | |
| 302 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 303 | context.arg0 = eRegisterKindGeneric; |
| 304 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 305 | context.arg2 = -sp_offset; |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 306 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 307 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 308 | return false; |
| 309 | } |
| 310 | return true; |
| 311 | } |
| 312 | |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 313 | // Pop Multiple Registers loads multiple registers from the stack, loading from |
| 314 | // consecutive memory locations staring at the address in SP, and updates |
| 315 | // SP to point just above the loaded data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 316 | bool |
| 317 | EmulateInstructionARM::EmulatePop (ARMEncoding encoding) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 318 | { |
| 319 | #if 0 |
| 320 | // ARM pseudo code... |
| 321 | if (ConditionPassed()) |
| 322 | { |
| 323 | EncodingSpecificOperations(); NullCheckIfThumbEE(13); |
| 324 | address = SP; |
| 325 | for i = 0 to 14 |
| 326 | if registers<i> == ‘1’ then |
| 327 | R[i} = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4; |
| 328 | if registers<15> == ‘1’ then |
| 329 | if UnalignedAllowed then |
| 330 | LoadWritePC(MemU[address,4]); |
| 331 | else |
| 332 | LoadWritePC(MemA[address,4]); |
| 333 | if registers<13> == ‘0’ then SP = SP + 4*BitCount(registers); |
| 334 | if registers<13> == ‘1’ then SP = bits(32) UNKNOWN; |
| 335 | } |
| 336 | #endif |
| 337 | |
| 338 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 339 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 340 | if (!success) |
| 341 | return false; |
| 342 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 343 | if (ConditionPassed()) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 344 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 345 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 346 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 347 | if (!success) |
| 348 | return false; |
| 349 | uint32_t registers = 0; |
| 350 | uint32_t Rt; // the destination register |
| 351 | switch (encoding) { |
| 352 | case eEncodingT1: |
| 353 | registers = Bits32(opcode, 7, 0); |
| 354 | // The P bit represents PC. |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 355 | if (Bit32(opcode, 8)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 356 | registers |= (1u << 15); |
| 357 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 358 | if (BitCount(registers) < 1) |
| 359 | return false; |
| 360 | break; |
| 361 | case eEncodingT2: |
| 362 | // Ignore bit 13. |
| 363 | registers = Bits32(opcode, 15, 0) & ~0x2000; |
| 364 | // if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 365 | if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14))) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 366 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 367 | // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
| 368 | if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock()) |
| 369 | return false; |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 370 | break; |
| 371 | case eEncodingT3: |
| 372 | Rt = Bits32(opcode, 15, 12); |
| 373 | // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 374 | if (Rt == 13) |
| 375 | return false; |
| 376 | if (Rt == 15 && InITBlock() && !LastInITBlock()) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 377 | return false; |
| 378 | registers = (1u << Rt); |
| 379 | break; |
| 380 | case eEncodingA1: |
| 381 | registers = Bits32(opcode, 15, 0); |
| 382 | // Instead of return false, let's handle the following case as well, |
| 383 | // which amounts to popping one reg from the full descending stacks. |
| 384 | // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD; |
| 385 | |
| 386 | // if registers<13> == ‘1’ && ArchVersion() >= 7 then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 387 | if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 388 | return false; |
| 389 | break; |
| 390 | case eEncodingA2: |
| 391 | Rt = Bits32(opcode, 15, 12); |
| 392 | // if t == 13 then UNPREDICTABLE; |
| 393 | if (Rt == dwarf_sp) |
| 394 | return false; |
| 395 | registers = (1u << Rt); |
| 396 | break; |
| 397 | default: |
| 398 | return false; |
| 399 | } |
| 400 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
| 401 | addr_t addr = sp; |
| 402 | uint32_t i, data; |
| 403 | |
| 404 | EmulateInstruction::Context context = { EmulateInstruction::eContextPopRegisterOffStack, eRegisterKindDWARF, 0, 0 }; |
| 405 | for (i=0; i<15; ++i) |
| 406 | { |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 407 | if (BitIsSet (registers, i)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 408 | { |
| 409 | context.arg1 = dwarf_r0 + i; // arg1 in the context is the DWARF register number |
| 410 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 411 | data = ReadMemoryUnsigned(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 412 | if (!success) |
| 413 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 414 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, context.arg1, data)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 415 | return false; |
| 416 | addr += addr_byte_size; |
| 417 | } |
| 418 | } |
| 419 | |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 420 | if (BitIsSet (registers, 15)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 421 | { |
| 422 | context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number |
| 423 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 424 | data = ReadMemoryUnsigned(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 425 | if (!success) |
| 426 | return false; |
Johnny Chen | f3eaacf | 2011-02-09 19:30:49 +0000 | [diff] [blame] | 427 | // In ARMv5T and above, this is an interworking branch. |
| 428 | if (!LoadWritePC(context, data)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 429 | return false; |
| 430 | addr += addr_byte_size; |
| 431 | } |
| 432 | |
| 433 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 434 | context.arg0 = eRegisterKindGeneric; |
| 435 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
| 436 | context.arg2 = sp_offset; |
| 437 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 438 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 439 | return false; |
| 440 | } |
| 441 | return true; |
| 442 | } |
| 443 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 444 | // Set r7 or ip to point to saved value residing within the stack. |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 445 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 446 | bool |
| 447 | EmulateInstructionARM::EmulateAddRdSPImmediate (ARMEncoding encoding) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 448 | { |
| 449 | #if 0 |
| 450 | // ARM pseudo code... |
| 451 | if (ConditionPassed()) |
| 452 | { |
| 453 | EncodingSpecificOperations(); |
| 454 | (result, carry, overflow) = AddWithCarry(SP, imm32, ‘0’); |
| 455 | if d == 15 then |
| 456 | ALUWritePC(result); // setflags is always FALSE here |
| 457 | else |
| 458 | R[d] = result; |
| 459 | if setflags then |
| 460 | APSR.N = result<31>; |
| 461 | APSR.Z = IsZeroBit(result); |
| 462 | APSR.C = carry; |
| 463 | APSR.V = overflow; |
| 464 | } |
| 465 | #endif |
| 466 | |
| 467 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 468 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 469 | if (!success) |
| 470 | return false; |
| 471 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 472 | if (ConditionPassed()) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 473 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 474 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 475 | if (!success) |
| 476 | return false; |
| 477 | uint32_t Rd; // the destination register |
| 478 | uint32_t imm32; |
| 479 | switch (encoding) { |
| 480 | case eEncodingT1: |
| 481 | Rd = 7; |
| 482 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32) |
| 483 | break; |
| 484 | case eEncodingA1: |
| 485 | Rd = Bits32(opcode, 15, 12); |
| 486 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 487 | break; |
| 488 | default: |
| 489 | return false; |
| 490 | } |
| 491 | addr_t sp_offset = imm32; |
| 492 | addr_t addr = sp + sp_offset; // a pointer to the stack area |
| 493 | |
| 494 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 495 | eRegisterKindGeneric, |
| 496 | LLDB_REGNUM_GENERIC_SP, |
| 497 | sp_offset }; |
| 498 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 499 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr)) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 500 | return false; |
| 501 | } |
| 502 | return true; |
| 503 | } |
| 504 | |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 505 | // Set r7 or ip to the current stack pointer. |
| 506 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 507 | bool |
| 508 | EmulateInstructionARM::EmulateMovRdSP (ARMEncoding encoding) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 509 | { |
| 510 | #if 0 |
| 511 | // ARM pseudo code... |
| 512 | if (ConditionPassed()) |
| 513 | { |
| 514 | EncodingSpecificOperations(); |
| 515 | result = R[m]; |
| 516 | if d == 15 then |
| 517 | ALUWritePC(result); // setflags is always FALSE here |
| 518 | else |
| 519 | R[d] = result; |
| 520 | if setflags then |
| 521 | APSR.N = result<31>; |
| 522 | APSR.Z = IsZeroBit(result); |
| 523 | // APSR.C unchanged |
| 524 | // APSR.V unchanged |
| 525 | } |
| 526 | #endif |
| 527 | |
| 528 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 529 | //const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 530 | //if (!success) |
| 531 | // return false; |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 532 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 533 | if (ConditionPassed()) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 534 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 535 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 536 | if (!success) |
| 537 | return false; |
| 538 | uint32_t Rd; // the destination register |
| 539 | switch (encoding) { |
| 540 | case eEncodingT1: |
| 541 | Rd = 7; |
| 542 | break; |
| 543 | case eEncodingA1: |
| 544 | Rd = 12; |
| 545 | break; |
| 546 | default: |
| 547 | return false; |
| 548 | } |
| 549 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 550 | eRegisterKindGeneric, |
| 551 | LLDB_REGNUM_GENERIC_SP, |
| 552 | 0 }; |
| 553 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 554 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp)) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 555 | return false; |
| 556 | } |
| 557 | return true; |
| 558 | } |
| 559 | |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 560 | // Move from high register (r8-r15) to low register (r0-r7). |
| 561 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 562 | bool |
| 563 | EmulateInstructionARM::EmulateMovLowHigh (ARMEncoding encoding) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 564 | { |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 565 | return EmulateMovRdRm (encoding); |
| 566 | } |
| 567 | |
| 568 | // Move from register to register. |
| 569 | // MOV (register) |
| 570 | bool |
| 571 | EmulateInstructionARM::EmulateMovRdRm (ARMEncoding encoding) |
| 572 | { |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 573 | #if 0 |
| 574 | // ARM pseudo code... |
| 575 | if (ConditionPassed()) |
| 576 | { |
| 577 | EncodingSpecificOperations(); |
| 578 | result = R[m]; |
| 579 | if d == 15 then |
| 580 | ALUWritePC(result); // setflags is always FALSE here |
| 581 | else |
| 582 | R[d] = result; |
| 583 | if setflags then |
| 584 | APSR.N = result<31>; |
| 585 | APSR.Z = IsZeroBit(result); |
| 586 | // APSR.C unchanged |
| 587 | // APSR.V unchanged |
| 588 | } |
| 589 | #endif |
| 590 | |
| 591 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 592 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 593 | if (!success) |
| 594 | return false; |
| 595 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 596 | if (ConditionPassed()) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 597 | { |
| 598 | uint32_t Rm; // the source register |
| 599 | uint32_t Rd; // the destination register |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 600 | bool setflags; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 601 | switch (encoding) { |
| 602 | case eEncodingT1: |
| 603 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 604 | Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 1); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 605 | setflags = false; |
| 606 | break; |
| 607 | case eEncodingT2: |
| 608 | Rm = Bits32(opcode, 5, 3); |
| 609 | Rd = Bits32(opcode, 2, 1); |
| 610 | setflags = true; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 611 | break; |
| 612 | default: |
| 613 | return false; |
| 614 | } |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 615 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 616 | if (!success) |
| 617 | return false; |
| 618 | |
| 619 | // The context specifies that Rm is to be moved into Rd. |
| 620 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 621 | eRegisterKindDWARF, |
| 622 | dwarf_r0 + Rm, |
| 623 | 0 }; |
| 624 | |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 625 | if (Rd == 15) |
| 626 | { |
| 627 | if (!ALUWritePC (context, reg_value)) |
| 628 | return false; |
| 629 | } |
| 630 | else |
| 631 | { |
| 632 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, reg_value)) |
| 633 | return false; |
| 634 | if (setflags) |
| 635 | { |
| 636 | m_new_inst_cpsr = m_inst_cpsr; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 637 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(reg_value, CPSR_N)); |
| 638 | SetBit32(m_new_inst_cpsr, CPSR_Z, reg_value == 0 ? 1 : 0); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 639 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 640 | { |
| 641 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 642 | return false; |
| 643 | } |
| 644 | } |
| 645 | } |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 646 | } |
| 647 | return true; |
| 648 | } |
| 649 | |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame^] | 650 | // Move (immediate) writes an immediate value to the destination register. It |
| 651 | // can optionally update the condition flags based on the value. |
| 652 | // MOV (immediate) |
| 653 | bool |
| 654 | EmulateInstructionARM::EmulateMovRdImm (ARMEncoding encoding) |
| 655 | { |
| 656 | #if 0 |
| 657 | // ARM pseudo code... |
| 658 | if (ConditionPassed()) |
| 659 | { |
| 660 | EncodingSpecificOperations(); |
| 661 | result = imm32; |
| 662 | if d == 15 then // Can only occur for ARM encoding |
| 663 | ALUWritePC(result); // setflags is always FALSE here |
| 664 | else |
| 665 | R[d] = result; |
| 666 | if setflags then |
| 667 | APSR.N = result<31>; |
| 668 | APSR.Z = IsZeroBit(result); |
| 669 | APSR.C = carry; |
| 670 | // APSR.V unchanged |
| 671 | } |
| 672 | #endif |
| 673 | bool success = false; |
| 674 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 675 | if (!success) |
| 676 | return false; |
| 677 | |
| 678 | if (ConditionPassed()) |
| 679 | { |
| 680 | uint32_t Rd; // the destination register |
| 681 | uint32_t imm12; // some intermediate result |
| 682 | uint32_t imm32; // the immediate value to be written to Rd |
| 683 | uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C. |
| 684 | bool setflags; |
| 685 | switch (encoding) { |
| 686 | case eEncodingT1: |
| 687 | Rd = Bits32(opcode, 11, 8); |
| 688 | setflags = !InITBlock(); |
| 689 | imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) |
| 690 | carry = Bit32(m_inst_cpsr, CPSR_C); |
| 691 | break; |
| 692 | case eEncodingT2: |
| 693 | Rd = Bits32(opcode, 15, 12); |
| 694 | setflags = BitIsSet(opcode, 20); |
| 695 | imm12 = Bit32(opcode, 26) << 11 | Bits32(opcode, 14, 12) << 8 | Bits32(opcode, 7, 0); |
| 696 | imm32 = ThumbExpandImm_C(imm12, Bit32(m_inst_cpsr, CPSR_C), carry); |
| 697 | break; |
| 698 | default: |
| 699 | return false; |
| 700 | } |
| 701 | uint32_t result = imm32; |
| 702 | |
| 703 | // The context specifies that an immediate is to be moved into Rd. |
| 704 | EmulateInstruction::Context context = { EmulateInstruction::eContextImmediate, |
| 705 | 0, |
| 706 | 0, |
| 707 | 0 }; |
| 708 | |
| 709 | if (Rd == 15) |
| 710 | { |
| 711 | if (!ALUWritePC (context, result)) |
| 712 | return false; |
| 713 | } |
| 714 | else |
| 715 | { |
| 716 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
| 717 | return false; |
| 718 | if (setflags) |
| 719 | { |
| 720 | m_new_inst_cpsr = m_inst_cpsr; |
| 721 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(result, CPSR_N)); |
| 722 | SetBit32(m_new_inst_cpsr, CPSR_Z, result == 0 ? 1 : 0); |
| 723 | SetBit32(m_new_inst_cpsr, CPSR_C, carry); |
| 724 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 725 | { |
| 726 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 727 | return false; |
| 728 | } |
| 729 | } |
| 730 | } |
| 731 | } |
| 732 | return true; |
| 733 | } |
| 734 | |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 735 | // Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to |
| 736 | // the destination register. It can optionally update the condition flags based |
| 737 | // on the value. |
| 738 | // MVN (immediate) |
| 739 | bool |
| 740 | EmulateInstructionARM::EmulateMvnRdImm (ARMEncoding encoding) |
| 741 | { |
| 742 | #if 0 |
| 743 | // ARM pseudo code... |
| 744 | if (ConditionPassed()) |
| 745 | { |
| 746 | EncodingSpecificOperations(); |
| 747 | result = NOT(imm32); |
| 748 | if d == 15 then // Can only occur for ARM encoding |
| 749 | ALUWritePC(result); // setflags is always FALSE here |
| 750 | else |
| 751 | R[d] = result; |
| 752 | if setflags then |
| 753 | APSR.N = result<31>; |
| 754 | APSR.Z = IsZeroBit(result); |
| 755 | APSR.C = carry; |
| 756 | // APSR.V unchanged |
| 757 | } |
| 758 | #endif |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 759 | bool success = false; |
| 760 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 761 | if (!success) |
| 762 | return false; |
| 763 | |
| 764 | if (ConditionPassed()) |
| 765 | { |
| 766 | uint32_t Rd; // the destination register |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame^] | 767 | uint32_t imm12; // the first operand to ThumbExpandImm_C or ARMExpandImm_C |
| 768 | uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C |
| 769 | uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 770 | bool setflags; |
| 771 | switch (encoding) { |
| 772 | case eEncodingT1: |
| 773 | Rd = Bits32(opcode, 11, 8); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 774 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame^] | 775 | imm12 = Bit32(opcode, 26) << 11 | Bits32(opcode, 14, 12) << 8 | Bits32(opcode, 7, 0); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 776 | imm32 = ThumbExpandImm_C(imm12, Bit32(m_inst_cpsr, CPSR_C), carry); |
| 777 | break; |
| 778 | case eEncodingA1: |
| 779 | Rd = Bits32(opcode, 15, 12); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 780 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame^] | 781 | imm12 = Bits32(opcode, 11, 0); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 782 | imm32 = ARMExpandImm_C(imm12, Bit32(m_inst_cpsr, CPSR_C), carry); |
| 783 | break; |
| 784 | default: |
| 785 | return false; |
| 786 | } |
| 787 | uint32_t result = ~imm32; |
| 788 | |
| 789 | // The context specifies that an immediate is to be moved into Rd. |
| 790 | EmulateInstruction::Context context = { EmulateInstruction::eContextImmediate, |
| 791 | 0, |
| 792 | 0, |
| 793 | 0 }; |
| 794 | |
| 795 | if (Rd == 15) |
| 796 | { |
| 797 | if (!ALUWritePC (context, result)) |
| 798 | return false; |
| 799 | } |
| 800 | else |
| 801 | { |
| 802 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
| 803 | return false; |
| 804 | if (setflags) |
| 805 | { |
| 806 | m_new_inst_cpsr = m_inst_cpsr; |
| 807 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(result, CPSR_N)); |
| 808 | SetBit32(m_new_inst_cpsr, CPSR_Z, result == 0 ? 1 : 0); |
| 809 | SetBit32(m_new_inst_cpsr, CPSR_C, carry); |
| 810 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 811 | { |
| 812 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 813 | return false; |
| 814 | } |
| 815 | } |
| 816 | } |
| 817 | } |
| 818 | return true; |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 819 | } |
| 820 | |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 821 | // PC relative immediate load into register, possibly followed by ADD (SP plus register). |
| 822 | // LDR (literal) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 823 | bool |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 824 | EmulateInstructionARM::EmulateLDRRtPCRelative (ARMEncoding encoding) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 825 | { |
| 826 | #if 0 |
| 827 | // ARM pseudo code... |
| 828 | if (ConditionPassed()) |
| 829 | { |
| 830 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 831 | base = Align(PC,4); |
| 832 | address = if add then (base + imm32) else (base - imm32); |
| 833 | data = MemU[address,4]; |
| 834 | if t == 15 then |
| 835 | if address<1:0> == ‘00’ then LoadWritePC(data); else UNPREDICTABLE; |
| 836 | elsif UnalignedSupport() || address<1:0> = ‘00’ then |
| 837 | R[t] = data; |
| 838 | else // Can only apply before ARMv7 |
| 839 | if CurrentInstrSet() == InstrSet_ARM then |
| 840 | R[t] = ROR(data, 8*UInt(address<1:0>)); |
| 841 | else |
| 842 | R[t] = bits(32) UNKNOWN; |
| 843 | } |
| 844 | #endif |
| 845 | |
| 846 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 847 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 848 | if (!success) |
| 849 | return false; |
| 850 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 851 | if (ConditionPassed()) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 852 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 853 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 854 | if (!success) |
| 855 | return false; |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 856 | |
| 857 | // PC relative immediate load context |
| 858 | EmulateInstruction::Context context = {EmulateInstruction::eContextRegisterPlusOffset, |
| 859 | eRegisterKindGeneric, |
| 860 | LLDB_REGNUM_GENERIC_PC, |
| 861 | 0}; |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 862 | uint32_t Rt; // the destination register |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 863 | uint32_t imm32; // immediate offset from the PC |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 864 | bool add; // +imm32 or -imm32? |
| 865 | addr_t base; // the base address |
| 866 | addr_t address; // the PC relative address |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 867 | uint32_t data; // the literal data value from the PC relative load |
| 868 | switch (encoding) { |
| 869 | case eEncodingT1: |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 870 | Rt = Bits32(opcode, 10, 8); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 871 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32); |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 872 | add = true; |
| 873 | base = Align(pc + 4, 4); |
| 874 | context.arg2 = 4 + imm32; |
| 875 | break; |
| 876 | case eEncodingT2: |
| 877 | Rt = Bits32(opcode, 15, 12); |
| 878 | imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32); |
| 879 | add = BitIsSet(opcode, 23); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 880 | if (Rt == 15 && InITBlock() && !LastInITBlock()) |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 881 | return false; |
| 882 | base = Align(pc + 4, 4); |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 883 | context.arg2 = 4 + imm32; |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 884 | break; |
| 885 | default: |
| 886 | return false; |
| 887 | } |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 888 | |
| 889 | if (add) |
| 890 | address = base + imm32; |
| 891 | else |
| 892 | address = base - imm32; |
| 893 | data = ReadMemoryUnsigned(context, address, 4, 0, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 894 | if (!success) |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 895 | return false; |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 896 | |
| 897 | if (Rt == 15) |
| 898 | { |
| 899 | if (Bits32(address, 1, 0) == 0) |
| 900 | { |
| 901 | // In ARMv5T and above, this is an interworking branch. |
| 902 | if (!LoadWritePC(context, data)) |
| 903 | return false; |
| 904 | } |
| 905 | else |
| 906 | return false; |
| 907 | } |
| 908 | else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) |
| 909 | { |
| 910 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
| 911 | return false; |
| 912 | } |
| 913 | else // We don't handle ARM for now. |
| 914 | return false; |
| 915 | |
| 916 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 917 | return false; |
| 918 | } |
| 919 | return true; |
| 920 | } |
| 921 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 922 | // An add operation to adjust the SP. |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 923 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 924 | bool |
| 925 | EmulateInstructionARM::EmulateAddSPImmediate (ARMEncoding encoding) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 926 | { |
| 927 | #if 0 |
| 928 | // ARM pseudo code... |
| 929 | if (ConditionPassed()) |
| 930 | { |
| 931 | EncodingSpecificOperations(); |
| 932 | (result, carry, overflow) = AddWithCarry(SP, imm32, ‘0’); |
| 933 | if d == 15 then // Can only occur for ARM encoding |
| 934 | ALUWritePC(result); // setflags is always FALSE here |
| 935 | else |
| 936 | R[d] = result; |
| 937 | if setflags then |
| 938 | APSR.N = result<31>; |
| 939 | APSR.Z = IsZeroBit(result); |
| 940 | APSR.C = carry; |
| 941 | APSR.V = overflow; |
| 942 | } |
| 943 | #endif |
| 944 | |
| 945 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 946 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 947 | if (!success) |
| 948 | return false; |
| 949 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 950 | if (ConditionPassed()) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 951 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 952 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 953 | if (!success) |
| 954 | return false; |
| 955 | uint32_t imm32; // the immediate operand |
| 956 | switch (encoding) { |
| 957 | case eEncodingT2: |
| 958 | imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
| 959 | break; |
| 960 | default: |
| 961 | return false; |
| 962 | } |
| 963 | addr_t sp_offset = imm32; |
| 964 | addr_t addr = sp + sp_offset; // the adjusted stack pointer value |
| 965 | |
| 966 | EmulateInstruction::Context context = { EmulateInstruction::eContextAdjustStackPointer, |
| 967 | eRegisterKindGeneric, |
| 968 | LLDB_REGNUM_GENERIC_SP, |
| 969 | sp_offset }; |
| 970 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 971 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 972 | return false; |
| 973 | } |
| 974 | return true; |
| 975 | } |
| 976 | |
| 977 | // An add operation to adjust the SP. |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 978 | // ADD (SP plus register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 979 | bool |
| 980 | EmulateInstructionARM::EmulateAddSPRm (ARMEncoding encoding) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 981 | { |
| 982 | #if 0 |
| 983 | // ARM pseudo code... |
| 984 | if (ConditionPassed()) |
| 985 | { |
| 986 | EncodingSpecificOperations(); |
| 987 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 988 | (result, carry, overflow) = AddWithCarry(SP, shifted, ‘0’); |
| 989 | if d == 15 then |
| 990 | ALUWritePC(result); // setflags is always FALSE here |
| 991 | else |
| 992 | R[d] = result; |
| 993 | if setflags then |
| 994 | APSR.N = result<31>; |
| 995 | APSR.Z = IsZeroBit(result); |
| 996 | APSR.C = carry; |
| 997 | APSR.V = overflow; |
| 998 | } |
| 999 | #endif |
| 1000 | |
| 1001 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1002 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1003 | if (!success) |
| 1004 | return false; |
| 1005 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1006 | if (ConditionPassed()) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1007 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1008 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1009 | if (!success) |
| 1010 | return false; |
| 1011 | uint32_t Rm; // the second operand |
| 1012 | switch (encoding) { |
| 1013 | case eEncodingT2: |
| 1014 | Rm = Bits32(opcode, 6, 3); |
| 1015 | break; |
| 1016 | default: |
| 1017 | return false; |
| 1018 | } |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1019 | int32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1020 | if (!success) |
| 1021 | return false; |
| 1022 | |
| 1023 | addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value |
| 1024 | |
| 1025 | EmulateInstruction::Context context = { EmulateInstruction::eContextAdjustStackPointer, |
| 1026 | eRegisterKindGeneric, |
| 1027 | LLDB_REGNUM_GENERIC_SP, |
| 1028 | reg_value }; |
| 1029 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1030 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1031 | return false; |
| 1032 | } |
| 1033 | return true; |
| 1034 | } |
| 1035 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1036 | // Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine |
| 1037 | // at a PC-relative address, and changes instruction set from ARM to Thumb, or |
| 1038 | // from Thumb to ARM. |
| 1039 | // BLX (immediate) |
| 1040 | bool |
| 1041 | EmulateInstructionARM::EmulateBLXImmediate (ARMEncoding encoding) |
| 1042 | { |
| 1043 | #if 0 |
| 1044 | // ARM pseudo code... |
| 1045 | if (ConditionPassed()) |
| 1046 | { |
| 1047 | EncodingSpecificOperations(); |
| 1048 | if CurrentInstrSet() == InstrSet_ARM then |
| 1049 | LR = PC - 4; |
| 1050 | else |
| 1051 | LR = PC<31:1> : '1'; |
| 1052 | if targetInstrSet == InstrSet_ARM then |
| 1053 | targetAddress = Align(PC,4) + imm32; |
| 1054 | else |
| 1055 | targetAddress = PC + imm32; |
| 1056 | SelectInstrSet(targetInstrSet); |
| 1057 | BranchWritePC(targetAddress); |
| 1058 | } |
| 1059 | #endif |
| 1060 | |
| 1061 | bool success = false; |
| 1062 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1063 | if (!success) |
| 1064 | return false; |
| 1065 | |
| 1066 | if (ConditionPassed()) |
| 1067 | { |
| 1068 | EmulateInstruction::Context context = { EmulateInstruction::eContextRelativeBranchImmediate, 0, 0, 0}; |
| 1069 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1070 | if (!success) |
| 1071 | return false; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1072 | addr_t lr; // next instruction address |
| 1073 | addr_t target; // target address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1074 | int32_t imm32; // PC-relative offset |
| 1075 | switch (encoding) { |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1076 | case eEncodingT1: |
| 1077 | { |
| 1078 | lr = (pc + 4) | 1u; // return address |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1079 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1080 | uint32_t imm10 = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1081 | uint32_t J1 = Bit32(opcode, 13); |
| 1082 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1083 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 1084 | uint32_t I1 = !(J1 ^ S); |
| 1085 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1086 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1087 | imm32 = llvm::SignExtend32<25>(imm25); |
| 1088 | target = pc + 4 + imm32; |
| 1089 | context.arg1 = 4 + imm32; // signed offset |
| 1090 | context.arg2 = eModeThumb; // target instruction set |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1091 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1092 | return false; |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1093 | break; |
| 1094 | } |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1095 | case eEncodingT2: |
| 1096 | { |
| 1097 | lr = (pc + 4) | 1u; // return address |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1098 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1099 | uint32_t imm10H = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1100 | uint32_t J1 = Bit32(opcode, 13); |
| 1101 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1102 | uint32_t imm10L = Bits32(opcode, 10, 1); |
| 1103 | uint32_t I1 = !(J1 ^ S); |
| 1104 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1105 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1106 | imm32 = llvm::SignExtend32<25>(imm25); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1107 | target = Align(pc + 4, 4) + imm32; |
| 1108 | context.arg1 = 4 + imm32; // signed offset |
| 1109 | context.arg2 = eModeARM; // target instruction set |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1110 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1111 | return false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1112 | break; |
| 1113 | } |
Johnny Chen | c47d0ca | 2011-02-08 18:58:31 +0000 | [diff] [blame] | 1114 | case eEncodingA1: |
| 1115 | lr = pc + 4; // return address |
| 1116 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1117 | target = Align(pc + 8, 4) + imm32; |
| 1118 | context.arg1 = 8 + imm32; // signed offset |
| 1119 | context.arg2 = eModeARM; // target instruction set |
Johnny Chen | c47d0ca | 2011-02-08 18:58:31 +0000 | [diff] [blame] | 1120 | break; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1121 | case eEncodingA2: |
| 1122 | lr = pc + 4; // return address |
| 1123 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1); |
| 1124 | target = pc + 8 + imm32; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1125 | context.arg1 = 8 + imm32; // signed offset |
| 1126 | context.arg2 = eModeThumb; // target instruction set |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1127 | break; |
| 1128 | default: |
| 1129 | return false; |
| 1130 | } |
| 1131 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1132 | return false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1133 | if (!BranchWritePC(context, target)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1134 | return false; |
| 1135 | } |
| 1136 | return true; |
| 1137 | } |
| 1138 | |
| 1139 | // Branch with Link and Exchange (register) calls a subroutine at an address and |
| 1140 | // instruction set specified by a register. |
| 1141 | // BLX (register) |
| 1142 | bool |
| 1143 | EmulateInstructionARM::EmulateBLXRm (ARMEncoding encoding) |
| 1144 | { |
| 1145 | #if 0 |
| 1146 | // ARM pseudo code... |
| 1147 | if (ConditionPassed()) |
| 1148 | { |
| 1149 | EncodingSpecificOperations(); |
| 1150 | target = R[m]; |
| 1151 | if CurrentInstrSet() == InstrSet_ARM then |
| 1152 | next_instr_addr = PC - 4; |
| 1153 | LR = next_instr_addr; |
| 1154 | else |
| 1155 | next_instr_addr = PC - 2; |
| 1156 | LR = next_instr_addr<31:1> : ‘1’; |
| 1157 | BXWritePC(target); |
| 1158 | } |
| 1159 | #endif |
| 1160 | |
| 1161 | bool success = false; |
| 1162 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1163 | if (!success) |
| 1164 | return false; |
| 1165 | |
| 1166 | if (ConditionPassed()) |
| 1167 | { |
| 1168 | EmulateInstruction::Context context = { EmulateInstruction::eContextAbsoluteBranchRegister, 0, 0, 0}; |
| 1169 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1170 | addr_t lr; // next instruction address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1171 | if (!success) |
| 1172 | return false; |
| 1173 | uint32_t Rm; // the register with the target address |
| 1174 | switch (encoding) { |
| 1175 | case eEncodingT1: |
| 1176 | lr = (pc + 2) | 1u; // return address |
| 1177 | Rm = Bits32(opcode, 6, 3); |
| 1178 | // if m == 15 then UNPREDICTABLE; |
| 1179 | if (Rm == 15) |
| 1180 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1181 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1182 | return false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1183 | break; |
| 1184 | case eEncodingA1: |
| 1185 | lr = pc + 4; // return address |
| 1186 | Rm = Bits32(opcode, 3, 0); |
| 1187 | // if m == 15 then UNPREDICTABLE; |
| 1188 | if (Rm == 15) |
| 1189 | return false; |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1190 | break; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1191 | default: |
| 1192 | return false; |
| 1193 | } |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1194 | addr_t target = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 1195 | if (!success) |
| 1196 | return false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1197 | context.arg0 = eRegisterKindDWARF; |
| 1198 | context.arg1 = dwarf_r0 + Rm; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1199 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1200 | return false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1201 | if (!BXWritePC(context, target)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1202 | return false; |
| 1203 | } |
| 1204 | return true; |
| 1205 | } |
| 1206 | |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1207 | // Branch and Exchange causes a branch to an address and instruction set specified by a register. |
| 1208 | // BX |
| 1209 | bool |
| 1210 | EmulateInstructionARM::EmulateBXRm (ARMEncoding encoding) |
| 1211 | { |
| 1212 | #if 0 |
| 1213 | // ARM pseudo code... |
| 1214 | if (ConditionPassed()) |
| 1215 | { |
| 1216 | EncodingSpecificOperations(); |
| 1217 | BXWritePC(R[m]); |
| 1218 | } |
| 1219 | #endif |
| 1220 | |
| 1221 | bool success = false; |
| 1222 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1223 | if (!success) |
| 1224 | return false; |
| 1225 | |
| 1226 | if (ConditionPassed()) |
| 1227 | { |
| 1228 | EmulateInstruction::Context context = { EmulateInstruction::eContextAbsoluteBranchRegister, 0, 0, 0}; |
| 1229 | uint32_t Rm; // the register with the target address |
| 1230 | switch (encoding) { |
| 1231 | case eEncodingT1: |
| 1232 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1233 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1234 | return false; |
| 1235 | break; |
| 1236 | case eEncodingA1: |
| 1237 | Rm = Bits32(opcode, 3, 0); |
| 1238 | break; |
| 1239 | default: |
| 1240 | return false; |
| 1241 | } |
| 1242 | addr_t target = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 1243 | if (!success) |
| 1244 | return false; |
| 1245 | context.arg0 = eRegisterKindDWARF; |
| 1246 | context.arg1 = dwarf_r0 + Rm; |
| 1247 | if (!BXWritePC(context, target)) |
| 1248 | return false; |
| 1249 | } |
| 1250 | return true; |
| 1251 | } |
| 1252 | |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1253 | // Set r7 to point to some ip offset. |
| 1254 | // SUB (immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1255 | bool |
| 1256 | EmulateInstructionARM::EmulateSubR7IPImmediate (ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1257 | { |
| 1258 | #if 0 |
| 1259 | // ARM pseudo code... |
| 1260 | if (ConditionPassed()) |
| 1261 | { |
| 1262 | EncodingSpecificOperations(); |
| 1263 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 1264 | if d == 15 then // Can only occur for ARM encoding |
| 1265 | ALUWritePC(result); // setflags is always FALSE here |
| 1266 | else |
| 1267 | R[d] = result; |
| 1268 | if setflags then |
| 1269 | APSR.N = result<31>; |
| 1270 | APSR.Z = IsZeroBit(result); |
| 1271 | APSR.C = carry; |
| 1272 | APSR.V = overflow; |
| 1273 | } |
| 1274 | #endif |
| 1275 | |
| 1276 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1277 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1278 | if (!success) |
| 1279 | return false; |
| 1280 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1281 | if (ConditionPassed()) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1282 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1283 | const addr_t ip = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r12, 0, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1284 | if (!success) |
| 1285 | return false; |
| 1286 | uint32_t imm32; |
| 1287 | switch (encoding) { |
| 1288 | case eEncodingA1: |
| 1289 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 1290 | break; |
| 1291 | default: |
| 1292 | return false; |
| 1293 | } |
| 1294 | addr_t ip_offset = imm32; |
| 1295 | addr_t addr = ip - ip_offset; // the adjusted ip value |
| 1296 | |
| 1297 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 1298 | eRegisterKindDWARF, |
| 1299 | dwarf_r12, |
| 1300 | -ip_offset }; |
| 1301 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1302 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r7, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1303 | return false; |
| 1304 | } |
| 1305 | return true; |
| 1306 | } |
| 1307 | |
| 1308 | // Set ip to point to some stack offset. |
| 1309 | // SUB (SP minus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1310 | bool |
| 1311 | EmulateInstructionARM::EmulateSubIPSPImmediate (ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1312 | { |
| 1313 | #if 0 |
| 1314 | // ARM pseudo code... |
| 1315 | if (ConditionPassed()) |
| 1316 | { |
| 1317 | EncodingSpecificOperations(); |
| 1318 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 1319 | if d == 15 then // Can only occur for ARM encoding |
| 1320 | ALUWritePC(result); // setflags is always FALSE here |
| 1321 | else |
| 1322 | R[d] = result; |
| 1323 | if setflags then |
| 1324 | APSR.N = result<31>; |
| 1325 | APSR.Z = IsZeroBit(result); |
| 1326 | APSR.C = carry; |
| 1327 | APSR.V = overflow; |
| 1328 | } |
| 1329 | #endif |
| 1330 | |
| 1331 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1332 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1333 | if (!success) |
| 1334 | return false; |
| 1335 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1336 | if (ConditionPassed()) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1337 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1338 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1339 | if (!success) |
| 1340 | return false; |
| 1341 | uint32_t imm32; |
| 1342 | switch (encoding) { |
| 1343 | case eEncodingA1: |
| 1344 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 1345 | break; |
| 1346 | default: |
| 1347 | return false; |
| 1348 | } |
| 1349 | addr_t sp_offset = imm32; |
| 1350 | addr_t addr = sp - sp_offset; // the adjusted stack pointer value |
| 1351 | |
| 1352 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 1353 | eRegisterKindGeneric, |
| 1354 | LLDB_REGNUM_GENERIC_SP, |
| 1355 | -sp_offset }; |
| 1356 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1357 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r12, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1358 | return false; |
| 1359 | } |
| 1360 | return true; |
| 1361 | } |
| 1362 | |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1363 | // A sub operation to adjust the SP -- allocate space for local storage. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1364 | bool |
| 1365 | EmulateInstructionARM::EmulateSubSPImmdiate (ARMEncoding encoding) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1366 | { |
| 1367 | #if 0 |
| 1368 | // ARM pseudo code... |
| 1369 | if (ConditionPassed()) |
| 1370 | { |
| 1371 | EncodingSpecificOperations(); |
| 1372 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 1373 | if d == 15 then // Can only occur for ARM encoding |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1374 | ALUWritePC(result); // setflags is always FALSE here |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1375 | else |
| 1376 | R[d] = result; |
| 1377 | if setflags then |
| 1378 | APSR.N = result<31>; |
| 1379 | APSR.Z = IsZeroBit(result); |
| 1380 | APSR.C = carry; |
| 1381 | APSR.V = overflow; |
| 1382 | } |
| 1383 | #endif |
| 1384 | |
| 1385 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1386 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1387 | if (!success) |
| 1388 | return false; |
| 1389 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1390 | if (ConditionPassed()) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1391 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1392 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1393 | if (!success) |
| 1394 | return false; |
| 1395 | uint32_t imm32; |
| 1396 | switch (encoding) { |
Johnny Chen | e445502 | 2011-01-26 00:08:59 +0000 | [diff] [blame] | 1397 | case eEncodingT1: |
| 1398 | imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1399 | case eEncodingT2: |
| 1400 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 1401 | break; |
| 1402 | case eEncodingT3: |
| 1403 | imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) |
| 1404 | break; |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1405 | case eEncodingA1: |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1406 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1407 | break; |
| 1408 | default: |
| 1409 | return false; |
| 1410 | } |
| 1411 | addr_t sp_offset = imm32; |
| 1412 | addr_t addr = sp - sp_offset; // the adjusted stack pointer value |
| 1413 | |
| 1414 | EmulateInstruction::Context context = { EmulateInstruction::eContextAdjustStackPointer, |
| 1415 | eRegisterKindGeneric, |
| 1416 | LLDB_REGNUM_GENERIC_SP, |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1417 | -sp_offset }; |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1418 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1419 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1420 | return false; |
| 1421 | } |
| 1422 | return true; |
| 1423 | } |
| 1424 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1425 | // A store operation to the stack that also updates the SP. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1426 | bool |
| 1427 | EmulateInstructionARM::EmulateSTRRtSP (ARMEncoding encoding) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1428 | { |
| 1429 | #if 0 |
| 1430 | // ARM pseudo code... |
| 1431 | if (ConditionPassed()) |
| 1432 | { |
| 1433 | EncodingSpecificOperations(); |
| 1434 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 1435 | address = if index then offset_addr else R[n]; |
| 1436 | MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; |
| 1437 | if wback then R[n] = offset_addr; |
| 1438 | } |
| 1439 | #endif |
| 1440 | |
| 1441 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1442 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1443 | if (!success) |
| 1444 | return false; |
| 1445 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1446 | if (ConditionPassed()) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1447 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1448 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1449 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1450 | if (!success) |
| 1451 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1452 | uint32_t Rt; // the source register |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1453 | uint32_t imm12; |
| 1454 | switch (encoding) { |
| 1455 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 1456 | Rt = Bits32(opcode, 15, 12); |
| 1457 | imm12 = Bits32(opcode, 11, 0); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1458 | break; |
| 1459 | default: |
| 1460 | return false; |
| 1461 | } |
| 1462 | addr_t sp_offset = imm12; |
| 1463 | addr_t addr = sp - sp_offset; |
| 1464 | |
| 1465 | EmulateInstruction::Context context = { EmulateInstruction::eContextPushRegisterOnStack, eRegisterKindDWARF, 0, 0 }; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1466 | if (Rt != 15) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1467 | { |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1468 | context.arg1 = dwarf_r0 + Rt; // arg1 in the context is the DWARF register number |
| 1469 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1470 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, context.arg1, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1471 | if (!success) |
| 1472 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1473 | if (!WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1474 | return false; |
| 1475 | } |
| 1476 | else |
| 1477 | { |
| 1478 | context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number |
| 1479 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1480 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1481 | if (!success) |
| 1482 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1483 | if (!WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1484 | return false; |
| 1485 | } |
| 1486 | |
| 1487 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1488 | context.arg0 = eRegisterKindGeneric; |
| 1489 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1490 | context.arg2 = -sp_offset; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1491 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1492 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1493 | return false; |
| 1494 | } |
| 1495 | return true; |
| 1496 | } |
| 1497 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1498 | // Vector Push stores multiple extension registers to the stack. |
| 1499 | // It also updates SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1500 | bool |
| 1501 | EmulateInstructionARM::EmulateVPUSH (ARMEncoding encoding) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1502 | { |
| 1503 | #if 0 |
| 1504 | // ARM pseudo code... |
| 1505 | if (ConditionPassed()) |
| 1506 | { |
| 1507 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1508 | address = SP - imm32; |
| 1509 | SP = SP - imm32; |
| 1510 | if single_regs then |
| 1511 | for r = 0 to regs-1 |
| 1512 | MemA[address,4] = S[d+r]; address = address+4; |
| 1513 | else |
| 1514 | for r = 0 to regs-1 |
| 1515 | // Store as two word-aligned words in the correct order for current endianness. |
| 1516 | MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>; |
| 1517 | MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>; |
| 1518 | address = address+8; |
| 1519 | } |
| 1520 | #endif |
| 1521 | |
| 1522 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1523 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1524 | if (!success) |
| 1525 | return false; |
| 1526 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1527 | if (ConditionPassed()) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1528 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1529 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1530 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1531 | if (!success) |
| 1532 | return false; |
| 1533 | bool single_regs; |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1534 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1535 | uint32_t imm32; // stack offset |
| 1536 | uint32_t regs; // number of registers |
| 1537 | switch (encoding) { |
| 1538 | case eEncodingT1: |
| 1539 | case eEncodingA1: |
| 1540 | single_regs = false; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1541 | d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1542 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1543 | // If UInt(imm8) is odd, see "FSTMX". |
| 1544 | regs = Bits32(opcode, 7, 0) / 2; |
| 1545 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1546 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1547 | return false; |
| 1548 | break; |
| 1549 | case eEncodingT2: |
| 1550 | case eEncodingA2: |
| 1551 | single_regs = true; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1552 | d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1553 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1554 | regs = Bits32(opcode, 7, 0); |
| 1555 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1556 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1557 | return false; |
| 1558 | break; |
| 1559 | default: |
| 1560 | return false; |
| 1561 | } |
| 1562 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1563 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1564 | addr_t sp_offset = imm32; |
| 1565 | addr_t addr = sp - sp_offset; |
| 1566 | uint32_t i; |
| 1567 | |
| 1568 | EmulateInstruction::Context context = { EmulateInstruction::eContextPushRegisterOnStack, eRegisterKindDWARF, 0, 0 }; |
| 1569 | for (i=d; i<regs; ++i) |
| 1570 | { |
| 1571 | context.arg1 = start_reg + i; // arg1 in the context is the DWARF register number |
| 1572 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
| 1573 | // uint64_t to accommodate 64-bit registers. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1574 | uint64_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, context.arg1, 0, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1575 | if (!success) |
| 1576 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1577 | if (!WriteMemoryUnsigned (context, addr, reg_value, reg_byte_size)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1578 | return false; |
| 1579 | addr += reg_byte_size; |
| 1580 | } |
| 1581 | |
| 1582 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1583 | context.arg0 = eRegisterKindGeneric; |
| 1584 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1585 | context.arg2 = -sp_offset; |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1586 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1587 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1588 | return false; |
| 1589 | } |
| 1590 | return true; |
| 1591 | } |
| 1592 | |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1593 | // Vector Pop loads multiple extension registers from the stack. |
| 1594 | // It also updates SP to point just above the loaded data. |
| 1595 | bool |
| 1596 | EmulateInstructionARM::EmulateVPOP (ARMEncoding encoding) |
| 1597 | { |
| 1598 | #if 0 |
| 1599 | // ARM pseudo code... |
| 1600 | if (ConditionPassed()) |
| 1601 | { |
| 1602 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1603 | address = SP; |
| 1604 | SP = SP + imm32; |
| 1605 | if single_regs then |
| 1606 | for r = 0 to regs-1 |
| 1607 | S[d+r] = MemA[address,4]; address = address+4; |
| 1608 | else |
| 1609 | for r = 0 to regs-1 |
| 1610 | word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8; |
| 1611 | // Combine the word-aligned words in the correct order for current endianness. |
| 1612 | D[d+r] = if BigEndian() then word1:word2 else word2:word1; |
| 1613 | } |
| 1614 | #endif |
| 1615 | |
| 1616 | bool success = false; |
| 1617 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1618 | if (!success) |
| 1619 | return false; |
| 1620 | |
| 1621 | if (ConditionPassed()) |
| 1622 | { |
| 1623 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1624 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
| 1625 | if (!success) |
| 1626 | return false; |
| 1627 | bool single_regs; |
| 1628 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
| 1629 | uint32_t imm32; // stack offset |
| 1630 | uint32_t regs; // number of registers |
| 1631 | switch (encoding) { |
| 1632 | case eEncodingT1: |
| 1633 | case eEncodingA1: |
| 1634 | single_regs = false; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1635 | d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1636 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1637 | // If UInt(imm8) is odd, see "FLDMX". |
| 1638 | regs = Bits32(opcode, 7, 0) / 2; |
| 1639 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1640 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1641 | return false; |
| 1642 | break; |
| 1643 | case eEncodingT2: |
| 1644 | case eEncodingA2: |
| 1645 | single_regs = true; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1646 | d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1647 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1648 | regs = Bits32(opcode, 7, 0); |
| 1649 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1650 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1651 | return false; |
| 1652 | break; |
| 1653 | default: |
| 1654 | return false; |
| 1655 | } |
| 1656 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1657 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1658 | addr_t sp_offset = imm32; |
| 1659 | addr_t addr = sp; |
| 1660 | uint32_t i; |
| 1661 | uint64_t data; // uint64_t to accomodate 64-bit registers. |
| 1662 | |
| 1663 | EmulateInstruction::Context context = { EmulateInstruction::eContextPopRegisterOffStack, eRegisterKindDWARF, 0, 0 }; |
| 1664 | for (i=d; i<regs; ++i) |
| 1665 | { |
| 1666 | context.arg1 = start_reg + i; // arg1 in the context is the DWARF register number |
| 1667 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
| 1668 | data = ReadMemoryUnsigned(context, addr, reg_byte_size, 0, &success); |
| 1669 | if (!success) |
| 1670 | return false; |
| 1671 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, context.arg1, data)) |
| 1672 | return false; |
| 1673 | addr += reg_byte_size; |
| 1674 | } |
| 1675 | |
| 1676 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1677 | context.arg0 = eRegisterKindGeneric; |
| 1678 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
| 1679 | context.arg2 = sp_offset; |
| 1680 | |
| 1681 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
| 1682 | return false; |
| 1683 | } |
| 1684 | return true; |
| 1685 | } |
| 1686 | |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1687 | // SVC (previously SWI) |
| 1688 | bool |
| 1689 | EmulateInstructionARM::EmulateSVC (ARMEncoding encoding) |
| 1690 | { |
| 1691 | #if 0 |
| 1692 | // ARM pseudo code... |
| 1693 | if (ConditionPassed()) |
| 1694 | { |
| 1695 | EncodingSpecificOperations(); |
| 1696 | CallSupervisor(); |
| 1697 | } |
| 1698 | #endif |
| 1699 | |
| 1700 | bool success = false; |
| 1701 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1702 | if (!success) |
| 1703 | return false; |
| 1704 | |
| 1705 | if (ConditionPassed()) |
| 1706 | { |
| 1707 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1708 | addr_t lr; // next instruction address |
| 1709 | if (!success) |
| 1710 | return false; |
| 1711 | uint32_t imm32; // the immediate constant |
| 1712 | uint32_t mode; // ARM or Thumb mode |
| 1713 | switch (encoding) { |
| 1714 | case eEncodingT1: |
| 1715 | lr = (pc + 2) | 1u; // return address |
| 1716 | imm32 = Bits32(opcode, 7, 0); |
| 1717 | mode = eModeThumb; |
| 1718 | break; |
| 1719 | case eEncodingA1: |
| 1720 | lr = pc + 4; // return address |
| 1721 | imm32 = Bits32(opcode, 23, 0); |
| 1722 | mode = eModeARM; |
| 1723 | break; |
| 1724 | default: |
| 1725 | return false; |
| 1726 | } |
| 1727 | EmulateInstruction::Context context = { EmulateInstruction::eContextSupervisorCall, mode, imm32, 0}; |
| 1728 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1729 | return false; |
| 1730 | } |
| 1731 | return true; |
| 1732 | } |
| 1733 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 1734 | // If Then makes up to four following instructions (the IT block) conditional. |
| 1735 | bool |
| 1736 | EmulateInstructionARM::EmulateIT (ARMEncoding encoding) |
| 1737 | { |
| 1738 | #if 0 |
| 1739 | // ARM pseudo code... |
| 1740 | EncodingSpecificOperations(); |
| 1741 | ITSTATE.IT<7:0> = firstcond:mask; |
| 1742 | #endif |
| 1743 | |
| 1744 | bool success = false; |
| 1745 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1746 | if (!success) |
| 1747 | return false; |
| 1748 | |
| 1749 | m_it_session.InitIT(Bits32(opcode, 7, 0)); |
| 1750 | return true; |
| 1751 | } |
| 1752 | |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1753 | // Branch causes a branch to a target address. |
| 1754 | bool |
| 1755 | EmulateInstructionARM::EmulateB (ARMEncoding encoding) |
| 1756 | { |
| 1757 | #if 0 |
| 1758 | // ARM pseudo code... |
| 1759 | if (ConditionPassed()) |
| 1760 | { |
| 1761 | EncodingSpecificOperations(); |
| 1762 | BranchWritePC(PC + imm32); |
| 1763 | } |
| 1764 | #endif |
| 1765 | |
| 1766 | bool success = false; |
| 1767 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1768 | if (!success) |
| 1769 | return false; |
| 1770 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1771 | if (ConditionPassed()) |
| 1772 | { |
| 1773 | EmulateInstruction::Context context = { EmulateInstruction::eContextRelativeBranchImmediate, 0, 0, 0}; |
| 1774 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1775 | if (!success) |
| 1776 | return false; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1777 | addr_t target; // target address |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1778 | int32_t imm32; // PC-relative offset |
| 1779 | switch (encoding) { |
| 1780 | case eEncodingT1: |
| 1781 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 1782 | imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1); |
| 1783 | target = pc + 4 + imm32; |
| 1784 | context.arg1 = 4 + imm32; // signed offset |
| 1785 | context.arg2 = eModeThumb; // target instruction set |
| 1786 | break; |
| 1787 | case eEncodingT2: |
| 1788 | imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0)); |
| 1789 | target = pc + 4 + imm32; |
| 1790 | context.arg1 = 4 + imm32; // signed offset |
| 1791 | context.arg2 = eModeThumb; // target instruction set |
| 1792 | break; |
| 1793 | case eEncodingT3: |
| 1794 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 1795 | { |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1796 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1797 | uint32_t imm6 = Bits32(opcode, 21, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1798 | uint32_t J1 = Bit32(opcode, 13); |
| 1799 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1800 | uint32_t imm11 = Bits32(opcode, 10, 0); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1801 | uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1802 | imm32 = llvm::SignExtend32<21>(imm21); |
| 1803 | target = pc + 4 + imm32; |
| 1804 | context.arg1 = eModeThumb; // target instruction set |
| 1805 | context.arg2 = 4 + imm32; // signed offset |
| 1806 | break; |
| 1807 | } |
| 1808 | case eEncodingT4: |
| 1809 | { |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1810 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1811 | uint32_t imm10 = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1812 | uint32_t J1 = Bit32(opcode, 13); |
| 1813 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1814 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 1815 | uint32_t I1 = !(J1 ^ S); |
| 1816 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1817 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1818 | imm32 = llvm::SignExtend32<25>(imm25); |
| 1819 | target = pc + 4 + imm32; |
| 1820 | context.arg1 = eModeThumb; // target instruction set |
| 1821 | context.arg2 = 4 + imm32; // signed offset |
| 1822 | break; |
| 1823 | } |
| 1824 | case eEncodingA1: |
| 1825 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); |
| 1826 | target = pc + 8 + imm32; |
| 1827 | context.arg1 = eModeARM; // target instruction set |
| 1828 | context.arg2 = 8 + imm32; // signed offset |
| 1829 | break; |
| 1830 | default: |
| 1831 | return false; |
| 1832 | } |
| 1833 | if (!BranchWritePC(context, target)) |
| 1834 | return false; |
| 1835 | } |
| 1836 | return true; |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1837 | } |
| 1838 | |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1839 | // Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with |
| 1840 | // zero and conditionally branch forward a constant value. They do not affect the condition flags. |
| 1841 | // CBNZ, CBZ |
| 1842 | bool |
| 1843 | EmulateInstructionARM::EmulateCB (ARMEncoding encoding) |
| 1844 | { |
| 1845 | #if 0 |
| 1846 | // ARM pseudo code... |
| 1847 | EncodingSpecificOperations(); |
| 1848 | if nonzero ^ IsZero(R[n]) then |
| 1849 | BranchWritePC(PC + imm32); |
| 1850 | #endif |
| 1851 | |
| 1852 | bool success = false; |
| 1853 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1854 | if (!success) |
| 1855 | return false; |
| 1856 | |
| 1857 | // Read the register value from the operand register Rn. |
| 1858 | uint32_t reg_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Bits32(opcode, 2, 0), 0, &success); |
| 1859 | if (!success) |
| 1860 | return false; |
| 1861 | |
| 1862 | EmulateInstruction::Context context = { EmulateInstruction::eContextRelativeBranchImmediate, 0, 0, 0}; |
| 1863 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1864 | if (!success) |
| 1865 | return false; |
| 1866 | |
| 1867 | addr_t target; // target address |
| 1868 | uint32_t imm32; // PC-relative offset to branch forward |
| 1869 | bool nonzero; |
| 1870 | switch (encoding) { |
| 1871 | case eEncodingT1: |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1872 | imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1873 | nonzero = BitIsSet(opcode, 11); |
| 1874 | target = pc + 4 + imm32; |
| 1875 | context.arg1 = 4 + imm32; // signed offset |
| 1876 | context.arg2 = eModeThumb; // target instruction set |
| 1877 | break; |
| 1878 | default: |
| 1879 | return false; |
| 1880 | } |
| 1881 | if (nonzero ^ (reg_val == 0)) |
| 1882 | if (!BranchWritePC(context, target)) |
| 1883 | return false; |
| 1884 | |
| 1885 | return true; |
| 1886 | } |
| 1887 | |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1888 | // ADD <Rdn>, <Rm> |
| 1889 | // where <Rdn> the destination register is also the first operand register |
| 1890 | // and <Rm> is the second operand register. |
| 1891 | bool |
| 1892 | EmulateInstructionARM::EmulateAddRdnRm (ARMEncoding encoding) |
| 1893 | { |
| 1894 | #if 0 |
| 1895 | // ARM pseudo code... |
| 1896 | if ConditionPassed() then |
| 1897 | EncodingSpecificOperations(); |
| 1898 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 1899 | (result, carry, overflow) = AddWithCarry(R[n], shifted, '0'); |
| 1900 | if d == 15 then |
| 1901 | ALUWritePC(result); // setflags is always FALSE here |
| 1902 | else |
| 1903 | R[d] = result; |
| 1904 | if setflags then |
| 1905 | APSR.N = result<31>; |
| 1906 | APSR.Z = IsZeroBit(result); |
| 1907 | APSR.C = carry; |
| 1908 | APSR.V = overflow; |
| 1909 | #endif |
| 1910 | |
| 1911 | bool success = false; |
| 1912 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1913 | if (!success) |
| 1914 | return false; |
| 1915 | |
| 1916 | if (ConditionPassed()) |
| 1917 | { |
| 1918 | uint32_t Rd, Rn, Rm; |
| 1919 | //bool setflags = false; |
| 1920 | switch (encoding) |
| 1921 | { |
| 1922 | case eEncodingT2: |
| 1923 | // setflags = FALSE |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1924 | Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1925 | Rm = Bits32(opcode, 6, 3); |
| 1926 | if (Rn == 15 && Rm == 15) |
| 1927 | return false; |
| 1928 | break; |
| 1929 | default: |
| 1930 | return false; |
| 1931 | } |
| 1932 | |
| 1933 | int32_t result, val1, val2; |
| 1934 | // Read the first operand. |
| 1935 | if (Rn == 15) |
| 1936 | val1 = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1937 | else |
| 1938 | val1 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 1939 | if (!success) |
| 1940 | return false; |
| 1941 | |
| 1942 | // Read the second operand. |
| 1943 | if (Rm == 15) |
| 1944 | val2 = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1945 | else |
| 1946 | val2 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 1947 | if (!success) |
| 1948 | return false; |
| 1949 | |
| 1950 | result = val1 + val2; |
| 1951 | EmulateInstruction::Context context = { EmulateInstruction::eContextImmediate, |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 1952 | 0, |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1953 | 0, |
| 1954 | 0 }; |
| 1955 | |
| 1956 | if (Rd == 15) |
| 1957 | { |
| 1958 | if (!ALUWritePC (context, result)) |
| 1959 | return false; |
| 1960 | } |
| 1961 | else |
| 1962 | { |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 1963 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1964 | return false; |
| 1965 | } |
| 1966 | } |
| 1967 | return true; |
| 1968 | } |
| 1969 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 1970 | // CMP (immediate) |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 1971 | bool |
| 1972 | EmulateInstructionARM::EmulateCmpRnImm (ARMEncoding encoding) |
| 1973 | { |
| 1974 | #if 0 |
| 1975 | // ARM pseudo code... |
| 1976 | if ConditionPassed() then |
| 1977 | EncodingSpecificOperations(); |
| 1978 | (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1'); |
| 1979 | APSR.N = result<31>; |
| 1980 | APSR.Z = IsZeroBit(result); |
| 1981 | APSR.C = carry; |
| 1982 | APSR.V = overflow; |
| 1983 | #endif |
| 1984 | |
| 1985 | bool success = false; |
| 1986 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1987 | if (!success) |
| 1988 | return false; |
| 1989 | |
| 1990 | uint32_t Rn; // the first operand |
| 1991 | uint32_t imm32; // the immediate value to be compared with |
| 1992 | switch (encoding) { |
| 1993 | case eEncodingT1: |
| 1994 | Rn = Bits32(opcode, 10, 8); |
| 1995 | imm32 = Bits32(opcode, 7, 0); |
| 1996 | break; |
| 1997 | default: |
| 1998 | return false; |
| 1999 | } |
| 2000 | // Read the register value from the operand register Rn. |
| 2001 | uint32_t reg_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 2002 | if (!success) |
| 2003 | return false; |
| 2004 | |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2005 | AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); |
| 2006 | m_new_inst_cpsr = m_inst_cpsr; |
| 2007 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(res.result, CPSR_N)); |
| 2008 | SetBit32(m_new_inst_cpsr, CPSR_Z, res.result == 0 ? 1 : 0); |
| 2009 | SetBit32(m_new_inst_cpsr, CPSR_C, res.carry_out); |
| 2010 | SetBit32(m_new_inst_cpsr, CPSR_V, res.overflow); |
| 2011 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 2012 | { |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 2013 | EmulateInstruction::Context context = { EmulateInstruction::eContextImmediate, 0, 0, 0}; |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2014 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 2015 | return false; |
| 2016 | } |
| 2017 | return true; |
| 2018 | } |
| 2019 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2020 | // CMP (register) |
| 2021 | bool |
| 2022 | EmulateInstructionARM::EmulateCmpRnRm (ARMEncoding encoding) |
| 2023 | { |
| 2024 | #if 0 |
| 2025 | // ARM pseudo code... |
| 2026 | if ConditionPassed() then |
| 2027 | EncodingSpecificOperations(); |
| 2028 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 2029 | (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1'); |
| 2030 | APSR.N = result<31>; |
| 2031 | APSR.Z = IsZeroBit(result); |
| 2032 | APSR.C = carry; |
| 2033 | APSR.V = overflow; |
| 2034 | #endif |
| 2035 | |
| 2036 | bool success = false; |
| 2037 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2038 | if (!success) |
| 2039 | return false; |
| 2040 | |
| 2041 | uint32_t Rn; // the first operand |
| 2042 | uint32_t Rm; // the second operand |
| 2043 | switch (encoding) { |
| 2044 | case eEncodingT1: |
| 2045 | Rn = Bits32(opcode, 2, 0); |
| 2046 | Rm = Bits32(opcode, 5, 3); |
| 2047 | break; |
| 2048 | case eEncodingT2: |
| 2049 | Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); |
| 2050 | Rm = Bits32(opcode, 6, 3); |
| 2051 | if (Rn < 8 && Rm < 8) |
| 2052 | return false; |
| 2053 | if (Rn == 15 || Rm == 15) |
| 2054 | return false; |
| 2055 | break; |
| 2056 | default: |
| 2057 | return false; |
| 2058 | } |
| 2059 | // Read the register value from register Rn. |
| 2060 | uint32_t reg_val1 = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 2061 | if (!success) |
| 2062 | return false; |
| 2063 | // Read the register value from register Rm. |
| 2064 | // The register value is not being shifted since we don't handle ARM for now. |
| 2065 | uint32_t reg_val2 = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 2066 | if (!success) |
| 2067 | return false; |
| 2068 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2069 | AddWithCarryResult res = AddWithCarry(reg_val1, reg_val2, 1); |
| 2070 | m_new_inst_cpsr = m_inst_cpsr; |
| 2071 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(res.result, CPSR_N)); |
| 2072 | SetBit32(m_new_inst_cpsr, CPSR_Z, res.result == 0 ? 1 : 0); |
| 2073 | SetBit32(m_new_inst_cpsr, CPSR_C, res.carry_out); |
| 2074 | SetBit32(m_new_inst_cpsr, CPSR_V, res.overflow); |
| 2075 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 2076 | { |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 2077 | EmulateInstruction::Context context = { EmulateInstruction::eContextImmediate, 0, 0, 0}; |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2078 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 2079 | return false; |
| 2080 | } |
| 2081 | return true; |
| 2082 | } |
| 2083 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2084 | // LDM loads multiple registers from consecutive memory locations, using an |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2085 | // address from a base register. Optionally the address just above the highest of those locations |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2086 | // can be written back to the base register. |
| 2087 | bool |
| 2088 | EmulateInstructionARM::EmulateLDM (ARMEncoding encoding) |
| 2089 | { |
| 2090 | #if 0 |
| 2091 | // ARM pseudo code... |
| 2092 | if ConditionPassed() |
| 2093 | EncodingSpecificOperations(); NullCheckIfThumbEE (n); |
| 2094 | address = R[n]; |
| 2095 | |
| 2096 | for i = 0 to 14 |
| 2097 | if registers<i> == '1' then |
| 2098 | R[i] = MemA[address, 4]; address = address + 4; |
| 2099 | if registers<15> == '1' then |
| 2100 | LoadWritePC (MemA[address, 4]); |
| 2101 | |
| 2102 | if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers); |
| 2103 | if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2104 | |
| 2105 | #endif |
| 2106 | |
| 2107 | bool success = false; |
| 2108 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2109 | if (!success) |
| 2110 | return false; |
| 2111 | |
| 2112 | if (ConditionPassed()) |
| 2113 | { |
| 2114 | uint32_t n; |
| 2115 | uint32_t registers = 0; |
| 2116 | bool wback; |
| 2117 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2118 | switch (encoding) |
| 2119 | { |
| 2120 | case eEncodingT1: |
| 2121 | n = Bits32 (opcode, 10, 8); |
| 2122 | registers = Bits32 (opcode, 7, 0); |
| 2123 | wback = BitIsClear (registers, n); |
| 2124 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 2125 | if (BitCount(registers) < 1) |
| 2126 | return false; |
| 2127 | break; |
| 2128 | case eEncodingT2: |
| 2129 | n = Bits32 (opcode, 19, 16); |
| 2130 | registers = Bits32 (opcode, 15, 0); |
| 2131 | wback = BitIsSet (opcode, 21); |
| 2132 | if ((n == 15) |
| 2133 | || (BitCount (registers) < 2) |
| 2134 | || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) |
| 2135 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 2136 | if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2137 | return false; |
| 2138 | if (wback |
| 2139 | && BitIsSet (registers, n)) |
| 2140 | return false; |
| 2141 | break; |
| 2142 | case eEncodingA1: |
| 2143 | n = Bits32 (opcode, 19, 16); |
| 2144 | registers = Bits32 (opcode, 15, 0); |
| 2145 | wback = BitIsSet (opcode, 21); |
| 2146 | if ((n == 15) |
| 2147 | || (BitCount (registers) < 1)) |
| 2148 | return false; |
| 2149 | break; |
| 2150 | default: |
| 2151 | return false; |
| 2152 | } |
| 2153 | |
| 2154 | int32_t offset = 0; |
| 2155 | const addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2156 | if (!success) |
| 2157 | return false; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2158 | |
| 2159 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 2160 | eRegisterKindDWARF, |
| 2161 | dwarf_r0 + n, |
| 2162 | offset }; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2163 | |
| 2164 | for (int i = 0; i < 14; ++i) |
| 2165 | { |
| 2166 | if (BitIsSet (registers, i)) |
| 2167 | { |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2168 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2169 | context.arg2 = offset; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2170 | if (wback && (n == 13)) // Pop Instruction |
| 2171 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 2172 | |
| 2173 | // R[i] = MemA [address, 4]; address = address + 4; |
| 2174 | uint32_t data = ReadMemoryUnsigned (context, base_address + offset, addr_byte_size, 0, &success); |
| 2175 | if (!success) |
| 2176 | return false; |
| 2177 | |
| 2178 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2179 | return false; |
| 2180 | |
| 2181 | offset += addr_byte_size; |
| 2182 | } |
| 2183 | } |
| 2184 | |
| 2185 | if (BitIsSet (registers, 15)) |
| 2186 | { |
| 2187 | //LoadWritePC (MemA [address, 4]); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2188 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2189 | context.arg2 = offset; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2190 | uint32_t data = ReadMemoryUnsigned (context, base_address + offset, addr_byte_size, 0, &success); |
| 2191 | if (!success) |
| 2192 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 2193 | // In ARMv5T and above, this is an interworking branch. |
| 2194 | if (!LoadWritePC(context, data)) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2195 | return false; |
| 2196 | } |
| 2197 | |
| 2198 | if (wback && BitIsClear (registers, n)) |
| 2199 | { |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2200 | // R[n] = R[n] + 4 * BitCount (registers) |
| 2201 | int32_t offset = addr_byte_size * BitCount (registers); |
| 2202 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2203 | context.arg2 = offset; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2204 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2205 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, base_address + offset)) |
| 2206 | return false; |
| 2207 | } |
| 2208 | if (wback && BitIsSet (registers, n)) |
| 2209 | // R[n] bits(32) UNKNOWN; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2210 | return WriteBits32Unknown (n); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2211 | } |
| 2212 | return true; |
| 2213 | } |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2214 | |
| 2215 | // LDMDA loads multiple registers from consecutive memory locations using an address from a base registers. |
| 2216 | // The consecutive memorty locations end at this address and the address just below the lowest of those locations |
| 2217 | // can optionally be written back tot he base registers. |
| 2218 | bool |
| 2219 | EmulateInstructionARM::EmulateLDMDA (ARMEncoding encoding) |
| 2220 | { |
| 2221 | #if 0 |
| 2222 | // ARM pseudo code... |
| 2223 | if ConditionPassed() then |
| 2224 | EncodingSpecificOperations(); |
| 2225 | address = R[n] - 4*BitCount(registers) + 4; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2226 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2227 | for i = 0 to 14 |
| 2228 | if registers<i> == ’1’ then |
| 2229 | R[i] = MemA[address,4]; address = address + 4; |
| 2230 | |
| 2231 | if registers<15> == ’1’ then |
| 2232 | LoadWritePC(MemA[address,4]); |
| 2233 | |
| 2234 | if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2235 | if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; |
| 2236 | #endif |
| 2237 | |
| 2238 | bool success = false; |
| 2239 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2240 | if (!success) |
| 2241 | return false; |
| 2242 | |
| 2243 | if (ConditionPassed()) |
| 2244 | { |
| 2245 | uint32_t n; |
| 2246 | uint32_t registers = 0; |
| 2247 | bool wback; |
| 2248 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2249 | |
| 2250 | // EncodingSpecificOperations(); |
| 2251 | switch (encoding) |
| 2252 | { |
| 2253 | case eEncodingA1: |
| 2254 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2255 | n = Bits32 (opcode, 19, 16); |
| 2256 | registers = Bits32 (opcode, 15, 0); |
| 2257 | wback = BitIsSet (opcode, 21); |
| 2258 | |
| 2259 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2260 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2261 | return false; |
| 2262 | |
| 2263 | break; |
| 2264 | |
| 2265 | default: |
| 2266 | return false; |
| 2267 | } |
| 2268 | // address = R[n] - 4*BitCount(registers) + 4; |
| 2269 | |
| 2270 | int32_t offset = 0; |
| 2271 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2272 | |
| 2273 | if (!success) |
| 2274 | return false; |
| 2275 | |
| 2276 | address = address - (addr_byte_size * BitCount (registers)) + addr_byte_size; |
| 2277 | |
| 2278 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 2279 | eRegisterKindDWARF, |
| 2280 | dwarf_r0 + n, |
| 2281 | offset }; |
| 2282 | |
| 2283 | // for i = 0 to 14 |
| 2284 | for (int i = 0; i < 14; ++i) |
| 2285 | { |
| 2286 | // if registers<i> == ’1’ then |
| 2287 | if (BitIsSet (registers, i)) |
| 2288 | { |
| 2289 | // R[i] = MemA[address,4]; address = address + 4; |
| 2290 | context.arg2 = offset; |
| 2291 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2292 | if (!success) |
| 2293 | return false; |
| 2294 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2295 | return false; |
| 2296 | offset += addr_byte_size; |
| 2297 | } |
| 2298 | } |
| 2299 | |
| 2300 | // if registers<15> == ’1’ then |
| 2301 | // LoadWritePC(MemA[address,4]); |
| 2302 | if (BitIsSet (registers, 15)) |
| 2303 | { |
| 2304 | context.arg2 = offset; |
| 2305 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2306 | if (!success) |
| 2307 | return false; |
Johnny Chen | 44c10f0 | 2011-02-11 19:37:03 +0000 | [diff] [blame] | 2308 | // In ARMv5T and above, this is an interworking branch. |
| 2309 | if (!LoadWritePC(context, data)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2310 | return false; |
| 2311 | } |
| 2312 | |
| 2313 | // if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2314 | if (wback && BitIsClear (registers, n)) |
| 2315 | { |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2316 | addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2317 | if (!success) |
| 2318 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2319 | |
| 2320 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 2321 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 2322 | context.arg2 = offset; |
| 2323 | addr = addr + offset; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2324 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 2325 | return false; |
| 2326 | } |
| 2327 | |
| 2328 | // if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; |
| 2329 | if (wback && BitIsSet (registers, n)) |
| 2330 | return WriteBits32Unknown (n); |
| 2331 | } |
| 2332 | return true; |
| 2333 | } |
| 2334 | |
| 2335 | // LDMDB loads multiple registers from consecutive memory locations using an address from a base register. The |
| 2336 | // consecutive memory lcoations end just below this address, and the address of the lowest of those locations can |
| 2337 | // be optionally written back to the base register. |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2338 | bool |
| 2339 | EmulateInstructionARM::EmulateLDMDB (ARMEncoding encoding) |
| 2340 | { |
| 2341 | #if 0 |
| 2342 | // ARM pseudo code... |
| 2343 | if ConditionPassed() then |
| 2344 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 2345 | address = R[n] - 4*BitCount(registers); |
| 2346 | |
| 2347 | for i = 0 to 14 |
| 2348 | if registers<i> == ’1’ then |
| 2349 | R[i] = MemA[address,4]; address = address + 4; |
| 2350 | if registers<15> == ’1’ then |
| 2351 | LoadWritePC(MemA[address,4]); |
| 2352 | |
| 2353 | if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2354 | if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2355 | #endif |
| 2356 | |
| 2357 | bool success = false; |
| 2358 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2359 | if (!success) |
| 2360 | return false; |
| 2361 | |
| 2362 | if (ConditionPassed()) |
| 2363 | { |
| 2364 | uint32_t n; |
| 2365 | uint32_t registers = 0; |
| 2366 | bool wback; |
| 2367 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2368 | switch (encoding) |
| 2369 | { |
| 2370 | case eEncodingT1: |
| 2371 | // n = UInt(Rn); registers = P:M:’0’:register_list; wback = (W == ’1’); |
| 2372 | n = Bits32 (opcode, 19, 16); |
| 2373 | registers = Bits32 (opcode, 15, 0); |
| 2374 | wback = BitIsSet (opcode, 21); |
| 2375 | |
| 2376 | // if n == 15 || BitCount(registers) < 2 || (P == ’1’ && M == ’1’) then UNPREDICTABLE; |
| 2377 | if ((n == 15) |
| 2378 | || (BitCount (registers) < 2) |
| 2379 | || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) |
| 2380 | return false; |
| 2381 | |
| 2382 | // if registers<15> == ’1’ && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 2383 | if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2384 | return false; |
| 2385 | |
| 2386 | // if wback && registers<n> == ’1’ then UNPREDICTABLE; |
| 2387 | if (wback && BitIsSet (registers, n)) |
| 2388 | return false; |
| 2389 | |
| 2390 | break; |
| 2391 | |
| 2392 | case eEncodingA1: |
| 2393 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2394 | n = Bits32 (opcode, 19, 16); |
| 2395 | registers = Bits32 (opcode, 15, 0); |
| 2396 | wback = BitIsSet (opcode, 21); |
| 2397 | |
| 2398 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2399 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2400 | return false; |
| 2401 | |
| 2402 | break; |
| 2403 | |
| 2404 | default: |
| 2405 | return false; |
| 2406 | } |
| 2407 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2408 | // address = R[n] - 4*BitCount(registers); |
| 2409 | |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2410 | int32_t offset = 0; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2411 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2412 | |
| 2413 | if (!success) |
| 2414 | return false; |
| 2415 | |
| 2416 | address = address - (addr_byte_size * BitCount (registers)); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2417 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 2418 | eRegisterKindDWARF, |
| 2419 | dwarf_r0 + n, |
| 2420 | offset }; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2421 | |
| 2422 | for (int i = 0; i < 14; ++i) |
| 2423 | { |
| 2424 | if (BitIsSet (registers, i)) |
| 2425 | { |
| 2426 | // R[i] = MemA[address,4]; address = address + 4; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2427 | context.arg2 = offset; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2428 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2429 | if (!success) |
| 2430 | return false; |
| 2431 | |
| 2432 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2433 | return false; |
| 2434 | |
| 2435 | offset += addr_byte_size; |
| 2436 | } |
| 2437 | } |
| 2438 | |
| 2439 | // if registers<15> == ’1’ then |
| 2440 | // LoadWritePC(MemA[address,4]); |
| 2441 | if (BitIsSet (registers, 15)) |
| 2442 | { |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2443 | context.arg2 = offset; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2444 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2445 | if (!success) |
| 2446 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 2447 | // In ARMv5T and above, this is an interworking branch. |
| 2448 | if (!LoadWritePC(context, data)) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2449 | return false; |
| 2450 | } |
| 2451 | |
| 2452 | // if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2453 | if (wback && BitIsClear (registers, n)) |
| 2454 | { |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2455 | addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2456 | if (!success) |
| 2457 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2458 | |
| 2459 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 2460 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 2461 | context.arg2 = offset; |
| 2462 | addr = addr + offset; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2463 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 2464 | return false; |
| 2465 | } |
| 2466 | |
| 2467 | // if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2468 | if (wback && BitIsSet (registers, n)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2469 | return WriteBits32Unknown (n); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2470 | } |
| 2471 | return true; |
| 2472 | } |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2473 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2474 | // LDMIB loads multiple registers from consecutive memory locations using an address from a base register. The |
| 2475 | // consecutive memory locations start just above this address, and thea ddress of the last of those locations can |
| 2476 | // optinoally be written back to the base register. |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2477 | bool |
| 2478 | EmulateInstructionARM::EmulateLDMIB (ARMEncoding encoding) |
| 2479 | { |
| 2480 | #if 0 |
| 2481 | if ConditionPassed() then |
| 2482 | EncodingSpecificOperations(); |
| 2483 | address = R[n] + 4; |
| 2484 | |
| 2485 | for i = 0 to 14 |
| 2486 | if registers<i> == ’1’ then |
| 2487 | R[i] = MemA[address,4]; address = address + 4; |
| 2488 | if registers<15> == ’1’ then |
| 2489 | LoadWritePC(MemA[address,4]); |
| 2490 | |
| 2491 | if wback && registers<n> == ’0’ then R[n] = R[n] + 4*BitCount(registers); |
| 2492 | if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; |
| 2493 | #endif |
| 2494 | |
| 2495 | bool success = false; |
| 2496 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2497 | if (!success) |
| 2498 | return false; |
| 2499 | |
| 2500 | if (ConditionPassed()) |
| 2501 | { |
| 2502 | uint32_t n; |
| 2503 | uint32_t registers = 0; |
| 2504 | bool wback; |
| 2505 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2506 | switch (encoding) |
| 2507 | { |
| 2508 | case eEncodingA1: |
| 2509 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2510 | n = Bits32 (opcode, 19, 16); |
| 2511 | registers = Bits32 (opcode, 15, 0); |
| 2512 | wback = BitIsSet (opcode, 21); |
| 2513 | |
| 2514 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2515 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2516 | return false; |
| 2517 | |
| 2518 | break; |
| 2519 | default: |
| 2520 | return false; |
| 2521 | } |
| 2522 | // address = R[n] + 4; |
| 2523 | |
| 2524 | int32_t offset = 0; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2525 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2526 | |
| 2527 | if (!success) |
| 2528 | return false; |
| 2529 | |
| 2530 | address = address + addr_byte_size; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2531 | |
| 2532 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 2533 | eRegisterKindDWARF, |
| 2534 | dwarf_r0 + n, |
| 2535 | offset }; |
| 2536 | |
| 2537 | for (int i = 0; i < 14; ++i) |
| 2538 | { |
| 2539 | if (BitIsSet (registers, i)) |
| 2540 | { |
| 2541 | // R[i] = MemA[address,4]; address = address + 4; |
| 2542 | |
| 2543 | context.arg2 = offset; |
| 2544 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2545 | if (!success) |
| 2546 | return false; |
| 2547 | |
| 2548 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2549 | return false; |
| 2550 | |
| 2551 | offset += addr_byte_size; |
| 2552 | } |
| 2553 | } |
| 2554 | |
| 2555 | // if registers<15> == ’1’ then |
| 2556 | // LoadWritePC(MemA[address,4]); |
| 2557 | if (BitIsSet (registers, 15)) |
| 2558 | { |
| 2559 | context.arg2 = offset; |
| 2560 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2561 | if (!success) |
| 2562 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 2563 | // In ARMv5T and above, this is an interworking branch. |
| 2564 | if (!LoadWritePC(context, data)) |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2565 | return false; |
| 2566 | } |
| 2567 | |
| 2568 | // if wback && registers<n> == ’0’ then R[n] = R[n] + 4*BitCount(registers); |
| 2569 | if (wback && BitIsClear (registers, n)) |
| 2570 | { |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2571 | addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2572 | if (!success) |
| 2573 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2574 | |
| 2575 | offset = addr_byte_size * BitCount (registers); |
| 2576 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 2577 | context.arg2 = offset; |
| 2578 | addr = addr + offset; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2579 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 2580 | return false; |
| 2581 | } |
| 2582 | |
| 2583 | // if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2584 | if (wback && BitIsSet (registers, n)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2585 | return WriteBits32Unknown (n); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2586 | } |
| 2587 | return true; |
| 2588 | } |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2589 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 2590 | // Load Register (immediate) calculates an address from a base register value and |
| 2591 | // an immediate offset, loads a word from memory, and writes to a register. |
| 2592 | // LDR (immediate, Thumb) |
| 2593 | bool |
| 2594 | EmulateInstructionARM::EmulateLDRRtRnImm (ARMEncoding encoding) |
| 2595 | { |
| 2596 | #if 0 |
| 2597 | // ARM pseudo code... |
| 2598 | if (ConditionPassed()) |
| 2599 | { |
| 2600 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 2601 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 2602 | address = if index then offset_addr else R[n]; |
| 2603 | data = MemU[address,4]; |
| 2604 | if wback then R[n] = offset_addr; |
| 2605 | if t == 15 then |
| 2606 | if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; |
| 2607 | elsif UnalignedSupport() || address<1:0> = '00' then |
| 2608 | R[t] = data; |
| 2609 | else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7 |
| 2610 | } |
| 2611 | #endif |
| 2612 | |
| 2613 | bool success = false; |
| 2614 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2615 | if (!success) |
| 2616 | return false; |
| 2617 | |
| 2618 | if (ConditionPassed()) |
| 2619 | { |
| 2620 | uint32_t Rt; // the destination register |
| 2621 | uint32_t Rn; // the base register |
| 2622 | uint32_t imm32; // the immediate offset used to form the address |
| 2623 | addr_t offset_addr; // the offset address |
| 2624 | addr_t address; // the calculated address |
| 2625 | uint32_t data; // the literal data value from memory load |
| 2626 | bool add, index, wback; |
| 2627 | switch (encoding) { |
| 2628 | case eEncodingT1: |
| 2629 | Rt = Bits32(opcode, 5, 3); |
| 2630 | Rn = Bits32(opcode, 2, 0); |
| 2631 | imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32); |
| 2632 | // index = TRUE; add = TRUE; wback = FALSE |
| 2633 | add = true; |
| 2634 | index = true; |
| 2635 | wback = false; |
| 2636 | break; |
| 2637 | default: |
| 2638 | return false; |
| 2639 | } |
| 2640 | uint32_t base = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 2641 | if (!success) |
| 2642 | return false; |
| 2643 | if (add) |
| 2644 | offset_addr = base + imm32; |
| 2645 | else |
| 2646 | offset_addr = base - imm32; |
| 2647 | |
| 2648 | address = (index ? offset_addr : base); |
| 2649 | |
| 2650 | if (wback) |
| 2651 | { |
| 2652 | EmulateInstruction::Context ctx = { EmulateInstruction::eContextRegisterPlusOffset, |
| 2653 | eRegisterKindDWARF, |
| 2654 | dwarf_r0 + Rn, |
| 2655 | (int32_t) (offset_addr - base)}; |
| 2656 | if (!WriteRegisterUnsigned (ctx, eRegisterKindDWARF, dwarf_r0 + Rn, offset_addr)) |
| 2657 | return false; |
| 2658 | } |
| 2659 | |
| 2660 | // Prepare to write to the Rt register. |
| 2661 | EmulateInstruction::Context context = {EmulateInstruction::eContextImmediate, |
| 2662 | 0, |
| 2663 | 0, |
| 2664 | 0}; |
| 2665 | |
| 2666 | // Read memory from the address. |
| 2667 | data = ReadMemoryUnsigned(context, address, 4, 0, &success); |
| 2668 | if (!success) |
| 2669 | return false; |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 2670 | |
| 2671 | if (Rt == 15) |
| 2672 | { |
| 2673 | if (Bits32(address, 1, 0) == 0) |
| 2674 | { |
| 2675 | if (!LoadWritePC(context, data)) |
| 2676 | return false; |
| 2677 | } |
| 2678 | else |
| 2679 | return false; |
| 2680 | } |
| 2681 | else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) |
| 2682 | { |
| 2683 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
| 2684 | return false; |
| 2685 | } |
| 2686 | else |
| 2687 | return false; |
| 2688 | } |
| 2689 | return true; |
| 2690 | } |
| 2691 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2692 | // STM stores multiple registers to consecutive memory locations using an address from a base register. The |
| 2693 | // consecutive memory locations start at this address, and teh address just above the last of those locations can |
| 2694 | // optionally be written back to the base register. |
| 2695 | bool |
| 2696 | EmulateInstructionARM::EmulateSTM (ARMEncoding encoding) |
| 2697 | { |
| 2698 | #if 0 |
| 2699 | if ConditionPassed() then |
| 2700 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 2701 | address = R[n]; |
| 2702 | |
| 2703 | for i = 0 to 14 |
| 2704 | if registers<i> == ’1’ then |
| 2705 | if i == n && wback && i != LowestSetBit(registers) then |
| 2706 | MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1 |
| 2707 | else |
| 2708 | MemA[address,4] = R[i]; |
| 2709 | address = address + 4; |
| 2710 | |
| 2711 | if registers<15> == ’1’ then // Only possible for encoding A1 |
| 2712 | MemA[address,4] = PCStoreValue(); |
| 2713 | if wback then R[n] = R[n] + 4*BitCount(registers); |
| 2714 | #endif |
| 2715 | |
| 2716 | bool success = false; |
| 2717 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2718 | if (!success) |
| 2719 | return false; |
| 2720 | |
| 2721 | if (ConditionPassed ()) |
| 2722 | { |
| 2723 | uint32_t n; |
| 2724 | uint32_t registers = 0; |
| 2725 | bool wback; |
| 2726 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2727 | |
| 2728 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 2729 | switch (encoding) |
| 2730 | { |
| 2731 | case eEncodingT1: |
| 2732 | // n = UInt(Rn); registers = ’00000000’:register_list; wback = TRUE; |
| 2733 | n = Bits32 (opcode, 10, 8); |
| 2734 | registers = Bits32 (opcode, 7, 0); |
| 2735 | wback = true; |
| 2736 | |
| 2737 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 2738 | if (BitCount (registers) < 1) |
| 2739 | return false; |
| 2740 | |
| 2741 | break; |
| 2742 | |
| 2743 | case eEncodingT2: |
| 2744 | // n = UInt(Rn); registers = ’0’:M:’0’:register_list; wback = (W == ’1’); |
| 2745 | n = Bits32 (opcode, 19, 16); |
| 2746 | registers = Bits32 (opcode, 15, 0); |
| 2747 | wback = BitIsSet (opcode, 21); |
| 2748 | |
| 2749 | // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE; |
| 2750 | if ((n == 15) || (BitCount (registers) < 2)) |
| 2751 | return false; |
| 2752 | |
| 2753 | // if wback && registers<n> == ’1’ then UNPREDICTABLE; |
| 2754 | if (wback && BitIsSet (registers, n)) |
| 2755 | return false; |
| 2756 | |
| 2757 | break; |
| 2758 | |
| 2759 | case eEncodingA1: |
| 2760 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2761 | n = Bits32 (opcode, 19, 16); |
| 2762 | registers = Bits32 (opcode, 15, 0); |
| 2763 | wback = BitIsSet (opcode, 21); |
| 2764 | |
| 2765 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2766 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2767 | return false; |
| 2768 | |
| 2769 | break; |
| 2770 | |
| 2771 | default: |
| 2772 | return false; |
| 2773 | } |
| 2774 | |
| 2775 | // address = R[n]; |
| 2776 | int32_t offset = 0; |
| 2777 | const addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2778 | if (!success) |
| 2779 | return false; |
| 2780 | |
| 2781 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterStore, |
| 2782 | eRegisterKindDWARF, |
| 2783 | dwarf_r0 + n, |
| 2784 | offset }; |
| 2785 | |
| 2786 | // for i = 0 to 14 |
| 2787 | for (int i = 0; i < 14; ++i) |
| 2788 | { |
| 2789 | int lowest_set_bit = 14; |
| 2790 | // if registers<i> == ’1’ then |
| 2791 | if (BitIsSet (registers, i)) |
| 2792 | { |
| 2793 | if (i < lowest_set_bit) |
| 2794 | lowest_set_bit = i; |
| 2795 | // if i == n && wback && i != LowestSetBit(registers) then |
| 2796 | if ((i == n) && wback && (i != lowest_set_bit)) |
| 2797 | // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1 |
| 2798 | WriteBits32UnknownToMemory (address + offset); |
| 2799 | else |
| 2800 | { |
| 2801 | // MemA[address,4] = R[i]; |
| 2802 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 2803 | if (!success) |
| 2804 | return false; |
| 2805 | |
| 2806 | context.arg1 = dwarf_r0 + i; |
| 2807 | context.arg2 = address + offset; |
| 2808 | if (!WriteMemoryUnsigned (context, address + offset, data, addr_byte_size)) |
| 2809 | return false; |
| 2810 | } |
| 2811 | |
| 2812 | // address = address + 4; |
| 2813 | offset += addr_byte_size; |
| 2814 | } |
| 2815 | } |
| 2816 | |
| 2817 | // if registers<15> == ’1’ then // Only possible for encoding A1 |
| 2818 | // MemA[address,4] = PCStoreValue(); |
| 2819 | if (BitIsSet (registers, 15)) |
| 2820 | { |
| 2821 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
| 2822 | if (!success) |
| 2823 | return false; |
| 2824 | |
| 2825 | context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number |
| 2826 | context.arg2 = address + offset - sp; // arg2 in the context is the stack pointer offset |
| 2827 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 2828 | if (!success) |
| 2829 | return false; |
| 2830 | |
| 2831 | if (!WriteMemoryUnsigned (context, address + offset, pc + 8, addr_byte_size)) |
| 2832 | return false; |
| 2833 | } |
| 2834 | |
| 2835 | // if wback then R[n] = R[n] + 4*BitCount(registers); |
| 2836 | if (wback) |
| 2837 | { |
| 2838 | offset = addr_byte_size * BitCount (registers); |
| 2839 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 2840 | context.arg1 = dwarf_r0 + n; |
| 2841 | context.arg2 = offset; |
| 2842 | addr_t data = address + offset; |
| 2843 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 2844 | return false; |
| 2845 | } |
| 2846 | } |
| 2847 | return true; |
| 2848 | } |
| 2849 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2850 | EmulateInstructionARM::ARMOpcode* |
| 2851 | EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 2852 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2853 | static ARMOpcode |
| 2854 | g_arm_opcodes[] = |
| 2855 | { |
| 2856 | //---------------------------------------------------------------------- |
| 2857 | // Prologue instructions |
| 2858 | //---------------------------------------------------------------------- |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 2859 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2860 | // push register(s) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2861 | { 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePush, "push <registers>" }, |
| 2862 | { 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePush, "push <register>" }, |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 2863 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2864 | // set r7 to point to a stack offset |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2865 | { 0x0ffff000, 0x028d7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add r7, sp, #<const>" }, |
| 2866 | { 0x0ffff000, 0x024c7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubR7IPImmediate, "sub r7, ip, #<const>"}, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 2867 | // copy the stack pointer to ip |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2868 | { 0x0fffffff, 0x01a0c00d, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMovRdSP, "mov ip, sp" }, |
| 2869 | { 0x0ffff000, 0x028dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add ip, sp, #<const>" }, |
| 2870 | { 0x0ffff000, 0x024dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubIPSPImmediate, "sub ip, sp, #<const>"}, |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 2871 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2872 | // adjust the stack pointer |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2873 | { 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "sub sp, sp, #<const>"}, |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 2874 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2875 | // push one register |
| 2876 | // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH; |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2877 | { 0x0fff0000, 0x052d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!" }, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 2878 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2879 | // vector push consecutive extension register(s) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 2880 | { 0x0fbf0f00, 0x0d2d0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 2881 | { 0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 2882 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2883 | //---------------------------------------------------------------------- |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 2884 | // Epilogue instructions |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2885 | //---------------------------------------------------------------------- |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 2886 | |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2887 | { 0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePop, "pop <registers>"}, |
| 2888 | { 0x0fff0fff, 0x049d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePop, "pop <register>"}, |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 2889 | { 0x0fbf0f00, 0x0cbd0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 2890 | { 0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
| 2891 | |
| 2892 | //---------------------------------------------------------------------- |
| 2893 | // Supervisor Call (previously Software Interrupt) |
| 2894 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 2895 | { 0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSVC, "svc #imm24"}, |
| 2896 | |
| 2897 | //---------------------------------------------------------------------- |
| 2898 | // Branch instructions |
| 2899 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2900 | { 0x0f000000, 0x0a000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSVC, "b #imm24"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 2901 | // To resolve ambiguity, "blx <label>" should come before "bl <label>". |
| 2902 | { 0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
| 2903 | { 0x0f000000, 0x0b000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"}, |
| 2904 | { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 2905 | // for example, "bx lr" |
| 2906 | { 0x0ffffff0, 0x012fff10, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 2907 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2908 | //---------------------------------------------------------------------- |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 2909 | // Data-processing instructions |
| 2910 | //---------------------------------------------------------------------- |
| 2911 | // move bitwise not |
| 2912 | { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMvnRdImm, "mvn{s} <Rd>, #<const>"}, |
| 2913 | |
| 2914 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2915 | // Load instructions |
| 2916 | //---------------------------------------------------------------------- |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2917 | { 0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" }, |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2918 | { 0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDA, "ldmda<c> <Rn>{!} <registers>" }, |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2919 | { 0x0fd00000, 0x09100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" }, |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2920 | { 0x0fd00000, 0x09900000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>" }, |
| 2921 | |
| 2922 | //---------------------------------------------------------------------- |
| 2923 | // Store instructions |
| 2924 | //---------------------------------------------------------------------- |
| 2925 | { 0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" } |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2926 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2927 | }; |
| 2928 | static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode); |
| 2929 | |
| 2930 | for (size_t i=0; i<k_num_arm_opcodes; ++i) |
| 2931 | { |
| 2932 | if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value) |
| 2933 | return &g_arm_opcodes[i]; |
| 2934 | } |
| 2935 | return NULL; |
| 2936 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 2937 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2938 | |
| 2939 | EmulateInstructionARM::ARMOpcode* |
| 2940 | EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode) |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 2941 | { |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 2942 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2943 | static ARMOpcode |
| 2944 | g_thumb_opcodes[] = |
| 2945 | { |
| 2946 | //---------------------------------------------------------------------- |
| 2947 | // Prologue instructions |
| 2948 | //---------------------------------------------------------------------- |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 2949 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2950 | // push register(s) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2951 | { 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePush, "push <registers>" }, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 2952 | { 0xffff0000, 0xe92d0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePush, "push.w <registers>" }, |
| 2953 | { 0xffff0fff, 0xf84d0d04, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePush, "push.w <register>" }, |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 2954 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2955 | // set r7 to point to a stack offset |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2956 | { 0xffffff00, 0x0000af00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add r7, sp, #imm" }, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 2957 | // copy the stack pointer to r7 |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2958 | { 0xffffffff, 0x0000466f, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdSP, "mov r7, sp" }, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 2959 | // move from high register to low register (comes after "mov r7, sp" to resolve ambiguity) |
| 2960 | { 0xffffffc0, 0x00004640, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovLowHigh, "mov r0-r7, r8-r15" }, |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 2961 | |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 2962 | // PC-relative load into register (see also EmulateAddSPRm) |
| 2963 | { 0xfffff800, 0x00004800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"}, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 2964 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2965 | // adjust the stack pointer |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2966 | { 0xffffff87, 0x00004485, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateAddSPRm, "add sp, <Rm>"}, |
| 2967 | { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSubSPImmdiate, "add sp, sp, #imm"}, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 2968 | { 0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "sub.w sp, sp, #<const>"}, |
| 2969 | { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "subw sp, sp, #imm12"}, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 2970 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2971 | // vector push consecutive extension register(s) |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 2972 | { 0xffbf0f00, 0xed2d0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 2973 | { 0xffbf0f00, 0xed2d0a00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 2974 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 2975 | //---------------------------------------------------------------------- |
| 2976 | // Epilogue instructions |
| 2977 | //---------------------------------------------------------------------- |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 2978 | |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 2979 | { 0xffffff80, 0x0000b000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateAddSPImmediate, "add sp, #imm"}, |
| 2980 | { 0xfffffe00, 0x0000bc00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePop, "pop <registers>"}, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 2981 | { 0xffff0000, 0xe8bd0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePop, "pop.w <registers>" }, |
| 2982 | { 0xffff0fff, 0xf85d0d04, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePop, "pop.w <register>" }, |
| 2983 | { 0xffbf0f00, 0xecbd0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
| 2984 | { 0xffbf0f00, 0xecbd0a00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 2985 | |
| 2986 | //---------------------------------------------------------------------- |
| 2987 | // Supervisor Call (previously Software Interrupt) |
| 2988 | //---------------------------------------------------------------------- |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 2989 | { 0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSVC, "svc #imm8"}, |
| 2990 | |
| 2991 | //---------------------------------------------------------------------- |
| 2992 | // If Then makes up to four following instructions conditional. |
| 2993 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 2994 | { 0xffffff00, 0x0000bf00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"}, |
| 2995 | |
| 2996 | //---------------------------------------------------------------------- |
| 2997 | // Branch instructions |
| 2998 | //---------------------------------------------------------------------- |
| 2999 | // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8". |
| 3000 | { 0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"}, |
| 3001 | { 0xffff8000, 0x0000e000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateB, "b #imm11 (outside or last in IT)"}, |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3002 | { 0xf800d000, 0xf0008000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"}, |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3003 | { 0xf800d000, 0xf0009000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateB, "b.w #imm8 (outside or last in IT)"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 3004 | // J1 == J2 == 1 |
| 3005 | { 0xf800f800, 0xf000f800, ARMV4T_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"}, |
| 3006 | // J1 == J2 == 1 |
| 3007 | { 0xf800e800, 0xf000e800, ARMV5_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
| 3008 | { 0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 3009 | // for example, "bx lr" |
| 3010 | { 0xffffff87, 0x00004700, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"}, |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 3011 | // compare and branch |
| 3012 | { 0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCB, "cb{n}z <Rn>, <label>"}, |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3013 | |
| 3014 | //---------------------------------------------------------------------- |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 3015 | // Data-processing instructions |
| 3016 | //---------------------------------------------------------------------- |
| 3017 | // Make sure "add sp, <Rm>" comes before this instruction, so there's no ambiguity decoding the two. |
| 3018 | { 0xffffff00, 0x00004400, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateAddRdnRm, "add <Rdn>, <Rm>"}, |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 3019 | // move from high register to high register |
| 3020 | { 0xffffff00, 0x00004600, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdRm, "mov<c> <Rd>, <Rm>"}, |
| 3021 | // move from low register to low register |
| 3022 | { 0xffffffc0, 0x00000000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateMovRdRm, "movs <Rd>, <Rm>"}, |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame^] | 3023 | // move immediate |
| 3024 | { 0xfffff800, 0x00002000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdImm, "movs|mov<c> <Rd>, #imm8"}, |
| 3025 | { 0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMovRdImm, "mov{s}<c>.w <Rd>, #<const>"}, |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 3026 | // move bitwise not |
| 3027 | { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateMvnRdImm, "mvn{s} <Rd>, #<const>"}, |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 3028 | // compare a register with immediate |
| 3029 | { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCmpRnImm, "cmp<c> <Rn>, #imm8"}, |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 3030 | // compare Rn with Rm (Rn and Rm both from r0-r7) |
| 3031 | { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCmpRnRm, "cmp<c> <Rn>, <Rm>"}, |
| 3032 | // compare Rn with Rm (Rn and Rm not both from r0-r7) |
| 3033 | { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateCmpRnRm, "cmp<c> <Rn>, <Rm>"}, |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 3034 | |
| 3035 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3036 | // Load instructions |
| 3037 | //---------------------------------------------------------------------- |
| 3038 | { 0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" }, |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3039 | { 0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c>.w <Rn>{!} <registers>" }, |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3040 | { 0xffd00000, 0xe9100000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" }, |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 3041 | { 0xfffff800, 0x00006800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"}, |
| 3042 | // Thumb2 PC-relative load into register |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3043 | { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"}, |
| 3044 | |
| 3045 | //---------------------------------------------------------------------- |
| 3046 | // Store instructions |
| 3047 | //---------------------------------------------------------------------- |
| 3048 | { 0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" }, |
| 3049 | { 0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c>.w <Rn>{!} <registers>" } |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3050 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3051 | }; |
| 3052 | |
| 3053 | const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode); |
| 3054 | for (size_t i=0; i<k_num_thumb_opcodes; ++i) |
| 3055 | { |
| 3056 | if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value) |
| 3057 | return &g_thumb_opcodes[i]; |
| 3058 | } |
| 3059 | return NULL; |
| 3060 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3061 | |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 3062 | bool |
| 3063 | EmulateInstructionARM::SetTargetTriple (const ConstString &triple) |
| 3064 | { |
| 3065 | m_arm_isa = 0; |
| 3066 | const char *triple_cstr = triple.GetCString(); |
| 3067 | if (triple_cstr) |
| 3068 | { |
| 3069 | const char *dash = ::strchr (triple_cstr, '-'); |
| 3070 | if (dash) |
| 3071 | { |
| 3072 | std::string arch (triple_cstr, dash); |
| 3073 | const char *arch_cstr = arch.c_str(); |
| 3074 | if (strcasecmp(arch_cstr, "armv4t") == 0) |
| 3075 | m_arm_isa = ARMv4T; |
| 3076 | else if (strcasecmp(arch_cstr, "armv4") == 0) |
| 3077 | m_arm_isa = ARMv4; |
| 3078 | else if (strcasecmp(arch_cstr, "armv5tej") == 0) |
| 3079 | m_arm_isa = ARMv5TEJ; |
| 3080 | else if (strcasecmp(arch_cstr, "armv5te") == 0) |
| 3081 | m_arm_isa = ARMv5TE; |
| 3082 | else if (strcasecmp(arch_cstr, "armv5t") == 0) |
| 3083 | m_arm_isa = ARMv5T; |
| 3084 | else if (strcasecmp(arch_cstr, "armv6k") == 0) |
| 3085 | m_arm_isa = ARMv6K; |
| 3086 | else if (strcasecmp(arch_cstr, "armv6") == 0) |
| 3087 | m_arm_isa = ARMv6; |
| 3088 | else if (strcasecmp(arch_cstr, "armv6t2") == 0) |
| 3089 | m_arm_isa = ARMv6T2; |
| 3090 | else if (strcasecmp(arch_cstr, "armv7") == 0) |
| 3091 | m_arm_isa = ARMv7; |
| 3092 | else if (strcasecmp(arch_cstr, "armv8") == 0) |
| 3093 | m_arm_isa = ARMv8; |
| 3094 | } |
| 3095 | } |
| 3096 | return m_arm_isa != 0; |
| 3097 | } |
| 3098 | |
| 3099 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3100 | bool |
| 3101 | EmulateInstructionARM::ReadInstruction () |
| 3102 | { |
| 3103 | bool success = false; |
| 3104 | m_inst_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, 0, &success); |
| 3105 | if (success) |
| 3106 | { |
| 3107 | addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success); |
| 3108 | if (success) |
| 3109 | { |
| 3110 | Context read_inst_context = {eContextReadOpcode, 0, 0}; |
| 3111 | if (m_inst_cpsr & MASK_CPSR_T) |
| 3112 | { |
| 3113 | m_inst_mode = eModeThumb; |
| 3114 | uint32_t thumb_opcode = ReadMemoryUnsigned(read_inst_context, pc, 2, 0, &success); |
| 3115 | |
| 3116 | if (success) |
| 3117 | { |
| 3118 | if ((m_inst.opcode.inst16 & 0xe000) != 0xe000 || ((m_inst.opcode.inst16 & 0x1800u) == 0)) |
| 3119 | { |
| 3120 | m_inst.opcode_type = eOpcode16; |
| 3121 | m_inst.opcode.inst16 = thumb_opcode; |
| 3122 | } |
| 3123 | else |
| 3124 | { |
| 3125 | m_inst.opcode_type = eOpcode32; |
| 3126 | m_inst.opcode.inst32 = (thumb_opcode << 16) | ReadMemoryUnsigned(read_inst_context, pc + 2, 2, 0, &success); |
| 3127 | } |
| 3128 | } |
| 3129 | } |
| 3130 | else |
| 3131 | { |
| 3132 | m_inst_mode = eModeARM; |
| 3133 | m_inst.opcode_type = eOpcode32; |
| 3134 | m_inst.opcode.inst32 = ReadMemoryUnsigned(read_inst_context, pc, 4, 0, &success); |
| 3135 | } |
| 3136 | } |
| 3137 | } |
| 3138 | if (!success) |
| 3139 | { |
| 3140 | m_inst_mode = eModeInvalid; |
| 3141 | m_inst_pc = LLDB_INVALID_ADDRESS; |
| 3142 | } |
| 3143 | return success; |
| 3144 | } |
| 3145 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3146 | uint32_t |
| 3147 | EmulateInstructionARM::ArchVersion () |
| 3148 | { |
| 3149 | return m_arm_isa; |
| 3150 | } |
| 3151 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3152 | bool |
| 3153 | EmulateInstructionARM::ConditionPassed () |
| 3154 | { |
| 3155 | if (m_inst_cpsr == 0) |
| 3156 | return false; |
| 3157 | |
| 3158 | const uint32_t cond = CurrentCond (); |
| 3159 | |
| 3160 | if (cond == UINT32_MAX) |
| 3161 | return false; |
| 3162 | |
| 3163 | bool result = false; |
| 3164 | switch (UnsignedBits(cond, 3, 1)) |
| 3165 | { |
| 3166 | case 0: result = (m_inst_cpsr & MASK_CPSR_Z) != 0; break; |
| 3167 | case 1: result = (m_inst_cpsr & MASK_CPSR_C) != 0; break; |
| 3168 | case 2: result = (m_inst_cpsr & MASK_CPSR_N) != 0; break; |
| 3169 | case 3: result = (m_inst_cpsr & MASK_CPSR_V) != 0; break; |
| 3170 | case 4: result = ((m_inst_cpsr & MASK_CPSR_C) != 0) && ((m_inst_cpsr & MASK_CPSR_Z) == 0); break; |
| 3171 | case 5: |
| 3172 | { |
| 3173 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 3174 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 3175 | result = n == v; |
| 3176 | } |
| 3177 | break; |
| 3178 | case 6: |
| 3179 | { |
| 3180 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 3181 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 3182 | result = n == v && ((m_inst_cpsr & MASK_CPSR_Z) == 0); |
| 3183 | } |
| 3184 | break; |
| 3185 | case 7: |
| 3186 | result = true; |
| 3187 | break; |
| 3188 | } |
| 3189 | |
| 3190 | if (cond & 1) |
| 3191 | result = !result; |
| 3192 | return result; |
| 3193 | } |
| 3194 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3195 | uint32_t |
| 3196 | EmulateInstructionARM::CurrentCond () |
| 3197 | { |
| 3198 | switch (m_inst_mode) |
| 3199 | { |
| 3200 | default: |
| 3201 | case eModeInvalid: |
| 3202 | break; |
| 3203 | |
| 3204 | case eModeARM: |
| 3205 | return UnsignedBits(m_inst.opcode.inst32, 31, 28); |
| 3206 | |
| 3207 | case eModeThumb: |
| 3208 | // For T1 and T3 encodings of the Branch instruction, it returns the 4-bit |
| 3209 | // 'cond' field of the encoding. |
| 3210 | if (m_inst.opcode_type == eOpcode16 && |
| 3211 | Bits32(m_inst.opcode.inst16, 15, 12) == 0x0d && |
| 3212 | Bits32(m_inst.opcode.inst16, 11, 7) != 0x0f) |
| 3213 | { |
| 3214 | return Bits32(m_inst.opcode.inst16, 11, 7); |
| 3215 | } |
| 3216 | else if (m_inst.opcode_type == eOpcode32 && |
| 3217 | Bits32(m_inst.opcode.inst32, 31, 27) == 0x1e && |
| 3218 | Bits32(m_inst.opcode.inst32, 15, 14) == 0x02 && |
| 3219 | Bits32(m_inst.opcode.inst32, 12, 12) == 0x00 && |
| 3220 | Bits32(m_inst.opcode.inst32, 25, 22) <= 0x0d) |
| 3221 | { |
| 3222 | return Bits32(m_inst.opcode.inst32, 25, 22); |
| 3223 | } |
| 3224 | |
| 3225 | return m_it_session.GetCond(); |
| 3226 | } |
| 3227 | return UINT32_MAX; // Return invalid value |
| 3228 | } |
| 3229 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3230 | bool |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 3231 | EmulateInstructionARM::InITBlock() |
| 3232 | { |
| 3233 | return CurrentInstrSet() == eModeThumb && m_it_session.InITBlock(); |
| 3234 | } |
| 3235 | |
| 3236 | bool |
| 3237 | EmulateInstructionARM::LastInITBlock() |
| 3238 | { |
| 3239 | return CurrentInstrSet() == eModeThumb && m_it_session.LastInITBlock(); |
| 3240 | } |
| 3241 | |
| 3242 | bool |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3243 | EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr) |
| 3244 | { |
| 3245 | addr_t target; |
| 3246 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3247 | // Check the current instruction set. |
| 3248 | if (CurrentInstrSet() == eModeARM) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3249 | target = addr & 0xfffffffc; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3250 | else |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3251 | target = addr & 0xfffffffe; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3252 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3253 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 3254 | return false; |
| 3255 | |
| 3256 | return true; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3257 | } |
| 3258 | |
| 3259 | // As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr. |
| 3260 | bool |
| 3261 | EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr) |
| 3262 | { |
| 3263 | addr_t target; |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3264 | // If the CPSR is changed due to switching between ARM and Thumb ISETSTATE, |
| 3265 | // we want to record it and issue a WriteRegister callback so the clients |
| 3266 | // can track the mode changes accordingly. |
| 3267 | bool cpsr_changed = false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3268 | |
| 3269 | if (BitIsSet(addr, 0)) |
| 3270 | { |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3271 | if (CurrentInstrSet() != eModeThumb) |
| 3272 | { |
| 3273 | SelectInstrSet(eModeThumb); |
| 3274 | cpsr_changed = true; |
| 3275 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3276 | target = addr & 0xfffffffe; |
| 3277 | context.arg2 = eModeThumb; |
| 3278 | } |
| 3279 | else if (BitIsClear(addr, 1)) |
| 3280 | { |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3281 | if (CurrentInstrSet() != eModeARM) |
| 3282 | { |
| 3283 | SelectInstrSet(eModeARM); |
| 3284 | cpsr_changed = true; |
| 3285 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3286 | target = addr & 0xfffffffc; |
| 3287 | context.arg2 = eModeARM; |
| 3288 | } |
| 3289 | else |
| 3290 | return false; // address<1:0> == '10' => UNPREDICTABLE |
| 3291 | |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3292 | if (cpsr_changed) |
| 3293 | { |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3294 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3295 | return false; |
| 3296 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3297 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 3298 | return false; |
| 3299 | |
| 3300 | return true; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3301 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3302 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3303 | // Dispatches to either BXWritePC or BranchWritePC based on architecture versions. |
| 3304 | bool |
| 3305 | EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr) |
| 3306 | { |
| 3307 | if (ArchVersion() >= ARMv5T) |
| 3308 | return BXWritePC(context, addr); |
| 3309 | else |
| 3310 | return BranchWritePC((const Context)context, addr); |
| 3311 | } |
| 3312 | |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 3313 | // Dispatches to either BXWritePC or BranchWritePC based on architecture versions and current instruction set. |
| 3314 | bool |
| 3315 | EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr) |
| 3316 | { |
| 3317 | if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM) |
| 3318 | return BXWritePC(context, addr); |
| 3319 | else |
| 3320 | return BranchWritePC((const Context)context, addr); |
| 3321 | } |
| 3322 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3323 | EmulateInstructionARM::Mode |
| 3324 | EmulateInstructionARM::CurrentInstrSet () |
| 3325 | { |
| 3326 | return m_inst_mode; |
| 3327 | } |
| 3328 | |
| 3329 | // Set the 'T' bit of our CPSR. The m_inst_mode gets updated when the next |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3330 | // ReadInstruction() is performed. This function has a side effect of updating |
| 3331 | // the m_new_inst_cpsr member variable if necessary. |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3332 | bool |
| 3333 | EmulateInstructionARM::SelectInstrSet (Mode arm_or_thumb) |
| 3334 | { |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3335 | m_new_inst_cpsr = m_inst_cpsr; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3336 | switch (arm_or_thumb) |
| 3337 | { |
| 3338 | default: |
| 3339 | return false; |
| 3340 | eModeARM: |
| 3341 | // Clear the T bit. |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3342 | m_new_inst_cpsr &= ~MASK_CPSR_T; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3343 | break; |
| 3344 | eModeThumb: |
| 3345 | // Set the T bit. |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3346 | m_new_inst_cpsr |= MASK_CPSR_T; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3347 | break; |
| 3348 | } |
| 3349 | return true; |
| 3350 | } |
| 3351 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3352 | // This function returns TRUE if the processor currently provides support for |
| 3353 | // unaligned memory accesses, or FALSE otherwise. This is always TRUE in ARMv7, |
| 3354 | // controllable by the SCTLR.U bit in ARMv6, and always FALSE before ARMv6. |
| 3355 | bool |
| 3356 | EmulateInstructionARM::UnalignedSupport() |
| 3357 | { |
| 3358 | return (ArchVersion() >= ARMv7); |
| 3359 | } |
| 3360 | |
Johnny Chen | bf6ad17 | 2011-02-11 01:29:53 +0000 | [diff] [blame] | 3361 | // The main addition and subtraction instructions can produce status information |
| 3362 | // about both unsigned carry and signed overflow conditions. This status |
| 3363 | // information can be used to synthesize multi-word additions and subtractions. |
| 3364 | EmulateInstructionARM::AddWithCarryResult |
| 3365 | EmulateInstructionARM::AddWithCarry (uint32_t x, uint32_t y, uint8_t carry_in) |
| 3366 | { |
| 3367 | uint32_t result; |
| 3368 | uint8_t carry_out; |
| 3369 | uint8_t overflow; |
| 3370 | |
| 3371 | uint64_t unsigned_sum = x + y + carry_in; |
| 3372 | int64_t signed_sum = (int32_t)x + (int32_t)y + (int32_t)carry_in; |
| 3373 | |
| 3374 | result = UnsignedBits(unsigned_sum, 31, 0); |
| 3375 | carry_out = (result == unsigned_sum ? 0 : 1); |
| 3376 | overflow = ((int32_t)result == signed_sum ? 0 : 1); |
| 3377 | |
| 3378 | AddWithCarryResult res = { result, carry_out, overflow }; |
| 3379 | return res; |
| 3380 | } |
| 3381 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3382 | bool |
| 3383 | EmulateInstructionARM::EvaluateInstruction () |
| 3384 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 3385 | // Advance the ITSTATE bits to their values for the next instruction. |
| 3386 | if (m_inst_mode == eModeThumb && m_it_session.InITBlock()) |
| 3387 | m_it_session.ITAdvance(); |
| 3388 | |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame^] | 3389 | // If the flags have changed, flush it out. |
| 3390 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 3391 | m_inst_cpsr = m_new_inst_cpsr; |
| 3392 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3393 | return false; |
| 3394 | } |