blob: a67110ce9b98e509c1615ae66559a7a9c4c494e5 [file] [log] [blame]
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001//===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements routines for translating from LLVM IR into SelectionDAG IR.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "isel"
15#include "SelectionDAGBuild.h"
16#include "llvm/ADT/BitVector.h"
Dan Gohman5b229802008-09-04 20:49:27 +000017#include "llvm/ADT/SmallSet.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000018#include "llvm/Analysis/AliasAnalysis.h"
19#include "llvm/Constants.h"
20#include "llvm/CallingConv.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalVariable.h"
24#include "llvm/InlineAsm.h"
25#include "llvm/Instructions.h"
26#include "llvm/Intrinsics.h"
27#include "llvm/IntrinsicInst.h"
Bill Wendlingb2a42982008-11-06 02:29:10 +000028#include "llvm/Module.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000029#include "llvm/CodeGen/FastISel.h"
30#include "llvm/CodeGen/GCStrategy.h"
31#include "llvm/CodeGen/GCMetadata.h"
32#include "llvm/CodeGen/MachineFunction.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineJumpTableInfo.h"
36#include "llvm/CodeGen/MachineModuleInfo.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
Bill Wendlingb2a42982008-11-06 02:29:10 +000038#include "llvm/CodeGen/PseudoSourceValue.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000039#include "llvm/CodeGen/SelectionDAG.h"
Devang Patel83489bb2009-01-13 00:35:13 +000040#include "llvm/CodeGen/DwarfWriter.h"
41#include "llvm/Analysis/DebugInfo.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000042#include "llvm/Target/TargetRegisterInfo.h"
43#include "llvm/Target/TargetData.h"
44#include "llvm/Target/TargetFrameInfo.h"
45#include "llvm/Target/TargetInstrInfo.h"
46#include "llvm/Target/TargetLowering.h"
47#include "llvm/Target/TargetMachine.h"
48#include "llvm/Target/TargetOptions.h"
49#include "llvm/Support/Compiler.h"
Mikhail Glushenkov2388a582009-01-16 07:02:28 +000050#include "llvm/Support/CommandLine.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000051#include "llvm/Support/Debug.h"
52#include "llvm/Support/MathExtras.h"
Anton Korobeynikov56d245b2008-12-23 22:26:18 +000053#include "llvm/Support/raw_ostream.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000054#include <algorithm>
55using namespace llvm;
56
Dale Johannesen601d3c02008-09-05 01:48:15 +000057/// LimitFloatPrecision - Generate low-precision inline sequences for
58/// some float libcalls (6, 8 or 12 bits).
59static unsigned LimitFloatPrecision;
60
61static cl::opt<unsigned, true>
62LimitFPPrecision("limit-float-precision",
63 cl::desc("Generate low-precision inline sequences "
64 "for some float libcalls"),
65 cl::location(LimitFloatPrecision),
66 cl::init(0));
67
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000068/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
Dan Gohman2c91d102009-01-06 22:53:52 +000069/// of insertvalue or extractvalue indices that identify a member, return
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000070/// the linearized index of the start of the member.
71///
72static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
73 const unsigned *Indices,
74 const unsigned *IndicesEnd,
75 unsigned CurIndex = 0) {
76 // Base case: We're done.
77 if (Indices && Indices == IndicesEnd)
78 return CurIndex;
79
80 // Given a struct type, recursively traverse the elements.
81 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
82 for (StructType::element_iterator EB = STy->element_begin(),
83 EI = EB,
84 EE = STy->element_end();
85 EI != EE; ++EI) {
86 if (Indices && *Indices == unsigned(EI - EB))
87 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
88 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
89 }
Dan Gohman2c91d102009-01-06 22:53:52 +000090 return CurIndex;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000091 }
92 // Given an array type, recursively traverse the elements.
93 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
94 const Type *EltTy = ATy->getElementType();
95 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
96 if (Indices && *Indices == i)
97 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
98 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
99 }
Dan Gohman2c91d102009-01-06 22:53:52 +0000100 return CurIndex;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000101 }
102 // We haven't found the type we're looking for, so keep searching.
103 return CurIndex + 1;
104}
105
106/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
107/// MVTs that represent all the individual underlying
108/// non-aggregate types that comprise it.
109///
110/// If Offsets is non-null, it points to a vector to be filled in
111/// with the in-memory offsets of each of the individual values.
112///
113static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
114 SmallVectorImpl<MVT> &ValueVTs,
115 SmallVectorImpl<uint64_t> *Offsets = 0,
116 uint64_t StartingOffset = 0) {
117 // Given a struct type, recursively traverse the elements.
118 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
119 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
120 for (StructType::element_iterator EB = STy->element_begin(),
121 EI = EB,
122 EE = STy->element_end();
123 EI != EE; ++EI)
124 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
125 StartingOffset + SL->getElementOffset(EI - EB));
126 return;
127 }
128 // Given an array type, recursively traverse the elements.
129 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
130 const Type *EltTy = ATy->getElementType();
Duncan Sandsceb4d1a2009-01-12 20:38:59 +0000131 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000132 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
133 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
134 StartingOffset + i * EltSize);
135 return;
136 }
137 // Base case: we can get an MVT for this LLVM IR type.
138 ValueVTs.push_back(TLI.getValueType(Ty));
139 if (Offsets)
140 Offsets->push_back(StartingOffset);
141}
142
Dan Gohman2a7c6712008-09-03 23:18:39 +0000143namespace llvm {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000144 /// RegsForValue - This struct represents the registers (physical or virtual)
145 /// that a particular set of values is assigned, and the type information about
146 /// the value. The most common situation is to represent one value at a time,
147 /// but struct or array values are handled element-wise as multiple values.
148 /// The splitting of aggregates is performed recursively, so that we never
149 /// have aggregate-typed registers. The values at this point do not necessarily
150 /// have legal types, so each value may require one or more registers of some
151 /// legal type.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000152 ///
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000153 struct VISIBILITY_HIDDEN RegsForValue {
154 /// TLI - The TargetLowering object.
155 ///
156 const TargetLowering *TLI;
157
158 /// ValueVTs - The value types of the values, which may not be legal, and
159 /// may need be promoted or synthesized from one or more registers.
160 ///
161 SmallVector<MVT, 4> ValueVTs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000162
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000163 /// RegVTs - The value types of the registers. This is the same size as
164 /// ValueVTs and it records, for each value, what the type of the assigned
165 /// register or registers are. (Individual values are never synthesized
166 /// from more than one type of register.)
167 ///
168 /// With virtual registers, the contents of RegVTs is redundant with TLI's
169 /// getRegisterType member function, however when with physical registers
170 /// it is necessary to have a separate record of the types.
171 ///
172 SmallVector<MVT, 4> RegVTs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000173
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000174 /// Regs - This list holds the registers assigned to the values.
175 /// Each legal or promoted value requires one register, and each
176 /// expanded value requires multiple registers.
177 ///
178 SmallVector<unsigned, 4> Regs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000179
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000180 RegsForValue() : TLI(0) {}
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000181
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000182 RegsForValue(const TargetLowering &tli,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000183 const SmallVector<unsigned, 4> &regs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000184 MVT regvt, MVT valuevt)
185 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
186 RegsForValue(const TargetLowering &tli,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000187 const SmallVector<unsigned, 4> &regs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000188 const SmallVector<MVT, 4> &regvts,
189 const SmallVector<MVT, 4> &valuevts)
190 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 unsigned Reg, const Type *Ty) : TLI(&tli) {
193 ComputeValueVTs(tli, Ty, ValueVTs);
194
195 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
196 MVT ValueVT = ValueVTs[Value];
197 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
198 MVT RegisterVT = TLI->getRegisterType(ValueVT);
199 for (unsigned i = 0; i != NumRegs; ++i)
200 Regs.push_back(Reg + i);
201 RegVTs.push_back(RegisterVT);
202 Reg += NumRegs;
203 }
204 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000205
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000206 /// append - Add the specified values to this one.
207 void append(const RegsForValue &RHS) {
208 TLI = RHS.TLI;
209 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
210 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
211 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
212 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000213
214
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000215 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000216 /// this value and returns the result as a ValueVTs value. This uses
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000217 /// Chain/Flag as the input and updates them for the output Chain/Flag.
218 /// If the Flag pointer is NULL, no flag is used.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000219 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000220 SDValue &Chain, SDValue *Flag) const;
221
222 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000223 /// specified value into the registers specified by this object. This uses
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000224 /// Chain/Flag as the input and updates them for the output Chain/Flag.
225 /// If the Flag pointer is NULL, no flag is used.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000226 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000227 SDValue &Chain, SDValue *Flag) const;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000228
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000229 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000230 /// operand list. This adds the code marker and includes the number of
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000231 /// values added into it.
232 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
233 std::vector<SDValue> &Ops) const;
234 };
235}
236
237/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000238/// PHI nodes or outside of the basic block that defines it, or used by a
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000239/// switch or atomic instruction, which may expand to multiple basic blocks.
240static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
241 if (isa<PHINode>(I)) return true;
242 BasicBlock *BB = I->getParent();
243 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
244 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
245 // FIXME: Remove switchinst special case.
246 isa<SwitchInst>(*UI))
247 return true;
248 return false;
249}
250
251/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
252/// entry block, return true. This includes arguments used by switches, since
253/// the switch may expand into multiple basic blocks.
254static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
255 // With FastISel active, we may be splitting blocks, so force creation
256 // of virtual registers for all non-dead arguments.
Dan Gohman33134c42008-09-25 17:05:24 +0000257 // Don't force virtual registers for byval arguments though, because
258 // fast-isel can't handle those in all cases.
259 if (EnableFastISel && !A->hasByValAttr())
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000260 return A->use_empty();
261
262 BasicBlock *Entry = A->getParent()->begin();
263 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
264 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
265 return false; // Use not in entry block.
266 return true;
267}
268
269FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
270 : TLI(tli) {
271}
272
273void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
274 bool EnableFastISel) {
275 Fn = &fn;
276 MF = &mf;
277 RegInfo = &MF->getRegInfo();
278
279 // Create a vreg for each argument register that is not dead and is used
280 // outside of the entry block for the function.
281 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
282 AI != E; ++AI)
283 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
284 InitializeRegForValue(AI);
285
286 // Initialize the mapping of values to registers. This is only set up for
287 // instruction values that are used outside of the block that defines
288 // them.
289 Function::iterator BB = Fn->begin(), EB = Fn->end();
290 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
291 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
292 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
293 const Type *Ty = AI->getAllocatedType();
Duncan Sandsceb4d1a2009-01-12 20:38:59 +0000294 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000295 unsigned Align =
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000296 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
297 AI->getAlignment());
298
299 TySize *= CUI->getZExtValue(); // Get total allocated size.
300 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
301 StaticAllocaMap[AI] =
302 MF->getFrameInfo()->CreateStackObject(TySize, Align);
303 }
304
305 for (; BB != EB; ++BB)
306 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
307 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
308 if (!isa<AllocaInst>(I) ||
309 !StaticAllocaMap.count(cast<AllocaInst>(I)))
310 InitializeRegForValue(I);
311
312 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
313 // also creates the initial PHI MachineInstrs, though none of the input
314 // operands are populated.
315 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
316 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
317 MBBMap[BB] = MBB;
318 MF->push_back(MBB);
319
320 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
321 // appropriate.
322 PHINode *PN;
323 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
324 if (PN->use_empty()) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000325
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000326 unsigned PHIReg = ValueMap[PN];
327 assert(PHIReg && "PHI node does not have an assigned virtual register!");
328
329 SmallVector<MVT, 4> ValueVTs;
330 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
331 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
332 MVT VT = ValueVTs[vti];
333 unsigned NumRegisters = TLI.getNumRegisters(VT);
Dan Gohman6448d912008-09-04 15:39:15 +0000334 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000335 for (unsigned i = 0; i != NumRegisters; ++i)
Bill Wendlingec37e982009-02-03 01:33:28 +0000336 BuildMI(MBB, DebugLoc::getUnknownLoc(),
337 TII->get(TargetInstrInfo::PHI), PHIReg + i);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000338 PHIReg += NumRegisters;
339 }
340 }
341 }
342}
343
344unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
345 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
346}
347
348/// CreateRegForValue - Allocate the appropriate number of virtual registers of
349/// the correctly promoted or expanded types. Assign these registers
350/// consecutive vreg numbers and return the first assigned number.
351///
352/// In the case that the given value has struct or array type, this function
353/// will assign registers for each member or element.
354///
355unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
356 SmallVector<MVT, 4> ValueVTs;
357 ComputeValueVTs(TLI, V->getType(), ValueVTs);
358
359 unsigned FirstReg = 0;
360 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
361 MVT ValueVT = ValueVTs[Value];
362 MVT RegisterVT = TLI.getRegisterType(ValueVT);
363
364 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
365 for (unsigned i = 0; i != NumRegs; ++i) {
366 unsigned R = MakeReg(RegisterVT);
367 if (!FirstReg) FirstReg = R;
368 }
369 }
370 return FirstReg;
371}
372
373/// getCopyFromParts - Create a value that contains the specified legal parts
374/// combined into the value they represent. If the parts combine to a type
375/// larger then ValueVT then AssertOp can be used to specify whether the extra
376/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
377/// (ISD::AssertSext).
Dale Johannesen66978ee2009-01-31 02:22:37 +0000378static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
379 const SDValue *Parts,
Duncan Sands0b3aa262009-01-28 14:42:54 +0000380 unsigned NumParts, MVT PartVT, MVT ValueVT,
381 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000382 assert(NumParts > 0 && "No parts to assemble!");
Dan Gohmane9530ec2009-01-15 16:58:17 +0000383 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000384 SDValue Val = Parts[0];
385
386 if (NumParts > 1) {
387 // Assemble the value from multiple parts.
388 if (!ValueVT.isVector()) {
389 unsigned PartBits = PartVT.getSizeInBits();
390 unsigned ValueBits = ValueVT.getSizeInBits();
391
392 // Assemble the power of 2 part.
393 unsigned RoundParts = NumParts & (NumParts - 1) ?
394 1 << Log2_32(NumParts) : NumParts;
395 unsigned RoundBits = PartBits * RoundParts;
396 MVT RoundVT = RoundBits == ValueBits ?
397 ValueVT : MVT::getIntegerVT(RoundBits);
398 SDValue Lo, Hi;
399
Duncan Sandsd22ec5f2008-10-29 14:22:20 +0000400 MVT HalfVT = ValueVT.isInteger() ?
401 MVT::getIntegerVT(RoundBits/2) :
402 MVT::getFloatingPointVT(RoundBits/2);
403
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000404 if (RoundParts > 2) {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000405 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
406 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000407 PartVT, HalfVT);
408 } else {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000409 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
410 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000411 }
412 if (TLI.isBigEndian())
413 std::swap(Lo, Hi);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000414 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000415
416 if (RoundParts < NumParts) {
417 // Assemble the trailing non-power-of-2 part.
418 unsigned OddParts = NumParts - RoundParts;
419 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000420 Hi = getCopyFromParts(DAG, dl,
421 Parts+RoundParts, OddParts, PartVT, OddVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000422
423 // Combine the round and odd parts.
424 Lo = Val;
425 if (TLI.isBigEndian())
426 std::swap(Lo, Hi);
427 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000428 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
429 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000430 DAG.getConstant(Lo.getValueType().getSizeInBits(),
Duncan Sands92abc622009-01-31 15:50:11 +0000431 TLI.getPointerTy()));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000432 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
433 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000434 }
435 } else {
436 // Handle a multi-element vector.
437 MVT IntermediateVT, RegisterVT;
438 unsigned NumIntermediates;
439 unsigned NumRegs =
440 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
441 RegisterVT);
442 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
443 NumParts = NumRegs; // Silence a compiler warning.
444 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
445 assert(RegisterVT == Parts[0].getValueType() &&
446 "Part type doesn't match part!");
447
448 // Assemble the parts into intermediate operands.
449 SmallVector<SDValue, 8> Ops(NumIntermediates);
450 if (NumIntermediates == NumParts) {
451 // If the register was not expanded, truncate or copy the value,
452 // as appropriate.
453 for (unsigned i = 0; i != NumParts; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000454 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000455 PartVT, IntermediateVT);
456 } else if (NumParts > 0) {
457 // If the intermediate type was expanded, build the intermediate operands
458 // from the parts.
459 assert(NumParts % NumIntermediates == 0 &&
460 "Must expand into a divisible number of parts!");
461 unsigned Factor = NumParts / NumIntermediates;
462 for (unsigned i = 0; i != NumIntermediates; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000463 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000464 PartVT, IntermediateVT);
465 }
466
467 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
468 // operands.
469 Val = DAG.getNode(IntermediateVT.isVector() ?
Dale Johannesen66978ee2009-01-31 02:22:37 +0000470 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000471 ValueVT, &Ops[0], NumIntermediates);
472 }
473 }
474
475 // There is now one part, held in Val. Correct it to match ValueVT.
476 PartVT = Val.getValueType();
477
478 if (PartVT == ValueVT)
479 return Val;
480
481 if (PartVT.isVector()) {
482 assert(ValueVT.isVector() && "Unknown vector conversion!");
Dale Johannesen66978ee2009-01-31 02:22:37 +0000483 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000484 }
485
486 if (ValueVT.isVector()) {
487 assert(ValueVT.getVectorElementType() == PartVT &&
488 ValueVT.getVectorNumElements() == 1 &&
489 "Only trivial scalar-to-vector conversions should get here!");
Dale Johannesen66978ee2009-01-31 02:22:37 +0000490 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000491 }
492
493 if (PartVT.isInteger() &&
494 ValueVT.isInteger()) {
495 if (ValueVT.bitsLT(PartVT)) {
496 // For a truncate, see if we have any information to
497 // indicate whether the truncated bits will always be
498 // zero or sign-extension.
499 if (AssertOp != ISD::DELETED_NODE)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000500 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000501 DAG.getValueType(ValueVT));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000502 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000503 } else {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000504 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000505 }
506 }
507
508 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
509 if (ValueVT.bitsLT(Val.getValueType()))
510 // FP_ROUND's are always exact here.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000511 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000512 DAG.getIntPtrConstant(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000513 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000514 }
515
516 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
Dale Johannesen66978ee2009-01-31 02:22:37 +0000517 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000518
519 assert(0 && "Unknown mismatch!");
520 return SDValue();
521}
522
523/// getCopyToParts - Create a series of nodes that contain the specified value
524/// split into legal parts. If the parts contain more bits than Val, then, for
525/// integers, ExtendKind can be used to specify how to generate the extra bits.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000526static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
Chris Lattner01426e12008-10-21 00:45:36 +0000527 SDValue *Parts, unsigned NumParts, MVT PartVT,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000528 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
Dan Gohmane9530ec2009-01-15 16:58:17 +0000529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000530 MVT PtrVT = TLI.getPointerTy();
531 MVT ValueVT = Val.getValueType();
532 unsigned PartBits = PartVT.getSizeInBits();
533 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
534
535 if (!NumParts)
536 return;
537
538 if (!ValueVT.isVector()) {
539 if (PartVT == ValueVT) {
540 assert(NumParts == 1 && "No-op copy with multiple parts!");
541 Parts[0] = Val;
542 return;
543 }
544
545 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
546 // If the parts cover more bits than the value has, promote the value.
547 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
548 assert(NumParts == 1 && "Do not know what to promote to!");
Dale Johannesen66978ee2009-01-31 02:22:37 +0000549 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000550 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
551 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000552 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000553 } else {
554 assert(0 && "Unknown mismatch!");
555 }
556 } else if (PartBits == ValueVT.getSizeInBits()) {
557 // Different types of the same size.
558 assert(NumParts == 1 && PartVT != ValueVT);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000559 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000560 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
561 // If the parts cover less bits than value has, truncate the value.
562 if (PartVT.isInteger() && ValueVT.isInteger()) {
563 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000564 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000565 } else {
566 assert(0 && "Unknown mismatch!");
567 }
568 }
569
570 // The value may have changed - recompute ValueVT.
571 ValueVT = Val.getValueType();
572 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
573 "Failed to tile the value with PartVT!");
574
575 if (NumParts == 1) {
576 assert(PartVT == ValueVT && "Type conversion failed!");
577 Parts[0] = Val;
578 return;
579 }
580
581 // Expand the value into multiple parts.
582 if (NumParts & (NumParts - 1)) {
583 // The number of parts is not a power of 2. Split off and copy the tail.
584 assert(PartVT.isInteger() && ValueVT.isInteger() &&
585 "Do not know what to expand to!");
586 unsigned RoundParts = 1 << Log2_32(NumParts);
587 unsigned RoundBits = RoundParts * PartBits;
588 unsigned OddParts = NumParts - RoundParts;
Dale Johannesen66978ee2009-01-31 02:22:37 +0000589 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
Duncan Sands0b3aa262009-01-28 14:42:54 +0000590 DAG.getConstant(RoundBits,
Duncan Sands92abc622009-01-31 15:50:11 +0000591 TLI.getPointerTy()));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000592 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000593 if (TLI.isBigEndian())
594 // The odd parts were reversed by getCopyToParts - unreverse them.
595 std::reverse(Parts + RoundParts, Parts + NumParts);
596 NumParts = RoundParts;
597 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000598 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000599 }
600
601 // The number of parts is a power of 2. Repeatedly bisect the value using
602 // EXTRACT_ELEMENT.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000603 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000604 MVT::getIntegerVT(ValueVT.getSizeInBits()),
605 Val);
606 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
607 for (unsigned i = 0; i < NumParts; i += StepSize) {
608 unsigned ThisBits = StepSize * PartBits / 2;
609 MVT ThisVT = MVT::getIntegerVT (ThisBits);
610 SDValue &Part0 = Parts[i];
611 SDValue &Part1 = Parts[i+StepSize/2];
612
Dale Johannesen66978ee2009-01-31 02:22:37 +0000613 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000614 ThisVT, Part0,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000615 DAG.getConstant(1, PtrVT));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000616 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000617 ThisVT, Part0,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000618 DAG.getConstant(0, PtrVT));
619
620 if (ThisBits == PartBits && ThisVT != PartVT) {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000621 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000622 PartVT, Part0);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000623 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000624 PartVT, Part1);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000625 }
626 }
627 }
628
629 if (TLI.isBigEndian())
630 std::reverse(Parts, Parts + NumParts);
631
632 return;
633 }
634
635 // Vector ValueVT.
636 if (NumParts == 1) {
637 if (PartVT != ValueVT) {
638 if (PartVT.isVector()) {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000639 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000640 } else {
641 assert(ValueVT.getVectorElementType() == PartVT &&
642 ValueVT.getVectorNumElements() == 1 &&
643 "Only trivial vector-to-scalar conversions should get here!");
Dale Johannesen66978ee2009-01-31 02:22:37 +0000644 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000645 PartVT, Val,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000646 DAG.getConstant(0, PtrVT));
647 }
648 }
649
650 Parts[0] = Val;
651 return;
652 }
653
654 // Handle a multi-element vector.
655 MVT IntermediateVT, RegisterVT;
656 unsigned NumIntermediates;
Dan Gohmane9530ec2009-01-15 16:58:17 +0000657 unsigned NumRegs = TLI
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000658 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
659 RegisterVT);
660 unsigned NumElements = ValueVT.getVectorNumElements();
661
662 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
663 NumParts = NumRegs; // Silence a compiler warning.
664 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
665
666 // Split the vector into intermediate operands.
667 SmallVector<SDValue, 8> Ops(NumIntermediates);
668 for (unsigned i = 0; i != NumIntermediates; ++i)
669 if (IntermediateVT.isVector())
Dale Johannesen66978ee2009-01-31 02:22:37 +0000670 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000671 IntermediateVT, Val,
672 DAG.getConstant(i * (NumElements / NumIntermediates),
673 PtrVT));
674 else
Dale Johannesen66978ee2009-01-31 02:22:37 +0000675 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000676 IntermediateVT, Val,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000677 DAG.getConstant(i, PtrVT));
678
679 // Split the intermediate operands into legal parts.
680 if (NumParts == NumIntermediates) {
681 // If the register was not expanded, promote or copy the value,
682 // as appropriate.
683 for (unsigned i = 0; i != NumParts; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000684 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000685 } else if (NumParts > 0) {
686 // If the intermediate type was expanded, split each the value into
687 // legal parts.
688 assert(NumParts % NumIntermediates == 0 &&
689 "Must expand into a divisible number of parts!");
690 unsigned Factor = NumParts / NumIntermediates;
691 for (unsigned i = 0; i != NumIntermediates; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000692 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000693 }
694}
695
696
697void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
698 AA = &aa;
699 GFI = gfi;
700 TD = DAG.getTarget().getTargetData();
701}
702
703/// clear - Clear out the curret SelectionDAG and the associated
704/// state and prepare this SelectionDAGLowering object to be used
705/// for a new block. This doesn't clear out information about
706/// additional blocks that are needed to complete switch lowering
707/// or PHI node updating; that information is cleared out as it is
708/// consumed.
709void SelectionDAGLowering::clear() {
710 NodeMap.clear();
711 PendingLoads.clear();
712 PendingExports.clear();
713 DAG.clear();
714}
715
716/// getRoot - Return the current virtual root of the Selection DAG,
717/// flushing any PendingLoad items. This must be done before emitting
718/// a store or any other node that may need to be ordered after any
719/// prior load instructions.
720///
721SDValue SelectionDAGLowering::getRoot() {
722 if (PendingLoads.empty())
723 return DAG.getRoot();
724
725 if (PendingLoads.size() == 1) {
726 SDValue Root = PendingLoads[0];
727 DAG.setRoot(Root);
728 PendingLoads.clear();
729 return Root;
730 }
731
732 // Otherwise, we have to make a token factor node.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000733 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000734 &PendingLoads[0], PendingLoads.size());
735 PendingLoads.clear();
736 DAG.setRoot(Root);
737 return Root;
738}
739
740/// getControlRoot - Similar to getRoot, but instead of flushing all the
741/// PendingLoad items, flush all the PendingExports items. It is necessary
742/// to do this before emitting a terminator instruction.
743///
744SDValue SelectionDAGLowering::getControlRoot() {
745 SDValue Root = DAG.getRoot();
746
747 if (PendingExports.empty())
748 return Root;
749
750 // Turn all of the CopyToReg chains into one factored node.
751 if (Root.getOpcode() != ISD::EntryToken) {
752 unsigned i = 0, e = PendingExports.size();
753 for (; i != e; ++i) {
754 assert(PendingExports[i].getNode()->getNumOperands() > 1);
755 if (PendingExports[i].getNode()->getOperand(0) == Root)
756 break; // Don't add the root if we already indirectly depend on it.
757 }
758
759 if (i == e)
760 PendingExports.push_back(Root);
761 }
762
Dale Johannesen66978ee2009-01-31 02:22:37 +0000763 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000764 &PendingExports[0],
765 PendingExports.size());
766 PendingExports.clear();
767 DAG.setRoot(Root);
768 return Root;
769}
770
771void SelectionDAGLowering::visit(Instruction &I) {
772 visit(I.getOpcode(), I);
773}
774
775void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
776 // Note: this doesn't use InstVisitor, because it has to work with
777 // ConstantExpr's in addition to instructions.
778 switch (Opcode) {
779 default: assert(0 && "Unknown instruction type encountered!");
780 abort();
781 // Build the switch statement using the Instruction.def file.
782#define HANDLE_INST(NUM, OPCODE, CLASS) \
783 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
784#include "llvm/Instruction.def"
785 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000786}
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000787
788void SelectionDAGLowering::visitAdd(User &I) {
789 if (I.getType()->isFPOrFPVector())
790 visitBinary(I, ISD::FADD);
791 else
792 visitBinary(I, ISD::ADD);
793}
794
795void SelectionDAGLowering::visitMul(User &I) {
796 if (I.getType()->isFPOrFPVector())
797 visitBinary(I, ISD::FMUL);
798 else
799 visitBinary(I, ISD::MUL);
800}
801
802SDValue SelectionDAGLowering::getValue(const Value *V) {
803 SDValue &N = NodeMap[V];
804 if (N.getNode()) return N;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000805
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000806 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
807 MVT VT = TLI.getValueType(V->getType(), true);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000808
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000809 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
Dan Gohman4fbd7962008-09-12 18:08:03 +0000810 return N = DAG.getConstant(*CI, VT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000811
812 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
813 return N = DAG.getGlobalAddress(GV, VT);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000814
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000815 if (isa<ConstantPointerNull>(C))
816 return N = DAG.getConstant(0, TLI.getPointerTy());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000817
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000818 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
Dan Gohman4fbd7962008-09-12 18:08:03 +0000819 return N = DAG.getConstantFP(*CFP, VT);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000820
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000821 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
822 !V->getType()->isAggregateType())
Dale Johannesen66978ee2009-01-31 02:22:37 +0000823 return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000824
825 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
826 visit(CE->getOpcode(), *CE);
827 SDValue N1 = NodeMap[V];
828 assert(N1.getNode() && "visit didn't populate the ValueMap!");
829 return N1;
830 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000831
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000832 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
833 SmallVector<SDValue, 4> Constants;
834 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
835 OI != OE; ++OI) {
836 SDNode *Val = getValue(*OI).getNode();
837 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
838 Constants.push_back(SDValue(Val, i));
839 }
840 return DAG.getMergeValues(&Constants[0], Constants.size());
841 }
842
843 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
844 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
845 "Unknown struct or array constant!");
846
847 SmallVector<MVT, 4> ValueVTs;
848 ComputeValueVTs(TLI, C->getType(), ValueVTs);
849 unsigned NumElts = ValueVTs.size();
850 if (NumElts == 0)
851 return SDValue(); // empty struct
852 SmallVector<SDValue, 4> Constants(NumElts);
853 for (unsigned i = 0; i != NumElts; ++i) {
854 MVT EltVT = ValueVTs[i];
855 if (isa<UndefValue>(C))
Dale Johannesen66978ee2009-01-31 02:22:37 +0000856 Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000857 else if (EltVT.isFloatingPoint())
858 Constants[i] = DAG.getConstantFP(0, EltVT);
859 else
860 Constants[i] = DAG.getConstant(0, EltVT);
861 }
862 return DAG.getMergeValues(&Constants[0], NumElts);
863 }
864
865 const VectorType *VecTy = cast<VectorType>(V->getType());
866 unsigned NumElements = VecTy->getNumElements();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000867
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000868 // Now that we know the number and type of the elements, get that number of
869 // elements into the Ops array based on what kind of constant it is.
870 SmallVector<SDValue, 16> Ops;
871 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
872 for (unsigned i = 0; i != NumElements; ++i)
873 Ops.push_back(getValue(CP->getOperand(i)));
874 } else {
875 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
876 "Unknown vector constant!");
877 MVT EltVT = TLI.getValueType(VecTy->getElementType());
878
879 SDValue Op;
880 if (isa<UndefValue>(C))
Dale Johannesen66978ee2009-01-31 02:22:37 +0000881 Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000882 else if (EltVT.isFloatingPoint())
883 Op = DAG.getConstantFP(0, EltVT);
884 else
885 Op = DAG.getConstant(0, EltVT);
886 Ops.assign(NumElements, Op);
887 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000888
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000889 // Create a BUILD_VECTOR node.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000890 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000891 VT, &Ops[0], Ops.size());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000892 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000893
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000894 // If this is a static alloca, generate it as the frameindex instead of
895 // computation.
896 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
897 DenseMap<const AllocaInst*, int>::iterator SI =
898 FuncInfo.StaticAllocaMap.find(AI);
899 if (SI != FuncInfo.StaticAllocaMap.end())
900 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
901 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000902
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000903 unsigned InReg = FuncInfo.ValueMap[V];
904 assert(InReg && "Value not in map!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000905
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000906 RegsForValue RFV(TLI, InReg, V->getType());
907 SDValue Chain = DAG.getEntryNode();
Dale Johannesen66978ee2009-01-31 02:22:37 +0000908 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000909}
910
911
912void SelectionDAGLowering::visitRet(ReturnInst &I) {
913 if (I.getNumOperands() == 0) {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000914 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000915 MVT::Other, getControlRoot()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000916 return;
917 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000918
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000919 SmallVector<SDValue, 8> NewValues;
920 NewValues.push_back(getControlRoot());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000921 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000922 SmallVector<MVT, 4> ValueVTs;
923 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
Dan Gohman7ea1ca62008-10-21 20:00:42 +0000924 unsigned NumValues = ValueVTs.size();
925 if (NumValues == 0) continue;
926
927 SDValue RetOp = getValue(I.getOperand(i));
928 for (unsigned j = 0, f = NumValues; j != f; ++j) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000929 MVT VT = ValueVTs[j];
930
931 // FIXME: C calling convention requires the return type to be promoted to
Dale Johannesenc9c6da62008-09-25 20:47:45 +0000932 // at least 32-bit. But this is not necessary for non-C calling
933 // conventions.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000934 if (VT.isInteger()) {
935 MVT MinVT = TLI.getRegisterType(MVT::i32);
936 if (VT.bitsLT(MinVT))
937 VT = MinVT;
938 }
939
940 unsigned NumParts = TLI.getNumRegisters(VT);
941 MVT PartVT = TLI.getRegisterType(VT);
942 SmallVector<SDValue, 4> Parts(NumParts);
943 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000944
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000945 const Function *F = I.getParent()->getParent();
Devang Patel05988662008-09-25 21:00:45 +0000946 if (F->paramHasAttr(0, Attribute::SExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000947 ExtendKind = ISD::SIGN_EXTEND;
Devang Patel05988662008-09-25 21:00:45 +0000948 else if (F->paramHasAttr(0, Attribute::ZExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000949 ExtendKind = ISD::ZERO_EXTEND;
950
Dale Johannesen66978ee2009-01-31 02:22:37 +0000951 getCopyToParts(DAG, getCurDebugLoc(),
952 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000953 &Parts[0], NumParts, PartVT, ExtendKind);
954
Dale Johannesenc9c6da62008-09-25 20:47:45 +0000955 // 'inreg' on function refers to return value
956 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
Devang Patel05988662008-09-25 21:00:45 +0000957 if (F->paramHasAttr(0, Attribute::InReg))
Dale Johannesenc9c6da62008-09-25 20:47:45 +0000958 Flags.setInReg();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000959 for (unsigned i = 0; i < NumParts; ++i) {
960 NewValues.push_back(Parts[i]);
Dale Johannesenc9c6da62008-09-25 20:47:45 +0000961 NewValues.push_back(DAG.getArgFlags(Flags));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000962 }
963 }
964 }
Dale Johannesen66978ee2009-01-31 02:22:37 +0000965 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000966 &NewValues[0], NewValues.size()));
967}
968
969/// ExportFromCurrentBlock - If this condition isn't known to be exported from
970/// the current basic block, add it to ValueMap now so that we'll get a
971/// CopyTo/FromReg.
972void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
973 // No need to export constants.
974 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000975
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000976 // Already exported?
977 if (FuncInfo.isExportedInst(V)) return;
978
979 unsigned Reg = FuncInfo.InitializeRegForValue(V);
980 CopyValueToVirtualRegister(V, Reg);
981}
982
983bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
984 const BasicBlock *FromBB) {
985 // The operands of the setcc have to be in this block. We don't know
986 // how to export them from some other block.
987 if (Instruction *VI = dyn_cast<Instruction>(V)) {
988 // Can export from current BB.
989 if (VI->getParent() == FromBB)
990 return true;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000991
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000992 // Is already exported, noop.
993 return FuncInfo.isExportedInst(V);
994 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000995
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000996 // If this is an argument, we can export it if the BB is the entry block or
997 // if it is already exported.
998 if (isa<Argument>(V)) {
999 if (FromBB == &FromBB->getParent()->getEntryBlock())
1000 return true;
1001
1002 // Otherwise, can only export this if it is already exported.
1003 return FuncInfo.isExportedInst(V);
1004 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001005
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001006 // Otherwise, constants can always be exported.
1007 return true;
1008}
1009
1010static bool InBlock(const Value *V, const BasicBlock *BB) {
1011 if (const Instruction *I = dyn_cast<Instruction>(V))
1012 return I->getParent() == BB;
1013 return true;
1014}
1015
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00001016/// getFCmpCondCode - Return the ISD condition code corresponding to
1017/// the given LLVM IR floating-point condition code. This includes
1018/// consideration of global floating-point math flags.
1019///
1020static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1021 ISD::CondCode FPC, FOC;
1022 switch (Pred) {
1023 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1024 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1025 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1026 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1027 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1028 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1029 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1030 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1031 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1032 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1033 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1034 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1035 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1036 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1037 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1038 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1039 default:
1040 assert(0 && "Invalid FCmp predicate opcode!");
1041 FOC = FPC = ISD::SETFALSE;
1042 break;
1043 }
1044 if (FiniteOnlyFPMath())
1045 return FOC;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001046 else
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00001047 return FPC;
1048}
1049
1050/// getICmpCondCode - Return the ISD condition code corresponding to
1051/// the given LLVM IR integer condition code.
1052///
1053static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1054 switch (Pred) {
1055 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1056 case ICmpInst::ICMP_NE: return ISD::SETNE;
1057 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1058 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1059 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1060 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1061 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1062 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1063 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1064 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1065 default:
1066 assert(0 && "Invalid ICmp predicate opcode!");
1067 return ISD::SETNE;
1068 }
1069}
1070
Dan Gohmanc2277342008-10-17 21:16:08 +00001071/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1072/// This function emits a branch and is used at the leaves of an OR or an
1073/// AND operator tree.
1074///
1075void
1076SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1077 MachineBasicBlock *TBB,
1078 MachineBasicBlock *FBB,
1079 MachineBasicBlock *CurBB) {
1080 const BasicBlock *BB = CurBB->getBasicBlock();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001081
Dan Gohmanc2277342008-10-17 21:16:08 +00001082 // If the leaf of the tree is a comparison, merge the condition into
1083 // the caseblock.
1084 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1085 // The operands of the cmp have to be in this block. We don't know
1086 // how to export them from some other block. If this is the first block
1087 // of the sequence, no exporting is needed.
1088 if (CurBB == CurMBB ||
1089 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1090 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001091 ISD::CondCode Condition;
1092 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00001093 Condition = getICmpCondCode(IC->getPredicate());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001094 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00001095 Condition = getFCmpCondCode(FC->getPredicate());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001096 } else {
1097 Condition = ISD::SETEQ; // silence warning.
1098 assert(0 && "Unknown compare instruction");
1099 }
Dan Gohmanc2277342008-10-17 21:16:08 +00001100
1101 CaseBlock CB(Condition, BOp->getOperand(0),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001102 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1103 SwitchCases.push_back(CB);
1104 return;
1105 }
Dan Gohmanc2277342008-10-17 21:16:08 +00001106 }
1107
1108 // Create a CaseBlock record representing this branch.
1109 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1110 NULL, TBB, FBB, CurBB);
1111 SwitchCases.push_back(CB);
1112}
1113
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001114/// FindMergedConditions - If Cond is an expression like
Dan Gohmanc2277342008-10-17 21:16:08 +00001115void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1116 MachineBasicBlock *TBB,
1117 MachineBasicBlock *FBB,
1118 MachineBasicBlock *CurBB,
1119 unsigned Opc) {
1120 // If this node is not part of the or/and tree, emit it as a branch.
1121 Instruction *BOp = dyn_cast<Instruction>(Cond);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001122 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
Dan Gohmanc2277342008-10-17 21:16:08 +00001123 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1124 BOp->getParent() != CurBB->getBasicBlock() ||
1125 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1126 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1127 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001128 return;
1129 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001130
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001131 // Create TmpBB after CurBB.
1132 MachineFunction::iterator BBI = CurBB;
1133 MachineFunction &MF = DAG.getMachineFunction();
1134 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1135 CurBB->getParent()->insert(++BBI, TmpBB);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001136
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001137 if (Opc == Instruction::Or) {
1138 // Codegen X | Y as:
1139 // jmp_if_X TBB
1140 // jmp TmpBB
1141 // TmpBB:
1142 // jmp_if_Y TBB
1143 // jmp FBB
1144 //
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001145
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001146 // Emit the LHS condition.
1147 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001148
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001149 // Emit the RHS condition into TmpBB.
1150 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1151 } else {
1152 assert(Opc == Instruction::And && "Unknown merge op!");
1153 // Codegen X & Y as:
1154 // jmp_if_X TmpBB
1155 // jmp FBB
1156 // TmpBB:
1157 // jmp_if_Y TBB
1158 // jmp FBB
1159 //
1160 // This requires creation of TmpBB after CurBB.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001161
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001162 // Emit the LHS condition.
1163 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001164
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001165 // Emit the RHS condition into TmpBB.
1166 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1167 }
1168}
1169
1170/// If the set of cases should be emitted as a series of branches, return true.
1171/// If we should emit this as a bunch of and/or'd together conditions, return
1172/// false.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001173bool
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001174SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1175 if (Cases.size() != 2) return true;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001176
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001177 // If this is two comparisons of the same values or'd or and'd together, they
1178 // will get folded into a single comparison, so don't emit two blocks.
1179 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1180 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1181 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1182 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1183 return false;
1184 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001185
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001186 return true;
1187}
1188
1189void SelectionDAGLowering::visitBr(BranchInst &I) {
1190 // Update machine-CFG edges.
1191 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1192
1193 // Figure out which block is immediately after the current one.
1194 MachineBasicBlock *NextBlock = 0;
1195 MachineFunction::iterator BBI = CurMBB;
1196 if (++BBI != CurMBB->getParent()->end())
1197 NextBlock = BBI;
1198
1199 if (I.isUnconditional()) {
1200 // Update machine-CFG edges.
1201 CurMBB->addSuccessor(Succ0MBB);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001202
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001203 // If this is not a fall-through branch, emit the branch.
1204 if (Succ0MBB != NextBlock)
Dale Johannesen66978ee2009-01-31 02:22:37 +00001205 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001206 MVT::Other, getControlRoot(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001207 DAG.getBasicBlock(Succ0MBB)));
1208 return;
1209 }
1210
1211 // If this condition is one of the special cases we handle, do special stuff
1212 // now.
1213 Value *CondVal = I.getCondition();
1214 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1215
1216 // If this is a series of conditions that are or'd or and'd together, emit
1217 // this as a sequence of branches instead of setcc's with and/or operations.
1218 // For example, instead of something like:
1219 // cmp A, B
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001220 // C = seteq
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001221 // cmp D, E
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001222 // F = setle
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001223 // or C, F
1224 // jnz foo
1225 // Emit:
1226 // cmp A, B
1227 // je foo
1228 // cmp D, E
1229 // jle foo
1230 //
1231 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001232 if (BOp->hasOneUse() &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001233 (BOp->getOpcode() == Instruction::And ||
1234 BOp->getOpcode() == Instruction::Or)) {
1235 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1236 // If the compares in later blocks need to use values not currently
1237 // exported from this block, export them now. This block should always
1238 // be the first entry.
1239 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001240
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001241 // Allow some cases to be rejected.
1242 if (ShouldEmitAsBranches(SwitchCases)) {
1243 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1244 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1245 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1246 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001247
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001248 // Emit the branch for this block.
1249 visitSwitchCase(SwitchCases[0]);
1250 SwitchCases.erase(SwitchCases.begin());
1251 return;
1252 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001253
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001254 // Okay, we decided not to do this, remove any inserted MBB's and clear
1255 // SwitchCases.
1256 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1257 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001258
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001259 SwitchCases.clear();
1260 }
1261 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001262
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001263 // Create a CaseBlock record representing this branch.
1264 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1265 NULL, Succ0MBB, Succ1MBB, CurMBB);
1266 // Use visitSwitchCase to actually insert the fast branch sequence for this
1267 // cond branch.
1268 visitSwitchCase(CB);
1269}
1270
1271/// visitSwitchCase - Emits the necessary code to represent a single node in
1272/// the binary search tree resulting from lowering a switch instruction.
1273void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1274 SDValue Cond;
1275 SDValue CondLHS = getValue(CB.CmpLHS);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001276
1277 // Build the setcc now.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001278 if (CB.CmpMHS == NULL) {
1279 // Fold "(X == true)" to X and "(X == false)" to !X to
1280 // handle common cases produced by branch lowering.
1281 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1282 Cond = CondLHS;
1283 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1284 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00001285 Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001286 CondLHS.getValueType(), CondLHS, True);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001287 } else
1288 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1289 } else {
1290 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1291
Anton Korobeynikov23218582008-12-23 22:25:27 +00001292 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1293 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001294
1295 SDValue CmpOp = getValue(CB.CmpMHS);
1296 MVT VT = CmpOp.getValueType();
1297
1298 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1299 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1300 } else {
Dale Johannesen66978ee2009-01-31 02:22:37 +00001301 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001302 VT, CmpOp, DAG.getConstant(Low, VT));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001303 Cond = DAG.getSetCC(MVT::i1, SUB,
1304 DAG.getConstant(High-Low, VT), ISD::SETULE);
1305 }
1306 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001307
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001308 // Update successor info
1309 CurMBB->addSuccessor(CB.TrueBB);
1310 CurMBB->addSuccessor(CB.FalseBB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001311
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001312 // Set NextBlock to be the MBB immediately after the current one, if any.
1313 // This is used to avoid emitting unnecessary branches to the next block.
1314 MachineBasicBlock *NextBlock = 0;
1315 MachineFunction::iterator BBI = CurMBB;
1316 if (++BBI != CurMBB->getParent()->end())
1317 NextBlock = BBI;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001318
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001319 // If the lhs block is the next block, invert the condition so that we can
1320 // fall through to the lhs instead of the rhs block.
1321 if (CB.TrueBB == NextBlock) {
1322 std::swap(CB.TrueBB, CB.FalseBB);
1323 SDValue True = DAG.getConstant(1, Cond.getValueType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00001324 Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001325 Cond.getValueType(), Cond, True);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001326 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00001327 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001328 MVT::Other, getControlRoot(), Cond,
1329 DAG.getBasicBlock(CB.TrueBB));
Anton Korobeynikov23218582008-12-23 22:25:27 +00001330
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001331 // If the branch was constant folded, fix up the CFG.
1332 if (BrCond.getOpcode() == ISD::BR) {
1333 CurMBB->removeSuccessor(CB.FalseBB);
1334 DAG.setRoot(BrCond);
1335 } else {
1336 // Otherwise, go ahead and insert the false branch.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001337 if (BrCond == getControlRoot())
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001338 CurMBB->removeSuccessor(CB.TrueBB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001339
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001340 if (CB.FalseBB == NextBlock)
1341 DAG.setRoot(BrCond);
1342 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001343 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001344 DAG.getBasicBlock(CB.FalseBB)));
1345 }
1346}
1347
1348/// visitJumpTable - Emit JumpTable node in the current MBB
1349void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1350 // Emit the code for the jump table
1351 assert(JT.Reg != -1U && "Should lower JT Header first!");
1352 MVT PTy = TLI.getPointerTy();
1353 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1354 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
Dale Johannesen66978ee2009-01-31 02:22:37 +00001355 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001356 MVT::Other, Index.getValue(1),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001357 Table, Index));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001358}
1359
1360/// visitJumpTableHeader - This function emits necessary code to produce index
1361/// in the JumpTable from switch case.
1362void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1363 JumpTableHeader &JTH) {
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001364 // Subtract the lowest switch case value from the value being switched on and
1365 // conditional branch to default mbb if the result is greater than the
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001366 // difference between smallest and largest cases.
1367 SDValue SwitchOp = getValue(JTH.SValue);
1368 MVT VT = SwitchOp.getValueType();
Dale Johannesen66978ee2009-01-31 02:22:37 +00001369 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001370 DAG.getConstant(JTH.First, VT));
Anton Korobeynikov23218582008-12-23 22:25:27 +00001371
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001372 // The SDNode we just created, which holds the value being switched on minus
1373 // the the smallest case value, needs to be copied to a virtual register so it
1374 // can be used as an index into the jump table in a subsequent basic block.
1375 // This value may be smaller or larger than the target's pointer type, and
1376 // therefore require extension or truncating.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001377 if (VT.bitsGT(TLI.getPointerTy()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00001378 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001379 TLI.getPointerTy(), SUB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001380 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001381 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001382 TLI.getPointerTy(), SUB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001383
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001384 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1385 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1386 JT.Reg = JumpTableReg;
1387
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001388 // Emit the range check for the jump table, and branch to the default block
1389 // for the switch statement if the value being switched on exceeds the largest
1390 // case in the switch.
Duncan Sands5480c042009-01-01 15:52:00 +00001391 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001392 DAG.getConstant(JTH.Last-JTH.First,VT),
1393 ISD::SETUGT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001394
1395 // Set NextBlock to be the MBB immediately after the current one, if any.
1396 // This is used to avoid emitting unnecessary branches to the next block.
1397 MachineBasicBlock *NextBlock = 0;
1398 MachineFunction::iterator BBI = CurMBB;
1399 if (++BBI != CurMBB->getParent()->end())
1400 NextBlock = BBI;
1401
Dale Johannesen66978ee2009-01-31 02:22:37 +00001402 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001403 MVT::Other, CopyTo, CMP,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001404 DAG.getBasicBlock(JT.Default));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001405
1406 if (JT.MBB == NextBlock)
1407 DAG.setRoot(BrCond);
1408 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001409 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001410 DAG.getBasicBlock(JT.MBB)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001411}
1412
1413/// visitBitTestHeader - This function emits necessary code to produce value
1414/// suitable for "bit tests"
1415void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1416 // Subtract the minimum value
1417 SDValue SwitchOp = getValue(B.SValue);
1418 MVT VT = SwitchOp.getValueType();
Dale Johannesen66978ee2009-01-31 02:22:37 +00001419 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001420 DAG.getConstant(B.First, VT));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001421
1422 // Check range
Duncan Sands5480c042009-01-01 15:52:00 +00001423 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001424 DAG.getConstant(B.Range, VT),
1425 ISD::SETUGT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001426
1427 SDValue ShiftOp;
Duncan Sands92abc622009-01-31 15:50:11 +00001428 if (VT.bitsGT(TLI.getPointerTy()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00001429 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Duncan Sands92abc622009-01-31 15:50:11 +00001430 TLI.getPointerTy(), SUB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001431 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001432 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Duncan Sands92abc622009-01-31 15:50:11 +00001433 TLI.getPointerTy(), SUB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001434
Duncan Sands92abc622009-01-31 15:50:11 +00001435 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
Anton Korobeynikov36c826a2009-01-26 19:26:01 +00001436 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001437
1438 // Set NextBlock to be the MBB immediately after the current one, if any.
1439 // This is used to avoid emitting unnecessary branches to the next block.
1440 MachineBasicBlock *NextBlock = 0;
1441 MachineFunction::iterator BBI = CurMBB;
1442 if (++BBI != CurMBB->getParent()->end())
1443 NextBlock = BBI;
1444
1445 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1446
1447 CurMBB->addSuccessor(B.Default);
1448 CurMBB->addSuccessor(MBB);
1449
Dale Johannesen66978ee2009-01-31 02:22:37 +00001450 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001451 MVT::Other, CopyTo, RangeCmp,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001452 DAG.getBasicBlock(B.Default));
Anton Korobeynikov23218582008-12-23 22:25:27 +00001453
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001454 if (MBB == NextBlock)
1455 DAG.setRoot(BrRange);
1456 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001457 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001458 DAG.getBasicBlock(MBB)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001459}
1460
1461/// visitBitTestCase - this function produces one "bit test"
1462void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1463 unsigned Reg,
1464 BitTestCase &B) {
Anton Korobeynikov36c826a2009-01-26 19:26:01 +00001465 // Make desired shift
1466 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg,
Duncan Sands92abc622009-01-31 15:50:11 +00001467 TLI.getPointerTy());
Dale Johannesen66978ee2009-01-31 02:22:37 +00001468 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001469 TLI.getPointerTy(),
Anton Korobeynikov36c826a2009-01-26 19:26:01 +00001470 DAG.getConstant(1, TLI.getPointerTy()),
1471 ShiftOp);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001472
Anton Korobeynikov36c826a2009-01-26 19:26:01 +00001473 // Emit bit tests and jumps
Dale Johannesen66978ee2009-01-31 02:22:37 +00001474 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001475 TLI.getPointerTy(), SwitchVal,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001476 DAG.getConstant(B.Mask, TLI.getPointerTy()));
Duncan Sands5480c042009-01-01 15:52:00 +00001477 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()),
1478 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001479 ISD::SETNE);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001480
1481 CurMBB->addSuccessor(B.TargetBB);
1482 CurMBB->addSuccessor(NextMBB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001483
Dale Johannesen66978ee2009-01-31 02:22:37 +00001484 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001485 MVT::Other, getControlRoot(),
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001486 AndCmp, DAG.getBasicBlock(B.TargetBB));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001487
1488 // Set NextBlock to be the MBB immediately after the current one, if any.
1489 // This is used to avoid emitting unnecessary branches to the next block.
1490 MachineBasicBlock *NextBlock = 0;
1491 MachineFunction::iterator BBI = CurMBB;
1492 if (++BBI != CurMBB->getParent()->end())
1493 NextBlock = BBI;
1494
1495 if (NextMBB == NextBlock)
1496 DAG.setRoot(BrAnd);
1497 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001498 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001499 DAG.getBasicBlock(NextMBB)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001500}
1501
1502void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1503 // Retrieve successors.
1504 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1505 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1506
Gabor Greifb67e6b32009-01-15 11:10:44 +00001507 const Value *Callee(I.getCalledValue());
1508 if (isa<InlineAsm>(Callee))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001509 visitInlineAsm(&I);
1510 else
Gabor Greifb67e6b32009-01-15 11:10:44 +00001511 LowerCallTo(&I, getValue(Callee), false, LandingPad);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001512
1513 // If the value of the invoke is used outside of its defining block, make it
1514 // available as a virtual register.
1515 if (!I.use_empty()) {
1516 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1517 if (VMI != FuncInfo.ValueMap.end())
1518 CopyValueToVirtualRegister(&I, VMI->second);
1519 }
1520
1521 // Update successor info
1522 CurMBB->addSuccessor(Return);
1523 CurMBB->addSuccessor(LandingPad);
1524
1525 // Drop into normal successor.
Dale Johannesen66978ee2009-01-31 02:22:37 +00001526 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001527 MVT::Other, getControlRoot(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001528 DAG.getBasicBlock(Return)));
1529}
1530
1531void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1532}
1533
1534/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1535/// small case ranges).
1536bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1537 CaseRecVector& WorkList,
1538 Value* SV,
1539 MachineBasicBlock* Default) {
1540 Case& BackCase = *(CR.Range.second-1);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001541
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001542 // Size is the number of Cases represented by this range.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001543 size_t Size = CR.Range.second - CR.Range.first;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001544 if (Size > 3)
Anton Korobeynikov23218582008-12-23 22:25:27 +00001545 return false;
1546
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001547 // Get the MachineFunction which holds the current MBB. This is used when
1548 // inserting any additional MBBs necessary to represent the switch.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001549 MachineFunction *CurMF = CurMBB->getParent();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001550
1551 // Figure out which block is immediately after the current one.
1552 MachineBasicBlock *NextBlock = 0;
1553 MachineFunction::iterator BBI = CR.CaseBB;
1554
1555 if (++BBI != CurMBB->getParent()->end())
1556 NextBlock = BBI;
1557
1558 // TODO: If any two of the cases has the same destination, and if one value
1559 // is the same as the other, but has one bit unset that the other has set,
1560 // use bit manipulation to do two compares at once. For example:
1561 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
Anton Korobeynikov23218582008-12-23 22:25:27 +00001562
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001563 // Rearrange the case blocks so that the last one falls through if possible.
1564 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1565 // The last case block won't fall through into 'NextBlock' if we emit the
1566 // branches in this order. See if rearranging a case value would help.
1567 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1568 if (I->BB == NextBlock) {
1569 std::swap(*I, BackCase);
1570 break;
1571 }
1572 }
1573 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001574
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001575 // Create a CaseBlock record representing a conditional branch to
1576 // the Case's target mbb if the value being switched on SV is equal
1577 // to C.
1578 MachineBasicBlock *CurBlock = CR.CaseBB;
1579 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1580 MachineBasicBlock *FallThrough;
1581 if (I != E-1) {
1582 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1583 CurMF->insert(BBI, FallThrough);
1584 } else {
1585 // If the last case doesn't match, go to the default block.
1586 FallThrough = Default;
1587 }
1588
1589 Value *RHS, *LHS, *MHS;
1590 ISD::CondCode CC;
1591 if (I->High == I->Low) {
1592 // This is just small small case range :) containing exactly 1 case
1593 CC = ISD::SETEQ;
1594 LHS = SV; RHS = I->High; MHS = NULL;
1595 } else {
1596 CC = ISD::SETLE;
1597 LHS = I->Low; MHS = SV; RHS = I->High;
1598 }
1599 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001600
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001601 // If emitting the first comparison, just call visitSwitchCase to emit the
1602 // code into the current block. Otherwise, push the CaseBlock onto the
1603 // vector to be later processed by SDISel, and insert the node's MBB
1604 // before the next MBB.
1605 if (CurBlock == CurMBB)
1606 visitSwitchCase(CB);
1607 else
1608 SwitchCases.push_back(CB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001609
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001610 CurBlock = FallThrough;
1611 }
1612
1613 return true;
1614}
1615
1616static inline bool areJTsAllowed(const TargetLowering &TLI) {
1617 return !DisableJumpTables &&
Dan Gohmanf560ffa2009-01-28 17:46:25 +00001618 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1619 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001620}
Anton Korobeynikov23218582008-12-23 22:25:27 +00001621
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001622static APInt ComputeRange(const APInt &First, const APInt &Last) {
1623 APInt LastExt(Last), FirstExt(First);
1624 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1625 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1626 return (LastExt - FirstExt + 1ULL);
1627}
1628
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001629/// handleJTSwitchCase - Emit jumptable for current switch case range
1630bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1631 CaseRecVector& WorkList,
1632 Value* SV,
1633 MachineBasicBlock* Default) {
1634 Case& FrontCase = *CR.Range.first;
1635 Case& BackCase = *(CR.Range.second-1);
1636
Anton Korobeynikov23218582008-12-23 22:25:27 +00001637 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1638 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001639
Anton Korobeynikov23218582008-12-23 22:25:27 +00001640 size_t TSize = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001641 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1642 I!=E; ++I)
1643 TSize += I->size();
1644
1645 if (!areJTsAllowed(TLI) || TSize <= 3)
1646 return false;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001647
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001648 APInt Range = ComputeRange(First, Last);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001649 double Density = (double)TSize / Range.roundToDouble();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001650 if (Density < 0.4)
1651 return false;
1652
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001653 DEBUG(errs() << "Lowering jump table\n"
1654 << "First entry: " << First << ". Last entry: " << Last << '\n'
1655 << "Range: " << Range
1656 << "Size: " << TSize << ". Density: " << Density << "\n\n");
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001657
1658 // Get the MachineFunction which holds the current MBB. This is used when
1659 // inserting any additional MBBs necessary to represent the switch.
1660 MachineFunction *CurMF = CurMBB->getParent();
1661
1662 // Figure out which block is immediately after the current one.
1663 MachineBasicBlock *NextBlock = 0;
1664 MachineFunction::iterator BBI = CR.CaseBB;
1665
1666 if (++BBI != CurMBB->getParent()->end())
1667 NextBlock = BBI;
1668
1669 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1670
1671 // Create a new basic block to hold the code for loading the address
1672 // of the jump table, and jumping to it. Update successor information;
1673 // we will either branch to the default case for the switch, or the jump
1674 // table.
1675 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1676 CurMF->insert(BBI, JumpTableBB);
1677 CR.CaseBB->addSuccessor(Default);
1678 CR.CaseBB->addSuccessor(JumpTableBB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001679
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001680 // Build a vector of destination BBs, corresponding to each target
1681 // of the jump table. If the value of the jump table slot corresponds to
1682 // a case statement, push the case's BB onto the vector, otherwise, push
1683 // the default BB.
1684 std::vector<MachineBasicBlock*> DestBBs;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001685 APInt TEI = First;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001686 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
Anton Korobeynikov23218582008-12-23 22:25:27 +00001687 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1688 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1689
1690 if (Low.sle(TEI) && TEI.sle(High)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001691 DestBBs.push_back(I->BB);
1692 if (TEI==High)
1693 ++I;
1694 } else {
1695 DestBBs.push_back(Default);
1696 }
1697 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001698
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001699 // Update successor info. Add one edge to each unique successor.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001700 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1701 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001702 E = DestBBs.end(); I != E; ++I) {
1703 if (!SuccsHandled[(*I)->getNumber()]) {
1704 SuccsHandled[(*I)->getNumber()] = true;
1705 JumpTableBB->addSuccessor(*I);
1706 }
1707 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001708
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001709 // Create a jump table index for this jump table, or return an existing
1710 // one.
1711 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001712
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001713 // Set the jump table information so that we can codegen it as a second
1714 // MachineBasicBlock
1715 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1716 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1717 if (CR.CaseBB == CurMBB)
1718 visitJumpTableHeader(JT, JTH);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001719
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001720 JTCases.push_back(JumpTableBlock(JTH, JT));
1721
1722 return true;
1723}
1724
1725/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1726/// 2 subtrees.
1727bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1728 CaseRecVector& WorkList,
1729 Value* SV,
1730 MachineBasicBlock* Default) {
1731 // Get the MachineFunction which holds the current MBB. This is used when
1732 // inserting any additional MBBs necessary to represent the switch.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001733 MachineFunction *CurMF = CurMBB->getParent();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001734
1735 // Figure out which block is immediately after the current one.
1736 MachineBasicBlock *NextBlock = 0;
1737 MachineFunction::iterator BBI = CR.CaseBB;
1738
1739 if (++BBI != CurMBB->getParent()->end())
1740 NextBlock = BBI;
1741
1742 Case& FrontCase = *CR.Range.first;
1743 Case& BackCase = *(CR.Range.second-1);
1744 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1745
1746 // Size is the number of Cases represented by this range.
1747 unsigned Size = CR.Range.second - CR.Range.first;
1748
Anton Korobeynikov23218582008-12-23 22:25:27 +00001749 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1750 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001751 double FMetric = 0;
1752 CaseItr Pivot = CR.Range.first + Size/2;
1753
1754 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1755 // (heuristically) allow us to emit JumpTable's later.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001756 size_t TSize = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001757 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1758 I!=E; ++I)
1759 TSize += I->size();
1760
Anton Korobeynikov23218582008-12-23 22:25:27 +00001761 size_t LSize = FrontCase.size();
1762 size_t RSize = TSize-LSize;
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001763 DEBUG(errs() << "Selecting best pivot: \n"
1764 << "First: " << First << ", Last: " << Last <<'\n'
1765 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001766 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1767 J!=E; ++I, ++J) {
Anton Korobeynikov23218582008-12-23 22:25:27 +00001768 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1769 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001770 APInt Range = ComputeRange(LEnd, RBegin);
1771 assert((Range - 2ULL).isNonNegative() &&
1772 "Invalid case distance");
Anton Korobeynikov23218582008-12-23 22:25:27 +00001773 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1774 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001775 double Metric = Range.logBase2()*(LDensity+RDensity);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001776 // Should always split in some non-trivial place
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001777 DEBUG(errs() <<"=>Step\n"
1778 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1779 << "LDensity: " << LDensity
1780 << ", RDensity: " << RDensity << '\n'
1781 << "Metric: " << Metric << '\n');
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001782 if (FMetric < Metric) {
1783 Pivot = J;
1784 FMetric = Metric;
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001785 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001786 }
1787
1788 LSize += J->size();
1789 RSize -= J->size();
1790 }
1791 if (areJTsAllowed(TLI)) {
1792 // If our case is dense we *really* should handle it earlier!
1793 assert((FMetric > 0) && "Should handle dense range earlier!");
1794 } else {
1795 Pivot = CR.Range.first + Size/2;
1796 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001797
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001798 CaseRange LHSR(CR.Range.first, Pivot);
1799 CaseRange RHSR(Pivot, CR.Range.second);
1800 Constant *C = Pivot->Low;
1801 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001802
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001803 // We know that we branch to the LHS if the Value being switched on is
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001804 // less than the Pivot value, C. We use this to optimize our binary
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001805 // tree a bit, by recognizing that if SV is greater than or equal to the
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001806 // LHS's Case Value, and that Case Value is exactly one less than the
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001807 // Pivot's Value, then we can branch directly to the LHS's Target,
1808 // rather than creating a leaf node for it.
1809 if ((LHSR.second - LHSR.first) == 1 &&
1810 LHSR.first->High == CR.GE &&
Anton Korobeynikov23218582008-12-23 22:25:27 +00001811 cast<ConstantInt>(C)->getValue() ==
1812 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001813 TrueBB = LHSR.first->BB;
1814 } else {
1815 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1816 CurMF->insert(BBI, TrueBB);
1817 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1818 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001819
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001820 // Similar to the optimization above, if the Value being switched on is
1821 // known to be less than the Constant CR.LT, and the current Case Value
1822 // is CR.LT - 1, then we can branch directly to the target block for
1823 // the current Case Value, rather than emitting a RHS leaf node for it.
1824 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
Anton Korobeynikov23218582008-12-23 22:25:27 +00001825 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1826 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001827 FalseBB = RHSR.first->BB;
1828 } else {
1829 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1830 CurMF->insert(BBI, FalseBB);
1831 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1832 }
1833
1834 // Create a CaseBlock record representing a conditional branch to
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001835 // the LHS node if the value being switched on SV is less than C.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001836 // Otherwise, branch to LHS.
1837 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1838
1839 if (CR.CaseBB == CurMBB)
1840 visitSwitchCase(CB);
1841 else
1842 SwitchCases.push_back(CB);
1843
1844 return true;
1845}
1846
1847/// handleBitTestsSwitchCase - if current case range has few destination and
1848/// range span less, than machine word bitwidth, encode case range into series
1849/// of masks and emit bit tests with these masks.
1850bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1851 CaseRecVector& WorkList,
1852 Value* SV,
1853 MachineBasicBlock* Default){
1854 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1855
1856 Case& FrontCase = *CR.Range.first;
1857 Case& BackCase = *(CR.Range.second-1);
1858
1859 // Get the MachineFunction which holds the current MBB. This is used when
1860 // inserting any additional MBBs necessary to represent the switch.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001861 MachineFunction *CurMF = CurMBB->getParent();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001862
Anton Korobeynikov23218582008-12-23 22:25:27 +00001863 size_t numCmps = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001864 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1865 I!=E; ++I) {
1866 // Single case counts one, case range - two.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001867 numCmps += (I->Low == I->High ? 1 : 2);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001868 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001869
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001870 // Count unique destinations
1871 SmallSet<MachineBasicBlock*, 4> Dests;
1872 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1873 Dests.insert(I->BB);
1874 if (Dests.size() > 3)
1875 // Don't bother the code below, if there are too much unique destinations
1876 return false;
1877 }
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001878 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1879 << "Total number of comparisons: " << numCmps << '\n');
Anton Korobeynikov23218582008-12-23 22:25:27 +00001880
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001881 // Compute span of values.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001882 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1883 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001884 APInt cmpRange = maxValue - minValue;
1885
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001886 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1887 << "Low bound: " << minValue << '\n'
1888 << "High bound: " << maxValue << '\n');
Anton Korobeynikov23218582008-12-23 22:25:27 +00001889
1890 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001891 (!(Dests.size() == 1 && numCmps >= 3) &&
1892 !(Dests.size() == 2 && numCmps >= 5) &&
1893 !(Dests.size() >= 3 && numCmps >= 6)))
1894 return false;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001895
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001896 DEBUG(errs() << "Emitting bit tests\n");
Anton Korobeynikov23218582008-12-23 22:25:27 +00001897 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1898
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001899 // Optimize the case where all the case values fit in a
1900 // word without having to subtract minValue. In this case,
1901 // we can optimize away the subtraction.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001902 if (minValue.isNonNegative() &&
1903 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1904 cmpRange = maxValue;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001905 } else {
Anton Korobeynikov23218582008-12-23 22:25:27 +00001906 lowBound = minValue;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001907 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001908
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001909 CaseBitsVector CasesBits;
1910 unsigned i, count = 0;
1911
1912 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1913 MachineBasicBlock* Dest = I->BB;
1914 for (i = 0; i < count; ++i)
1915 if (Dest == CasesBits[i].BB)
1916 break;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001917
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001918 if (i == count) {
1919 assert((count < 3) && "Too much destinations to test!");
1920 CasesBits.push_back(CaseBits(0, Dest, 0));
1921 count++;
1922 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001923
1924 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1925 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1926
1927 uint64_t lo = (lowValue - lowBound).getZExtValue();
1928 uint64_t hi = (highValue - lowBound).getZExtValue();
1929
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001930 for (uint64_t j = lo; j <= hi; j++) {
1931 CasesBits[i].Mask |= 1ULL << j;
1932 CasesBits[i].Bits++;
1933 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001934
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001935 }
1936 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
Anton Korobeynikov23218582008-12-23 22:25:27 +00001937
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001938 BitTestInfo BTC;
1939
1940 // Figure out which block is immediately after the current one.
1941 MachineFunction::iterator BBI = CR.CaseBB;
1942 ++BBI;
1943
1944 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1945
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001946 DEBUG(errs() << "Cases:\n");
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001947 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001948 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
1949 << ", Bits: " << CasesBits[i].Bits
1950 << ", BB: " << CasesBits[i].BB << '\n');
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001951
1952 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1953 CurMF->insert(BBI, CaseBB);
1954 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1955 CaseBB,
1956 CasesBits[i].BB));
1957 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001958
1959 BitTestBlock BTB(lowBound, cmpRange, SV,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001960 -1U, (CR.CaseBB == CurMBB),
1961 CR.CaseBB, Default, BTC);
1962
1963 if (CR.CaseBB == CurMBB)
1964 visitBitTestHeader(BTB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001965
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001966 BitTestCases.push_back(BTB);
1967
1968 return true;
1969}
1970
1971
1972/// Clusterify - Transform simple list of Cases into list of CaseRange's
Anton Korobeynikov23218582008-12-23 22:25:27 +00001973size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001974 const SwitchInst& SI) {
Anton Korobeynikov23218582008-12-23 22:25:27 +00001975 size_t numCmps = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001976
1977 // Start with "simple" cases
Anton Korobeynikov23218582008-12-23 22:25:27 +00001978 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001979 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1980 Cases.push_back(Case(SI.getSuccessorValue(i),
1981 SI.getSuccessorValue(i),
1982 SMBB));
1983 }
1984 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1985
1986 // Merge case into clusters
Anton Korobeynikov23218582008-12-23 22:25:27 +00001987 if (Cases.size() >= 2)
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001988 // Must recompute end() each iteration because it may be
1989 // invalidated by erase if we hold on to it
Anton Korobeynikov23218582008-12-23 22:25:27 +00001990 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
1991 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
1992 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001993 MachineBasicBlock* nextBB = J->BB;
1994 MachineBasicBlock* currentBB = I->BB;
1995
1996 // If the two neighboring cases go to the same destination, merge them
1997 // into a single case.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001998 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001999 I->High = J->High;
2000 J = Cases.erase(J);
2001 } else {
2002 I = J++;
2003 }
2004 }
2005
2006 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2007 if (I->Low != I->High)
2008 // A range counts double, since it requires two compares.
2009 ++numCmps;
2010 }
2011
2012 return numCmps;
2013}
2014
Anton Korobeynikov23218582008-12-23 22:25:27 +00002015void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002016 // Figure out which block is immediately after the current one.
2017 MachineBasicBlock *NextBlock = 0;
2018 MachineFunction::iterator BBI = CurMBB;
2019
2020 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2021
2022 // If there is only the default destination, branch to it if it is not the
2023 // next basic block. Otherwise, just fall through.
2024 if (SI.getNumOperands() == 2) {
2025 // Update machine-CFG edges.
2026
2027 // If this is not a fall-through branch, emit the branch.
2028 CurMBB->addSuccessor(Default);
2029 if (Default != NextBlock)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002030 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002031 MVT::Other, getControlRoot(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002032 DAG.getBasicBlock(Default)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002033 return;
2034 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00002035
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002036 // If there are any non-default case statements, create a vector of Cases
2037 // representing each one, and sort the vector so that we can efficiently
2038 // create a binary search tree from them.
2039 CaseVector Cases;
Anton Korobeynikov23218582008-12-23 22:25:27 +00002040 size_t numCmps = Clusterify(Cases, SI);
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00002041 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2042 << ". Total compares: " << numCmps << '\n');
Devang Patel8a84e442009-01-05 17:31:22 +00002043 numCmps = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002044
2045 // Get the Value to be switched on and default basic blocks, which will be
2046 // inserted into CaseBlock records, representing basic blocks in the binary
2047 // search tree.
2048 Value *SV = SI.getOperand(0);
2049
2050 // Push the initial CaseRec onto the worklist
2051 CaseRecVector WorkList;
2052 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2053
2054 while (!WorkList.empty()) {
2055 // Grab a record representing a case range to process off the worklist
2056 CaseRec CR = WorkList.back();
2057 WorkList.pop_back();
2058
2059 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2060 continue;
Anton Korobeynikov23218582008-12-23 22:25:27 +00002061
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002062 // If the range has few cases (two or less) emit a series of specific
2063 // tests.
2064 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2065 continue;
Anton Korobeynikov23218582008-12-23 22:25:27 +00002066
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00002067 // If the switch has more than 5 blocks, and at least 40% dense, and the
2068 // target supports indirect branches, then emit a jump table rather than
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002069 // lowering the switch to a binary tree of conditional branches.
2070 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2071 continue;
Anton Korobeynikov23218582008-12-23 22:25:27 +00002072
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002073 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2074 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2075 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2076 }
2077}
2078
2079
2080void SelectionDAGLowering::visitSub(User &I) {
2081 // -0.0 - X --> fneg
2082 const Type *Ty = I.getType();
2083 if (isa<VectorType>(Ty)) {
2084 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2085 const VectorType *DestTy = cast<VectorType>(I.getType());
2086 const Type *ElTy = DestTy->getElementType();
2087 if (ElTy->isFloatingPoint()) {
2088 unsigned VL = DestTy->getNumElements();
2089 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2090 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2091 if (CV == CNZ) {
2092 SDValue Op2 = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002093 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002094 Op2.getValueType(), Op2));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002095 return;
2096 }
2097 }
2098 }
2099 }
2100 if (Ty->isFloatingPoint()) {
2101 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2102 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2103 SDValue Op2 = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002104 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002105 Op2.getValueType(), Op2));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002106 return;
2107 }
2108 }
2109
2110 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2111}
2112
2113void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2114 SDValue Op1 = getValue(I.getOperand(0));
2115 SDValue Op2 = getValue(I.getOperand(1));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002116
Dale Johannesen66978ee2009-01-31 02:22:37 +00002117 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002118 Op1.getValueType(), Op1, Op2));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002119}
2120
2121void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2122 SDValue Op1 = getValue(I.getOperand(0));
2123 SDValue Op2 = getValue(I.getOperand(1));
2124 if (!isa<VectorType>(I.getType())) {
Duncan Sands92abc622009-01-31 15:50:11 +00002125 if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002126 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Duncan Sands92abc622009-01-31 15:50:11 +00002127 TLI.getPointerTy(), Op2);
2128 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002129 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
Duncan Sands92abc622009-01-31 15:50:11 +00002130 TLI.getPointerTy(), Op2);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002131 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002132
Dale Johannesen66978ee2009-01-31 02:22:37 +00002133 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002134 Op1.getValueType(), Op1, Op2));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002135}
2136
2137void SelectionDAGLowering::visitICmp(User &I) {
2138 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2139 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2140 predicate = IC->getPredicate();
2141 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2142 predicate = ICmpInst::Predicate(IC->getPredicate());
2143 SDValue Op1 = getValue(I.getOperand(0));
2144 SDValue Op2 = getValue(I.getOperand(1));
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00002145 ISD::CondCode Opcode = getICmpCondCode(predicate);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002146 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2147}
2148
2149void SelectionDAGLowering::visitFCmp(User &I) {
2150 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2151 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2152 predicate = FC->getPredicate();
2153 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2154 predicate = FCmpInst::Predicate(FC->getPredicate());
2155 SDValue Op1 = getValue(I.getOperand(0));
2156 SDValue Op2 = getValue(I.getOperand(1));
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00002157 ISD::CondCode Condition = getFCmpCondCode(predicate);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002158 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2159}
2160
2161void SelectionDAGLowering::visitVICmp(User &I) {
2162 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2163 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2164 predicate = IC->getPredicate();
2165 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2166 predicate = ICmpInst::Predicate(IC->getPredicate());
2167 SDValue Op1 = getValue(I.getOperand(0));
2168 SDValue Op2 = getValue(I.getOperand(1));
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00002169 ISD::CondCode Opcode = getICmpCondCode(predicate);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002170 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2171}
2172
2173void SelectionDAGLowering::visitVFCmp(User &I) {
2174 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2175 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2176 predicate = FC->getPredicate();
2177 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2178 predicate = FCmpInst::Predicate(FC->getPredicate());
2179 SDValue Op1 = getValue(I.getOperand(0));
2180 SDValue Op2 = getValue(I.getOperand(1));
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00002181 ISD::CondCode Condition = getFCmpCondCode(predicate);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002182 MVT DestVT = TLI.getValueType(I.getType());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002183
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002184 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2185}
2186
2187void SelectionDAGLowering::visitSelect(User &I) {
Dan Gohman7ea1ca62008-10-21 20:00:42 +00002188 SmallVector<MVT, 4> ValueVTs;
2189 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2190 unsigned NumValues = ValueVTs.size();
2191 if (NumValues != 0) {
2192 SmallVector<SDValue, 4> Values(NumValues);
2193 SDValue Cond = getValue(I.getOperand(0));
2194 SDValue TrueVal = getValue(I.getOperand(1));
2195 SDValue FalseVal = getValue(I.getOperand(2));
2196
2197 for (unsigned i = 0; i != NumValues; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002198 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002199 TrueVal.getValueType(), Cond,
Dan Gohman7ea1ca62008-10-21 20:00:42 +00002200 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2201 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2202
Dale Johannesen66978ee2009-01-31 02:22:37 +00002203 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
Duncan Sandsaaffa052008-12-01 11:41:29 +00002204 DAG.getVTList(&ValueVTs[0], NumValues),
2205 &Values[0], NumValues));
Dan Gohman7ea1ca62008-10-21 20:00:42 +00002206 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002207}
2208
2209
2210void SelectionDAGLowering::visitTrunc(User &I) {
2211 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2212 SDValue N = getValue(I.getOperand(0));
2213 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002214 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002215}
2216
2217void SelectionDAGLowering::visitZExt(User &I) {
2218 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2219 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2220 SDValue N = getValue(I.getOperand(0));
2221 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002222 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002223}
2224
2225void SelectionDAGLowering::visitSExt(User &I) {
2226 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2227 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2228 SDValue N = getValue(I.getOperand(0));
2229 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002230 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002231}
2232
2233void SelectionDAGLowering::visitFPTrunc(User &I) {
2234 // FPTrunc is never a no-op cast, no need to check
2235 SDValue N = getValue(I.getOperand(0));
2236 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002237 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002238 DestVT, N, DAG.getIntPtrConstant(0)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002239}
2240
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002241void SelectionDAGLowering::visitFPExt(User &I){
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002242 // FPTrunc is never a no-op cast, no need to check
2243 SDValue N = getValue(I.getOperand(0));
2244 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002245 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002246}
2247
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002248void SelectionDAGLowering::visitFPToUI(User &I) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002249 // FPToUI is never a no-op cast, no need to check
2250 SDValue N = getValue(I.getOperand(0));
2251 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002252 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002253}
2254
2255void SelectionDAGLowering::visitFPToSI(User &I) {
2256 // FPToSI is never a no-op cast, no need to check
2257 SDValue N = getValue(I.getOperand(0));
2258 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002259 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002260}
2261
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002262void SelectionDAGLowering::visitUIToFP(User &I) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002263 // UIToFP is never a no-op cast, no need to check
2264 SDValue N = getValue(I.getOperand(0));
2265 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002266 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002267}
2268
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002269void SelectionDAGLowering::visitSIToFP(User &I){
Bill Wendling181b6272008-10-19 20:34:04 +00002270 // SIToFP is never a no-op cast, no need to check
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002271 SDValue N = getValue(I.getOperand(0));
2272 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002273 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002274}
2275
2276void SelectionDAGLowering::visitPtrToInt(User &I) {
2277 // What to do depends on the size of the integer and the size of the pointer.
2278 // We can either truncate, zero extend, or no-op, accordingly.
2279 SDValue N = getValue(I.getOperand(0));
2280 MVT SrcVT = N.getValueType();
2281 MVT DestVT = TLI.getValueType(I.getType());
2282 SDValue Result;
2283 if (DestVT.bitsLT(SrcVT))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002284 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002285 else
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002286 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
Dale Johannesen66978ee2009-01-31 02:22:37 +00002287 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002288 setValue(&I, Result);
2289}
2290
2291void SelectionDAGLowering::visitIntToPtr(User &I) {
2292 // What to do depends on the size of the integer and the size of the pointer.
2293 // We can either truncate, zero extend, or no-op, accordingly.
2294 SDValue N = getValue(I.getOperand(0));
2295 MVT SrcVT = N.getValueType();
2296 MVT DestVT = TLI.getValueType(I.getType());
2297 if (DestVT.bitsLT(SrcVT))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002298 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002299 else
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002300 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
Dale Johannesen66978ee2009-01-31 02:22:37 +00002301 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002302 DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002303}
2304
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002305void SelectionDAGLowering::visitBitCast(User &I) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002306 SDValue N = getValue(I.getOperand(0));
2307 MVT DestVT = TLI.getValueType(I.getType());
2308
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002309 // BitCast assures us that source and destination are the same size so this
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002310 // is either a BIT_CONVERT or a no-op.
2311 if (DestVT != N.getValueType())
Dale Johannesen66978ee2009-01-31 02:22:37 +00002312 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002313 DestVT, N)); // convert types
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002314 else
2315 setValue(&I, N); // noop cast.
2316}
2317
2318void SelectionDAGLowering::visitInsertElement(User &I) {
2319 SDValue InVec = getValue(I.getOperand(0));
2320 SDValue InVal = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002321 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002322 TLI.getPointerTy(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002323 getValue(I.getOperand(2)));
2324
Dale Johannesen66978ee2009-01-31 02:22:37 +00002325 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002326 TLI.getValueType(I.getType()),
2327 InVec, InVal, InIdx));
2328}
2329
2330void SelectionDAGLowering::visitExtractElement(User &I) {
2331 SDValue InVec = getValue(I.getOperand(0));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002332 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002333 TLI.getPointerTy(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002334 getValue(I.getOperand(1)));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002335 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002336 TLI.getValueType(I.getType()), InVec, InIdx));
2337}
2338
Mon P Wangaeb06d22008-11-10 04:46:22 +00002339
2340// Utility for visitShuffleVector - Returns true if the mask is mask starting
2341// from SIndx and increasing to the element length (undefs are allowed).
2342static bool SequentialMask(SDValue Mask, unsigned SIndx) {
Mon P Wangc7849c22008-11-16 05:06:27 +00002343 unsigned MaskNumElts = Mask.getNumOperands();
2344 for (unsigned i = 0; i != MaskNumElts; ++i) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002345 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2346 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2347 if (Idx != i + SIndx)
2348 return false;
2349 }
2350 }
2351 return true;
2352}
2353
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002354void SelectionDAGLowering::visitShuffleVector(User &I) {
Mon P Wang230e4fa2008-11-21 04:25:21 +00002355 SDValue Src1 = getValue(I.getOperand(0));
2356 SDValue Src2 = getValue(I.getOperand(1));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002357 SDValue Mask = getValue(I.getOperand(2));
2358
Mon P Wangaeb06d22008-11-10 04:46:22 +00002359 MVT VT = TLI.getValueType(I.getType());
Mon P Wang230e4fa2008-11-21 04:25:21 +00002360 MVT SrcVT = Src1.getValueType();
Mon P Wangc7849c22008-11-16 05:06:27 +00002361 int MaskNumElts = Mask.getNumOperands();
2362 int SrcNumElts = SrcVT.getVectorNumElements();
Mon P Wangaeb06d22008-11-10 04:46:22 +00002363
Mon P Wangc7849c22008-11-16 05:06:27 +00002364 if (SrcNumElts == MaskNumElts) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002365 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002366 VT, Src1, Src2, Mask));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002367 return;
2368 }
2369
2370 // Normalize the shuffle vector since mask and vector length don't match.
Mon P Wangc7849c22008-11-16 05:06:27 +00002371 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2372
2373 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2374 // Mask is longer than the source vectors and is a multiple of the source
2375 // vectors. We can use concatenate vector to make the mask and vectors
Mon P Wang230e4fa2008-11-21 04:25:21 +00002376 // lengths match.
Mon P Wangc7849c22008-11-16 05:06:27 +00002377 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2378 // The shuffle is concatenating two vectors together.
Dale Johannesen66978ee2009-01-31 02:22:37 +00002379 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002380 VT, Src1, Src2));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002381 return;
2382 }
2383
Mon P Wangc7849c22008-11-16 05:06:27 +00002384 // Pad both vectors with undefs to make them the same length as the mask.
2385 unsigned NumConcat = MaskNumElts / SrcNumElts;
Dale Johannesen66978ee2009-01-31 02:22:37 +00002386 SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT);
Mon P Wangaeb06d22008-11-10 04:46:22 +00002387
Mon P Wang230e4fa2008-11-21 04:25:21 +00002388 SDValue* MOps1 = new SDValue[NumConcat];
2389 SDValue* MOps2 = new SDValue[NumConcat];
2390 MOps1[0] = Src1;
2391 MOps2[0] = Src2;
Mon P Wangaeb06d22008-11-10 04:46:22 +00002392 for (unsigned i = 1; i != NumConcat; ++i) {
Mon P Wang230e4fa2008-11-21 04:25:21 +00002393 MOps1[i] = UndefVal;
2394 MOps2[i] = UndefVal;
Mon P Wangaeb06d22008-11-10 04:46:22 +00002395 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00002396 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002397 VT, MOps1, NumConcat);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002398 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002399 VT, MOps2, NumConcat);
Mon P Wang230e4fa2008-11-21 04:25:21 +00002400
2401 delete [] MOps1;
2402 delete [] MOps2;
2403
Mon P Wangaeb06d22008-11-10 04:46:22 +00002404 // Readjust mask for new input vector length.
2405 SmallVector<SDValue, 8> MappedOps;
Mon P Wangc7849c22008-11-16 05:06:27 +00002406 for (int i = 0; i != MaskNumElts; ++i) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002407 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2408 MappedOps.push_back(Mask.getOperand(i));
2409 } else {
Mon P Wangc7849c22008-11-16 05:06:27 +00002410 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2411 if (Idx < SrcNumElts)
2412 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2413 else
2414 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2415 MaskEltVT));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002416 }
2417 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00002418 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002419 Mask.getValueType(),
Mon P Wangaeb06d22008-11-10 04:46:22 +00002420 &MappedOps[0], MappedOps.size());
2421
Dale Johannesen66978ee2009-01-31 02:22:37 +00002422 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002423 VT, Src1, Src2, Mask));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002424 return;
2425 }
2426
Mon P Wangc7849c22008-11-16 05:06:27 +00002427 if (SrcNumElts > MaskNumElts) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002428 // Resulting vector is shorter than the incoming vector.
Mon P Wangc7849c22008-11-16 05:06:27 +00002429 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002430 // Shuffle extracts 1st vector.
Mon P Wang230e4fa2008-11-21 04:25:21 +00002431 setValue(&I, Src1);
Mon P Wangaeb06d22008-11-10 04:46:22 +00002432 return;
2433 }
2434
Mon P Wangc7849c22008-11-16 05:06:27 +00002435 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002436 // Shuffle extracts 2nd vector.
Mon P Wang230e4fa2008-11-21 04:25:21 +00002437 setValue(&I, Src2);
Mon P Wangaeb06d22008-11-10 04:46:22 +00002438 return;
2439 }
2440
Mon P Wangc7849c22008-11-16 05:06:27 +00002441 // Analyze the access pattern of the vector to see if we can extract
2442 // two subvectors and do the shuffle. The analysis is done by calculating
2443 // the range of elements the mask access on both vectors.
2444 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2445 int MaxRange[2] = {-1, -1};
2446
2447 for (int i = 0; i != MaskNumElts; ++i) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002448 SDValue Arg = Mask.getOperand(i);
2449 if (Arg.getOpcode() != ISD::UNDEF) {
2450 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Mon P Wangc7849c22008-11-16 05:06:27 +00002451 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2452 int Input = 0;
2453 if (Idx >= SrcNumElts) {
2454 Input = 1;
2455 Idx -= SrcNumElts;
2456 }
2457 if (Idx > MaxRange[Input])
2458 MaxRange[Input] = Idx;
2459 if (Idx < MinRange[Input])
2460 MinRange[Input] = Idx;
Mon P Wangaeb06d22008-11-10 04:46:22 +00002461 }
2462 }
Mon P Wangaeb06d22008-11-10 04:46:22 +00002463
Mon P Wangc7849c22008-11-16 05:06:27 +00002464 // Check if the access is smaller than the vector size and can we find
2465 // a reasonable extract index.
Mon P Wang230e4fa2008-11-21 04:25:21 +00002466 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
Mon P Wangc7849c22008-11-16 05:06:27 +00002467 int StartIdx[2]; // StartIdx to extract from
2468 for (int Input=0; Input < 2; ++Input) {
2469 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2470 RangeUse[Input] = 0; // Unused
2471 StartIdx[Input] = 0;
2472 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2473 // Fits within range but we should see if we can find a good
Mon P Wang230e4fa2008-11-21 04:25:21 +00002474 // start index that is a multiple of the mask length.
Mon P Wangc7849c22008-11-16 05:06:27 +00002475 if (MaxRange[Input] < MaskNumElts) {
2476 RangeUse[Input] = 1; // Extract from beginning of the vector
2477 StartIdx[Input] = 0;
2478 } else {
2479 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
Mon P Wang6cce3da2008-11-23 04:35:05 +00002480 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002481 StartIdx[Input] + MaskNumElts < SrcNumElts)
Mon P Wangc7849c22008-11-16 05:06:27 +00002482 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
Mon P Wangc7849c22008-11-16 05:06:27 +00002483 }
Mon P Wang230e4fa2008-11-21 04:25:21 +00002484 }
Mon P Wangc7849c22008-11-16 05:06:27 +00002485 }
2486
2487 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002488 setValue(&I, DAG.getNode(ISD::UNDEF,
Dale Johannesen66978ee2009-01-31 02:22:37 +00002489 getCurDebugLoc(), VT)); // Vectors are not used.
Mon P Wangc7849c22008-11-16 05:06:27 +00002490 return;
2491 }
2492 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2493 // Extract appropriate subvector and generate a vector shuffle
2494 for (int Input=0; Input < 2; ++Input) {
Mon P Wang230e4fa2008-11-21 04:25:21 +00002495 SDValue& Src = Input == 0 ? Src1 : Src2;
Mon P Wangc7849c22008-11-16 05:06:27 +00002496 if (RangeUse[Input] == 0) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002497 Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
Mon P Wangc7849c22008-11-16 05:06:27 +00002498 } else {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002499 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002500 Src, DAG.getIntPtrConstant(StartIdx[Input]));
Mon P Wangc7849c22008-11-16 05:06:27 +00002501 }
Mon P Wangaeb06d22008-11-10 04:46:22 +00002502 }
Mon P Wangc7849c22008-11-16 05:06:27 +00002503 // Calculate new mask.
2504 SmallVector<SDValue, 8> MappedOps;
2505 for (int i = 0; i != MaskNumElts; ++i) {
2506 SDValue Arg = Mask.getOperand(i);
2507 if (Arg.getOpcode() == ISD::UNDEF) {
2508 MappedOps.push_back(Arg);
2509 } else {
2510 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2511 if (Idx < SrcNumElts)
2512 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2513 else {
2514 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2515 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002516 }
Mon P Wangc7849c22008-11-16 05:06:27 +00002517 }
2518 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00002519 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002520 Mask.getValueType(),
Mon P Wangc7849c22008-11-16 05:06:27 +00002521 &MappedOps[0], MappedOps.size());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002522 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002523 VT, Src1, Src2, Mask));
Mon P Wangc7849c22008-11-16 05:06:27 +00002524 return;
Mon P Wangaeb06d22008-11-10 04:46:22 +00002525 }
2526 }
2527
Mon P Wangc7849c22008-11-16 05:06:27 +00002528 // We can't use either concat vectors or extract subvectors so fall back to
2529 // replacing the shuffle with extract and build vector.
2530 // to insert and build vector.
Mon P Wangaeb06d22008-11-10 04:46:22 +00002531 MVT EltVT = VT.getVectorElementType();
2532 MVT PtrVT = TLI.getPointerTy();
2533 SmallVector<SDValue,8> Ops;
Mon P Wangc7849c22008-11-16 05:06:27 +00002534 for (int i = 0; i != MaskNumElts; ++i) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002535 SDValue Arg = Mask.getOperand(i);
2536 if (Arg.getOpcode() == ISD::UNDEF) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002537 Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002538 } else {
2539 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Mon P Wangc7849c22008-11-16 05:06:27 +00002540 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2541 if (Idx < SrcNumElts)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002542 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002543 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002544 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00002545 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002546 EltVT, Src2,
Mon P Wangc7849c22008-11-16 05:06:27 +00002547 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002548 }
2549 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00002550 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002551 VT, &Ops[0], Ops.size()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002552}
2553
2554void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2555 const Value *Op0 = I.getOperand(0);
2556 const Value *Op1 = I.getOperand(1);
2557 const Type *AggTy = I.getType();
2558 const Type *ValTy = Op1->getType();
2559 bool IntoUndef = isa<UndefValue>(Op0);
2560 bool FromUndef = isa<UndefValue>(Op1);
2561
2562 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2563 I.idx_begin(), I.idx_end());
2564
2565 SmallVector<MVT, 4> AggValueVTs;
2566 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2567 SmallVector<MVT, 4> ValValueVTs;
2568 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2569
2570 unsigned NumAggValues = AggValueVTs.size();
2571 unsigned NumValValues = ValValueVTs.size();
2572 SmallVector<SDValue, 4> Values(NumAggValues);
2573
2574 SDValue Agg = getValue(Op0);
2575 SDValue Val = getValue(Op1);
2576 unsigned i = 0;
2577 // Copy the beginning value(s) from the original aggregate.
2578 for (; i != LinearIndex; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002579 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002580 AggValueVTs[i]) :
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002581 SDValue(Agg.getNode(), Agg.getResNo() + i);
2582 // Copy values from the inserted value(s).
2583 for (; i != LinearIndex + NumValValues; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002584 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002585 AggValueVTs[i]) :
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002586 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2587 // Copy remaining value(s) from the original aggregate.
2588 for (; i != NumAggValues; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002589 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002590 AggValueVTs[i]) :
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002591 SDValue(Agg.getNode(), Agg.getResNo() + i);
2592
Dale Johannesen66978ee2009-01-31 02:22:37 +00002593 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
Duncan Sandsaaffa052008-12-01 11:41:29 +00002594 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2595 &Values[0], NumAggValues));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002596}
2597
2598void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2599 const Value *Op0 = I.getOperand(0);
2600 const Type *AggTy = Op0->getType();
2601 const Type *ValTy = I.getType();
2602 bool OutOfUndef = isa<UndefValue>(Op0);
2603
2604 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2605 I.idx_begin(), I.idx_end());
2606
2607 SmallVector<MVT, 4> ValValueVTs;
2608 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2609
2610 unsigned NumValValues = ValValueVTs.size();
2611 SmallVector<SDValue, 4> Values(NumValValues);
2612
2613 SDValue Agg = getValue(Op0);
2614 // Copy out the selected value(s).
2615 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2616 Values[i - LinearIndex] =
Bill Wendlingf0a2d0c2008-11-20 07:24:30 +00002617 OutOfUndef ?
Dale Johannesen66978ee2009-01-31 02:22:37 +00002618 DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
Bill Wendlingf0a2d0c2008-11-20 07:24:30 +00002619 Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2620 SDValue(Agg.getNode(), Agg.getResNo() + i);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002621
Dale Johannesen66978ee2009-01-31 02:22:37 +00002622 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
Duncan Sandsaaffa052008-12-01 11:41:29 +00002623 DAG.getVTList(&ValValueVTs[0], NumValValues),
2624 &Values[0], NumValValues));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002625}
2626
2627
2628void SelectionDAGLowering::visitGetElementPtr(User &I) {
2629 SDValue N = getValue(I.getOperand(0));
2630 const Type *Ty = I.getOperand(0)->getType();
2631
2632 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2633 OI != E; ++OI) {
2634 Value *Idx = *OI;
2635 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2636 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2637 if (Field) {
2638 // N = N + Offset
2639 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002640 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002641 DAG.getIntPtrConstant(Offset));
2642 }
2643 Ty = StTy->getElementType(Field);
2644 } else {
2645 Ty = cast<SequentialType>(Ty)->getElementType();
2646
2647 // If this is a constant subscript, handle it quickly.
2648 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2649 if (CI->getZExtValue() == 0) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002650 uint64_t Offs =
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00002651 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
Dale Johannesen66978ee2009-01-31 02:22:37 +00002652 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002653 DAG.getIntPtrConstant(Offs));
2654 continue;
2655 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002656
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002657 // N = N + Idx * ElementSize;
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00002658 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002659 SDValue IdxN = getValue(Idx);
2660
2661 // If the index is smaller or larger than intptr_t, truncate or extend
2662 // it.
2663 if (IdxN.getValueType().bitsLT(N.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002664 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002665 N.getValueType(), IdxN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002666 else if (IdxN.getValueType().bitsGT(N.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002667 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002668 N.getValueType(), IdxN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002669
2670 // If this is a multiply by a power of two, turn it into a shl
2671 // immediately. This is a very common case.
2672 if (ElementSize != 1) {
2673 if (isPowerOf2_64(ElementSize)) {
2674 unsigned Amt = Log2_64(ElementSize);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002675 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002676 N.getValueType(), IdxN,
Duncan Sands92abc622009-01-31 15:50:11 +00002677 DAG.getConstant(Amt, TLI.getPointerTy()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002678 } else {
2679 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002680 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002681 N.getValueType(), IdxN, Scale);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002682 }
2683 }
2684
Dale Johannesen66978ee2009-01-31 02:22:37 +00002685 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002686 N.getValueType(), N, IdxN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002687 }
2688 }
2689 setValue(&I, N);
2690}
2691
2692void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2693 // If this is a fixed sized alloca in the entry block of the function,
2694 // allocate it statically on the stack.
2695 if (FuncInfo.StaticAllocaMap.count(&I))
2696 return; // getValue will auto-populate this.
2697
2698 const Type *Ty = I.getAllocatedType();
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00002699 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002700 unsigned Align =
2701 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2702 I.getAlignment());
2703
2704 SDValue AllocSize = getValue(I.getArraySize());
2705 MVT IntPtr = TLI.getPointerTy();
2706 if (IntPtr.bitsLT(AllocSize.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002707 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002708 IntPtr, AllocSize);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002709 else if (IntPtr.bitsGT(AllocSize.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002710 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002711 IntPtr, AllocSize);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002712
Dale Johannesen66978ee2009-01-31 02:22:37 +00002713 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002714 DAG.getIntPtrConstant(TySize));
2715
2716 // Handle alignment. If the requested alignment is less than or equal to
2717 // the stack alignment, ignore it. If the size is greater than or equal to
2718 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2719 unsigned StackAlign =
2720 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2721 if (Align <= StackAlign)
2722 Align = 0;
2723
2724 // Round the size of the allocation up to the stack alignment size
2725 // by add SA-1 to the size.
Dale Johannesen66978ee2009-01-31 02:22:37 +00002726 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002727 AllocSize.getValueType(), AllocSize,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002728 DAG.getIntPtrConstant(StackAlign-1));
2729 // Mask out the low bits for alignment purposes.
Dale Johannesen66978ee2009-01-31 02:22:37 +00002730 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002731 AllocSize.getValueType(), AllocSize,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002732 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2733
2734 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2735 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2736 MVT::Other);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002737 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002738 VTs, 2, Ops, 3);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002739 setValue(&I, DSA);
2740 DAG.setRoot(DSA.getValue(1));
2741
2742 // Inform the Frame Information that we have just allocated a variable-sized
2743 // object.
2744 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2745}
2746
2747void SelectionDAGLowering::visitLoad(LoadInst &I) {
2748 const Value *SV = I.getOperand(0);
2749 SDValue Ptr = getValue(SV);
2750
2751 const Type *Ty = I.getType();
2752 bool isVolatile = I.isVolatile();
2753 unsigned Alignment = I.getAlignment();
2754
2755 SmallVector<MVT, 4> ValueVTs;
2756 SmallVector<uint64_t, 4> Offsets;
2757 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2758 unsigned NumValues = ValueVTs.size();
2759 if (NumValues == 0)
2760 return;
2761
2762 SDValue Root;
2763 bool ConstantMemory = false;
2764 if (I.isVolatile())
2765 // Serialize volatile loads with other side effects.
2766 Root = getRoot();
2767 else if (AA->pointsToConstantMemory(SV)) {
2768 // Do not serialize (non-volatile) loads of constant memory with anything.
2769 Root = DAG.getEntryNode();
2770 ConstantMemory = true;
2771 } else {
2772 // Do not serialize non-volatile loads against each other.
2773 Root = DAG.getRoot();
2774 }
2775
2776 SmallVector<SDValue, 4> Values(NumValues);
2777 SmallVector<SDValue, 4> Chains(NumValues);
2778 MVT PtrVT = Ptr.getValueType();
2779 for (unsigned i = 0; i != NumValues; ++i) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002780 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2781 DAG.getNode(ISD::ADD, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002782 PtrVT, Ptr,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002783 DAG.getConstant(Offsets[i], PtrVT)),
2784 SV, Offsets[i],
2785 isVolatile, Alignment);
2786 Values[i] = L;
2787 Chains[i] = L.getValue(1);
2788 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002789
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002790 if (!ConstantMemory) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002791 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002792 MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002793 &Chains[0], NumValues);
2794 if (isVolatile)
2795 DAG.setRoot(Chain);
2796 else
2797 PendingLoads.push_back(Chain);
2798 }
2799
Dale Johannesen66978ee2009-01-31 02:22:37 +00002800 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
Duncan Sandsaaffa052008-12-01 11:41:29 +00002801 DAG.getVTList(&ValueVTs[0], NumValues),
2802 &Values[0], NumValues));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002803}
2804
2805
2806void SelectionDAGLowering::visitStore(StoreInst &I) {
2807 Value *SrcV = I.getOperand(0);
2808 Value *PtrV = I.getOperand(1);
2809
2810 SmallVector<MVT, 4> ValueVTs;
2811 SmallVector<uint64_t, 4> Offsets;
2812 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2813 unsigned NumValues = ValueVTs.size();
2814 if (NumValues == 0)
2815 return;
2816
2817 // Get the lowered operands. Note that we do this after
2818 // checking if NumResults is zero, because with zero results
2819 // the operands won't have values in the map.
2820 SDValue Src = getValue(SrcV);
2821 SDValue Ptr = getValue(PtrV);
2822
2823 SDValue Root = getRoot();
2824 SmallVector<SDValue, 4> Chains(NumValues);
2825 MVT PtrVT = Ptr.getValueType();
2826 bool isVolatile = I.isVolatile();
2827 unsigned Alignment = I.getAlignment();
2828 for (unsigned i = 0; i != NumValues; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002829 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002830 SDValue(Src.getNode(), Src.getResNo() + i),
Dale Johannesen66978ee2009-01-31 02:22:37 +00002831 DAG.getNode(ISD::ADD, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002832 PtrVT, Ptr,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002833 DAG.getConstant(Offsets[i], PtrVT)),
2834 PtrV, Offsets[i],
2835 isVolatile, Alignment);
2836
Dale Johannesen66978ee2009-01-31 02:22:37 +00002837 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002838 MVT::Other, &Chains[0], NumValues));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002839}
2840
2841/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2842/// node.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002843void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002844 unsigned Intrinsic) {
2845 bool HasChain = !I.doesNotAccessMemory();
2846 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2847
2848 // Build the operand list.
2849 SmallVector<SDValue, 8> Ops;
2850 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2851 if (OnlyLoad) {
2852 // We don't need to serialize loads against other loads.
2853 Ops.push_back(DAG.getRoot());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002854 } else {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002855 Ops.push_back(getRoot());
2856 }
2857 }
Mon P Wang3efcd4a2008-11-01 20:24:53 +00002858
2859 // Info is set by getTgtMemInstrinsic
2860 TargetLowering::IntrinsicInfo Info;
2861 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2862
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002863 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
Mon P Wang3efcd4a2008-11-01 20:24:53 +00002864 if (!IsTgtIntrinsic)
2865 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002866
2867 // Add all operands of the call to the operand list.
2868 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2869 SDValue Op = getValue(I.getOperand(i));
2870 assert(TLI.isTypeLegal(Op.getValueType()) &&
2871 "Intrinsic uses a non-legal type?");
2872 Ops.push_back(Op);
2873 }
2874
2875 std::vector<MVT> VTs;
2876 if (I.getType() != Type::VoidTy) {
2877 MVT VT = TLI.getValueType(I.getType());
2878 if (VT.isVector()) {
2879 const VectorType *DestTy = cast<VectorType>(I.getType());
2880 MVT EltVT = TLI.getValueType(DestTy->getElementType());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002881
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002882 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2883 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2884 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002885
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002886 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2887 VTs.push_back(VT);
2888 }
2889 if (HasChain)
2890 VTs.push_back(MVT::Other);
2891
2892 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2893
2894 // Create the node.
2895 SDValue Result;
Mon P Wang3efcd4a2008-11-01 20:24:53 +00002896 if (IsTgtIntrinsic) {
2897 // This is target intrinsic that touches memory
Dale Johannesen66978ee2009-01-31 02:22:37 +00002898 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002899 VTList, VTs.size(),
Mon P Wang3efcd4a2008-11-01 20:24:53 +00002900 &Ops[0], Ops.size(),
2901 Info.memVT, Info.ptrVal, Info.offset,
2902 Info.align, Info.vol,
2903 Info.readMem, Info.writeMem);
2904 }
2905 else if (!HasChain)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002906 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002907 VTList, VTs.size(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002908 &Ops[0], Ops.size());
2909 else if (I.getType() != Type::VoidTy)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002910 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002911 VTList, VTs.size(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002912 &Ops[0], Ops.size());
2913 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00002914 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002915 VTList, VTs.size(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002916 &Ops[0], Ops.size());
2917
2918 if (HasChain) {
2919 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2920 if (OnlyLoad)
2921 PendingLoads.push_back(Chain);
2922 else
2923 DAG.setRoot(Chain);
2924 }
2925 if (I.getType() != Type::VoidTy) {
2926 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2927 MVT VT = TLI.getValueType(PTy);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002928 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002929 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002930 setValue(&I, Result);
2931 }
2932}
2933
2934/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2935static GlobalVariable *ExtractTypeInfo(Value *V) {
2936 V = V->stripPointerCasts();
2937 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2938 assert ((GV || isa<ConstantPointerNull>(V)) &&
2939 "TypeInfo must be a global variable or NULL");
2940 return GV;
2941}
2942
2943namespace llvm {
2944
2945/// AddCatchInfo - Extract the personality and type infos from an eh.selector
2946/// call, and add them to the specified machine basic block.
2947void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2948 MachineBasicBlock *MBB) {
2949 // Inform the MachineModuleInfo of the personality for this landing pad.
2950 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2951 assert(CE->getOpcode() == Instruction::BitCast &&
2952 isa<Function>(CE->getOperand(0)) &&
2953 "Personality should be a function");
2954 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2955
2956 // Gather all the type infos for this landing pad and pass them along to
2957 // MachineModuleInfo.
2958 std::vector<GlobalVariable *> TyInfo;
2959 unsigned N = I.getNumOperands();
2960
2961 for (unsigned i = N - 1; i > 2; --i) {
2962 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2963 unsigned FilterLength = CI->getZExtValue();
2964 unsigned FirstCatch = i + FilterLength + !FilterLength;
2965 assert (FirstCatch <= N && "Invalid filter length");
2966
2967 if (FirstCatch < N) {
2968 TyInfo.reserve(N - FirstCatch);
2969 for (unsigned j = FirstCatch; j < N; ++j)
2970 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2971 MMI->addCatchTypeInfo(MBB, TyInfo);
2972 TyInfo.clear();
2973 }
2974
2975 if (!FilterLength) {
2976 // Cleanup.
2977 MMI->addCleanup(MBB);
2978 } else {
2979 // Filter.
2980 TyInfo.reserve(FilterLength - 1);
2981 for (unsigned j = i + 1; j < FirstCatch; ++j)
2982 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2983 MMI->addFilterTypeInfo(MBB, TyInfo);
2984 TyInfo.clear();
2985 }
2986
2987 N = i;
2988 }
2989 }
2990
2991 if (N > 3) {
2992 TyInfo.reserve(N - 3);
2993 for (unsigned j = 3; j < N; ++j)
2994 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2995 MMI->addCatchTypeInfo(MBB, TyInfo);
2996 }
2997}
2998
2999}
3000
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003001/// GetSignificand - Get the significand and build it into a floating-point
3002/// number with exponent of 1:
3003///
3004/// Op = (Op & 0x007fffff) | 0x3f800000;
3005///
3006/// where Op is the hexidecimal representation of floating point value.
Bill Wendling39150252008-09-09 20:39:27 +00003007static SDValue
Dale Johannesen66978ee2009-01-31 02:22:37 +00003008GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3009 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
Bill Wendlinge9a72862009-01-20 21:17:57 +00003010 DAG.getConstant(0x007fffff, MVT::i32));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003011 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
Bill Wendlinge9a72862009-01-20 21:17:57 +00003012 DAG.getConstant(0x3f800000, MVT::i32));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003013 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
Bill Wendling39150252008-09-09 20:39:27 +00003014}
3015
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003016/// GetExponent - Get the exponent:
3017///
Bill Wendlinge9a72862009-01-20 21:17:57 +00003018/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003019///
3020/// where Op is the hexidecimal representation of floating point value.
Bill Wendling39150252008-09-09 20:39:27 +00003021static SDValue
Dale Johannesen66978ee2009-01-31 02:22:37 +00003022GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3023 DebugLoc dl) {
3024 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
Bill Wendlinge9a72862009-01-20 21:17:57 +00003025 DAG.getConstant(0x7f800000, MVT::i32));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003026 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
Duncan Sands92abc622009-01-31 15:50:11 +00003027 DAG.getConstant(23, TLI.getPointerTy()));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003028 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
Bill Wendlinge9a72862009-01-20 21:17:57 +00003029 DAG.getConstant(127, MVT::i32));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003030 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
Bill Wendling39150252008-09-09 20:39:27 +00003031}
3032
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003033/// getF32Constant - Get 32-bit floating point constant.
3034static SDValue
3035getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3036 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3037}
3038
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003039/// Inlined utility function to implement binary input atomic intrinsics for
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003040/// visitIntrinsicCall: I is a call instruction
3041/// Op is the associated NodeType for I
3042const char *
3043SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003044 SDValue Root = getRoot();
Dan Gohman0b1d4a72008-12-23 21:37:04 +00003045 SDValue L =
Dale Johannesen66978ee2009-01-31 02:22:37 +00003046 DAG.getAtomic(Op, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003047 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
Dan Gohman0b1d4a72008-12-23 21:37:04 +00003048 Root,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003049 getValue(I.getOperand(1)),
Dan Gohman0b1d4a72008-12-23 21:37:04 +00003050 getValue(I.getOperand(2)),
3051 I.getOperand(1));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003052 setValue(&I, L);
3053 DAG.setRoot(L.getValue(1));
3054 return 0;
3055}
3056
Bill Wendling2ce4e5c2008-12-10 00:28:22 +00003057// implVisitAluOverflow - Lower arithmetic overflow instrinsics.
Bill Wendling74c37652008-12-09 22:08:41 +00003058const char *
3059SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
Bill Wendling2ce4e5c2008-12-10 00:28:22 +00003060 SDValue Op1 = getValue(I.getOperand(1));
3061 SDValue Op2 = getValue(I.getOperand(2));
Bill Wendling74c37652008-12-09 22:08:41 +00003062
Bill Wendling2ce4e5c2008-12-10 00:28:22 +00003063 MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
3064 SDValue Ops[] = { Op1, Op2 };
Bill Wendling74c37652008-12-09 22:08:41 +00003065
Dale Johannesen66978ee2009-01-31 02:22:37 +00003066 SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003067 DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
Bill Wendling74c37652008-12-09 22:08:41 +00003068
Bill Wendling2ce4e5c2008-12-10 00:28:22 +00003069 setValue(&I, Result);
3070 return 0;
3071}
Bill Wendling74c37652008-12-09 22:08:41 +00003072
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003073/// visitExp - Lower an exp intrinsic. Handles the special sequences for
3074/// limited-precision mode.
Dale Johannesen59e577f2008-09-05 18:38:42 +00003075void
3076SelectionDAGLowering::visitExp(CallInst &I) {
3077 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003078 DebugLoc dl = getCurDebugLoc();
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003079
3080 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3081 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3082 SDValue Op = getValue(I.getOperand(1));
3083
3084 // Put the exponent in the right bit position for later addition to the
3085 // final result:
3086 //
3087 // #define LOG2OFe 1.4426950f
3088 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003089 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003090 getF32Constant(DAG, 0x3fb8aa3b));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003091 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003092
3093 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003094 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3095 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003096
3097 // IntegerPartOfX <<= 23;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003098 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
Duncan Sands92abc622009-01-31 15:50:11 +00003099 DAG.getConstant(23, TLI.getPointerTy()));
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003100
3101 if (LimitFloatPrecision <= 6) {
3102 // For floating-point precision of 6:
3103 //
3104 // TwoToFractionalPartOfX =
3105 // 0.997535578f +
3106 // (0.735607626f + 0.252464424f * x) * x;
3107 //
3108 // error 0.0144103317, which is 6 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003109 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003110 getF32Constant(DAG, 0x3e814304));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003111 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003112 getF32Constant(DAG, 0x3f3c50c8));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003113 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3114 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003115 getF32Constant(DAG, 0x3f7f5e7e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003116 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003117
3118 // Add the exponent into the result in integer domain.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003119 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003120 TwoToFracPartOfX, IntegerPartOfX);
3121
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003122 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003123 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3124 // For floating-point precision of 12:
3125 //
3126 // TwoToFractionalPartOfX =
3127 // 0.999892986f +
3128 // (0.696457318f +
3129 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3130 //
3131 // 0.000107046256 error, which is 13 to 14 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003132 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003133 getF32Constant(DAG, 0x3da235e3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003134 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003135 getF32Constant(DAG, 0x3e65b8f3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003136 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3137 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003138 getF32Constant(DAG, 0x3f324b07));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003139 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3140 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003141 getF32Constant(DAG, 0x3f7ff8fd));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003142 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003143
3144 // Add the exponent into the result in integer domain.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003145 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003146 TwoToFracPartOfX, IntegerPartOfX);
3147
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003148 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003149 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3150 // For floating-point precision of 18:
3151 //
3152 // TwoToFractionalPartOfX =
3153 // 0.999999982f +
3154 // (0.693148872f +
3155 // (0.240227044f +
3156 // (0.554906021e-1f +
3157 // (0.961591928e-2f +
3158 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3159 //
3160 // error 2.47208000*10^(-7), which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003161 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003162 getF32Constant(DAG, 0x3924b03e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003163 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003164 getF32Constant(DAG, 0x3ab24b87));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003165 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3166 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003167 getF32Constant(DAG, 0x3c1d8c17));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003168 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3169 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003170 getF32Constant(DAG, 0x3d634a1d));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003171 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3172 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003173 getF32Constant(DAG, 0x3e75fe14));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003174 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3175 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003176 getF32Constant(DAG, 0x3f317234));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003177 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3178 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003179 getF32Constant(DAG, 0x3f800000));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003180 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3181 MVT::i32, t13);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003182
3183 // Add the exponent into the result in integer domain.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003184 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003185 TwoToFracPartOfX, IntegerPartOfX);
3186
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003187 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003188 }
3189 } else {
3190 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003191 result = DAG.getNode(ISD::FEXP, dl,
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003192 getValue(I.getOperand(1)).getValueType(),
3193 getValue(I.getOperand(1)));
3194 }
3195
Dale Johannesen59e577f2008-09-05 18:38:42 +00003196 setValue(&I, result);
3197}
3198
Bill Wendling39150252008-09-09 20:39:27 +00003199/// visitLog - Lower a log intrinsic. Handles the special sequences for
3200/// limited-precision mode.
Dale Johannesen59e577f2008-09-05 18:38:42 +00003201void
3202SelectionDAGLowering::visitLog(CallInst &I) {
3203 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003204 DebugLoc dl = getCurDebugLoc();
Bill Wendling39150252008-09-09 20:39:27 +00003205
3206 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3207 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3208 SDValue Op = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003209 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
Bill Wendling39150252008-09-09 20:39:27 +00003210
3211 // Scale the exponent by log(2) [0.69314718f].
Dale Johannesen66978ee2009-01-31 02:22:37 +00003212 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003213 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003214 getF32Constant(DAG, 0x3f317218));
Bill Wendling39150252008-09-09 20:39:27 +00003215
3216 // Get the significand and build it into a floating-point number with
3217 // exponent of 1.
Dale Johannesen66978ee2009-01-31 02:22:37 +00003218 SDValue X = GetSignificand(DAG, Op1, dl);
Bill Wendling39150252008-09-09 20:39:27 +00003219
3220 if (LimitFloatPrecision <= 6) {
3221 // For floating-point precision of 6:
3222 //
3223 // LogofMantissa =
3224 // -1.1609546f +
3225 // (1.4034025f - 0.23903021f * x) * x;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003226 //
Bill Wendling39150252008-09-09 20:39:27 +00003227 // error 0.0034276066, which is better than 8 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003228 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003229 getF32Constant(DAG, 0xbe74c456));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003230 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003231 getF32Constant(DAG, 0x3fb3a2b1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003232 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3233 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003234 getF32Constant(DAG, 0x3f949a29));
Bill Wendling39150252008-09-09 20:39:27 +00003235
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003236 result = DAG.getNode(ISD::FADD, dl,
3237 MVT::f32, LogOfExponent, LogOfMantissa);
Bill Wendling39150252008-09-09 20:39:27 +00003238 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3239 // For floating-point precision of 12:
3240 //
3241 // LogOfMantissa =
3242 // -1.7417939f +
3243 // (2.8212026f +
3244 // (-1.4699568f +
3245 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3246 //
3247 // error 0.000061011436, which is 14 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003248 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003249 getF32Constant(DAG, 0xbd67b6d6));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003250 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003251 getF32Constant(DAG, 0x3ee4f4b8));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3253 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003254 getF32Constant(DAG, 0x3fbc278b));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3256 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003257 getF32Constant(DAG, 0x40348e95));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003258 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3259 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003260 getF32Constant(DAG, 0x3fdef31a));
Bill Wendling39150252008-09-09 20:39:27 +00003261
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003262 result = DAG.getNode(ISD::FADD, dl,
3263 MVT::f32, LogOfExponent, LogOfMantissa);
Bill Wendling39150252008-09-09 20:39:27 +00003264 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3265 // For floating-point precision of 18:
3266 //
3267 // LogOfMantissa =
3268 // -2.1072184f +
3269 // (4.2372794f +
3270 // (-3.7029485f +
3271 // (2.2781945f +
3272 // (-0.87823314f +
3273 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3274 //
3275 // error 0.0000023660568, which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003276 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003277 getF32Constant(DAG, 0xbc91e5ac));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003278 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003279 getF32Constant(DAG, 0x3e4350aa));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003280 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3281 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003282 getF32Constant(DAG, 0x3f60d3e3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003283 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3284 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003285 getF32Constant(DAG, 0x4011cdf0));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003286 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3287 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003288 getF32Constant(DAG, 0x406cfd1c));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003289 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3290 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003291 getF32Constant(DAG, 0x408797cb));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003292 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3293 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003294 getF32Constant(DAG, 0x4006dcab));
Bill Wendling39150252008-09-09 20:39:27 +00003295
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003296 result = DAG.getNode(ISD::FADD, dl,
3297 MVT::f32, LogOfExponent, LogOfMantissa);
Bill Wendling39150252008-09-09 20:39:27 +00003298 }
3299 } else {
3300 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003301 result = DAG.getNode(ISD::FLOG, dl,
Bill Wendling39150252008-09-09 20:39:27 +00003302 getValue(I.getOperand(1)).getValueType(),
3303 getValue(I.getOperand(1)));
3304 }
3305
Dale Johannesen59e577f2008-09-05 18:38:42 +00003306 setValue(&I, result);
3307}
3308
Bill Wendling3eb59402008-09-09 00:28:24 +00003309/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3310/// limited-precision mode.
Dale Johannesen59e577f2008-09-05 18:38:42 +00003311void
3312SelectionDAGLowering::visitLog2(CallInst &I) {
3313 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003314 DebugLoc dl = getCurDebugLoc();
Bill Wendling3eb59402008-09-09 00:28:24 +00003315
Dale Johannesen853244f2008-09-05 23:49:37 +00003316 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
Bill Wendling3eb59402008-09-09 00:28:24 +00003317 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3318 SDValue Op = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003319 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
Bill Wendling3eb59402008-09-09 00:28:24 +00003320
Bill Wendling39150252008-09-09 20:39:27 +00003321 // Get the exponent.
Dale Johannesen66978ee2009-01-31 02:22:37 +00003322 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
Bill Wendling3eb59402008-09-09 00:28:24 +00003323
3324 // Get the significand and build it into a floating-point number with
Bill Wendling39150252008-09-09 20:39:27 +00003325 // exponent of 1.
Dale Johannesen66978ee2009-01-31 02:22:37 +00003326 SDValue X = GetSignificand(DAG, Op1, dl);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003327
Bill Wendling3eb59402008-09-09 00:28:24 +00003328 // Different possible minimax approximations of significand in
3329 // floating-point for various degrees of accuracy over [1,2].
3330 if (LimitFloatPrecision <= 6) {
3331 // For floating-point precision of 6:
3332 //
3333 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3334 //
3335 // error 0.0049451742, which is more than 7 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003336 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003337 getF32Constant(DAG, 0xbeb08fe0));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003338 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003339 getF32Constant(DAG, 0x40019463));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003340 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3341 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003342 getF32Constant(DAG, 0x3fd6633d));
Bill Wendling3eb59402008-09-09 00:28:24 +00003343
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003344 result = DAG.getNode(ISD::FADD, dl,
3345 MVT::f32, LogOfExponent, Log2ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003346 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3347 // For floating-point precision of 12:
3348 //
3349 // Log2ofMantissa =
3350 // -2.51285454f +
3351 // (4.07009056f +
3352 // (-2.12067489f +
3353 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003354 //
Bill Wendling3eb59402008-09-09 00:28:24 +00003355 // error 0.0000876136000, which is better than 13 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003356 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003357 getF32Constant(DAG, 0xbda7262e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003358 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003359 getF32Constant(DAG, 0x3f25280b));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003360 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3361 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003362 getF32Constant(DAG, 0x4007b923));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003363 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3364 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003365 getF32Constant(DAG, 0x40823e2f));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003366 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3367 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003368 getF32Constant(DAG, 0x4020d29c));
Bill Wendling3eb59402008-09-09 00:28:24 +00003369
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003370 result = DAG.getNode(ISD::FADD, dl,
3371 MVT::f32, LogOfExponent, Log2ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003372 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3373 // For floating-point precision of 18:
3374 //
3375 // Log2ofMantissa =
3376 // -3.0400495f +
3377 // (6.1129976f +
3378 // (-5.3420409f +
3379 // (3.2865683f +
3380 // (-1.2669343f +
3381 // (0.27515199f -
3382 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3383 //
3384 // error 0.0000018516, which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003385 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003386 getF32Constant(DAG, 0xbcd2769e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003387 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003388 getF32Constant(DAG, 0x3e8ce0b9));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003389 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3390 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003391 getF32Constant(DAG, 0x3fa22ae7));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003392 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3393 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003394 getF32Constant(DAG, 0x40525723));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003395 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3396 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003397 getF32Constant(DAG, 0x40aaf200));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003398 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3399 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003400 getF32Constant(DAG, 0x40c39dad));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003401 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3402 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003403 getF32Constant(DAG, 0x4042902c));
Bill Wendling3eb59402008-09-09 00:28:24 +00003404
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003405 result = DAG.getNode(ISD::FADD, dl,
3406 MVT::f32, LogOfExponent, Log2ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003407 }
Dale Johannesen853244f2008-09-05 23:49:37 +00003408 } else {
Bill Wendling3eb59402008-09-09 00:28:24 +00003409 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003410 result = DAG.getNode(ISD::FLOG2, dl,
Dale Johannesen853244f2008-09-05 23:49:37 +00003411 getValue(I.getOperand(1)).getValueType(),
3412 getValue(I.getOperand(1)));
3413 }
Bill Wendling3eb59402008-09-09 00:28:24 +00003414
Dale Johannesen59e577f2008-09-05 18:38:42 +00003415 setValue(&I, result);
3416}
3417
Bill Wendling3eb59402008-09-09 00:28:24 +00003418/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3419/// limited-precision mode.
Dale Johannesen59e577f2008-09-05 18:38:42 +00003420void
3421SelectionDAGLowering::visitLog10(CallInst &I) {
3422 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003423 DebugLoc dl = getCurDebugLoc();
Bill Wendling181b6272008-10-19 20:34:04 +00003424
Dale Johannesen852680a2008-09-05 21:27:19 +00003425 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
Bill Wendling3eb59402008-09-09 00:28:24 +00003426 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3427 SDValue Op = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003428 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
Bill Wendling3eb59402008-09-09 00:28:24 +00003429
Bill Wendling39150252008-09-09 20:39:27 +00003430 // Scale the exponent by log10(2) [0.30102999f].
Dale Johannesen66978ee2009-01-31 02:22:37 +00003431 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003432 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003433 getF32Constant(DAG, 0x3e9a209a));
Bill Wendling3eb59402008-09-09 00:28:24 +00003434
3435 // Get the significand and build it into a floating-point number with
Bill Wendling39150252008-09-09 20:39:27 +00003436 // exponent of 1.
Dale Johannesen66978ee2009-01-31 02:22:37 +00003437 SDValue X = GetSignificand(DAG, Op1, dl);
Bill Wendling3eb59402008-09-09 00:28:24 +00003438
3439 if (LimitFloatPrecision <= 6) {
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003440 // For floating-point precision of 6:
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003441 //
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003442 // Log10ofMantissa =
3443 // -0.50419619f +
3444 // (0.60948995f - 0.10380950f * x) * x;
3445 //
3446 // error 0.0014886165, which is 6 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003447 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003448 getF32Constant(DAG, 0xbdd49a13));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003449 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003450 getF32Constant(DAG, 0x3f1c0789));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003451 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3452 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003453 getF32Constant(DAG, 0x3f011300));
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003454
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003455 result = DAG.getNode(ISD::FADD, dl,
3456 MVT::f32, LogOfExponent, Log10ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003457 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3458 // For floating-point precision of 12:
3459 //
3460 // Log10ofMantissa =
3461 // -0.64831180f +
3462 // (0.91751397f +
3463 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3464 //
3465 // error 0.00019228036, which is better than 12 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003466 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003467 getF32Constant(DAG, 0x3d431f31));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003468 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003469 getF32Constant(DAG, 0x3ea21fb2));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003470 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3471 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003472 getF32Constant(DAG, 0x3f6ae232));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003473 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3474 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003475 getF32Constant(DAG, 0x3f25f7c3));
Bill Wendling3eb59402008-09-09 00:28:24 +00003476
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003477 result = DAG.getNode(ISD::FADD, dl,
3478 MVT::f32, LogOfExponent, Log10ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003479 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003480 // For floating-point precision of 18:
3481 //
3482 // Log10ofMantissa =
3483 // -0.84299375f +
3484 // (1.5327582f +
3485 // (-1.0688956f +
3486 // (0.49102474f +
3487 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3488 //
3489 // error 0.0000037995730, which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003490 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003491 getF32Constant(DAG, 0x3c5d51ce));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003492 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003493 getF32Constant(DAG, 0x3e00685a));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003494 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3495 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003496 getF32Constant(DAG, 0x3efb6798));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003497 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3498 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003499 getF32Constant(DAG, 0x3f88d192));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003500 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3501 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003502 getF32Constant(DAG, 0x3fc4316c));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003503 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3504 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003505 getF32Constant(DAG, 0x3f57ce70));
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003506
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003507 result = DAG.getNode(ISD::FADD, dl,
3508 MVT::f32, LogOfExponent, Log10ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003509 }
Dale Johannesen852680a2008-09-05 21:27:19 +00003510 } else {
Bill Wendling3eb59402008-09-09 00:28:24 +00003511 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003512 result = DAG.getNode(ISD::FLOG10, dl,
Dale Johannesen852680a2008-09-05 21:27:19 +00003513 getValue(I.getOperand(1)).getValueType(),
3514 getValue(I.getOperand(1)));
3515 }
Bill Wendling3eb59402008-09-09 00:28:24 +00003516
Dale Johannesen59e577f2008-09-05 18:38:42 +00003517 setValue(&I, result);
3518}
3519
Bill Wendlinge10c8142008-09-09 22:39:21 +00003520/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3521/// limited-precision mode.
Dale Johannesen601d3c02008-09-05 01:48:15 +00003522void
3523SelectionDAGLowering::visitExp2(CallInst &I) {
3524 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003525 DebugLoc dl = getCurDebugLoc();
Bill Wendlinge10c8142008-09-09 22:39:21 +00003526
Dale Johannesen601d3c02008-09-05 01:48:15 +00003527 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
Bill Wendlinge10c8142008-09-09 22:39:21 +00003528 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3529 SDValue Op = getValue(I.getOperand(1));
3530
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003531 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003532
3533 // FractionalPartOfX = x - (float)IntegerPartOfX;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003534 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3535 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003536
3537 // IntegerPartOfX <<= 23;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003538 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
Duncan Sands92abc622009-01-31 15:50:11 +00003539 DAG.getConstant(23, TLI.getPointerTy()));
Bill Wendlinge10c8142008-09-09 22:39:21 +00003540
3541 if (LimitFloatPrecision <= 6) {
3542 // For floating-point precision of 6:
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003543 //
Bill Wendlinge10c8142008-09-09 22:39:21 +00003544 // TwoToFractionalPartOfX =
3545 // 0.997535578f +
3546 // (0.735607626f + 0.252464424f * x) * x;
3547 //
3548 // error 0.0144103317, which is 6 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003549 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003550 getF32Constant(DAG, 0x3e814304));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003551 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003552 getF32Constant(DAG, 0x3f3c50c8));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003553 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3554 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003555 getF32Constant(DAG, 0x3f7f5e7e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003556 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003557 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003558 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003559
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003560 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3561 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003562 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3563 // For floating-point precision of 12:
3564 //
3565 // TwoToFractionalPartOfX =
3566 // 0.999892986f +
3567 // (0.696457318f +
3568 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3569 //
3570 // error 0.000107046256, which is 13 to 14 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003571 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003572 getF32Constant(DAG, 0x3da235e3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003573 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003574 getF32Constant(DAG, 0x3e65b8f3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003575 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3576 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003577 getF32Constant(DAG, 0x3f324b07));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003578 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3579 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003580 getF32Constant(DAG, 0x3f7ff8fd));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003581 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003582 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003583 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003584
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003585 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3586 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003587 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3588 // For floating-point precision of 18:
3589 //
3590 // TwoToFractionalPartOfX =
3591 // 0.999999982f +
3592 // (0.693148872f +
3593 // (0.240227044f +
3594 // (0.554906021e-1f +
3595 // (0.961591928e-2f +
3596 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3597 // error 2.47208000*10^(-7), which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003598 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003599 getF32Constant(DAG, 0x3924b03e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003600 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003601 getF32Constant(DAG, 0x3ab24b87));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003602 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3603 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003604 getF32Constant(DAG, 0x3c1d8c17));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003605 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3606 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003607 getF32Constant(DAG, 0x3d634a1d));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003608 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3609 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003610 getF32Constant(DAG, 0x3e75fe14));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003611 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3612 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003613 getF32Constant(DAG, 0x3f317234));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003614 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3615 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003616 getF32Constant(DAG, 0x3f800000));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003617 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003618 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003619 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003620
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003621 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3622 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003623 }
Dale Johannesen601d3c02008-09-05 01:48:15 +00003624 } else {
Bill Wendling3eb59402008-09-09 00:28:24 +00003625 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003626 result = DAG.getNode(ISD::FEXP2, dl,
Dale Johannesen601d3c02008-09-05 01:48:15 +00003627 getValue(I.getOperand(1)).getValueType(),
3628 getValue(I.getOperand(1)));
3629 }
Bill Wendlinge10c8142008-09-09 22:39:21 +00003630
Dale Johannesen601d3c02008-09-05 01:48:15 +00003631 setValue(&I, result);
3632}
3633
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003634/// visitPow - Lower a pow intrinsic. Handles the special sequences for
3635/// limited-precision mode with x == 10.0f.
3636void
3637SelectionDAGLowering::visitPow(CallInst &I) {
3638 SDValue result;
3639 Value *Val = I.getOperand(1);
Dale Johannesen66978ee2009-01-31 02:22:37 +00003640 DebugLoc dl = getCurDebugLoc();
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003641 bool IsExp10 = false;
3642
3643 if (getValue(Val).getValueType() == MVT::f32 &&
Bill Wendling277fc242008-09-10 00:24:59 +00003644 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003645 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3646 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3647 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3648 APFloat Ten(10.0f);
3649 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3650 }
3651 }
3652 }
3653
3654 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3655 SDValue Op = getValue(I.getOperand(2));
3656
3657 // Put the exponent in the right bit position for later addition to the
3658 // final result:
3659 //
3660 // #define LOG2OF10 3.3219281f
3661 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003662 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003663 getF32Constant(DAG, 0x40549a78));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003664 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003665
3666 // FractionalPartOfX = x - (float)IntegerPartOfX;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003667 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3668 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003669
3670 // IntegerPartOfX <<= 23;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003671 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
Duncan Sands92abc622009-01-31 15:50:11 +00003672 DAG.getConstant(23, TLI.getPointerTy()));
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003673
3674 if (LimitFloatPrecision <= 6) {
3675 // For floating-point precision of 6:
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003676 //
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003677 // twoToFractionalPartOfX =
3678 // 0.997535578f +
3679 // (0.735607626f + 0.252464424f * x) * x;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003680 //
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003681 // error 0.0144103317, which is 6 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003682 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003683 getF32Constant(DAG, 0x3e814304));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003684 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003685 getF32Constant(DAG, 0x3f3c50c8));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003686 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3687 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003688 getF32Constant(DAG, 0x3f7f5e7e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003689 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003690 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003691 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003692
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003693 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3694 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003695 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3696 // For floating-point precision of 12:
3697 //
3698 // TwoToFractionalPartOfX =
3699 // 0.999892986f +
3700 // (0.696457318f +
3701 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3702 //
3703 // error 0.000107046256, which is 13 to 14 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003704 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003705 getF32Constant(DAG, 0x3da235e3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003706 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003707 getF32Constant(DAG, 0x3e65b8f3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003708 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3709 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003710 getF32Constant(DAG, 0x3f324b07));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003711 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3712 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003713 getF32Constant(DAG, 0x3f7ff8fd));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003714 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003715 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003716 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003717
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003718 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3719 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003720 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3721 // For floating-point precision of 18:
3722 //
3723 // TwoToFractionalPartOfX =
3724 // 0.999999982f +
3725 // (0.693148872f +
3726 // (0.240227044f +
3727 // (0.554906021e-1f +
3728 // (0.961591928e-2f +
3729 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3730 // error 2.47208000*10^(-7), which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003731 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003732 getF32Constant(DAG, 0x3924b03e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003733 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003734 getF32Constant(DAG, 0x3ab24b87));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003735 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3736 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003737 getF32Constant(DAG, 0x3c1d8c17));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003738 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3739 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003740 getF32Constant(DAG, 0x3d634a1d));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003741 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3742 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003743 getF32Constant(DAG, 0x3e75fe14));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003744 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3745 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003746 getF32Constant(DAG, 0x3f317234));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003747 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3748 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003749 getF32Constant(DAG, 0x3f800000));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003750 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003751 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003752 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003753
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003754 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3755 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003756 }
3757 } else {
3758 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003759 result = DAG.getNode(ISD::FPOW, dl,
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003760 getValue(I.getOperand(1)).getValueType(),
3761 getValue(I.getOperand(1)),
3762 getValue(I.getOperand(2)));
3763 }
3764
3765 setValue(&I, result);
3766}
3767
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003768/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3769/// we want to emit this as a call to a named external function, return the name
3770/// otherwise lower it and return null.
3771const char *
3772SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00003773 DebugLoc dl = getCurDebugLoc();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003774 switch (Intrinsic) {
3775 default:
3776 // By default, turn this into a target intrinsic node.
3777 visitTargetIntrinsic(I, Intrinsic);
3778 return 0;
3779 case Intrinsic::vastart: visitVAStart(I); return 0;
3780 case Intrinsic::vaend: visitVAEnd(I); return 0;
3781 case Intrinsic::vacopy: visitVACopy(I); return 0;
3782 case Intrinsic::returnaddress:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003783 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003784 getValue(I.getOperand(1))));
3785 return 0;
Bill Wendlingd5d81912008-09-26 22:10:44 +00003786 case Intrinsic::frameaddress:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003787 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003788 getValue(I.getOperand(1))));
3789 return 0;
3790 case Intrinsic::setjmp:
3791 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3792 break;
3793 case Intrinsic::longjmp:
3794 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3795 break;
Chris Lattner824b9582008-11-21 16:42:48 +00003796 case Intrinsic::memcpy: {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003797 SDValue Op1 = getValue(I.getOperand(1));
3798 SDValue Op2 = getValue(I.getOperand(2));
3799 SDValue Op3 = getValue(I.getOperand(3));
3800 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3801 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3802 I.getOperand(1), 0, I.getOperand(2), 0));
3803 return 0;
3804 }
Chris Lattner824b9582008-11-21 16:42:48 +00003805 case Intrinsic::memset: {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003806 SDValue Op1 = getValue(I.getOperand(1));
3807 SDValue Op2 = getValue(I.getOperand(2));
3808 SDValue Op3 = getValue(I.getOperand(3));
3809 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3810 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3811 I.getOperand(1), 0));
3812 return 0;
3813 }
Chris Lattner824b9582008-11-21 16:42:48 +00003814 case Intrinsic::memmove: {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003815 SDValue Op1 = getValue(I.getOperand(1));
3816 SDValue Op2 = getValue(I.getOperand(2));
3817 SDValue Op3 = getValue(I.getOperand(3));
3818 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3819
3820 // If the source and destination are known to not be aliases, we can
3821 // lower memmove as memcpy.
3822 uint64_t Size = -1ULL;
3823 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003824 Size = C->getZExtValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003825 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3826 AliasAnalysis::NoAlias) {
3827 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3828 I.getOperand(1), 0, I.getOperand(2), 0));
3829 return 0;
3830 }
3831
3832 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3833 I.getOperand(1), 0, I.getOperand(2), 0));
3834 return 0;
3835 }
3836 case Intrinsic::dbg_stoppoint: {
Devang Patel83489bb2009-01-13 00:35:13 +00003837 DwarfWriter *DW = DAG.getDwarfWriter();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003838 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003839 if (DW && DW->ValidDebugInfo(SPI.getContext())) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003840 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3841 SPI.getLine(),
3842 SPI.getColumn(),
Devang Patel83489bb2009-01-13 00:35:13 +00003843 SPI.getContext()));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003844 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3845 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
3846 unsigned idx = DAG.getMachineFunction().
3847 getOrCreateDebugLocID(SrcFile,
3848 SPI.getLine(),
3849 SPI.getColumn());
Dale Johannesen66978ee2009-01-31 02:22:37 +00003850 setCurDebugLoc(DebugLoc::get(idx));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003851 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003852 return 0;
3853 }
3854 case Intrinsic::dbg_region_start: {
Devang Patel83489bb2009-01-13 00:35:13 +00003855 DwarfWriter *DW = DAG.getDwarfWriter();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003856 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
Devang Patelb79b5352009-01-19 23:21:49 +00003857 if (DW && DW->ValidDebugInfo(RSI.getContext())) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003858 unsigned LabelID =
Devang Patel83489bb2009-01-13 00:35:13 +00003859 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003860 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3861 }
3862
3863 return 0;
3864 }
3865 case Intrinsic::dbg_region_end: {
Devang Patel83489bb2009-01-13 00:35:13 +00003866 DwarfWriter *DW = DAG.getDwarfWriter();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003867 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
Devang Patelb79b5352009-01-19 23:21:49 +00003868 if (DW && DW->ValidDebugInfo(REI.getContext())) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003869 unsigned LabelID =
Devang Patel83489bb2009-01-13 00:35:13 +00003870 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003871 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3872 }
3873
3874 return 0;
3875 }
3876 case Intrinsic::dbg_func_start: {
Devang Patel83489bb2009-01-13 00:35:13 +00003877 DwarfWriter *DW = DAG.getDwarfWriter();
3878 if (!DW) return 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003879 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3880 Value *SP = FSI.getSubprogram();
Devang Patelcf3a4482009-01-15 23:41:32 +00003881 if (SP && DW->ValidDebugInfo(SP)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003882 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3883 // what (most?) gdb expects.
Devang Patel83489bb2009-01-13 00:35:13 +00003884 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3885 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3886 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(),
3887 CompileUnit.getFilename());
Bill Wendling9bc96a52009-02-03 00:55:04 +00003888
Devang Patel20dd0462008-11-06 00:30:09 +00003889 // Record the source line but does not create a label for the normal
3890 // function start. It will be emitted at asm emission time. However,
3891 // create a label if this is a beginning of inlined function.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003892 unsigned Line = Subprogram.getLineNumber();
Bill Wendling9bc96a52009-02-03 00:55:04 +00003893 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
3894
Devang Patel83489bb2009-01-13 00:35:13 +00003895 if (DW->getRecordSourceLineCount() != 1)
Devang Patel20dd0462008-11-06 00:30:09 +00003896 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
Bill Wendling9bc96a52009-02-03 00:55:04 +00003897
Dale Johannesen66978ee2009-01-31 02:22:37 +00003898 setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction().
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003899 getOrCreateDebugLocID(SrcFile, Line, 0)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003900 }
3901
3902 return 0;
3903 }
3904 case Intrinsic::dbg_declare: {
Devang Patel83489bb2009-01-13 00:35:13 +00003905 DwarfWriter *DW = DAG.getDwarfWriter();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003906 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3907 Value *Variable = DI.getVariable();
Devang Patelb79b5352009-01-19 23:21:49 +00003908 if (DW && DW->ValidDebugInfo(Variable))
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003909 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003910 getValue(DI.getAddress()), getValue(Variable)));
3911 return 0;
3912 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003913
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003914 case Intrinsic::eh_exception: {
3915 if (!CurMBB->isLandingPad()) {
3916 // FIXME: Mark exception register as live in. Hack for PR1508.
3917 unsigned Reg = TLI.getExceptionAddressRegister();
3918 if (Reg) CurMBB->addLiveIn(Reg);
3919 }
3920 // Insert the EXCEPTIONADDR instruction.
3921 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3922 SDValue Ops[1];
3923 Ops[0] = DAG.getRoot();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003924 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003925 setValue(&I, Op);
3926 DAG.setRoot(Op.getValue(1));
3927 return 0;
3928 }
3929
3930 case Intrinsic::eh_selector_i32:
3931 case Intrinsic::eh_selector_i64: {
3932 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3933 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3934 MVT::i32 : MVT::i64);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003935
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003936 if (MMI) {
3937 if (CurMBB->isLandingPad())
3938 AddCatchInfo(I, MMI, CurMBB);
3939 else {
3940#ifndef NDEBUG
3941 FuncInfo.CatchInfoLost.insert(&I);
3942#endif
3943 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3944 unsigned Reg = TLI.getExceptionSelectorRegister();
3945 if (Reg) CurMBB->addLiveIn(Reg);
3946 }
3947
3948 // Insert the EHSELECTION instruction.
3949 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3950 SDValue Ops[2];
3951 Ops[0] = getValue(I.getOperand(1));
3952 Ops[1] = getRoot();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003953 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003954 setValue(&I, Op);
3955 DAG.setRoot(Op.getValue(1));
3956 } else {
3957 setValue(&I, DAG.getConstant(0, VT));
3958 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003959
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003960 return 0;
3961 }
3962
3963 case Intrinsic::eh_typeid_for_i32:
3964 case Intrinsic::eh_typeid_for_i64: {
3965 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3966 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3967 MVT::i32 : MVT::i64);
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00003968
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003969 if (MMI) {
3970 // Find the type id for the given typeinfo.
3971 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3972
3973 unsigned TypeID = MMI->getTypeIDFor(GV);
3974 setValue(&I, DAG.getConstant(TypeID, VT));
3975 } else {
3976 // Return something different to eh_selector.
3977 setValue(&I, DAG.getConstant(1, VT));
3978 }
3979
3980 return 0;
3981 }
3982
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00003983 case Intrinsic::eh_return_i32:
3984 case Intrinsic::eh_return_i64:
3985 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003986 MMI->setCallsEHReturn(true);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003987 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003988 MVT::Other,
3989 getControlRoot(),
3990 getValue(I.getOperand(1)),
3991 getValue(I.getOperand(2))));
3992 } else {
3993 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3994 }
3995
3996 return 0;
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00003997 case Intrinsic::eh_unwind_init:
3998 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3999 MMI->setCallsUnwindInit(true);
4000 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004001
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004002 return 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004003
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004004 case Intrinsic::eh_dwarf_cfa: {
4005 MVT VT = getValue(I.getOperand(1)).getValueType();
4006 SDValue CfaArg;
4007 if (VT.bitsGT(TLI.getPointerTy()))
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004008 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004009 TLI.getPointerTy(), getValue(I.getOperand(1)));
4010 else
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004011 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004012 TLI.getPointerTy(), getValue(I.getOperand(1)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004013
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004014 SDValue Offset = DAG.getNode(ISD::ADD, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004015 TLI.getPointerTy(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004016 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004017 TLI.getPointerTy()),
4018 CfaArg);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004019 setValue(&I, DAG.getNode(ISD::ADD, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004020 TLI.getPointerTy(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004021 DAG.getNode(ISD::FRAMEADDR, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004022 TLI.getPointerTy(),
4023 DAG.getConstant(0,
4024 TLI.getPointerTy())),
4025 Offset));
4026 return 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004027 }
4028
Mon P Wang77cdf302008-11-10 20:54:11 +00004029 case Intrinsic::convertff:
4030 case Intrinsic::convertfsi:
4031 case Intrinsic::convertfui:
4032 case Intrinsic::convertsif:
4033 case Intrinsic::convertuif:
4034 case Intrinsic::convertss:
4035 case Intrinsic::convertsu:
4036 case Intrinsic::convertus:
4037 case Intrinsic::convertuu: {
4038 ISD::CvtCode Code = ISD::CVT_INVALID;
4039 switch (Intrinsic) {
4040 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4041 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4042 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4043 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4044 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4045 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4046 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4047 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4048 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4049 }
4050 MVT DestVT = TLI.getValueType(I.getType());
4051 Value* Op1 = I.getOperand(1);
4052 setValue(&I, DAG.getConvertRndSat(DestVT, getValue(Op1),
4053 DAG.getValueType(DestVT),
4054 DAG.getValueType(getValue(Op1).getValueType()),
4055 getValue(I.getOperand(2)),
4056 getValue(I.getOperand(3)),
4057 Code));
4058 return 0;
4059 }
4060
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004061 case Intrinsic::sqrt:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004062 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004063 getValue(I.getOperand(1)).getValueType(),
4064 getValue(I.getOperand(1))));
4065 return 0;
4066 case Intrinsic::powi:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004067 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004068 getValue(I.getOperand(1)).getValueType(),
4069 getValue(I.getOperand(1)),
4070 getValue(I.getOperand(2))));
4071 return 0;
4072 case Intrinsic::sin:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004073 setValue(&I, DAG.getNode(ISD::FSIN, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004074 getValue(I.getOperand(1)).getValueType(),
4075 getValue(I.getOperand(1))));
4076 return 0;
4077 case Intrinsic::cos:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004078 setValue(&I, DAG.getNode(ISD::FCOS, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004079 getValue(I.getOperand(1)).getValueType(),
4080 getValue(I.getOperand(1))));
4081 return 0;
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004082 case Intrinsic::log:
Dale Johannesen59e577f2008-09-05 18:38:42 +00004083 visitLog(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004084 return 0;
4085 case Intrinsic::log2:
Dale Johannesen59e577f2008-09-05 18:38:42 +00004086 visitLog2(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004087 return 0;
4088 case Intrinsic::log10:
Dale Johannesen59e577f2008-09-05 18:38:42 +00004089 visitLog10(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004090 return 0;
4091 case Intrinsic::exp:
Dale Johannesen59e577f2008-09-05 18:38:42 +00004092 visitExp(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004093 return 0;
4094 case Intrinsic::exp2:
Dale Johannesen601d3c02008-09-05 01:48:15 +00004095 visitExp2(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004096 return 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004097 case Intrinsic::pow:
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00004098 visitPow(I);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004099 return 0;
4100 case Intrinsic::pcmarker: {
4101 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004102 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004103 return 0;
4104 }
4105 case Intrinsic::readcyclecounter: {
4106 SDValue Op = getRoot();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004107 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004108 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
4109 &Op, 1);
4110 setValue(&I, Tmp);
4111 DAG.setRoot(Tmp.getValue(1));
4112 return 0;
4113 }
4114 case Intrinsic::part_select: {
4115 // Currently not implemented: just abort
4116 assert(0 && "part_select intrinsic not implemented");
4117 abort();
4118 }
4119 case Intrinsic::part_set: {
4120 // Currently not implemented: just abort
4121 assert(0 && "part_set intrinsic not implemented");
4122 abort();
4123 }
4124 case Intrinsic::bswap:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004125 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004126 getValue(I.getOperand(1)).getValueType(),
4127 getValue(I.getOperand(1))));
4128 return 0;
4129 case Intrinsic::cttz: {
4130 SDValue Arg = getValue(I.getOperand(1));
4131 MVT Ty = Arg.getValueType();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004132 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004133 setValue(&I, result);
4134 return 0;
4135 }
4136 case Intrinsic::ctlz: {
4137 SDValue Arg = getValue(I.getOperand(1));
4138 MVT Ty = Arg.getValueType();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004139 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004140 setValue(&I, result);
4141 return 0;
4142 }
4143 case Intrinsic::ctpop: {
4144 SDValue Arg = getValue(I.getOperand(1));
4145 MVT Ty = Arg.getValueType();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004146 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004147 setValue(&I, result);
4148 return 0;
4149 }
4150 case Intrinsic::stacksave: {
4151 SDValue Op = getRoot();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004152 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004153 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
4154 setValue(&I, Tmp);
4155 DAG.setRoot(Tmp.getValue(1));
4156 return 0;
4157 }
4158 case Intrinsic::stackrestore: {
4159 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004160 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004161 return 0;
4162 }
Bill Wendling57344502008-11-18 11:01:33 +00004163 case Intrinsic::stackprotector: {
Bill Wendlingb2a42982008-11-06 02:29:10 +00004164 // Emit code into the DAG to store the stack guard onto the stack.
4165 MachineFunction &MF = DAG.getMachineFunction();
4166 MachineFrameInfo *MFI = MF.getFrameInfo();
4167 MVT PtrTy = TLI.getPointerTy();
4168
Bill Wendlingb7c6ebc2008-11-07 01:23:58 +00004169 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4170 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
Bill Wendlingb2a42982008-11-06 02:29:10 +00004171
Bill Wendlingb7c6ebc2008-11-07 01:23:58 +00004172 int FI = FuncInfo.StaticAllocaMap[Slot];
Bill Wendlingb2a42982008-11-06 02:29:10 +00004173 MFI->setStackProtectorIndex(FI);
4174
4175 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4176
4177 // Store the stack protector onto the stack.
Dale Johannesen66978ee2009-01-31 02:22:37 +00004178 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
Bill Wendlingb2a42982008-11-06 02:29:10 +00004179 PseudoSourceValue::getFixedStack(FI),
4180 0, true);
4181 setValue(&I, Result);
4182 DAG.setRoot(Result);
4183 return 0;
4184 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004185 case Intrinsic::var_annotation:
4186 // Discard annotate attributes
4187 return 0;
4188
4189 case Intrinsic::init_trampoline: {
4190 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4191
4192 SDValue Ops[6];
4193 Ops[0] = getRoot();
4194 Ops[1] = getValue(I.getOperand(1));
4195 Ops[2] = getValue(I.getOperand(2));
4196 Ops[3] = getValue(I.getOperand(3));
4197 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4198 Ops[5] = DAG.getSrcValue(F);
4199
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004200 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004201 DAG.getNodeValueTypes(TLI.getPointerTy(),
4202 MVT::Other), 2,
4203 Ops, 6);
4204
4205 setValue(&I, Tmp);
4206 DAG.setRoot(Tmp.getValue(1));
4207 return 0;
4208 }
4209
4210 case Intrinsic::gcroot:
4211 if (GFI) {
4212 Value *Alloca = I.getOperand(1);
4213 Constant *TypeMap = cast<Constant>(I.getOperand(2));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004214
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004215 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4216 GFI->addStackRoot(FI->getIndex(), TypeMap);
4217 }
4218 return 0;
4219
4220 case Intrinsic::gcread:
4221 case Intrinsic::gcwrite:
4222 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4223 return 0;
4224
4225 case Intrinsic::flt_rounds: {
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004226 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004227 return 0;
4228 }
4229
4230 case Intrinsic::trap: {
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004231 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004232 return 0;
4233 }
Bill Wendling7cdc3c82008-11-21 02:03:52 +00004234
Bill Wendlingef375462008-11-21 02:38:44 +00004235 case Intrinsic::uadd_with_overflow:
Bill Wendling74c37652008-12-09 22:08:41 +00004236 return implVisitAluOverflow(I, ISD::UADDO);
4237 case Intrinsic::sadd_with_overflow:
4238 return implVisitAluOverflow(I, ISD::SADDO);
4239 case Intrinsic::usub_with_overflow:
4240 return implVisitAluOverflow(I, ISD::USUBO);
4241 case Intrinsic::ssub_with_overflow:
4242 return implVisitAluOverflow(I, ISD::SSUBO);
4243 case Intrinsic::umul_with_overflow:
4244 return implVisitAluOverflow(I, ISD::UMULO);
4245 case Intrinsic::smul_with_overflow:
4246 return implVisitAluOverflow(I, ISD::SMULO);
Bill Wendling7cdc3c82008-11-21 02:03:52 +00004247
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004248 case Intrinsic::prefetch: {
4249 SDValue Ops[4];
4250 Ops[0] = getRoot();
4251 Ops[1] = getValue(I.getOperand(1));
4252 Ops[2] = getValue(I.getOperand(2));
4253 Ops[3] = getValue(I.getOperand(3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004254 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004255 return 0;
4256 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004257
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004258 case Intrinsic::memory_barrier: {
4259 SDValue Ops[6];
4260 Ops[0] = getRoot();
4261 for (int x = 1; x < 6; ++x)
4262 Ops[x] = getValue(I.getOperand(x));
4263
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004264 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004265 return 0;
4266 }
4267 case Intrinsic::atomic_cmp_swap: {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004268 SDValue Root = getRoot();
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004269 SDValue L =
Dale Johannesen66978ee2009-01-31 02:22:37 +00004270 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004271 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4272 Root,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004273 getValue(I.getOperand(1)),
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004274 getValue(I.getOperand(2)),
4275 getValue(I.getOperand(3)),
4276 I.getOperand(1));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004277 setValue(&I, L);
4278 DAG.setRoot(L.getValue(1));
4279 return 0;
4280 }
4281 case Intrinsic::atomic_load_add:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004282 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004283 case Intrinsic::atomic_load_sub:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004284 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004285 case Intrinsic::atomic_load_or:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004286 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004287 case Intrinsic::atomic_load_xor:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004288 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004289 case Intrinsic::atomic_load_and:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004290 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004291 case Intrinsic::atomic_load_nand:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004292 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004293 case Intrinsic::atomic_load_max:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004294 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004295 case Intrinsic::atomic_load_min:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004296 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004297 case Intrinsic::atomic_load_umin:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004298 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004299 case Intrinsic::atomic_load_umax:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004300 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004301 case Intrinsic::atomic_swap:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004302 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004303 }
4304}
4305
4306
4307void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4308 bool IsTailCall,
4309 MachineBasicBlock *LandingPad) {
4310 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4311 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4312 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4313 unsigned BeginLabel = 0, EndLabel = 0;
4314
4315 TargetLowering::ArgListTy Args;
4316 TargetLowering::ArgListEntry Entry;
4317 Args.reserve(CS.arg_size());
4318 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4319 i != e; ++i) {
4320 SDValue ArgNode = getValue(*i);
4321 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4322
4323 unsigned attrInd = i - CS.arg_begin() + 1;
Devang Patel05988662008-09-25 21:00:45 +00004324 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4325 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4326 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4327 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4328 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4329 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004330 Entry.Alignment = CS.getParamAlignment(attrInd);
4331 Args.push_back(Entry);
4332 }
4333
4334 if (LandingPad && MMI) {
4335 // Insert a label before the invoke call to mark the try range. This can be
4336 // used to detect deletion of the invoke via the MachineModuleInfo.
4337 BeginLabel = MMI->NextLabelID();
4338 // Both PendingLoads and PendingExports must be flushed here;
4339 // this call might not return.
4340 (void)getRoot();
4341 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
4342 }
4343
4344 std::pair<SDValue,SDValue> Result =
4345 TLI.LowerCallTo(getRoot(), CS.getType(),
Devang Patel05988662008-09-25 21:00:45 +00004346 CS.paramHasAttr(0, Attribute::SExt),
Dale Johannesen86098bd2008-09-26 19:31:26 +00004347 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4348 CS.paramHasAttr(0, Attribute::InReg),
4349 CS.getCallingConv(),
Dan Gohman1937e2f2008-09-16 01:42:28 +00004350 IsTailCall && PerformTailCallOpt,
Dale Johannesen66978ee2009-01-31 02:22:37 +00004351 Callee, Args, DAG, getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004352 if (CS.getType() != Type::VoidTy)
4353 setValue(CS.getInstruction(), Result.first);
4354 DAG.setRoot(Result.second);
4355
4356 if (LandingPad && MMI) {
4357 // Insert a label at the end of the invoke call to mark the try range. This
4358 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4359 EndLabel = MMI->NextLabelID();
4360 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
4361
4362 // Inform MachineModuleInfo of range.
4363 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4364 }
4365}
4366
4367
4368void SelectionDAGLowering::visitCall(CallInst &I) {
4369 const char *RenameFn = 0;
4370 if (Function *F = I.getCalledFunction()) {
4371 if (F->isDeclaration()) {
4372 if (unsigned IID = F->getIntrinsicID()) {
4373 RenameFn = visitIntrinsicCall(I, IID);
4374 if (!RenameFn)
4375 return;
4376 }
4377 }
4378
4379 // Check for well-known libc/libm calls. If the function is internal, it
4380 // can't be a library call.
4381 unsigned NameLen = F->getNameLen();
Rafael Espindolabb46f522009-01-15 20:18:42 +00004382 if (!F->hasLocalLinkage() && NameLen) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004383 const char *NameStr = F->getNameStart();
4384 if (NameStr[0] == 'c' &&
4385 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4386 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4387 if (I.getNumOperands() == 3 && // Basic sanity checks.
4388 I.getOperand(1)->getType()->isFloatingPoint() &&
4389 I.getType() == I.getOperand(1)->getType() &&
4390 I.getType() == I.getOperand(2)->getType()) {
4391 SDValue LHS = getValue(I.getOperand(1));
4392 SDValue RHS = getValue(I.getOperand(2));
Dale Johannesen66978ee2009-01-31 02:22:37 +00004393 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004394 LHS.getValueType(), LHS, RHS));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004395 return;
4396 }
4397 } else if (NameStr[0] == 'f' &&
4398 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4399 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4400 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4401 if (I.getNumOperands() == 2 && // Basic sanity checks.
4402 I.getOperand(1)->getType()->isFloatingPoint() &&
4403 I.getType() == I.getOperand(1)->getType()) {
4404 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00004405 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004406 Tmp.getValueType(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004407 return;
4408 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004409 } else if (NameStr[0] == 's' &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004410 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4411 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4412 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4413 if (I.getNumOperands() == 2 && // Basic sanity checks.
4414 I.getOperand(1)->getType()->isFloatingPoint() &&
4415 I.getType() == I.getOperand(1)->getType()) {
4416 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00004417 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004418 Tmp.getValueType(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004419 return;
4420 }
4421 } else if (NameStr[0] == 'c' &&
4422 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4423 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4424 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4425 if (I.getNumOperands() == 2 && // Basic sanity checks.
4426 I.getOperand(1)->getType()->isFloatingPoint() &&
4427 I.getType() == I.getOperand(1)->getType()) {
4428 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00004429 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004430 Tmp.getValueType(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004431 return;
4432 }
4433 }
4434 }
4435 } else if (isa<InlineAsm>(I.getOperand(0))) {
4436 visitInlineAsm(&I);
4437 return;
4438 }
4439
4440 SDValue Callee;
4441 if (!RenameFn)
4442 Callee = getValue(I.getOperand(0));
4443 else
Bill Wendling056292f2008-09-16 21:48:12 +00004444 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004445
4446 LowerCallTo(&I, Callee, I.isTailCall());
4447}
4448
4449
4450/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004451/// this value and returns the result as a ValueVT value. This uses
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004452/// Chain/Flag as the input and updates them for the output Chain/Flag.
4453/// If the Flag pointer is NULL, no flag is used.
Dale Johannesen66978ee2009-01-31 02:22:37 +00004454SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004455 SDValue &Chain,
4456 SDValue *Flag) const {
4457 // Assemble the legal parts into the final values.
4458 SmallVector<SDValue, 4> Values(ValueVTs.size());
4459 SmallVector<SDValue, 8> Parts;
4460 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4461 // Copy the legal parts from the registers.
4462 MVT ValueVT = ValueVTs[Value];
4463 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4464 MVT RegisterVT = RegVTs[Value];
4465
4466 Parts.resize(NumRegs);
4467 for (unsigned i = 0; i != NumRegs; ++i) {
4468 SDValue P;
4469 if (Flag == 0)
4470 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
4471 else {
4472 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
4473 *Flag = P.getValue(2);
4474 }
4475 Chain = P.getValue(1);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004476
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004477 // If the source register was virtual and if we know something about it,
4478 // add an assert node.
4479 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4480 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4481 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4482 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4483 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4484 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004485
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004486 unsigned RegSize = RegisterVT.getSizeInBits();
4487 unsigned NumSignBits = LOI.NumSignBits;
4488 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004489
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004490 // FIXME: We capture more information than the dag can represent. For
4491 // now, just use the tightest assertzext/assertsext possible.
4492 bool isSExt = true;
4493 MVT FromVT(MVT::Other);
4494 if (NumSignBits == RegSize)
4495 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4496 else if (NumZeroBits >= RegSize-1)
4497 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4498 else if (NumSignBits > RegSize-8)
4499 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4500 else if (NumZeroBits >= RegSize-9)
4501 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4502 else if (NumSignBits > RegSize-16)
Bill Wendling181b6272008-10-19 20:34:04 +00004503 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004504 else if (NumZeroBits >= RegSize-17)
Bill Wendling181b6272008-10-19 20:34:04 +00004505 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004506 else if (NumSignBits > RegSize-32)
Bill Wendling181b6272008-10-19 20:34:04 +00004507 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004508 else if (NumZeroBits >= RegSize-33)
Bill Wendling181b6272008-10-19 20:34:04 +00004509 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004510
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004511 if (FromVT != MVT::Other) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00004512 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004513 RegisterVT, P, DAG.getValueType(FromVT));
4514
4515 }
4516 }
4517 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004518
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004519 Parts[i] = P;
4520 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004521
Dale Johannesen66978ee2009-01-31 02:22:37 +00004522 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4523 NumRegs, RegisterVT, ValueVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004524 Part += NumRegs;
4525 Parts.clear();
4526 }
4527
Dale Johannesen66978ee2009-01-31 02:22:37 +00004528 return DAG.getNode(ISD::MERGE_VALUES, dl,
Duncan Sandsaaffa052008-12-01 11:41:29 +00004529 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4530 &Values[0], ValueVTs.size());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004531}
4532
4533/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004534/// specified value into the registers specified by this object. This uses
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004535/// Chain/Flag as the input and updates them for the output Chain/Flag.
4536/// If the Flag pointer is NULL, no flag is used.
Dale Johannesen66978ee2009-01-31 02:22:37 +00004537void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004538 SDValue &Chain, SDValue *Flag) const {
4539 // Get the list of the values's legal parts.
4540 unsigned NumRegs = Regs.size();
4541 SmallVector<SDValue, 8> Parts(NumRegs);
4542 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4543 MVT ValueVT = ValueVTs[Value];
4544 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4545 MVT RegisterVT = RegVTs[Value];
4546
Dale Johannesen66978ee2009-01-31 02:22:37 +00004547 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004548 &Parts[Part], NumParts, RegisterVT);
4549 Part += NumParts;
4550 }
4551
4552 // Copy the parts into the registers.
4553 SmallVector<SDValue, 8> Chains(NumRegs);
4554 for (unsigned i = 0; i != NumRegs; ++i) {
4555 SDValue Part;
4556 if (Flag == 0)
4557 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
4558 else {
4559 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
4560 *Flag = Part.getValue(1);
4561 }
4562 Chains[i] = Part.getValue(0);
4563 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004564
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004565 if (NumRegs == 1 || Flag)
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004566 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004567 // flagged to it. That is the CopyToReg nodes and the user are considered
4568 // a single scheduling unit. If we create a TokenFactor and return it as
4569 // chain, then the TokenFactor is both a predecessor (operand) of the
4570 // user as well as a successor (the TF operands are flagged to the user).
4571 // c1, f1 = CopyToReg
4572 // c2, f2 = CopyToReg
4573 // c3 = TokenFactor c1, c2
4574 // ...
4575 // = op c3, ..., f2
4576 Chain = Chains[NumRegs-1];
4577 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00004578 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004579}
4580
4581/// AddInlineAsmOperands - Add this value to the specified inlineasm node
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004582/// operand list. This adds the code marker and includes the number of
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004583/// values added into it.
4584void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4585 std::vector<SDValue> &Ops) const {
4586 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4587 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4588 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4589 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4590 MVT RegisterVT = RegVTs[Value];
Chris Lattner58f15c42008-10-17 16:21:11 +00004591 for (unsigned i = 0; i != NumRegs; ++i) {
4592 assert(Reg < Regs.size() && "Mismatch in # registers expected");
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004593 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
Chris Lattner58f15c42008-10-17 16:21:11 +00004594 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004595 }
4596}
4597
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004598/// isAllocatableRegister - If the specified register is safe to allocate,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004599/// i.e. it isn't a stack pointer or some other special register, return the
4600/// register class for the register. Otherwise, return null.
4601static const TargetRegisterClass *
4602isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4603 const TargetLowering &TLI,
4604 const TargetRegisterInfo *TRI) {
4605 MVT FoundVT = MVT::Other;
4606 const TargetRegisterClass *FoundRC = 0;
4607 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4608 E = TRI->regclass_end(); RCI != E; ++RCI) {
4609 MVT ThisVT = MVT::Other;
4610
4611 const TargetRegisterClass *RC = *RCI;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004612 // If none of the the value types for this register class are valid, we
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004613 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4614 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4615 I != E; ++I) {
4616 if (TLI.isTypeLegal(*I)) {
4617 // If we have already found this register in a different register class,
4618 // choose the one with the largest VT specified. For example, on
4619 // PowerPC, we favor f64 register classes over f32.
4620 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4621 ThisVT = *I;
4622 break;
4623 }
4624 }
4625 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004626
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004627 if (ThisVT == MVT::Other) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004628
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004629 // NOTE: This isn't ideal. In particular, this might allocate the
4630 // frame pointer in functions that need it (due to them not being taken
4631 // out of allocation, because a variable sized allocation hasn't been seen
4632 // yet). This is a slight code pessimization, but should still work.
4633 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4634 E = RC->allocation_order_end(MF); I != E; ++I)
4635 if (*I == Reg) {
4636 // We found a matching register class. Keep looking at others in case
4637 // we find one with larger registers that this physreg is also in.
4638 FoundRC = RC;
4639 FoundVT = ThisVT;
4640 break;
4641 }
4642 }
4643 return FoundRC;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004644}
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004645
4646
4647namespace llvm {
4648/// AsmOperandInfo - This contains information for each constraint that we are
4649/// lowering.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004650struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
Daniel Dunbarc0c3b9a2008-09-10 04:16:29 +00004651 public TargetLowering::AsmOperandInfo {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004652 /// CallOperand - If this is the result output operand or a clobber
4653 /// this is null, otherwise it is the incoming operand to the CallInst.
4654 /// This gets modified as the asm is processed.
4655 SDValue CallOperand;
4656
4657 /// AssignedRegs - If this is a register or register class operand, this
4658 /// contains the set of register corresponding to the operand.
4659 RegsForValue AssignedRegs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004660
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004661 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4662 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4663 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004664
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004665 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4666 /// busy in OutputRegs/InputRegs.
4667 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004668 std::set<unsigned> &OutputRegs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004669 std::set<unsigned> &InputRegs,
4670 const TargetRegisterInfo &TRI) const {
4671 if (isOutReg) {
4672 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4673 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4674 }
4675 if (isInReg) {
4676 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4677 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4678 }
4679 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004680
Chris Lattner81249c92008-10-17 17:05:25 +00004681 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4682 /// corresponds to. If there is no Value* for this operand, it returns
4683 /// MVT::Other.
4684 MVT getCallOperandValMVT(const TargetLowering &TLI,
4685 const TargetData *TD) const {
4686 if (CallOperandVal == 0) return MVT::Other;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004687
Chris Lattner81249c92008-10-17 17:05:25 +00004688 if (isa<BasicBlock>(CallOperandVal))
4689 return TLI.getPointerTy();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004690
Chris Lattner81249c92008-10-17 17:05:25 +00004691 const llvm::Type *OpTy = CallOperandVal->getType();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004692
Chris Lattner81249c92008-10-17 17:05:25 +00004693 // If this is an indirect operand, the operand is a pointer to the
4694 // accessed type.
4695 if (isIndirect)
4696 OpTy = cast<PointerType>(OpTy)->getElementType();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004697
Chris Lattner81249c92008-10-17 17:05:25 +00004698 // If OpTy is not a single value, it may be a struct/union that we
4699 // can tile with integers.
4700 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4701 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4702 switch (BitSize) {
4703 default: break;
4704 case 1:
4705 case 8:
4706 case 16:
4707 case 32:
4708 case 64:
Chris Lattnercfc14c12008-10-17 19:59:51 +00004709 case 128:
Chris Lattner81249c92008-10-17 17:05:25 +00004710 OpTy = IntegerType::get(BitSize);
4711 break;
4712 }
4713 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004714
Chris Lattner81249c92008-10-17 17:05:25 +00004715 return TLI.getValueType(OpTy, true);
4716 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004717
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004718private:
4719 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4720 /// specified set.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004721 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004722 const TargetRegisterInfo &TRI) {
4723 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4724 Regs.insert(Reg);
4725 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4726 for (; *Aliases; ++Aliases)
4727 Regs.insert(*Aliases);
4728 }
4729};
4730} // end llvm namespace.
4731
4732
4733/// GetRegistersForValue - Assign registers (virtual or physical) for the
4734/// specified operand. We prefer to assign virtual registers, to allow the
4735/// register allocator handle the assignment process. However, if the asm uses
4736/// features that we can't model on machineinstrs, we have SDISel do the
4737/// allocation. This produces generally horrible, but correct, code.
4738///
4739/// OpInfo describes the operand.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004740/// Input and OutputRegs are the set of already allocated physical registers.
4741///
4742void SelectionDAGLowering::
Dale Johannesen8e3455b2008-09-24 23:13:09 +00004743GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004744 std::set<unsigned> &OutputRegs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004745 std::set<unsigned> &InputRegs) {
4746 // Compute whether this value requires an input register, an output register,
4747 // or both.
4748 bool isOutReg = false;
4749 bool isInReg = false;
4750 switch (OpInfo.Type) {
4751 case InlineAsm::isOutput:
4752 isOutReg = true;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004753
4754 // If there is an input constraint that matches this, we need to reserve
Dale Johannesen8e3455b2008-09-24 23:13:09 +00004755 // the input register so no other inputs allocate to it.
Chris Lattner6bdcda32008-10-17 16:47:46 +00004756 isInReg = OpInfo.hasMatchingInput();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004757 break;
4758 case InlineAsm::isInput:
4759 isInReg = true;
4760 isOutReg = false;
4761 break;
4762 case InlineAsm::isClobber:
4763 isOutReg = true;
4764 isInReg = true;
4765 break;
4766 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004767
4768
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004769 MachineFunction &MF = DAG.getMachineFunction();
4770 SmallVector<unsigned, 4> Regs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004771
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004772 // If this is a constraint for a single physreg, or a constraint for a
4773 // register class, find it.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004774 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004775 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4776 OpInfo.ConstraintVT);
4777
4778 unsigned NumRegs = 1;
Chris Lattner01426e12008-10-21 00:45:36 +00004779 if (OpInfo.ConstraintVT != MVT::Other) {
4780 // If this is a FP input in an integer register (or visa versa) insert a bit
4781 // cast of the input value. More generally, handle any case where the input
4782 // value disagrees with the register class we plan to stick this in.
4783 if (OpInfo.Type == InlineAsm::isInput &&
4784 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4785 // Try to convert to the first MVT that the reg class contains. If the
4786 // types are identical size, use a bitcast to convert (e.g. two differing
4787 // vector types).
4788 MVT RegVT = *PhysReg.second->vt_begin();
4789 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00004790 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004791 RegVT, OpInfo.CallOperand);
Chris Lattner01426e12008-10-21 00:45:36 +00004792 OpInfo.ConstraintVT = RegVT;
4793 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4794 // If the input is a FP value and we want it in FP registers, do a
4795 // bitcast to the corresponding integer type. This turns an f64 value
4796 // into i64, which can be passed with two i32 values on a 32-bit
4797 // machine.
4798 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
Dale Johannesen66978ee2009-01-31 02:22:37 +00004799 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004800 RegVT, OpInfo.CallOperand);
Chris Lattner01426e12008-10-21 00:45:36 +00004801 OpInfo.ConstraintVT = RegVT;
4802 }
4803 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004804
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004805 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
Chris Lattner01426e12008-10-21 00:45:36 +00004806 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004807
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004808 MVT RegVT;
4809 MVT ValueVT = OpInfo.ConstraintVT;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004810
4811 // If this is a constraint for a specific physical register, like {r17},
4812 // assign it now.
4813 if (PhysReg.first) {
4814 if (OpInfo.ConstraintVT == MVT::Other)
4815 ValueVT = *PhysReg.second->vt_begin();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004816
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004817 // Get the actual register value type. This is important, because the user
4818 // may have asked for (e.g.) the AX register in i32 type. We need to
4819 // remember that AX is actually i16 to get the right extension.
4820 RegVT = *PhysReg.second->vt_begin();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004821
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004822 // This is a explicit reference to a physical register.
4823 Regs.push_back(PhysReg.first);
4824
4825 // If this is an expanded reference, add the rest of the regs to Regs.
4826 if (NumRegs != 1) {
4827 TargetRegisterClass::iterator I = PhysReg.second->begin();
4828 for (; *I != PhysReg.first; ++I)
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004829 assert(I != PhysReg.second->end() && "Didn't find reg!");
4830
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004831 // Already added the first reg.
4832 --NumRegs; ++I;
4833 for (; NumRegs; --NumRegs, ++I) {
4834 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4835 Regs.push_back(*I);
4836 }
4837 }
4838 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4839 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4840 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4841 return;
4842 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004843
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004844 // Otherwise, if this was a reference to an LLVM register class, create vregs
4845 // for this reference.
4846 std::vector<unsigned> RegClassRegs;
4847 const TargetRegisterClass *RC = PhysReg.second;
4848 if (RC) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004849 // If this is a tied register, our regalloc doesn't know how to maintain
Chris Lattner58f15c42008-10-17 16:21:11 +00004850 // the constraint, so we have to pick a register to pin the input/output to.
4851 // If it isn't a matched constraint, go ahead and create vreg and let the
4852 // regalloc do its thing.
Chris Lattner6bdcda32008-10-17 16:47:46 +00004853 if (!OpInfo.hasMatchingInput()) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004854 RegVT = *PhysReg.second->vt_begin();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004855 if (OpInfo.ConstraintVT == MVT::Other)
4856 ValueVT = RegVT;
4857
4858 // Create the appropriate number of virtual registers.
4859 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4860 for (; NumRegs; --NumRegs)
4861 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004862
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004863 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4864 return;
4865 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004866
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004867 // Otherwise, we can't allocate it. Let the code below figure out how to
4868 // maintain these constraints.
4869 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004870
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004871 } else {
4872 // This is a reference to a register class that doesn't directly correspond
4873 // to an LLVM register class. Allocate NumRegs consecutive, available,
4874 // registers from the class.
4875 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4876 OpInfo.ConstraintVT);
4877 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004878
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004879 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4880 unsigned NumAllocated = 0;
4881 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4882 unsigned Reg = RegClassRegs[i];
4883 // See if this register is available.
4884 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4885 (isInReg && InputRegs.count(Reg))) { // Already used.
4886 // Make sure we find consecutive registers.
4887 NumAllocated = 0;
4888 continue;
4889 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004890
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004891 // Check to see if this register is allocatable (i.e. don't give out the
4892 // stack pointer).
4893 if (RC == 0) {
4894 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4895 if (!RC) { // Couldn't allocate this register.
4896 // Reset NumAllocated to make sure we return consecutive registers.
4897 NumAllocated = 0;
4898 continue;
4899 }
4900 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004901
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004902 // Okay, this register is good, we can use it.
4903 ++NumAllocated;
4904
4905 // If we allocated enough consecutive registers, succeed.
4906 if (NumAllocated == NumRegs) {
4907 unsigned RegStart = (i-NumAllocated)+1;
4908 unsigned RegEnd = i+1;
4909 // Mark all of the allocated registers used.
4910 for (unsigned i = RegStart; i != RegEnd; ++i)
4911 Regs.push_back(RegClassRegs[i]);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004912
4913 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004914 OpInfo.ConstraintVT);
4915 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4916 return;
4917 }
4918 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004919
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004920 // Otherwise, we couldn't allocate enough registers for this.
4921}
4922
Evan Chengda43bcf2008-09-24 00:05:32 +00004923/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4924/// processed uses a memory 'm' constraint.
4925static bool
4926hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
Dan Gohmane9530ec2009-01-15 16:58:17 +00004927 const TargetLowering &TLI) {
Evan Chengda43bcf2008-09-24 00:05:32 +00004928 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4929 InlineAsm::ConstraintInfo &CI = CInfos[i];
4930 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4931 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4932 if (CType == TargetLowering::C_Memory)
4933 return true;
4934 }
4935 }
4936
4937 return false;
4938}
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004939
4940/// visitInlineAsm - Handle a call to an InlineAsm object.
4941///
4942void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4943 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4944
4945 /// ConstraintOperands - Information about all of the constraints.
4946 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004947
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004948 SDValue Chain = getRoot();
4949 SDValue Flag;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004950
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004951 std::set<unsigned> OutputRegs, InputRegs;
4952
4953 // Do a prepass over the constraints, canonicalizing them, and building up the
4954 // ConstraintOperands list.
4955 std::vector<InlineAsm::ConstraintInfo>
4956 ConstraintInfos = IA->ParseConstraints();
4957
Evan Chengda43bcf2008-09-24 00:05:32 +00004958 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004959
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004960 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4961 unsigned ResNo = 0; // ResNo - The result number of the next output.
4962 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4963 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4964 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004965
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004966 MVT OpVT = MVT::Other;
4967
4968 // Compute the value type for each operand.
4969 switch (OpInfo.Type) {
4970 case InlineAsm::isOutput:
4971 // Indirect outputs just consume an argument.
4972 if (OpInfo.isIndirect) {
4973 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4974 break;
4975 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004976
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004977 // The return value of the call is this value. As such, there is no
4978 // corresponding argument.
4979 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4980 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4981 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4982 } else {
4983 assert(ResNo == 0 && "Asm only has one result!");
4984 OpVT = TLI.getValueType(CS.getType());
4985 }
4986 ++ResNo;
4987 break;
4988 case InlineAsm::isInput:
4989 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4990 break;
4991 case InlineAsm::isClobber:
4992 // Nothing to do.
4993 break;
4994 }
4995
4996 // If this is an input or an indirect output, process the call argument.
4997 // BasicBlocks are labels, currently appearing only in asm's.
4998 if (OpInfo.CallOperandVal) {
Chris Lattner81249c92008-10-17 17:05:25 +00004999 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005000 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
Chris Lattner81249c92008-10-17 17:05:25 +00005001 } else {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005002 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005003 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005004
Chris Lattner81249c92008-10-17 17:05:25 +00005005 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005006 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005007
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005008 OpInfo.ConstraintVT = OpVT;
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005009 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005010
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005011 // Second pass over the constraints: compute which constraint option to use
5012 // and assign registers to constraints that want a specific physreg.
5013 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5014 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005015
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005016 // If this is an output operand with a matching input operand, look up the
Evan Cheng09dc9c02008-12-16 18:21:39 +00005017 // matching input. If their types mismatch, e.g. one is an integer, the
5018 // other is floating point, or their sizes are different, flag it as an
5019 // error.
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005020 if (OpInfo.hasMatchingInput()) {
5021 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5022 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Evan Cheng09dc9c02008-12-16 18:21:39 +00005023 if ((OpInfo.ConstraintVT.isInteger() !=
5024 Input.ConstraintVT.isInteger()) ||
5025 (OpInfo.ConstraintVT.getSizeInBits() !=
5026 Input.ConstraintVT.getSizeInBits())) {
5027 cerr << "Unsupported asm: input constraint with a matching output "
5028 << "constraint of incompatible type!\n";
5029 exit(1);
5030 }
5031 Input.ConstraintVT = OpInfo.ConstraintVT;
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005032 }
5033 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005034
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005035 // Compute the constraint code and ConstraintType to use.
Evan Chengda43bcf2008-09-24 00:05:32 +00005036 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005037
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005038 // If this is a memory input, and if the operand is not indirect, do what we
5039 // need to to provide an address for the memory input.
5040 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5041 !OpInfo.isIndirect) {
5042 assert(OpInfo.Type == InlineAsm::isInput &&
5043 "Can only indirectify direct input operands!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005044
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005045 // Memory operands really want the address of the value. If we don't have
5046 // an indirect input, put it in the constpool if we can, otherwise spill
5047 // it to a stack slot.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005048
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005049 // If the operand is a float, integer, or vector constant, spill to a
5050 // constant pool entry to get its address.
5051 Value *OpVal = OpInfo.CallOperandVal;
5052 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5053 isa<ConstantVector>(OpVal)) {
5054 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5055 TLI.getPointerTy());
5056 } else {
5057 // Otherwise, create a stack slot and emit a store to it before the
5058 // asm.
5059 const Type *Ty = OpVal->getType();
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00005060 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005061 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5062 MachineFunction &MF = DAG.getMachineFunction();
5063 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5064 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
Dale Johannesen66978ee2009-01-31 02:22:37 +00005065 Chain = DAG.getStore(Chain, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005066 OpInfo.CallOperand, StackSlot, NULL, 0);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005067 OpInfo.CallOperand = StackSlot;
5068 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005069
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005070 // There is no longer a Value* corresponding to this operand.
5071 OpInfo.CallOperandVal = 0;
5072 // It is now an indirect operand.
5073 OpInfo.isIndirect = true;
5074 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005075
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005076 // If this constraint is for a specific register, allocate it before
5077 // anything else.
5078 if (OpInfo.ConstraintType == TargetLowering::C_Register)
Dale Johannesen8e3455b2008-09-24 23:13:09 +00005079 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005080 }
5081 ConstraintInfos.clear();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005082
5083
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005084 // Second pass - Loop over all of the operands, assigning virtual or physregs
Chris Lattner58f15c42008-10-17 16:21:11 +00005085 // to register class operands.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005086 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5087 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005088
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005089 // C_Register operands have already been allocated, Other/Memory don't need
5090 // to be.
5091 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
Dale Johannesen8e3455b2008-09-24 23:13:09 +00005092 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005093 }
5094
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005095 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5096 std::vector<SDValue> AsmNodeOperands;
5097 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5098 AsmNodeOperands.push_back(
Bill Wendling056292f2008-09-16 21:48:12 +00005099 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005100
5101
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005102 // Loop over all of the inputs, copying the operand values into the
5103 // appropriate registers and processing the output regs.
5104 RegsForValue RetValRegs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005105
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005106 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5107 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005108
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005109 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5110 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5111
5112 switch (OpInfo.Type) {
5113 case InlineAsm::isOutput: {
5114 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5115 OpInfo.ConstraintType != TargetLowering::C_Register) {
5116 // Memory output, or 'other' output (e.g. 'X' constraint).
5117 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5118
5119 // Add information to the INLINEASM node to know about this output.
Dale Johannesen86b49f82008-09-24 01:07:17 +00005120 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5121 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005122 TLI.getPointerTy()));
5123 AsmNodeOperands.push_back(OpInfo.CallOperand);
5124 break;
5125 }
5126
5127 // Otherwise, this is a register or register class output.
5128
5129 // Copy the output from the appropriate register. Find a register that
5130 // we can use.
5131 if (OpInfo.AssignedRegs.Regs.empty()) {
5132 cerr << "Couldn't allocate output reg for constraint '"
5133 << OpInfo.ConstraintCode << "'!\n";
5134 exit(1);
5135 }
5136
5137 // If this is an indirect operand, store through the pointer after the
5138 // asm.
5139 if (OpInfo.isIndirect) {
5140 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5141 OpInfo.CallOperandVal));
5142 } else {
5143 // This is the result value of the call.
5144 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5145 // Concatenate this output onto the outputs list.
5146 RetValRegs.append(OpInfo.AssignedRegs);
5147 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005148
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005149 // Add information to the INLINEASM node to know that this register is
5150 // set.
Dale Johannesen913d3df2008-09-12 17:49:03 +00005151 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5152 6 /* EARLYCLOBBER REGDEF */ :
5153 2 /* REGDEF */ ,
5154 DAG, AsmNodeOperands);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005155 break;
5156 }
5157 case InlineAsm::isInput: {
5158 SDValue InOperandVal = OpInfo.CallOperand;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005159
Chris Lattner6bdcda32008-10-17 16:47:46 +00005160 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005161 // If this is required to match an output register we have already set,
5162 // just use its register.
Chris Lattner58f15c42008-10-17 16:21:11 +00005163 unsigned OperandNo = OpInfo.getMatchedOperand();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005164
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005165 // Scan until we find the definition we already emitted of this operand.
5166 // When we find it, create a RegsForValue operand.
5167 unsigned CurOp = 2; // The first operand.
5168 for (; OperandNo; --OperandNo) {
5169 // Advance to the next operand.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005170 unsigned NumOps =
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005171 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005172 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
Dale Johannesen913d3df2008-09-12 17:49:03 +00005173 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
Dale Johannesen86b49f82008-09-24 01:07:17 +00005174 (NumOps & 7) == 4 /*MEM*/) &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005175 "Skipped past definitions?");
5176 CurOp += (NumOps>>3)+1;
5177 }
5178
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005179 unsigned NumOps =
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005180 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005181 if ((NumOps & 7) == 2 /*REGDEF*/
Dale Johannesen913d3df2008-09-12 17:49:03 +00005182 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005183 // Add NumOps>>3 registers to MatchedRegs.
5184 RegsForValue MatchedRegs;
5185 MatchedRegs.TLI = &TLI;
5186 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5187 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
5188 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
5189 unsigned Reg =
5190 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
5191 MatchedRegs.Regs.push_back(Reg);
5192 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005193
5194 // Use the produced MatchedRegs object to
Dale Johannesen66978ee2009-01-31 02:22:37 +00005195 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5196 Chain, &Flag);
Dale Johannesen86b49f82008-09-24 01:07:17 +00005197 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005198 break;
5199 } else {
Dale Johannesen86b49f82008-09-24 01:07:17 +00005200 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005201 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005202 // Add information to the INLINEASM node to know about this input.
Dale Johannesen91aac102008-09-17 21:13:11 +00005203 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005204 TLI.getPointerTy()));
5205 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5206 break;
5207 }
5208 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005209
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005210 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005211 assert(!OpInfo.isIndirect &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005212 "Don't know how to handle indirect other inputs yet!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005213
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005214 std::vector<SDValue> Ops;
5215 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
Evan Chengda43bcf2008-09-24 00:05:32 +00005216 hasMemory, Ops, DAG);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005217 if (Ops.empty()) {
5218 cerr << "Invalid operand for inline asm constraint '"
5219 << OpInfo.ConstraintCode << "'!\n";
5220 exit(1);
5221 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005222
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005223 // Add information to the INLINEASM node to know about this input.
5224 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005225 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005226 TLI.getPointerTy()));
5227 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5228 break;
5229 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5230 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5231 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5232 "Memory operands expect pointer values");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005233
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005234 // Add information to the INLINEASM node to know about this input.
Dale Johannesen86b49f82008-09-24 01:07:17 +00005235 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5236 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005237 TLI.getPointerTy()));
5238 AsmNodeOperands.push_back(InOperandVal);
5239 break;
5240 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005241
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005242 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5243 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5244 "Unknown constraint type!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005245 assert(!OpInfo.isIndirect &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005246 "Don't know how to handle indirect register inputs yet!");
5247
5248 // Copy the input into the appropriate registers.
Evan Chengaa765b82008-09-25 00:14:04 +00005249 if (OpInfo.AssignedRegs.Regs.empty()) {
5250 cerr << "Couldn't allocate output reg for constraint '"
5251 << OpInfo.ConstraintCode << "'!\n";
5252 exit(1);
5253 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005254
Dale Johannesen66978ee2009-01-31 02:22:37 +00005255 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5256 Chain, &Flag);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005257
Dale Johannesen86b49f82008-09-24 01:07:17 +00005258 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
5259 DAG, AsmNodeOperands);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005260 break;
5261 }
5262 case InlineAsm::isClobber: {
5263 // Add the clobbered value to the operand list, so that the register
5264 // allocator is aware that the physreg got clobbered.
5265 if (!OpInfo.AssignedRegs.Regs.empty())
Dale Johannesen91aac102008-09-17 21:13:11 +00005266 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5267 DAG, AsmNodeOperands);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005268 break;
5269 }
5270 }
5271 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005272
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005273 // Finish up input operands.
5274 AsmNodeOperands[0] = Chain;
5275 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005276
Dale Johannesen66978ee2009-01-31 02:22:37 +00005277 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005278 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
5279 &AsmNodeOperands[0], AsmNodeOperands.size());
5280 Flag = Chain.getValue(1);
5281
5282 // If this asm returns a register value, copy the result from that register
5283 // and set it as the value of the call.
5284 if (!RetValRegs.Regs.empty()) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005285 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5286 Chain, &Flag);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005287
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005288 // FIXME: Why don't we do this for inline asms with MRVs?
5289 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5290 MVT ResultType = TLI.getValueType(CS.getType());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005291
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005292 // If any of the results of the inline asm is a vector, it may have the
5293 // wrong width/num elts. This can happen for register classes that can
5294 // contain multiple different value types. The preg or vreg allocated may
5295 // not have the same VT as was expected. Convert it to the right type
5296 // with bit_convert.
5297 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005298 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005299 ResultType, Val);
Dan Gohman95915732008-10-18 01:03:45 +00005300
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005301 } else if (ResultType != Val.getValueType() &&
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005302 ResultType.isInteger() && Val.getValueType().isInteger()) {
5303 // If a result value was tied to an input value, the computed result may
5304 // have a wider width than the expected result. Extract the relevant
5305 // portion.
Dale Johannesen66978ee2009-01-31 02:22:37 +00005306 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
Dan Gohman95915732008-10-18 01:03:45 +00005307 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005308
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005309 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
Chris Lattner0c526442008-10-17 17:52:49 +00005310 }
Dan Gohman95915732008-10-18 01:03:45 +00005311
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005312 setValue(CS.getInstruction(), Val);
5313 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005314
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005315 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005316
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005317 // Process indirect outputs, first output all of the flagged copies out of
5318 // physregs.
5319 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5320 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5321 Value *Ptr = IndirectStoresToEmit[i].second;
Dale Johannesen66978ee2009-01-31 02:22:37 +00005322 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5323 Chain, &Flag);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005324 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5325 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005326
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005327 // Emit the non-flagged stores from the physregs.
5328 SmallVector<SDValue, 8> OutChains;
5329 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00005330 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005331 StoresToEmit[i].first,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005332 getValue(StoresToEmit[i].second),
5333 StoresToEmit[i].second, 0));
5334 if (!OutChains.empty())
Dale Johannesen66978ee2009-01-31 02:22:37 +00005335 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005336 &OutChains[0], OutChains.size());
5337 DAG.setRoot(Chain);
5338}
5339
5340
5341void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5342 SDValue Src = getValue(I.getOperand(0));
5343
5344 MVT IntPtr = TLI.getPointerTy();
5345
5346 if (IntPtr.bitsLT(Src.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00005347 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005348 else if (IntPtr.bitsGT(Src.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00005349 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005350
5351 // Scale the source by the type size.
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00005352 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00005353 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005354 Src, DAG.getIntPtrConstant(ElementSize));
5355
5356 TargetLowering::ArgListTy Args;
5357 TargetLowering::ArgListEntry Entry;
5358 Entry.Node = Src;
5359 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5360 Args.push_back(Entry);
5361
5362 std::pair<SDValue,SDValue> Result =
Dale Johannesen86098bd2008-09-26 19:31:26 +00005363 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005364 CallingConv::C, PerformTailCallOpt,
Dale Johannesen86098bd2008-09-26 19:31:26 +00005365 DAG.getExternalSymbol("malloc", IntPtr),
Dale Johannesen66978ee2009-01-31 02:22:37 +00005366 Args, DAG, getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005367 setValue(&I, Result.first); // Pointers always fit in registers
5368 DAG.setRoot(Result.second);
5369}
5370
5371void SelectionDAGLowering::visitFree(FreeInst &I) {
5372 TargetLowering::ArgListTy Args;
5373 TargetLowering::ArgListEntry Entry;
5374 Entry.Node = getValue(I.getOperand(0));
5375 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5376 Args.push_back(Entry);
5377 MVT IntPtr = TLI.getPointerTy();
5378 std::pair<SDValue,SDValue> Result =
Dale Johannesen86098bd2008-09-26 19:31:26 +00005379 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
Dan Gohman1937e2f2008-09-16 01:42:28 +00005380 CallingConv::C, PerformTailCallOpt,
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005381 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
Dale Johannesen66978ee2009-01-31 02:22:37 +00005382 getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005383 DAG.setRoot(Result.second);
5384}
5385
5386void SelectionDAGLowering::visitVAStart(CallInst &I) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005387 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005388 MVT::Other, getRoot(),
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005389 getValue(I.getOperand(1)),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005390 DAG.getSrcValue(I.getOperand(1))));
5391}
5392
5393void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5394 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
5395 getValue(I.getOperand(0)),
5396 DAG.getSrcValue(I.getOperand(0)));
5397 setValue(&I, V);
5398 DAG.setRoot(V.getValue(1));
5399}
5400
5401void SelectionDAGLowering::visitVAEnd(CallInst &I) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005402 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005403 MVT::Other, getRoot(),
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005404 getValue(I.getOperand(1)),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005405 DAG.getSrcValue(I.getOperand(1))));
5406}
5407
5408void SelectionDAGLowering::visitVACopy(CallInst &I) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005409 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005410 MVT::Other, getRoot(),
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005411 getValue(I.getOperand(1)),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005412 getValue(I.getOperand(2)),
5413 DAG.getSrcValue(I.getOperand(1)),
5414 DAG.getSrcValue(I.getOperand(2))));
5415}
5416
5417/// TargetLowering::LowerArguments - This is the default LowerArguments
5418/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005419/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005420/// integrated into SDISel.
5421void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005422 SmallVectorImpl<SDValue> &ArgValues,
5423 DebugLoc dl) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005424 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5425 SmallVector<SDValue, 3+16> Ops;
5426 Ops.push_back(DAG.getRoot());
5427 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5428 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5429
5430 // Add one result value for each formal argument.
5431 SmallVector<MVT, 16> RetVals;
5432 unsigned j = 1;
5433 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5434 I != E; ++I, ++j) {
5435 SmallVector<MVT, 4> ValueVTs;
5436 ComputeValueVTs(*this, I->getType(), ValueVTs);
5437 for (unsigned Value = 0, NumValues = ValueVTs.size();
5438 Value != NumValues; ++Value) {
5439 MVT VT = ValueVTs[Value];
5440 const Type *ArgTy = VT.getTypeForMVT();
5441 ISD::ArgFlagsTy Flags;
5442 unsigned OriginalAlignment =
5443 getTargetData()->getABITypeAlignment(ArgTy);
5444
Devang Patel05988662008-09-25 21:00:45 +00005445 if (F.paramHasAttr(j, Attribute::ZExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005446 Flags.setZExt();
Devang Patel05988662008-09-25 21:00:45 +00005447 if (F.paramHasAttr(j, Attribute::SExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005448 Flags.setSExt();
Devang Patel05988662008-09-25 21:00:45 +00005449 if (F.paramHasAttr(j, Attribute::InReg))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005450 Flags.setInReg();
Devang Patel05988662008-09-25 21:00:45 +00005451 if (F.paramHasAttr(j, Attribute::StructRet))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005452 Flags.setSRet();
Devang Patel05988662008-09-25 21:00:45 +00005453 if (F.paramHasAttr(j, Attribute::ByVal)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005454 Flags.setByVal();
5455 const PointerType *Ty = cast<PointerType>(I->getType());
5456 const Type *ElementTy = Ty->getElementType();
5457 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00005458 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005459 // For ByVal, alignment should be passed from FE. BE will guess if
5460 // this info is not there but there are cases it cannot get right.
5461 if (F.getParamAlignment(j))
5462 FrameAlign = F.getParamAlignment(j);
5463 Flags.setByValAlign(FrameAlign);
5464 Flags.setByValSize(FrameSize);
5465 }
Devang Patel05988662008-09-25 21:00:45 +00005466 if (F.paramHasAttr(j, Attribute::Nest))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005467 Flags.setNest();
5468 Flags.setOrigAlign(OriginalAlignment);
5469
5470 MVT RegisterVT = getRegisterType(VT);
5471 unsigned NumRegs = getNumRegisters(VT);
5472 for (unsigned i = 0; i != NumRegs; ++i) {
5473 RetVals.push_back(RegisterVT);
5474 ISD::ArgFlagsTy MyFlags = Flags;
5475 if (NumRegs > 1 && i == 0)
5476 MyFlags.setSplit();
5477 // if it isn't first piece, alignment must be 1
5478 else if (i > 0)
5479 MyFlags.setOrigAlign(1);
5480 Ops.push_back(DAG.getArgFlags(MyFlags));
5481 }
5482 }
5483 }
5484
5485 RetVals.push_back(MVT::Other);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005486
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005487 // Create the node.
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005488 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005489 DAG.getVTList(&RetVals[0], RetVals.size()),
5490 &Ops[0], Ops.size()).getNode();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005491
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005492 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5493 // allows exposing the loads that may be part of the argument access to the
5494 // first DAGCombiner pass.
5495 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005496
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005497 // The number of results should match up, except that the lowered one may have
5498 // an extra flag result.
5499 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5500 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5501 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5502 && "Lowering produced unexpected number of results!");
5503
5504 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5505 if (Result != TmpRes.getNode() && Result->use_empty()) {
5506 HandleSDNode Dummy(DAG.getRoot());
5507 DAG.RemoveDeadNode(Result);
5508 }
5509
5510 Result = TmpRes.getNode();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005511
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005512 unsigned NumArgRegs = Result->getNumValues() - 1;
5513 DAG.setRoot(SDValue(Result, NumArgRegs));
5514
5515 // Set up the return result vector.
5516 unsigned i = 0;
5517 unsigned Idx = 1;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005518 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005519 ++I, ++Idx) {
5520 SmallVector<MVT, 4> ValueVTs;
5521 ComputeValueVTs(*this, I->getType(), ValueVTs);
5522 for (unsigned Value = 0, NumValues = ValueVTs.size();
5523 Value != NumValues; ++Value) {
5524 MVT VT = ValueVTs[Value];
5525 MVT PartVT = getRegisterType(VT);
5526
5527 unsigned NumParts = getNumRegisters(VT);
5528 SmallVector<SDValue, 4> Parts(NumParts);
5529 for (unsigned j = 0; j != NumParts; ++j)
5530 Parts[j] = SDValue(Result, i++);
5531
5532 ISD::NodeType AssertOp = ISD::DELETED_NODE;
Devang Patel05988662008-09-25 21:00:45 +00005533 if (F.paramHasAttr(Idx, Attribute::SExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005534 AssertOp = ISD::AssertSext;
Devang Patel05988662008-09-25 21:00:45 +00005535 else if (F.paramHasAttr(Idx, Attribute::ZExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005536 AssertOp = ISD::AssertZext;
5537
Dale Johannesen66978ee2009-01-31 02:22:37 +00005538 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5539 PartVT, VT, AssertOp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005540 }
5541 }
5542 assert(i == NumArgRegs && "Argument register count mismatch!");
5543}
5544
5545
5546/// TargetLowering::LowerCallTo - This is the default LowerCallTo
5547/// implementation, which just inserts an ISD::CALL node, which is later custom
5548/// lowered by the target to something concrete. FIXME: When all targets are
5549/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5550std::pair<SDValue, SDValue>
5551TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5552 bool RetSExt, bool RetZExt, bool isVarArg,
Dale Johannesen86098bd2008-09-26 19:31:26 +00005553 bool isInreg,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005554 unsigned CallingConv, bool isTailCall,
5555 SDValue Callee,
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005556 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
Dan Gohman1937e2f2008-09-16 01:42:28 +00005557 assert((!isTailCall || PerformTailCallOpt) &&
5558 "isTailCall set when tail-call optimizations are disabled!");
5559
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005560 SmallVector<SDValue, 32> Ops;
5561 Ops.push_back(Chain); // Op#0 - Chain
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005562 Ops.push_back(Callee);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005563
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005564 // Handle all of the outgoing arguments.
5565 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5566 SmallVector<MVT, 4> ValueVTs;
5567 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5568 for (unsigned Value = 0, NumValues = ValueVTs.size();
5569 Value != NumValues; ++Value) {
5570 MVT VT = ValueVTs[Value];
5571 const Type *ArgTy = VT.getTypeForMVT();
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005572 SDValue Op = SDValue(Args[i].Node.getNode(),
5573 Args[i].Node.getResNo() + Value);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005574 ISD::ArgFlagsTy Flags;
5575 unsigned OriginalAlignment =
5576 getTargetData()->getABITypeAlignment(ArgTy);
5577
5578 if (Args[i].isZExt)
5579 Flags.setZExt();
5580 if (Args[i].isSExt)
5581 Flags.setSExt();
5582 if (Args[i].isInReg)
5583 Flags.setInReg();
5584 if (Args[i].isSRet)
5585 Flags.setSRet();
5586 if (Args[i].isByVal) {
5587 Flags.setByVal();
5588 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5589 const Type *ElementTy = Ty->getElementType();
5590 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00005591 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005592 // For ByVal, alignment should come from FE. BE will guess if this
5593 // info is not there but there are cases it cannot get right.
5594 if (Args[i].Alignment)
5595 FrameAlign = Args[i].Alignment;
5596 Flags.setByValAlign(FrameAlign);
5597 Flags.setByValSize(FrameSize);
5598 }
5599 if (Args[i].isNest)
5600 Flags.setNest();
5601 Flags.setOrigAlign(OriginalAlignment);
5602
5603 MVT PartVT = getRegisterType(VT);
5604 unsigned NumParts = getNumRegisters(VT);
5605 SmallVector<SDValue, 4> Parts(NumParts);
5606 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5607
5608 if (Args[i].isSExt)
5609 ExtendKind = ISD::SIGN_EXTEND;
5610 else if (Args[i].isZExt)
5611 ExtendKind = ISD::ZERO_EXTEND;
5612
Dale Johannesen66978ee2009-01-31 02:22:37 +00005613 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005614
5615 for (unsigned i = 0; i != NumParts; ++i) {
5616 // if it isn't first piece, alignment must be 1
5617 ISD::ArgFlagsTy MyFlags = Flags;
5618 if (NumParts > 1 && i == 0)
5619 MyFlags.setSplit();
5620 else if (i != 0)
5621 MyFlags.setOrigAlign(1);
5622
5623 Ops.push_back(Parts[i]);
5624 Ops.push_back(DAG.getArgFlags(MyFlags));
5625 }
5626 }
5627 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005628
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005629 // Figure out the result value types. We start by making a list of
5630 // the potentially illegal return value types.
5631 SmallVector<MVT, 4> LoweredRetTys;
5632 SmallVector<MVT, 4> RetTys;
5633 ComputeValueVTs(*this, RetTy, RetTys);
5634
5635 // Then we translate that to a list of legal types.
5636 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5637 MVT VT = RetTys[I];
5638 MVT RegisterVT = getRegisterType(VT);
5639 unsigned NumRegs = getNumRegisters(VT);
5640 for (unsigned i = 0; i != NumRegs; ++i)
5641 LoweredRetTys.push_back(RegisterVT);
5642 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005643
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005644 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005645
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005646 // Create the CALL node.
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005647 SDValue Res = DAG.getCall(CallingConv, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005648 isVarArg, isTailCall, isInreg,
Dan Gohman095cc292008-09-13 01:54:27 +00005649 DAG.getVTList(&LoweredRetTys[0],
5650 LoweredRetTys.size()),
Dale Johannesen86098bd2008-09-26 19:31:26 +00005651 &Ops[0], Ops.size()
5652 );
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005653 Chain = Res.getValue(LoweredRetTys.size() - 1);
5654
5655 // Gather up the call result into a single value.
Dan Gohmanb5cc34d2008-10-07 00:12:37 +00005656 if (RetTy != Type::VoidTy && !RetTys.empty()) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005657 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5658
5659 if (RetSExt)
5660 AssertOp = ISD::AssertSext;
5661 else if (RetZExt)
5662 AssertOp = ISD::AssertZext;
5663
5664 SmallVector<SDValue, 4> ReturnValues;
5665 unsigned RegNo = 0;
5666 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5667 MVT VT = RetTys[I];
5668 MVT RegisterVT = getRegisterType(VT);
5669 unsigned NumRegs = getNumRegisters(VT);
5670 unsigned RegNoEnd = NumRegs + RegNo;
5671 SmallVector<SDValue, 4> Results;
5672 for (; RegNo != RegNoEnd; ++RegNo)
5673 Results.push_back(Res.getValue(RegNo));
5674 SDValue ReturnValue =
Dale Johannesen66978ee2009-01-31 02:22:37 +00005675 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005676 AssertOp);
5677 ReturnValues.push_back(ReturnValue);
5678 }
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005679 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
Duncan Sandsaaffa052008-12-01 11:41:29 +00005680 DAG.getVTList(&RetTys[0], RetTys.size()),
5681 &ReturnValues[0], ReturnValues.size());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005682 }
5683
5684 return std::make_pair(Res, Chain);
5685}
5686
Duncan Sands9fbc7e22009-01-21 09:00:29 +00005687void TargetLowering::LowerOperationWrapper(SDNode *N,
5688 SmallVectorImpl<SDValue> &Results,
5689 SelectionDAG &DAG) {
5690 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
Sanjiv Guptabb326bb2009-01-21 04:48:39 +00005691 if (Res.getNode())
5692 Results.push_back(Res);
5693}
5694
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005695SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5696 assert(0 && "LowerOperation not implemented for this target!");
5697 abort();
5698 return SDValue();
5699}
5700
5701
5702void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5703 SDValue Op = getValue(V);
5704 assert((Op.getOpcode() != ISD::CopyFromReg ||
5705 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5706 "Copy from a reg to the same reg!");
5707 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5708
5709 RegsForValue RFV(TLI, Reg, V->getType());
5710 SDValue Chain = DAG.getEntryNode();
Dale Johannesen66978ee2009-01-31 02:22:37 +00005711 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005712 PendingExports.push_back(Chain);
5713}
5714
5715#include "llvm/CodeGen/SelectionDAGISel.h"
5716
5717void SelectionDAGISel::
5718LowerArguments(BasicBlock *LLVMBB) {
5719 // If this is the entry block, emit arguments.
5720 Function &F = *LLVMBB->getParent();
5721 SDValue OldRoot = SDL->DAG.getRoot();
5722 SmallVector<SDValue, 16> Args;
Dale Johannesen66978ee2009-01-31 02:22:37 +00005723 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005724
5725 unsigned a = 0;
5726 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5727 AI != E; ++AI) {
5728 SmallVector<MVT, 4> ValueVTs;
5729 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5730 unsigned NumValues = ValueVTs.size();
5731 if (!AI->use_empty()) {
5732 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
5733 // If this argument is live outside of the entry block, insert a copy from
5734 // whereever we got it to the vreg that other BB's will reference it as.
5735 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5736 if (VMI != FuncInfo->ValueMap.end()) {
5737 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5738 }
5739 }
5740 a += NumValues;
5741 }
5742
5743 // Finally, if the target has anything special to do, allow it to do so.
5744 // FIXME: this should insert code into the DAG!
5745 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5746}
5747
5748/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5749/// ensure constants are generated when needed. Remember the virtual registers
5750/// that need to be added to the Machine PHI nodes as input. We cannot just
5751/// directly add them, because expansion might result in multiple MBB's for one
5752/// BB. As such, the start of the BB might correspond to a different MBB than
5753/// the end.
5754///
5755void
5756SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5757 TerminatorInst *TI = LLVMBB->getTerminator();
5758
5759 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5760
5761 // Check successor nodes' PHI nodes that expect a constant to be available
5762 // from this block.
5763 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5764 BasicBlock *SuccBB = TI->getSuccessor(succ);
5765 if (!isa<PHINode>(SuccBB->begin())) continue;
5766 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005767
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005768 // If this terminator has multiple identical successors (common for
5769 // switches), only handle each succ once.
5770 if (!SuccsHandled.insert(SuccMBB)) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005771
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005772 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5773 PHINode *PN;
5774
5775 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5776 // nodes and Machine PHI nodes, but the incoming operands have not been
5777 // emitted yet.
5778 for (BasicBlock::iterator I = SuccBB->begin();
5779 (PN = dyn_cast<PHINode>(I)); ++I) {
5780 // Ignore dead phi's.
5781 if (PN->use_empty()) continue;
5782
5783 unsigned Reg;
5784 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5785
5786 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5787 unsigned &RegOut = SDL->ConstantsOut[C];
5788 if (RegOut == 0) {
5789 RegOut = FuncInfo->CreateRegForValue(C);
5790 SDL->CopyValueToVirtualRegister(C, RegOut);
5791 }
5792 Reg = RegOut;
5793 } else {
5794 Reg = FuncInfo->ValueMap[PHIOp];
5795 if (Reg == 0) {
5796 assert(isa<AllocaInst>(PHIOp) &&
5797 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5798 "Didn't codegen value into a register!??");
5799 Reg = FuncInfo->CreateRegForValue(PHIOp);
5800 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5801 }
5802 }
5803
5804 // Remember that this register needs to added to the machine PHI node as
5805 // the input for this MBB.
5806 SmallVector<MVT, 4> ValueVTs;
5807 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5808 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5809 MVT VT = ValueVTs[vti];
5810 unsigned NumRegisters = TLI.getNumRegisters(VT);
5811 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5812 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5813 Reg += NumRegisters;
5814 }
5815 }
5816 }
5817 SDL->ConstantsOut.clear();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005818}
5819
Dan Gohman3df24e62008-09-03 23:12:08 +00005820/// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5821/// supports legal types, and it emits MachineInstrs directly instead of
5822/// creating SelectionDAG nodes.
5823///
5824bool
5825SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5826 FastISel *F) {
5827 TerminatorInst *TI = LLVMBB->getTerminator();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005828
Dan Gohman3df24e62008-09-03 23:12:08 +00005829 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5830 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5831
5832 // Check successor nodes' PHI nodes that expect a constant to be available
5833 // from this block.
5834 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5835 BasicBlock *SuccBB = TI->getSuccessor(succ);
5836 if (!isa<PHINode>(SuccBB->begin())) continue;
5837 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005838
Dan Gohman3df24e62008-09-03 23:12:08 +00005839 // If this terminator has multiple identical successors (common for
5840 // switches), only handle each succ once.
5841 if (!SuccsHandled.insert(SuccMBB)) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005842
Dan Gohman3df24e62008-09-03 23:12:08 +00005843 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5844 PHINode *PN;
5845
5846 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5847 // nodes and Machine PHI nodes, but the incoming operands have not been
5848 // emitted yet.
5849 for (BasicBlock::iterator I = SuccBB->begin();
5850 (PN = dyn_cast<PHINode>(I)); ++I) {
5851 // Ignore dead phi's.
5852 if (PN->use_empty()) continue;
5853
5854 // Only handle legal types. Two interesting things to note here. First,
5855 // by bailing out early, we may leave behind some dead instructions,
5856 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5857 // own moves. Second, this check is necessary becuase FastISel doesn't
5858 // use CreateRegForValue to create registers, so it always creates
5859 // exactly one register for each non-void instruction.
5860 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5861 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
Dan Gohman74321ab2008-09-10 21:01:31 +00005862 // Promote MVT::i1.
5863 if (VT == MVT::i1)
5864 VT = TLI.getTypeToTransformTo(VT);
5865 else {
5866 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5867 return false;
5868 }
Dan Gohman3df24e62008-09-03 23:12:08 +00005869 }
5870
5871 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5872
5873 unsigned Reg = F->getRegForValue(PHIOp);
5874 if (Reg == 0) {
5875 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5876 return false;
5877 }
5878 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
5879 }
5880 }
5881
5882 return true;
5883}