blob: 38360123e5e75aa82b3b264c3a02053b737d1d93 [file] [log] [blame]
Stéphane Marchesin25a26062014-09-12 16:18:59 -07001/*
Daniele Castagna7a755de2016-12-16 17:32:30 -05002 * Copyright 2014 The Chromium OS Authors. All rights reserved.
Stéphane Marchesin25a26062014-09-12 16:18:59 -07003 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Gurchetan Singh46faf6b2016-08-05 14:40:07 -07007#ifdef DRV_I915
Stéphane Marchesin25a26062014-09-12 16:18:59 -07008
9#include <errno.h>
Gurchetan Singh82a8eed2017-01-03 13:01:37 -080010#include <i915_drm.h>
Gurchetan Singhcc015e82017-01-17 16:15:25 -080011#include <stdio.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070012#include <string.h>
Gurchetan Singhef920532016-08-12 16:38:25 -070013#include <sys/mman.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070014#include <xf86drm.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070015
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070016#include "drv_priv.h"
Stéphane Marchesin25a26062014-09-12 16:18:59 -070017#include "helpers.h"
18#include "util.h"
19
Gurchetan Singh68af9c22017-01-18 13:48:11 -080020#define I915_CACHELINE_SIZE 64
21#define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
22
Daniele Castagna7a2df902017-10-18 16:15:44 -040023static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB1555,
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070024 DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
Daniele Castagna7a2df902017-10-18 16:15:44 -040025 DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888,
26 DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB2101010,
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070027 DRM_FORMAT_XRGB8888 };
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080028
Dongseong Hwang750e0b92017-06-07 15:17:25 -070029static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_NV12,
30 DRM_FORMAT_R8, DRM_FORMAT_UYVY,
31 DRM_FORMAT_YUYV };
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070032
33static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
Gurchetan Singh179687e2016-10-28 10:07:35 -070034
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080035struct i915_device {
Gurchetan Singh68af9c22017-01-18 13:48:11 -080036 uint32_t gen;
37 int32_t has_llc;
Stéphane Marchesin25a26062014-09-12 16:18:59 -070038};
39
Gurchetan Singh68af9c22017-01-18 13:48:11 -080040static uint32_t i915_get_gen(int device_id)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070041{
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080042 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
43 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
Stéphane Marchesina39dfde2014-09-15 15:38:25 -070044 unsigned i;
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080045 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070046 if (gen3_ids[i] == device_id)
47 return 3;
48
49 return 4;
50}
51
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080052static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
53{
54 uint32_t i;
55 struct combination *combo;
56
57 /*
58 * Older hardware can't scanout Y-tiled formats. Newer devices can, and
59 * report this functionality via format modifiers.
60 */
Ege Mihmanli96b7d462017-09-19 20:13:26 -070061 for (i = 0; i < drv->combos.size; i++) {
62 combo = &drv->combos.data[i];
Tomasz Figae821cc22017-07-08 15:53:11 +090063 if (combo->format != item->format)
64 continue;
65
Kristian H. Kristensenbc8c5932017-10-24 18:36:32 -070066 if (item->modifier == DRM_FORMAT_MOD_INVALID &&
Tomasz Figae821cc22017-07-08 15:53:11 +090067 combo->metadata.tiling == I915_TILING_X) {
68 /*
69 * FIXME: drv_query_kms() does not report the available modifiers
70 * yet, but we know that all hardware can scanout from X-tiled
71 * buffers, so let's add this to our combinations, except for
72 * cursor, which must not be tiled.
73 */
Gurchetan Singha1892b22017-09-28 16:40:52 -070074 combo->use_flags |= item->use_flags & ~BO_USE_CURSOR;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080075 }
Tomasz Figae821cc22017-07-08 15:53:11 +090076
77 if (combo->metadata.modifier == item->modifier)
Gurchetan Singha1892b22017-09-28 16:40:52 -070078 combo->use_flags |= item->use_flags;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080079 }
80
81 return 0;
82}
83
84static int i915_add_combinations(struct driver *drv)
85{
86 int ret;
87 uint32_t i, num_items;
88 struct kms_item *items;
89 struct format_metadata metadata;
Gurchetan Singha1892b22017-09-28 16:40:52 -070090 uint64_t render_use_flags, texture_use_flags;
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070091
Gurchetan Singha1892b22017-09-28 16:40:52 -070092 render_use_flags = BO_USE_RENDER_MASK;
93 texture_use_flags = BO_USE_TEXTURE_MASK;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080094
95 metadata.tiling = I915_TILING_NONE;
96 metadata.priority = 1;
Kristian H. Kristensenbc8c5932017-10-24 18:36:32 -070097 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080098
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070099 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
Gurchetan Singha1892b22017-09-28 16:40:52 -0700100 &metadata, render_use_flags);
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800101 if (ret)
102 return ret;
103
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700104 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
Gurchetan Singha1892b22017-09-28 16:40:52 -0700105 &metadata, texture_use_flags);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700106 if (ret)
107 return ret;
108
109 ret = drv_add_combinations(drv, tileable_texture_source_formats,
Dongseong Hwang3c5be5a2017-06-14 10:47:11 -0700110 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
Gurchetan Singha1892b22017-09-28 16:40:52 -0700111 texture_use_flags);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800112 if (ret)
113 return ret;
114
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800115 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
116 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800117
Tomasz Figad30c0a52017-07-05 17:50:18 +0900118 /* IPU3 camera ISP supports only NV12 output. */
119 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
Tomasz Figafd0b0162017-07-11 18:28:02 +0900120 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
Tomasz Figad30c0a52017-07-05 17:50:18 +0900121 /*
122 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
123 * from camera.
124 */
125 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
Tomasz Figafd0b0162017-07-11 18:28:02 +0900126 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
Tomasz Figad30c0a52017-07-05 17:50:18 +0900127
Gurchetan Singha1892b22017-09-28 16:40:52 -0700128 render_use_flags &= ~BO_USE_RENDERSCRIPT;
129 render_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
130 render_use_flags &= ~BO_USE_SW_READ_OFTEN;
131 render_use_flags &= ~BO_USE_LINEAR;
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700132
Gurchetan Singha1892b22017-09-28 16:40:52 -0700133 texture_use_flags &= ~BO_USE_RENDERSCRIPT;
134 texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
135 texture_use_flags &= ~BO_USE_SW_READ_OFTEN;
136 texture_use_flags &= ~BO_USE_LINEAR;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800137
138 metadata.tiling = I915_TILING_X;
139 metadata.priority = 2;
Tomasz Figae821cc22017-07-08 15:53:11 +0900140 metadata.modifier = I915_FORMAT_MOD_X_TILED;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800141
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700142 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
Gurchetan Singha1892b22017-09-28 16:40:52 -0700143 &metadata, render_use_flags);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700144 if (ret)
145 return ret;
146
147 ret = drv_add_combinations(drv, tileable_texture_source_formats,
148 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
Gurchetan Singha1892b22017-09-28 16:40:52 -0700149 texture_use_flags);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800150 if (ret)
151 return ret;
152
153 metadata.tiling = I915_TILING_Y;
154 metadata.priority = 3;
Tomasz Figae821cc22017-07-08 15:53:11 +0900155 metadata.modifier = I915_FORMAT_MOD_Y_TILED;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800156
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700157 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
Gurchetan Singha1892b22017-09-28 16:40:52 -0700158 &metadata, render_use_flags);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700159 if (ret)
160 return ret;
161
162 ret = drv_add_combinations(drv, tileable_texture_source_formats,
163 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
Gurchetan Singha1892b22017-09-28 16:40:52 -0700164 texture_use_flags);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800165 if (ret)
166 return ret;
167
168 items = drv_query_kms(drv, &num_items);
169 if (!items || !num_items)
170 return 0;
171
172 for (i = 0; i < num_items; i++) {
173 ret = i915_add_kms_item(drv, &items[i]);
174 if (ret) {
175 free(items);
176 return ret;
177 }
178 }
179
180 free(items);
181 return 0;
182}
183
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800184static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
185 uint32_t *aligned_height)
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700186{
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700187 struct i915_device *i915 = bo->drv->priv;
188 uint32_t horizontal_alignment = 4;
189 uint32_t vertical_alignment = 4;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700190
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700191 switch (tiling) {
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700192 default:
193 case I915_TILING_NONE:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700194 horizontal_alignment = 64;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700195 break;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800196
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700197 case I915_TILING_X:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700198 horizontal_alignment = 512;
199 vertical_alignment = 8;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700200 break;
201
202 case I915_TILING_Y:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700203 if (i915->gen == 3) {
204 horizontal_alignment = 512;
205 vertical_alignment = 8;
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800206 } else {
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700207 horizontal_alignment = 128;
208 vertical_alignment = 32;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700209 }
210 break;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700211 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800212
Tomasz Figa33615a52017-07-29 15:37:58 +0900213 /*
214 * The alignment calculated above is based on the full size luma plane and to have chroma
215 * planes properly aligned with subsampled formats, we need to multiply luma alignment by
216 * subsampling factor.
217 */
218 switch (bo->format) {
219 case DRM_FORMAT_YVU420_ANDROID:
220 case DRM_FORMAT_YVU420:
221 horizontal_alignment *= 2;
Gurchetan Singh7dcdff12017-09-14 13:04:11 -0700222 /* Fall through */
Tomasz Figa33615a52017-07-29 15:37:58 +0900223 case DRM_FORMAT_NV12:
224 vertical_alignment *= 2;
225 break;
226 }
227
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700228 *aligned_height = ALIGN(bo->height, vertical_alignment);
229 if (i915->gen > 3) {
230 *stride = ALIGN(*stride, horizontal_alignment);
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800231 } else {
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700232 while (*stride > horizontal_alignment)
233 horizontal_alignment <<= 1;
234
235 *stride = horizontal_alignment;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800236 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800237
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700238 if (i915->gen <= 3 && *stride > 8192)
239 return -EINVAL;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800240
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700241 return 0;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700242}
243
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800244static void i915_clflush(void *start, size_t size)
245{
246 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
247 void *end = (void *)((uintptr_t)start + size);
248
249 __builtin_ia32_mfence();
250 while (p < end) {
251 __builtin_ia32_clflush(p);
252 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
253 }
254}
255
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800256static int i915_init(struct driver *drv)
257{
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800258 int ret;
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800259 int device_id;
260 struct i915_device *i915;
261 drm_i915_getparam_t get_param;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800262
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800263 i915 = calloc(1, sizeof(*i915));
264 if (!i915)
265 return -ENOMEM;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800266
267 memset(&get_param, 0, sizeof(get_param));
268 get_param.param = I915_PARAM_CHIPSET_ID;
269 get_param.value = &device_id;
270 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
271 if (ret) {
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800272 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800273 free(i915);
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800274 return -EINVAL;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800275 }
276
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800277 i915->gen = i915_get_gen(device_id);
278
279 memset(&get_param, 0, sizeof(get_param));
280 get_param.param = I915_PARAM_HAS_LLC;
281 get_param.value = &i915->has_llc;
282 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
283 if (ret) {
284 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
285 free(i915);
286 return -EINVAL;
287 }
288
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800289 drv->priv = i915;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800290
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800291 return i915_add_combinations(drv);
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800292}
293
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800294static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
Gurchetan Singha1892b22017-09-28 16:40:52 -0700295 uint64_t use_flags)
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700296{
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700297 int ret;
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800298 size_t plane;
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700299 uint32_t stride;
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800300 struct drm_i915_gem_create gem_create;
301 struct drm_i915_gem_set_tiling gem_set_tiling;
Tomasz Figa7ec07882017-06-23 18:04:02 +0900302 struct combination *combo;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700303
Gurchetan Singha1892b22017-09-28 16:40:52 -0700304 combo = drv_get_combination(bo->drv, format, use_flags);
Tomasz Figa7ec07882017-06-23 18:04:02 +0900305 if (!combo)
306 return -EINVAL;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700307
Tomasz Figa7ec07882017-06-23 18:04:02 +0900308 bo->tiling = combo->metadata.tiling;
Owen Linbbb69fd2017-06-05 14:33:08 +0800309
310 stride = drv_stride_from_format(format, width, 0);
Gurchetan Singh507f5dd2017-03-16 13:14:30 -0700311
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800312 ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700313 if (ret)
314 return ret;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800315
Owen Linbbb69fd2017-06-05 14:33:08 +0800316 /*
Tomasz Figad846de62017-07-29 15:47:54 +0900317 * HAL_PIXEL_FORMAT_YV12 requires the buffer height not be aligned, but we need to keep
318 * total size as with aligned height to ensure enough padding space after each plane to
319 * satisfy GPU alignment requirements.
320 *
321 * We do it by first calling drv_bo_from_format() with aligned height and
322 * DRM_FORMAT_YVU420, which allows height alignment, saving the total size it calculates
323 * and then calling it again with requested parameters.
324 *
325 * This relies on the fact that i965 driver uses separate surfaces for each plane and
326 * contents of padding bytes is not affected, as it is only used to satisfy GPU cache
327 * requests.
328 *
329 * This is enforced by Mesa in src/intel/isl/isl_gen8.c, inside
330 * isl_gen8_choose_image_alignment_el(), which is used for GEN9 and GEN8.
Owen Linbbb69fd2017-06-05 14:33:08 +0800331 */
Tomasz Figad846de62017-07-29 15:47:54 +0900332 if (format == DRM_FORMAT_YVU420_ANDROID) {
333 uint32_t unaligned_height = bo->height;
334 size_t total_size;
Owen Linbbb69fd2017-06-05 14:33:08 +0800335
Tomasz Figad846de62017-07-29 15:47:54 +0900336 drv_bo_from_format(bo, stride, height, DRM_FORMAT_YVU420);
337 total_size = bo->total_size;
338 drv_bo_from_format(bo, stride, unaligned_height, format);
339 bo->total_size = total_size;
340 } else {
341 drv_bo_from_format(bo, stride, height, format);
342 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800343
Tomasz Figa581f3a52017-07-23 15:02:19 +0900344 /*
345 * Quoting Mesa ISL library:
346 *
347 * - For linear surfaces, additional padding of 64 bytes is required at
348 * the bottom of the surface. This is in addition to the padding
349 * required above.
350 */
351 if (bo->tiling == I915_TILING_NONE)
352 bo->total_size += 64;
353
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800354 memset(&gem_create, 0, sizeof(gem_create));
355 gem_create.size = bo->total_size;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800356
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800357 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
358 if (ret) {
359 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
360 gem_create.size);
361 return ret;
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -0700362 }
Gurchetan Singh83dc4fb2016-07-19 15:52:33 -0700363
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800364 for (plane = 0; plane < bo->num_planes; plane++)
365 bo->handles[plane].u32 = gem_create.handle;
Daniel Nicoara1de26dc2014-09-25 18:53:19 -0400366
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800367 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
368 gem_set_tiling.handle = bo->handles[0].u32;
369 gem_set_tiling.tiling_mode = bo->tiling;
370 gem_set_tiling.stride = bo->strides[0];
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700371
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800372 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
373 if (ret) {
374 struct drm_gem_close gem_close;
375 memset(&gem_close, 0, sizeof(gem_close));
376 gem_close.handle = bo->handles[0].u32;
377 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800378
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800379 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700380 return -errno;
381 }
382
383 return 0;
384}
385
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800386static void i915_close(struct driver *drv)
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800387{
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800388 free(drv->priv);
389 drv->priv = NULL;
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800390}
391
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800392static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
393{
394 int ret;
395 struct drm_i915_gem_get_tiling gem_get_tiling;
396
397 ret = drv_prime_bo_import(bo, data);
398 if (ret)
399 return ret;
400
401 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
402 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
403 gem_get_tiling.handle = bo->handles[0].u32;
404
405 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
406 if (ret) {
Joe Kniss9e5d12a2017-06-29 11:54:22 -0700407 drv_gem_bo_destroy(bo);
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800408 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
409 return ret;
410 }
411
412 bo->tiling = gem_get_tiling.tiling_mode;
413 return 0;
414}
415
Gurchetan Singhcfb88762017-09-28 17:14:50 -0700416static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
Gurchetan Singhef920532016-08-12 16:38:25 -0700417{
418 int ret;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800419 void *addr;
Gurchetan Singhef920532016-08-12 16:38:25 -0700420
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800421 if (bo->tiling == I915_TILING_NONE) {
422 struct drm_i915_gem_mmap gem_map;
423 memset(&gem_map, 0, sizeof(gem_map));
Gurchetan Singhef920532016-08-12 16:38:25 -0700424
Gurchetan Singha1892b22017-09-28 16:40:52 -0700425 if ((bo->use_flags & BO_USE_SCANOUT) && !(bo->use_flags & BO_USE_RENDERSCRIPT))
Gurchetan Singh5af20232017-09-19 15:10:58 -0700426 gem_map.flags = I915_MMAP_WC;
427
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800428 gem_map.handle = bo->handles[0].u32;
429 gem_map.offset = 0;
430 gem_map.size = bo->total_size;
431
432 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
433 if (ret) {
434 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
435 return MAP_FAILED;
436 }
437
438 addr = (void *)(uintptr_t)gem_map.addr_ptr;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800439 } else {
440 struct drm_i915_gem_mmap_gtt gem_map;
441 memset(&gem_map, 0, sizeof(gem_map));
442
443 gem_map.handle = bo->handles[0].u32;
444
445 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
446 if (ret) {
447 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
448 return MAP_FAILED;
449 }
450
Gurchetan Singhcfb88762017-09-28 17:14:50 -0700451 addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
452 gem_map.offset);
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800453 }
454
455 if (addr == MAP_FAILED) {
456 fprintf(stderr, "drv: i915 GEM mmap failed\n");
457 return addr;
458 }
459
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800460 data->length = bo->total_size;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800461 return addr;
462}
Gurchetan Singh1a31e602016-10-06 10:58:00 -0700463
Gurchetan Singh2d1877f2017-10-10 14:12:46 -0700464static int i915_bo_invalidate(struct bo *bo, struct map_info *data)
465{
466 int ret;
467 struct drm_i915_gem_set_domain set_domain;
468
469 memset(&set_domain, 0, sizeof(set_domain));
470 set_domain.handle = bo->handles[0].u32;
471 if (bo->tiling == I915_TILING_NONE) {
472 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
473 if (data->map_flags & BO_MAP_WRITE)
474 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
475 } else {
476 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
477 if (data->map_flags & BO_MAP_WRITE)
478 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
479 }
480
481 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
482 if (ret) {
483 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
484 return ret;
485 }
486
487 return 0;
488}
489
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700490static int i915_bo_flush(struct bo *bo, struct map_info *data)
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800491{
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800492 struct i915_device *i915 = bo->drv->priv;
493 if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
494 i915_clflush(data->addr, data->length);
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800495
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700496 return 0;
Gurchetan Singhef920532016-08-12 16:38:25 -0700497}
498
Gurchetan Singha1892b22017-09-28 16:40:52 -0700499static uint32_t i915_resolve_format(uint32_t format, uint64_t use_flags)
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700500{
501 switch (format) {
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800502 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
Tomasz Figad30c0a52017-07-05 17:50:18 +0900503 /* KBL camera subsystem requires NV12. */
Gurchetan Singha1892b22017-09-28 16:40:52 -0700504 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
Tomasz Figad30c0a52017-07-05 17:50:18 +0900505 return DRM_FORMAT_NV12;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700506 /*HACK: See b/28671744 */
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800507 return DRM_FORMAT_XBGR8888;
508 case DRM_FORMAT_FLEX_YCbCr_420_888:
Tomasz Figad30c0a52017-07-05 17:50:18 +0900509 /* KBL camera subsystem requires NV12. */
Gurchetan Singha1892b22017-09-28 16:40:52 -0700510 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
Tomasz Figad30c0a52017-07-05 17:50:18 +0900511 return DRM_FORMAT_NV12;
Owen Linbbb69fd2017-06-05 14:33:08 +0800512 return DRM_FORMAT_YVU420;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700513 default:
514 return format;
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700515 }
516}
517
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800518struct backend backend_i915 = {
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700519 .name = "i915",
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700520 .init = i915_init,
521 .close = i915_close,
522 .bo_create = i915_bo_create,
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800523 .bo_destroy = drv_gem_bo_destroy,
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800524 .bo_import = i915_bo_import,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700525 .bo_map = i915_bo_map,
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700526 .bo_unmap = drv_bo_munmap,
Gurchetan Singh2d1877f2017-10-10 14:12:46 -0700527 .bo_invalidate = i915_bo_invalidate,
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700528 .bo_flush = i915_bo_flush,
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700529 .resolve_format = i915_resolve_format,
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700530};
531
532#endif