Add Om1 lowering with no optimizations.
This adds infrastructure for low-level x86-32 instructions, and the target lowering patterns.
Practically no optimizations are performed. Optimizations to be introduced later include liveness analysis, dead-code elimination, global linear-scan register allocation, linear-scan based stack slot coalescing, and compare/branch fusing. One optimization that is present is simple coalescing of stack slots for variables that are only live within a single basic block.
There are also some fairly comprehensive cross tests. This testing infrastructure translates bitcode using both Subzero and llc, and a testing harness calls both versions with a variety of "interesting" inputs and compares the results. Specifically, Arithmetic, Icmp, Fcmp, and Cast instructions are tested this way, across all PNaCl primitive types.
BUG=
R=jvoung@chromium.org
Review URL: https://codereview.chromium.org/265703002
diff --git a/src/IceCfg.cpp b/src/IceCfg.cpp
index f2b1cc9..3d720fa 100644
--- a/src/IceCfg.cpp
+++ b/src/IceCfg.cpp
@@ -17,13 +17,16 @@
#include "IceDefs.h"
#include "IceInst.h"
#include "IceOperand.h"
+#include "IceTargetLowering.h"
namespace Ice {
Cfg::Cfg(GlobalContext *Ctx)
: Ctx(Ctx), FunctionName(""), ReturnType(IceType_void),
IsInternalLinkage(false), HasError(false), ErrorMessage(""), Entry(NULL),
- NextInstNumber(1), CurrentNode(NULL) {}
+ NextInstNumber(1),
+ Target(TargetLowering::createLowering(Ctx->getTargetArch(), this)),
+ CurrentNode(NULL) {}
Cfg::~Cfg() {}
@@ -54,14 +57,107 @@
Args.push_back(Arg);
}
+// Returns whether the stack frame layout has been computed yet. This
+// is used for dumping the stack frame location of Variables.
+bool Cfg::hasComputedFrame() const { return getTarget()->hasComputedFrame(); }
+
+void Cfg::translate() {
+ Ostream &Str = Ctx->getStrDump();
+ if (hasError())
+ return;
+
+ if (Ctx->isVerbose()) {
+ Str << "================ Initial CFG ================\n";
+ dump();
+ }
+
+ Timer T_translate;
+ // The set of translation passes and their order are determined by
+ // the target.
+ getTarget()->translate();
+ T_translate.printElapsedUs(getContext(), "translate()");
+
+ if (Ctx->isVerbose()) {
+ Str << "================ Final output ================\n";
+ dump();
+ }
+}
+
void Cfg::computePredecessors() {
for (NodeList::iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
(*I)->computePredecessors();
}
}
+// placePhiLoads() must be called before placePhiStores().
+void Cfg::placePhiLoads() {
+ for (NodeList::iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
+ (*I)->placePhiLoads();
+ }
+}
+
+// placePhiStores() must be called after placePhiLoads().
+void Cfg::placePhiStores() {
+ for (NodeList::iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
+ (*I)->placePhiStores();
+ }
+}
+
+void Cfg::deletePhis() {
+ for (NodeList::iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
+ (*I)->deletePhis();
+ }
+}
+
+void Cfg::genCode() {
+ for (NodeList::iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
+ (*I)->genCode();
+ }
+}
+
+// Compute the stack frame layout.
+void Cfg::genFrame() {
+ getTarget()->addProlog(Entry);
+ // TODO: Consider folding epilog generation into the final
+ // emission/assembly pass to avoid an extra iteration over the node
+ // list. Or keep a separate list of exit nodes.
+ for (NodeList::iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
+ CfgNode *Node = *I;
+ if (Node->getHasReturn())
+ getTarget()->addEpilog(Node);
+ }
+}
+
// ======================== Dump routines ======================== //
+void Cfg::emit() {
+ Ostream &Str = Ctx->getStrEmit();
+ Timer T_emit;
+ if (!Ctx->testAndSetHasEmittedFirstMethod()) {
+ // Print a helpful command for assembling the output.
+ // TODO: have the Target emit the header
+ // TODO: need a per-file emit in addition to per-CFG
+ Str << "# $LLVM_BIN_PATH/llvm-mc"
+ << " -arch=x86"
+ << " -x86-asm-syntax=intel"
+ << " -filetype=obj"
+ << " -o=MyObj.o"
+ << "\n\n";
+ }
+ Str << "\t.text\n";
+ if (!getInternal()) {
+ IceString MangledName = getContext()->mangleName(getFunctionName());
+ Str << "\t.globl\t" << MangledName << "\n";
+ Str << "\t.type\t" << MangledName << ",@function\n";
+ }
+ for (NodeList::const_iterator I = Nodes.begin(), E = Nodes.end(); I != E;
+ ++I) {
+ (*I)->emit(this);
+ }
+ Str << "\n";
+ T_emit.printElapsedUs(Ctx, "emit()");
+}
+
void Cfg::dump() {
Ostream &Str = Ctx->getStrDump();
setCurrentNode(getEntryNode());
diff --git a/src/IceCfg.h b/src/IceCfg.h
index 05e1e3b..5f3bfd3 100644
--- a/src/IceCfg.h
+++ b/src/IceCfg.h
@@ -58,7 +58,7 @@
const NodeList &getNodes() const { return Nodes; }
// Manage instruction numbering.
- int newInstNumber() { return NextInstNumber++; }
+ int32_t newInstNumber() { return NextInstNumber++; }
// Manage Variables.
Variable *makeVariable(Type Ty, const CfgNode *Node,
@@ -70,16 +70,28 @@
void addArg(Variable *Arg);
const VarList &getArgs() const { return Args; }
+ // Miscellaneous accessors.
+ TargetLowering *getTarget() const { return Target.get(); }
+ bool hasComputedFrame() const;
+
+ // Passes over the CFG.
+ void translate();
// After the CFG is fully constructed, iterate over the nodes and
// compute the predecessor edges, in the form of
// CfgNode::InEdges[].
void computePredecessors();
+ void placePhiLoads();
+ void placePhiStores();
+ void deletePhis();
+ void genCode();
+ void genFrame();
// Manage the CurrentNode field, which is used for validating the
// Variable::DefNode field during dumping/emitting.
void setCurrentNode(const CfgNode *Node) { CurrentNode = Node; }
const CfgNode *getCurrentNode() const { return CurrentNode; }
+ void emit();
void dump();
// Allocate data of type T using the per-Cfg allocator.
@@ -124,9 +136,10 @@
IceString ErrorMessage;
CfgNode *Entry; // entry basic block
NodeList Nodes; // linearized node list; Entry should be first
- int NextInstNumber;
+ int32_t NextInstNumber;
VarList Variables;
VarList Args; // subset of Variables, in argument order
+ llvm::OwningPtr<TargetLowering> Target;
// CurrentNode is maintained during dumping/emitting just for
// validating Variable::DefNode. Normally, a traversal over
diff --git a/src/IceCfgNode.cpp b/src/IceCfgNode.cpp
index fe8b70e..c00b2c7 100644
--- a/src/IceCfgNode.cpp
+++ b/src/IceCfgNode.cpp
@@ -7,8 +7,8 @@
//
//===----------------------------------------------------------------------===//
//
-// This file implements the CfgNode class, including the
-// complexities of instruction insertion and in-edge calculation.
+// This file implements the CfgNode class, including the complexities
+// of instruction insertion and in-edge calculation.
//
//===----------------------------------------------------------------------===//
@@ -16,11 +16,12 @@
#include "IceCfgNode.h"
#include "IceInst.h"
#include "IceOperand.h"
+#include "IceTargetLowering.h"
namespace Ice {
CfgNode::CfgNode(Cfg *Func, SizeT LabelNumber, IceString Name)
- : Func(Func), Number(LabelNumber), Name(Name) {}
+ : Func(Func), Number(LabelNumber), Name(Name), HasReturn(false) {}
// Returns the name the node was created with. If no name was given,
// it synthesizes a (hopefully) unique name.
@@ -61,8 +62,135 @@
}
}
+// This does part 1 of Phi lowering, by creating a new dest variable
+// for each Phi instruction, replacing the Phi instruction's dest with
+// that variable, and adding an explicit assignment of the old dest to
+// the new dest. For example,
+// a=phi(...)
+// changes to
+// "a_phi=phi(...); a=a_phi".
+//
+// This is in preparation for part 2 which deletes the Phi
+// instructions and appends assignment instructions to predecessor
+// blocks. Note that this transformation preserves SSA form.
+void CfgNode::placePhiLoads() {
+ for (PhiList::iterator I = Phis.begin(), E = Phis.end(); I != E; ++I) {
+ Inst *Inst = (*I)->lower(Func, this);
+ Insts.insert(Insts.begin(), Inst);
+ Inst->updateVars(this);
+ }
+}
+
+// This does part 2 of Phi lowering. For each Phi instruction at each
+// out-edge, create a corresponding assignment instruction, and add
+// all the assignments near the end of this block. They need to be
+// added before any branch instruction, and also if the block ends
+// with a compare instruction followed by a branch instruction that we
+// may want to fuse, it's better to insert the new assignments before
+// the compare instruction.
+//
+// Note that this transformation takes the Phi dest variables out of
+// SSA form, as there may be assignments to the dest variable in
+// multiple blocks.
+//
+// TODO: Defer this pass until after register allocation, then split
+// critical edges, add the assignments, and lower them. This should
+// reduce the amount of shuffling at the end of each block.
+void CfgNode::placePhiStores() {
+ // Find the insertion point. TODO: After branch/compare fusing is
+ // implemented, try not to insert Phi stores between the compare and
+ // conditional branch instructions, otherwise the branch/compare
+ // pattern matching may fail. However, the branch/compare sequence
+ // will have to be broken if the compare result is read (by the
+ // assignment) before it is written (by the compare).
+ InstList::iterator InsertionPoint = Insts.end();
+ // Every block must end in a terminator instruction.
+ assert(InsertionPoint != Insts.begin());
+ --InsertionPoint;
+ // Confirm via assert() that InsertionPoint is a terminator
+ // instruction. Calling getTerminatorEdges() on a non-terminator
+ // instruction will cause an llvm_unreachable().
+ assert(((*InsertionPoint)->getTerminatorEdges(), true));
+
+ // Consider every out-edge.
+ for (NodeList::const_iterator I1 = OutEdges.begin(), E1 = OutEdges.end();
+ I1 != E1; ++I1) {
+ CfgNode *Target = *I1;
+ // Consider every Phi instruction at the out-edge.
+ for (PhiList::const_iterator I2 = Target->Phis.begin(),
+ E2 = Target->Phis.end();
+ I2 != E2; ++I2) {
+ Operand *Operand = (*I2)->getOperandForTarget(this);
+ assert(Operand);
+ Variable *Dest = (*I2)->getDest();
+ assert(Dest);
+ InstAssign *NewInst = InstAssign::create(Func, Dest, Operand);
+ // If Src is a variable, set the Src and Dest variables to
+ // prefer each other for register allocation.
+ if (Variable *Src = llvm::dyn_cast<Variable>(Operand)) {
+ bool AllowOverlap = false;
+ Dest->setPreferredRegister(Src, AllowOverlap);
+ Src->setPreferredRegister(Dest, AllowOverlap);
+ }
+ Insts.insert(InsertionPoint, NewInst);
+ NewInst->updateVars(this);
+ }
+ }
+}
+
+// Deletes the phi instructions after the loads and stores are placed.
+void CfgNode::deletePhis() {
+ for (PhiList::iterator I = Phis.begin(), E = Phis.end(); I != E; ++I) {
+ (*I)->setDeleted();
+ }
+}
+
+// Drives the target lowering. Passes the current instruction and the
+// next non-deleted instruction for target lowering.
+void CfgNode::genCode() {
+ TargetLowering *Target = Func->getTarget();
+ LoweringContext &Context = Target->getContext();
+ // Lower only the regular instructions. Defer the Phi instructions.
+ Context.init(this);
+ while (!Context.atEnd()) {
+ InstList::iterator Orig = Context.getCur();
+ if (llvm::isa<InstRet>(*Orig))
+ setHasReturn();
+ Target->lower();
+ // Ensure target lowering actually moved the cursor.
+ assert(Context.getCur() != Orig);
+ }
+}
+
// ======================== Dump routines ======================== //
+void CfgNode::emit(Cfg *Func) const {
+ Func->setCurrentNode(this);
+ Ostream &Str = Func->getContext()->getStrEmit();
+ if (Func->getEntryNode() == this) {
+ Str << Func->getContext()->mangleName(Func->getFunctionName()) << ":\n";
+ }
+ Str << getAsmName() << ":\n";
+ for (PhiList::const_iterator I = Phis.begin(), E = Phis.end(); I != E; ++I) {
+ InstPhi *Inst = *I;
+ if (Inst->isDeleted())
+ continue;
+ // Emitting a Phi instruction should cause an error.
+ Inst->emit(Func);
+ }
+ for (InstList::const_iterator I = Insts.begin(), E = Insts.end(); I != E;
+ ++I) {
+ Inst *Inst = *I;
+ if (Inst->isDeleted())
+ continue;
+ // Here we detect redundant assignments like "mov eax, eax" and
+ // suppress them.
+ if (Inst->isRedundantAssign())
+ continue;
+ (*I)->emit(Func);
+ }
+}
+
void CfgNode::dump(Cfg *Func) const {
Func->setCurrentNode(this);
Ostream &Str = Func->getContext()->getStrDump();
diff --git a/src/IceCfgNode.h b/src/IceCfgNode.h
index bf96aef..645dc57 100644
--- a/src/IceCfgNode.h
+++ b/src/IceCfgNode.h
@@ -29,6 +29,14 @@
// Access the label number and name for this node.
SizeT getIndex() const { return Number; }
IceString getName() const;
+ IceString getAsmName() const {
+ return ".L" + Func->getFunctionName() + "$" + getName();
+ }
+
+ // The HasReturn flag indicates that this node contains a return
+ // instruction and therefore needs an epilog.
+ void setHasReturn() { HasReturn = true; }
+ bool getHasReturn() const { return HasReturn; }
// Access predecessor and successor edge lists.
const NodeList &getInEdges() const { return InEdges; }
@@ -42,6 +50,11 @@
// node's successors.
void computePredecessors();
+ void placePhiLoads();
+ void placePhiStores();
+ void deletePhis();
+ void genCode();
+ void emit(Cfg *Func) const;
void dump(Cfg *Func) const;
private:
@@ -51,6 +64,7 @@
Cfg *const Func;
const SizeT Number; // label index
IceString Name; // for dumping only
+ bool HasReturn; // does this block need an epilog?
NodeList InEdges; // in no particular order
NodeList OutEdges; // in no particular order
PhiList Phis; // unordered set of phi instructions
diff --git a/src/IceDefs.h b/src/IceDefs.h
index 25c384a..6c5cb1a 100644
--- a/src/IceDefs.h
+++ b/src/IceDefs.h
@@ -35,16 +35,23 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Timer.h"
+// Roll our own static_assert<> in the absence of C++11. TODO: change
+// to static_assert<> with C++11.
+template <bool> struct staticAssert;
+template <> struct staticAssert<true> {}; // only true is defined
+#define STATIC_ASSERT(x) staticAssert<(x)>()
+
namespace Ice {
+class Cfg;
class CfgNode;
class Constant;
class GlobalContext;
-class Cfg;
class Inst;
class InstPhi;
class InstTarget;
class Operand;
+class TargetLowering;
class Variable;
// TODO: Switch over to LLVM's ADT container classes.
diff --git a/src/IceGlobalContext.cpp b/src/IceGlobalContext.cpp
index 11de013..ab63b4c 100644
--- a/src/IceGlobalContext.cpp
+++ b/src/IceGlobalContext.cpp
@@ -17,6 +17,7 @@
#include "IceCfg.h"
#include "IceGlobalContext.h"
#include "IceOperand.h"
+#include "IceTargetLowering.h"
namespace Ice {
@@ -75,18 +76,17 @@
GlobalContext::GlobalContext(llvm::raw_ostream *OsDump,
llvm::raw_ostream *OsEmit, VerboseMask Mask,
+ TargetArch Arch, OptLevel Opt,
IceString TestPrefix)
: StrDump(OsDump), StrEmit(OsEmit), VMask(Mask),
- ConstPool(new ConstantPool()), TestPrefix(TestPrefix) {}
+ ConstPool(new ConstantPool()), Arch(Arch), Opt(Opt),
+ TestPrefix(TestPrefix), HasEmittedFirstMethod(false) {}
// In this context, name mangling means to rewrite a symbol using a
// given prefix. For a C++ symbol, nest the original symbol inside
// the "prefix" namespace. For other symbols, just prepend the
// prefix.
IceString GlobalContext::mangleName(const IceString &Name) const {
- // TODO: Add explicit tests (beyond the implicit tests in the linker
- // that come from the cross tests).
- //
// An already-nested name like foo::bar() gets pushed down one
// level, making it equivalent to Prefix::foo::bar().
// _ZN3foo3barExyz ==> _ZN6Prefix3foo3barExyz
@@ -100,9 +100,9 @@
unsigned PrefixLength = getTestPrefix().length();
char NameBase[1 + Name.length()];
- const size_t BufLen = 30 + Name.length() + getTestPrefix().length();
+ const size_t BufLen = 30 + Name.length() + PrefixLength;
char NewName[BufLen];
- uint32_t BaseLength = 0;
+ uint32_t BaseLength = 0; // using uint32_t due to sscanf format string
int ItemsParsed = sscanf(Name.c_str(), "_ZN%s", NameBase);
if (ItemsParsed == 1) {
@@ -118,15 +118,28 @@
}
ItemsParsed = sscanf(Name.c_str(), "_Z%u%s", &BaseLength, NameBase);
- if (ItemsParsed == 2) {
- // Transform _Z3barxyz ==> ZN6Prefix3barExyz
- // ^^^^^^^^ ^
+ if (ItemsParsed == 2 && BaseLength <= strlen(NameBase)) {
+ // Transform _Z3barxyz ==> _ZN6Prefix3barExyz
+ // ^^^^^^^^ ^
// (splice in "N6Prefix", and insert "E" after "3bar")
+ // But an "I" after the identifier indicates a template argument
+ // list terminated with "E"; insert the new "E" before/after the
+ // old "E". E.g.:
+ // Transform _Z3barIabcExyz ==> _ZN6Prefix3barIabcEExyz
+ // ^^^^^^^^ ^
+ // (splice in "N6Prefix", and insert "E" after "3barIabcE")
char OrigName[Name.length()];
char OrigSuffix[Name.length()];
- strncpy(OrigName, NameBase, BaseLength);
- OrigName[BaseLength] = '\0';
- strcpy(OrigSuffix, NameBase + BaseLength);
+ uint32_t ActualBaseLength = BaseLength;
+ if (NameBase[ActualBaseLength] == 'I') {
+ ++ActualBaseLength;
+ while (NameBase[ActualBaseLength] != 'E' &&
+ NameBase[ActualBaseLength] != '\0')
+ ++ActualBaseLength;
+ }
+ strncpy(OrigName, NameBase, ActualBaseLength);
+ OrigName[ActualBaseLength] = '\0';
+ strcpy(OrigSuffix, NameBase + ActualBaseLength);
snprintf(NewName, BufLen, "_ZN%u%s%u%sE%s", PrefixLength,
getTestPrefix().c_str(), BaseLength, OrigName, OrigSuffix);
return NewName;
diff --git a/src/IceGlobalContext.h b/src/IceGlobalContext.h
index 9224d89..1ad5f07 100644
--- a/src/IceGlobalContext.h
+++ b/src/IceGlobalContext.h
@@ -30,7 +30,8 @@
class GlobalContext {
public:
GlobalContext(llvm::raw_ostream *OsDump, llvm::raw_ostream *OsEmit,
- VerboseMask Mask, IceString TestPrefix);
+ VerboseMask Mask, TargetArch Arch, OptLevel Opt,
+ IceString TestPrefix);
~GlobalContext();
// Returns true if any of the specified options in the verbose mask
@@ -48,6 +49,9 @@
Ostream &getStrDump() { return StrDump; }
Ostream &getStrEmit() { return StrEmit; }
+ TargetArch getTargetArch() const { return Arch; }
+ OptLevel getOptLevel() const { return Opt; }
+
// When emitting assembly, we allow a string to be prepended to
// names of translated functions. This makes it easier to create an
// execution test against a reference translator like llc, with both
@@ -55,6 +59,15 @@
IceString getTestPrefix() const { return TestPrefix; }
IceString mangleName(const IceString &Name) const;
+ // The purpose of HasEmitted is to add a header comment at the
+ // beginning of assembly code emission, doing it once per file
+ // rather than once per function.
+ bool testAndSetHasEmittedFirstMethod() {
+ bool HasEmitted = HasEmittedFirstMethod;
+ HasEmittedFirstMethod = true;
+ return HasEmitted;
+ }
+
// Manage Constants.
// getConstant*() functions are not const because they might add
// something to the constant pool.
@@ -75,7 +88,10 @@
llvm::BumpPtrAllocator Allocator;
VerboseMask VMask;
llvm::OwningPtr<class ConstantPool> ConstPool;
+ const TargetArch Arch;
+ const OptLevel Opt;
const IceString TestPrefix;
+ bool HasEmittedFirstMethod;
GlobalContext(const GlobalContext &) LLVM_DELETED_FUNCTION;
GlobalContext &operator=(const GlobalContext &) LLVM_DELETED_FUNCTION;
};
diff --git a/src/IceInst.cpp b/src/IceInst.cpp
index 391f197..3f0c97d 100644
--- a/src/IceInst.cpp
+++ b/src/IceInst.cpp
@@ -22,7 +22,7 @@
namespace {
// Using non-anonymous struct so that array_lengthof works.
-const struct _InstArithmeticAttributes {
+const struct InstArithmeticAttributes_ {
const char *DisplayString;
bool IsCommutative;
} InstArithmeticAttributes[] = {
@@ -36,7 +36,7 @@
llvm::array_lengthof(InstArithmeticAttributes);
// Using non-anonymous struct so that array_lengthof works.
-const struct _InstCastAttributes {
+const struct InstCastAttributes_ {
const char *DisplayString;
} InstCastAttributes[] = {
#define X(tag, str) \
@@ -48,7 +48,7 @@
const size_t InstCastAttributesSize = llvm::array_lengthof(InstCastAttributes);
// Using non-anonymous struct so that array_lengthof works.
-const struct _InstFcmpAttributes {
+const struct InstFcmpAttributes_ {
const char *DisplayString;
} InstFcmpAttributes[] = {
#define X(tag, str) \
@@ -60,7 +60,7 @@
const size_t InstFcmpAttributesSize = llvm::array_lengthof(InstFcmpAttributes);
// Using non-anonymous struct so that array_lengthof works.
-const struct _InstIcmpAttributes {
+const struct InstIcmpAttributes_ {
const char *DisplayString;
} InstIcmpAttributes[] = {
#define X(tag, str) \
@@ -180,6 +180,35 @@
addSource(Source);
}
+// Find the source operand corresponding to the incoming edge for the
+// given node. TODO: This uses a linear-time search, which could be
+// improved if it becomes a problem.
+Operand *InstPhi::getOperandForTarget(CfgNode *Target) const {
+ for (SizeT I = 0; I < getSrcSize(); ++I) {
+ if (Labels[I] == Target)
+ return getSrc(I);
+ }
+ llvm_unreachable("Phi target not found");
+ return NULL;
+}
+
+// Change "a=phi(...)" to "a_phi=phi(...)" and return a new
+// instruction "a=a_phi".
+Inst *InstPhi::lower(Cfg *Func, CfgNode *Node) {
+ Variable *Dest = getDest();
+ assert(Dest);
+ IceString PhiName = Dest->getName() + "_phi";
+ Variable *NewSrc = Func->makeVariable(Dest->getType(), Node, PhiName);
+ this->Dest = NewSrc;
+ InstAssign *NewInst = InstAssign::create(Func, Dest, NewSrc);
+ // Set Dest and NewSrc to have affinity with each other, as a hint
+ // for register allocation.
+ Dest->setPreferredRegister(NewSrc, false);
+ NewSrc->setPreferredRegister(Dest, false);
+ Dest->replaceDefinition(NewInst, Node);
+ return NewInst;
+}
+
InstRet::InstRet(Cfg *Func, Operand *RetValue)
: Inst(Func, Ret, RetValue ? 1 : 0, NULL) {
if (RetValue)
@@ -233,11 +262,35 @@
InstUnreachable::InstUnreachable(Cfg *Func)
: Inst(Func, Inst::Unreachable, 0, NULL) {}
+InstFakeDef::InstFakeDef(Cfg *Func, Variable *Dest, Variable *Src)
+ : Inst(Func, Inst::FakeDef, Src ? 1 : 0, Dest) {
+ assert(Dest);
+ if (Src)
+ addSource(Src);
+}
+
+InstFakeUse::InstFakeUse(Cfg *Func, Variable *Src)
+ : Inst(Func, Inst::FakeUse, 1, NULL) {
+ assert(Src);
+ addSource(Src);
+}
+
+InstFakeKill::InstFakeKill(Cfg *Func, const VarList &KilledRegs,
+ const Inst *Linked)
+ : Inst(Func, Inst::FakeKill, KilledRegs.size(), NULL), Linked(Linked) {
+ for (VarList::const_iterator I = KilledRegs.begin(), E = KilledRegs.end();
+ I != E; ++I) {
+ Variable *Var = *I;
+ addSource(Var);
+ }
+}
+
// ======================== Dump routines ======================== //
void Inst::dumpDecorated(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrDump();
- if (!Func->getContext()->isVerbose(IceV_Deleted) && isDeleted())
+ if (!Func->getContext()->isVerbose(IceV_Deleted) &&
+ (isDeleted() || isRedundantAssign()))
return;
if (Func->getContext()->isVerbose(IceV_InstNumbers)) {
char buf[30];
@@ -255,6 +308,10 @@
Str << "\n";
}
+void Inst::emit(const Cfg * /*Func*/) const {
+ llvm_unreachable("emit() called on a non-lowered instruction");
+}
+
void Inst::dump(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrDump();
dumpDest(Func);
@@ -271,6 +328,15 @@
}
}
+void Inst::emitSources(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ for (SizeT I = 0; I < getSrcSize(); ++I) {
+ if (I > 0)
+ Str << ", ";
+ getSrc(I)->emit(Func);
+ }
+}
+
void Inst::dumpDest(const Cfg *Func) const {
if (getDest())
getDest()->dump(Func);
@@ -406,7 +472,7 @@
void InstRet::dump(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrDump();
- Type Ty = hasRetValue() ? getSrc(0)->getType() : IceType_void;
+ Type Ty = hasRetValue() ? getRetValue()->getType() : IceType_void;
Str << "ret " << Ty;
if (hasRetValue()) {
Str << " ";
@@ -433,4 +499,58 @@
Str << "unreachable";
}
+void InstFakeDef::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ Str << "\t# ";
+ getDest()->emit(Func);
+ Str << " = def.pseudo ";
+ emitSources(Func);
+ Str << "\n";
+}
+
+void InstFakeDef::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = def.pseudo ";
+ dumpSources(Func);
+}
+
+void InstFakeUse::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ Str << "\t# ";
+ Str << "use.pseudo ";
+ emitSources(Func);
+ Str << "\n";
+}
+
+void InstFakeUse::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "use.pseudo ";
+ dumpSources(Func);
+}
+
+void InstFakeKill::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ Str << "\t# ";
+ if (Linked->isDeleted())
+ Str << "// ";
+ Str << "kill.pseudo ";
+ emitSources(Func);
+ Str << "\n";
+}
+
+void InstFakeKill::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ if (Linked->isDeleted())
+ Str << "// ";
+ Str << "kill.pseudo ";
+ dumpSources(Func);
+}
+
+void InstTarget::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "[TARGET] ";
+ Inst::dump(Func);
+}
+
} // end of namespace Ice
diff --git a/src/IceInst.def b/src/IceInst.def
index 60c613d..a9cadb2 100644
--- a/src/IceInst.def
+++ b/src/IceInst.def
@@ -85,5 +85,4 @@
X(Sle, "sle")
//#define X(tag, str)
-
#endif // SUBZERO_SRC_ICEINST_DEF
diff --git a/src/IceInst.h b/src/IceInst.h
index 57f8b9e..3067c26 100644
--- a/src/IceInst.h
+++ b/src/IceInst.h
@@ -47,7 +47,12 @@
Ret,
Select,
Store,
- Switch
+ Switch,
+ FakeDef, // not part of LLVM/PNaCl bitcode
+ FakeUse, // not part of LLVM/PNaCl bitcode
+ FakeKill, // not part of LLVM/PNaCl bitcode
+ Target // target-specific low-level ICE
+ // Anything >= Target is an InstTarget subclass.
};
InstKind getKind() const { return Kind; }
@@ -83,10 +88,13 @@
// basic blocks, i.e. used in a different block from their definition.
void updateVars(CfgNode *Node);
+ virtual void emit(const Cfg *Func) const;
virtual void dump(const Cfg *Func) const;
void dumpDecorated(const Cfg *Func) const;
+ void emitSources(const Cfg *Func) const;
void dumpSources(const Cfg *Func) const;
void dumpDest(const Cfg *Func) const;
+ virtual bool isRedundantAssign() const { return false; }
virtual ~Inst() {}
@@ -154,6 +162,7 @@
ICEINSTARITHMETIC_TABLE
#undef X
};
+
static InstArithmetic *create(Cfg *Func, OpKind Op, Variable *Dest,
Operand *Source1, Operand *Source2) {
return new (Func->allocateInst<InstArithmetic>())
@@ -279,6 +288,7 @@
ICEINSTCAST_TABLE
#undef X
};
+
static InstCast *create(Cfg *Func, OpKind CastKind, Variable *Dest,
Operand *Source) {
return new (Func->allocateInst<InstCast>())
@@ -305,6 +315,7 @@
ICEINSTFCMP_TABLE
#undef X
};
+
static InstFcmp *create(Cfg *Func, FCond Condition, Variable *Dest,
Operand *Source1, Operand *Source2) {
return new (Func->allocateInst<InstFcmp>())
@@ -332,6 +343,7 @@
ICEINSTICMP_TABLE
#undef X
};
+
static InstIcmp *create(Cfg *Func, ICond Condition, Variable *Dest,
Operand *Source1, Operand *Source2) {
return new (Func->allocateInst<InstIcmp>())
@@ -376,6 +388,8 @@
return new (Func->allocateInst<InstPhi>()) InstPhi(Func, MaxSrcs, Dest);
}
void addArgument(Operand *Source, CfgNode *Label);
+ Operand *getOperandForTarget(CfgNode *Target) const;
+ Inst *lower(Cfg *Func, CfgNode *Node);
virtual void dump(const Cfg *Func) const;
static bool classof(const Inst *Inst) { return Inst->getKind() == Phi; }
@@ -522,6 +536,104 @@
virtual ~InstUnreachable() {}
};
+// FakeDef instruction. This creates a fake definition of a variable,
+// which is how we represent the case when an instruction produces
+// multiple results. This doesn't happen with high-level ICE
+// instructions, but might with lowered instructions. For example,
+// this would be a way to represent condition flags being modified by
+// an instruction.
+//
+// It's generally useful to set the optional source operand to be the
+// dest variable of the instruction that actually produces the FakeDef
+// dest. Otherwise, the original instruction could be dead-code
+// eliminated if its dest operand is unused, and therefore the FakeDef
+// dest wouldn't be properly initialized.
+class InstFakeDef : public Inst {
+public:
+ static InstFakeDef *create(Cfg *Func, Variable *Dest, Variable *Src = NULL) {
+ return new (Func->allocateInst<InstFakeDef>()) InstFakeDef(Func, Dest, Src);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return Inst->getKind() == FakeDef; }
+
+private:
+ InstFakeDef(Cfg *Func, Variable *Dest, Variable *Src);
+ InstFakeDef(const InstFakeDef &) LLVM_DELETED_FUNCTION;
+ InstFakeDef &operator=(const InstFakeDef &) LLVM_DELETED_FUNCTION;
+ virtual ~InstFakeDef() {}
+};
+
+// FakeUse instruction. This creates a fake use of a variable, to
+// keep the instruction that produces that variable from being
+// dead-code eliminated. This is useful in a variety of lowering
+// situations. The FakeUse instruction has no dest, so it can itself
+// never be dead-code eliminated.
+class InstFakeUse : public Inst {
+public:
+ static InstFakeUse *create(Cfg *Func, Variable *Src) {
+ return new (Func->allocateInst<InstFakeUse>()) InstFakeUse(Func, Src);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return Inst->getKind() == FakeUse; }
+
+private:
+ InstFakeUse(Cfg *Func, Variable *Src);
+ InstFakeUse(const InstFakeUse &) LLVM_DELETED_FUNCTION;
+ InstFakeUse &operator=(const InstFakeUse &) LLVM_DELETED_FUNCTION;
+ virtual ~InstFakeUse() {}
+};
+
+// FakeKill instruction. This "kills" a set of variables by adding a
+// trivial live range at this instruction to each variable. The
+// primary use is to indicate that scratch registers are killed after
+// a call, so that the register allocator won't assign a scratch
+// register to a variable whose live range spans a call.
+//
+// The FakeKill instruction also holds a pointer to the instruction
+// that kills the set of variables, so that if that linked instruction
+// gets dead-code eliminated, the FakeKill instruction will as well.
+class InstFakeKill : public Inst {
+public:
+ static InstFakeKill *create(Cfg *Func, const VarList &KilledRegs,
+ const Inst *Linked) {
+ return new (Func->allocateInst<InstFakeKill>())
+ InstFakeKill(Func, KilledRegs, Linked);
+ }
+ const Inst *getLinked() const { return Linked; }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return Inst->getKind() == FakeKill; }
+
+private:
+ InstFakeKill(Cfg *Func, const VarList &KilledRegs, const Inst *Linked);
+ InstFakeKill(const InstFakeKill &) LLVM_DELETED_FUNCTION;
+ InstFakeKill &operator=(const InstFakeKill &) LLVM_DELETED_FUNCTION;
+ virtual ~InstFakeKill() {}
+
+ // This instruction is ignored if Linked->isDeleted() is true.
+ const Inst *Linked;
+};
+
+// The Target instruction is the base class for all target-specific
+// instructions.
+class InstTarget : public Inst {
+public:
+ virtual void emit(const Cfg *Func) const = 0;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return Inst->getKind() >= Target; }
+
+protected:
+ InstTarget(Cfg *Func, InstKind Kind, SizeT MaxSrcs, Variable *Dest)
+ : Inst(Func, Kind, MaxSrcs, Dest) {
+ assert(Kind >= Target);
+ }
+ InstTarget(const InstTarget &) LLVM_DELETED_FUNCTION;
+ InstTarget &operator=(const InstTarget &) LLVM_DELETED_FUNCTION;
+ virtual ~InstTarget() {}
+};
+
} // end of namespace Ice
#endif // SUBZERO_SRC_ICEINST_H
diff --git a/src/IceInstX8632.cpp b/src/IceInstX8632.cpp
new file mode 100644
index 0000000..5d3f01b
--- /dev/null
+++ b/src/IceInstX8632.cpp
@@ -0,0 +1,868 @@
+//===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
+//
+// The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the InstX8632 and OperandX8632 classes,
+// primarily the constructors and the dump()/emit() methods.
+//
+//===----------------------------------------------------------------------===//
+
+#include "IceCfg.h"
+#include "IceCfgNode.h"
+#include "IceInst.h"
+#include "IceInstX8632.h"
+#include "IceTargetLoweringX8632.h"
+#include "IceOperand.h"
+
+namespace Ice {
+
+namespace {
+
+const struct InstX8632BrAttributes_ {
+ const char *DisplayString;
+ const char *EmitString;
+} InstX8632BrAttributes[] = {
+#define X(tag, dump, emit) \
+ { dump, emit } \
+ ,
+ ICEINSTX8632BR_TABLE
+#undef X
+ };
+const size_t InstX8632BrAttributesSize =
+ llvm::array_lengthof(InstX8632BrAttributes);
+
+const struct TypeX8632Attributes_ {
+ const char *CvtString; // i (integer), s (single FP), d (double FP)
+ const char *SdSsString; // ss, sd, or <blank>
+ const char *WidthString; // {byte,word,dword,qword} ptr
+} TypeX8632Attributes[] = {
+#define X(tag, cvt, sdss, width) \
+ { cvt, "" sdss, width } \
+ ,
+ ICETYPEX8632_TABLE
+#undef X
+ };
+const size_t TypeX8632AttributesSize =
+ llvm::array_lengthof(TypeX8632Attributes);
+
+} // end of anonymous namespace
+
+const char *InstX8632::getWidthString(Type Ty) {
+ return TypeX8632Attributes[Ty].WidthString;
+}
+
+OperandX8632Mem::OperandX8632Mem(Cfg *Func, Type Ty, Variable *Base,
+ Constant *Offset, Variable *Index,
+ uint32_t Shift)
+ : OperandX8632(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
+ Shift(Shift) {
+ assert(Shift <= 3);
+ Vars = NULL;
+ NumVars = 0;
+ if (Base)
+ ++NumVars;
+ if (Index)
+ ++NumVars;
+ if (NumVars) {
+ Vars = Func->allocateArrayOf<Variable *>(NumVars);
+ SizeT I = 0;
+ if (Base)
+ Vars[I++] = Base;
+ if (Index)
+ Vars[I++] = Index;
+ assert(I == NumVars);
+ }
+}
+
+InstX8632Mul::InstX8632Mul(Cfg *Func, Variable *Dest, Variable *Source1,
+ Operand *Source2)
+ : InstX8632(Func, InstX8632::Mul, 2, Dest) {
+ addSource(Source1);
+ addSource(Source2);
+}
+
+InstX8632Shld::InstX8632Shld(Cfg *Func, Variable *Dest, Variable *Source1,
+ Variable *Source2)
+ : InstX8632(Func, InstX8632::Shld, 3, Dest) {
+ addSource(Dest);
+ addSource(Source1);
+ addSource(Source2);
+}
+
+InstX8632Shrd::InstX8632Shrd(Cfg *Func, Variable *Dest, Variable *Source1,
+ Variable *Source2)
+ : InstX8632(Func, InstX8632::Shrd, 3, Dest) {
+ addSource(Dest);
+ addSource(Source1);
+ addSource(Source2);
+}
+
+InstX8632Label::InstX8632Label(Cfg *Func, TargetX8632 *Target)
+ : InstX8632(Func, InstX8632::Label, 0, NULL),
+ Number(Target->makeNextLabelNumber()) {}
+
+IceString InstX8632Label::getName(const Cfg *Func) const {
+ char buf[30];
+ snprintf(buf, llvm::array_lengthof(buf), "%u", Number);
+ return ".L" + Func->getFunctionName() + "$__" + buf;
+}
+
+InstX8632Br::InstX8632Br(Cfg *Func, CfgNode *TargetTrue, CfgNode *TargetFalse,
+ InstX8632Label *Label, InstX8632Br::BrCond Condition)
+ : InstX8632(Func, InstX8632::Br, 0, NULL), Condition(Condition),
+ TargetTrue(TargetTrue), TargetFalse(TargetFalse), Label(Label) {}
+
+InstX8632Call::InstX8632Call(Cfg *Func, Variable *Dest, Operand *CallTarget)
+ : InstX8632(Func, InstX8632::Call, 1, Dest) {
+ HasSideEffects = true;
+ addSource(CallTarget);
+}
+
+InstX8632Cdq::InstX8632Cdq(Cfg *Func, Variable *Dest, Operand *Source)
+ : InstX8632(Func, InstX8632::Cdq, 1, Dest) {
+ assert(Dest->getRegNum() == TargetX8632::Reg_edx);
+ assert(llvm::isa<Variable>(Source));
+ assert(llvm::dyn_cast<Variable>(Source)->getRegNum() == TargetX8632::Reg_eax);
+ addSource(Source);
+}
+
+InstX8632Cvt::InstX8632Cvt(Cfg *Func, Variable *Dest, Operand *Source)
+ : InstX8632(Func, InstX8632::Cvt, 1, Dest) {
+ addSource(Source);
+}
+
+InstX8632Icmp::InstX8632Icmp(Cfg *Func, Operand *Src0, Operand *Src1)
+ : InstX8632(Func, InstX8632::Icmp, 2, NULL) {
+ addSource(Src0);
+ addSource(Src1);
+}
+
+InstX8632Ucomiss::InstX8632Ucomiss(Cfg *Func, Operand *Src0, Operand *Src1)
+ : InstX8632(Func, InstX8632::Ucomiss, 2, NULL) {
+ addSource(Src0);
+ addSource(Src1);
+}
+
+InstX8632Test::InstX8632Test(Cfg *Func, Operand *Src1, Operand *Src2)
+ : InstX8632(Func, InstX8632::Test, 2, NULL) {
+ addSource(Src1);
+ addSource(Src2);
+}
+
+InstX8632Store::InstX8632Store(Cfg *Func, Operand *Value, OperandX8632 *Mem)
+ : InstX8632(Func, InstX8632::Store, 2, NULL) {
+ addSource(Value);
+ addSource(Mem);
+}
+
+InstX8632Mov::InstX8632Mov(Cfg *Func, Variable *Dest, Operand *Source)
+ : InstX8632(Func, InstX8632::Mov, 1, Dest) {
+ addSource(Source);
+}
+
+InstX8632Movsx::InstX8632Movsx(Cfg *Func, Variable *Dest, Operand *Source)
+ : InstX8632(Func, InstX8632::Movsx, 1, Dest) {
+ addSource(Source);
+}
+
+InstX8632Movzx::InstX8632Movzx(Cfg *Func, Variable *Dest, Operand *Source)
+ : InstX8632(Func, InstX8632::Movzx, 1, Dest) {
+ addSource(Source);
+}
+
+InstX8632Fld::InstX8632Fld(Cfg *Func, Operand *Src)
+ : InstX8632(Func, InstX8632::Fld, 1, NULL) {
+ addSource(Src);
+}
+
+InstX8632Fstp::InstX8632Fstp(Cfg *Func, Variable *Dest)
+ : InstX8632(Func, InstX8632::Fstp, 0, Dest) {}
+
+InstX8632Pop::InstX8632Pop(Cfg *Func, Variable *Dest)
+ : InstX8632(Func, InstX8632::Pop, 0, Dest) {}
+
+InstX8632Push::InstX8632Push(Cfg *Func, Operand *Source,
+ bool SuppressStackAdjustment)
+ : InstX8632(Func, InstX8632::Push, 1, NULL),
+ SuppressStackAdjustment(SuppressStackAdjustment) {
+ addSource(Source);
+}
+
+bool InstX8632Mov::isRedundantAssign() const {
+ Variable *Src = llvm::dyn_cast<Variable>(getSrc(0));
+ if (Src == NULL)
+ return false;
+ if (getDest()->hasReg() && getDest()->getRegNum() == Src->getRegNum()) {
+ // TODO: On x86-64, instructions like "mov eax, eax" are used to
+ // clear the upper 32 bits of rax. We need to recognize and
+ // preserve these.
+ return true;
+ }
+ if (!getDest()->hasReg() && !Src->hasReg() &&
+ Dest->getStackOffset() == Src->getStackOffset())
+ return true;
+ return false;
+}
+
+InstX8632Ret::InstX8632Ret(Cfg *Func, Variable *Source)
+ : InstX8632(Func, InstX8632::Ret, Source ? 1 : 0, NULL) {
+ if (Source)
+ addSource(Source);
+}
+
+// ======================== Dump routines ======================== //
+
+void InstX8632::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "[X8632] ";
+ Inst::dump(Func);
+}
+
+void InstX8632Label::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ Str << getName(Func) << ":\n";
+}
+
+void InstX8632Label::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << getName(Func) << ":";
+}
+
+void InstX8632Br::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ Str << "\t";
+
+ if (Condition == Br_None) {
+ Str << "jmp";
+ } else {
+ Str << InstX8632BrAttributes[Condition].EmitString;
+ }
+
+ if (Label) {
+ Str << "\t" << Label->getName(Func) << "\n";
+ } else {
+ if (Condition == Br_None) {
+ Str << "\t" << getTargetFalse()->getAsmName() << "\n";
+ } else {
+ Str << "\t" << getTargetTrue()->getAsmName() << "\n";
+ if (getTargetFalse()) {
+ Str << "\tjmp\t" << getTargetFalse()->getAsmName() << "\n";
+ }
+ }
+ }
+}
+
+void InstX8632Br::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "br ";
+
+ if (Condition == Br_None) {
+ Str << "label %"
+ << (Label ? Label->getName(Func) : getTargetFalse()->getName());
+ return;
+ }
+
+ Str << InstX8632BrAttributes[Condition].DisplayString;
+ if (Label) {
+ Str << ", label %" << Label->getName(Func);
+ } else {
+ Str << ", label %" << getTargetTrue()->getName();
+ if (getTargetFalse()) {
+ Str << ", label %" << getTargetFalse()->getName();
+ }
+ }
+}
+
+void InstX8632Call::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 1);
+ Str << "\tcall\t";
+ getCallTarget()->emit(Func);
+ Str << "\n";
+ Func->getTarget()->resetStackAdjustment();
+}
+
+void InstX8632Call::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ if (getDest()) {
+ dumpDest(Func);
+ Str << " = ";
+ }
+ Str << "call ";
+ getCallTarget()->dump(Func);
+}
+
+// The ShiftHack parameter is used to emit "cl" instead of "ecx" for
+// shift instructions, in order to be syntactically valid. The
+// Opcode parameter needs to be char* and not IceString because of
+// template issues.
+void emitTwoAddress(const char *Opcode, const Inst *Inst, const Cfg *Func,
+ bool ShiftHack) {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(Inst->getSrcSize() == 2);
+ assert(Inst->getDest() == Inst->getSrc(0));
+ Str << "\t" << Opcode << "\t";
+ Inst->getDest()->emit(Func);
+ Str << ", ";
+ bool EmittedSrc1 = false;
+ if (ShiftHack) {
+ Variable *ShiftReg = llvm::dyn_cast<Variable>(Inst->getSrc(1));
+ if (ShiftReg && ShiftReg->getRegNum() == TargetX8632::Reg_ecx) {
+ Str << "cl";
+ EmittedSrc1 = true;
+ }
+ }
+ if (!EmittedSrc1)
+ Inst->getSrc(1)->emit(Func);
+ Str << "\n";
+}
+
+template <> const char *InstX8632Add::Opcode = "add";
+template <> const char *InstX8632Adc::Opcode = "adc";
+template <> const char *InstX8632Addss::Opcode = "addss";
+template <> const char *InstX8632Sub::Opcode = "sub";
+template <> const char *InstX8632Subss::Opcode = "subss";
+template <> const char *InstX8632Sbb::Opcode = "sbb";
+template <> const char *InstX8632And::Opcode = "and";
+template <> const char *InstX8632Or::Opcode = "or";
+template <> const char *InstX8632Xor::Opcode = "xor";
+template <> const char *InstX8632Imul::Opcode = "imul";
+template <> const char *InstX8632Mulss::Opcode = "mulss";
+template <> const char *InstX8632Div::Opcode = "div";
+template <> const char *InstX8632Idiv::Opcode = "idiv";
+template <> const char *InstX8632Divss::Opcode = "divss";
+template <> const char *InstX8632Shl::Opcode = "shl";
+template <> const char *InstX8632Shr::Opcode = "shr";
+template <> const char *InstX8632Sar::Opcode = "sar";
+
+template <> void InstX8632Addss::emit(const Cfg *Func) const {
+ char buf[30];
+ snprintf(buf, llvm::array_lengthof(buf), "add%s",
+ TypeX8632Attributes[getDest()->getType()].SdSsString);
+ emitTwoAddress(buf, this, Func);
+}
+
+template <> void InstX8632Subss::emit(const Cfg *Func) const {
+ char buf[30];
+ snprintf(buf, llvm::array_lengthof(buf), "sub%s",
+ TypeX8632Attributes[getDest()->getType()].SdSsString);
+ emitTwoAddress(buf, this, Func);
+}
+
+template <> void InstX8632Mulss::emit(const Cfg *Func) const {
+ char buf[30];
+ snprintf(buf, llvm::array_lengthof(buf), "mul%s",
+ TypeX8632Attributes[getDest()->getType()].SdSsString);
+ emitTwoAddress(buf, this, Func);
+}
+
+template <> void InstX8632Divss::emit(const Cfg *Func) const {
+ char buf[30];
+ snprintf(buf, llvm::array_lengthof(buf), "div%s",
+ TypeX8632Attributes[getDest()->getType()].SdSsString);
+ emitTwoAddress(buf, this, Func);
+}
+
+template <> void InstX8632Imul::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 2);
+ if (getDest()->getType() == IceType_i8) {
+ // The 8-bit version of imul only allows the form "imul r/m8".
+ Variable *Src0 = llvm::dyn_cast<Variable>(getSrc(0));
+ assert(Src0 && Src0->getRegNum() == TargetX8632::Reg_eax);
+ Str << "\timul\t";
+ getSrc(1)->emit(Func);
+ Str << "\n";
+ } else if (llvm::isa<Constant>(getSrc(1))) {
+ Str << "\timul\t";
+ getDest()->emit(Func);
+ Str << ", ";
+ getSrc(0)->emit(Func);
+ Str << ", ";
+ getSrc(1)->emit(Func);
+ Str << "\n";
+ } else {
+ emitTwoAddress("imul", this, Func);
+ }
+}
+
+void InstX8632Mul::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 2);
+ assert(llvm::isa<Variable>(getSrc(0)));
+ assert(llvm::dyn_cast<Variable>(getSrc(0))->getRegNum() ==
+ TargetX8632::Reg_eax);
+ assert(getDest()->getRegNum() == TargetX8632::Reg_eax); // TODO: allow edx?
+ Str << "\tmul\t";
+ getSrc(1)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Mul::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = mul." << getDest()->getType() << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Shld::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 3);
+ assert(getDest() == getSrc(0));
+ Str << "\tshld\t";
+ getDest()->emit(Func);
+ Str << ", ";
+ getSrc(1)->emit(Func);
+ Str << ", ";
+ if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
+ assert(ShiftReg->getRegNum() == TargetX8632::Reg_ecx);
+ Str << "cl";
+ } else {
+ getSrc(2)->emit(Func);
+ }
+ Str << "\n";
+}
+
+void InstX8632Shld::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = shld." << getDest()->getType() << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Shrd::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 3);
+ assert(getDest() == getSrc(0));
+ Str << "\tshrd\t";
+ getDest()->emit(Func);
+ Str << ", ";
+ getSrc(1)->emit(Func);
+ Str << ", ";
+ if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
+ assert(ShiftReg->getRegNum() == TargetX8632::Reg_ecx);
+ Str << "cl";
+ } else {
+ getSrc(2)->emit(Func);
+ }
+ Str << "\n";
+}
+
+void InstX8632Shrd::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = shrd." << getDest()->getType() << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Cdq::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 1);
+ Str << "\tcdq\n";
+}
+
+void InstX8632Cdq::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = cdq." << getSrc(0)->getType() << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Cvt::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 1);
+ Str << "\tcvts" << TypeX8632Attributes[getSrc(0)->getType()].CvtString << "2s"
+ << TypeX8632Attributes[getDest()->getType()].CvtString << "\t";
+ getDest()->emit(Func);
+ Str << ", ";
+ getSrc(0)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Cvt::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = cvts" << TypeX8632Attributes[getSrc(0)->getType()].CvtString
+ << "2s" << TypeX8632Attributes[getDest()->getType()].CvtString << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Icmp::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 2);
+ Str << "\tcmp\t";
+ getSrc(0)->emit(Func);
+ Str << ", ";
+ getSrc(1)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Icmp::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "cmp." << getSrc(0)->getType() << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Ucomiss::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 2);
+ Str << "\tucomi" << TypeX8632Attributes[getSrc(0)->getType()].SdSsString
+ << "\t";
+ getSrc(0)->emit(Func);
+ Str << ", ";
+ getSrc(1)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Ucomiss::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "ucomiss." << getSrc(0)->getType() << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Test::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 2);
+ Str << "\ttest\t";
+ getSrc(0)->emit(Func);
+ Str << ", ";
+ getSrc(1)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Test::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "test." << getSrc(0)->getType() << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Store::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 2);
+ Str << "\tmov\t";
+ getSrc(1)->emit(Func);
+ Str << ", ";
+ getSrc(0)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Store::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "mov." << getSrc(0)->getType() << " ";
+ getSrc(1)->dump(Func);
+ Str << ", ";
+ getSrc(0)->dump(Func);
+}
+
+void InstX8632Mov::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 1);
+ Str << "\tmov" << TypeX8632Attributes[getDest()->getType()].SdSsString
+ << "\t";
+ // For an integer truncation operation, src is wider than dest.
+ // Ideally, we use a mov instruction whose data width matches the
+ // narrower dest. This is a problem if e.g. src is a register like
+ // esi or si where there is no 8-bit version of the register. To be
+ // safe, we instead widen the dest to match src. This works even
+ // for stack-allocated dest variables because typeWidthOnStack()
+ // pads to a 4-byte boundary even if only a lower portion is used.
+ assert(Func->getTarget()->typeWidthInBytesOnStack(getDest()->getType()) ==
+ Func->getTarget()->typeWidthInBytesOnStack(getSrc(0)->getType()));
+ getDest()->asType(getSrc(0)->getType()).emit(Func);
+ Str << ", ";
+ getSrc(0)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Mov::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "mov." << getDest()->getType() << " ";
+ dumpDest(Func);
+ Str << ", ";
+ dumpSources(Func);
+}
+
+void InstX8632Movsx::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 1);
+ Str << "\tmovsx\t";
+ getDest()->emit(Func);
+ Str << ", ";
+ getSrc(0)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Movsx::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "movsx." << getDest()->getType() << "." << getSrc(0)->getType();
+ Str << " ";
+ dumpDest(Func);
+ Str << ", ";
+ dumpSources(Func);
+}
+
+void InstX8632Movzx::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 1);
+ Str << "\tmovzx\t";
+ getDest()->emit(Func);
+ Str << ", ";
+ getSrc(0)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Movzx::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "movzx." << getDest()->getType() << "." << getSrc(0)->getType();
+ Str << " ";
+ dumpDest(Func);
+ Str << ", ";
+ dumpSources(Func);
+}
+
+void InstX8632Fld::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 1);
+ Type Ty = getSrc(0)->getType();
+ Variable *Var = llvm::dyn_cast<Variable>(getSrc(0));
+ if (Var && Var->hasReg()) {
+ // This is a physical xmm register, so we need to spill it to a
+ // temporary stack slot.
+ SizeT Width = typeWidthInBytes(Ty);
+ Str << "\tsub\tesp, " << Width << "\n";
+ Str << "\tmov" << TypeX8632Attributes[Ty].SdSsString << "\t"
+ << TypeX8632Attributes[Ty].WidthString << " [esp], ";
+ Var->emit(Func);
+ Str << "\n";
+ Str << "\tfld\t" << TypeX8632Attributes[Ty].WidthString << " [esp]\n";
+ Str << "\tadd\tesp, " << Width << "\n";
+ return;
+ }
+ Str << "\tfld\t";
+ getSrc(0)->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Fld::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "fld." << getSrc(0)->getType() << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Fstp::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 0);
+ if (getDest() == NULL) {
+ Str << "\tfstp\tst(0)\n";
+ return;
+ }
+ if (!getDest()->hasReg()) {
+ Str << "\tfstp\t";
+ getDest()->emit(Func);
+ Str << "\n";
+ return;
+ }
+ // Dest is a physical (xmm) register, so st(0) needs to go through
+ // memory. Hack this by creating a temporary stack slot, spilling
+ // st(0) there, loading it into the xmm register, and deallocating
+ // the stack slot.
+ Type Ty = getDest()->getType();
+ size_t Width = typeWidthInBytes(Ty);
+ Str << "\tsub\tesp, " << Width << "\n";
+ Str << "\tfstp\t" << TypeX8632Attributes[Ty].WidthString << " [esp]\n";
+ Str << "\tmov" << TypeX8632Attributes[Ty].SdSsString << "\t";
+ getDest()->emit(Func);
+ Str << ", " << TypeX8632Attributes[Ty].WidthString << " [esp]\n";
+ Str << "\tadd\tesp, " << Width << "\n";
+}
+
+void InstX8632Fstp::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = fstp." << getDest()->getType() << ", st(0)";
+ Str << "\n";
+}
+
+void InstX8632Pop::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 0);
+ Str << "\tpop\t";
+ getDest()->emit(Func);
+ Str << "\n";
+}
+
+void InstX8632Pop::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = pop." << getDest()->getType() << " ";
+}
+
+void InstX8632Push::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 1);
+ Type Ty = getSrc(0)->getType();
+ Variable *Var = llvm::dyn_cast<Variable>(getSrc(0));
+ if ((Ty == IceType_f32 || Ty == IceType_f64) && Var && Var->hasReg()) {
+ // The xmm registers can't be directly pushed, so we fake it by
+ // decrementing esp and then storing to [esp].
+ Str << "\tsub\tesp, " << typeWidthInBytes(Ty) << "\n";
+ if (!SuppressStackAdjustment)
+ Func->getTarget()->updateStackAdjustment(typeWidthInBytes(Ty));
+ Str << "\tmov" << TypeX8632Attributes[Ty].SdSsString << "\t"
+ << TypeX8632Attributes[Ty].WidthString << " [esp], ";
+ getSrc(0)->emit(Func);
+ Str << "\n";
+ } else if (Ty == IceType_f64 && (!Var || !Var->hasReg())) {
+ // A double on the stack has to be pushed as two halves. Push the
+ // upper half followed by the lower half for little-endian. TODO:
+ // implement.
+ llvm_unreachable("Missing support for pushing doubles from memory");
+ } else {
+ Str << "\tpush\t";
+ getSrc(0)->emit(Func);
+ Str << "\n";
+ if (!SuppressStackAdjustment)
+ Func->getTarget()->updateStackAdjustment(4);
+ }
+}
+
+void InstX8632Push::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "push." << getSrc(0)->getType() << " ";
+ dumpSources(Func);
+}
+
+void InstX8632Ret::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ Str << "\tret\n";
+}
+
+void InstX8632Ret::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Type Ty = (getSrcSize() == 0 ? IceType_void : getSrc(0)->getType());
+ Str << "ret." << Ty << " ";
+ dumpSources(Func);
+}
+
+void OperandX8632::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ Str << "<OperandX8632>";
+}
+
+void OperandX8632Mem::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ Str << TypeX8632Attributes[getType()].WidthString << " ";
+ // TODO: The following is an almost verbatim paste of dump().
+ bool Dumped = false;
+ Str << "[";
+ if (Base) {
+ Base->emit(Func);
+ Dumped = true;
+ }
+ if (Index) {
+ assert(Base);
+ Str << "+";
+ if (Shift > 0)
+ Str << (1u << Shift) << "*";
+ Index->emit(Func);
+ Dumped = true;
+ }
+ // Pretty-print the Offset.
+ bool OffsetIsZero = false;
+ bool OffsetIsNegative = false;
+ if (Offset == NULL) {
+ OffsetIsZero = true;
+ } else if (ConstantInteger *CI = llvm::dyn_cast<ConstantInteger>(Offset)) {
+ OffsetIsZero = (CI->getValue() == 0);
+ OffsetIsNegative = (static_cast<int64_t>(CI->getValue()) < 0);
+ }
+ if (!OffsetIsZero) { // Suppress if Offset is known to be 0
+ if (Dumped) {
+ if (!OffsetIsNegative) // Suppress if Offset is known to be negative
+ Str << "+";
+ }
+ Offset->emit(Func);
+ }
+ Str << "]";
+}
+
+void OperandX8632Mem::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ bool Dumped = false;
+ Str << "[";
+ if (Base) {
+ Base->dump(Func);
+ Dumped = true;
+ }
+ if (Index) {
+ assert(Base);
+ Str << "+";
+ if (Shift > 0)
+ Str << (1u << Shift) << "*";
+ Index->dump(Func);
+ Dumped = true;
+ }
+ // Pretty-print the Offset.
+ bool OffsetIsZero = false;
+ bool OffsetIsNegative = false;
+ if (Offset == NULL) {
+ OffsetIsZero = true;
+ } else if (ConstantInteger *CI = llvm::dyn_cast<ConstantInteger>(Offset)) {
+ OffsetIsZero = (CI->getValue() == 0);
+ OffsetIsNegative = (static_cast<int64_t>(CI->getValue()) < 0);
+ }
+ if (!OffsetIsZero) { // Suppress if Offset is known to be 0
+ if (Dumped) {
+ if (!OffsetIsNegative) // Suppress if Offset is known to be negative
+ Str << "+";
+ }
+ Offset->dump(Func);
+ }
+ Str << "]";
+}
+
+void VariableSplit::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(Var->getLocalUseNode() == NULL ||
+ Var->getLocalUseNode() == Func->getCurrentNode());
+ assert(!Var->hasReg());
+ // The following is copied/adapted from TargetX8632::emitVariable().
+ const TargetLowering *Target = Func->getTarget();
+ const Type Ty = IceType_i32;
+ Str << TypeX8632Attributes[Ty].WidthString << " ["
+ << Target->getRegName(Target->getFrameOrStackReg(), Ty);
+ int32_t Offset = Var->getStackOffset() + Target->getStackAdjustment();
+ if (Part == High)
+ Offset += 4;
+ if (Offset) {
+ if (Offset > 0)
+ Str << "+";
+ Str << Offset;
+ }
+ Str << "]";
+}
+
+void VariableSplit::dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ switch (Part) {
+ case Low:
+ Str << "low";
+ break;
+ case High:
+ Str << "high";
+ break;
+ default:
+ Str << "???";
+ break;
+ }
+ Str << "(";
+ Var->dump(Func);
+ Str << ")";
+}
+
+} // end of namespace Ice
diff --git a/src/IceInstX8632.def b/src/IceInstX8632.def
new file mode 100644
index 0000000..665dd8d
--- /dev/null
+++ b/src/IceInstX8632.def
@@ -0,0 +1,71 @@
+//===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
+//
+// The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines properties of lowered x86-32 instructions in the
+// form of x-macros.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICEINSTX8632_DEF
+#define SUBZERO_SRC_ICEINSTX8632_DEF
+
+#define REGX8632_TABLE \
+ /* val, init, name, name16, name8, scratch, preserved, stackptr, \
+ frameptr, isI8, isInt, isFP */ \
+ X(Reg_eax, = 0, "eax", "ax", "al", 1, 0, 0, 0, 1, 1, 0) \
+ X(Reg_ecx, = Reg_eax + 1, "ecx", "cx", "cl", 1, 0, 0, 0, 1, 1, 0) \
+ X(Reg_edx, = Reg_eax + 2, "edx", "dx", "dl", 1, 0, 0, 0, 1, 1, 0) \
+ X(Reg_ebx, = Reg_eax + 3, "ebx", "bx", "bl", 0, 1, 0, 0, 1, 1, 0) \
+ X(Reg_esp, = Reg_eax + 4, "esp", "sp", , 0, 0, 1, 0, 0, 1, 0) \
+ X(Reg_ebp, = Reg_eax + 5, "ebp", "bp", , 0, 1, 0, 1, 0, 1, 0) \
+ X(Reg_esi, = Reg_eax + 6, "esi", "si", , 0, 1, 0, 0, 0, 1, 0) \
+ X(Reg_edi, = Reg_eax + 7, "edi", "di", , 0, 1, 0, 0, 0, 1, 0) \
+ X(Reg_ah, /*none*/, "???", , "ah", 0, 0, 0, 0, 1, 0, 0) \
+ X(Reg_xmm0, /*none*/, "xmm0", , , 1, 0, 0, 0, 0, 0, 1) \
+ X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", , , 1, 0, 0, 0, 0, 0, 1) \
+ X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", , , 1, 0, 0, 0, 0, 0, 1) \
+ X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", , , 1, 0, 0, 0, 0, 0, 1) \
+ X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4", , , 1, 0, 0, 0, 0, 0, 1) \
+ X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", , , 1, 0, 0, 0, 0, 0, 1) \
+ X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6", , , 1, 0, 0, 0, 0, 0, 1) \
+ X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7", , , 1, 0, 0, 0, 0, 0, 1) \
+//#define X(val, init, name, name16, name8, scratch, preserved, stackptr,
+// frameptr, isI8, isInt, isFP)
+
+
+#define ICEINSTX8632BR_TABLE \
+ /* enum value, dump, emit */ \
+ X(Br_a, "a", "ja") \
+ X(Br_ae, "ae", "jae") \
+ X(Br_b, "b", "jb") \
+ X(Br_be, "be", "jbe") \
+ X(Br_e, "e", "je") \
+ X(Br_g, "g", "jg") \
+ X(Br_ge, "ge", "jge") \
+ X(Br_l, "l", "jl") \
+ X(Br_le, "le", "jle") \
+ X(Br_ne, "ne", "jne") \
+ X(Br_np, "np", "jnp") \
+ X(Br_p, "p", "jp") \
+//#define X(tag, dump, emit)
+
+#define ICETYPEX8632_TABLE \
+ /* tag, cvt, sdss, width */ \
+ X(IceType_void, "?", , "???") \
+ X(IceType_i1, "i", , "byte ptr") \
+ X(IceType_i8, "i", , "byte ptr") \
+ X(IceType_i16, "i", , "word ptr") \
+ X(IceType_i32, "i", , "dword ptr") \
+ X(IceType_i64, "i", , "qword ptr") \
+ X(IceType_f32, "s", "ss", "dword ptr") \
+ X(IceType_f64, "d", "sd", "qword ptr") \
+ X(IceType_NUM, "?", , "???") \
+//#define X(tag, cvt, sdss, width)
+
+#endif // SUBZERO_SRC_ICEINSTX8632_DEF
diff --git a/src/IceInstX8632.h b/src/IceInstX8632.h
new file mode 100644
index 0000000..8a6f14a
--- /dev/null
+++ b/src/IceInstX8632.h
@@ -0,0 +1,720 @@
+//===- subzero/src/IceInstX8632.h - Low-level x86 instructions --*- C++ -*-===//
+//
+// The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the InstX8632 and OperandX8632 classes and
+// their subclasses. This represents the machine instructions and
+// operands used for x86-32 code selection.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICEINSTX8632_H
+#define SUBZERO_SRC_ICEINSTX8632_H
+
+#include "IceDefs.h"
+#include "IceInst.h"
+#include "IceInstX8632.def"
+#include "IceOperand.h"
+
+namespace Ice {
+
+class TargetX8632;
+
+// OperandX8632 extends the Operand hierarchy. Its subclasses are
+// OperandX8632Mem and VariableSplit.
+class OperandX8632 : public Operand {
+public:
+ enum OperandKindX8632 {
+ k__Start = Operand::kTarget,
+ kMem,
+ kSplit
+ };
+ virtual void emit(const Cfg *Func) const = 0;
+ void dump(const Cfg *Func) const;
+
+protected:
+ OperandX8632(OperandKindX8632 Kind, Type Ty)
+ : Operand(static_cast<OperandKind>(Kind), Ty) {}
+ virtual ~OperandX8632() {}
+
+private:
+ OperandX8632(const OperandX8632 &) LLVM_DELETED_FUNCTION;
+ OperandX8632 &operator=(const OperandX8632 &) LLVM_DELETED_FUNCTION;
+};
+
+// OperandX8632Mem represents the m32 addressing mode, with optional
+// base and index registers, a constant offset, and a fixed shift
+// value for the index register.
+class OperandX8632Mem : public OperandX8632 {
+public:
+ static OperandX8632Mem *create(Cfg *Func, Type Ty, Variable *Base,
+ Constant *Offset, Variable *Index = NULL,
+ uint32_t Shift = 0) {
+ return new (Func->allocate<OperandX8632Mem>())
+ OperandX8632Mem(Func, Ty, Base, Offset, Index, Shift);
+ }
+ Variable *getBase() const { return Base; }
+ Constant *getOffset() const { return Offset; }
+ Variable *getIndex() const { return Index; }
+ uint32_t getShift() const { return Shift; }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+
+ static bool classof(const Operand *Operand) {
+ return Operand->getKind() == static_cast<OperandKind>(kMem);
+ }
+
+private:
+ OperandX8632Mem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
+ Variable *Index, uint32_t Shift);
+ OperandX8632Mem(const OperandX8632Mem &) LLVM_DELETED_FUNCTION;
+ OperandX8632Mem &operator=(const OperandX8632Mem &) LLVM_DELETED_FUNCTION;
+ virtual ~OperandX8632Mem() {}
+ Variable *Base;
+ Constant *Offset;
+ Variable *Index;
+ uint32_t Shift;
+};
+
+// VariableSplit is a way to treat an f64 memory location as a pair
+// of i32 locations (Low and High). This is needed for some cases
+// of the Bitcast instruction. Since it's not possible for integer
+// registers to access the XMM registers and vice versa, the
+// lowering forces the f64 to be spilled to the stack and then
+// accesses through the VariableSplit.
+class VariableSplit : public OperandX8632 {
+public:
+ enum Portion {
+ Low,
+ High
+ };
+ static VariableSplit *create(Cfg *Func, Variable *Var, Portion Part) {
+ return new (Func->allocate<VariableSplit>()) VariableSplit(Func, Var, Part);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+
+ static bool classof(const Operand *Operand) {
+ return Operand->getKind() == static_cast<OperandKind>(kSplit);
+ }
+
+private:
+ VariableSplit(Cfg *Func, Variable *Var, Portion Part)
+ : OperandX8632(kSplit, IceType_i32), Func(Func), Var(Var), Part(Part) {
+ assert(Var->getType() == IceType_f64);
+ Vars = Func->allocateArrayOf<Variable *>(1);
+ Vars[0] = Var;
+ NumVars = 1;
+ }
+ VariableSplit(const VariableSplit &) LLVM_DELETED_FUNCTION;
+ VariableSplit &operator=(const VariableSplit &) LLVM_DELETED_FUNCTION;
+ virtual ~VariableSplit() { Func->deallocateArrayOf<Variable *>(Vars); }
+ Cfg *Func; // Held only for the destructor.
+ Variable *Var;
+ Portion Part;
+};
+
+class InstX8632 : public InstTarget {
+public:
+ enum InstKindX8632 {
+ k__Start = Inst::Target,
+ Adc,
+ Add,
+ Addss,
+ And,
+ Br,
+ Call,
+ Cdq,
+ Cvt,
+ Div,
+ Divss,
+ Fld,
+ Fstp,
+ Icmp,
+ Idiv,
+ Imul,
+ Label,
+ Load,
+ Mov,
+ Movsx,
+ Movzx,
+ Mul,
+ Mulss,
+ Or,
+ Pop,
+ Push,
+ Ret,
+ Sar,
+ Sbb,
+ Shl,
+ Shld,
+ Shr,
+ Shrd,
+ Store,
+ Sub,
+ Subss,
+ Test,
+ Ucomiss,
+ Xor
+ };
+ static const char *getWidthString(Type Ty);
+ virtual void emit(const Cfg *Func) const = 0;
+ virtual void dump(const Cfg *Func) const;
+
+protected:
+ InstX8632(Cfg *Func, InstKindX8632 Kind, SizeT Maxsrcs, Variable *Dest)
+ : InstTarget(Func, static_cast<InstKind>(Kind), Maxsrcs, Dest) {}
+ virtual ~InstX8632() {}
+ static bool isClassof(const Inst *Inst, InstKindX8632 MyKind) {
+ return Inst->getKind() == static_cast<InstKind>(MyKind);
+ }
+
+private:
+ InstX8632(const InstX8632 &) LLVM_DELETED_FUNCTION;
+ InstX8632 &operator=(const InstX8632 &) LLVM_DELETED_FUNCTION;
+};
+
+// InstX8632Label represents an intra-block label that is the
+// target of an intra-block branch. These are used for lowering i1
+// calculations, Select instructions, and 64-bit compares on a 32-bit
+// architecture, without basic block splitting. Basic block splitting
+// is not so desirable for several reasons, one of which is the impact
+// on decisions based on whether a variable's live range spans
+// multiple basic blocks.
+//
+// Intra-block control flow must be used with caution. Consider the
+// sequence for "c = (a >= b ? x : y)".
+// cmp a, b
+// br lt, L1
+// mov c, x
+// jmp L2
+// L1:
+// mov c, y
+// L2:
+//
+// Labels L1 and L2 are intra-block labels. Without knowledge of the
+// intra-block control flow, liveness analysis will determine the "mov
+// c, x" instruction to be dead. One way to prevent this is to insert
+// a "FakeUse(c)" instruction anywhere between the two "mov c, ..."
+// instructions, e.g.:
+//
+// cmp a, b
+// br lt, L1
+// mov c, x
+// jmp L2
+// FakeUse(c)
+// L1:
+// mov c, y
+// L2:
+//
+// The down-side is that "mov c, x" can never be dead-code eliminated
+// even if there are no uses of c. As unlikely as this situation is,
+// it may be prevented by running dead code elimination before
+// lowering.
+class InstX8632Label : public InstX8632 {
+public:
+ static InstX8632Label *create(Cfg *Func, TargetX8632 *Target) {
+ return new (Func->allocate<InstX8632Label>()) InstX8632Label(Func, Target);
+ }
+ IceString getName(const Cfg *Func) const;
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+
+private:
+ InstX8632Label(Cfg *Func, TargetX8632 *Target);
+ InstX8632Label(const InstX8632Label &) LLVM_DELETED_FUNCTION;
+ InstX8632Label &operator=(const InstX8632Label &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Label() {}
+ SizeT Number; // used only for unique label string generation
+};
+
+// Conditional and unconditional branch instruction.
+class InstX8632Br : public InstX8632 {
+public:
+ enum BrCond {
+#define X(tag, dump, emit) tag,
+ ICEINSTX8632BR_TABLE
+#undef X
+ Br_None
+ };
+
+ // Create a conditional branch to a node.
+ static InstX8632Br *create(Cfg *Func, CfgNode *TargetTrue,
+ CfgNode *TargetFalse, BrCond Condition) {
+ return new (Func->allocate<InstX8632Br>())
+ InstX8632Br(Func, TargetTrue, TargetFalse, NULL, Condition);
+ }
+ // Create an unconditional branch to a node.
+ static InstX8632Br *create(Cfg *Func, CfgNode *Target) {
+ return new (Func->allocate<InstX8632Br>())
+ InstX8632Br(Func, NULL, Target, NULL, Br_None);
+ }
+ // Create a non-terminator conditional branch to a node, with a
+ // fallthrough to the next instruction in the current node. This is
+ // used for switch lowering.
+ static InstX8632Br *create(Cfg *Func, CfgNode *Target, BrCond Condition) {
+ return new (Func->allocate<InstX8632Br>())
+ InstX8632Br(Func, Target, NULL, NULL, Condition);
+ }
+ // Create a conditional intra-block branch (or unconditional, if
+ // Condition==None) to a label in the current block.
+ static InstX8632Br *create(Cfg *Func, InstX8632Label *Label,
+ BrCond Condition) {
+ return new (Func->allocate<InstX8632Br>())
+ InstX8632Br(Func, NULL, NULL, Label, Condition);
+ }
+ CfgNode *getTargetTrue() const { return TargetTrue; }
+ CfgNode *getTargetFalse() const { return TargetFalse; }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Br); }
+
+private:
+ InstX8632Br(Cfg *Func, CfgNode *TargetTrue, CfgNode *TargetFalse,
+ InstX8632Label *Label, BrCond Condition);
+ InstX8632Br(const InstX8632Br &) LLVM_DELETED_FUNCTION;
+ InstX8632Br &operator=(const InstX8632Br &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Br() {}
+ BrCond Condition;
+ CfgNode *TargetTrue;
+ CfgNode *TargetFalse;
+ InstX8632Label *Label; // Intra-block branch target
+};
+
+// Call instruction. Arguments should have already been pushed.
+class InstX8632Call : public InstX8632 {
+public:
+ static InstX8632Call *create(Cfg *Func, Variable *Dest, Operand *CallTarget) {
+ return new (Func->allocate<InstX8632Call>())
+ InstX8632Call(Func, Dest, CallTarget);
+ }
+ Operand *getCallTarget() const { return getSrc(0); }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Call); }
+
+private:
+ InstX8632Call(Cfg *Func, Variable *Dest, Operand *CallTarget);
+ InstX8632Call(const InstX8632Call &) LLVM_DELETED_FUNCTION;
+ InstX8632Call &operator=(const InstX8632Call &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Call() {}
+};
+
+// See the definition of emitTwoAddress() for a description of
+// ShiftHack.
+void emitTwoAddress(const char *Opcode, const Inst *Inst, const Cfg *Func,
+ bool ShiftHack = false);
+
+template <InstX8632::InstKindX8632 K, bool ShiftHack = false>
+class InstX8632Binop : public InstX8632 {
+public:
+ // Create an ordinary binary-op instruction like add or sub.
+ static InstX8632Binop *create(Cfg *Func, Variable *Dest, Operand *Source) {
+ return new (Func->allocate<InstX8632Binop>())
+ InstX8632Binop(Func, Dest, Source);
+ }
+ virtual void emit(const Cfg *Func) const {
+ emitTwoAddress(Opcode, this, Func, ShiftHack);
+ }
+ virtual void dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = " << Opcode << "." << getDest()->getType() << " ";
+ dumpSources(Func);
+ }
+ static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
+
+private:
+ InstX8632Binop(Cfg *Func, Variable *Dest, Operand *Source)
+ : InstX8632(Func, K, 2, Dest) {
+ addSource(Dest);
+ addSource(Source);
+ }
+ InstX8632Binop(const InstX8632Binop &) LLVM_DELETED_FUNCTION;
+ InstX8632Binop &operator=(const InstX8632Binop &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Binop() {}
+ static const char *Opcode;
+};
+
+template <InstX8632::InstKindX8632 K> class InstX8632Ternop : public InstX8632 {
+public:
+ // Create a ternary-op instruction like div or idiv.
+ static InstX8632Ternop *create(Cfg *Func, Variable *Dest, Operand *Source1,
+ Operand *Source2) {
+ return new (Func->allocate<InstX8632Ternop>())
+ InstX8632Ternop(Func, Dest, Source1, Source2);
+ }
+ virtual void emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ assert(getSrcSize() == 3);
+ Str << "\t" << Opcode << "\t";
+ getSrc(1)->emit(Func);
+ Str << "\n";
+ }
+ virtual void dump(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrDump();
+ dumpDest(Func);
+ Str << " = " << Opcode << "." << getDest()->getType() << " ";
+ dumpSources(Func);
+ }
+ static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
+
+private:
+ InstX8632Ternop(Cfg *Func, Variable *Dest, Operand *Source1, Operand *Source2)
+ : InstX8632(Func, K, 3, Dest) {
+ addSource(Dest);
+ addSource(Source1);
+ addSource(Source2);
+ }
+ InstX8632Ternop(const InstX8632Ternop &) LLVM_DELETED_FUNCTION;
+ InstX8632Ternop &operator=(const InstX8632Ternop &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Ternop() {}
+ static const char *Opcode;
+};
+
+typedef InstX8632Binop<InstX8632::Add> InstX8632Add;
+typedef InstX8632Binop<InstX8632::Adc> InstX8632Adc;
+typedef InstX8632Binop<InstX8632::Addss> InstX8632Addss;
+typedef InstX8632Binop<InstX8632::Sub> InstX8632Sub;
+typedef InstX8632Binop<InstX8632::Subss> InstX8632Subss;
+typedef InstX8632Binop<InstX8632::Sbb> InstX8632Sbb;
+typedef InstX8632Binop<InstX8632::And> InstX8632And;
+typedef InstX8632Binop<InstX8632::Or> InstX8632Or;
+typedef InstX8632Binop<InstX8632::Xor> InstX8632Xor;
+typedef InstX8632Binop<InstX8632::Imul> InstX8632Imul;
+typedef InstX8632Binop<InstX8632::Mulss> InstX8632Mulss;
+typedef InstX8632Binop<InstX8632::Divss> InstX8632Divss;
+typedef InstX8632Binop<InstX8632::Shl, true> InstX8632Shl;
+typedef InstX8632Binop<InstX8632::Shr, true> InstX8632Shr;
+typedef InstX8632Binop<InstX8632::Sar, true> InstX8632Sar;
+typedef InstX8632Ternop<InstX8632::Idiv> InstX8632Idiv;
+typedef InstX8632Ternop<InstX8632::Div> InstX8632Div;
+
+// Mul instruction - unsigned multiply.
+class InstX8632Mul : public InstX8632 {
+public:
+ static InstX8632Mul *create(Cfg *Func, Variable *Dest, Variable *Source1,
+ Operand *Source2) {
+ return new (Func->allocate<InstX8632Mul>())
+ InstX8632Mul(Func, Dest, Source1, Source2);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Mul); }
+
+private:
+ InstX8632Mul(Cfg *Func, Variable *Dest, Variable *Source1, Operand *Source2);
+ InstX8632Mul(const InstX8632Mul &) LLVM_DELETED_FUNCTION;
+ InstX8632Mul &operator=(const InstX8632Mul &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Mul() {}
+};
+
+// Shld instruction - shift across a pair of operands. TODO: Verify
+// that the validator accepts the shld instruction.
+class InstX8632Shld : public InstX8632 {
+public:
+ static InstX8632Shld *create(Cfg *Func, Variable *Dest, Variable *Source1,
+ Variable *Source2) {
+ return new (Func->allocate<InstX8632Shld>())
+ InstX8632Shld(Func, Dest, Source1, Source2);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Shld); }
+
+private:
+ InstX8632Shld(Cfg *Func, Variable *Dest, Variable *Source1,
+ Variable *Source2);
+ InstX8632Shld(const InstX8632Shld &) LLVM_DELETED_FUNCTION;
+ InstX8632Shld &operator=(const InstX8632Shld &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Shld() {}
+};
+
+// Shrd instruction - shift across a pair of operands. TODO: Verify
+// that the validator accepts the shrd instruction.
+class InstX8632Shrd : public InstX8632 {
+public:
+ static InstX8632Shrd *create(Cfg *Func, Variable *Dest, Variable *Source1,
+ Variable *Source2) {
+ return new (Func->allocate<InstX8632Shrd>())
+ InstX8632Shrd(Func, Dest, Source1, Source2);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Shrd); }
+
+private:
+ InstX8632Shrd(Cfg *Func, Variable *Dest, Variable *Source1,
+ Variable *Source2);
+ InstX8632Shrd(const InstX8632Shrd &) LLVM_DELETED_FUNCTION;
+ InstX8632Shrd &operator=(const InstX8632Shrd &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Shrd() {}
+};
+
+// Cdq instruction - sign-extend eax into edx
+class InstX8632Cdq : public InstX8632 {
+public:
+ static InstX8632Cdq *create(Cfg *Func, Variable *Dest, Operand *Source) {
+ return new (Func->allocate<InstX8632Cdq>())
+ InstX8632Cdq(Func, Dest, Source);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Cdq); }
+
+private:
+ InstX8632Cdq(Cfg *Func, Variable *Dest, Operand *Source);
+ InstX8632Cdq(const InstX8632Cdq &) LLVM_DELETED_FUNCTION;
+ InstX8632Cdq &operator=(const InstX8632Cdq &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Cdq() {}
+};
+
+// Cvt instruction - wrapper for cvtsX2sY where X and Y are in {s,d,i}
+// as appropriate. s=float, d=double, i=int. X and Y are determined
+// from dest/src types. Sign and zero extension on the integer
+// operand needs to be done separately.
+class InstX8632Cvt : public InstX8632 {
+public:
+ static InstX8632Cvt *create(Cfg *Func, Variable *Dest, Operand *Source) {
+ return new (Func->allocate<InstX8632Cvt>())
+ InstX8632Cvt(Func, Dest, Source);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Cvt); }
+
+private:
+ InstX8632Cvt(Cfg *Func, Variable *Dest, Operand *Source);
+ InstX8632Cvt(const InstX8632Cvt &) LLVM_DELETED_FUNCTION;
+ InstX8632Cvt &operator=(const InstX8632Cvt &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Cvt() {}
+};
+
+// cmp - Integer compare instruction.
+class InstX8632Icmp : public InstX8632 {
+public:
+ static InstX8632Icmp *create(Cfg *Func, Operand *Src1, Operand *Src2) {
+ return new (Func->allocate<InstX8632Icmp>())
+ InstX8632Icmp(Func, Src1, Src2);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Icmp); }
+
+private:
+ InstX8632Icmp(Cfg *Func, Operand *Src1, Operand *Src2);
+ InstX8632Icmp(const InstX8632Icmp &) LLVM_DELETED_FUNCTION;
+ InstX8632Icmp &operator=(const InstX8632Icmp &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Icmp() {}
+};
+
+// ucomiss/ucomisd - floating-point compare instruction.
+class InstX8632Ucomiss : public InstX8632 {
+public:
+ static InstX8632Ucomiss *create(Cfg *Func, Operand *Src1, Operand *Src2) {
+ return new (Func->allocate<InstX8632Ucomiss>())
+ InstX8632Ucomiss(Func, Src1, Src2);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Ucomiss); }
+
+private:
+ InstX8632Ucomiss(Cfg *Func, Operand *Src1, Operand *Src2);
+ InstX8632Ucomiss(const InstX8632Ucomiss &) LLVM_DELETED_FUNCTION;
+ InstX8632Ucomiss &operator=(const InstX8632Ucomiss &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Ucomiss() {}
+};
+
+// Test instruction.
+class InstX8632Test : public InstX8632 {
+public:
+ static InstX8632Test *create(Cfg *Func, Operand *Source1, Operand *Source2) {
+ return new (Func->allocate<InstX8632Test>())
+ InstX8632Test(Func, Source1, Source2);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Test); }
+
+private:
+ InstX8632Test(Cfg *Func, Operand *Source1, Operand *Source2);
+ InstX8632Test(const InstX8632Test &) LLVM_DELETED_FUNCTION;
+ InstX8632Test &operator=(const InstX8632Test &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Test() {}
+};
+
+// This is essentially a "mov" instruction with an OperandX8632Mem
+// operand instead of Variable as the destination. It's important
+// for liveness that there is no Dest operand.
+class InstX8632Store : public InstX8632 {
+public:
+ static InstX8632Store *create(Cfg *Func, Operand *Value, OperandX8632 *Mem) {
+ return new (Func->allocate<InstX8632Store>())
+ InstX8632Store(Func, Value, Mem);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Store); }
+
+private:
+ InstX8632Store(Cfg *Func, Operand *Value, OperandX8632 *Mem);
+ InstX8632Store(const InstX8632Store &) LLVM_DELETED_FUNCTION;
+ InstX8632Store &operator=(const InstX8632Store &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Store() {}
+};
+
+// Move/assignment instruction - wrapper for mov/movss/movsd.
+class InstX8632Mov : public InstX8632 {
+public:
+ static InstX8632Mov *create(Cfg *Func, Variable *Dest, Operand *Source) {
+ return new (Func->allocate<InstX8632Mov>())
+ InstX8632Mov(Func, Dest, Source);
+ }
+ virtual bool isRedundantAssign() const;
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Mov); }
+
+private:
+ InstX8632Mov(Cfg *Func, Variable *Dest, Operand *Source);
+ InstX8632Mov(const InstX8632Mov &) LLVM_DELETED_FUNCTION;
+ InstX8632Mov &operator=(const InstX8632Mov &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Mov() {}
+};
+
+// Movsx - copy from a narrower integer type to a wider integer
+// type, with sign extension.
+class InstX8632Movsx : public InstX8632 {
+public:
+ static InstX8632Movsx *create(Cfg *Func, Variable *Dest, Operand *Source) {
+ return new (Func->allocate<InstX8632Movsx>())
+ InstX8632Movsx(Func, Dest, Source);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Movsx); }
+
+private:
+ InstX8632Movsx(Cfg *Func, Variable *Dest, Operand *Source);
+ InstX8632Movsx(const InstX8632Movsx &) LLVM_DELETED_FUNCTION;
+ InstX8632Movsx &operator=(const InstX8632Movsx &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Movsx() {}
+};
+
+// Movsx - copy from a narrower integer type to a wider integer
+// type, with zero extension.
+class InstX8632Movzx : public InstX8632 {
+public:
+ static InstX8632Movzx *create(Cfg *Func, Variable *Dest, Operand *Source) {
+ return new (Func->allocate<InstX8632Movzx>())
+ InstX8632Movzx(Func, Dest, Source);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Movzx); }
+
+private:
+ InstX8632Movzx(Cfg *Func, Variable *Dest, Operand *Source);
+ InstX8632Movzx(const InstX8632Movzx &) LLVM_DELETED_FUNCTION;
+ InstX8632Movzx &operator=(const InstX8632Movzx &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Movzx() {}
+};
+
+// Fld - load a value onto the x87 FP stack.
+class InstX8632Fld : public InstX8632 {
+public:
+ static InstX8632Fld *create(Cfg *Func, Operand *Src) {
+ return new (Func->allocate<InstX8632Fld>()) InstX8632Fld(Func, Src);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Fld); }
+
+private:
+ InstX8632Fld(Cfg *Func, Operand *Src);
+ InstX8632Fld(const InstX8632Fld &) LLVM_DELETED_FUNCTION;
+ InstX8632Fld &operator=(const InstX8632Fld &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Fld() {}
+};
+
+// Fstp - store x87 st(0) into memory and pop st(0).
+class InstX8632Fstp : public InstX8632 {
+public:
+ static InstX8632Fstp *create(Cfg *Func, Variable *Dest) {
+ return new (Func->allocate<InstX8632Fstp>()) InstX8632Fstp(Func, Dest);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Fstp); }
+
+private:
+ InstX8632Fstp(Cfg *Func, Variable *Dest);
+ InstX8632Fstp(const InstX8632Fstp &) LLVM_DELETED_FUNCTION;
+ InstX8632Fstp &operator=(const InstX8632Fstp &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Fstp() {}
+};
+
+class InstX8632Pop : public InstX8632 {
+public:
+ static InstX8632Pop *create(Cfg *Func, Variable *Dest) {
+ return new (Func->allocate<InstX8632Pop>()) InstX8632Pop(Func, Dest);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Pop); }
+
+private:
+ InstX8632Pop(Cfg *Func, Variable *Dest);
+ InstX8632Pop(const InstX8632Pop &) LLVM_DELETED_FUNCTION;
+ InstX8632Pop &operator=(const InstX8632Pop &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Pop() {}
+};
+
+class InstX8632Push : public InstX8632 {
+public:
+ static InstX8632Push *create(Cfg *Func, Operand *Source,
+ bool SuppressStackAdjustment) {
+ return new (Func->allocate<InstX8632Push>())
+ InstX8632Push(Func, Source, SuppressStackAdjustment);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Push); }
+
+private:
+ InstX8632Push(Cfg *Func, Operand *Source, bool SuppressStackAdjustment);
+ InstX8632Push(const InstX8632Push &) LLVM_DELETED_FUNCTION;
+ InstX8632Push &operator=(const InstX8632Push &) LLVM_DELETED_FUNCTION;
+ bool SuppressStackAdjustment;
+ virtual ~InstX8632Push() {}
+};
+
+// Ret instruction. Currently only supports the "ret" version that
+// does not pop arguments. This instruction takes a Source operand
+// (for non-void returning functions) for liveness analysis, though
+// a FakeUse before the ret would do just as well.
+class InstX8632Ret : public InstX8632 {
+public:
+ static InstX8632Ret *create(Cfg *Func, Variable *Source = NULL) {
+ return new (Func->allocate<InstX8632Ret>()) InstX8632Ret(Func, Source);
+ }
+ virtual void emit(const Cfg *Func) const;
+ virtual void dump(const Cfg *Func) const;
+ static bool classof(const Inst *Inst) { return isClassof(Inst, Ret); }
+
+private:
+ InstX8632Ret(Cfg *Func, Variable *Source);
+ InstX8632Ret(const InstX8632Ret &) LLVM_DELETED_FUNCTION;
+ InstX8632Ret &operator=(const InstX8632Ret &) LLVM_DELETED_FUNCTION;
+ virtual ~InstX8632Ret() {}
+};
+
+} // end of namespace Ice
+
+#endif // SUBZERO_SRC_ICEINSTX8632_H
diff --git a/src/IceOperand.cpp b/src/IceOperand.cpp
index 1009a33..56520d3 100644
--- a/src/IceOperand.cpp
+++ b/src/IceOperand.cpp
@@ -16,6 +16,7 @@
#include "IceCfg.h"
#include "IceInst.h"
#include "IceOperand.h"
+#include "IceTargetLowering.h" // dumping stack/frame pointer register
namespace Ice {
@@ -27,6 +28,14 @@
return A.Name < B.Name;
}
+bool operator<(const RegWeight &A, const RegWeight &B) {
+ return A.getWeight() < B.getWeight();
+}
+bool operator<=(const RegWeight &A, const RegWeight &B) { return !(B < A); }
+bool operator==(const RegWeight &A, const RegWeight &B) {
+ return !(B < A) && !(A < B);
+}
+
void Variable::setUse(const Inst *Inst, const CfgNode *Node) {
if (DefNode == NULL)
return;
@@ -66,19 +75,57 @@
return buf;
}
+Variable Variable::asType(Type Ty) {
+ Variable V(Ty, DefNode, Number, Name);
+ V.RegNum = RegNum;
+ V.StackOffset = StackOffset;
+ return V;
+}
+
// ======================== dump routines ======================== //
+void Variable::emit(const Cfg *Func) const {
+ Func->getTarget()->emitVariable(this, Func);
+}
+
void Variable::dump(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrDump();
const CfgNode *CurrentNode = Func->getCurrentNode();
(void)CurrentNode; // used only in assert()
assert(CurrentNode == NULL || DefNode == NULL || DefNode == CurrentNode);
- Str << "%" << getName();
+ if (Func->getContext()->isVerbose(IceV_RegOrigins) ||
+ (!hasReg() && !Func->getTarget()->hasComputedFrame()))
+ Str << "%" << getName();
+ if (hasReg()) {
+ if (Func->getContext()->isVerbose(IceV_RegOrigins))
+ Str << ":";
+ Str << Func->getTarget()->getRegName(RegNum, getType());
+ } else if (Func->getTarget()->hasComputedFrame()) {
+ if (Func->getContext()->isVerbose(IceV_RegOrigins))
+ Str << ":";
+ Str << "[" << Func->getTarget()->getRegName(
+ Func->getTarget()->getFrameOrStackReg(), IceType_i32);
+ int32_t Offset = getStackOffset();
+ if (Offset) {
+ if (Offset > 0)
+ Str << "+";
+ Str << Offset;
+ }
+ Str << "]";
+ }
}
-void Operand::dump(const Cfg *Func) const {
- Ostream &Str = Func->getContext()->getStrDump();
- Str << "Operand<?>";
+void ConstantRelocatable::emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ if (SuppressMangling)
+ Str << Name;
+ else
+ Str << Func->getContext()->mangleName(Name);
+ if (Offset) {
+ if (Offset > 0)
+ Str << "+";
+ Str << Offset;
+ }
}
void ConstantRelocatable::dump(const Cfg *Func) const {
@@ -88,4 +135,12 @@
Str << "+" << Offset;
}
+Ostream &operator<<(Ostream &Str, const RegWeight &W) {
+ if (W.getWeight() == RegWeight::Inf)
+ Str << "Inf";
+ else
+ Str << W.getWeight();
+ return Str;
+}
+
} // end of namespace Ice
diff --git a/src/IceOperand.h b/src/IceOperand.h
index fcad7b9..c75be78 100644
--- a/src/IceOperand.h
+++ b/src/IceOperand.h
@@ -49,6 +49,7 @@
assert(I < getNumVars());
return Vars[I];
}
+ virtual void emit(const Cfg *Func) const = 0;
virtual void dump(const Cfg *Func) const = 0;
// Query whether this object was allocated in isolation, or added to
@@ -79,6 +80,7 @@
// constants are allocated from a global arena and are pooled.
class Constant : public Operand {
public:
+ virtual void emit(const Cfg *Func) const = 0;
virtual void dump(const Cfg *Func) const = 0;
static bool classof(const Operand *Operand) {
@@ -107,6 +109,10 @@
ConstantPrimitive(Ty, Value);
}
T getValue() const { return Value; }
+ virtual void emit(const Cfg *Func) const {
+ Ostream &Str = Func->getContext()->getStrEmit();
+ Str << getValue();
+ }
virtual void dump(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrDump();
Str << getValue();
@@ -163,6 +169,7 @@
IceString getName() const { return Name; }
void setSuppressMangling(bool Value) { SuppressMangling = Value; }
bool getSuppressMangling() const { return SuppressMangling; }
+ virtual void emit(const Cfg *Func) const;
virtual void dump(const Cfg *Func) const;
static bool classof(const Operand *Operand) {
@@ -184,6 +191,34 @@
bool SuppressMangling;
};
+// RegWeight is a wrapper for a uint32_t weight value, with a
+// special value that represents infinite weight, and an addWeight()
+// method that ensures that W+infinity=infinity.
+class RegWeight {
+public:
+ RegWeight() : Weight(0) {}
+ RegWeight(uint32_t Weight) : Weight(Weight) {}
+ const static uint32_t Inf = ~0; // Force regalloc to give a register
+ const static uint32_t Zero = 0; // Force regalloc NOT to give a register
+ void addWeight(uint32_t Delta) {
+ if (Delta == Inf)
+ Weight = Inf;
+ else if (Weight != Inf)
+ Weight += Delta;
+ }
+ void addWeight(const RegWeight &Other) { addWeight(Other.Weight); }
+ void setWeight(uint32_t Val) { Weight = Val; }
+ uint32_t getWeight() const { return Weight; }
+ bool isInf() const { return Weight == Inf; }
+
+private:
+ uint32_t Weight;
+};
+Ostream &operator<<(Ostream &Str, const RegWeight &W);
+bool operator<(const RegWeight &A, const RegWeight &B);
+bool operator<=(const RegWeight &A, const RegWeight &B);
+bool operator==(const RegWeight &A, const RegWeight &B);
+
// Variable represents an operand that is register-allocated or
// stack-allocated. If it is register-allocated, it will ultimately
// have a non-negative RegNum field.
@@ -208,23 +243,66 @@
bool getIsArg() const { return IsArgument; }
void setIsArg(Cfg *Func);
+ int32_t getStackOffset() const { return StackOffset; }
+ void setStackOffset(int32_t Offset) { StackOffset = Offset; }
+
+ static const int32_t NoRegister = -1;
+ bool hasReg() const { return getRegNum() != NoRegister; }
+ int32_t getRegNum() const { return RegNum; }
+ void setRegNum(int32_t NewRegNum) {
+ // Regnum shouldn't be set more than once.
+ assert(!hasReg() || RegNum == NewRegNum);
+ RegNum = NewRegNum;
+ }
+
+ RegWeight getWeight() const { return Weight; }
+ void setWeight(uint32_t NewWeight) { Weight = NewWeight; }
+ void setWeightInfinite() { Weight = RegWeight::Inf; }
+
+ Variable *getPreferredRegister() const { return RegisterPreference; }
+ bool getRegisterOverlap() const { return AllowRegisterOverlap; }
+ void setPreferredRegister(Variable *Prefer, bool Overlap) {
+ RegisterPreference = Prefer;
+ AllowRegisterOverlap = Overlap;
+ }
+
+ Variable *getLo() const { return LoVar; }
+ Variable *getHi() const { return HiVar; }
+ void setLoHi(Variable *Lo, Variable *Hi) {
+ assert(LoVar == NULL);
+ assert(HiVar == NULL);
+ LoVar = Lo;
+ HiVar = Hi;
+ }
+ // Creates a temporary copy of the variable with a different type.
+ // Used primarily for syntactic correctness of textual assembly
+ // emission. Note that only basic information is copied, in
+ // particular not DefInst, IsArgument, Weight, RegisterPreference,
+ // AllowRegisterOverlap, LoVar, HiVar, VarsReal.
+ Variable asType(Type Ty);
+
+ virtual void emit(const Cfg *Func) const;
virtual void dump(const Cfg *Func) const;
static bool classof(const Operand *Operand) {
return Operand->getKind() == kVariable;
}
+ // The destructor is public because of the asType() method.
+ virtual ~Variable() {}
+
private:
Variable(Type Ty, const CfgNode *Node, SizeT Index, const IceString &Name)
: Operand(kVariable, Ty), Number(Index), Name(Name), DefInst(NULL),
- DefNode(Node), IsArgument(false) {
+ DefNode(Node), IsArgument(false), StackOffset(0), RegNum(NoRegister),
+ Weight(1), RegisterPreference(NULL), AllowRegisterOverlap(false),
+ LoVar(NULL), HiVar(NULL) {
Vars = VarsReal;
Vars[0] = this;
NumVars = 1;
}
Variable(const Variable &) LLVM_DELETED_FUNCTION;
Variable &operator=(const Variable &) LLVM_DELETED_FUNCTION;
- virtual ~Variable() {}
// Number is unique across all variables, and is used as a
// (bit)vector index for liveness analysis.
const SizeT Number;
@@ -241,6 +319,32 @@
// of incrementally computing and maintaining the information.
const CfgNode *DefNode;
bool IsArgument;
+ // StackOffset is the canonical location on stack (only if
+ // RegNum<0 || IsArgument).
+ int32_t StackOffset;
+ // RegNum is the allocated register, or NoRegister if it isn't
+ // register-allocated.
+ int32_t RegNum;
+ RegWeight Weight; // Register allocation priority
+ // RegisterPreference says that if possible, the register allocator
+ // should prefer the register that was assigned to this linked
+ // variable. It also allows a spill slot to share its stack
+ // location with another variable, if that variable does not get
+ // register-allocated and therefore has a stack location.
+ Variable *RegisterPreference;
+ // AllowRegisterOverlap says that it is OK to honor
+ // RegisterPreference and "share" a register even if the two live
+ // ranges overlap.
+ bool AllowRegisterOverlap;
+ // LoVar and HiVar are needed for lowering from 64 to 32 bits. When
+ // lowering from I64 to I32 on a 32-bit architecture, we split the
+ // variable into two machine-size pieces. LoVar is the low-order
+ // machine-size portion, and HiVar is the remaining high-order
+ // portion. TODO: It's wasteful to penalize all variables on all
+ // targets this way; use a sparser representation. It's also
+ // wasteful for a 64-bit target.
+ Variable *LoVar;
+ Variable *HiVar;
// VarsReal (and Operand::Vars) are set up such that Vars[0] ==
// this.
Variable *VarsReal[1];
diff --git a/src/IceTargetLowering.cpp b/src/IceTargetLowering.cpp
new file mode 100644
index 0000000..0d07475
--- /dev/null
+++ b/src/IceTargetLowering.cpp
@@ -0,0 +1,147 @@
+//===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
+//
+// The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the skeleton of the TargetLowering class,
+// specifically invoking the appropriate lowering method for a given
+// instruction kind and driving global register allocation. It also
+// implements the non-deleted instruction iteration in
+// LoweringContext.
+//
+//===----------------------------------------------------------------------===//
+
+#include "IceCfg.h" // setError()
+#include "IceCfgNode.h"
+#include "IceOperand.h"
+#include "IceTargetLowering.h"
+#include "IceTargetLoweringX8632.h"
+
+namespace Ice {
+
+void LoweringContext::init(CfgNode *N) {
+ Node = N;
+ Cur = getNode()->getInsts().begin();
+ End = getNode()->getInsts().end();
+ skipDeleted(Cur);
+ Next = Cur;
+ advance(Next);
+}
+
+void LoweringContext::insert(Inst *Inst) {
+ getNode()->getInsts().insert(Next, Inst);
+ Inst->updateVars(getNode());
+}
+
+void LoweringContext::skipDeleted(InstList::iterator &I) {
+ while (I != End && (*I)->isDeleted())
+ ++I;
+}
+
+void LoweringContext::advance(InstList::iterator &I) {
+ if (I != End) {
+ ++I;
+ skipDeleted(I);
+ }
+}
+
+TargetLowering *TargetLowering::createLowering(TargetArch Target, Cfg *Func) {
+ // These statements can be #ifdef'd to specialize the code generator
+ // to a subset of the available targets. TODO: use CRTP.
+ if (Target == Target_X8632)
+ return TargetX8632::create(Func);
+#if 0
+ if (Target == Target_X8664)
+ return IceTargetX8664::create(Func);
+ if (Target == Target_ARM32)
+ return IceTargetARM32::create(Func);
+ if (Target == Target_ARM64)
+ return IceTargetARM64::create(Func);
+#endif
+ Func->setError("Unsupported target");
+ return NULL;
+}
+
+// Lowers a single instruction according to the information in
+// Context, by checking the Context.Cur instruction kind and calling
+// the appropriate lowering method. The lowering method should insert
+// target instructions at the Cur.Next insertion point, and should not
+// delete the Context.Cur instruction or advance Context.Cur.
+//
+// The lowering method may look ahead in the instruction stream as
+// desired, and lower additional instructions in conjunction with the
+// current one, for example fusing a compare and branch. If it does,
+// it should advance Context.Cur to point to the next non-deleted
+// instruction to process, and it should delete any additional
+// instructions it consumes.
+void TargetLowering::lower() {
+ assert(!Context.atEnd());
+ Inst *Inst = *Context.getCur();
+ switch (Inst->getKind()) {
+ case Inst::Alloca:
+ lowerAlloca(llvm::dyn_cast<InstAlloca>(Inst));
+ break;
+ case Inst::Arithmetic:
+ lowerArithmetic(llvm::dyn_cast<InstArithmetic>(Inst));
+ break;
+ case Inst::Assign:
+ lowerAssign(llvm::dyn_cast<InstAssign>(Inst));
+ break;
+ case Inst::Br:
+ lowerBr(llvm::dyn_cast<InstBr>(Inst));
+ break;
+ case Inst::Call:
+ lowerCall(llvm::dyn_cast<InstCall>(Inst));
+ break;
+ case Inst::Cast:
+ lowerCast(llvm::dyn_cast<InstCast>(Inst));
+ break;
+ case Inst::Fcmp:
+ lowerFcmp(llvm::dyn_cast<InstFcmp>(Inst));
+ break;
+ case Inst::Icmp:
+ lowerIcmp(llvm::dyn_cast<InstIcmp>(Inst));
+ break;
+ case Inst::Load:
+ lowerLoad(llvm::dyn_cast<InstLoad>(Inst));
+ break;
+ case Inst::Phi:
+ lowerPhi(llvm::dyn_cast<InstPhi>(Inst));
+ break;
+ case Inst::Ret:
+ lowerRet(llvm::dyn_cast<InstRet>(Inst));
+ break;
+ case Inst::Select:
+ lowerSelect(llvm::dyn_cast<InstSelect>(Inst));
+ break;
+ case Inst::Store:
+ lowerStore(llvm::dyn_cast<InstStore>(Inst));
+ break;
+ case Inst::Switch:
+ lowerSwitch(llvm::dyn_cast<InstSwitch>(Inst));
+ break;
+ case Inst::Unreachable:
+ lowerUnreachable(llvm::dyn_cast<InstUnreachable>(Inst));
+ break;
+ case Inst::FakeDef:
+ case Inst::FakeUse:
+ case Inst::FakeKill:
+ case Inst::Target:
+ // These are all Target instruction types and shouldn't be
+ // encountered at this stage.
+ Func->setError("Can't lower unsupported instruction type");
+ break;
+ }
+ Inst->setDeleted();
+
+ postLower();
+
+ Context.advanceCur();
+ Context.advanceNext();
+}
+
+} // end of namespace Ice
diff --git a/src/IceTargetLowering.h b/src/IceTargetLowering.h
new file mode 100644
index 0000000..a24c51d
--- /dev/null
+++ b/src/IceTargetLowering.h
@@ -0,0 +1,197 @@
+//===- subzero/src/IceTargetLowering.h - Lowering interface -----*- C++ -*-===//
+//
+// The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the TargetLowering and LoweringContext
+// classes. TargetLowering is an abstract class used to drive the
+// translation/lowering process. LoweringContext maintains a
+// context for lowering each instruction, offering conveniences such
+// as iterating over non-deleted instructions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICETARGETLOWERING_H
+#define SUBZERO_SRC_ICETARGETLOWERING_H
+
+#include "IceDefs.h"
+#include "IceTypes.h"
+
+#include "IceInst.h" // for the names of the Inst subtypes
+
+namespace Ice {
+
+// LoweringContext makes it easy to iterate through non-deleted
+// instructions in a node, and insert new (lowered) instructions at
+// the current point. Along with the instruction list container and
+// associated iterators, it holds the current node, which is needed
+// when inserting new instructions in order to track whether variables
+// are used as single-block or multi-block.
+class LoweringContext {
+public:
+ LoweringContext() : Node(NULL) {}
+ ~LoweringContext() {}
+ void init(CfgNode *Node);
+ Inst *getNextInst() const {
+ if (Next == End)
+ return NULL;
+ return *Next;
+ }
+ CfgNode *getNode() const { return Node; }
+ bool atEnd() const { return Cur == End; }
+ InstList::iterator getCur() const { return Cur; }
+ InstList::iterator getEnd() const { return End; }
+ void insert(Inst *Inst);
+ void advanceCur() { Cur = Next; }
+ void advanceNext() { advance(Next); }
+ void setInsertPoint(const InstList::iterator &Position) { Next = Position; }
+
+private:
+ // Node is the argument to Inst::updateVars().
+ CfgNode *Node;
+ // Cur points to the current instruction being considered. It is
+ // guaranteed to point to a non-deleted instruction, or to be End.
+ InstList::iterator Cur;
+ // Next doubles as a pointer to the next valid instruction (if any),
+ // and the new-instruction insertion point. It is also updated for
+ // the caller in case the lowering consumes more than one high-level
+ // instruction. It is guaranteed to point to a non-deleted
+ // instruction after Cur, or to be End. TODO: Consider separating
+ // the notion of "next valid instruction" and "new instruction
+ // insertion point", to avoid confusion when previously-deleted
+ // instructions come between the two points.
+ InstList::iterator Next;
+ // End is a copy of Insts.end(), used if Next needs to be advanced.
+ InstList::iterator End;
+
+ void skipDeleted(InstList::iterator &I);
+ void advance(InstList::iterator &I);
+ LoweringContext(const LoweringContext &) LLVM_DELETED_FUNCTION;
+ LoweringContext &operator=(const LoweringContext &) LLVM_DELETED_FUNCTION;
+};
+
+class TargetLowering {
+public:
+ static TargetLowering *createLowering(TargetArch Target, Cfg *Func);
+ void translate() {
+ switch (Ctx->getOptLevel()) {
+ case Opt_m1:
+ translateOm1();
+ break;
+ case Opt_0:
+ translateO0();
+ break;
+ case Opt_1:
+ translateO1();
+ break;
+ case Opt_2:
+ translateO2();
+ break;
+ default:
+ Func->setError("Target doesn't specify lowering steps.");
+ break;
+ }
+ }
+ virtual void translateOm1() {
+ Func->setError("Target doesn't specify Om1 lowering steps.");
+ }
+ virtual void translateO0() {
+ Func->setError("Target doesn't specify O0 lowering steps.");
+ }
+ virtual void translateO1() {
+ Func->setError("Target doesn't specify O1 lowering steps.");
+ }
+ virtual void translateO2() {
+ Func->setError("Target doesn't specify O2 lowering steps.");
+ }
+
+ // Lowers a single instruction.
+ void lower();
+
+ // Returns a variable pre-colored to the specified physical
+ // register. This is generally used to get very direct access to
+ // the register such as in the prolog or epilog or for marking
+ // scratch registers as killed by a call.
+ virtual Variable *getPhysicalRegister(SizeT RegNum) = 0;
+ // Returns a printable name for the register.
+ virtual IceString getRegName(SizeT RegNum, Type Ty) const = 0;
+
+ virtual bool hasFramePointer() const { return false; }
+ virtual SizeT getFrameOrStackReg() const = 0;
+ virtual size_t typeWidthInBytesOnStack(Type Ty) = 0;
+ bool hasComputedFrame() const { return HasComputedFrame; }
+ int32_t getStackAdjustment() const { return StackAdjustment; }
+ void updateStackAdjustment(int32_t Offset) { StackAdjustment += Offset; }
+ void resetStackAdjustment() { StackAdjustment = 0; }
+ LoweringContext &getContext() { return Context; }
+
+ enum RegSet {
+ RegSet_None = 0,
+ RegSet_CallerSave = 1 << 0,
+ RegSet_CalleeSave = 1 << 1,
+ RegSet_StackPointer = 1 << 2,
+ RegSet_FramePointer = 1 << 3,
+ RegSet_All = ~RegSet_None
+ };
+ typedef uint32_t RegSetMask;
+
+ virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include,
+ RegSetMask Exclude) const = 0;
+ virtual const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const = 0;
+ void regAlloc();
+
+ virtual void emitVariable(const Variable *Var, const Cfg *Func) const = 0;
+
+ virtual void addProlog(CfgNode *Node) = 0;
+ virtual void addEpilog(CfgNode *Node) = 0;
+
+ virtual ~TargetLowering() {}
+
+protected:
+ TargetLowering(Cfg *Func)
+ : Func(Func), Ctx(Func->getContext()), HasComputedFrame(false),
+ StackAdjustment(0) {}
+ virtual void lowerAlloca(const InstAlloca *Inst) = 0;
+ virtual void lowerArithmetic(const InstArithmetic *Inst) = 0;
+ virtual void lowerAssign(const InstAssign *Inst) = 0;
+ virtual void lowerBr(const InstBr *Inst) = 0;
+ virtual void lowerCall(const InstCall *Inst) = 0;
+ virtual void lowerCast(const InstCast *Inst) = 0;
+ virtual void lowerFcmp(const InstFcmp *Inst) = 0;
+ virtual void lowerIcmp(const InstIcmp *Inst) = 0;
+ virtual void lowerLoad(const InstLoad *Inst) = 0;
+ virtual void lowerPhi(const InstPhi *Inst) = 0;
+ virtual void lowerRet(const InstRet *Inst) = 0;
+ virtual void lowerSelect(const InstSelect *Inst) = 0;
+ virtual void lowerStore(const InstStore *Inst) = 0;
+ virtual void lowerSwitch(const InstSwitch *Inst) = 0;
+ virtual void lowerUnreachable(const InstUnreachable *Inst) = 0;
+
+ // This gives the target an opportunity to post-process the lowered
+ // expansion before returning. The primary intention is to do some
+ // Register Manager activity as necessary, specifically to eagerly
+ // allocate registers based on affinity and other factors. The
+ // simplest lowering does nothing here and leaves it all to a
+ // subsequent global register allocation pass.
+ virtual void postLower() {}
+
+ Cfg *Func;
+ GlobalContext *Ctx;
+ bool HasComputedFrame;
+ // StackAdjustment keeps track of the current stack offset from its
+ // natural location, as arguments are pushed for a function call.
+ int32_t StackAdjustment;
+ LoweringContext Context;
+
+private:
+ TargetLowering(const TargetLowering &) LLVM_DELETED_FUNCTION;
+ TargetLowering &operator=(const TargetLowering &) LLVM_DELETED_FUNCTION;
+};
+
+} // end of namespace Ice
+
+#endif // SUBZERO_SRC_ICETARGETLOWERING_H
diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
new file mode 100644
index 0000000..32246c4
--- /dev/null
+++ b/src/IceTargetLoweringX8632.cpp
@@ -0,0 +1,1881 @@
+//===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
+//
+// The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the TargetLoweringX8632 class, which
+// consists almost entirely of the lowering sequence for each
+// high-level instruction. It also implements
+// TargetX8632Fast::postLower() which does the simplest possible
+// register allocation for the "fast" target.
+//
+//===----------------------------------------------------------------------===//
+
+#include "IceDefs.h"
+#include "IceCfg.h"
+#include "IceCfgNode.h"
+#include "IceInstX8632.h"
+#include "IceOperand.h"
+#include "IceTargetLoweringX8632.def"
+#include "IceTargetLoweringX8632.h"
+
+namespace Ice {
+
+namespace {
+
+// The following table summarizes the logic for lowering the fcmp instruction.
+// There is one table entry for each of the 16 conditions. A comment in
+// lowerFcmp() describes the lowering template. In the most general case, there
+// is a compare followed by two conditional branches, because some fcmp
+// conditions don't map to a single x86 conditional branch. However, in many
+// cases it is possible to swap the operands in the comparison and have a single
+// conditional branch. Since it's quite tedious to validate the table by hand,
+// good execution tests are helpful.
+
+const struct TableFcmp_ {
+ uint32_t Default;
+ bool SwapOperands;
+ InstX8632Br::BrCond C1, C2;
+} TableFcmp[] = {
+#define X(val, dflt, swap, C1, C2) \
+ { dflt, swap, InstX8632Br::C1, InstX8632Br::C2 } \
+ ,
+ FCMPX8632_TABLE
+#undef X
+ };
+const size_t TableFcmpSize = llvm::array_lengthof(TableFcmp);
+
+// The following table summarizes the logic for lowering the icmp instruction
+// for i32 and narrower types. Each icmp condition has a clear mapping to an
+// x86 conditional branch instruction.
+
+const struct TableIcmp32_ {
+ InstX8632Br::BrCond Mapping;
+} TableIcmp32[] = {
+#define X(val, C_32, C1_64, C2_64, C3_64) \
+ { InstX8632Br::C_32 } \
+ ,
+ ICMPX8632_TABLE
+#undef X
+ };
+const size_t TableIcmp32Size = llvm::array_lengthof(TableIcmp32);
+
+// The following table summarizes the logic for lowering the icmp instruction
+// for the i64 type. For Eq and Ne, two separate 32-bit comparisons and
+// conditional branches are needed. For the other conditions, three separate
+// conditional branches are needed.
+const struct TableIcmp64_ {
+ InstX8632Br::BrCond C1, C2, C3;
+} TableIcmp64[] = {
+#define X(val, C_32, C1_64, C2_64, C3_64) \
+ { InstX8632Br::C1_64, InstX8632Br::C2_64, InstX8632Br::C3_64 } \
+ ,
+ ICMPX8632_TABLE
+#undef X
+ };
+const size_t TableIcmp64Size = llvm::array_lengthof(TableIcmp64);
+
+InstX8632Br::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
+ size_t Index = static_cast<size_t>(Cond);
+ assert(Index < TableIcmp32Size);
+ return TableIcmp32[Index].Mapping;
+}
+
+// In some cases, there are x-macros tables for both high-level and
+// low-level instructions/operands that use the same enum key value.
+// The tables are kept separate to maintain a proper separation
+// between abstraction layers. There is a risk that the tables
+// could get out of sync if enum values are reordered or if entries
+// are added or deleted. This dummy function uses static_assert to
+// ensure everything is kept in sync.
+void xMacroIntegrityCheck() {
+ // Validate the enum values in FCMPX8632_TABLE.
+ {
+ // Define a temporary set of enum values based on low-level
+ // table entries.
+ enum _tmp_enum {
+#define X(val, dflt, swap, C1, C2) _tmp_##val,
+ FCMPX8632_TABLE
+#undef X
+ };
+// Define a set of constants based on high-level table entries.
+#define X(tag, str) static const int _table1_##tag = InstFcmp::tag;
+ ICEINSTFCMP_TABLE;
+#undef X
+// Define a set of constants based on low-level table entries,
+// and ensure the table entry keys are consistent.
+#define X(val, dflt, swap, C1, C2) \
+ static const int _table2_##val = _tmp_##val; \
+ STATIC_ASSERT(_table1_##val == _table2_##val);
+ FCMPX8632_TABLE;
+#undef X
+// Repeat the static asserts with respect to the high-level
+// table entries in case the high-level table has extra entries.
+#define X(tag, str) STATIC_ASSERT(_table1_##tag == _table2_##tag);
+ ICEINSTFCMP_TABLE;
+#undef X
+ }
+
+ // Validate the enum values in ICMPX8632_TABLE.
+ {
+ // Define a temporary set of enum values based on low-level
+ // table entries.
+ enum _tmp_enum {
+#define X(val, C_32, C1_64, C2_64, C3_64) _tmp_##val,
+ ICMPX8632_TABLE
+#undef X
+ };
+// Define a set of constants based on high-level table entries.
+#define X(tag, str) static const int _table1_##tag = InstIcmp::tag;
+ ICEINSTICMP_TABLE;
+#undef X
+// Define a set of constants based on low-level table entries,
+// and ensure the table entry keys are consistent.
+#define X(val, C_32, C1_64, C2_64, C3_64) \
+ static const int _table2_##val = _tmp_##val; \
+ STATIC_ASSERT(_table1_##val == _table2_##val);
+ ICMPX8632_TABLE;
+#undef X
+// Repeat the static asserts with respect to the high-level
+// table entries in case the high-level table has extra entries.
+#define X(tag, str) STATIC_ASSERT(_table1_##tag == _table2_##tag);
+ ICEINSTICMP_TABLE;
+#undef X
+ }
+
+ // Validate the enum values in ICETYPEX8632_TABLE.
+ {
+ // Define a temporary set of enum values based on low-level
+ // table entries.
+ enum _tmp_enum {
+#define X(tag, cvt, sdss, width) _tmp_##tag,
+ ICETYPEX8632_TABLE
+#undef X
+ };
+// Define a set of constants based on high-level table entries.
+#define X(tag, size, align, str) static const int _table1_##tag = tag;
+ ICETYPE_TABLE;
+#undef X
+// Define a set of constants based on low-level table entries,
+// and ensure the table entry keys are consistent.
+#define X(tag, cvt, sdss, width) \
+ static const int _table2_##tag = _tmp_##tag; \
+ STATIC_ASSERT(_table1_##tag == _table2_##tag);
+ ICETYPEX8632_TABLE;
+#undef X
+// Repeat the static asserts with respect to the high-level
+// table entries in case the high-level table has extra entries.
+#define X(tag, size, align, str) STATIC_ASSERT(_table1_##tag == _table2_##tag);
+ ICETYPE_TABLE;
+#undef X
+ }
+}
+
+} // end of anonymous namespace
+
+TargetX8632::TargetX8632(Cfg *Func)
+ : TargetLowering(Func), IsEbpBasedFrame(false), FrameSizeLocals(0),
+ LocalsSizeBytes(0), NextLabelNumber(0), ComputedLiveRanges(false),
+ PhysicalRegisters(VarList(Reg_NUM)) {
+ // TODO: Don't initialize IntegerRegisters and friends every time.
+ // Instead, initialize in some sort of static initializer for the
+ // class.
+ llvm::SmallBitVector IntegerRegisters(Reg_NUM);
+ llvm::SmallBitVector IntegerRegistersI8(Reg_NUM);
+ llvm::SmallBitVector FloatRegisters(Reg_NUM);
+ llvm::SmallBitVector InvalidRegisters(Reg_NUM);
+ ScratchRegs.resize(Reg_NUM);
+#define X(val, init, name, name16, name8, scratch, preserved, stackptr, \
+ frameptr, isI8, isInt, isFP) \
+ IntegerRegisters[val] = isInt; \
+ IntegerRegistersI8[val] = isI8; \
+ FloatRegisters[val] = isFP; \
+ ScratchRegs[val] = scratch;
+ REGX8632_TABLE;
+#undef X
+ TypeToRegisterSet[IceType_void] = InvalidRegisters;
+ TypeToRegisterSet[IceType_i1] = IntegerRegistersI8;
+ TypeToRegisterSet[IceType_i8] = IntegerRegistersI8;
+ TypeToRegisterSet[IceType_i16] = IntegerRegisters;
+ TypeToRegisterSet[IceType_i32] = IntegerRegisters;
+ TypeToRegisterSet[IceType_i64] = IntegerRegisters;
+ TypeToRegisterSet[IceType_f32] = FloatRegisters;
+ TypeToRegisterSet[IceType_f64] = FloatRegisters;
+}
+
+void TargetX8632::translateOm1() {
+ GlobalContext *Context = Func->getContext();
+ Ostream &Str = Context->getStrDump();
+ Timer T_placePhiLoads;
+ Func->placePhiLoads();
+ if (Func->hasError())
+ return;
+ T_placePhiLoads.printElapsedUs(Context, "placePhiLoads()");
+ Timer T_placePhiStores;
+ Func->placePhiStores();
+ if (Func->hasError())
+ return;
+ T_placePhiStores.printElapsedUs(Context, "placePhiStores()");
+ Timer T_deletePhis;
+ Func->deletePhis();
+ if (Func->hasError())
+ return;
+ T_deletePhis.printElapsedUs(Context, "deletePhis()");
+ if (Context->isVerbose()) {
+ Str << "================ After Phi lowering ================\n";
+ Func->dump();
+ }
+
+ Timer T_genCode;
+ Func->genCode();
+ if (Func->hasError())
+ return;
+ T_genCode.printElapsedUs(Context, "genCode()");
+ if (Context->isVerbose()) {
+ Str << "================ After initial x8632 codegen ================\n";
+ Func->dump();
+ }
+
+ Timer T_genFrame;
+ Func->genFrame();
+ if (Func->hasError())
+ return;
+ T_genFrame.printElapsedUs(Context, "genFrame()");
+ if (Context->isVerbose()) {
+ Str << "================ After stack frame mapping ================\n";
+ Func->dump();
+ }
+}
+
+IceString TargetX8632::RegNames[] = {
+#define X(val, init, name, name16, name8, scratch, preserved, stackptr, \
+ frameptr, isI8, isInt, isFP) \
+ name,
+ REGX8632_TABLE
+#undef X
+};
+
+Variable *TargetX8632::getPhysicalRegister(SizeT RegNum) {
+ assert(RegNum < PhysicalRegisters.size());
+ Variable *Reg = PhysicalRegisters[RegNum];
+ if (Reg == NULL) {
+ CfgNode *Node = NULL; // NULL means multi-block lifetime
+ Reg = Func->makeVariable(IceType_i32, Node);
+ Reg->setRegNum(RegNum);
+ PhysicalRegisters[RegNum] = Reg;
+ }
+ return Reg;
+}
+
+IceString TargetX8632::getRegName(SizeT RegNum, Type Ty) const {
+ assert(RegNum < Reg_NUM);
+ static IceString RegNames8[] = {
+#define X(val, init, name, name16, name8, scratch, preserved, stackptr, \
+ frameptr, isI8, isInt, isFP) \
+ "" name8,
+ REGX8632_TABLE
+#undef X
+ };
+ static IceString RegNames16[] = {
+#define X(val, init, name, name16, name8, scratch, preserved, stackptr, \
+ frameptr, isI8, isInt, isFP) \
+ "" name16,
+ REGX8632_TABLE
+#undef X
+ };
+ switch (Ty) {
+ case IceType_i1:
+ case IceType_i8:
+ return RegNames8[RegNum];
+ case IceType_i16:
+ return RegNames16[RegNum];
+ default:
+ return RegNames[RegNum];
+ }
+}
+
+void TargetX8632::emitVariable(const Variable *Var, const Cfg *Func) const {
+ Ostream &Str = Ctx->getStrEmit();
+ assert(Var->getLocalUseNode() == NULL ||
+ Var->getLocalUseNode() == Func->getCurrentNode());
+ if (Var->hasReg()) {
+ Str << getRegName(Var->getRegNum(), Var->getType());
+ return;
+ }
+ Str << InstX8632::getWidthString(Var->getType());
+ Str << " [" << getRegName(getFrameOrStackReg(), IceType_i32);
+ int32_t Offset = Var->getStackOffset() + getStackAdjustment();
+ if (Offset) {
+ if (Offset > 0)
+ Str << "+";
+ Str << Offset;
+ }
+ Str << "]";
+}
+
+// Helper function for addProlog(). Sets the frame offset for Arg,
+// updates InArgsSizeBytes according to Arg's width, and generates an
+// instruction to copy Arg into its assigned register if applicable.
+// For an I64 arg that has been split into Lo and Hi components, it
+// calls itself recursively on the components, taking care to handle
+// Lo first because of the little-endian architecture.
+void TargetX8632::setArgOffsetAndCopy(Variable *Arg, Variable *FramePtr,
+ int32_t BasicFrameOffset,
+ int32_t &InArgsSizeBytes) {
+ Variable *Lo = Arg->getLo();
+ Variable *Hi = Arg->getHi();
+ Type Ty = Arg->getType();
+ if (Lo && Hi && Ty == IceType_i64) {
+ assert(Lo->getType() != IceType_i64); // don't want infinite recursion
+ assert(Hi->getType() != IceType_i64); // don't want infinite recursion
+ setArgOffsetAndCopy(Lo, FramePtr, BasicFrameOffset, InArgsSizeBytes);
+ setArgOffsetAndCopy(Hi, FramePtr, BasicFrameOffset, InArgsSizeBytes);
+ return;
+ }
+ Arg->setStackOffset(BasicFrameOffset + InArgsSizeBytes);
+ if (Arg->hasReg()) {
+ assert(Ty != IceType_i64);
+ OperandX8632Mem *Mem = OperandX8632Mem::create(
+ Func, Ty, FramePtr,
+ Ctx->getConstantInt(IceType_i32, Arg->getStackOffset()));
+ _mov(Arg, Mem);
+ }
+ InArgsSizeBytes += typeWidthInBytesOnStack(Ty);
+}
+
+void TargetX8632::addProlog(CfgNode *Node) {
+ // If SimpleCoalescing is false, each variable without a register
+ // gets its own unique stack slot, which leads to large stack
+ // frames. If SimpleCoalescing is true, then each "global" variable
+ // without a register gets its own slot, but "local" variable slots
+ // are reused across basic blocks. E.g., if A and B are local to
+ // block 1 and C is local to block 2, then C may share a slot with A
+ // or B.
+ const bool SimpleCoalescing = true;
+ int32_t InArgsSizeBytes = 0;
+ int32_t RetIpSizeBytes = 4;
+ int32_t PreservedRegsSizeBytes = 0;
+ LocalsSizeBytes = 0;
+ Context.init(Node);
+ Context.setInsertPoint(Context.getCur());
+
+ // Determine stack frame offsets for each Variable without a
+ // register assignment. This can be done as one variable per stack
+ // slot. Or, do coalescing by running the register allocator again
+ // with an infinite set of registers (as a side effect, this gives
+ // variables a second chance at physical register assignment).
+ //
+ // A middle ground approach is to leverage sparsity and allocate one
+ // block of space on the frame for globals (variables with
+ // multi-block lifetime), and one block to share for locals
+ // (single-block lifetime).
+
+ llvm::SmallBitVector CalleeSaves =
+ getRegisterSet(RegSet_CalleeSave, RegSet_None);
+
+ int32_t GlobalsSize = 0;
+ std::vector<int> LocalsSize(Func->getNumNodes());
+
+ // Prepass. Compute RegsUsed, PreservedRegsSizeBytes, and
+ // LocalsSizeBytes.
+ RegsUsed = llvm::SmallBitVector(CalleeSaves.size());
+ const VarList &Variables = Func->getVariables();
+ const VarList &Args = Func->getArgs();
+ for (VarList::const_iterator I = Variables.begin(), E = Variables.end();
+ I != E; ++I) {
+ Variable *Var = *I;
+ if (Var->hasReg()) {
+ RegsUsed[Var->getRegNum()] = true;
+ continue;
+ }
+ // An argument passed on the stack already has a stack slot.
+ if (Var->getIsArg())
+ continue;
+ // A spill slot linked to a variable with a stack slot should reuse
+ // that stack slot.
+ if (Var->getWeight() == RegWeight::Zero && Var->getRegisterOverlap()) {
+ if (Variable *Linked = Var->getPreferredRegister()) {
+ if (!Linked->hasReg())
+ continue;
+ }
+ }
+ int32_t Increment = typeWidthInBytesOnStack(Var->getType());
+ if (SimpleCoalescing) {
+ if (Var->isMultiblockLife()) {
+ GlobalsSize += Increment;
+ } else {
+ SizeT NodeIndex = Var->getLocalUseNode()->getIndex();
+ LocalsSize[NodeIndex] += Increment;
+ if (LocalsSize[NodeIndex] > LocalsSizeBytes)
+ LocalsSizeBytes = LocalsSize[NodeIndex];
+ }
+ } else {
+ LocalsSizeBytes += Increment;
+ }
+ }
+ LocalsSizeBytes += GlobalsSize;
+
+ // Add push instructions for preserved registers.
+ for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
+ if (CalleeSaves[i] && RegsUsed[i]) {
+ PreservedRegsSizeBytes += 4;
+ const bool SuppressStackAdjustment = true;
+ _push(getPhysicalRegister(i), SuppressStackAdjustment);
+ }
+ }
+
+ // Generate "push ebp; mov ebp, esp"
+ if (IsEbpBasedFrame) {
+ assert((RegsUsed & getRegisterSet(RegSet_FramePointer, RegSet_None))
+ .count() == 0);
+ PreservedRegsSizeBytes += 4;
+ Variable *ebp = getPhysicalRegister(Reg_ebp);
+ Variable *esp = getPhysicalRegister(Reg_esp);
+ const bool SuppressStackAdjustment = true;
+ _push(ebp, SuppressStackAdjustment);
+ _mov(ebp, esp);
+ }
+
+ // Generate "sub esp, LocalsSizeBytes"
+ if (LocalsSizeBytes)
+ _sub(getPhysicalRegister(Reg_esp),
+ Ctx->getConstantInt(IceType_i32, LocalsSizeBytes));
+
+ resetStackAdjustment();
+
+ // Fill in stack offsets for args, and copy args into registers for
+ // those that were register-allocated. Args are pushed right to
+ // left, so Arg[0] is closest to the stack/frame pointer.
+ //
+ // TODO: Make this right for different width args, calling
+ // conventions, etc. For one thing, args passed in registers will
+ // need to be copied/shuffled to their home registers (the
+ // RegManager code may have some permutation logic to leverage),
+ // and if they have no home register, home space will need to be
+ // allocated on the stack to copy into.
+ Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg());
+ int32_t BasicFrameOffset = PreservedRegsSizeBytes + RetIpSizeBytes;
+ if (!IsEbpBasedFrame)
+ BasicFrameOffset += LocalsSizeBytes;
+ for (SizeT i = 0; i < Args.size(); ++i) {
+ Variable *Arg = Args[i];
+ setArgOffsetAndCopy(Arg, FramePtr, BasicFrameOffset, InArgsSizeBytes);
+ }
+
+ // Fill in stack offsets for locals.
+ int32_t TotalGlobalsSize = GlobalsSize;
+ GlobalsSize = 0;
+ LocalsSize.assign(LocalsSize.size(), 0);
+ int32_t NextStackOffset = 0;
+ for (VarList::const_iterator I = Variables.begin(), E = Variables.end();
+ I != E; ++I) {
+ Variable *Var = *I;
+ if (Var->hasReg()) {
+ RegsUsed[Var->getRegNum()] = true;
+ continue;
+ }
+ if (Var->getIsArg())
+ continue;
+ if (Var->getWeight() == RegWeight::Zero && Var->getRegisterOverlap()) {
+ if (Variable *Linked = Var->getPreferredRegister()) {
+ if (!Linked->hasReg()) {
+ // TODO: Make sure Linked has already been assigned a stack
+ // slot.
+ Var->setStackOffset(Linked->getStackOffset());
+ continue;
+ }
+ }
+ }
+ int32_t Increment = typeWidthInBytesOnStack(Var->getType());
+ if (SimpleCoalescing) {
+ if (Var->isMultiblockLife()) {
+ GlobalsSize += Increment;
+ NextStackOffset = GlobalsSize;
+ } else {
+ SizeT NodeIndex = Var->getLocalUseNode()->getIndex();
+ LocalsSize[NodeIndex] += Increment;
+ NextStackOffset = TotalGlobalsSize + LocalsSize[NodeIndex];
+ }
+ } else {
+ NextStackOffset += Increment;
+ }
+ if (IsEbpBasedFrame)
+ Var->setStackOffset(-NextStackOffset);
+ else
+ Var->setStackOffset(LocalsSizeBytes - NextStackOffset);
+ }
+ this->FrameSizeLocals = NextStackOffset;
+ this->HasComputedFrame = true;
+
+ if (Func->getContext()->isVerbose(IceV_Frame)) {
+ Func->getContext()->getStrDump() << "LocalsSizeBytes=" << LocalsSizeBytes
+ << "\n"
+ << "InArgsSizeBytes=" << InArgsSizeBytes
+ << "\n"
+ << "PreservedRegsSizeBytes="
+ << PreservedRegsSizeBytes << "\n";
+ }
+}
+
+void TargetX8632::addEpilog(CfgNode *Node) {
+ InstList &Insts = Node->getInsts();
+ InstList::reverse_iterator RI, E;
+ for (RI = Insts.rbegin(), E = Insts.rend(); RI != E; ++RI) {
+ if (llvm::isa<InstX8632Ret>(*RI))
+ break;
+ }
+ if (RI == E)
+ return;
+
+ // Convert the reverse_iterator position into its corresponding
+ // (forward) iterator position.
+ InstList::iterator InsertPoint = RI.base();
+ --InsertPoint;
+ Context.init(Node);
+ Context.setInsertPoint(InsertPoint);
+
+ Variable *esp = getPhysicalRegister(Reg_esp);
+ if (IsEbpBasedFrame) {
+ Variable *ebp = getPhysicalRegister(Reg_ebp);
+ _mov(esp, ebp);
+ _pop(ebp);
+ } else {
+ // add esp, LocalsSizeBytes
+ if (LocalsSizeBytes)
+ _add(esp, Ctx->getConstantInt(IceType_i32, LocalsSizeBytes));
+ }
+
+ // Add pop instructions for preserved registers.
+ llvm::SmallBitVector CalleeSaves =
+ getRegisterSet(RegSet_CalleeSave, RegSet_None);
+ for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
+ SizeT j = CalleeSaves.size() - i - 1;
+ if (j == Reg_ebp && IsEbpBasedFrame)
+ continue;
+ if (CalleeSaves[j] && RegsUsed[j]) {
+ _pop(getPhysicalRegister(j));
+ }
+ }
+}
+
+void TargetX8632::split64(Variable *Var) {
+ switch (Var->getType()) {
+ default:
+ return;
+ case IceType_i64:
+ // TODO: Only consider F64 if we need to push each half when
+ // passing as an argument to a function call. Note that each half
+ // is still typed as I32.
+ case IceType_f64:
+ break;
+ }
+ Variable *Lo = Var->getLo();
+ Variable *Hi = Var->getHi();
+ if (Lo) {
+ assert(Hi);
+ return;
+ }
+ assert(Hi == NULL);
+ Lo = Func->makeVariable(IceType_i32, Context.getNode(),
+ Var->getName() + "__lo");
+ Hi = Func->makeVariable(IceType_i32, Context.getNode(),
+ Var->getName() + "__hi");
+ Var->setLoHi(Lo, Hi);
+ if (Var->getIsArg()) {
+ Lo->setIsArg(Func);
+ Hi->setIsArg(Func);
+ }
+}
+
+Operand *TargetX8632::loOperand(Operand *Operand) {
+ assert(Operand->getType() == IceType_i64);
+ if (Operand->getType() != IceType_i64)
+ return Operand;
+ if (Variable *Var = llvm::dyn_cast<Variable>(Operand)) {
+ split64(Var);
+ return Var->getLo();
+ }
+ if (ConstantInteger *Const = llvm::dyn_cast<ConstantInteger>(Operand)) {
+ uint64_t Mask = (1ull << 32) - 1;
+ return Ctx->getConstantInt(IceType_i32, Const->getValue() & Mask);
+ }
+ if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Operand)) {
+ return OperandX8632Mem::create(Func, IceType_i32, Mem->getBase(),
+ Mem->getOffset(), Mem->getIndex(),
+ Mem->getShift());
+ }
+ llvm_unreachable("Unsupported operand type");
+ return NULL;
+}
+
+Operand *TargetX8632::hiOperand(Operand *Operand) {
+ assert(Operand->getType() == IceType_i64);
+ if (Operand->getType() != IceType_i64)
+ return Operand;
+ if (Variable *Var = llvm::dyn_cast<Variable>(Operand)) {
+ split64(Var);
+ return Var->getHi();
+ }
+ if (ConstantInteger *Const = llvm::dyn_cast<ConstantInteger>(Operand)) {
+ return Ctx->getConstantInt(IceType_i32, Const->getValue() >> 32);
+ }
+ if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Operand)) {
+ Constant *Offset = Mem->getOffset();
+ if (Offset == NULL)
+ Offset = Ctx->getConstantInt(IceType_i32, 4);
+ else if (ConstantInteger *IntOffset =
+ llvm::dyn_cast<ConstantInteger>(Offset)) {
+ Offset = Ctx->getConstantInt(IceType_i32, 4 + IntOffset->getValue());
+ } else if (ConstantRelocatable *SymOffset =
+ llvm::dyn_cast<ConstantRelocatable>(Offset)) {
+ Offset = Ctx->getConstantSym(IceType_i32, 4 + SymOffset->getOffset(),
+ SymOffset->getName());
+ }
+ return OperandX8632Mem::create(Func, IceType_i32, Mem->getBase(), Offset,
+ Mem->getIndex(), Mem->getShift());
+ }
+ llvm_unreachable("Unsupported operand type");
+ return NULL;
+}
+
+llvm::SmallBitVector TargetX8632::getRegisterSet(RegSetMask Include,
+ RegSetMask Exclude) const {
+ llvm::SmallBitVector Registers(Reg_NUM);
+
+#define X(val, init, name, name16, name8, scratch, preserved, stackptr, \
+ frameptr, isI8, isInt, isFP) \
+ if (scratch && (Include & RegSet_CallerSave)) \
+ Registers[val] = true; \
+ if (preserved && (Include & RegSet_CalleeSave)) \
+ Registers[val] = true; \
+ if (stackptr && (Include & RegSet_StackPointer)) \
+ Registers[val] = true; \
+ if (frameptr && (Include & RegSet_FramePointer)) \
+ Registers[val] = true; \
+ if (scratch && (Exclude & RegSet_CallerSave)) \
+ Registers[val] = false; \
+ if (preserved && (Exclude & RegSet_CalleeSave)) \
+ Registers[val] = false; \
+ if (stackptr && (Exclude & RegSet_StackPointer)) \
+ Registers[val] = false; \
+ if (frameptr && (Exclude & RegSet_FramePointer)) \
+ Registers[val] = false;
+
+ REGX8632_TABLE
+
+#undef X
+
+ return Registers;
+}
+
+void TargetX8632::lowerAlloca(const InstAlloca *Inst) {
+ IsEbpBasedFrame = true;
+ // TODO(sehr,stichnot): align allocated memory, keep stack aligned, minimize
+ // the number of adjustments of esp, etc.
+ Variable *esp = getPhysicalRegister(Reg_esp);
+ Operand *TotalSize = legalize(Inst->getSizeInBytes());
+ Variable *Dest = Inst->getDest();
+ _sub(esp, TotalSize);
+ _mov(Dest, esp);
+}
+
+void TargetX8632::lowerArithmetic(const InstArithmetic *Inst) {
+ Variable *Dest = Inst->getDest();
+ Operand *Src0 = legalize(Inst->getSrc(0));
+ Operand *Src1 = legalize(Inst->getSrc(1));
+ if (Dest->getType() == IceType_i64) {
+ Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
+ Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+ Operand *Src0Lo = loOperand(Src0);
+ Operand *Src0Hi = hiOperand(Src0);
+ Operand *Src1Lo = loOperand(Src1);
+ Operand *Src1Hi = hiOperand(Src1);
+ Variable *T_Lo = NULL, *T_Hi = NULL;
+ switch (Inst->getOp()) {
+ case InstArithmetic::Add:
+ _mov(T_Lo, Src0Lo);
+ _add(T_Lo, Src1Lo);
+ _mov(DestLo, T_Lo);
+ _mov(T_Hi, Src0Hi);
+ _adc(T_Hi, Src1Hi);
+ _mov(DestHi, T_Hi);
+ break;
+ case InstArithmetic::And:
+ _mov(T_Lo, Src0Lo);
+ _and(T_Lo, Src1Lo);
+ _mov(DestLo, T_Lo);
+ _mov(T_Hi, Src0Hi);
+ _and(T_Hi, Src1Hi);
+ _mov(DestHi, T_Hi);
+ break;
+ case InstArithmetic::Or:
+ _mov(T_Lo, Src0Lo);
+ _or(T_Lo, Src1Lo);
+ _mov(DestLo, T_Lo);
+ _mov(T_Hi, Src0Hi);
+ _or(T_Hi, Src1Hi);
+ _mov(DestHi, T_Hi);
+ break;
+ case InstArithmetic::Xor:
+ _mov(T_Lo, Src0Lo);
+ _xor(T_Lo, Src1Lo);
+ _mov(DestLo, T_Lo);
+ _mov(T_Hi, Src0Hi);
+ _xor(T_Hi, Src1Hi);
+ _mov(DestHi, T_Hi);
+ break;
+ case InstArithmetic::Sub:
+ _mov(T_Lo, Src0Lo);
+ _sub(T_Lo, Src1Lo);
+ _mov(DestLo, T_Lo);
+ _mov(T_Hi, Src0Hi);
+ _sbb(T_Hi, Src1Hi);
+ _mov(DestHi, T_Hi);
+ break;
+ case InstArithmetic::Mul: {
+ Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
+ Variable *T_4Lo = makeReg(IceType_i32, Reg_eax);
+ Variable *T_4Hi = makeReg(IceType_i32, Reg_edx);
+ // gcc does the following:
+ // a=b*c ==>
+ // t1 = b.hi; t1 *=(imul) c.lo
+ // t2 = c.hi; t2 *=(imul) b.lo
+ // t3:eax = b.lo
+ // t4.hi:edx,t4.lo:eax = t3:eax *(mul) c.lo
+ // a.lo = t4.lo
+ // t4.hi += t1
+ // t4.hi += t2
+ // a.hi = t4.hi
+ _mov(T_1, Src0Hi);
+ _imul(T_1, Src1Lo);
+ _mov(T_2, Src1Hi);
+ _imul(T_2, Src0Lo);
+ _mov(T_3, Src0Lo, Reg_eax);
+ _mul(T_4Lo, T_3, Src1Lo);
+ // The mul instruction produces two dest variables, edx:eax. We
+ // create a fake definition of edx to account for this.
+ Context.insert(InstFakeDef::create(Func, T_4Hi, T_4Lo));
+ _mov(DestLo, T_4Lo);
+ _add(T_4Hi, T_1);
+ _add(T_4Hi, T_2);
+ _mov(DestHi, T_4Hi);
+ } break;
+ case InstArithmetic::Shl: {
+ // TODO: Refactor the similarities between Shl, Lshr, and Ashr.
+ // gcc does the following:
+ // a=b<<c ==>
+ // t1:ecx = c.lo & 0xff
+ // t2 = b.lo
+ // t3 = b.hi
+ // t3 = shld t3, t2, t1
+ // t2 = shl t2, t1
+ // test t1, 0x20
+ // je L1
+ // use(t3)
+ // t3 = t2
+ // t2 = 0
+ // L1:
+ // a.lo = t2
+ // a.hi = t3
+ Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
+ Constant *BitTest = Ctx->getConstantInt(IceType_i32, 0x20);
+ Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+ InstX8632Label *Label = InstX8632Label::create(Func, this);
+ _mov(T_1, Src1Lo, Reg_ecx);
+ _mov(T_2, Src0Lo);
+ _mov(T_3, Src0Hi);
+ _shld(T_3, T_2, T_1);
+ _shl(T_2, T_1);
+ _test(T_1, BitTest);
+ _br(InstX8632Br::Br_e, Label);
+ // Because of the intra-block control flow, we need to fake a use
+ // of T_3 to prevent its earlier definition from being dead-code
+ // eliminated in the presence of its later definition.
+ Context.insert(InstFakeUse::create(Func, T_3));
+ _mov(T_3, T_2);
+ _mov(T_2, Zero);
+ Context.insert(Label);
+ _mov(DestLo, T_2);
+ _mov(DestHi, T_3);
+ } break;
+ case InstArithmetic::Lshr: {
+ // a=b>>c (unsigned) ==>
+ // t1:ecx = c.lo & 0xff
+ // t2 = b.lo
+ // t3 = b.hi
+ // t2 = shrd t2, t3, t1
+ // t3 = shr t3, t1
+ // test t1, 0x20
+ // je L1
+ // use(t2)
+ // t2 = t3
+ // t3 = 0
+ // L1:
+ // a.lo = t2
+ // a.hi = t3
+ Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
+ Constant *BitTest = Ctx->getConstantInt(IceType_i32, 0x20);
+ Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+ InstX8632Label *Label = InstX8632Label::create(Func, this);
+ _mov(T_1, Src1Lo, Reg_ecx);
+ _mov(T_2, Src0Lo);
+ _mov(T_3, Src0Hi);
+ _shrd(T_2, T_3, T_1);
+ _shr(T_3, T_1);
+ _test(T_1, BitTest);
+ _br(InstX8632Br::Br_e, Label);
+ // Because of the intra-block control flow, we need to fake a use
+ // of T_3 to prevent its earlier definition from being dead-code
+ // eliminated in the presence of its later definition.
+ Context.insert(InstFakeUse::create(Func, T_2));
+ _mov(T_2, T_3);
+ _mov(T_3, Zero);
+ Context.insert(Label);
+ _mov(DestLo, T_2);
+ _mov(DestHi, T_3);
+ } break;
+ case InstArithmetic::Ashr: {
+ // a=b>>c (signed) ==>
+ // t1:ecx = c.lo & 0xff
+ // t2 = b.lo
+ // t3 = b.hi
+ // t2 = shrd t2, t3, t1
+ // t3 = sar t3, t1
+ // test t1, 0x20
+ // je L1
+ // use(t2)
+ // t2 = t3
+ // t3 = sar t3, 0x1f
+ // L1:
+ // a.lo = t2
+ // a.hi = t3
+ Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
+ Constant *BitTest = Ctx->getConstantInt(IceType_i32, 0x20);
+ Constant *SignExtend = Ctx->getConstantInt(IceType_i32, 0x1f);
+ InstX8632Label *Label = InstX8632Label::create(Func, this);
+ _mov(T_1, Src1Lo, Reg_ecx);
+ _mov(T_2, Src0Lo);
+ _mov(T_3, Src0Hi);
+ _shrd(T_2, T_3, T_1);
+ _sar(T_3, T_1);
+ _test(T_1, BitTest);
+ _br(InstX8632Br::Br_e, Label);
+ // Because of the intra-block control flow, we need to fake a use
+ // of T_3 to prevent its earlier definition from being dead-code
+ // eliminated in the presence of its later definition.
+ Context.insert(InstFakeUse::create(Func, T_2));
+ _mov(T_2, T_3);
+ _sar(T_3, SignExtend);
+ Context.insert(Label);
+ _mov(DestLo, T_2);
+ _mov(DestHi, T_3);
+ } break;
+ case InstArithmetic::Udiv: {
+ const SizeT MaxSrcs = 2;
+ InstCall *Call = makeHelperCall("__udivdi3", Dest, MaxSrcs);
+ Call->addArg(Inst->getSrc(0));
+ Call->addArg(Inst->getSrc(1));
+ lowerCall(Call);
+ } break;
+ case InstArithmetic::Sdiv: {
+ const SizeT MaxSrcs = 2;
+ InstCall *Call = makeHelperCall("__divdi3", Dest, MaxSrcs);
+ Call->addArg(Inst->getSrc(0));
+ Call->addArg(Inst->getSrc(1));
+ lowerCall(Call);
+ } break;
+ case InstArithmetic::Urem: {
+ const SizeT MaxSrcs = 2;
+ InstCall *Call = makeHelperCall("__umoddi3", Dest, MaxSrcs);
+ Call->addArg(Inst->getSrc(0));
+ Call->addArg(Inst->getSrc(1));
+ lowerCall(Call);
+ } break;
+ case InstArithmetic::Srem: {
+ const SizeT MaxSrcs = 2;
+ InstCall *Call = makeHelperCall("__moddi3", Dest, MaxSrcs);
+ Call->addArg(Inst->getSrc(0));
+ Call->addArg(Inst->getSrc(1));
+ lowerCall(Call);
+ } break;
+ case InstArithmetic::Fadd:
+ case InstArithmetic::Fsub:
+ case InstArithmetic::Fmul:
+ case InstArithmetic::Fdiv:
+ case InstArithmetic::Frem:
+ llvm_unreachable("FP instruction with i64 type");
+ break;
+ }
+ } else { // Dest->getType() != IceType_i64
+ Variable *T_edx = NULL;
+ Variable *T = NULL;
+ switch (Inst->getOp()) {
+ case InstArithmetic::Add:
+ _mov(T, Src0);
+ _add(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::And:
+ _mov(T, Src0);
+ _and(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Or:
+ _mov(T, Src0);
+ _or(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Xor:
+ _mov(T, Src0);
+ _xor(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Sub:
+ _mov(T, Src0);
+ _sub(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Mul:
+ // TODO: Optimize for llvm::isa<Constant>(Src1)
+ // TODO: Strength-reduce multiplications by a constant,
+ // particularly -1 and powers of 2. Advanced: use lea to
+ // multiply by 3, 5, 9.
+ //
+ // The 8-bit version of imul only allows the form "imul r/m8"
+ // where T must be in eax.
+ if (Dest->getType() == IceType_i8)
+ _mov(T, Src0, Reg_eax);
+ else
+ _mov(T, Src0);
+ _imul(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Shl:
+ _mov(T, Src0);
+ if (!llvm::isa<Constant>(Src1))
+ Src1 = legalizeToVar(Src1, false, Reg_ecx);
+ _shl(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Lshr:
+ _mov(T, Src0);
+ if (!llvm::isa<Constant>(Src1))
+ Src1 = legalizeToVar(Src1, false, Reg_ecx);
+ _shr(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Ashr:
+ _mov(T, Src0);
+ if (!llvm::isa<Constant>(Src1))
+ Src1 = legalizeToVar(Src1, false, Reg_ecx);
+ _sar(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Udiv:
+ if (Dest->getType() == IceType_i8) {
+ Variable *T_ah = NULL;
+ Constant *Zero = Ctx->getConstantInt(IceType_i8, 0);
+ _mov(T, Src0, Reg_eax);
+ _mov(T_ah, Zero, Reg_ah);
+ _div(T, Src1, T_ah);
+ _mov(Dest, T);
+ } else {
+ Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+ _mov(T, Src0, Reg_eax);
+ _mov(T_edx, Zero, Reg_edx);
+ _div(T, Src1, T_edx);
+ _mov(Dest, T);
+ }
+ break;
+ case InstArithmetic::Sdiv:
+ T_edx = makeReg(IceType_i32, Reg_edx);
+ _mov(T, Src0, Reg_eax);
+ _cdq(T_edx, T);
+ _idiv(T, Src1, T_edx);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Urem:
+ if (Dest->getType() == IceType_i8) {
+ Variable *T_ah = NULL;
+ Constant *Zero = Ctx->getConstantInt(IceType_i8, 0);
+ _mov(T, Src0, Reg_eax);
+ _mov(T_ah, Zero, Reg_ah);
+ _div(T_ah, Src1, T);
+ _mov(Dest, T_ah);
+ } else {
+ Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+ _mov(T_edx, Zero, Reg_edx);
+ _mov(T, Src0, Reg_eax);
+ _div(T_edx, Src1, T);
+ _mov(Dest, T_edx);
+ }
+ break;
+ case InstArithmetic::Srem:
+ T_edx = makeReg(IceType_i32, Reg_edx);
+ _mov(T, Src0, Reg_eax);
+ _cdq(T_edx, T);
+ _idiv(T_edx, Src1, T);
+ _mov(Dest, T_edx);
+ break;
+ case InstArithmetic::Fadd:
+ _mov(T, Src0);
+ _addss(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Fsub:
+ _mov(T, Src0);
+ _subss(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Fmul:
+ _mov(T, Src0);
+ _mulss(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Fdiv:
+ _mov(T, Src0);
+ _divss(T, Src1);
+ _mov(Dest, T);
+ break;
+ case InstArithmetic::Frem: {
+ const SizeT MaxSrcs = 2;
+ Type Ty = Dest->getType();
+ InstCall *Call =
+ makeHelperCall(Ty == IceType_f32 ? "fmodf" : "fmod", Dest, MaxSrcs);
+ Call->addArg(Src0);
+ Call->addArg(Src1);
+ return lowerCall(Call);
+ } break;
+ }
+ }
+}
+
+void TargetX8632::lowerAssign(const InstAssign *Inst) {
+ Variable *Dest = Inst->getDest();
+ Operand *Src0 = Inst->getSrc(0);
+ assert(Dest->getType() == Src0->getType());
+ if (Dest->getType() == IceType_i64) {
+ Src0 = legalize(Src0);
+ Operand *Src0Lo = loOperand(Src0);
+ Operand *Src0Hi = hiOperand(Src0);
+ Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
+ Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+ Variable *T_Lo = NULL, *T_Hi = NULL;
+ _mov(T_Lo, Src0Lo);
+ _mov(DestLo, T_Lo);
+ _mov(T_Hi, Src0Hi);
+ _mov(DestHi, T_Hi);
+ } else {
+ const bool AllowOverlap = true;
+ // RI is either a physical register or an immediate.
+ Operand *RI = legalize(Src0, Legal_Reg | Legal_Imm, AllowOverlap);
+ _mov(Dest, RI);
+ }
+}
+
+void TargetX8632::lowerBr(const InstBr *Inst) {
+ if (Inst->isUnconditional()) {
+ _br(Inst->getTargetUnconditional());
+ } else {
+ Operand *Src0 = legalize(Inst->getCondition());
+ Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+ _cmp(Src0, Zero);
+ _br(InstX8632Br::Br_ne, Inst->getTargetTrue(), Inst->getTargetFalse());
+ }
+}
+
+void TargetX8632::lowerCall(const InstCall *Instr) {
+ // Generate a sequence of push instructions, pushing right to left,
+ // keeping track of stack offsets in case a push involves a stack
+ // operand and we are using an esp-based frame.
+ uint32_t StackOffset = 0;
+ // TODO: If for some reason the call instruction gets dead-code
+ // eliminated after lowering, we would need to ensure that the
+ // pre-call push instructions and the post-call esp adjustment get
+ // eliminated as well.
+ for (SizeT NumArgs = Instr->getNumArgs(), i = 0; i < NumArgs; ++i) {
+ Operand *Arg = legalize(Instr->getArg(NumArgs - i - 1));
+ if (Arg->getType() == IceType_i64) {
+ _push(hiOperand(Arg));
+ _push(loOperand(Arg));
+ } else if (Arg->getType() == IceType_f64) {
+ // If the Arg turns out to be a memory operand, we need to push
+ // 8 bytes, which requires two push instructions. This ends up
+ // being somewhat clumsy in the current IR, so we use a
+ // workaround. Force the operand into a (xmm) register, and
+ // then push the register. An xmm register push is actually not
+ // possible in x86, but the Push instruction emitter handles
+ // this by decrementing the stack pointer and directly writing
+ // the xmm register value.
+ Variable *T = NULL;
+ _mov(T, Arg);
+ _push(T);
+ } else {
+ _push(Arg);
+ }
+ StackOffset += typeWidthInBytesOnStack(Arg->getType());
+ }
+ // Generate the call instruction. Assign its result to a temporary
+ // with high register allocation weight.
+ Variable *Dest = Instr->getDest();
+ Variable *eax = NULL; // doubles as RegLo as necessary
+ Variable *edx = NULL;
+ if (Dest) {
+ switch (Dest->getType()) {
+ case IceType_NUM:
+ llvm_unreachable("Invalid Call dest type");
+ break;
+ case IceType_void:
+ break;
+ case IceType_i1:
+ case IceType_i8:
+ case IceType_i16:
+ case IceType_i32:
+ eax = makeReg(Dest->getType(), Reg_eax);
+ break;
+ case IceType_i64:
+ eax = makeReg(IceType_i32, Reg_eax);
+ edx = makeReg(IceType_i32, Reg_edx);
+ break;
+ case IceType_f32:
+ case IceType_f64:
+ // Leave eax==edx==NULL, and capture the result with the fstp
+ // instruction.
+ break;
+ }
+ }
+ Operand *CallTarget = legalize(Instr->getCallTarget());
+ Inst *NewCall = InstX8632Call::create(Func, eax, CallTarget);
+ Context.insert(NewCall);
+ if (edx)
+ Context.insert(InstFakeDef::create(Func, edx));
+
+ // Add the appropriate offset to esp.
+ if (StackOffset) {
+ Variable *esp = Func->getTarget()->getPhysicalRegister(Reg_esp);
+ _add(esp, Ctx->getConstantInt(IceType_i32, StackOffset));
+ }
+
+ // Insert a register-kill pseudo instruction.
+ VarList KilledRegs;
+ for (SizeT i = 0; i < ScratchRegs.size(); ++i) {
+ if (ScratchRegs[i])
+ KilledRegs.push_back(Func->getTarget()->getPhysicalRegister(i));
+ }
+ Context.insert(InstFakeKill::create(Func, KilledRegs, NewCall));
+
+ // Generate a FakeUse to keep the call live if necessary.
+ if (Instr->hasSideEffects() && eax) {
+ Inst *FakeUse = InstFakeUse::create(Func, eax);
+ Context.insert(FakeUse);
+ }
+
+ // Generate Dest=eax assignment.
+ if (Dest && eax) {
+ if (edx) {
+ split64(Dest);
+ Variable *DestLo = Dest->getLo();
+ Variable *DestHi = Dest->getHi();
+ DestLo->setPreferredRegister(eax, false);
+ DestHi->setPreferredRegister(edx, false);
+ _mov(DestLo, eax);
+ _mov(DestHi, edx);
+ } else {
+ Dest->setPreferredRegister(eax, false);
+ _mov(Dest, eax);
+ }
+ }
+
+ // Special treatment for an FP function which returns its result in
+ // st(0).
+ if (Dest &&
+ (Dest->getType() == IceType_f32 || Dest->getType() == IceType_f64)) {
+ _fstp(Dest);
+ // If Dest ends up being a physical xmm register, the fstp emit
+ // code will route st(0) through a temporary stack slot.
+ }
+}
+
+void TargetX8632::lowerCast(const InstCast *Inst) {
+ // a = cast(b) ==> t=cast(b); a=t; (link t->b, link a->t, no overlap)
+ InstCast::OpKind CastKind = Inst->getCastKind();
+ Variable *Dest = Inst->getDest();
+ // Src0RM is the source operand legalized to physical register or memory, but
+ // not immediate, since the relevant x86 native instructions don't allow an
+ // immediate operand. If the operand is an immediate, we could consider
+ // computing the strength-reduced result at translation time, but we're
+ // unlikely to see something like that in the bitcode that the optimizer
+ // wouldn't have already taken care of.
+ Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem, true);
+ switch (CastKind) {
+ default:
+ Func->setError("Cast type not supported");
+ return;
+ case InstCast::Sext:
+ if (Dest->getType() == IceType_i64) {
+ // t1=movsx src; t2=t1; t2=sar t2, 31; dst.lo=t1; dst.hi=t2
+ Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
+ Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+ Variable *T_Lo = makeReg(DestLo->getType());
+ if (Src0RM->getType() == IceType_i32)
+ _mov(T_Lo, Src0RM);
+ else
+ _movsx(T_Lo, Src0RM);
+ _mov(DestLo, T_Lo);
+ Variable *T_Hi = NULL;
+ Constant *Shift = Ctx->getConstantInt(IceType_i32, 31);
+ _mov(T_Hi, T_Lo);
+ _sar(T_Hi, Shift);
+ _mov(DestHi, T_Hi);
+ } else {
+ // TODO: Sign-extend an i1 via "shl reg, 31; sar reg, 31", and
+ // also copy to the high operand of a 64-bit variable.
+ // t1 = movsx src; dst = t1
+ Variable *T = makeReg(Dest->getType());
+ _movsx(T, Src0RM);
+ _mov(Dest, T);
+ }
+ break;
+ case InstCast::Zext:
+ if (Dest->getType() == IceType_i64) {
+ // t1=movzx src; dst.lo=t1; dst.hi=0
+ Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+ Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
+ Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+ Variable *Tmp = makeReg(DestLo->getType());
+ if (Src0RM->getType() == IceType_i32)
+ _mov(Tmp, Src0RM);
+ else
+ _movzx(Tmp, Src0RM);
+ _mov(DestLo, Tmp);
+ _mov(DestHi, Zero);
+ } else if (Src0RM->getType() == IceType_i1) {
+ // t = Src0RM; t &= 1; Dest = t
+ Operand *One = Ctx->getConstantInt(IceType_i32, 1);
+ Variable *T = makeReg(IceType_i32);
+ _movzx(T, Src0RM);
+ _and(T, One);
+ _mov(Dest, T);
+ } else {
+ // t1 = movzx src; dst = t1
+ Variable *T = makeReg(Dest->getType());
+ _movzx(T, Src0RM);
+ _mov(Dest, T);
+ }
+ break;
+ case InstCast::Trunc: {
+ if (Src0RM->getType() == IceType_i64)
+ Src0RM = loOperand(Src0RM);
+ // t1 = trunc Src0RM; Dest = t1
+ Variable *T = NULL;
+ _mov(T, Src0RM);
+ _mov(Dest, T);
+ break;
+ }
+ case InstCast::Fptrunc:
+ case InstCast::Fpext: {
+ // t1 = cvt Src0RM; Dest = t1
+ Variable *T = makeReg(Dest->getType());
+ _cvt(T, Src0RM);
+ _mov(Dest, T);
+ break;
+ }
+ case InstCast::Fptosi:
+ if (Dest->getType() == IceType_i64) {
+ // Use a helper for converting floating-point values to 64-bit
+ // integers. SSE2 appears to have no way to convert from xmm
+ // registers to something like the edx:eax register pair, and
+ // gcc and clang both want to use x87 instructions complete with
+ // temporary manipulation of the status word. This helper is
+ // not needed for x86-64.
+ split64(Dest);
+ const SizeT MaxSrcs = 1;
+ Type SrcType = Inst->getSrc(0)->getType();
+ InstCall *Call = makeHelperCall(
+ SrcType == IceType_f32 ? "cvtftosi64" : "cvtdtosi64", Dest, MaxSrcs);
+ // TODO: Call the correct compiler-rt helper function.
+ Call->addArg(Inst->getSrc(0));
+ lowerCall(Call);
+ } else {
+ // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
+ Variable *T_1 = makeReg(IceType_i32);
+ Variable *T_2 = makeReg(Dest->getType());
+ _cvt(T_1, Src0RM);
+ _mov(T_2, T_1); // T_1 and T_2 may have different integer types
+ _mov(Dest, T_2);
+ T_2->setPreferredRegister(T_1, true);
+ }
+ break;
+ case InstCast::Fptoui:
+ if (Dest->getType() == IceType_i64 || Dest->getType() == IceType_i32) {
+ // Use a helper for both x86-32 and x86-64.
+ split64(Dest);
+ const SizeT MaxSrcs = 1;
+ Type DestType = Dest->getType();
+ Type SrcType = Src0RM->getType();
+ IceString DstSubstring = (DestType == IceType_i64 ? "64" : "32");
+ IceString SrcSubstring = (SrcType == IceType_f32 ? "f" : "d");
+ // Possibilities are cvtftoui32, cvtdtoui32, cvtftoui64, cvtdtoui64
+ IceString TargetString = "cvt" + SrcSubstring + "toui" + DstSubstring;
+ // TODO: Call the correct compiler-rt helper function.
+ InstCall *Call = makeHelperCall(TargetString, Dest, MaxSrcs);
+ Call->addArg(Inst->getSrc(0));
+ lowerCall(Call);
+ return;
+ } else {
+ // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
+ Variable *T_1 = makeReg(IceType_i32);
+ Variable *T_2 = makeReg(Dest->getType());
+ _cvt(T_1, Src0RM);
+ _mov(T_2, T_1); // T_1 and T_2 may have different integer types
+ _mov(Dest, T_2);
+ T_2->setPreferredRegister(T_1, true);
+ }
+ break;
+ case InstCast::Sitofp:
+ if (Src0RM->getType() == IceType_i64) {
+ // Use a helper for x86-32.
+ const SizeT MaxSrcs = 1;
+ Type DestType = Dest->getType();
+ InstCall *Call = makeHelperCall(
+ DestType == IceType_f32 ? "cvtsi64tof" : "cvtsi64tod", Dest, MaxSrcs);
+ // TODO: Call the correct compiler-rt helper function.
+ Call->addArg(Inst->getSrc(0));
+ lowerCall(Call);
+ return;
+ } else {
+ // Sign-extend the operand.
+ // t1.i32 = movsx Src0RM; t2 = Cvt t1.i32; Dest = t2
+ Variable *T_1 = makeReg(IceType_i32);
+ Variable *T_2 = makeReg(Dest->getType());
+ if (Src0RM->getType() == IceType_i32)
+ _mov(T_1, Src0RM);
+ else
+ _movsx(T_1, Src0RM);
+ _cvt(T_2, T_1);
+ _mov(Dest, T_2);
+ }
+ break;
+ case InstCast::Uitofp:
+ if (Src0RM->getType() == IceType_i64 || Src0RM->getType() == IceType_i32) {
+ // Use a helper for x86-32 and x86-64. Also use a helper for
+ // i32 on x86-32.
+ const SizeT MaxSrcs = 1;
+ Type DestType = Dest->getType();
+ IceString SrcSubstring = (Src0RM->getType() == IceType_i64 ? "64" : "32");
+ IceString DstSubstring = (DestType == IceType_f32 ? "f" : "d");
+ // Possibilities are cvtui32tof, cvtui32tod, cvtui64tof, cvtui64tod
+ IceString TargetString = "cvtui" + SrcSubstring + "to" + DstSubstring;
+ // TODO: Call the correct compiler-rt helper function.
+ InstCall *Call = makeHelperCall(TargetString, Dest, MaxSrcs);
+ Call->addArg(Inst->getSrc(0));
+ lowerCall(Call);
+ return;
+ } else {
+ // Zero-extend the operand.
+ // t1.i32 = movzx Src0RM; t2 = Cvt t1.i32; Dest = t2
+ Variable *T_1 = makeReg(IceType_i32);
+ Variable *T_2 = makeReg(Dest->getType());
+ if (Src0RM->getType() == IceType_i32)
+ _mov(T_1, Src0RM);
+ else
+ _movzx(T_1, Src0RM);
+ _cvt(T_2, T_1);
+ _mov(Dest, T_2);
+ }
+ break;
+ case InstCast::Bitcast:
+ if (Dest->getType() == Src0RM->getType()) {
+ InstAssign *Assign = InstAssign::create(Func, Dest, Src0RM);
+ lowerAssign(Assign);
+ return;
+ }
+ switch (Dest->getType()) {
+ default:
+ llvm_unreachable("Unexpected Bitcast dest type");
+ case IceType_i32:
+ case IceType_f32: {
+ Type DestType = Dest->getType();
+ Type SrcType = Src0RM->getType();
+ assert((DestType == IceType_i32 && SrcType == IceType_f32) ||
+ (DestType == IceType_f32 && SrcType == IceType_i32));
+ // a.i32 = bitcast b.f32 ==>
+ // t.f32 = b.f32
+ // s.f32 = spill t.f32
+ // a.i32 = s.f32
+ Variable *T = NULL;
+ // TODO: Should be able to force a spill setup by calling legalize() with
+ // Legal_Mem and not Legal_Reg or Legal_Imm.
+ Variable *Spill = Func->makeVariable(SrcType, Context.getNode());
+ Spill->setWeight(RegWeight::Zero);
+ Spill->setPreferredRegister(Dest, true);
+ _mov(T, Src0RM);
+ _mov(Spill, T);
+ _mov(Dest, Spill);
+ } break;
+ case IceType_i64: {
+ assert(Src0RM->getType() == IceType_f64);
+ // a.i64 = bitcast b.f64 ==>
+ // s.f64 = spill b.f64
+ // t_lo.i32 = lo(s.f64)
+ // a_lo.i32 = t_lo.i32
+ // t_hi.i32 = hi(s.f64)
+ // a_hi.i32 = t_hi.i32
+ Variable *Spill = Func->makeVariable(IceType_f64, Context.getNode());
+ Spill->setWeight(RegWeight::Zero);
+ Spill->setPreferredRegister(llvm::dyn_cast<Variable>(Src0RM), true);
+ _mov(Spill, Src0RM);
+
+ Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
+ Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+ Variable *T_Lo = makeReg(IceType_i32);
+ Variable *T_Hi = makeReg(IceType_i32);
+ VariableSplit *SpillLo =
+ VariableSplit::create(Func, Spill, VariableSplit::Low);
+ VariableSplit *SpillHi =
+ VariableSplit::create(Func, Spill, VariableSplit::High);
+
+ _mov(T_Lo, SpillLo);
+ _mov(DestLo, T_Lo);
+ _mov(T_Hi, SpillHi);
+ _mov(DestHi, T_Hi);
+ } break;
+ case IceType_f64: {
+ assert(Src0RM->getType() == IceType_i64);
+ // a.f64 = bitcast b.i64 ==>
+ // t_lo.i32 = b_lo.i32
+ // lo(s.f64) = t_lo.i32
+ // FakeUse(s.f64)
+ // t_hi.i32 = b_hi.i32
+ // hi(s.f64) = t_hi.i32
+ // a.f64 = s.f64
+ Variable *Spill = Func->makeVariable(IceType_f64, Context.getNode());
+ Spill->setWeight(RegWeight::Zero);
+ Spill->setPreferredRegister(Dest, true);
+
+ Context.insert(InstFakeDef::create(Func, Spill));
+
+ Variable *T_Lo = NULL, *T_Hi = NULL;
+ VariableSplit *SpillLo =
+ VariableSplit::create(Func, Spill, VariableSplit::Low);
+ VariableSplit *SpillHi =
+ VariableSplit::create(Func, Spill, VariableSplit::High);
+ _mov(T_Lo, loOperand(Src0RM));
+ _store(T_Lo, SpillLo);
+ _mov(T_Hi, hiOperand(Src0RM));
+ _store(T_Hi, SpillHi);
+ _mov(Dest, Spill);
+ } break;
+ }
+ break;
+ }
+}
+
+void TargetX8632::lowerFcmp(const InstFcmp *Inst) {
+ Operand *Src0 = Inst->getSrc(0);
+ Operand *Src1 = Inst->getSrc(1);
+ Variable *Dest = Inst->getDest();
+ // Lowering a = fcmp cond, b, c
+ // ucomiss b, c /* only if C1 != Br_None */
+ // /* but swap b,c order if SwapOperands==true */
+ // mov a, <default>
+ // j<C1> label /* only if C1 != Br_None */
+ // j<C2> label /* only if C2 != Br_None */
+ // FakeUse(a) /* only if C1 != Br_None */
+ // mov a, !<default> /* only if C1 != Br_None */
+ // label: /* only if C1 != Br_None */
+ InstFcmp::FCond Condition = Inst->getCondition();
+ size_t Index = static_cast<size_t>(Condition);
+ assert(Index < TableFcmpSize);
+ if (TableFcmp[Index].SwapOperands) {
+ Operand *Tmp = Src0;
+ Src0 = Src1;
+ Src1 = Tmp;
+ }
+ bool HasC1 = (TableFcmp[Index].C1 != InstX8632Br::Br_None);
+ bool HasC2 = (TableFcmp[Index].C2 != InstX8632Br::Br_None);
+ if (HasC1) {
+ Src0 = legalize(Src0);
+ Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
+ Variable *T = NULL;
+ _mov(T, Src0);
+ _ucomiss(T, Src1RM);
+ }
+ Constant *Default =
+ Ctx->getConstantInt(IceType_i32, TableFcmp[Index].Default);
+ _mov(Dest, Default);
+ if (HasC1) {
+ InstX8632Label *Label = InstX8632Label::create(Func, this);
+ _br(TableFcmp[Index].C1, Label);
+ if (HasC2) {
+ _br(TableFcmp[Index].C2, Label);
+ }
+ Context.insert(InstFakeUse::create(Func, Dest));
+ Constant *NonDefault =
+ Ctx->getConstantInt(IceType_i32, !TableFcmp[Index].Default);
+ _mov(Dest, NonDefault);
+ Context.insert(Label);
+ }
+}
+
+void TargetX8632::lowerIcmp(const InstIcmp *Inst) {
+ Operand *Src0 = legalize(Inst->getSrc(0));
+ Operand *Src1 = legalize(Inst->getSrc(1));
+ Variable *Dest = Inst->getDest();
+
+ // a=icmp cond, b, c ==> cmp b,c; a=1; br cond,L1; FakeUse(a); a=0; L1:
+ Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+ Constant *One = Ctx->getConstantInt(IceType_i32, 1);
+ if (Src0->getType() == IceType_i64) {
+ InstIcmp::ICond Condition = Inst->getCondition();
+ size_t Index = static_cast<size_t>(Condition);
+ assert(Index < TableIcmp64Size);
+ Operand *Src1LoRI = legalize(loOperand(Src1), Legal_Reg | Legal_Imm);
+ Operand *Src1HiRI = legalize(hiOperand(Src1), Legal_Reg | Legal_Imm);
+ if (Condition == InstIcmp::Eq || Condition == InstIcmp::Ne) {
+ InstX8632Label *Label = InstX8632Label::create(Func, this);
+ _mov(Dest, (Condition == InstIcmp::Eq ? Zero : One));
+ _cmp(loOperand(Src0), Src1LoRI);
+ _br(InstX8632Br::Br_ne, Label);
+ _cmp(hiOperand(Src0), Src1HiRI);
+ _br(InstX8632Br::Br_ne, Label);
+ Context.insert(InstFakeUse::create(Func, Dest));
+ _mov(Dest, (Condition == InstIcmp::Eq ? One : Zero));
+ Context.insert(Label);
+ } else {
+ InstX8632Label *LabelFalse = InstX8632Label::create(Func, this);
+ InstX8632Label *LabelTrue = InstX8632Label::create(Func, this);
+ _mov(Dest, One);
+ _cmp(hiOperand(Src0), Src1HiRI);
+ _br(TableIcmp64[Index].C1, LabelTrue);
+ _br(TableIcmp64[Index].C2, LabelFalse);
+ _cmp(loOperand(Src0), Src1LoRI);
+ _br(TableIcmp64[Index].C3, LabelTrue);
+ Context.insert(LabelFalse);
+ Context.insert(InstFakeUse::create(Func, Dest));
+ _mov(Dest, Zero);
+ Context.insert(LabelTrue);
+ }
+ return;
+ }
+
+ // If Src1 is an immediate, or known to be a physical register, we can
+ // allow Src0 to be a memory operand. Otherwise, Src0 must be copied into
+ // a physical register. (Actually, either Src0 or Src1 can be chosen for
+ // the physical register, but unfortunately we have to commit to one or
+ // the other before register allocation.)
+ bool IsSrc1ImmOrReg = false;
+ if (llvm::isa<Constant>(Src1)) {
+ IsSrc1ImmOrReg = true;
+ } else if (Variable *Var = llvm::dyn_cast<Variable>(Src1)) {
+ if (Var->hasReg())
+ IsSrc1ImmOrReg = true;
+ }
+
+ // cmp b, c
+ Operand *Src0New =
+ legalize(Src0, IsSrc1ImmOrReg ? Legal_All : Legal_Reg, true);
+ InstX8632Label *Label = InstX8632Label::create(Func, this);
+ _cmp(Src0New, Src1);
+ _mov(Dest, One);
+ _br(getIcmp32Mapping(Inst->getCondition()), Label);
+ Context.insert(InstFakeUse::create(Func, Dest));
+ _mov(Dest, Zero);
+ Context.insert(Label);
+}
+
+void TargetX8632::lowerLoad(const InstLoad *Inst) {
+ // A Load instruction can be treated the same as an Assign
+ // instruction, after the source operand is transformed into an
+ // OperandX8632Mem operand. Note that the address mode
+ // optimization already creates an OperandX8632Mem operand, so it
+ // doesn't need another level of transformation.
+ Type Ty = Inst->getDest()->getType();
+ Operand *Src0 = Inst->getSourceAddress();
+ // Address mode optimization already creates an OperandX8632Mem
+ // operand, so it doesn't need another level of transformation.
+ if (!llvm::isa<OperandX8632Mem>(Src0)) {
+ Variable *Base = llvm::dyn_cast<Variable>(Src0);
+ Constant *Offset = llvm::dyn_cast<Constant>(Src0);
+ assert(Base || Offset);
+ Src0 = OperandX8632Mem::create(Func, Ty, Base, Offset);
+ }
+
+ InstAssign *Assign = InstAssign::create(Func, Inst->getDest(), Src0);
+ lowerAssign(Assign);
+}
+
+void TargetX8632::lowerPhi(const InstPhi * /*Inst*/) {
+ Func->setError("Phi found in regular instruction list");
+}
+
+void TargetX8632::lowerRet(const InstRet *Inst) {
+ Variable *Reg = NULL;
+ if (Inst->hasRetValue()) {
+ Operand *Src0 = legalize(Inst->getRetValue());
+ if (Src0->getType() == IceType_i64) {
+ Variable *eax = legalizeToVar(loOperand(Src0), false, Reg_eax);
+ Variable *edx = legalizeToVar(hiOperand(Src0), false, Reg_edx);
+ Reg = eax;
+ Context.insert(InstFakeUse::create(Func, edx));
+ } else if (Src0->getType() == IceType_f32 ||
+ Src0->getType() == IceType_f64) {
+ _fld(Src0);
+ } else {
+ _mov(Reg, Src0, Reg_eax);
+ }
+ }
+ _ret(Reg);
+ // Add a fake use of esp to make sure esp stays alive for the entire
+ // function. Otherwise post-call esp adjustments get dead-code
+ // eliminated. TODO: Are there more places where the fake use
+ // should be inserted? E.g. "void f(int n){while(1) g(n);}" may not
+ // have a ret instruction.
+ Variable *esp = Func->getTarget()->getPhysicalRegister(Reg_esp);
+ Context.insert(InstFakeUse::create(Func, esp));
+}
+
+void TargetX8632::lowerSelect(const InstSelect *Inst) {
+ // a=d?b:c ==> cmp d,0; a=b; jne L1; FakeUse(a); a=c; L1:
+ Variable *Dest = Inst->getDest();
+ Operand *SrcT = Inst->getTrueOperand();
+ Operand *SrcF = Inst->getFalseOperand();
+ Operand *Condition = legalize(Inst->getCondition());
+ Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+ InstX8632Label *Label = InstX8632Label::create(Func, this);
+
+ if (Dest->getType() == IceType_i64) {
+ Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
+ Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+ Operand *SrcLoRI = legalize(loOperand(SrcT), Legal_Reg | Legal_Imm, true);
+ Operand *SrcHiRI = legalize(hiOperand(SrcT), Legal_Reg | Legal_Imm, true);
+ _cmp(Condition, Zero);
+ _mov(DestLo, SrcLoRI);
+ _mov(DestHi, SrcHiRI);
+ _br(InstX8632Br::Br_ne, Label);
+ Context.insert(InstFakeUse::create(Func, DestLo));
+ Context.insert(InstFakeUse::create(Func, DestHi));
+ Operand *SrcFLo = loOperand(SrcF);
+ Operand *SrcFHi = hiOperand(SrcF);
+ SrcLoRI = legalize(SrcFLo, Legal_Reg | Legal_Imm, true);
+ SrcHiRI = legalize(SrcFHi, Legal_Reg | Legal_Imm, true);
+ _mov(DestLo, SrcLoRI);
+ _mov(DestHi, SrcHiRI);
+ } else {
+ _cmp(Condition, Zero);
+ SrcT = legalize(SrcT, Legal_Reg | Legal_Imm, true);
+ _mov(Dest, SrcT);
+ _br(InstX8632Br::Br_ne, Label);
+ Context.insert(InstFakeUse::create(Func, Dest));
+ SrcF = legalize(SrcF, Legal_Reg | Legal_Imm, true);
+ _mov(Dest, SrcF);
+ }
+
+ Context.insert(Label);
+}
+
+void TargetX8632::lowerStore(const InstStore *Inst) {
+ Operand *Value = Inst->getData();
+ Operand *Addr = Inst->getAddr();
+ OperandX8632Mem *NewAddr = llvm::dyn_cast<OperandX8632Mem>(Addr);
+ // Address mode optimization already creates an OperandX8632Mem
+ // operand, so it doesn't need another level of transformation.
+ if (!NewAddr) {
+ // The address will be either a constant (which represents a global
+ // variable) or a variable, so either the Base or Offset component
+ // of the OperandX8632Mem will be set.
+ Variable *Base = llvm::dyn_cast<Variable>(Addr);
+ Constant *Offset = llvm::dyn_cast<Constant>(Addr);
+ assert(Base || Offset);
+ NewAddr = OperandX8632Mem::create(Func, Value->getType(), Base, Offset);
+ }
+ NewAddr = llvm::cast<OperandX8632Mem>(legalize(NewAddr));
+
+ if (NewAddr->getType() == IceType_i64) {
+ Value = legalize(Value);
+ Operand *ValueHi = legalize(hiOperand(Value), Legal_Reg | Legal_Imm, true);
+ Operand *ValueLo = legalize(loOperand(Value), Legal_Reg | Legal_Imm, true);
+ _store(ValueHi, llvm::cast<OperandX8632Mem>(hiOperand(NewAddr)));
+ _store(ValueLo, llvm::cast<OperandX8632Mem>(loOperand(NewAddr)));
+ } else {
+ Value = legalize(Value, Legal_Reg | Legal_Imm, true);
+ _store(Value, NewAddr);
+ }
+}
+
+void TargetX8632::lowerSwitch(const InstSwitch *Inst) {
+ // This implements the most naive possible lowering.
+ // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
+ Operand *Src0 = Inst->getComparison();
+ SizeT NumCases = Inst->getNumCases();
+ // OK, we'll be slightly less naive by forcing Src into a physical
+ // register if there are 2 or more uses.
+ if (NumCases >= 2)
+ Src0 = legalizeToVar(Src0, true);
+ else
+ Src0 = legalize(Src0, Legal_All, true);
+ for (SizeT I = 0; I < NumCases; ++I) {
+ Operand *Value = Ctx->getConstantInt(IceType_i32, Inst->getValue(I));
+ _cmp(Src0, Value);
+ _br(InstX8632Br::Br_e, Inst->getLabel(I));
+ }
+
+ _br(Inst->getLabelDefault());
+}
+
+void TargetX8632::lowerUnreachable(const InstUnreachable * /*Inst*/) {
+ const SizeT MaxSrcs = 0;
+ Variable *Dest = NULL;
+ InstCall *Call = makeHelperCall("ice_unreachable", Dest, MaxSrcs);
+ lowerCall(Call);
+}
+
+Operand *TargetX8632::legalize(Operand *From, LegalMask Allowed,
+ bool AllowOverlap, int32_t RegNum) {
+ // Assert that a physical register is allowed. To date, all calls
+ // to legalize() allow a physical register. If a physical register
+ // needs to be explicitly disallowed, then new code will need to be
+ // written to force a spill.
+ assert(Allowed & Legal_Reg);
+ // If we're asking for a specific physical register, make sure we're
+ // not allowing any other operand kinds. (This could be future
+ // work, e.g. allow the shl shift amount to be either an immediate
+ // or in ecx.)
+ assert(RegNum == Variable::NoRegister || Allowed == Legal_Reg);
+ if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(From)) {
+ // Before doing anything with a Mem operand, we need to ensure
+ // that the Base and Index components are in physical registers.
+ Variable *Base = Mem->getBase();
+ Variable *Index = Mem->getIndex();
+ Variable *RegBase = NULL;
+ Variable *RegIndex = NULL;
+ if (Base) {
+ RegBase = legalizeToVar(Base, true);
+ }
+ if (Index) {
+ RegIndex = legalizeToVar(Index, true);
+ }
+ if (Base != RegBase || Index != RegIndex) {
+ From =
+ OperandX8632Mem::create(Func, Mem->getType(), RegBase,
+ Mem->getOffset(), RegIndex, Mem->getShift());
+ }
+
+ if (!(Allowed & Legal_Mem)) {
+ Variable *Reg = makeReg(From->getType(), RegNum);
+ _mov(Reg, From, RegNum);
+ From = Reg;
+ }
+ return From;
+ }
+ if (llvm::isa<Constant>(From)) {
+ if (!(Allowed & Legal_Imm)) {
+ Variable *Reg = makeReg(From->getType(), RegNum);
+ _mov(Reg, From);
+ From = Reg;
+ }
+ return From;
+ }
+ if (Variable *Var = llvm::dyn_cast<Variable>(From)) {
+ // We need a new physical register for the operand if:
+ // Mem is not allowed and Var->getRegNum() is unknown, or
+ // RegNum is required and Var->getRegNum() doesn't match.
+ if ((!(Allowed & Legal_Mem) && !Var->hasReg()) ||
+ (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
+ Variable *Reg = makeReg(From->getType(), RegNum);
+ if (RegNum == Variable::NoRegister) {
+ Reg->setPreferredRegister(Var, AllowOverlap);
+ }
+ _mov(Reg, From);
+ From = Reg;
+ }
+ return From;
+ }
+ llvm_unreachable("Unhandled operand kind in legalize()");
+ return From;
+}
+
+// Provide a trivial wrapper to legalize() for this common usage.
+Variable *TargetX8632::legalizeToVar(Operand *From, bool AllowOverlap,
+ int32_t RegNum) {
+ return llvm::cast<Variable>(legalize(From, Legal_Reg, AllowOverlap, RegNum));
+}
+
+Variable *TargetX8632::makeReg(Type Type, int32_t RegNum) {
+ Variable *Reg = Func->makeVariable(Type, Context.getNode());
+ if (RegNum == Variable::NoRegister)
+ Reg->setWeightInfinite();
+ else
+ Reg->setRegNum(RegNum);
+ return Reg;
+}
+
+void TargetX8632::postLower() {
+ if (Ctx->getOptLevel() != Opt_m1)
+ return;
+ // TODO: Avoid recomputing WhiteList every instruction.
+ llvm::SmallBitVector WhiteList = getRegisterSet(RegSet_All, RegSet_None);
+ // Make one pass to black-list pre-colored registers. TODO: If
+ // there was some prior register allocation pass that made register
+ // assignments, those registers need to be black-listed here as
+ // well.
+ for (InstList::iterator I = Context.getCur(), E = Context.getEnd(); I != E;
+ ++I) {
+ const Inst *Inst = *I;
+ if (Inst->isDeleted())
+ continue;
+ if (llvm::isa<InstFakeKill>(Inst))
+ continue;
+ SizeT VarIndex = 0;
+ for (SizeT SrcNum = 0; SrcNum < Inst->getSrcSize(); ++SrcNum) {
+ Operand *Src = Inst->getSrc(SrcNum);
+ SizeT NumVars = Src->getNumVars();
+ for (SizeT J = 0; J < NumVars; ++J, ++VarIndex) {
+ const Variable *Var = Src->getVar(J);
+ if (!Var->hasReg())
+ continue;
+ WhiteList[Var->getRegNum()] = false;
+ }
+ }
+ }
+ // The second pass colors infinite-weight variables.
+ llvm::SmallBitVector AvailableRegisters = WhiteList;
+ for (InstList::iterator I = Context.getCur(), E = Context.getEnd(); I != E;
+ ++I) {
+ const Inst *Inst = *I;
+ if (Inst->isDeleted())
+ continue;
+ SizeT VarIndex = 0;
+ for (SizeT SrcNum = 0; SrcNum < Inst->getSrcSize(); ++SrcNum) {
+ Operand *Src = Inst->getSrc(SrcNum);
+ SizeT NumVars = Src->getNumVars();
+ for (SizeT J = 0; J < NumVars; ++J, ++VarIndex) {
+ Variable *Var = Src->getVar(J);
+ if (Var->hasReg())
+ continue;
+ if (!Var->getWeight().isInf())
+ continue;
+ llvm::SmallBitVector AvailableTypedRegisters =
+ AvailableRegisters & getRegisterSetForType(Var->getType());
+ if (!AvailableTypedRegisters.any()) {
+ // This is a hack in case we run out of physical registers
+ // due to an excessive number of "push" instructions from
+ // lowering a call.
+ AvailableRegisters = WhiteList;
+ AvailableTypedRegisters =
+ AvailableRegisters & getRegisterSetForType(Var->getType());
+ }
+ assert(AvailableTypedRegisters.any());
+ int32_t RegNum = AvailableTypedRegisters.find_first();
+ Var->setRegNum(RegNum);
+ AvailableRegisters[RegNum] = false;
+ }
+ }
+ }
+}
+
+} // end of namespace Ice
diff --git a/src/IceTargetLoweringX8632.def b/src/IceTargetLoweringX8632.def
new file mode 100644
index 0000000..b88091a
--- /dev/null
+++ b/src/IceTargetLoweringX8632.def
@@ -0,0 +1,52 @@
+//===- subzero/src/IceTargetLoweringX8632.def - x86-32 X-macros -*- C++ -*-===//
+//
+// The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines certain patterns for lowering to x86-32 target
+// instructions, in the form of x-macros.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICETARGETLOWERINGX8632_DEF
+#define SUBZERO_SRC_ICETARGETLOWERINGX8632_DEF
+
+#define FCMPX8632_TABLE \
+ /* val, dflt, swap, C1, C2 */ \
+ X(False, 0, 0, Br_None, Br_None) \
+ X(Oeq, 0, 0, Br_ne, Br_p) \
+ X(Ogt, 1, 0, Br_a, Br_None) \
+ X(Oge, 1, 0, Br_ae, Br_None) \
+ X(Olt, 1, 1, Br_a, Br_None) \
+ X(Ole, 1, 1, Br_ae, Br_None) \
+ X(One, 1, 0, Br_ne, Br_None) \
+ X(Ord, 1, 0, Br_np, Br_None) \
+ X(Ueq, 1, 0, Br_e, Br_None) \
+ X(Ugt, 1, 1, Br_b, Br_None) \
+ X(Uge, 1, 1, Br_be, Br_None) \
+ X(Ult, 1, 0, Br_b, Br_None) \
+ X(Ule, 1, 0, Br_be, Br_None) \
+ X(Une, 1, 0, Br_ne, Br_p) \
+ X(Uno, 1, 0, Br_p, Br_None) \
+ X(True, 1, 0, Br_None, Br_None) \
+//#define X(val, dflt, swap, C1, C2)
+
+#define ICMPX8632_TABLE \
+ /* val, C_32, C1_64, C2_64, C3_64 */ \
+ X(Eq, Br_e, Br_None, Br_None, Br_None) \
+ X(Ne, Br_ne, Br_None, Br_None, Br_None) \
+ X(Ugt, Br_a, Br_a, Br_b, Br_a) \
+ X(Uge, Br_ae, Br_a, Br_b, Br_ae) \
+ X(Ult, Br_b, Br_b, Br_a, Br_b) \
+ X(Ule, Br_be, Br_b, Br_a, Br_be) \
+ X(Sgt, Br_g, Br_g, Br_l, Br_a) \
+ X(Sge, Br_ge, Br_g, Br_l, Br_ae) \
+ X(Slt, Br_l, Br_l, Br_g, Br_b) \
+ X(Sle, Br_le, Br_l, Br_g, Br_be) \
+//#define X(val, C_32, C1_64, C2_64, C3_64)
+
+#endif // SUBZERO_SRC_ICETARGETLOWERINGX8632_DEF
diff --git a/src/IceTargetLoweringX8632.h b/src/IceTargetLoweringX8632.h
new file mode 100644
index 0000000..38184de
--- /dev/null
+++ b/src/IceTargetLoweringX8632.h
@@ -0,0 +1,268 @@
+//===- subzero/src/IceTargetLoweringX8632.h - x86-32 lowering ---*- C++ -*-===//
+//
+// The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the TargetLoweringX8632 class, which
+// implements the TargetLowering interface for the x86-32
+// architecture.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICETARGETLOWERINGX8632_H
+#define SUBZERO_SRC_ICETARGETLOWERINGX8632_H
+
+#include "IceDefs.h"
+#include "IceTargetLowering.h"
+#include "IceInstX8632.h"
+
+namespace Ice {
+
+class TargetX8632 : public TargetLowering {
+public:
+ static TargetX8632 *create(Cfg *Func) { return new TargetX8632(Func); }
+
+ virtual void translateOm1();
+
+ virtual Variable *getPhysicalRegister(SizeT RegNum);
+ virtual IceString getRegName(SizeT RegNum, Type Ty) const;
+ virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include,
+ RegSetMask Exclude) const;
+ virtual const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const {
+ return TypeToRegisterSet[Ty];
+ }
+ virtual bool hasFramePointer() const { return IsEbpBasedFrame; }
+ virtual SizeT getFrameOrStackReg() const {
+ return IsEbpBasedFrame ? Reg_ebp : Reg_esp;
+ }
+ virtual size_t typeWidthInBytesOnStack(Type Ty) {
+ // Round up to the next multiple of 4 bytes. In particular, i1,
+ // i8, and i16 are rounded up to 4 bytes.
+ return (typeWidthInBytes(Ty) + 3) & ~3;
+ }
+ virtual void emitVariable(const Variable *Var, const Cfg *Func) const;
+ virtual void addProlog(CfgNode *Node);
+ virtual void addEpilog(CfgNode *Node);
+ SizeT makeNextLabelNumber() { return NextLabelNumber++; }
+ // Ensure that a 64-bit Variable has been split into 2 32-bit
+ // Variables, creating them if necessary. This is needed for all
+ // I64 operations, and it is needed for pushing F64 arguments for
+ // function calls using the 32-bit push instruction (though the
+ // latter could be done by directly writing to the stack).
+ void split64(Variable *Var);
+ void setArgOffsetAndCopy(Variable *Arg, Variable *FramePtr,
+ int32_t BasicFrameOffset, int32_t &InArgsSizeBytes);
+ Operand *loOperand(Operand *Operand);
+ Operand *hiOperand(Operand *Operand);
+
+ enum Registers {
+#define X(val, init, name, name16, name8, scratch, preserved, stackptr, \
+ frameptr, isI8, isInt, isFP) \
+ val init,
+ REGX8632_TABLE
+#undef X
+ Reg_NUM
+ };
+
+protected:
+ TargetX8632(Cfg *Func);
+
+ virtual void postLower();
+
+ virtual void lowerAlloca(const InstAlloca *Inst);
+ virtual void lowerArithmetic(const InstArithmetic *Inst);
+ virtual void lowerAssign(const InstAssign *Inst);
+ virtual void lowerBr(const InstBr *Inst);
+ virtual void lowerCall(const InstCall *Inst);
+ virtual void lowerCast(const InstCast *Inst);
+ virtual void lowerFcmp(const InstFcmp *Inst);
+ virtual void lowerIcmp(const InstIcmp *Inst);
+ virtual void lowerLoad(const InstLoad *Inst);
+ virtual void lowerPhi(const InstPhi *Inst);
+ virtual void lowerRet(const InstRet *Inst);
+ virtual void lowerSelect(const InstSelect *Inst);
+ virtual void lowerStore(const InstStore *Inst);
+ virtual void lowerSwitch(const InstSwitch *Inst);
+ virtual void lowerUnreachable(const InstUnreachable *Inst);
+
+ // Operand legalization helpers. To deal with address mode
+ // constraints, the helpers will create a new Operand and emit
+ // instructions that guarantee that the Operand kind is one of those
+ // indicated by the LegalMask (a bitmask of allowed kinds). If the
+ // input Operand is known to already meet the constraints, it may be
+ // simply returned as the result, without creating any new
+ // instructions or operands.
+ enum OperandLegalization {
+ Legal_None = 0,
+ Legal_Reg = 1 << 0, // physical register, not stack location
+ Legal_Imm = 1 << 1,
+ Legal_Mem = 1 << 2, // includes [eax+4*ecx] as well as [esp+12]
+ Legal_All = ~Legal_None
+ };
+ typedef uint32_t LegalMask;
+ Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
+ bool AllowOverlap = false,
+ int32_t RegNum = Variable::NoRegister);
+ Variable *legalizeToVar(Operand *From, bool AllowOverlap = false,
+ int32_t RegNum = Variable::NoRegister);
+
+ Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);
+ InstCall *makeHelperCall(const IceString &Name, Variable *Dest,
+ SizeT MaxSrcs) {
+ bool SuppressMangling = true;
+ Type Ty = Dest ? Dest->getType() : IceType_void;
+ Constant *CallTarget = Ctx->getConstantSym(Ty, 0, Name, SuppressMangling);
+ InstCall *Call = InstCall::create(Func, MaxSrcs, Dest, CallTarget);
+ return Call;
+ }
+
+ // The following are helpers that insert lowered x86 instructions
+ // with minimal syntactic overhead, so that the lowering code can
+ // look as close to assembly as practical.
+ void _adc(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Adc::create(Func, Dest, Src0));
+ }
+ void _add(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Add::create(Func, Dest, Src0));
+ }
+ void _addss(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Addss::create(Func, Dest, Src0));
+ }
+ void _and(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632And::create(Func, Dest, Src0));
+ }
+ void _br(InstX8632Br::BrCond Condition, CfgNode *TargetTrue,
+ CfgNode *TargetFalse) {
+ Context.insert(
+ InstX8632Br::create(Func, TargetTrue, TargetFalse, Condition));
+ }
+ void _br(CfgNode *Target) {
+ Context.insert(InstX8632Br::create(Func, Target));
+ }
+ void _br(InstX8632Br::BrCond Condition, CfgNode *Target) {
+ Context.insert(InstX8632Br::create(Func, Target, Condition));
+ }
+ void _br(InstX8632Br::BrCond Condition, InstX8632Label *Label) {
+ Context.insert(InstX8632Br::create(Func, Label, Condition));
+ }
+ void _cdq(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Cdq::create(Func, Dest, Src0));
+ }
+ void _cmp(Operand *Src0, Operand *Src1) {
+ Context.insert(InstX8632Icmp::create(Func, Src0, Src1));
+ }
+ void _cvt(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Cvt::create(Func, Dest, Src0));
+ }
+ void _div(Variable *Dest, Operand *Src0, Operand *Src1) {
+ Context.insert(InstX8632Div::create(Func, Dest, Src0, Src1));
+ }
+ void _divss(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Divss::create(Func, Dest, Src0));
+ }
+ void _fld(Operand *Src0) { Context.insert(InstX8632Fld::create(Func, Src0)); }
+ void _fstp(Variable *Dest) {
+ Context.insert(InstX8632Fstp::create(Func, Dest));
+ }
+ void _idiv(Variable *Dest, Operand *Src0, Operand *Src1) {
+ Context.insert(InstX8632Idiv::create(Func, Dest, Src0, Src1));
+ }
+ void _imul(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Imul::create(Func, Dest, Src0));
+ }
+ // If Dest=NULL is passed in, then a new variable is created, marked
+ // as infinite register allocation weight, and returned through the
+ // in/out Dest argument.
+ void _mov(Variable *&Dest, Operand *Src0,
+ int32_t RegNum = Variable::NoRegister) {
+ if (Dest == NULL) {
+ Dest = legalizeToVar(Src0, false, RegNum);
+ } else {
+ Context.insert(InstX8632Mov::create(Func, Dest, Src0));
+ }
+ }
+ void _movsx(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Movsx::create(Func, Dest, Src0));
+ }
+ void _movzx(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Movzx::create(Func, Dest, Src0));
+ }
+ void _mul(Variable *Dest, Variable *Src0, Operand *Src1) {
+ Context.insert(InstX8632Mul::create(Func, Dest, Src0, Src1));
+ }
+ void _mulss(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Mulss::create(Func, Dest, Src0));
+ }
+ void _or(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Or::create(Func, Dest, Src0));
+ }
+ void _pop(Variable *Dest) {
+ Context.insert(InstX8632Pop::create(Func, Dest));
+ }
+ void _push(Operand *Src0, bool SuppressStackAdjustment = false) {
+ Context.insert(InstX8632Push::create(Func, Src0, SuppressStackAdjustment));
+ }
+ void _ret(Variable *Src0 = NULL) {
+ Context.insert(InstX8632Ret::create(Func, Src0));
+ }
+ void _sar(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Sar::create(Func, Dest, Src0));
+ }
+ void _sbb(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Sbb::create(Func, Dest, Src0));
+ }
+ void _shl(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Shl::create(Func, Dest, Src0));
+ }
+ void _shld(Variable *Dest, Variable *Src0, Variable *Src1) {
+ Context.insert(InstX8632Shld::create(Func, Dest, Src0, Src1));
+ }
+ void _shr(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Shr::create(Func, Dest, Src0));
+ }
+ void _shrd(Variable *Dest, Variable *Src0, Variable *Src1) {
+ Context.insert(InstX8632Shrd::create(Func, Dest, Src0, Src1));
+ }
+ void _store(Operand *Value, OperandX8632 *Mem) {
+ Context.insert(InstX8632Store::create(Func, Value, Mem));
+ }
+ void _sub(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Sub::create(Func, Dest, Src0));
+ }
+ void _subss(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Subss::create(Func, Dest, Src0));
+ }
+ void _test(Operand *Src0, Operand *Src1) {
+ Context.insert(InstX8632Test::create(Func, Src0, Src1));
+ }
+ void _ucomiss(Operand *Src0, Operand *Src1) {
+ Context.insert(InstX8632Ucomiss::create(Func, Src0, Src1));
+ }
+ void _xor(Variable *Dest, Operand *Src0) {
+ Context.insert(InstX8632Xor::create(Func, Dest, Src0));
+ }
+
+ bool IsEbpBasedFrame;
+ int32_t FrameSizeLocals;
+ int32_t LocalsSizeBytes;
+ llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
+ llvm::SmallBitVector ScratchRegs;
+ llvm::SmallBitVector RegsUsed;
+ SizeT NextLabelNumber;
+ bool ComputedLiveRanges;
+ VarList PhysicalRegisters;
+ static IceString RegNames[];
+
+private:
+ TargetX8632(const TargetX8632 &) LLVM_DELETED_FUNCTION;
+ TargetX8632 &operator=(const TargetX8632 &) LLVM_DELETED_FUNCTION;
+ virtual ~TargetX8632() {}
+};
+
+} // end of namespace Ice
+
+#endif // SUBZERO_SRC_ICETARGETLOWERINGX8632_H
diff --git a/src/IceTypes.cpp b/src/IceTypes.cpp
index b54c0d7..84cf410 100644
--- a/src/IceTypes.cpp
+++ b/src/IceTypes.cpp
@@ -41,7 +41,7 @@
if (Index < TypeAttributesSize) {
Width = TypeAttributes[Index].TypeWidthInBytes;
} else {
- assert(0 && "Invalid type for typeWidthInBytes()");
+ llvm_unreachable("Invalid type for typeWidthInBytes()");
}
return Width;
}
@@ -52,7 +52,7 @@
if (Index < TypeAttributesSize) {
Align = TypeAttributes[Index].TypeAlignInBytes;
} else {
- assert(0 && "Invalid type for typeAlignInBytes()");
+ llvm_unreachable("Invalid type for typeAlignInBytes()");
}
return Align;
}
@@ -65,7 +65,7 @@
Str << TypeAttributes[Index].DisplayString;
} else {
Str << "???";
- assert(0 && "Invalid type for printing");
+ llvm_unreachable("Invalid type for printing");
}
return Str;
diff --git a/src/IceTypes.def b/src/IceTypes.def
index a54ab65..fc48b9d 100644
--- a/src/IceTypes.def
+++ b/src/IceTypes.def
@@ -25,7 +25,8 @@
X(IceType_i32, 4, 1, "i32") \
X(IceType_i64, 8, 1, "i64") \
X(IceType_f32, 4, 4, "float") \
- X(IceType_f64, 8, 8, "double")
+ X(IceType_f64, 8, 8, "double") \
+ X(IceType_NUM, 0, 0, "<invalid>") \
//#define X(tag, size, align, str)
#endif // SUBZERO_SRC_ICETYPES_DEF
diff --git a/src/IceTypes.h b/src/IceTypes.h
index b3d28c3..21c399d 100644
--- a/src/IceTypes.h
+++ b/src/IceTypes.h
@@ -26,6 +26,20 @@
#undef X
};
+enum TargetArch {
+ Target_X8632,
+ Target_X8664,
+ Target_ARM32,
+ Target_ARM64
+};
+
+enum OptLevel {
+ Opt_m1,
+ Opt_0,
+ Opt_1,
+ Opt_2
+};
+
size_t typeWidthInBytes(Type Ty);
size_t typeAlignInBytes(Type Ty);
diff --git a/src/llvm2ice.cpp b/src/llvm2ice.cpp
index 7136331..08f90f8 100644
--- a/src/llvm2ice.cpp
+++ b/src/llvm2ice.cpp
@@ -165,8 +165,9 @@
return Ice::IceType_void;
}
- // Given a LLVM instruction and an operand number, produce the Operand this
- // refers to. If there's no such operand, return NULL.
+ // Given an LLVM instruction and an operand number, produce the
+ // Ice::Operand this refers to. If there's no such operand, return
+ // NULL.
Ice::Operand *convertOperand(const Instruction *Inst, unsigned OpNum) {
if (OpNum >= Inst->getNumOperands()) {
return NULL;
@@ -189,10 +190,10 @@
return Ctx->getConstantFloat(CFP->getValueAPF().convertToFloat());
else if (Type == Ice::IceType_f64)
return Ctx->getConstantDouble(CFP->getValueAPF().convertToDouble());
- assert(0 && "Unexpected floating point type");
+ llvm_unreachable("Unexpected floating point type");
return NULL;
} else {
- assert(0 && "Unhandled constant type");
+ llvm_unreachable("Unhandled constant type");
return NULL;
}
} else {
@@ -534,7 +535,7 @@
return Ice::InstAlloca::create(Func, ByteCount, Align, Dest);
}
- Ice::Inst *convertUnreachableInstruction(const UnreachableInst *Inst) {
+ Ice::Inst *convertUnreachableInstruction(const UnreachableInst * /*Inst*/) {
return Ice::InstUnreachable::create(Func);
}
@@ -576,12 +577,35 @@
clEnumValN(Ice::IceV_Timing, "time", "Pass timing details"),
clEnumValN(Ice::IceV_All, "all", "Use all verbose options"),
clEnumValN(Ice::IceV_None, "none", "No verbosity"), clEnumValEnd));
+static cl::opt<Ice::TargetArch> TargetArch(
+ "target", cl::desc("Target architecture:"), cl::init(Ice::Target_X8632),
+ cl::values(
+ clEnumValN(Ice::Target_X8632, "x8632", "x86-32"),
+ clEnumValN(Ice::Target_X8632, "x86-32", "x86-32 (same as x8632)"),
+ clEnumValN(Ice::Target_X8632, "x86_32", "x86-32 (same as x8632)"),
+ clEnumValN(Ice::Target_X8664, "x8664", "x86-64"),
+ clEnumValN(Ice::Target_X8664, "x86-64", "x86-64 (same as x8664)"),
+ clEnumValN(Ice::Target_X8664, "x86_64", "x86-64 (same as x8664)"),
+ clEnumValN(Ice::Target_ARM32, "arm", "arm32"),
+ clEnumValN(Ice::Target_ARM32, "arm32", "arm32 (same as arm)"),
+ clEnumValN(Ice::Target_ARM64, "arm64", "arm64"), clEnumValEnd));
+static cl::opt<Ice::OptLevel>
+OptLevel(cl::desc("Optimization level"), cl::init(Ice::Opt_m1),
+ cl::value_desc("level"),
+ cl::values(clEnumValN(Ice::Opt_m1, "Om1", "-1"),
+ clEnumValN(Ice::Opt_m1, "O-1", "-1"),
+ clEnumValN(Ice::Opt_0, "O0", "0"),
+ clEnumValN(Ice::Opt_1, "O1", "1"),
+ clEnumValN(Ice::Opt_2, "O2", "2"), clEnumValEnd));
static cl::opt<std::string> IRFilename(cl::Positional, cl::desc("<IR file>"),
cl::init("-"));
static cl::opt<std::string> OutputFilename("o",
cl::desc("Override output filename"),
cl::init("-"),
cl::value_desc("filename"));
+static cl::opt<std::string> LogFilename("log", cl::desc("Set log filename"),
+ cl::init("-"),
+ cl::value_desc("filename"));
static cl::opt<std::string>
TestPrefix("prefix", cl::desc("Prepend a prefix to symbol names for testing"),
cl::init(""), cl::value_desc("prefix"));
@@ -605,6 +629,8 @@
cl::init(LLVMFormat));
int main(int argc, char **argv) {
+ int ExitStatus = 0;
+
cl::ParseCommandLineOptions(argc, argv);
// Parse the input LLVM IR file into a module.
@@ -637,8 +663,14 @@
raw_os_ostream *Os =
new raw_os_ostream(OutputFilename == "-" ? std::cout : Ofs);
Os->SetUnbuffered();
+ std::ofstream Lfs;
+ if (LogFilename != "-") {
+ Lfs.open(LogFilename.c_str(), std::ofstream::out);
+ }
+ raw_os_ostream *Ls = new raw_os_ostream(LogFilename == "-" ? std::cout : Lfs);
+ Ls->SetUnbuffered();
- Ice::GlobalContext Ctx(Os, Os, VMask, TestPrefix);
+ Ice::GlobalContext Ctx(Ls, Os, VMask, TargetArch, OptLevel, TestPrefix);
for (Module::const_iterator I = Mod->begin(), E = Mod->end(); I != E; ++I) {
if (I->empty())
@@ -658,8 +690,28 @@
if (DisableTranslation) {
Func->dump();
+ } else {
+ Ice::Timer TTranslate;
+ Func->translate();
+ if (SubzeroTimingEnabled) {
+ std::cerr << "[Subzero timing] Translate function "
+ << Func->getFunctionName() << ": "
+ << TTranslate.getElapsedSec() << " sec\n";
+ }
+ if (Func->hasError()) {
+ errs() << "ICE translation error: " << Func->getError() << "\n";
+ ExitStatus = 1;
+ }
+
+ Ice::Timer TEmit;
+ Func->emit();
+ if (SubzeroTimingEnabled) {
+ std::cerr << "[Subzero timing] Emit function "
+ << Func->getFunctionName() << ": " << TEmit.getElapsedSec()
+ << " sec\n";
+ }
}
}
- return 0;
+ return ExitStatus;
}