cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 2 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 3 | /*--------------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 4 | /*--- begin guest_ppc_toIR.c ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 5 | /*--------------------------------------------------------------------*/ |
| 6 | |
| 7 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 8 | This file is part of Valgrind, a dynamic binary instrumentation |
| 9 | framework. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 10 | |
sewardj | 89ae847 | 2013-10-18 14:12:58 +0000 | [diff] [blame] | 11 | Copyright (C) 2004-2013 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 12 | info@open-works.net |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 13 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 14 | This program is free software; you can redistribute it and/or |
| 15 | modify it under the terms of the GNU General Public License as |
| 16 | published by the Free Software Foundation; either version 2 of the |
| 17 | License, or (at your option) any later version. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 19 | This program is distributed in the hope that it will be useful, but |
| 20 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 22 | General Public License for more details. |
| 23 | |
| 24 | You should have received a copy of the GNU General Public License |
| 25 | along with this program; if not, write to the Free Software |
| 26 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 27 | 02110-1301, USA. |
| 28 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 29 | The GNU General Public License is contained in the file COPYING. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 30 | |
| 31 | Neither the names of the U.S. Department of Energy nor the |
| 32 | University of California nor the names of its contributors may be |
| 33 | used to endorse or promote products derived from this software |
| 34 | without prior written permission. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 35 | */ |
| 36 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 37 | /* TODO 18/Nov/05: |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 38 | |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 39 | Spot rld... cases which are simply left/right shifts and emit |
| 40 | Shl64/Shr64 accordingly. |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 41 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 42 | Altivec |
| 43 | - datastream insns |
| 44 | - lvxl,stvxl: load/store with 'least recently used' hint |
| 45 | - vexptefp, vlogefp |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 46 | |
| 47 | LIMITATIONS: |
| 48 | |
| 49 | Various, including: |
| 50 | |
| 51 | - Some invalid forms of lswi and lswx are accepted when they should |
| 52 | not be. |
| 53 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 54 | - Floating Point: |
| 55 | - All exceptions disabled in FPSCR |
| 56 | - condition codes not set in FPSCR |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 57 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 58 | - Altivec floating point: |
| 59 | - vmaddfp, vnmsubfp |
| 60 | Because we're using Java/IEEE mode (FPSCR[NJ]), rather than the |
| 61 | system default of Non-Java mode, we get some small errors |
| 62 | (lowest bit only). |
| 63 | This is because Non-Java mode brutally hacks denormalised results |
| 64 | to zero, whereas we keep maximum accuracy. However, using |
| 65 | Non-Java mode would give us more inaccuracy, as our intermediate |
| 66 | results would then be zeroed, too. |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 67 | |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 68 | - AbiHints for the stack red zone are only emitted for |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 69 | unconditional calls and returns (bl, blr). They should also be |
| 70 | emitted for conditional calls and returns, but we don't have a |
| 71 | way to express that right now. Ah well. |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 72 | |
| 73 | - Uses of Iop_{Add,Sub,Mul}32Fx4: the backend (host_ppc_isel.c) |
| 74 | ignores the rounding mode, and generates code that assumes |
| 75 | round-to-nearest. This means V will compute incorrect results |
| 76 | for uses of these IROps when the rounding mode (first) arg is |
| 77 | not mkU32(Irrm_NEAREST). |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 78 | */ |
| 79 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 80 | /* "Special" instructions. |
| 81 | |
sewardj | 09e88d1 | 2006-01-27 16:05:49 +0000 | [diff] [blame] | 82 | This instruction decoder can decode four special instructions |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 83 | which mean nothing natively (are no-ops as far as regs/mem are |
| 84 | concerned) but have meaning for supporting Valgrind. A special |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 85 | instruction is flagged by a 16-byte preamble: |
| 86 | |
sewardj | 2171afd | 2014-02-10 12:27:29 +0000 | [diff] [blame] | 87 | 32-bit mode: 5400183E 5400683E 5400E83E 5400983E |
| 88 | (rlwinm 0,0,3,0,31; rlwinm 0,0,13,0,31; |
| 89 | rlwinm 0,0,29,0,31; rlwinm 0,0,19,0,31) |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 90 | |
| 91 | 64-bit mode: 78001800 78006800 7800E802 78009802 |
| 92 | (rotldi 0,0,3; rotldi 0,0,13; |
| 93 | rotldi 0,0,61; rotldi 0,0,51) |
| 94 | |
| 95 | Following that, one of the following 3 are allowed |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 96 | (standard interpretation in parentheses): |
| 97 | |
| 98 | 7C210B78 (or 1,1,1) %R3 = client_request ( %R4 ) |
| 99 | 7C421378 (or 2,2,2) %R3 = guest_NRADDR |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 100 | 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R11 Big endian |
| 101 | 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R12 Little endian |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 102 | 7C842378 (or 4,4,4) %R3 = guest_NRADDR_GPR2 |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 103 | 7CA52B78 (or 5,5,5) IR injection |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 104 | |
| 105 | Any other bytes following the 16-byte preamble are illegal and |
| 106 | constitute a failure in instruction decoding. This all assumes |
| 107 | that the preamble will never occur except in specific code |
| 108 | fragments designed for Valgrind to catch. |
| 109 | */ |
| 110 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 111 | /* Little Endian notes */ |
| 112 | /* |
| 113 | * Vector operations in little Endian mode behave in non-obvious ways at times. |
| 114 | * Below is an attempt at explaining this. |
| 115 | * |
| 116 | * LE/BE vector example |
| 117 | * With a vector of unsigned ints declared as follows: |
| 118 | * vector unsigned int vec_inA = |
| 119 | { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }; |
| 120 | * The '0x11111111' word is word zero in both LE and BE format. But the |
| 121 | * loaded vector register will have word zero on the far left in BE mode and |
| 122 | * on the far right in LE mode. The lvx and stvx instructions work naturally |
| 123 | * for whatever endianness is in effect. For example, in LE mode, the stvx |
| 124 | * stores word zero (far right word) of the vector at the lowest memory |
| 125 | * address of the EA; in BE mode, stvx still stores word zero at the lowest |
| 126 | * memory address, but with word zero interpreted as the one at the far left |
| 127 | * of the register. |
| 128 | * |
| 129 | * The lxvd2x and stxvd2x instructions are not so well suited for LE mode. |
| 130 | * When the compiler generates an lxvd2x instruction to load the |
| 131 | * above-declared vector of unsigned integers, it loads the vector as two |
| 132 | * double words, but they are in BE word-wise format. To put the vector in |
| 133 | * the right order for LE, the compiler also generates an xxswapd after the |
| 134 | * load, which puts it in proper LE format. Similarly, the stxvd2x |
| 135 | * instruction has a BE bias, storing the vector in BE word-wise format. But |
| 136 | * the compiler also generates an xxswapd prior to the store, thus ensuring |
| 137 | * the vector is stored in memory in the correct LE order. |
| 138 | * |
| 139 | * Vector-flavored Iops, such Iop_V128Hito64, reference the hi and lo parts |
| 140 | * of a double words and words within a vector. Because of the reverse order |
| 141 | * of numbering for LE as described above, the high part refers to word 1 in |
| 142 | * LE format. When input data is saved to a guest state vector register |
| 143 | * (e.g., via Iop_64HLtoV128), it is first saved to memory and then the |
| 144 | * register is loaded via PPCInstr_AvLdSt, which does an lvx instruction. |
| 145 | * The saving of the data to memory must be done in proper LE order. For the |
| 146 | * inverse operation of extracting data from a vector register (e.g., |
| 147 | * Iop_V128Hito64), the register is first saved (by PPCInstr_AvLdSt resulting |
| 148 | * in stvx), and then integer registers are loaded from the memory location |
| 149 | * from where the vector register was saved. Again, this must be done in |
| 150 | * proper LE order. So for these various vector Iops, we have LE-specific |
| 151 | * code in host_ppc_isel.c |
| 152 | * |
| 153 | * Another unique behavior of vectors in LE mode is with the vector scalar |
| 154 | * (VSX) operations that operate on "double word 0" of the source register, |
| 155 | * storing the result in "double word 0" of the output vector register. For |
| 156 | * these operations, "double word 0" is interpreted as "high half of the |
| 157 | * register" (i.e, the part on the left side). |
| 158 | * |
| 159 | */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 160 | /* Translates PPC32/64 code to IR. */ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 161 | |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 162 | /* References |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 163 | |
| 164 | #define PPC32 |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 165 | "PowerPC Microprocessor Family: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 166 | The Programming Environments Manual for 32-Bit Microprocessors" |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 167 | 02/21/2000 |
| 168 | http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF778525699600719DF2 |
| 169 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 170 | #define PPC64 |
| 171 | "PowerPC Microprocessor Family: |
| 172 | Programming Environments Manual for 64-Bit Microprocessors" |
| 173 | 06/10/2003 |
| 174 | http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/F7E732FF811F783187256FDD004D3797 |
| 175 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 176 | #define AV |
| 177 | "PowerPC Microprocessor Family: |
| 178 | AltiVec(TM) Technology Programming Environments Manual" |
| 179 | 07/10/2003 |
| 180 | http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/FBFA164F824370F987256D6A006F424D |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 181 | */ |
| 182 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 183 | #include "libvex_basictypes.h" |
| 184 | #include "libvex_ir.h" |
| 185 | #include "libvex.h" |
florian | 58a637b | 2012-09-30 20:30:17 +0000 | [diff] [blame] | 186 | #include "libvex_emnote.h" |
cerion | 1515db9 | 2005-01-25 17:21:23 +0000 | [diff] [blame] | 187 | #include "libvex_guest_ppc32.h" |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 188 | #include "libvex_guest_ppc64.h" |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 189 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 190 | #include "main_util.h" |
| 191 | #include "main_globals.h" |
| 192 | #include "guest_generic_bb_to_IR.h" |
| 193 | #include "guest_ppc_defs.h" |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 194 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 195 | /*------------------------------------------------------------*/ |
| 196 | /*--- Globals ---*/ |
| 197 | /*------------------------------------------------------------*/ |
| 198 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 199 | /* These are set at the start of the translation of an insn, right |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 200 | down in disInstr_PPC, so that we don't have to pass them around |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 201 | endlessly. They are all constant during the translation of any |
| 202 | given insn. */ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 203 | |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 204 | /* We need to know this to do sub-register accesses correctly. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 205 | static VexEndness host_endness; |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 206 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 207 | /* Pointer to the guest code area. */ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 208 | static UChar* guest_code; |
| 209 | |
| 210 | /* The guest address corresponding to guest_code[0]. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 211 | static Addr64 guest_CIA_bbstart; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 212 | |
sewardj | 01a9e80 | 2005-02-01 20:46:00 +0000 | [diff] [blame] | 213 | /* The guest address for the instruction currently being |
| 214 | translated. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 215 | static Addr64 guest_CIA_curr_instr; |
sewardj | 01a9e80 | 2005-02-01 20:46:00 +0000 | [diff] [blame] | 216 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 217 | /* The IRSB* into which we're generating code. */ |
| 218 | static IRSB* irsb; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 219 | |
sewardj | 5df65bb | 2005-11-29 14:47:04 +0000 | [diff] [blame] | 220 | /* Is our guest binary 32 or 64bit? Set at each call to |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 221 | disInstr_PPC below. */ |
sewardj | 5df65bb | 2005-11-29 14:47:04 +0000 | [diff] [blame] | 222 | static Bool mode64 = False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 223 | |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 224 | // Given a pointer to a function as obtained by "& functionname" in C, |
| 225 | // produce a pointer to the actual entry point for the function. For |
| 226 | // most platforms it's the identity function. Unfortunately, on |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 227 | // ppc64-linux it isn't (sigh) and ditto for ppc32-aix5 and |
| 228 | // ppc64-aix5. |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 229 | static void* fnptr_to_fnentry( VexAbiInfo* vbi, void* f ) |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 230 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 231 | if (vbi->host_ppc_calls_use_fndescrs) { |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 232 | /* f is a pointer to a 3-word function descriptor, of which the |
| 233 | first word is the entry address. */ |
| 234 | /* note, this is correct even with cross-jitting, since this is |
| 235 | purely a host issue, not a guest one. */ |
| 236 | HWord* fdescr = (HWord*)f; |
| 237 | return (void*)(fdescr[0]); |
| 238 | } else { |
| 239 | /* Simple; "& f" points directly at the code for f. */ |
| 240 | return f; |
| 241 | } |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 242 | } |
| 243 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 244 | #define SIGN_BIT 0x8000000000000000ULL |
| 245 | #define SIGN_MASK 0x7fffffffffffffffULL |
| 246 | #define SIGN_BIT32 0x80000000 |
| 247 | #define SIGN_MASK32 0x7fffffff |
| 248 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 249 | |
| 250 | /*------------------------------------------------------------*/ |
| 251 | /*--- Debugging output ---*/ |
| 252 | /*------------------------------------------------------------*/ |
| 253 | |
| 254 | #define DIP(format, args...) \ |
| 255 | if (vex_traceflags & VEX_TRACE_FE) \ |
| 256 | vex_printf(format, ## args) |
| 257 | |
| 258 | #define DIS(buf, format, args...) \ |
| 259 | if (vex_traceflags & VEX_TRACE_FE) \ |
| 260 | vex_sprintf(buf, format, ## args) |
| 261 | |
| 262 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 263 | /*------------------------------------------------------------*/ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 264 | /*--- Offsets of various parts of the ppc32/64 guest state ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 265 | /*------------------------------------------------------------*/ |
| 266 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 267 | #define offsetofPPCGuestState(_x) \ |
| 268 | (mode64 ? offsetof(VexGuestPPC64State, _x) : \ |
| 269 | offsetof(VexGuestPPC32State, _x)) |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 270 | |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 271 | #define OFFB_CIA offsetofPPCGuestState(guest_CIA) |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 272 | #define OFFB_IP_AT_SYSCALL offsetofPPCGuestState(guest_IP_AT_SYSCALL) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 273 | #define OFFB_SPRG3_RO offsetofPPCGuestState(guest_SPRG3_RO) |
| 274 | #define OFFB_LR offsetofPPCGuestState(guest_LR) |
| 275 | #define OFFB_CTR offsetofPPCGuestState(guest_CTR) |
| 276 | #define OFFB_XER_SO offsetofPPCGuestState(guest_XER_SO) |
| 277 | #define OFFB_XER_OV offsetofPPCGuestState(guest_XER_OV) |
| 278 | #define OFFB_XER_CA offsetofPPCGuestState(guest_XER_CA) |
| 279 | #define OFFB_XER_BC offsetofPPCGuestState(guest_XER_BC) |
| 280 | #define OFFB_FPROUND offsetofPPCGuestState(guest_FPROUND) |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 281 | #define OFFB_DFPROUND offsetofPPCGuestState(guest_DFPROUND) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 282 | #define OFFB_VRSAVE offsetofPPCGuestState(guest_VRSAVE) |
| 283 | #define OFFB_VSCR offsetofPPCGuestState(guest_VSCR) |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 284 | #define OFFB_EMNOTE offsetofPPCGuestState(guest_EMNOTE) |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 285 | #define OFFB_CMSTART offsetofPPCGuestState(guest_CMSTART) |
| 286 | #define OFFB_CMLEN offsetofPPCGuestState(guest_CMLEN) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 287 | #define OFFB_NRADDR offsetofPPCGuestState(guest_NRADDR) |
| 288 | #define OFFB_NRADDR_GPR2 offsetofPPCGuestState(guest_NRADDR_GPR2) |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 289 | #define OFFB_TFHAR offsetofPPCGuestState(guest_TFHAR) |
| 290 | #define OFFB_TEXASR offsetofPPCGuestState(guest_TEXASR) |
| 291 | #define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR) |
sewardj | 5ff11dd | 2006-01-20 14:19:25 +0000 | [diff] [blame] | 292 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 293 | |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 294 | /*------------------------------------------------------------*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 295 | /*--- Extract instruction fields --- */ |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 296 | /*------------------------------------------------------------*/ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 297 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 298 | /* Extract field from insn, given idx (zero = lsb) and field length */ |
| 299 | #define IFIELD( insn, idx, len ) ((insn >> idx) & ((1<<len)-1)) |
| 300 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 301 | /* Extract primary opcode, instr[31:26] */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 302 | static UChar ifieldOPC( UInt instr ) { |
| 303 | return toUChar( IFIELD( instr, 26, 6 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 304 | } |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 305 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 306 | /* Extract 10-bit secondary opcode, instr[10:1] */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 307 | static UInt ifieldOPClo10 ( UInt instr) { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 308 | return IFIELD( instr, 1, 10 ); |
| 309 | } |
| 310 | |
| 311 | /* Extract 9-bit secondary opcode, instr[9:1] */ |
| 312 | static UInt ifieldOPClo9 ( UInt instr) { |
| 313 | return IFIELD( instr, 1, 9 ); |
| 314 | } |
| 315 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 316 | /* Extract 8-bit secondary opcode, instr[8:1] */ |
| 317 | static UInt ifieldOPClo8 ( UInt instr) { |
| 318 | return IFIELD( instr, 1, 8 ); |
| 319 | } |
| 320 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 321 | /* Extract 5-bit secondary opcode, instr[5:1] */ |
| 322 | static UInt ifieldOPClo5 ( UInt instr) { |
| 323 | return IFIELD( instr, 1, 5 ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 324 | } |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 325 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 326 | /* Extract RD (destination register) field, instr[25:21] */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 327 | static UChar ifieldRegDS( UInt instr ) { |
| 328 | return toUChar( IFIELD( instr, 21, 5 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 329 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 330 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 331 | /* Extract XT (destination register) field, instr[0,25:21] */ |
| 332 | static UChar ifieldRegXT ( UInt instr ) |
| 333 | { |
| 334 | UChar upper_bit = toUChar (IFIELD (instr, 0, 1)); |
| 335 | UChar lower_bits = toUChar (IFIELD (instr, 21, 5)); |
| 336 | return (upper_bit << 5) | lower_bits; |
| 337 | } |
| 338 | |
| 339 | /* Extract XS (store source register) field, instr[0,25:21] */ |
| 340 | static inline UChar ifieldRegXS ( UInt instr ) |
| 341 | { |
| 342 | return ifieldRegXT ( instr ); |
| 343 | } |
| 344 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 345 | /* Extract RA (1st source register) field, instr[20:16] */ |
| 346 | static UChar ifieldRegA ( UInt instr ) { |
| 347 | return toUChar( IFIELD( instr, 16, 5 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 348 | } |
| 349 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 350 | /* Extract XA (1st source register) field, instr[2,20:16] */ |
| 351 | static UChar ifieldRegXA ( UInt instr ) |
| 352 | { |
| 353 | UChar upper_bit = toUChar (IFIELD (instr, 2, 1)); |
| 354 | UChar lower_bits = toUChar (IFIELD (instr, 16, 5)); |
| 355 | return (upper_bit << 5) | lower_bits; |
| 356 | } |
| 357 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 358 | /* Extract RB (2nd source register) field, instr[15:11] */ |
| 359 | static UChar ifieldRegB ( UInt instr ) { |
| 360 | return toUChar( IFIELD( instr, 11, 5 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 361 | } |
| 362 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 363 | /* Extract XB (2nd source register) field, instr[1,15:11] */ |
| 364 | static UChar ifieldRegXB ( UInt instr ) |
| 365 | { |
| 366 | UChar upper_bit = toUChar (IFIELD (instr, 1, 1)); |
| 367 | UChar lower_bits = toUChar (IFIELD (instr, 11, 5)); |
| 368 | return (upper_bit << 5) | lower_bits; |
| 369 | } |
| 370 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 371 | /* Extract RC (3rd source register) field, instr[10:6] */ |
| 372 | static UChar ifieldRegC ( UInt instr ) { |
| 373 | return toUChar( IFIELD( instr, 6, 5 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 374 | } |
| 375 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 376 | /* Extract XC (3rd source register) field, instr[3,10:6] */ |
| 377 | static UChar ifieldRegXC ( UInt instr ) |
| 378 | { |
| 379 | UChar upper_bit = toUChar (IFIELD (instr, 3, 1)); |
| 380 | UChar lower_bits = toUChar (IFIELD (instr, 6, 5)); |
| 381 | return (upper_bit << 5) | lower_bits; |
| 382 | } |
| 383 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 384 | /* Extract bit 10, instr[10] */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 385 | static UChar ifieldBIT10 ( UInt instr ) { |
| 386 | return toUChar( IFIELD( instr, 10, 1 ) ); |
| 387 | } |
| 388 | |
| 389 | /* Extract 2nd lowest bit, instr[1] */ |
| 390 | static UChar ifieldBIT1 ( UInt instr ) { |
| 391 | return toUChar( IFIELD( instr, 1, 1 ) ); |
| 392 | } |
| 393 | |
| 394 | /* Extract lowest bit, instr[0] */ |
| 395 | static UChar ifieldBIT0 ( UInt instr ) { |
| 396 | return toUChar( instr & 0x1 ); |
| 397 | } |
| 398 | |
| 399 | /* Extract unsigned bottom half, instr[15:0] */ |
| 400 | static UInt ifieldUIMM16 ( UInt instr ) { |
| 401 | return instr & 0xFFFF; |
| 402 | } |
| 403 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 404 | /* Extract unsigned bottom 26 bits, instr[25:0] */ |
| 405 | static UInt ifieldUIMM26 ( UInt instr ) { |
| 406 | return instr & 0x3FFFFFF; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 407 | } |
| 408 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 409 | /* Extract DM field, instr[9:8] */ |
| 410 | static UChar ifieldDM ( UInt instr ) { |
| 411 | return toUChar( IFIELD( instr, 8, 2 ) ); |
| 412 | } |
| 413 | |
| 414 | /* Extract SHW field, instr[9:8] */ |
| 415 | static inline UChar ifieldSHW ( UInt instr ) |
| 416 | { |
| 417 | return ifieldDM ( instr ); |
| 418 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 419 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 420 | /*------------------------------------------------------------*/ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 421 | /*--- Guest-state identifiers ---*/ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 422 | /*------------------------------------------------------------*/ |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 423 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 424 | typedef enum { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 425 | PPC_GST_CIA, // Current Instruction Address |
| 426 | PPC_GST_LR, // Link Register |
| 427 | PPC_GST_CTR, // Count Register |
| 428 | PPC_GST_XER, // Overflow, carry flags, byte count |
| 429 | PPC_GST_CR, // Condition Register |
| 430 | PPC_GST_FPSCR, // Floating Point Status/Control Register |
| 431 | PPC_GST_VRSAVE, // Vector Save/Restore Register |
| 432 | PPC_GST_VSCR, // Vector Status and Control Register |
| 433 | PPC_GST_EMWARN, // Emulation warnings |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 434 | PPC_GST_CMSTART,// For icbi: start of area to invalidate |
| 435 | PPC_GST_CMLEN, // For icbi: length of area to invalidate |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 436 | PPC_GST_IP_AT_SYSCALL, // the CIA of the most recently executed SC insn |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 437 | PPC_GST_SPRG3_RO, // SPRG3 |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 438 | PPC_GST_TFHAR, // Transactional Failure Handler Address Register |
| 439 | PPC_GST_TFIAR, // Transactional Failure Instruction Address Register |
| 440 | PPC_GST_TEXASR, // Transactional EXception And Summary Register |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 441 | PPC_GST_MAX |
| 442 | } PPC_GST; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 443 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 444 | #define MASK_FPSCR_RN 0x3ULL // Binary floating point rounding mode |
| 445 | #define MASK_FPSCR_DRN 0x700000000ULL // Decimal floating point rounding mode |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 446 | #define MASK_VSCR_VALID 0x00010001 |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 447 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 448 | |
| 449 | /*------------------------------------------------------------*/ |
| 450 | /*--- FP Helpers ---*/ |
| 451 | /*------------------------------------------------------------*/ |
| 452 | |
sewardj | 2ead522 | 2005-11-23 03:53:45 +0000 | [diff] [blame] | 453 | /* Produce the 32-bit pattern corresponding to the supplied |
| 454 | float. */ |
| 455 | static UInt float_to_bits ( Float f ) |
| 456 | { |
| 457 | union { UInt i; Float f; } u; |
| 458 | vassert(4 == sizeof(UInt)); |
| 459 | vassert(4 == sizeof(Float)); |
| 460 | vassert(4 == sizeof(u)); |
| 461 | u.f = f; |
| 462 | return u.i; |
| 463 | } |
| 464 | |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 465 | |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 466 | /*------------------------------------------------------------*/ |
| 467 | /*--- Misc Helpers ---*/ |
| 468 | /*------------------------------------------------------------*/ |
| 469 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 470 | /* Generate mask with 1's from 'begin' through 'end', |
| 471 | wrapping if begin > end. |
| 472 | begin->end works from right to left, 0=lsb |
| 473 | */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 474 | static UInt MASK32( UInt begin, UInt end ) |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 475 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 476 | UInt m1, m2, mask; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 477 | vassert(begin < 32); |
| 478 | vassert(end < 32); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 479 | m1 = ((UInt)(-1)) << begin; |
| 480 | m2 = ((UInt)(-1)) << end << 1; |
| 481 | mask = m1 ^ m2; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 482 | if (begin > end) mask = ~mask; // wrap mask |
| 483 | return mask; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 484 | } |
| 485 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 486 | static ULong MASK64( UInt begin, UInt end ) |
| 487 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 488 | ULong m1, m2, mask; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 489 | vassert(begin < 64); |
| 490 | vassert(end < 64); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 491 | m1 = ((ULong)(-1)) << begin; |
| 492 | m2 = ((ULong)(-1)) << end << 1; |
| 493 | mask = m1 ^ m2; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 494 | if (begin > end) mask = ~mask; // wrap mask |
| 495 | return mask; |
| 496 | } |
| 497 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 498 | static Addr64 nextInsnAddr( void ) |
| 499 | { |
| 500 | return guest_CIA_curr_instr + 4; |
| 501 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 502 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 503 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 504 | /*------------------------------------------------------------*/ |
| 505 | /*--- Helper bits and pieces for deconstructing the ---*/ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 506 | /*--- ppc32/64 insn stream. ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 507 | /*------------------------------------------------------------*/ |
| 508 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 509 | /* Add a statement to the list held by "irsb". */ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 510 | static void stmt ( IRStmt* st ) |
| 511 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 512 | addStmtToIRSB( irsb, st ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 513 | } |
| 514 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 515 | /* Generate a new temporary of the given type. */ |
| 516 | static IRTemp newTemp ( IRType ty ) |
| 517 | { |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 518 | vassert(isPlausibleIRType(ty)); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 519 | return newIRTemp( irsb->tyenv, ty ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 520 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 521 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 522 | /* Various simple conversions */ |
| 523 | |
| 524 | static UChar extend_s_5to8 ( UChar x ) |
| 525 | { |
| 526 | return toUChar((((Int)x) << 27) >> 27); |
| 527 | } |
| 528 | |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 529 | static UInt extend_s_8to32( UChar x ) |
| 530 | { |
| 531 | return (UInt)((((Int)x) << 24) >> 24); |
| 532 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 533 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 534 | static UInt extend_s_16to32 ( UInt x ) |
| 535 | { |
| 536 | return (UInt)((((Int)x) << 16) >> 16); |
| 537 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 538 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 539 | static ULong extend_s_16to64 ( UInt x ) |
| 540 | { |
| 541 | return (ULong)((((Long)x) << 48) >> 48); |
| 542 | } |
| 543 | |
| 544 | static ULong extend_s_26to64 ( UInt x ) |
| 545 | { |
| 546 | return (ULong)((((Long)x) << 38) >> 38); |
| 547 | } |
| 548 | |
| 549 | static ULong extend_s_32to64 ( UInt x ) |
| 550 | { |
| 551 | return (ULong)((((Long)x) << 32) >> 32); |
| 552 | } |
| 553 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 554 | /* Do a proper-endian load of a 32-bit word, regardless of the endianness |
sewardj | 684aa95 | 2005-01-30 12:52:14 +0000 | [diff] [blame] | 555 | of the underlying host. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 556 | static UInt getUIntPPCendianly ( UChar* p ) |
sewardj | 684aa95 | 2005-01-30 12:52:14 +0000 | [diff] [blame] | 557 | { |
cerion | cf00446 | 2005-01-31 15:24:55 +0000 | [diff] [blame] | 558 | UInt w = 0; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 559 | if (host_endness == VexEndnessBE) { |
| 560 | w = (w << 8) | p[0]; |
| 561 | w = (w << 8) | p[1]; |
| 562 | w = (w << 8) | p[2]; |
| 563 | w = (w << 8) | p[3]; |
| 564 | } else { |
| 565 | w = (w << 8) | p[3]; |
| 566 | w = (w << 8) | p[2]; |
| 567 | w = (w << 8) | p[1]; |
| 568 | w = (w << 8) | p[0]; |
| 569 | } |
sewardj | 684aa95 | 2005-01-30 12:52:14 +0000 | [diff] [blame] | 570 | return w; |
| 571 | } |
| 572 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 573 | |
| 574 | /*------------------------------------------------------------*/ |
| 575 | /*--- Helpers for constructing IR. ---*/ |
| 576 | /*------------------------------------------------------------*/ |
| 577 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 578 | static void assign ( IRTemp dst, IRExpr* e ) |
| 579 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 580 | stmt( IRStmt_WrTmp(dst, e) ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 581 | } |
| 582 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 583 | /* This generates a normal (non store-conditional) store. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 584 | static void store ( IRExpr* addr, IRExpr* data ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 585 | { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 586 | IRType tyA = typeOfIRExpr(irsb->tyenv, addr); |
| 587 | vassert(tyA == Ity_I32 || tyA == Ity_I64); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 588 | |
| 589 | if (host_endness == VexEndnessBE) |
| 590 | stmt( IRStmt_Store(Iend_BE, addr, data) ); |
| 591 | else |
| 592 | stmt( IRStmt_Store(Iend_LE, addr, data) ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 593 | } |
| 594 | |
| 595 | static IRExpr* unop ( IROp op, IRExpr* a ) |
| 596 | { |
| 597 | return IRExpr_Unop(op, a); |
| 598 | } |
| 599 | |
| 600 | static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) |
| 601 | { |
| 602 | return IRExpr_Binop(op, a1, a2); |
| 603 | } |
| 604 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 605 | static IRExpr* triop ( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3 ) |
| 606 | { |
| 607 | return IRExpr_Triop(op, a1, a2, a3); |
| 608 | } |
| 609 | |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 610 | static IRExpr* qop ( IROp op, IRExpr* a1, IRExpr* a2, |
| 611 | IRExpr* a3, IRExpr* a4 ) |
| 612 | { |
| 613 | return IRExpr_Qop(op, a1, a2, a3, a4); |
| 614 | } |
| 615 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 616 | static IRExpr* mkexpr ( IRTemp tmp ) |
| 617 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 618 | return IRExpr_RdTmp(tmp); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 619 | } |
| 620 | |
sewardj | 684c037 | 2005-02-07 02:33:58 +0000 | [diff] [blame] | 621 | static IRExpr* mkU8 ( UChar i ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 622 | { |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 623 | return IRExpr_Const(IRConst_U8(i)); |
| 624 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 625 | |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 626 | static IRExpr* mkU16 ( UInt i ) |
| 627 | { |
| 628 | return IRExpr_Const(IRConst_U16(i)); |
| 629 | } |
| 630 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 631 | static IRExpr* mkU32 ( UInt i ) |
| 632 | { |
| 633 | return IRExpr_Const(IRConst_U32(i)); |
| 634 | } |
| 635 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 636 | static IRExpr* mkU64 ( ULong i ) |
| 637 | { |
| 638 | return IRExpr_Const(IRConst_U64(i)); |
| 639 | } |
| 640 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 641 | static IRExpr* mkV128 ( UShort i ) |
| 642 | { |
| 643 | vassert(i == 0 || i == 0xffff); |
| 644 | return IRExpr_Const(IRConst_V128(i)); |
| 645 | } |
| 646 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 647 | /* This generates a normal (non load-linked) load. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 648 | static IRExpr* load ( IRType ty, IRExpr* addr ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 649 | { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 650 | if (host_endness == VexEndnessBE) |
| 651 | return IRExpr_Load(Iend_BE, ty, addr); |
| 652 | else |
| 653 | return IRExpr_Load(Iend_LE, ty, addr); |
| 654 | } |
| 655 | |
| 656 | static IRStmt* stmt_load ( IRTemp result, |
| 657 | IRExpr* addr, IRExpr* storedata ) |
| 658 | { |
| 659 | if (host_endness == VexEndnessBE) |
| 660 | return IRStmt_LLSC(Iend_BE, result, addr, storedata); |
| 661 | else |
| 662 | return IRStmt_LLSC(Iend_LE, result, addr, storedata); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 663 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 664 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 665 | static IRExpr* mkOR1 ( IRExpr* arg1, IRExpr* arg2 ) |
| 666 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 667 | vassert(typeOfIRExpr(irsb->tyenv, arg1) == Ity_I1); |
| 668 | vassert(typeOfIRExpr(irsb->tyenv, arg2) == Ity_I1); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 669 | return unop(Iop_32to1, binop(Iop_Or32, unop(Iop_1Uto32, arg1), |
| 670 | unop(Iop_1Uto32, arg2))); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | static IRExpr* mkAND1 ( IRExpr* arg1, IRExpr* arg2 ) |
| 674 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 675 | vassert(typeOfIRExpr(irsb->tyenv, arg1) == Ity_I1); |
| 676 | vassert(typeOfIRExpr(irsb->tyenv, arg2) == Ity_I1); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 677 | return unop(Iop_32to1, binop(Iop_And32, unop(Iop_1Uto32, arg1), |
| 678 | unop(Iop_1Uto32, arg2))); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 679 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 680 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 681 | /* expand V128_8Ux16 to 2x V128_16Ux8's */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 682 | static void expand8Ux16( IRExpr* vIn, |
| 683 | /*OUTs*/ IRTemp* vEvn, IRTemp* vOdd ) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 684 | { |
| 685 | IRTemp ones8x16 = newTemp(Ity_V128); |
| 686 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 687 | vassert(typeOfIRExpr(irsb->tyenv, vIn) == Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 688 | vassert(vEvn && *vEvn == IRTemp_INVALID); |
| 689 | vassert(vOdd && *vOdd == IRTemp_INVALID); |
| 690 | *vEvn = newTemp(Ity_V128); |
| 691 | *vOdd = newTemp(Ity_V128); |
| 692 | |
| 693 | assign( ones8x16, unop(Iop_Dup8x16, mkU8(0x1)) ); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 694 | assign( *vOdd, binop(Iop_MullEven8Ux16, mkexpr(ones8x16), vIn) ); |
| 695 | assign( *vEvn, binop(Iop_MullEven8Ux16, mkexpr(ones8x16), |
| 696 | binop(Iop_ShrV128, vIn, mkU8(8))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 697 | } |
| 698 | |
| 699 | /* expand V128_8Sx16 to 2x V128_16Sx8's */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 700 | static void expand8Sx16( IRExpr* vIn, |
| 701 | /*OUTs*/ IRTemp* vEvn, IRTemp* vOdd ) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 702 | { |
| 703 | IRTemp ones8x16 = newTemp(Ity_V128); |
| 704 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 705 | vassert(typeOfIRExpr(irsb->tyenv, vIn) == Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 706 | vassert(vEvn && *vEvn == IRTemp_INVALID); |
| 707 | vassert(vOdd && *vOdd == IRTemp_INVALID); |
| 708 | *vEvn = newTemp(Ity_V128); |
| 709 | *vOdd = newTemp(Ity_V128); |
| 710 | |
| 711 | assign( ones8x16, unop(Iop_Dup8x16, mkU8(0x1)) ); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 712 | assign( *vOdd, binop(Iop_MullEven8Sx16, mkexpr(ones8x16), vIn) ); |
| 713 | assign( *vEvn, binop(Iop_MullEven8Sx16, mkexpr(ones8x16), |
| 714 | binop(Iop_ShrV128, vIn, mkU8(8))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 715 | } |
| 716 | |
| 717 | /* expand V128_16Uto8 to 2x V128_32Ux4's */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 718 | static void expand16Ux8( IRExpr* vIn, |
| 719 | /*OUTs*/ IRTemp* vEvn, IRTemp* vOdd ) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 720 | { |
| 721 | IRTemp ones16x8 = newTemp(Ity_V128); |
| 722 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 723 | vassert(typeOfIRExpr(irsb->tyenv, vIn) == Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 724 | vassert(vEvn && *vEvn == IRTemp_INVALID); |
| 725 | vassert(vOdd && *vOdd == IRTemp_INVALID); |
| 726 | *vEvn = newTemp(Ity_V128); |
| 727 | *vOdd = newTemp(Ity_V128); |
| 728 | |
| 729 | assign( ones16x8, unop(Iop_Dup16x8, mkU16(0x1)) ); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 730 | assign( *vOdd, binop(Iop_MullEven16Ux8, mkexpr(ones16x8), vIn) ); |
| 731 | assign( *vEvn, binop(Iop_MullEven16Ux8, mkexpr(ones16x8), |
| 732 | binop(Iop_ShrV128, vIn, mkU8(16))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 733 | } |
| 734 | |
| 735 | /* expand V128_16Sto8 to 2x V128_32Sx4's */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 736 | static void expand16Sx8( IRExpr* vIn, |
| 737 | /*OUTs*/ IRTemp* vEvn, IRTemp* vOdd ) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 738 | { |
| 739 | IRTemp ones16x8 = newTemp(Ity_V128); |
| 740 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 741 | vassert(typeOfIRExpr(irsb->tyenv, vIn) == Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 742 | vassert(vEvn && *vEvn == IRTemp_INVALID); |
| 743 | vassert(vOdd && *vOdd == IRTemp_INVALID); |
| 744 | *vEvn = newTemp(Ity_V128); |
| 745 | *vOdd = newTemp(Ity_V128); |
| 746 | |
| 747 | assign( ones16x8, unop(Iop_Dup16x8, mkU16(0x1)) ); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 748 | assign( *vOdd, binop(Iop_MullEven16Sx8, mkexpr(ones16x8), vIn) ); |
| 749 | assign( *vEvn, binop(Iop_MullEven16Sx8, mkexpr(ones16x8), |
| 750 | binop(Iop_ShrV128, vIn, mkU8(16))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 751 | } |
| 752 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 753 | /* break V128 to 4xF64's*/ |
| 754 | static void breakV128to4xF64( IRExpr* t128, |
| 755 | /*OUTs*/ |
| 756 | IRTemp* t3, IRTemp* t2, |
| 757 | IRTemp* t1, IRTemp* t0 ) |
| 758 | { |
| 759 | IRTemp hi64 = newTemp(Ity_I64); |
| 760 | IRTemp lo64 = newTemp(Ity_I64); |
| 761 | |
| 762 | vassert(typeOfIRExpr(irsb->tyenv, t128) == Ity_V128); |
| 763 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 764 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 765 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 766 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 767 | *t0 = newTemp(Ity_F64); |
| 768 | *t1 = newTemp(Ity_F64); |
| 769 | *t2 = newTemp(Ity_F64); |
| 770 | *t3 = newTemp(Ity_F64); |
| 771 | |
| 772 | assign( hi64, unop(Iop_V128HIto64, t128) ); |
| 773 | assign( lo64, unop(Iop_V128to64, t128) ); |
| 774 | assign( *t3, |
| 775 | unop( Iop_F32toF64, |
| 776 | unop( Iop_ReinterpI32asF32, |
| 777 | unop( Iop_64HIto32, mkexpr( hi64 ) ) ) ) ); |
| 778 | assign( *t2, |
| 779 | unop( Iop_F32toF64, |
| 780 | unop( Iop_ReinterpI32asF32, unop( Iop_64to32, mkexpr( hi64 ) ) ) ) ); |
| 781 | assign( *t1, |
| 782 | unop( Iop_F32toF64, |
| 783 | unop( Iop_ReinterpI32asF32, |
| 784 | unop( Iop_64HIto32, mkexpr( lo64 ) ) ) ) ); |
| 785 | assign( *t0, |
| 786 | unop( Iop_F32toF64, |
| 787 | unop( Iop_ReinterpI32asF32, unop( Iop_64to32, mkexpr( lo64 ) ) ) ) ); |
| 788 | } |
| 789 | |
| 790 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 791 | /* break V128 to 4xI32's, then sign-extend to I64's */ |
| 792 | static void breakV128to4x64S( IRExpr* t128, |
| 793 | /*OUTs*/ |
| 794 | IRTemp* t3, IRTemp* t2, |
| 795 | IRTemp* t1, IRTemp* t0 ) |
| 796 | { |
| 797 | IRTemp hi64 = newTemp(Ity_I64); |
| 798 | IRTemp lo64 = newTemp(Ity_I64); |
| 799 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 800 | vassert(typeOfIRExpr(irsb->tyenv, t128) == Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 801 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 802 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 803 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 804 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 805 | *t0 = newTemp(Ity_I64); |
| 806 | *t1 = newTemp(Ity_I64); |
| 807 | *t2 = newTemp(Ity_I64); |
| 808 | *t3 = newTemp(Ity_I64); |
| 809 | |
| 810 | assign( hi64, unop(Iop_V128HIto64, t128) ); |
| 811 | assign( lo64, unop(Iop_V128to64, t128) ); |
| 812 | assign( *t3, unop(Iop_32Sto64, unop(Iop_64HIto32, mkexpr(hi64))) ); |
| 813 | assign( *t2, unop(Iop_32Sto64, unop(Iop_64to32, mkexpr(hi64))) ); |
| 814 | assign( *t1, unop(Iop_32Sto64, unop(Iop_64HIto32, mkexpr(lo64))) ); |
| 815 | assign( *t0, unop(Iop_32Sto64, unop(Iop_64to32, mkexpr(lo64))) ); |
| 816 | } |
| 817 | |
| 818 | /* break V128 to 4xI32's, then zero-extend to I64's */ |
| 819 | static void breakV128to4x64U ( IRExpr* t128, |
| 820 | /*OUTs*/ |
| 821 | IRTemp* t3, IRTemp* t2, |
| 822 | IRTemp* t1, IRTemp* t0 ) |
| 823 | { |
| 824 | IRTemp hi64 = newTemp(Ity_I64); |
| 825 | IRTemp lo64 = newTemp(Ity_I64); |
| 826 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 827 | vassert(typeOfIRExpr(irsb->tyenv, t128) == Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 828 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 829 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 830 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 831 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 832 | *t0 = newTemp(Ity_I64); |
| 833 | *t1 = newTemp(Ity_I64); |
| 834 | *t2 = newTemp(Ity_I64); |
| 835 | *t3 = newTemp(Ity_I64); |
| 836 | |
| 837 | assign( hi64, unop(Iop_V128HIto64, t128) ); |
| 838 | assign( lo64, unop(Iop_V128to64, t128) ); |
| 839 | assign( *t3, unop(Iop_32Uto64, unop(Iop_64HIto32, mkexpr(hi64))) ); |
| 840 | assign( *t2, unop(Iop_32Uto64, unop(Iop_64to32, mkexpr(hi64))) ); |
| 841 | assign( *t1, unop(Iop_32Uto64, unop(Iop_64HIto32, mkexpr(lo64))) ); |
| 842 | assign( *t0, unop(Iop_32Uto64, unop(Iop_64to32, mkexpr(lo64))) ); |
| 843 | } |
| 844 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 845 | static void breakV128to4x32( IRExpr* t128, |
| 846 | /*OUTs*/ |
| 847 | IRTemp* t3, IRTemp* t2, |
| 848 | IRTemp* t1, IRTemp* t0 ) |
| 849 | { |
| 850 | IRTemp hi64 = newTemp(Ity_I64); |
| 851 | IRTemp lo64 = newTemp(Ity_I64); |
| 852 | |
| 853 | vassert(typeOfIRExpr(irsb->tyenv, t128) == Ity_V128); |
| 854 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 855 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 856 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 857 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 858 | *t0 = newTemp(Ity_I32); |
| 859 | *t1 = newTemp(Ity_I32); |
| 860 | *t2 = newTemp(Ity_I32); |
| 861 | *t3 = newTemp(Ity_I32); |
| 862 | |
| 863 | assign( hi64, unop(Iop_V128HIto64, t128) ); |
| 864 | assign( lo64, unop(Iop_V128to64, t128) ); |
| 865 | assign( *t3, unop(Iop_64HIto32, mkexpr(hi64)) ); |
| 866 | assign( *t2, unop(Iop_64to32, mkexpr(hi64)) ); |
| 867 | assign( *t1, unop(Iop_64HIto32, mkexpr(lo64)) ); |
| 868 | assign( *t0, unop(Iop_64to32, mkexpr(lo64)) ); |
| 869 | } |
| 870 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 871 | static IRExpr* mkV128from32( IRTemp t3, IRTemp t2, |
| 872 | IRTemp t1, IRTemp t0 ) |
| 873 | { |
| 874 | return |
| 875 | binop( Iop_64HLtoV128, |
| 876 | binop(Iop_32HLto64, mkexpr(t3), mkexpr(t2)), |
| 877 | binop(Iop_32HLto64, mkexpr(t1), mkexpr(t0)) |
| 878 | ); |
| 879 | } |
| 880 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 881 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 882 | /* Signed saturating narrow 64S to 32 */ |
| 883 | static IRExpr* mkQNarrow64Sto32 ( IRExpr* t64 ) |
| 884 | { |
| 885 | IRTemp hi32 = newTemp(Ity_I32); |
| 886 | IRTemp lo32 = newTemp(Ity_I32); |
| 887 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 888 | vassert(typeOfIRExpr(irsb->tyenv, t64) == Ity_I64); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 889 | |
| 890 | assign( hi32, unop(Iop_64HIto32, t64)); |
| 891 | assign( lo32, unop(Iop_64to32, t64)); |
| 892 | |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 893 | return IRExpr_ITE( |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 894 | /* if (hi32 == (lo32 >>s 31)) */ |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 895 | binop(Iop_CmpEQ32, mkexpr(hi32), |
| 896 | binop( Iop_Sar32, mkexpr(lo32), mkU8(31))), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 897 | /* then: within signed-32 range: lo half good enough */ |
| 898 | mkexpr(lo32), |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 899 | /* else: sign dep saturate: 1->0x80000000, 0->0x7FFFFFFF */ |
| 900 | binop(Iop_Add32, mkU32(0x7FFFFFFF), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 901 | binop(Iop_Shr32, mkexpr(hi32), mkU8(31)))); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 902 | } |
| 903 | |
| 904 | /* Unsigned saturating narrow 64S to 32 */ |
| 905 | static IRExpr* mkQNarrow64Uto32 ( IRExpr* t64 ) |
| 906 | { |
| 907 | IRTemp hi32 = newTemp(Ity_I32); |
| 908 | IRTemp lo32 = newTemp(Ity_I32); |
| 909 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 910 | vassert(typeOfIRExpr(irsb->tyenv, t64) == Ity_I64); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 911 | |
| 912 | assign( hi32, unop(Iop_64HIto32, t64)); |
| 913 | assign( lo32, unop(Iop_64to32, t64)); |
| 914 | |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 915 | return IRExpr_ITE( |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 916 | /* if (top 32 bits of t64 are 0) */ |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 917 | binop(Iop_CmpEQ32, mkexpr(hi32), mkU32(0)), |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 918 | /* then: within unsigned-32 range: lo half good enough */ |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 919 | mkexpr(lo32), |
| 920 | /* else: positive saturate -> 0xFFFFFFFF */ |
| 921 | mkU32(0xFFFFFFFF)); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 922 | } |
| 923 | |
| 924 | /* Signed saturate narrow 64->32, combining to V128 */ |
| 925 | static IRExpr* mkV128from4x64S ( IRExpr* t3, IRExpr* t2, |
| 926 | IRExpr* t1, IRExpr* t0 ) |
| 927 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 928 | vassert(typeOfIRExpr(irsb->tyenv, t3) == Ity_I64); |
| 929 | vassert(typeOfIRExpr(irsb->tyenv, t2) == Ity_I64); |
| 930 | vassert(typeOfIRExpr(irsb->tyenv, t1) == Ity_I64); |
| 931 | vassert(typeOfIRExpr(irsb->tyenv, t0) == Ity_I64); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 932 | return binop(Iop_64HLtoV128, |
| 933 | binop(Iop_32HLto64, |
| 934 | mkQNarrow64Sto32( t3 ), |
| 935 | mkQNarrow64Sto32( t2 )), |
| 936 | binop(Iop_32HLto64, |
| 937 | mkQNarrow64Sto32( t1 ), |
| 938 | mkQNarrow64Sto32( t0 ))); |
| 939 | } |
| 940 | |
| 941 | /* Unsigned saturate narrow 64->32, combining to V128 */ |
| 942 | static IRExpr* mkV128from4x64U ( IRExpr* t3, IRExpr* t2, |
| 943 | IRExpr* t1, IRExpr* t0 ) |
| 944 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 945 | vassert(typeOfIRExpr(irsb->tyenv, t3) == Ity_I64); |
| 946 | vassert(typeOfIRExpr(irsb->tyenv, t2) == Ity_I64); |
| 947 | vassert(typeOfIRExpr(irsb->tyenv, t1) == Ity_I64); |
| 948 | vassert(typeOfIRExpr(irsb->tyenv, t0) == Ity_I64); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 949 | return binop(Iop_64HLtoV128, |
| 950 | binop(Iop_32HLto64, |
| 951 | mkQNarrow64Uto32( t3 ), |
| 952 | mkQNarrow64Uto32( t2 )), |
| 953 | binop(Iop_32HLto64, |
| 954 | mkQNarrow64Uto32( t1 ), |
| 955 | mkQNarrow64Uto32( t0 ))); |
| 956 | } |
| 957 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 958 | /* Simulate irops Iop_MullOdd*, since we don't have them */ |
| 959 | #define MK_Iop_MullOdd8Ux16( expr_vA, expr_vB ) \ |
| 960 | binop(Iop_MullEven8Ux16, \ |
| 961 | binop(Iop_ShrV128, expr_vA, mkU8(8)), \ |
| 962 | binop(Iop_ShrV128, expr_vB, mkU8(8))) |
| 963 | |
| 964 | #define MK_Iop_MullOdd8Sx16( expr_vA, expr_vB ) \ |
| 965 | binop(Iop_MullEven8Sx16, \ |
| 966 | binop(Iop_ShrV128, expr_vA, mkU8(8)), \ |
| 967 | binop(Iop_ShrV128, expr_vB, mkU8(8))) |
| 968 | |
| 969 | #define MK_Iop_MullOdd16Ux8( expr_vA, expr_vB ) \ |
| 970 | binop(Iop_MullEven16Ux8, \ |
| 971 | binop(Iop_ShrV128, expr_vA, mkU8(16)), \ |
| 972 | binop(Iop_ShrV128, expr_vB, mkU8(16))) |
| 973 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 974 | #define MK_Iop_MullOdd32Ux4( expr_vA, expr_vB ) \ |
| 975 | binop(Iop_MullEven32Ux4, \ |
| 976 | binop(Iop_ShrV128, expr_vA, mkU8(32)), \ |
| 977 | binop(Iop_ShrV128, expr_vB, mkU8(32))) |
| 978 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 979 | #define MK_Iop_MullOdd16Sx8( expr_vA, expr_vB ) \ |
| 980 | binop(Iop_MullEven16Sx8, \ |
| 981 | binop(Iop_ShrV128, expr_vA, mkU8(16)), \ |
| 982 | binop(Iop_ShrV128, expr_vB, mkU8(16))) |
| 983 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 984 | #define MK_Iop_MullOdd32Sx4( expr_vA, expr_vB ) \ |
| 985 | binop(Iop_MullEven32Sx4, \ |
| 986 | binop(Iop_ShrV128, expr_vA, mkU8(32)), \ |
| 987 | binop(Iop_ShrV128, expr_vB, mkU8(32))) |
| 988 | |
| 989 | |
cerion | 59b2c31 | 2005-12-17 11:28:53 +0000 | [diff] [blame] | 990 | static IRExpr* /* :: Ity_I64 */ mk64lo32Sto64 ( IRExpr* src ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 991 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 992 | vassert(typeOfIRExpr(irsb->tyenv, src) == Ity_I64); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 993 | return unop(Iop_32Sto64, unop(Iop_64to32, src)); |
| 994 | } |
| 995 | |
cerion | 59b2c31 | 2005-12-17 11:28:53 +0000 | [diff] [blame] | 996 | static IRExpr* /* :: Ity_I64 */ mk64lo32Uto64 ( IRExpr* src ) |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 997 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 998 | vassert(typeOfIRExpr(irsb->tyenv, src) == Ity_I64); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 999 | return unop(Iop_32Uto64, unop(Iop_64to32, src)); |
| 1000 | } |
| 1001 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1002 | static IROp mkSzOp ( IRType ty, IROp op8 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1003 | { |
| 1004 | Int adj; |
| 1005 | vassert(ty == Ity_I8 || ty == Ity_I16 || |
| 1006 | ty == Ity_I32 || ty == Ity_I64); |
| 1007 | vassert(op8 == Iop_Add8 || op8 == Iop_Sub8 || op8 == Iop_Mul8 || |
| 1008 | op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 || |
| 1009 | op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 || |
| 1010 | op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 || |
sewardj | eb17e49 | 2007-08-25 23:07:44 +0000 | [diff] [blame] | 1011 | op8 == Iop_Not8 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1012 | adj = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : (ty==Ity_I32 ? 2 : 3)); |
| 1013 | return adj + op8; |
| 1014 | } |
| 1015 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1016 | /* Make sure we get valid 32 and 64bit addresses */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1017 | static Addr64 mkSzAddr ( IRType ty, Addr64 addr ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1018 | { |
| 1019 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 1020 | return ( ty == Ity_I64 ? |
| 1021 | (Addr64)addr : |
| 1022 | (Addr64)extend_s_32to64( toUInt(addr) ) ); |
| 1023 | } |
| 1024 | |
| 1025 | /* sz, ULong -> IRExpr */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1026 | static IRExpr* mkSzImm ( IRType ty, ULong imm64 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1027 | { |
| 1028 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 1029 | return ty == Ity_I64 ? mkU64(imm64) : mkU32((UInt)imm64); |
| 1030 | } |
| 1031 | |
| 1032 | /* sz, ULong -> IRConst */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1033 | static IRConst* mkSzConst ( IRType ty, ULong imm64 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1034 | { |
| 1035 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 1036 | return ( ty == Ity_I64 ? |
| 1037 | IRConst_U64(imm64) : |
| 1038 | IRConst_U32((UInt)imm64) ); |
| 1039 | } |
| 1040 | |
| 1041 | /* Sign extend imm16 -> IRExpr* */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1042 | static IRExpr* mkSzExtendS16 ( IRType ty, UInt imm16 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1043 | { |
| 1044 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 1045 | return ( ty == Ity_I64 ? |
| 1046 | mkU64(extend_s_16to64(imm16)) : |
| 1047 | mkU32(extend_s_16to32(imm16)) ); |
| 1048 | } |
| 1049 | |
| 1050 | /* Sign extend imm32 -> IRExpr* */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1051 | static IRExpr* mkSzExtendS32 ( IRType ty, UInt imm32 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1052 | { |
| 1053 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 1054 | return ( ty == Ity_I64 ? |
| 1055 | mkU64(extend_s_32to64(imm32)) : |
| 1056 | mkU32(imm32) ); |
| 1057 | } |
| 1058 | |
| 1059 | /* IR narrows I32/I64 -> I8/I16/I32 */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1060 | static IRExpr* mkNarrowTo8 ( IRType ty, IRExpr* src ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1061 | { |
| 1062 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 1063 | return ty == Ity_I64 ? unop(Iop_64to8, src) : unop(Iop_32to8, src); |
| 1064 | } |
| 1065 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1066 | static IRExpr* mkNarrowTo16 ( IRType ty, IRExpr* src ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1067 | { |
| 1068 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 1069 | return ty == Ity_I64 ? unop(Iop_64to16, src) : unop(Iop_32to16, src); |
| 1070 | } |
| 1071 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1072 | static IRExpr* mkNarrowTo32 ( IRType ty, IRExpr* src ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1073 | { |
| 1074 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 1075 | return ty == Ity_I64 ? unop(Iop_64to32, src) : src; |
| 1076 | } |
| 1077 | |
| 1078 | /* Signed/Unsigned IR widens I8/I16/I32 -> I32/I64 */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1079 | static IRExpr* mkWidenFrom8 ( IRType ty, IRExpr* src, Bool sined ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1080 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1081 | IROp op; |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1082 | vassert(ty == Ity_I32 || ty == Ity_I64); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1083 | if (sined) op = (ty==Ity_I32) ? Iop_8Sto32 : Iop_8Sto64; |
| 1084 | else op = (ty==Ity_I32) ? Iop_8Uto32 : Iop_8Uto64; |
| 1085 | return unop(op, src); |
| 1086 | } |
| 1087 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1088 | static IRExpr* mkWidenFrom16 ( IRType ty, IRExpr* src, Bool sined ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1089 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1090 | IROp op; |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1091 | vassert(ty == Ity_I32 || ty == Ity_I64); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1092 | if (sined) op = (ty==Ity_I32) ? Iop_16Sto32 : Iop_16Sto64; |
| 1093 | else op = (ty==Ity_I32) ? Iop_16Uto32 : Iop_16Uto64; |
| 1094 | return unop(op, src); |
| 1095 | } |
| 1096 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1097 | static IRExpr* mkWidenFrom32 ( IRType ty, IRExpr* src, Bool sined ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1098 | { |
| 1099 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 1100 | if (ty == Ity_I32) |
| 1101 | return src; |
| 1102 | return (sined) ? unop(Iop_32Sto64, src) : unop(Iop_32Uto64, src); |
| 1103 | } |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 1104 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 1105 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1106 | static Int integerGuestRegOffset ( UInt archreg ) |
cerion | 45b70ff | 2005-01-31 17:03:25 +0000 | [diff] [blame] | 1107 | { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1108 | vassert(archreg < 32); |
| 1109 | |
| 1110 | // jrs: probably not necessary; only matters if we reference sub-parts |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1111 | // of the ppc registers, but that isn't the case |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1112 | // later: this might affect Altivec though? |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1113 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1114 | switch (archreg) { |
| 1115 | case 0: return offsetofPPCGuestState(guest_GPR0); |
| 1116 | case 1: return offsetofPPCGuestState(guest_GPR1); |
| 1117 | case 2: return offsetofPPCGuestState(guest_GPR2); |
| 1118 | case 3: return offsetofPPCGuestState(guest_GPR3); |
| 1119 | case 4: return offsetofPPCGuestState(guest_GPR4); |
| 1120 | case 5: return offsetofPPCGuestState(guest_GPR5); |
| 1121 | case 6: return offsetofPPCGuestState(guest_GPR6); |
| 1122 | case 7: return offsetofPPCGuestState(guest_GPR7); |
| 1123 | case 8: return offsetofPPCGuestState(guest_GPR8); |
| 1124 | case 9: return offsetofPPCGuestState(guest_GPR9); |
| 1125 | case 10: return offsetofPPCGuestState(guest_GPR10); |
| 1126 | case 11: return offsetofPPCGuestState(guest_GPR11); |
| 1127 | case 12: return offsetofPPCGuestState(guest_GPR12); |
| 1128 | case 13: return offsetofPPCGuestState(guest_GPR13); |
| 1129 | case 14: return offsetofPPCGuestState(guest_GPR14); |
| 1130 | case 15: return offsetofPPCGuestState(guest_GPR15); |
| 1131 | case 16: return offsetofPPCGuestState(guest_GPR16); |
| 1132 | case 17: return offsetofPPCGuestState(guest_GPR17); |
| 1133 | case 18: return offsetofPPCGuestState(guest_GPR18); |
| 1134 | case 19: return offsetofPPCGuestState(guest_GPR19); |
| 1135 | case 20: return offsetofPPCGuestState(guest_GPR20); |
| 1136 | case 21: return offsetofPPCGuestState(guest_GPR21); |
| 1137 | case 22: return offsetofPPCGuestState(guest_GPR22); |
| 1138 | case 23: return offsetofPPCGuestState(guest_GPR23); |
| 1139 | case 24: return offsetofPPCGuestState(guest_GPR24); |
| 1140 | case 25: return offsetofPPCGuestState(guest_GPR25); |
| 1141 | case 26: return offsetofPPCGuestState(guest_GPR26); |
| 1142 | case 27: return offsetofPPCGuestState(guest_GPR27); |
| 1143 | case 28: return offsetofPPCGuestState(guest_GPR28); |
| 1144 | case 29: return offsetofPPCGuestState(guest_GPR29); |
| 1145 | case 30: return offsetofPPCGuestState(guest_GPR30); |
| 1146 | case 31: return offsetofPPCGuestState(guest_GPR31); |
| 1147 | default: break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1148 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1149 | vpanic("integerGuestRegOffset(ppc,be)"); /*notreached*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1150 | } |
| 1151 | |
| 1152 | static IRExpr* getIReg ( UInt archreg ) |
| 1153 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1154 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1155 | vassert(archreg < 32); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1156 | return IRExpr_Get( integerGuestRegOffset(archreg), ty ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1157 | } |
| 1158 | |
| 1159 | /* Ditto, but write to a reg instead. */ |
| 1160 | static void putIReg ( UInt archreg, IRExpr* e ) |
| 1161 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1162 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1163 | vassert(archreg < 32); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1164 | vassert(typeOfIRExpr(irsb->tyenv, e) == ty ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1165 | stmt( IRStmt_Put(integerGuestRegOffset(archreg), e) ); |
| 1166 | } |
| 1167 | |
| 1168 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1169 | /* Floating point egisters are mapped to VSX registers[0..31]. */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1170 | static Int floatGuestRegOffset ( UInt archreg ) |
| 1171 | { |
| 1172 | vassert(archreg < 32); |
| 1173 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 1174 | if (host_endness == VexEndnessLE) { |
| 1175 | switch (archreg) { |
| 1176 | case 0: return offsetofPPCGuestState(guest_VSR0 + 8); |
| 1177 | case 1: return offsetofPPCGuestState(guest_VSR1 + 8); |
| 1178 | case 2: return offsetofPPCGuestState(guest_VSR2 + 8); |
| 1179 | case 3: return offsetofPPCGuestState(guest_VSR3 + 8); |
| 1180 | case 4: return offsetofPPCGuestState(guest_VSR4 + 8); |
| 1181 | case 5: return offsetofPPCGuestState(guest_VSR5 + 8); |
| 1182 | case 6: return offsetofPPCGuestState(guest_VSR6 + 8); |
| 1183 | case 7: return offsetofPPCGuestState(guest_VSR7 + 8); |
| 1184 | case 8: return offsetofPPCGuestState(guest_VSR8 + 8); |
| 1185 | case 9: return offsetofPPCGuestState(guest_VSR9 + 8); |
| 1186 | case 10: return offsetofPPCGuestState(guest_VSR10 + 8); |
| 1187 | case 11: return offsetofPPCGuestState(guest_VSR11 + 8); |
| 1188 | case 12: return offsetofPPCGuestState(guest_VSR12 + 8); |
| 1189 | case 13: return offsetofPPCGuestState(guest_VSR13 + 8); |
| 1190 | case 14: return offsetofPPCGuestState(guest_VSR14 + 8); |
| 1191 | case 15: return offsetofPPCGuestState(guest_VSR15 + 8); |
| 1192 | case 16: return offsetofPPCGuestState(guest_VSR16 + 8); |
| 1193 | case 17: return offsetofPPCGuestState(guest_VSR17 + 8); |
| 1194 | case 18: return offsetofPPCGuestState(guest_VSR18 + 8); |
| 1195 | case 19: return offsetofPPCGuestState(guest_VSR19 + 8); |
| 1196 | case 20: return offsetofPPCGuestState(guest_VSR20 + 8); |
| 1197 | case 21: return offsetofPPCGuestState(guest_VSR21 + 8); |
| 1198 | case 22: return offsetofPPCGuestState(guest_VSR22 + 8); |
| 1199 | case 23: return offsetofPPCGuestState(guest_VSR23 + 8); |
| 1200 | case 24: return offsetofPPCGuestState(guest_VSR24 + 8); |
| 1201 | case 25: return offsetofPPCGuestState(guest_VSR25 + 8); |
| 1202 | case 26: return offsetofPPCGuestState(guest_VSR26 + 8); |
| 1203 | case 27: return offsetofPPCGuestState(guest_VSR27 + 8); |
| 1204 | case 28: return offsetofPPCGuestState(guest_VSR28 + 8); |
| 1205 | case 29: return offsetofPPCGuestState(guest_VSR29 + 8); |
| 1206 | case 30: return offsetofPPCGuestState(guest_VSR30 + 8); |
| 1207 | case 31: return offsetofPPCGuestState(guest_VSR31 + 8); |
| 1208 | default: break; |
| 1209 | } |
| 1210 | } else { |
| 1211 | switch (archreg) { |
| 1212 | case 0: return offsetofPPCGuestState(guest_VSR0); |
| 1213 | case 1: return offsetofPPCGuestState(guest_VSR1); |
| 1214 | case 2: return offsetofPPCGuestState(guest_VSR2); |
| 1215 | case 3: return offsetofPPCGuestState(guest_VSR3); |
| 1216 | case 4: return offsetofPPCGuestState(guest_VSR4); |
| 1217 | case 5: return offsetofPPCGuestState(guest_VSR5); |
| 1218 | case 6: return offsetofPPCGuestState(guest_VSR6); |
| 1219 | case 7: return offsetofPPCGuestState(guest_VSR7); |
| 1220 | case 8: return offsetofPPCGuestState(guest_VSR8); |
| 1221 | case 9: return offsetofPPCGuestState(guest_VSR9); |
| 1222 | case 10: return offsetofPPCGuestState(guest_VSR10); |
| 1223 | case 11: return offsetofPPCGuestState(guest_VSR11); |
| 1224 | case 12: return offsetofPPCGuestState(guest_VSR12); |
| 1225 | case 13: return offsetofPPCGuestState(guest_VSR13); |
| 1226 | case 14: return offsetofPPCGuestState(guest_VSR14); |
| 1227 | case 15: return offsetofPPCGuestState(guest_VSR15); |
| 1228 | case 16: return offsetofPPCGuestState(guest_VSR16); |
| 1229 | case 17: return offsetofPPCGuestState(guest_VSR17); |
| 1230 | case 18: return offsetofPPCGuestState(guest_VSR18); |
| 1231 | case 19: return offsetofPPCGuestState(guest_VSR19); |
| 1232 | case 20: return offsetofPPCGuestState(guest_VSR20); |
| 1233 | case 21: return offsetofPPCGuestState(guest_VSR21); |
| 1234 | case 22: return offsetofPPCGuestState(guest_VSR22); |
| 1235 | case 23: return offsetofPPCGuestState(guest_VSR23); |
| 1236 | case 24: return offsetofPPCGuestState(guest_VSR24); |
| 1237 | case 25: return offsetofPPCGuestState(guest_VSR25); |
| 1238 | case 26: return offsetofPPCGuestState(guest_VSR26); |
| 1239 | case 27: return offsetofPPCGuestState(guest_VSR27); |
| 1240 | case 28: return offsetofPPCGuestState(guest_VSR28); |
| 1241 | case 29: return offsetofPPCGuestState(guest_VSR29); |
| 1242 | case 30: return offsetofPPCGuestState(guest_VSR30); |
| 1243 | case 31: return offsetofPPCGuestState(guest_VSR31); |
| 1244 | default: break; |
| 1245 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1246 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1247 | vpanic("floatGuestRegOffset(ppc)"); /*notreached*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1248 | } |
| 1249 | |
| 1250 | static IRExpr* getFReg ( UInt archreg ) |
| 1251 | { |
| 1252 | vassert(archreg < 32); |
| 1253 | return IRExpr_Get( floatGuestRegOffset(archreg), Ity_F64 ); |
| 1254 | } |
| 1255 | |
| 1256 | /* Ditto, but write to a reg instead. */ |
| 1257 | static void putFReg ( UInt archreg, IRExpr* e ) |
| 1258 | { |
| 1259 | vassert(archreg < 32); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1260 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1261 | stmt( IRStmt_Put(floatGuestRegOffset(archreg), e) ); |
| 1262 | } |
| 1263 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1264 | /* get Decimal float value. Note, they share floating point register file. */ |
| 1265 | static IRExpr* getDReg(UInt archreg) { |
| 1266 | IRExpr *e; |
| 1267 | vassert( archreg < 32 ); |
| 1268 | e = IRExpr_Get( floatGuestRegOffset( archreg ), Ity_D64 ); |
| 1269 | return e; |
| 1270 | } |
carll | f704eb2 | 2013-01-21 18:12:31 +0000 | [diff] [blame] | 1271 | static IRExpr* getDReg32(UInt archreg) { |
| 1272 | IRExpr *e; |
| 1273 | vassert( archreg < 32 ); |
| 1274 | e = IRExpr_Get( floatGuestRegOffset( archreg ), Ity_D32 ); |
| 1275 | return e; |
| 1276 | } |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1277 | |
| 1278 | /* Read a floating point register pair and combine their contents into a |
| 1279 | 128-bit value */ |
| 1280 | static IRExpr *getDReg_pair(UInt archreg) { |
| 1281 | IRExpr *high = getDReg( archreg ); |
| 1282 | IRExpr *low = getDReg( archreg + 1 ); |
| 1283 | |
| 1284 | return binop( Iop_D64HLtoD128, high, low ); |
| 1285 | } |
| 1286 | |
| 1287 | /* Ditto, but write to a reg instead. */ |
carll | f704eb2 | 2013-01-21 18:12:31 +0000 | [diff] [blame] | 1288 | static void putDReg32(UInt archreg, IRExpr* e) { |
| 1289 | vassert( archreg < 32 ); |
| 1290 | vassert( typeOfIRExpr(irsb->tyenv, e) == Ity_D32 ); |
| 1291 | stmt( IRStmt_Put( floatGuestRegOffset( archreg ), e ) ); |
| 1292 | } |
| 1293 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1294 | static void putDReg(UInt archreg, IRExpr* e) { |
| 1295 | vassert( archreg < 32 ); |
| 1296 | vassert( typeOfIRExpr(irsb->tyenv, e) == Ity_D64 ); |
| 1297 | stmt( IRStmt_Put( floatGuestRegOffset( archreg ), e ) ); |
| 1298 | } |
| 1299 | |
| 1300 | /* Write a 128-bit floating point value into a register pair. */ |
| 1301 | static void putDReg_pair(UInt archreg, IRExpr *e) { |
| 1302 | IRTemp low = newTemp( Ity_D64 ); |
| 1303 | IRTemp high = newTemp( Ity_D64 ); |
| 1304 | |
| 1305 | vassert( archreg < 32 ); |
| 1306 | vassert( typeOfIRExpr(irsb->tyenv, e) == Ity_D128 ); |
| 1307 | |
| 1308 | assign( low, unop( Iop_D128LOtoD64, e ) ); |
| 1309 | assign( high, unop( Iop_D128HItoD64, e ) ); |
| 1310 | |
| 1311 | stmt( IRStmt_Put( floatGuestRegOffset( archreg ), mkexpr( high ) ) ); |
| 1312 | stmt( IRStmt_Put( floatGuestRegOffset( archreg + 1 ), mkexpr( low ) ) ); |
| 1313 | } |
| 1314 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1315 | static Int vsxGuestRegOffset ( UInt archreg ) |
| 1316 | { |
| 1317 | vassert(archreg < 64); |
| 1318 | switch (archreg) { |
| 1319 | case 0: return offsetofPPCGuestState(guest_VSR0); |
| 1320 | case 1: return offsetofPPCGuestState(guest_VSR1); |
| 1321 | case 2: return offsetofPPCGuestState(guest_VSR2); |
| 1322 | case 3: return offsetofPPCGuestState(guest_VSR3); |
| 1323 | case 4: return offsetofPPCGuestState(guest_VSR4); |
| 1324 | case 5: return offsetofPPCGuestState(guest_VSR5); |
| 1325 | case 6: return offsetofPPCGuestState(guest_VSR6); |
| 1326 | case 7: return offsetofPPCGuestState(guest_VSR7); |
| 1327 | case 8: return offsetofPPCGuestState(guest_VSR8); |
| 1328 | case 9: return offsetofPPCGuestState(guest_VSR9); |
| 1329 | case 10: return offsetofPPCGuestState(guest_VSR10); |
| 1330 | case 11: return offsetofPPCGuestState(guest_VSR11); |
| 1331 | case 12: return offsetofPPCGuestState(guest_VSR12); |
| 1332 | case 13: return offsetofPPCGuestState(guest_VSR13); |
| 1333 | case 14: return offsetofPPCGuestState(guest_VSR14); |
| 1334 | case 15: return offsetofPPCGuestState(guest_VSR15); |
| 1335 | case 16: return offsetofPPCGuestState(guest_VSR16); |
| 1336 | case 17: return offsetofPPCGuestState(guest_VSR17); |
| 1337 | case 18: return offsetofPPCGuestState(guest_VSR18); |
| 1338 | case 19: return offsetofPPCGuestState(guest_VSR19); |
| 1339 | case 20: return offsetofPPCGuestState(guest_VSR20); |
| 1340 | case 21: return offsetofPPCGuestState(guest_VSR21); |
| 1341 | case 22: return offsetofPPCGuestState(guest_VSR22); |
| 1342 | case 23: return offsetofPPCGuestState(guest_VSR23); |
| 1343 | case 24: return offsetofPPCGuestState(guest_VSR24); |
| 1344 | case 25: return offsetofPPCGuestState(guest_VSR25); |
| 1345 | case 26: return offsetofPPCGuestState(guest_VSR26); |
| 1346 | case 27: return offsetofPPCGuestState(guest_VSR27); |
| 1347 | case 28: return offsetofPPCGuestState(guest_VSR28); |
| 1348 | case 29: return offsetofPPCGuestState(guest_VSR29); |
| 1349 | case 30: return offsetofPPCGuestState(guest_VSR30); |
| 1350 | case 31: return offsetofPPCGuestState(guest_VSR31); |
| 1351 | case 32: return offsetofPPCGuestState(guest_VSR32); |
| 1352 | case 33: return offsetofPPCGuestState(guest_VSR33); |
| 1353 | case 34: return offsetofPPCGuestState(guest_VSR34); |
| 1354 | case 35: return offsetofPPCGuestState(guest_VSR35); |
| 1355 | case 36: return offsetofPPCGuestState(guest_VSR36); |
| 1356 | case 37: return offsetofPPCGuestState(guest_VSR37); |
| 1357 | case 38: return offsetofPPCGuestState(guest_VSR38); |
| 1358 | case 39: return offsetofPPCGuestState(guest_VSR39); |
| 1359 | case 40: return offsetofPPCGuestState(guest_VSR40); |
| 1360 | case 41: return offsetofPPCGuestState(guest_VSR41); |
| 1361 | case 42: return offsetofPPCGuestState(guest_VSR42); |
| 1362 | case 43: return offsetofPPCGuestState(guest_VSR43); |
| 1363 | case 44: return offsetofPPCGuestState(guest_VSR44); |
| 1364 | case 45: return offsetofPPCGuestState(guest_VSR45); |
| 1365 | case 46: return offsetofPPCGuestState(guest_VSR46); |
| 1366 | case 47: return offsetofPPCGuestState(guest_VSR47); |
| 1367 | case 48: return offsetofPPCGuestState(guest_VSR48); |
| 1368 | case 49: return offsetofPPCGuestState(guest_VSR49); |
| 1369 | case 50: return offsetofPPCGuestState(guest_VSR50); |
| 1370 | case 51: return offsetofPPCGuestState(guest_VSR51); |
| 1371 | case 52: return offsetofPPCGuestState(guest_VSR52); |
| 1372 | case 53: return offsetofPPCGuestState(guest_VSR53); |
| 1373 | case 54: return offsetofPPCGuestState(guest_VSR54); |
| 1374 | case 55: return offsetofPPCGuestState(guest_VSR55); |
| 1375 | case 56: return offsetofPPCGuestState(guest_VSR56); |
| 1376 | case 57: return offsetofPPCGuestState(guest_VSR57); |
| 1377 | case 58: return offsetofPPCGuestState(guest_VSR58); |
| 1378 | case 59: return offsetofPPCGuestState(guest_VSR59); |
| 1379 | case 60: return offsetofPPCGuestState(guest_VSR60); |
| 1380 | case 61: return offsetofPPCGuestState(guest_VSR61); |
| 1381 | case 62: return offsetofPPCGuestState(guest_VSR62); |
| 1382 | case 63: return offsetofPPCGuestState(guest_VSR63); |
| 1383 | default: break; |
| 1384 | } |
| 1385 | vpanic("vsxGuestRegOffset(ppc)"); /*notreached*/ |
| 1386 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1387 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1388 | /* Vector registers are mapped to VSX registers[32..63]. */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1389 | static Int vectorGuestRegOffset ( UInt archreg ) |
| 1390 | { |
| 1391 | vassert(archreg < 32); |
| 1392 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1393 | switch (archreg) { |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1394 | case 0: return offsetofPPCGuestState(guest_VSR32); |
| 1395 | case 1: return offsetofPPCGuestState(guest_VSR33); |
| 1396 | case 2: return offsetofPPCGuestState(guest_VSR34); |
| 1397 | case 3: return offsetofPPCGuestState(guest_VSR35); |
| 1398 | case 4: return offsetofPPCGuestState(guest_VSR36); |
| 1399 | case 5: return offsetofPPCGuestState(guest_VSR37); |
| 1400 | case 6: return offsetofPPCGuestState(guest_VSR38); |
| 1401 | case 7: return offsetofPPCGuestState(guest_VSR39); |
| 1402 | case 8: return offsetofPPCGuestState(guest_VSR40); |
| 1403 | case 9: return offsetofPPCGuestState(guest_VSR41); |
| 1404 | case 10: return offsetofPPCGuestState(guest_VSR42); |
| 1405 | case 11: return offsetofPPCGuestState(guest_VSR43); |
| 1406 | case 12: return offsetofPPCGuestState(guest_VSR44); |
| 1407 | case 13: return offsetofPPCGuestState(guest_VSR45); |
| 1408 | case 14: return offsetofPPCGuestState(guest_VSR46); |
| 1409 | case 15: return offsetofPPCGuestState(guest_VSR47); |
| 1410 | case 16: return offsetofPPCGuestState(guest_VSR48); |
| 1411 | case 17: return offsetofPPCGuestState(guest_VSR49); |
| 1412 | case 18: return offsetofPPCGuestState(guest_VSR50); |
| 1413 | case 19: return offsetofPPCGuestState(guest_VSR51); |
| 1414 | case 20: return offsetofPPCGuestState(guest_VSR52); |
| 1415 | case 21: return offsetofPPCGuestState(guest_VSR53); |
| 1416 | case 22: return offsetofPPCGuestState(guest_VSR54); |
| 1417 | case 23: return offsetofPPCGuestState(guest_VSR55); |
| 1418 | case 24: return offsetofPPCGuestState(guest_VSR56); |
| 1419 | case 25: return offsetofPPCGuestState(guest_VSR57); |
| 1420 | case 26: return offsetofPPCGuestState(guest_VSR58); |
| 1421 | case 27: return offsetofPPCGuestState(guest_VSR59); |
| 1422 | case 28: return offsetofPPCGuestState(guest_VSR60); |
| 1423 | case 29: return offsetofPPCGuestState(guest_VSR61); |
| 1424 | case 30: return offsetofPPCGuestState(guest_VSR62); |
| 1425 | case 31: return offsetofPPCGuestState(guest_VSR63); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1426 | default: break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1427 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1428 | vpanic("vextorGuestRegOffset(ppc)"); /*notreached*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1429 | } |
| 1430 | |
| 1431 | static IRExpr* getVReg ( UInt archreg ) |
| 1432 | { |
| 1433 | vassert(archreg < 32); |
| 1434 | return IRExpr_Get( vectorGuestRegOffset(archreg), Ity_V128 ); |
| 1435 | } |
| 1436 | |
| 1437 | /* Ditto, but write to a reg instead. */ |
| 1438 | static void putVReg ( UInt archreg, IRExpr* e ) |
| 1439 | { |
| 1440 | vassert(archreg < 32); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1441 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1442 | stmt( IRStmt_Put(vectorGuestRegOffset(archreg), e) ); |
| 1443 | } |
| 1444 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1445 | /* Get contents of VSX guest register */ |
| 1446 | static IRExpr* getVSReg ( UInt archreg ) |
| 1447 | { |
| 1448 | vassert(archreg < 64); |
| 1449 | return IRExpr_Get( vsxGuestRegOffset(archreg), Ity_V128 ); |
| 1450 | } |
| 1451 | |
| 1452 | /* Ditto, but write to a VSX reg instead. */ |
| 1453 | static void putVSReg ( UInt archreg, IRExpr* e ) |
| 1454 | { |
| 1455 | vassert(archreg < 64); |
| 1456 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128); |
| 1457 | stmt( IRStmt_Put(vsxGuestRegOffset(archreg), e) ); |
| 1458 | } |
| 1459 | |
| 1460 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1461 | static Int guestCR321offset ( UInt cr ) |
| 1462 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1463 | switch (cr) { |
| 1464 | case 0: return offsetofPPCGuestState(guest_CR0_321 ); |
| 1465 | case 1: return offsetofPPCGuestState(guest_CR1_321 ); |
| 1466 | case 2: return offsetofPPCGuestState(guest_CR2_321 ); |
| 1467 | case 3: return offsetofPPCGuestState(guest_CR3_321 ); |
| 1468 | case 4: return offsetofPPCGuestState(guest_CR4_321 ); |
| 1469 | case 5: return offsetofPPCGuestState(guest_CR5_321 ); |
| 1470 | case 6: return offsetofPPCGuestState(guest_CR6_321 ); |
| 1471 | case 7: return offsetofPPCGuestState(guest_CR7_321 ); |
| 1472 | default: vpanic("guestCR321offset(ppc)"); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1473 | } |
| 1474 | } |
| 1475 | |
| 1476 | static Int guestCR0offset ( UInt cr ) |
| 1477 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1478 | switch (cr) { |
| 1479 | case 0: return offsetofPPCGuestState(guest_CR0_0 ); |
| 1480 | case 1: return offsetofPPCGuestState(guest_CR1_0 ); |
| 1481 | case 2: return offsetofPPCGuestState(guest_CR2_0 ); |
| 1482 | case 3: return offsetofPPCGuestState(guest_CR3_0 ); |
| 1483 | case 4: return offsetofPPCGuestState(guest_CR4_0 ); |
| 1484 | case 5: return offsetofPPCGuestState(guest_CR5_0 ); |
| 1485 | case 6: return offsetofPPCGuestState(guest_CR6_0 ); |
| 1486 | case 7: return offsetofPPCGuestState(guest_CR7_0 ); |
| 1487 | default: vpanic("guestCR3offset(ppc)"); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1488 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1489 | } |
| 1490 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1491 | typedef enum { |
| 1492 | _placeholder0, |
| 1493 | _placeholder1, |
| 1494 | _placeholder2, |
| 1495 | BYTE, |
| 1496 | HWORD, |
| 1497 | WORD, |
| 1498 | DWORD |
| 1499 | } _popcount_data_type; |
| 1500 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1501 | /* Generate an IR sequence to do a popcount operation on the supplied |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 1502 | IRTemp, and return a new IRTemp holding the result. 'ty' may be |
| 1503 | Ity_I32 or Ity_I64 only. */ |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1504 | static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, _popcount_data_type data_type ) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1505 | { |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1506 | /* Do count across 2^data_type bits, |
| 1507 | byte: data_type = 3 |
| 1508 | half word: data_type = 4 |
| 1509 | word: data_type = 5 |
| 1510 | double word: data_type = 6 (not supported for 32-bit type) |
| 1511 | */ |
| 1512 | Int shift[6]; |
| 1513 | _popcount_data_type idx, i; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 1514 | IRTemp mask[6]; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1515 | IRTemp old = IRTemp_INVALID; |
| 1516 | IRTemp nyu = IRTemp_INVALID; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1517 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 1518 | vassert(ty == Ity_I64 || ty == Ity_I32); |
| 1519 | |
| 1520 | if (ty == Ity_I32) { |
philippe | 738d9dd | 2012-07-06 21:56:53 +0000 | [diff] [blame] | 1521 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1522 | for (idx = 0; idx < WORD; idx++) { |
| 1523 | mask[idx] = newTemp(ty); |
| 1524 | shift[idx] = 1 << idx; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 1525 | } |
| 1526 | assign(mask[0], mkU32(0x55555555)); |
| 1527 | assign(mask[1], mkU32(0x33333333)); |
| 1528 | assign(mask[2], mkU32(0x0F0F0F0F)); |
| 1529 | assign(mask[3], mkU32(0x00FF00FF)); |
| 1530 | assign(mask[4], mkU32(0x0000FFFF)); |
| 1531 | old = src; |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1532 | for (i = 0; i < data_type; i++) { |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 1533 | nyu = newTemp(ty); |
| 1534 | assign(nyu, |
| 1535 | binop(Iop_Add32, |
| 1536 | binop(Iop_And32, |
| 1537 | mkexpr(old), |
| 1538 | mkexpr(mask[i])), |
| 1539 | binop(Iop_And32, |
| 1540 | binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])), |
| 1541 | mkexpr(mask[i])))); |
| 1542 | old = nyu; |
| 1543 | } |
| 1544 | return nyu; |
| 1545 | } |
philippe | 738d9dd | 2012-07-06 21:56:53 +0000 | [diff] [blame] | 1546 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1547 | // else, ty == Ity_I64 |
| 1548 | vassert(mode64); |
| 1549 | |
| 1550 | for (i = 0; i < DWORD; i++) { |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1551 | mask[i] = newTemp( Ity_I64 ); |
| 1552 | shift[i] = 1 << i; |
| 1553 | } |
| 1554 | assign( mask[0], mkU64( 0x5555555555555555ULL ) ); |
| 1555 | assign( mask[1], mkU64( 0x3333333333333333ULL ) ); |
| 1556 | assign( mask[2], mkU64( 0x0F0F0F0F0F0F0F0FULL ) ); |
| 1557 | assign( mask[3], mkU64( 0x00FF00FF00FF00FFULL ) ); |
| 1558 | assign( mask[4], mkU64( 0x0000FFFF0000FFFFULL ) ); |
| 1559 | assign( mask[5], mkU64( 0x00000000FFFFFFFFULL ) ); |
| 1560 | old = src; |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1561 | for (i = 0; i < data_type; i++) { |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1562 | nyu = newTemp( Ity_I64 ); |
| 1563 | assign( nyu, |
| 1564 | binop( Iop_Add64, |
| 1565 | binop( Iop_And64, mkexpr( old ), mkexpr( mask[i] ) ), |
| 1566 | binop( Iop_And64, |
| 1567 | binop( Iop_Shr64, mkexpr( old ), mkU8( shift[i] ) ), |
| 1568 | mkexpr( mask[i] ) ) ) ); |
| 1569 | old = nyu; |
| 1570 | } |
| 1571 | return nyu; |
| 1572 | } |
| 1573 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1574 | /* Special purpose population count function for |
| 1575 | * vpopcntd in 32-bit mode. |
| 1576 | */ |
| 1577 | static IRTemp gen_vpopcntd_mode32 ( IRTemp src1, IRTemp src2 ) |
| 1578 | { |
| 1579 | Int i, shift[6]; |
| 1580 | IRTemp mask[6]; |
| 1581 | IRTemp old = IRTemp_INVALID; |
| 1582 | IRTemp nyu1 = IRTemp_INVALID; |
| 1583 | IRTemp nyu2 = IRTemp_INVALID; |
| 1584 | IRTemp retval = newTemp(Ity_I64); |
| 1585 | |
| 1586 | vassert(!mode64); |
| 1587 | |
| 1588 | for (i = 0; i < WORD; i++) { |
| 1589 | mask[i] = newTemp(Ity_I32); |
| 1590 | shift[i] = 1 << i; |
| 1591 | } |
| 1592 | assign(mask[0], mkU32(0x55555555)); |
| 1593 | assign(mask[1], mkU32(0x33333333)); |
| 1594 | assign(mask[2], mkU32(0x0F0F0F0F)); |
| 1595 | assign(mask[3], mkU32(0x00FF00FF)); |
| 1596 | assign(mask[4], mkU32(0x0000FFFF)); |
| 1597 | old = src1; |
| 1598 | for (i = 0; i < WORD; i++) { |
| 1599 | nyu1 = newTemp(Ity_I32); |
| 1600 | assign(nyu1, |
| 1601 | binop(Iop_Add32, |
| 1602 | binop(Iop_And32, |
| 1603 | mkexpr(old), |
| 1604 | mkexpr(mask[i])), |
| 1605 | binop(Iop_And32, |
| 1606 | binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])), |
| 1607 | mkexpr(mask[i])))); |
| 1608 | old = nyu1; |
| 1609 | } |
| 1610 | |
| 1611 | old = src2; |
| 1612 | for (i = 0; i < WORD; i++) { |
| 1613 | nyu2 = newTemp(Ity_I32); |
| 1614 | assign(nyu2, |
| 1615 | binop(Iop_Add32, |
| 1616 | binop(Iop_And32, |
| 1617 | mkexpr(old), |
| 1618 | mkexpr(mask[i])), |
| 1619 | binop(Iop_And32, |
| 1620 | binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])), |
| 1621 | mkexpr(mask[i])))); |
| 1622 | old = nyu2; |
| 1623 | } |
| 1624 | assign(retval, unop(Iop_32Uto64, binop(Iop_Add32, mkexpr(nyu1), mkexpr(nyu2)))); |
| 1625 | return retval; |
| 1626 | } |
| 1627 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1628 | |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 1629 | // ROTL(src32/64, rot_amt5/6) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1630 | static IRExpr* /* :: Ity_I32/64 */ ROTL ( IRExpr* src, |
| 1631 | IRExpr* rot_amt ) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1632 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1633 | IRExpr *mask, *rot; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1634 | vassert(typeOfIRExpr(irsb->tyenv,rot_amt) == Ity_I8); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1635 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1636 | if (typeOfIRExpr(irsb->tyenv,src) == Ity_I64) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1637 | // rot = (src << rot_amt) | (src >> (64-rot_amt)) |
| 1638 | mask = binop(Iop_And8, rot_amt, mkU8(63)); |
| 1639 | rot = binop(Iop_Or64, |
| 1640 | binop(Iop_Shl64, src, mask), |
| 1641 | binop(Iop_Shr64, src, binop(Iop_Sub8, mkU8(64), mask))); |
| 1642 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1643 | // rot = (src << rot_amt) | (src >> (32-rot_amt)) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1644 | mask = binop(Iop_And8, rot_amt, mkU8(31)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1645 | rot = binop(Iop_Or32, |
| 1646 | binop(Iop_Shl32, src, mask), |
| 1647 | binop(Iop_Shr32, src, binop(Iop_Sub8, mkU8(32), mask))); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1648 | } |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 1649 | /* Note: the ITE not merely an optimisation; it's needed |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1650 | because otherwise the Shr is a shift by the word size when |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1651 | mask denotes zero. For rotates by immediates, a lot of |
sewardj | c965953 | 2005-07-21 21:33:57 +0000 | [diff] [blame] | 1652 | this junk gets folded out. */ |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 1653 | return IRExpr_ITE( binop(Iop_CmpNE8, mask, mkU8(0)), |
| 1654 | /* non-zero rotate */ rot, |
| 1655 | /* zero rotate */ src); |
cerion | 45b70ff | 2005-01-31 17:03:25 +0000 | [diff] [blame] | 1656 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1657 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1658 | /* Standard effective address calc: (rA + rB) */ |
| 1659 | static IRExpr* ea_rA_idxd ( UInt rA, UInt rB ) |
| 1660 | { |
| 1661 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1662 | vassert(rA < 32); |
| 1663 | vassert(rB < 32); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1664 | return binop(mkSzOp(ty, Iop_Add8), getIReg(rA), getIReg(rB)); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 1665 | } |
| 1666 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1667 | /* Standard effective address calc: (rA + simm) */ |
| 1668 | static IRExpr* ea_rA_simm ( UInt rA, UInt simm16 ) |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 1669 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1670 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1671 | vassert(rA < 32); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1672 | return binop(mkSzOp(ty, Iop_Add8), getIReg(rA), |
| 1673 | mkSzExtendS16(ty, simm16)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1674 | } |
| 1675 | |
| 1676 | /* Standard effective address calc: (rA|0) */ |
| 1677 | static IRExpr* ea_rAor0 ( UInt rA ) |
| 1678 | { |
| 1679 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1680 | vassert(rA < 32); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 1681 | if (rA == 0) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1682 | return mkSzImm(ty, 0); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 1683 | } else { |
| 1684 | return getIReg(rA); |
| 1685 | } |
| 1686 | } |
| 1687 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1688 | /* Standard effective address calc: (rA|0) + rB */ |
| 1689 | static IRExpr* ea_rAor0_idxd ( UInt rA, UInt rB ) |
| 1690 | { |
| 1691 | vassert(rA < 32); |
| 1692 | vassert(rB < 32); |
| 1693 | return (rA == 0) ? getIReg(rB) : ea_rA_idxd( rA, rB ); |
| 1694 | } |
| 1695 | |
| 1696 | /* Standard effective address calc: (rA|0) + simm16 */ |
| 1697 | static IRExpr* ea_rAor0_simm ( UInt rA, UInt simm16 ) |
| 1698 | { |
| 1699 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1700 | vassert(rA < 32); |
| 1701 | if (rA == 0) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1702 | return mkSzExtendS16(ty, simm16); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1703 | } else { |
| 1704 | return ea_rA_simm( rA, simm16 ); |
| 1705 | } |
| 1706 | } |
| 1707 | |
| 1708 | |
| 1709 | /* Align effective address */ |
| 1710 | static IRExpr* addr_align( IRExpr* addr, UChar align ) |
| 1711 | { |
| 1712 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1713 | Long mask; |
| 1714 | switch (align) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1715 | case 1: return addr; // byte aligned |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1716 | case 2: mask = ((Long)-1) << 1; break; // half-word aligned |
| 1717 | case 4: mask = ((Long)-1) << 2; break; // word aligned |
| 1718 | case 16: mask = ((Long)-1) << 4; break; // quad-word aligned |
| 1719 | default: |
| 1720 | vex_printf("addr_align: align = %u\n", align); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1721 | vpanic("addr_align(ppc)"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1722 | } |
| 1723 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1724 | vassert(typeOfIRExpr(irsb->tyenv,addr) == ty); |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 1725 | return binop( mkSzOp(ty, Iop_And8), addr, mkSzImm(ty, mask) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1726 | } |
| 1727 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1728 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1729 | /* Exit the trace if ADDR (intended to be a guest memory address) is |
| 1730 | not ALIGN-aligned, generating a request for a SIGBUS followed by a |
| 1731 | restart of the current insn. */ |
| 1732 | static void gen_SIGBUS_if_misaligned ( IRTemp addr, UChar align ) |
| 1733 | { |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 1734 | vassert(align == 4 || align == 8 || align == 16); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1735 | if (mode64) { |
| 1736 | vassert(typeOfIRTemp(irsb->tyenv, addr) == Ity_I64); |
| 1737 | stmt( |
| 1738 | IRStmt_Exit( |
| 1739 | binop(Iop_CmpNE64, |
| 1740 | binop(Iop_And64, mkexpr(addr), mkU64(align-1)), |
| 1741 | mkU64(0)), |
| 1742 | Ijk_SigBUS, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1743 | IRConst_U64( guest_CIA_curr_instr ), OFFB_CIA |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1744 | ) |
| 1745 | ); |
| 1746 | } else { |
| 1747 | vassert(typeOfIRTemp(irsb->tyenv, addr) == Ity_I32); |
| 1748 | stmt( |
| 1749 | IRStmt_Exit( |
| 1750 | binop(Iop_CmpNE32, |
| 1751 | binop(Iop_And32, mkexpr(addr), mkU32(align-1)), |
| 1752 | mkU32(0)), |
| 1753 | Ijk_SigBUS, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1754 | IRConst_U32( guest_CIA_curr_instr ), OFFB_CIA |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1755 | ) |
| 1756 | ); |
| 1757 | } |
| 1758 | } |
| 1759 | |
| 1760 | |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1761 | /* Generate AbiHints which mark points at which the ELF or PowerOpen |
| 1762 | ABIs say that the stack red zone (viz, -N(r1) .. -1(r1), for some |
| 1763 | N) becomes undefined. That is at function calls and returns. ELF |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 1764 | ppc32 doesn't have this "feature" (how fortunate for it). nia is |
| 1765 | the address of the next instruction to be executed. |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 1766 | */ |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 1767 | static void make_redzone_AbiHint ( VexAbiInfo* vbi, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1768 | IRTemp nia, const HChar* who ) |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 1769 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1770 | Int szB = vbi->guest_stack_redzone_size; |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 1771 | if (0) vex_printf("AbiHint: %s\n", who); |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1772 | vassert(szB >= 0); |
| 1773 | if (szB > 0) { |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 1774 | if (mode64) { |
| 1775 | vassert(typeOfIRTemp(irsb->tyenv, nia) == Ity_I64); |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1776 | stmt( IRStmt_AbiHint( |
| 1777 | binop(Iop_Sub64, getIReg(1), mkU64(szB)), |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 1778 | szB, |
| 1779 | mkexpr(nia) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1780 | )); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 1781 | } else { |
| 1782 | vassert(typeOfIRTemp(irsb->tyenv, nia) == Ity_I32); |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1783 | stmt( IRStmt_AbiHint( |
| 1784 | binop(Iop_Sub32, getIReg(1), mkU32(szB)), |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 1785 | szB, |
| 1786 | mkexpr(nia) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1787 | )); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 1788 | } |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1789 | } |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 1790 | } |
| 1791 | |
| 1792 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1793 | /*------------------------------------------------------------*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1794 | /*--- Helpers for condition codes. ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1795 | /*------------------------------------------------------------*/ |
| 1796 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1797 | /* Condition register layout. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1798 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1799 | In the hardware, CR is laid out like this. The leftmost end is the |
| 1800 | most significant bit in the register; however the IBM documentation |
| 1801 | numbers the bits backwards for some reason. |
| 1802 | |
| 1803 | CR0 CR1 .......... CR6 CR7 |
| 1804 | 0 .. 3 ....................... 28 .. 31 (IBM bit numbering) |
| 1805 | 31 28 3 0 (normal bit numbering) |
| 1806 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1807 | Each CR field is 4 bits: [<,>,==,SO] |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1808 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1809 | Hence in IBM's notation, BI=0 is CR7[SO], BI=1 is CR7[==], etc. |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1810 | |
| 1811 | Indexing from BI to guest state: |
| 1812 | |
| 1813 | let n = BI / 4 |
| 1814 | off = BI % 4 |
| 1815 | this references CR n: |
| 1816 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1817 | off==0 -> guest_CRn_321 >> 3 |
| 1818 | off==1 -> guest_CRn_321 >> 2 |
| 1819 | off==2 -> guest_CRn_321 >> 1 |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1820 | off==3 -> guest_CRn_SO |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1821 | |
| 1822 | Bear in mind the only significant bit in guest_CRn_SO is bit 0 |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1823 | (normal notation) and in guest_CRn_321 the significant bits are |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1824 | 3, 2 and 1 (normal notation). |
| 1825 | */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1826 | |
| 1827 | static void putCR321 ( UInt cr, IRExpr* e ) |
| 1828 | { |
| 1829 | vassert(cr < 8); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1830 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1831 | stmt( IRStmt_Put(guestCR321offset(cr), e) ); |
| 1832 | } |
| 1833 | |
| 1834 | static void putCR0 ( UInt cr, IRExpr* e ) |
| 1835 | { |
| 1836 | vassert(cr < 8); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1837 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1838 | stmt( IRStmt_Put(guestCR0offset(cr), e) ); |
| 1839 | } |
| 1840 | |
| 1841 | static IRExpr* /* :: Ity_I8 */ getCR0 ( UInt cr ) |
| 1842 | { |
| 1843 | vassert(cr < 8); |
| 1844 | return IRExpr_Get(guestCR0offset(cr), Ity_I8); |
| 1845 | } |
| 1846 | |
| 1847 | static IRExpr* /* :: Ity_I8 */ getCR321 ( UInt cr ) |
| 1848 | { |
| 1849 | vassert(cr < 8); |
| 1850 | return IRExpr_Get(guestCR321offset(cr), Ity_I8); |
| 1851 | } |
| 1852 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1853 | /* Fetch the specified CR bit (as per IBM/hardware notation) and |
| 1854 | return it at the bottom of an I32; the top 31 bits are guaranteed |
| 1855 | to be zero. */ |
| 1856 | static IRExpr* /* :: Ity_I32 */ getCRbit ( UInt bi ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1857 | { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1858 | UInt n = bi / 4; |
| 1859 | UInt off = bi % 4; |
| 1860 | vassert(bi < 32); |
| 1861 | if (off == 3) { |
| 1862 | /* Fetch the SO bit for this CR field */ |
| 1863 | /* Note: And32 is redundant paranoia iff guest state only has 0 |
| 1864 | or 1 in that slot. */ |
| 1865 | return binop(Iop_And32, unop(Iop_8Uto32, getCR0(n)), mkU32(1)); |
| 1866 | } else { |
| 1867 | /* Fetch the <, > or == bit for this CR field */ |
| 1868 | return binop( Iop_And32, |
| 1869 | binop( Iop_Shr32, |
| 1870 | unop(Iop_8Uto32, getCR321(n)), |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 1871 | mkU8(toUChar(3-off)) ), |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1872 | mkU32(1) ); |
| 1873 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 1874 | } |
| 1875 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1876 | /* Dually, write the least significant bit of BIT to the specified CR |
| 1877 | bit. Indexing as per getCRbit. */ |
| 1878 | static void putCRbit ( UInt bi, IRExpr* bit ) |
| 1879 | { |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 1880 | UInt n, off; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1881 | IRExpr* safe; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1882 | vassert(typeOfIRExpr(irsb->tyenv,bit) == Ity_I32); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1883 | safe = binop(Iop_And32, bit, mkU32(1)); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 1884 | n = bi / 4; |
| 1885 | off = bi % 4; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1886 | vassert(bi < 32); |
| 1887 | if (off == 3) { |
| 1888 | /* This is the SO bit for this CR field */ |
| 1889 | putCR0(n, unop(Iop_32to8, safe)); |
| 1890 | } else { |
| 1891 | off = 3 - off; |
| 1892 | vassert(off == 1 || off == 2 || off == 3); |
| 1893 | putCR321( |
| 1894 | n, |
| 1895 | unop( Iop_32to8, |
| 1896 | binop( Iop_Or32, |
| 1897 | /* old value with field masked out */ |
| 1898 | binop(Iop_And32, unop(Iop_8Uto32, getCR321(n)), |
| 1899 | mkU32(~(1 << off))), |
| 1900 | /* new value in the right place */ |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 1901 | binop(Iop_Shl32, safe, mkU8(toUChar(off))) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1902 | ) |
| 1903 | ) |
| 1904 | ); |
| 1905 | } |
| 1906 | } |
| 1907 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1908 | /* Fetch the specified CR bit (as per IBM/hardware notation) and |
| 1909 | return it somewhere in an I32; it does not matter where, but |
| 1910 | whichever bit it is, all other bits are guaranteed to be zero. In |
| 1911 | other words, the I32-typed expression will be zero if the bit is |
| 1912 | zero and nonzero if the bit is 1. Write into *where the index |
| 1913 | of where the bit will be. */ |
| 1914 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1915 | static |
| 1916 | IRExpr* /* :: Ity_I32 */ getCRbit_anywhere ( UInt bi, Int* where ) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1917 | { |
| 1918 | UInt n = bi / 4; |
| 1919 | UInt off = bi % 4; |
| 1920 | vassert(bi < 32); |
| 1921 | if (off == 3) { |
| 1922 | /* Fetch the SO bit for this CR field */ |
| 1923 | /* Note: And32 is redundant paranoia iff guest state only has 0 |
| 1924 | or 1 in that slot. */ |
| 1925 | *where = 0; |
| 1926 | return binop(Iop_And32, unop(Iop_8Uto32, getCR0(n)), mkU32(1)); |
| 1927 | } else { |
| 1928 | /* Fetch the <, > or == bit for this CR field */ |
| 1929 | *where = 3-off; |
| 1930 | return binop( Iop_And32, |
| 1931 | unop(Iop_8Uto32, getCR321(n)), |
| 1932 | mkU32(1 << (3-off)) ); |
| 1933 | } |
| 1934 | } |
| 1935 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1936 | /* Set the CR0 flags following an arithmetic operation. |
| 1937 | (Condition Register CR0 Field Definition, PPC32 p60) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1938 | */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1939 | static IRExpr* getXER_SO ( void ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1940 | static void set_CR0 ( IRExpr* result ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1941 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1942 | vassert(typeOfIRExpr(irsb->tyenv,result) == Ity_I32 || |
| 1943 | typeOfIRExpr(irsb->tyenv,result) == Ity_I64); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1944 | if (mode64) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1945 | putCR321( 0, unop(Iop_64to8, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1946 | binop(Iop_CmpORD64S, result, mkU64(0))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1947 | } else { |
| 1948 | putCR321( 0, unop(Iop_32to8, |
| 1949 | binop(Iop_CmpORD32S, result, mkU32(0))) ); |
| 1950 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1951 | putCR0( 0, getXER_SO() ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1952 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1953 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1954 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 1955 | /* Set the CR6 flags following an AltiVec compare operation. |
| 1956 | * NOTE: This also works for VSX single-precision compares. |
| 1957 | * */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1958 | static void set_AV_CR6 ( IRExpr* result, Bool test_all_ones ) |
| 1959 | { |
| 1960 | /* CR6[0:3] = {all_ones, 0, all_zeros, 0} |
| 1961 | all_ones = (v[0] && v[1] && v[2] && v[3]) |
| 1962 | all_zeros = ~(v[0] || v[1] || v[2] || v[3]) |
| 1963 | */ |
| 1964 | IRTemp v0 = newTemp(Ity_V128); |
| 1965 | IRTemp v1 = newTemp(Ity_V128); |
| 1966 | IRTemp v2 = newTemp(Ity_V128); |
| 1967 | IRTemp v3 = newTemp(Ity_V128); |
| 1968 | IRTemp rOnes = newTemp(Ity_I8); |
| 1969 | IRTemp rZeros = newTemp(Ity_I8); |
| 1970 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1971 | vassert(typeOfIRExpr(irsb->tyenv,result) == Ity_V128); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1972 | |
| 1973 | assign( v0, result ); |
| 1974 | assign( v1, binop(Iop_ShrV128, result, mkU8(32)) ); |
| 1975 | assign( v2, binop(Iop_ShrV128, result, mkU8(64)) ); |
| 1976 | assign( v3, binop(Iop_ShrV128, result, mkU8(96)) ); |
| 1977 | |
| 1978 | assign( rZeros, unop(Iop_1Uto8, |
| 1979 | binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF), |
| 1980 | unop(Iop_Not32, |
| 1981 | unop(Iop_V128to32, |
| 1982 | binop(Iop_OrV128, |
| 1983 | binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)), |
| 1984 | binop(Iop_OrV128, mkexpr(v2), mkexpr(v3)))) |
| 1985 | ))) ); |
| 1986 | |
| 1987 | if (test_all_ones) { |
| 1988 | assign( rOnes, unop(Iop_1Uto8, |
| 1989 | binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF), |
| 1990 | unop(Iop_V128to32, |
| 1991 | binop(Iop_AndV128, |
| 1992 | binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1993 | binop(Iop_AndV128, mkexpr(v2), mkexpr(v3))) |
| 1994 | ))) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1995 | putCR321( 6, binop(Iop_Or8, |
| 1996 | binop(Iop_Shl8, mkexpr(rOnes), mkU8(3)), |
| 1997 | binop(Iop_Shl8, mkexpr(rZeros), mkU8(1))) ); |
| 1998 | } else { |
| 1999 | putCR321( 6, binop(Iop_Shl8, mkexpr(rZeros), mkU8(1)) ); |
| 2000 | } |
| 2001 | putCR0( 6, mkU8(0) ); |
| 2002 | } |
| 2003 | |
| 2004 | |
| 2005 | |
| 2006 | /*------------------------------------------------------------*/ |
| 2007 | /*--- Helpers for XER flags. ---*/ |
| 2008 | /*------------------------------------------------------------*/ |
| 2009 | |
| 2010 | static void putXER_SO ( IRExpr* e ) |
| 2011 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 2012 | IRExpr* so; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2013 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 2014 | so = binop(Iop_And8, e, mkU8(1)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2015 | stmt( IRStmt_Put( OFFB_XER_SO, so ) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2016 | } |
| 2017 | |
| 2018 | static void putXER_OV ( IRExpr* e ) |
| 2019 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 2020 | IRExpr* ov; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2021 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 2022 | ov = binop(Iop_And8, e, mkU8(1)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2023 | stmt( IRStmt_Put( OFFB_XER_OV, ov ) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2024 | } |
| 2025 | |
| 2026 | static void putXER_CA ( IRExpr* e ) |
| 2027 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 2028 | IRExpr* ca; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2029 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 2030 | ca = binop(Iop_And8, e, mkU8(1)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2031 | stmt( IRStmt_Put( OFFB_XER_CA, ca ) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2032 | } |
| 2033 | |
| 2034 | static void putXER_BC ( IRExpr* e ) |
| 2035 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 2036 | IRExpr* bc; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2037 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 2038 | bc = binop(Iop_And8, e, mkU8(0x7F)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2039 | stmt( IRStmt_Put( OFFB_XER_BC, bc ) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2040 | } |
| 2041 | |
| 2042 | static IRExpr* /* :: Ity_I8 */ getXER_SO ( void ) |
| 2043 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2044 | return IRExpr_Get( OFFB_XER_SO, Ity_I8 ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2045 | } |
| 2046 | |
| 2047 | static IRExpr* /* :: Ity_I32 */ getXER_SO32 ( void ) |
| 2048 | { |
| 2049 | return binop( Iop_And32, unop(Iop_8Uto32, getXER_SO()), mkU32(1) ); |
| 2050 | } |
| 2051 | |
| 2052 | static IRExpr* /* :: Ity_I8 */ getXER_OV ( void ) |
| 2053 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2054 | return IRExpr_Get( OFFB_XER_OV, Ity_I8 ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2055 | } |
| 2056 | |
| 2057 | static IRExpr* /* :: Ity_I32 */ getXER_OV32 ( void ) |
| 2058 | { |
| 2059 | return binop( Iop_And32, unop(Iop_8Uto32, getXER_OV()), mkU32(1) ); |
| 2060 | } |
| 2061 | |
| 2062 | static IRExpr* /* :: Ity_I32 */ getXER_CA32 ( void ) |
| 2063 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2064 | IRExpr* ca = IRExpr_Get( OFFB_XER_CA, Ity_I8 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2065 | return binop( Iop_And32, unop(Iop_8Uto32, ca ), mkU32(1) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2066 | } |
| 2067 | |
| 2068 | static IRExpr* /* :: Ity_I8 */ getXER_BC ( void ) |
| 2069 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2070 | return IRExpr_Get( OFFB_XER_BC, Ity_I8 ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2071 | } |
| 2072 | |
| 2073 | static IRExpr* /* :: Ity_I32 */ getXER_BC32 ( void ) |
| 2074 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2075 | IRExpr* bc = IRExpr_Get( OFFB_XER_BC, Ity_I8 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2076 | return binop( Iop_And32, unop(Iop_8Uto32, bc), mkU32(0x7F) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2077 | } |
| 2078 | |
| 2079 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2080 | /* RES is the result of doing OP on ARGL and ARGR. Set %XER.OV and |
| 2081 | %XER.SO accordingly. */ |
| 2082 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2083 | static void set_XER_OV_32( UInt op, IRExpr* res, |
| 2084 | IRExpr* argL, IRExpr* argR ) |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2085 | { |
| 2086 | IRTemp t64; |
| 2087 | IRExpr* xer_ov; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2088 | vassert(op < PPCG_FLAG_OP_NUMBER); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2089 | vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32); |
| 2090 | vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32); |
| 2091 | vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2092 | |
| 2093 | # define INT32_MIN 0x80000000 |
| 2094 | |
| 2095 | # define XOR2(_aa,_bb) \ |
| 2096 | binop(Iop_Xor32,(_aa),(_bb)) |
| 2097 | |
| 2098 | # define XOR3(_cc,_dd,_ee) \ |
| 2099 | binop(Iop_Xor32,binop(Iop_Xor32,(_cc),(_dd)),(_ee)) |
| 2100 | |
| 2101 | # define AND3(_ff,_gg,_hh) \ |
| 2102 | binop(Iop_And32,binop(Iop_And32,(_ff),(_gg)),(_hh)) |
| 2103 | |
| 2104 | #define NOT(_jj) \ |
| 2105 | unop(Iop_Not32, (_jj)) |
| 2106 | |
| 2107 | switch (op) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2108 | case /* 0 */ PPCG_FLAG_OP_ADD: |
| 2109 | case /* 1 */ PPCG_FLAG_OP_ADDE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2110 | /* (argL^argR^-1) & (argL^res) & (1<<31) ?1:0 */ |
| 2111 | // i.e. ((both_same_sign) & (sign_changed) & (sign_mask)) |
| 2112 | xer_ov |
| 2113 | = AND3( XOR3(argL,argR,mkU32(-1)), |
| 2114 | XOR2(argL,res), |
| 2115 | mkU32(INT32_MIN) ); |
| 2116 | /* xer_ov can only be 0 or 1<<31 */ |
| 2117 | xer_ov |
| 2118 | = binop(Iop_Shr32, xer_ov, mkU8(31) ); |
| 2119 | break; |
| 2120 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2121 | case /* 2 */ PPCG_FLAG_OP_DIVW: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2122 | /* (argL == INT32_MIN && argR == -1) || argR == 0 */ |
| 2123 | xer_ov |
| 2124 | = mkOR1( |
| 2125 | mkAND1( |
| 2126 | binop(Iop_CmpEQ32, argL, mkU32(INT32_MIN)), |
| 2127 | binop(Iop_CmpEQ32, argR, mkU32(-1)) |
| 2128 | ), |
| 2129 | binop(Iop_CmpEQ32, argR, mkU32(0) ) |
| 2130 | ); |
| 2131 | xer_ov |
| 2132 | = unop(Iop_1Uto32, xer_ov); |
| 2133 | break; |
| 2134 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2135 | case /* 3 */ PPCG_FLAG_OP_DIVWU: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2136 | /* argR == 0 */ |
| 2137 | xer_ov |
| 2138 | = unop(Iop_1Uto32, binop(Iop_CmpEQ32, argR, mkU32(0))); |
| 2139 | break; |
| 2140 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2141 | case /* 4 */ PPCG_FLAG_OP_MULLW: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2142 | /* OV true if result can't be represented in 32 bits |
| 2143 | i.e sHi != sign extension of sLo */ |
| 2144 | t64 = newTemp(Ity_I64); |
| 2145 | assign( t64, binop(Iop_MullS32, argL, argR) ); |
| 2146 | xer_ov |
| 2147 | = binop( Iop_CmpNE32, |
| 2148 | unop(Iop_64HIto32, mkexpr(t64)), |
| 2149 | binop( Iop_Sar32, |
| 2150 | unop(Iop_64to32, mkexpr(t64)), |
| 2151 | mkU8(31)) |
| 2152 | ); |
| 2153 | xer_ov |
| 2154 | = unop(Iop_1Uto32, xer_ov); |
| 2155 | break; |
| 2156 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2157 | case /* 5 */ PPCG_FLAG_OP_NEG: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2158 | /* argL == INT32_MIN */ |
| 2159 | xer_ov |
| 2160 | = unop( Iop_1Uto32, |
| 2161 | binop(Iop_CmpEQ32, argL, mkU32(INT32_MIN)) ); |
| 2162 | break; |
| 2163 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2164 | case /* 6 */ PPCG_FLAG_OP_SUBF: |
| 2165 | case /* 7 */ PPCG_FLAG_OP_SUBFC: |
| 2166 | case /* 8 */ PPCG_FLAG_OP_SUBFE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2167 | /* ((~argL)^argR^-1) & ((~argL)^res) & (1<<31) ?1:0; */ |
| 2168 | xer_ov |
| 2169 | = AND3( XOR3(NOT(argL),argR,mkU32(-1)), |
| 2170 | XOR2(NOT(argL),res), |
| 2171 | mkU32(INT32_MIN) ); |
| 2172 | /* xer_ov can only be 0 or 1<<31 */ |
| 2173 | xer_ov |
| 2174 | = binop(Iop_Shr32, xer_ov, mkU8(31) ); |
| 2175 | break; |
| 2176 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 2177 | case PPCG_FLAG_OP_DIVWEU: |
| 2178 | xer_ov |
| 2179 | = binop( Iop_Or32, |
| 2180 | unop( Iop_1Uto32, binop( Iop_CmpEQ32, argR, mkU32( 0 ) ) ), |
| 2181 | unop( Iop_1Uto32, binop( Iop_CmpLT32U, argR, argL ) ) ); |
| 2182 | break; |
| 2183 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 2184 | case PPCG_FLAG_OP_DIVWE: |
| 2185 | |
| 2186 | /* If argR == 0 of if the result cannot fit in the 32-bit destination register, |
| 2187 | * then OV <- 1. If dest reg is 0 AND both dividend and divisor are non-zero, |
| 2188 | * an overflow is implied. |
| 2189 | */ |
| 2190 | xer_ov = binop( Iop_Or32, |
| 2191 | unop( Iop_1Uto32, binop( Iop_CmpEQ32, argR, mkU32( 0 ) ) ), |
| 2192 | unop( Iop_1Uto32, mkAND1( binop( Iop_CmpEQ32, res, mkU32( 0 ) ), |
| 2193 | mkAND1( binop( Iop_CmpNE32, argL, mkU32( 0 ) ), |
| 2194 | binop( Iop_CmpNE32, argR, mkU32( 0 ) ) ) ) ) ); |
| 2195 | break; |
| 2196 | |
| 2197 | |
| 2198 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2199 | default: |
| 2200 | vex_printf("set_XER_OV: op = %u\n", op); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2201 | vpanic("set_XER_OV(ppc)"); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2202 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2203 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2204 | /* xer_ov MUST denote either 0 or 1, no other value allowed */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2205 | putXER_OV( unop(Iop_32to8, xer_ov) ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2206 | |
| 2207 | /* Update the summary overflow */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2208 | putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2209 | |
| 2210 | # undef INT32_MIN |
| 2211 | # undef AND3 |
| 2212 | # undef XOR3 |
| 2213 | # undef XOR2 |
| 2214 | # undef NOT |
| 2215 | } |
| 2216 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2217 | static void set_XER_OV_64( UInt op, IRExpr* res, |
| 2218 | IRExpr* argL, IRExpr* argR ) |
| 2219 | { |
| 2220 | IRExpr* xer_ov; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2221 | vassert(op < PPCG_FLAG_OP_NUMBER); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2222 | vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64); |
| 2223 | vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64); |
| 2224 | vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2225 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2226 | # define INT64_MIN 0x8000000000000000ULL |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2227 | |
| 2228 | # define XOR2(_aa,_bb) \ |
| 2229 | binop(Iop_Xor64,(_aa),(_bb)) |
| 2230 | |
| 2231 | # define XOR3(_cc,_dd,_ee) \ |
| 2232 | binop(Iop_Xor64,binop(Iop_Xor64,(_cc),(_dd)),(_ee)) |
| 2233 | |
| 2234 | # define AND3(_ff,_gg,_hh) \ |
| 2235 | binop(Iop_And64,binop(Iop_And64,(_ff),(_gg)),(_hh)) |
| 2236 | |
| 2237 | #define NOT(_jj) \ |
| 2238 | unop(Iop_Not64, (_jj)) |
| 2239 | |
| 2240 | switch (op) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2241 | case /* 0 */ PPCG_FLAG_OP_ADD: |
| 2242 | case /* 1 */ PPCG_FLAG_OP_ADDE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2243 | /* (argL^argR^-1) & (argL^res) & (1<<63) ? 1:0 */ |
| 2244 | // i.e. ((both_same_sign) & (sign_changed) & (sign_mask)) |
| 2245 | xer_ov |
| 2246 | = AND3( XOR3(argL,argR,mkU64(-1)), |
| 2247 | XOR2(argL,res), |
| 2248 | mkU64(INT64_MIN) ); |
| 2249 | /* xer_ov can only be 0 or 1<<63 */ |
| 2250 | xer_ov |
| 2251 | = unop(Iop_64to1, binop(Iop_Shr64, xer_ov, mkU8(63))); |
| 2252 | break; |
| 2253 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2254 | case /* 2 */ PPCG_FLAG_OP_DIVW: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2255 | /* (argL == INT64_MIN && argR == -1) || argR == 0 */ |
| 2256 | xer_ov |
| 2257 | = mkOR1( |
| 2258 | mkAND1( |
| 2259 | binop(Iop_CmpEQ64, argL, mkU64(INT64_MIN)), |
| 2260 | binop(Iop_CmpEQ64, argR, mkU64(-1)) |
| 2261 | ), |
| 2262 | binop(Iop_CmpEQ64, argR, mkU64(0) ) |
| 2263 | ); |
| 2264 | break; |
| 2265 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2266 | case /* 3 */ PPCG_FLAG_OP_DIVWU: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2267 | /* argR == 0 */ |
| 2268 | xer_ov |
| 2269 | = binop(Iop_CmpEQ64, argR, mkU64(0)); |
| 2270 | break; |
| 2271 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2272 | case /* 4 */ PPCG_FLAG_OP_MULLW: { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2273 | /* OV true if result can't be represented in 64 bits |
| 2274 | i.e sHi != sign extension of sLo */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2275 | xer_ov |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2276 | = binop( Iop_CmpNE32, |
| 2277 | unop(Iop_64HIto32, res), |
| 2278 | binop( Iop_Sar32, |
| 2279 | unop(Iop_64to32, res), |
| 2280 | mkU8(31)) |
| 2281 | ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2282 | break; |
| 2283 | } |
| 2284 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2285 | case /* 5 */ PPCG_FLAG_OP_NEG: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2286 | /* argL == INT64_MIN */ |
| 2287 | xer_ov |
| 2288 | = binop(Iop_CmpEQ64, argL, mkU64(INT64_MIN)); |
| 2289 | break; |
| 2290 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2291 | case /* 6 */ PPCG_FLAG_OP_SUBF: |
| 2292 | case /* 7 */ PPCG_FLAG_OP_SUBFC: |
| 2293 | case /* 8 */ PPCG_FLAG_OP_SUBFE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2294 | /* ((~argL)^argR^-1) & ((~argL)^res) & (1<<63) ?1:0; */ |
| 2295 | xer_ov |
| 2296 | = AND3( XOR3(NOT(argL),argR,mkU64(-1)), |
| 2297 | XOR2(NOT(argL),res), |
| 2298 | mkU64(INT64_MIN) ); |
| 2299 | /* xer_ov can only be 0 or 1<<63 */ |
| 2300 | xer_ov |
| 2301 | = unop(Iop_64to1, binop(Iop_Shr64, xer_ov, mkU8(63))); |
| 2302 | break; |
| 2303 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 2304 | case PPCG_FLAG_OP_DIVDE: |
| 2305 | |
| 2306 | /* If argR == 0, we must set the OV bit. But there's another condition |
| 2307 | * where we can get overflow set for divde . . . when the |
| 2308 | * result cannot fit in the 64-bit destination register. If dest reg is 0 AND |
| 2309 | * both dividend and divisor are non-zero, it implies an overflow. |
| 2310 | */ |
| 2311 | xer_ov |
| 2312 | = mkOR1( binop( Iop_CmpEQ64, argR, mkU64( 0 ) ), |
| 2313 | mkAND1( binop( Iop_CmpEQ64, res, mkU64( 0 ) ), |
| 2314 | mkAND1( binop( Iop_CmpNE64, argL, mkU64( 0 ) ), |
| 2315 | binop( Iop_CmpNE64, argR, mkU64( 0 ) ) ) ) ); |
| 2316 | break; |
| 2317 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 2318 | case PPCG_FLAG_OP_DIVDEU: |
| 2319 | /* If argR == 0 or if argL >= argR, set OV. */ |
| 2320 | xer_ov = mkOR1( binop( Iop_CmpEQ64, argR, mkU64( 0 ) ), |
| 2321 | binop( Iop_CmpLE64U, argR, argL ) ); |
| 2322 | break; |
| 2323 | |
carll | 38b79ac | 2013-09-06 22:27:34 +0000 | [diff] [blame] | 2324 | case /* 18 */ PPCG_FLAG_OP_MULLD: { |
| 2325 | IRTemp t128; |
| 2326 | /* OV true if result can't be represented in 64 bits |
| 2327 | i.e sHi != sign extension of sLo */ |
| 2328 | t128 = newTemp(Ity_I128); |
| 2329 | assign( t128, binop(Iop_MullS64, argL, argR) ); |
| 2330 | xer_ov |
| 2331 | = binop( Iop_CmpNE64, |
| 2332 | unop(Iop_128HIto64, mkexpr(t128)), |
| 2333 | binop( Iop_Sar64, |
| 2334 | unop(Iop_128to64, mkexpr(t128)), |
| 2335 | mkU8(63)) |
| 2336 | ); |
| 2337 | break; |
| 2338 | } |
| 2339 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2340 | default: |
| 2341 | vex_printf("set_XER_OV: op = %u\n", op); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2342 | vpanic("set_XER_OV(ppc64)"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2343 | } |
| 2344 | |
| 2345 | /* xer_ov MUST denote either 0 or 1, no other value allowed */ |
| 2346 | putXER_OV( unop(Iop_1Uto8, xer_ov) ); |
| 2347 | |
| 2348 | /* Update the summary overflow */ |
| 2349 | putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) ); |
| 2350 | |
| 2351 | # undef INT64_MIN |
| 2352 | # undef AND3 |
| 2353 | # undef XOR3 |
| 2354 | # undef XOR2 |
| 2355 | # undef NOT |
| 2356 | } |
| 2357 | |
| 2358 | static void set_XER_OV ( IRType ty, UInt op, IRExpr* res, |
| 2359 | IRExpr* argL, IRExpr* argR ) |
| 2360 | { |
| 2361 | if (ty == Ity_I32) |
| 2362 | set_XER_OV_32( op, res, argL, argR ); |
| 2363 | else |
| 2364 | set_XER_OV_64( op, res, argL, argR ); |
| 2365 | } |
| 2366 | |
| 2367 | |
| 2368 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2369 | /* RES is the result of doing OP on ARGL and ARGR with the old %XER.CA |
| 2370 | value being OLDCA. Set %XER.CA accordingly. */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2371 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2372 | static void set_XER_CA_32 ( UInt op, IRExpr* res, |
| 2373 | IRExpr* argL, IRExpr* argR, IRExpr* oldca ) |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 2374 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 2375 | IRExpr* xer_ca; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2376 | vassert(op < PPCG_FLAG_OP_NUMBER); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2377 | vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32); |
| 2378 | vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32); |
| 2379 | vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32); |
| 2380 | vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I32); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2381 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2382 | /* Incoming oldca is assumed to hold the values 0 or 1 only. This |
| 2383 | seems reasonable given that it's always generated by |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2384 | getXER_CA32(), which masks it accordingly. In any case it being |
cerion | 7594920 | 2005-12-24 13:14:11 +0000 | [diff] [blame] | 2385 | 0 or 1 is an invariant of the ppc guest state representation; |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2386 | if it has any other value, that invariant has been violated. */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2387 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2388 | switch (op) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2389 | case /* 0 */ PPCG_FLAG_OP_ADD: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2390 | /* res <u argL */ |
| 2391 | xer_ca |
| 2392 | = unop(Iop_1Uto32, binop(Iop_CmpLT32U, res, argL)); |
| 2393 | break; |
| 2394 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2395 | case /* 1 */ PPCG_FLAG_OP_ADDE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2396 | /* res <u argL || (old_ca==1 && res==argL) */ |
| 2397 | xer_ca |
| 2398 | = mkOR1( |
| 2399 | binop(Iop_CmpLT32U, res, argL), |
| 2400 | mkAND1( |
| 2401 | binop(Iop_CmpEQ32, oldca, mkU32(1)), |
| 2402 | binop(Iop_CmpEQ32, res, argL) |
| 2403 | ) |
| 2404 | ); |
| 2405 | xer_ca |
| 2406 | = unop(Iop_1Uto32, xer_ca); |
| 2407 | break; |
| 2408 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2409 | case /* 8 */ PPCG_FLAG_OP_SUBFE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2410 | /* res <u argR || (old_ca==1 && res==argR) */ |
| 2411 | xer_ca |
| 2412 | = mkOR1( |
| 2413 | binop(Iop_CmpLT32U, res, argR), |
| 2414 | mkAND1( |
| 2415 | binop(Iop_CmpEQ32, oldca, mkU32(1)), |
| 2416 | binop(Iop_CmpEQ32, res, argR) |
| 2417 | ) |
| 2418 | ); |
| 2419 | xer_ca |
| 2420 | = unop(Iop_1Uto32, xer_ca); |
| 2421 | break; |
| 2422 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2423 | case /* 7 */ PPCG_FLAG_OP_SUBFC: |
| 2424 | case /* 9 */ PPCG_FLAG_OP_SUBFI: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2425 | /* res <=u argR */ |
| 2426 | xer_ca |
| 2427 | = unop(Iop_1Uto32, binop(Iop_CmpLE32U, res, argR)); |
| 2428 | break; |
| 2429 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2430 | case /* 10 */ PPCG_FLAG_OP_SRAW: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2431 | /* The shift amount is guaranteed to be in 0 .. 63 inclusive. |
| 2432 | If it is <= 31, behave like SRAWI; else XER.CA is the sign |
| 2433 | bit of argL. */ |
| 2434 | /* This term valid for shift amount < 32 only */ |
| 2435 | xer_ca |
| 2436 | = binop( |
| 2437 | Iop_And32, |
| 2438 | binop(Iop_Sar32, argL, mkU8(31)), |
| 2439 | binop( Iop_And32, |
| 2440 | argL, |
| 2441 | binop( Iop_Sub32, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2442 | binop(Iop_Shl32, mkU32(1), |
| 2443 | unop(Iop_32to8,argR)), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2444 | mkU32(1) ) |
| 2445 | ) |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2446 | ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2447 | xer_ca |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2448 | = IRExpr_ITE( |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2449 | /* shift amt > 31 ? */ |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 2450 | binop(Iop_CmpLT32U, mkU32(31), argR), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2451 | /* yes -- get sign bit of argL */ |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2452 | binop(Iop_Shr32, argL, mkU8(31)), |
| 2453 | /* no -- be like srawi */ |
| 2454 | unop(Iop_1Uto32, binop(Iop_CmpNE32, xer_ca, mkU32(0))) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2455 | ); |
| 2456 | break; |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2457 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2458 | case /* 11 */ PPCG_FLAG_OP_SRAWI: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2459 | /* xer_ca is 1 iff src was negative and bits_shifted_out != |
| 2460 | 0. Since the shift amount is known to be in the range |
| 2461 | 0 .. 31 inclusive the following seems viable: |
| 2462 | xer.ca == 1 iff the following is nonzero: |
| 2463 | (argL >>s 31) -- either all 0s or all 1s |
| 2464 | & (argL & (1<<argR)-1) -- the stuff shifted out */ |
| 2465 | xer_ca |
| 2466 | = binop( |
| 2467 | Iop_And32, |
| 2468 | binop(Iop_Sar32, argL, mkU8(31)), |
| 2469 | binop( Iop_And32, |
| 2470 | argL, |
| 2471 | binop( Iop_Sub32, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2472 | binop(Iop_Shl32, mkU32(1), |
| 2473 | unop(Iop_32to8,argR)), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2474 | mkU32(1) ) |
| 2475 | ) |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2476 | ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2477 | xer_ca |
| 2478 | = unop(Iop_1Uto32, binop(Iop_CmpNE32, xer_ca, mkU32(0))); |
| 2479 | break; |
| 2480 | |
| 2481 | default: |
| 2482 | vex_printf("set_XER_CA: op = %u\n", op); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2483 | vpanic("set_XER_CA(ppc)"); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2484 | } |
| 2485 | |
| 2486 | /* xer_ca MUST denote either 0 or 1, no other value allowed */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2487 | putXER_CA( unop(Iop_32to8, xer_ca) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2488 | } |
| 2489 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2490 | static void set_XER_CA_64 ( UInt op, IRExpr* res, |
| 2491 | IRExpr* argL, IRExpr* argR, IRExpr* oldca ) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2492 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2493 | IRExpr* xer_ca; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2494 | vassert(op < PPCG_FLAG_OP_NUMBER); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2495 | vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64); |
| 2496 | vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64); |
| 2497 | vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64); |
| 2498 | vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I64); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2499 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2500 | /* Incoming oldca is assumed to hold the values 0 or 1 only. This |
| 2501 | seems reasonable given that it's always generated by |
| 2502 | getXER_CA32(), which masks it accordingly. In any case it being |
cerion | 7594920 | 2005-12-24 13:14:11 +0000 | [diff] [blame] | 2503 | 0 or 1 is an invariant of the ppc guest state representation; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2504 | if it has any other value, that invariant has been violated. */ |
| 2505 | |
| 2506 | switch (op) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2507 | case /* 0 */ PPCG_FLAG_OP_ADD: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2508 | /* res <u argL */ |
| 2509 | xer_ca |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2510 | = unop(Iop_1Uto32, binop(Iop_CmpLT64U, res, argL)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2511 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2512 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2513 | case /* 1 */ PPCG_FLAG_OP_ADDE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2514 | /* res <u argL || (old_ca==1 && res==argL) */ |
| 2515 | xer_ca |
| 2516 | = mkOR1( |
| 2517 | binop(Iop_CmpLT64U, res, argL), |
| 2518 | mkAND1( |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2519 | binop(Iop_CmpEQ64, oldca, mkU64(1)), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2520 | binop(Iop_CmpEQ64, res, argL) |
| 2521 | ) |
| 2522 | ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2523 | xer_ca |
| 2524 | = unop(Iop_1Uto32, xer_ca); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2525 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2526 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2527 | case /* 8 */ PPCG_FLAG_OP_SUBFE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2528 | /* res <u argR || (old_ca==1 && res==argR) */ |
| 2529 | xer_ca |
| 2530 | = mkOR1( |
| 2531 | binop(Iop_CmpLT64U, res, argR), |
| 2532 | mkAND1( |
| 2533 | binop(Iop_CmpEQ64, oldca, mkU64(1)), |
| 2534 | binop(Iop_CmpEQ64, res, argR) |
| 2535 | ) |
| 2536 | ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2537 | xer_ca |
| 2538 | = unop(Iop_1Uto32, xer_ca); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2539 | break; |
| 2540 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2541 | case /* 7 */ PPCG_FLAG_OP_SUBFC: |
| 2542 | case /* 9 */ PPCG_FLAG_OP_SUBFI: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2543 | /* res <=u argR */ |
| 2544 | xer_ca |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2545 | = unop(Iop_1Uto32, binop(Iop_CmpLE64U, res, argR)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2546 | break; |
| 2547 | |
| 2548 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2549 | case /* 10 */ PPCG_FLAG_OP_SRAW: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2550 | /* The shift amount is guaranteed to be in 0 .. 31 inclusive. |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2551 | If it is <= 31, behave like SRAWI; else XER.CA is the sign |
| 2552 | bit of argL. */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2553 | /* This term valid for shift amount < 31 only */ |
| 2554 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2555 | xer_ca |
| 2556 | = binop( |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2557 | Iop_And64, |
| 2558 | binop(Iop_Sar64, argL, mkU8(31)), |
| 2559 | binop( Iop_And64, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2560 | argL, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2561 | binop( Iop_Sub64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2562 | binop(Iop_Shl64, mkU64(1), |
| 2563 | unop(Iop_64to8,argR)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2564 | mkU64(1) ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2565 | ) |
| 2566 | ); |
| 2567 | xer_ca |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2568 | = IRExpr_ITE( |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2569 | /* shift amt > 31 ? */ |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 2570 | binop(Iop_CmpLT64U, mkU64(31), argR), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2571 | /* yes -- get sign bit of argL */ |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2572 | unop(Iop_64to32, binop(Iop_Shr64, argL, mkU8(63))), |
| 2573 | /* no -- be like srawi */ |
| 2574 | unop(Iop_1Uto32, binop(Iop_CmpNE64, xer_ca, mkU64(0))) |
| 2575 | ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2576 | break; |
| 2577 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2578 | case /* 11 */ PPCG_FLAG_OP_SRAWI: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2579 | /* xer_ca is 1 iff src was negative and bits_shifted_out != 0. |
| 2580 | Since the shift amount is known to be in the range 0 .. 31 |
| 2581 | inclusive the following seems viable: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2582 | xer.ca == 1 iff the following is nonzero: |
| 2583 | (argL >>s 31) -- either all 0s or all 1s |
| 2584 | & (argL & (1<<argR)-1) -- the stuff shifted out */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2585 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2586 | xer_ca |
| 2587 | = binop( |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2588 | Iop_And64, |
| 2589 | binop(Iop_Sar64, argL, mkU8(31)), |
| 2590 | binop( Iop_And64, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2591 | argL, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2592 | binop( Iop_Sub64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2593 | binop(Iop_Shl64, mkU64(1), |
| 2594 | unop(Iop_64to8,argR)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2595 | mkU64(1) ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2596 | ) |
| 2597 | ); |
| 2598 | xer_ca |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2599 | = unop(Iop_1Uto32, binop(Iop_CmpNE64, xer_ca, mkU64(0))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2600 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2601 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2602 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2603 | case /* 12 */ PPCG_FLAG_OP_SRAD: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2604 | /* The shift amount is guaranteed to be in 0 .. 63 inclusive. |
| 2605 | If it is <= 63, behave like SRADI; else XER.CA is the sign |
| 2606 | bit of argL. */ |
| 2607 | /* This term valid for shift amount < 63 only */ |
| 2608 | |
| 2609 | xer_ca |
| 2610 | = binop( |
| 2611 | Iop_And64, |
| 2612 | binop(Iop_Sar64, argL, mkU8(63)), |
| 2613 | binop( Iop_And64, |
| 2614 | argL, |
| 2615 | binop( Iop_Sub64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2616 | binop(Iop_Shl64, mkU64(1), |
| 2617 | unop(Iop_64to8,argR)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2618 | mkU64(1) ) |
| 2619 | ) |
| 2620 | ); |
| 2621 | xer_ca |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2622 | = IRExpr_ITE( |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2623 | /* shift amt > 63 ? */ |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 2624 | binop(Iop_CmpLT64U, mkU64(63), argR), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2625 | /* yes -- get sign bit of argL */ |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2626 | unop(Iop_64to32, binop(Iop_Shr64, argL, mkU8(63))), |
| 2627 | /* no -- be like sradi */ |
| 2628 | unop(Iop_1Uto32, binop(Iop_CmpNE64, xer_ca, mkU64(0))) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2629 | ); |
| 2630 | break; |
| 2631 | |
| 2632 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2633 | case /* 13 */ PPCG_FLAG_OP_SRADI: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2634 | /* xer_ca is 1 iff src was negative and bits_shifted_out != 0. |
| 2635 | Since the shift amount is known to be in the range 0 .. 63 |
| 2636 | inclusive, the following seems viable: |
| 2637 | xer.ca == 1 iff the following is nonzero: |
| 2638 | (argL >>s 63) -- either all 0s or all 1s |
| 2639 | & (argL & (1<<argR)-1) -- the stuff shifted out */ |
| 2640 | |
| 2641 | xer_ca |
| 2642 | = binop( |
| 2643 | Iop_And64, |
| 2644 | binop(Iop_Sar64, argL, mkU8(63)), |
| 2645 | binop( Iop_And64, |
| 2646 | argL, |
| 2647 | binop( Iop_Sub64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2648 | binop(Iop_Shl64, mkU64(1), |
| 2649 | unop(Iop_64to8,argR)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2650 | mkU64(1) ) |
| 2651 | ) |
| 2652 | ); |
| 2653 | xer_ca |
| 2654 | = unop(Iop_1Uto32, binop(Iop_CmpNE64, xer_ca, mkU64(0))); |
| 2655 | break; |
| 2656 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2657 | default: |
| 2658 | vex_printf("set_XER_CA: op = %u\n", op); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2659 | vpanic("set_XER_CA(ppc64)"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2660 | } |
| 2661 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2662 | /* xer_ca MUST denote either 0 or 1, no other value allowed */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2663 | putXER_CA( unop(Iop_32to8, xer_ca) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2664 | } |
| 2665 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2666 | static void set_XER_CA ( IRType ty, UInt op, IRExpr* res, |
| 2667 | IRExpr* argL, IRExpr* argR, IRExpr* oldca ) |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2668 | { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2669 | if (ty == Ity_I32) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2670 | set_XER_CA_32( op, res, argL, argR, oldca ); |
| 2671 | else |
| 2672 | set_XER_CA_64( op, res, argL, argR, oldca ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2673 | } |
| 2674 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2675 | |
| 2676 | |
| 2677 | /*------------------------------------------------------------*/ |
| 2678 | /*--- Read/write to guest-state --- */ |
| 2679 | /*------------------------------------------------------------*/ |
| 2680 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2681 | static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg ) |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2682 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2683 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2684 | switch (reg) { |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 2685 | case PPC_GST_SPRG3_RO: |
| 2686 | return IRExpr_Get( OFFB_SPRG3_RO, ty ); |
| 2687 | |
| 2688 | case PPC_GST_CIA: |
| 2689 | return IRExpr_Get( OFFB_CIA, ty ); |
| 2690 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2691 | case PPC_GST_LR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2692 | return IRExpr_Get( OFFB_LR, ty ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2693 | |
| 2694 | case PPC_GST_CTR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2695 | return IRExpr_Get( OFFB_CTR, ty ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2696 | |
| 2697 | case PPC_GST_VRSAVE: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2698 | return IRExpr_Get( OFFB_VRSAVE, Ity_I32 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2699 | |
| 2700 | case PPC_GST_VSCR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2701 | return binop(Iop_And32, IRExpr_Get( OFFB_VSCR,Ity_I32 ), |
| 2702 | mkU32(MASK_VSCR_VALID)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2703 | |
| 2704 | case PPC_GST_CR: { |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2705 | /* Synthesise the entire CR into a single word. Expensive. */ |
| 2706 | # define FIELD(_n) \ |
| 2707 | binop(Iop_Shl32, \ |
| 2708 | unop(Iop_8Uto32, \ |
| 2709 | binop(Iop_Or8, \ |
| 2710 | binop(Iop_And8, getCR321(_n), mkU8(7<<1)), \ |
| 2711 | binop(Iop_And8, getCR0(_n), mkU8(1)) \ |
| 2712 | ) \ |
| 2713 | ), \ |
| 2714 | mkU8(4 * (7-(_n))) \ |
| 2715 | ) |
| 2716 | return binop(Iop_Or32, |
| 2717 | binop(Iop_Or32, |
| 2718 | binop(Iop_Or32, FIELD(0), FIELD(1)), |
| 2719 | binop(Iop_Or32, FIELD(2), FIELD(3)) |
| 2720 | ), |
| 2721 | binop(Iop_Or32, |
| 2722 | binop(Iop_Or32, FIELD(4), FIELD(5)), |
| 2723 | binop(Iop_Or32, FIELD(6), FIELD(7)) |
| 2724 | ) |
| 2725 | ); |
| 2726 | # undef FIELD |
| 2727 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2728 | |
| 2729 | case PPC_GST_XER: |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2730 | return binop(Iop_Or32, |
| 2731 | binop(Iop_Or32, |
| 2732 | binop( Iop_Shl32, getXER_SO32(), mkU8(31)), |
| 2733 | binop( Iop_Shl32, getXER_OV32(), mkU8(30))), |
| 2734 | binop(Iop_Or32, |
| 2735 | binop( Iop_Shl32, getXER_CA32(), mkU8(29)), |
| 2736 | getXER_BC32())); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2737 | |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 2738 | case PPC_GST_TFHAR: |
| 2739 | return IRExpr_Get( OFFB_TFHAR, ty ); |
| 2740 | |
| 2741 | case PPC_GST_TEXASR: |
| 2742 | return IRExpr_Get( OFFB_TEXASR, ty ); |
| 2743 | |
| 2744 | case PPC_GST_TFIAR: |
| 2745 | return IRExpr_Get( OFFB_TFIAR, ty ); |
| 2746 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2747 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2748 | vex_printf("getGST(ppc): reg = %u", reg); |
| 2749 | vpanic("getGST(ppc)"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2750 | } |
| 2751 | } |
| 2752 | |
| 2753 | /* Get a masked word from the given reg */ |
| 2754 | static IRExpr* /* ::Ity_I32 */ getGST_masked ( PPC_GST reg, UInt mask ) |
| 2755 | { |
| 2756 | IRTemp val = newTemp(Ity_I32); |
| 2757 | vassert( reg < PPC_GST_MAX ); |
| 2758 | |
| 2759 | switch (reg) { |
| 2760 | |
| 2761 | case PPC_GST_FPSCR: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2762 | /* Vex-generated code expects the FPSCR to be set as follows: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2763 | all exceptions masked, round-to-nearest. |
| 2764 | This corresponds to a FPSCR value of 0x0. */ |
| 2765 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2766 | /* In the lower 32 bits of FPSCR, we're only keeping track of |
| 2767 | * the binary floating point rounding mode, so if the mask isn't |
| 2768 | * asking for this, just return 0x0. |
| 2769 | */ |
| 2770 | if (mask & MASK_FPSCR_RN) { |
| 2771 | assign( val, unop( Iop_8Uto32, IRExpr_Get( OFFB_FPROUND, Ity_I8 ) ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2772 | } else { |
| 2773 | assign( val, mkU32(0x0) ); |
| 2774 | } |
| 2775 | break; |
| 2776 | } |
| 2777 | |
| 2778 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2779 | vex_printf("getGST_masked(ppc): reg = %u", reg); |
| 2780 | vpanic("getGST_masked(ppc)"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2781 | } |
| 2782 | |
| 2783 | if (mask != 0xFFFFFFFF) { |
| 2784 | return binop(Iop_And32, mkexpr(val), mkU32(mask)); |
| 2785 | } else { |
| 2786 | return mkexpr(val); |
| 2787 | } |
| 2788 | } |
| 2789 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2790 | /* Get a masked word from the given reg */ |
| 2791 | static IRExpr* /* ::Ity_I32 */getGST_masked_upper(PPC_GST reg, ULong mask) { |
| 2792 | IRExpr * val; |
| 2793 | vassert( reg < PPC_GST_MAX ); |
| 2794 | |
| 2795 | switch (reg) { |
| 2796 | |
| 2797 | case PPC_GST_FPSCR: { |
| 2798 | /* In the upper 32 bits of FPSCR, we're only keeping track |
| 2799 | * of the decimal floating point rounding mode, so if the mask |
| 2800 | * isn't asking for this, just return 0x0. |
| 2801 | */ |
| 2802 | if (mask & MASK_FPSCR_DRN) { |
| 2803 | val = binop( Iop_And32, |
| 2804 | unop( Iop_8Uto32, IRExpr_Get( OFFB_DFPROUND, Ity_I8 ) ), |
| 2805 | unop( Iop_64HIto32, mkU64( mask ) ) ); |
| 2806 | } else { |
| 2807 | val = mkU32( 0x0ULL ); |
| 2808 | } |
| 2809 | break; |
| 2810 | } |
| 2811 | |
| 2812 | default: |
| 2813 | vex_printf( "getGST_masked_upper(ppc): reg = %u", reg ); |
| 2814 | vpanic( "getGST_masked_upper(ppc)" ); |
| 2815 | } |
| 2816 | return val; |
| 2817 | } |
| 2818 | |
| 2819 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2820 | /* Fetch the specified REG[FLD] nibble (as per IBM/hardware notation) |
| 2821 | and return it at the bottom of an I32; the top 27 bits are |
| 2822 | guaranteed to be zero. */ |
| 2823 | static IRExpr* /* ::Ity_I32 */ getGST_field ( PPC_GST reg, UInt fld ) |
| 2824 | { |
| 2825 | UInt shft, mask; |
| 2826 | |
| 2827 | vassert( fld < 8 ); |
| 2828 | vassert( reg < PPC_GST_MAX ); |
| 2829 | |
| 2830 | shft = 4*(7-fld); |
| 2831 | mask = 0xF<<shft; |
| 2832 | |
| 2833 | switch (reg) { |
| 2834 | case PPC_GST_XER: |
| 2835 | vassert(fld ==7); |
| 2836 | return binop(Iop_Or32, |
| 2837 | binop(Iop_Or32, |
| 2838 | binop(Iop_Shl32, getXER_SO32(), mkU8(3)), |
| 2839 | binop(Iop_Shl32, getXER_OV32(), mkU8(2))), |
| 2840 | binop( Iop_Shl32, getXER_CA32(), mkU8(1))); |
| 2841 | break; |
| 2842 | |
| 2843 | default: |
| 2844 | if (shft == 0) |
| 2845 | return getGST_masked( reg, mask ); |
| 2846 | else |
| 2847 | return binop(Iop_Shr32, |
| 2848 | getGST_masked( reg, mask ), |
| 2849 | mkU8(toUChar( shft ))); |
| 2850 | } |
| 2851 | } |
| 2852 | |
| 2853 | static void putGST ( PPC_GST reg, IRExpr* src ) |
| 2854 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2855 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2856 | IRType ty_src = typeOfIRExpr(irsb->tyenv,src ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2857 | vassert( reg < PPC_GST_MAX ); |
| 2858 | switch (reg) { |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 2859 | case PPC_GST_IP_AT_SYSCALL: |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 2860 | vassert( ty_src == ty ); |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 2861 | stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL, src ) ); |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 2862 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2863 | case PPC_GST_CIA: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2864 | vassert( ty_src == ty ); |
| 2865 | stmt( IRStmt_Put( OFFB_CIA, src ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2866 | break; |
| 2867 | case PPC_GST_LR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2868 | vassert( ty_src == ty ); |
| 2869 | stmt( IRStmt_Put( OFFB_LR, src ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2870 | break; |
| 2871 | case PPC_GST_CTR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2872 | vassert( ty_src == ty ); |
| 2873 | stmt( IRStmt_Put( OFFB_CTR, src ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2874 | break; |
| 2875 | case PPC_GST_VRSAVE: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2876 | vassert( ty_src == Ity_I32 ); |
| 2877 | stmt( IRStmt_Put( OFFB_VRSAVE,src)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2878 | break; |
| 2879 | case PPC_GST_VSCR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2880 | vassert( ty_src == Ity_I32 ); |
| 2881 | stmt( IRStmt_Put( OFFB_VSCR, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2882 | binop(Iop_And32, src, |
| 2883 | mkU32(MASK_VSCR_VALID)) ) ); |
| 2884 | break; |
| 2885 | case PPC_GST_XER: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2886 | vassert( ty_src == Ity_I32 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2887 | putXER_SO( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(31))) ); |
| 2888 | putXER_OV( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(30))) ); |
| 2889 | putXER_CA( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(29))) ); |
| 2890 | putXER_BC( unop(Iop_32to8, src) ); |
| 2891 | break; |
| 2892 | |
| 2893 | case PPC_GST_EMWARN: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2894 | vassert( ty_src == Ity_I32 ); |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 2895 | stmt( IRStmt_Put( OFFB_EMNOTE,src) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2896 | break; |
| 2897 | |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 2898 | case PPC_GST_CMSTART: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2899 | vassert( ty_src == ty ); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 2900 | stmt( IRStmt_Put( OFFB_CMSTART, src) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2901 | break; |
| 2902 | |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 2903 | case PPC_GST_CMLEN: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2904 | vassert( ty_src == ty ); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 2905 | stmt( IRStmt_Put( OFFB_CMLEN, src) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2906 | break; |
| 2907 | |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 2908 | case PPC_GST_TEXASR: |
| 2909 | vassert( ty_src == Ity_I64 ); |
| 2910 | stmt( IRStmt_Put( OFFB_TEXASR, src ) ); |
| 2911 | break; |
| 2912 | case PPC_GST_TFIAR: |
| 2913 | vassert( ty_src == Ity_I64 ); |
| 2914 | stmt( IRStmt_Put( OFFB_TFIAR, src ) ); |
| 2915 | break; |
| 2916 | case PPC_GST_TFHAR: |
| 2917 | vassert( ty_src == Ity_I64 ); |
| 2918 | stmt( IRStmt_Put( OFFB_TFHAR, src ) ); |
| 2919 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2920 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2921 | vex_printf("putGST(ppc): reg = %u", reg); |
| 2922 | vpanic("putGST(ppc)"); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2923 | } |
| 2924 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2925 | |
| 2926 | /* Write masked src to the given reg */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2927 | static void putGST_masked ( PPC_GST reg, IRExpr* src, ULong mask ) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2928 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2929 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 2930 | vassert( reg < PPC_GST_MAX ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2931 | vassert( typeOfIRExpr( irsb->tyenv,src ) == Ity_I64 ); |
| 2932 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2933 | switch (reg) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2934 | case PPC_GST_FPSCR: { |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2935 | /* Allow writes to either binary or decimal floating point |
| 2936 | * Rounding Mode |
| 2937 | */ |
| 2938 | if (mask & MASK_FPSCR_RN) { |
| 2939 | stmt( IRStmt_Put( OFFB_FPROUND, |
| 2940 | unop( Iop_32to8, |
| 2941 | binop( Iop_And32, |
| 2942 | unop( Iop_64to32, src ), |
| 2943 | mkU32( MASK_FPSCR_RN & mask ) ) ) ) ); |
| 2944 | } else if (mask & MASK_FPSCR_DRN) { |
| 2945 | stmt( IRStmt_Put( OFFB_DFPROUND, |
| 2946 | unop( Iop_32to8, |
| 2947 | binop( Iop_And32, |
| 2948 | unop( Iop_64HIto32, src ), |
| 2949 | mkU32( ( MASK_FPSCR_DRN & mask ) |
| 2950 | >> 32 ) ) ) ) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2951 | } |
| 2952 | |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 2953 | /* Give EmNote for attempted writes to: |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2954 | - Exception Controls |
| 2955 | - Non-IEEE Mode |
| 2956 | */ |
| 2957 | if (mask & 0xFC) { // Exception Control, Non-IEE mode |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 2958 | VexEmNote ew = EmWarn_PPCexns; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2959 | |
| 2960 | /* If any of the src::exception_control bits are actually set, |
| 2961 | side-exit to the next insn, reporting the warning, |
| 2962 | so that Valgrind's dispatcher sees the warning. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2963 | putGST( PPC_GST_EMWARN, mkU32(ew) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2964 | stmt( |
| 2965 | IRStmt_Exit( |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 2966 | binop(Iop_CmpNE32, mkU32(ew), mkU32(EmNote_NONE)), |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2967 | Ijk_EmWarn, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 2968 | mkSzConst( ty, nextInsnAddr()), OFFB_CIA )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2969 | } |
| 2970 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2971 | /* Ignore all other writes */ |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2972 | break; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2973 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2974 | |
| 2975 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2976 | vex_printf("putGST_masked(ppc): reg = %u", reg); |
| 2977 | vpanic("putGST_masked(ppc)"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2978 | } |
| 2979 | } |
| 2980 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2981 | /* Write the least significant nibble of src to the specified |
| 2982 | REG[FLD] (as per IBM/hardware notation). */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2983 | static void putGST_field ( PPC_GST reg, IRExpr* src, UInt fld ) |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2984 | { |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2985 | UInt shft; |
| 2986 | ULong mask; |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 2987 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2988 | vassert( typeOfIRExpr(irsb->tyenv,src ) == Ity_I32 ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2989 | vassert( fld < 16 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2990 | vassert( reg < PPC_GST_MAX ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2991 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 2992 | if (fld < 8) |
| 2993 | shft = 4*(7-fld); |
| 2994 | else |
| 2995 | shft = 4*(15-fld); |
florian | 654b7f9 | 2013-02-02 00:10:36 +0000 | [diff] [blame] | 2996 | mask = 0xF; |
| 2997 | mask = mask << shft; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2998 | |
| 2999 | switch (reg) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3000 | case PPC_GST_CR: |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 3001 | putCR0 (fld, binop(Iop_And8, mkU8(1 ), unop(Iop_32to8, src))); |
| 3002 | putCR321(fld, binop(Iop_And8, mkU8(7<<1), unop(Iop_32to8, src))); |
| 3003 | break; |
| 3004 | |
| 3005 | default: |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 3006 | { |
| 3007 | IRExpr * src64 = unop( Iop_32Uto64, src ); |
| 3008 | |
| 3009 | if (shft == 0) { |
| 3010 | putGST_masked( reg, src64, mask ); |
| 3011 | } else { |
| 3012 | putGST_masked( reg, |
| 3013 | binop( Iop_Shl64, src64, mkU8( toUChar( shft ) ) ), |
| 3014 | mask ); |
| 3015 | } |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 3016 | } |
| 3017 | } |
| 3018 | } |
cerion | 62bec57 | 2005-02-01 21:29:39 +0000 | [diff] [blame] | 3019 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3020 | /*------------------------------------------------------------*/ |
| 3021 | /* Helpers for VSX instructions that do floating point |
| 3022 | * operations and need to determine if a src contains a |
| 3023 | * special FP value. |
| 3024 | * |
| 3025 | *------------------------------------------------------------*/ |
| 3026 | |
| 3027 | #define NONZERO_FRAC_MASK 0x000fffffffffffffULL |
| 3028 | #define FP_FRAC_PART(x) binop( Iop_And64, \ |
| 3029 | mkexpr( x ), \ |
| 3030 | mkU64( NONZERO_FRAC_MASK ) ) |
| 3031 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3032 | // Returns exponent part of a single precision floating point as I32 |
| 3033 | static IRExpr * fp_exp_part_sp(IRTemp src) |
| 3034 | { |
| 3035 | return binop( Iop_And32, |
| 3036 | binop( Iop_Shr32, mkexpr( src ), mkU8( 23 ) ), |
| 3037 | mkU32( 0xff ) ); |
| 3038 | } |
| 3039 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3040 | // Returns exponent part of floating point as I32 |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3041 | static IRExpr * fp_exp_part(IRTemp src, Bool sp) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3042 | { |
| 3043 | IRExpr * exp; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3044 | if (sp) |
| 3045 | return fp_exp_part_sp(src); |
| 3046 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3047 | if (!mode64) |
| 3048 | exp = binop( Iop_And32, binop( Iop_Shr32, unop( Iop_64HIto32, |
| 3049 | mkexpr( src ) ), |
| 3050 | mkU8( 20 ) ), mkU32( 0x7ff ) ); |
| 3051 | else |
| 3052 | exp = unop( Iop_64to32, |
| 3053 | binop( Iop_And64, |
| 3054 | binop( Iop_Shr64, mkexpr( src ), mkU8( 52 ) ), |
| 3055 | mkU64( 0x7ff ) ) ); |
| 3056 | return exp; |
| 3057 | } |
| 3058 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3059 | static IRExpr * is_Inf_sp(IRTemp src) |
| 3060 | { |
| 3061 | IRTemp frac_part = newTemp(Ity_I32); |
| 3062 | IRExpr * Inf_exp; |
| 3063 | |
| 3064 | assign( frac_part, binop( Iop_And32, mkexpr(src), mkU32(0x007fffff)) ); |
| 3065 | Inf_exp = binop( Iop_CmpEQ32, fp_exp_part( src, True /*single precision*/ ), mkU32( 0xff ) ); |
| 3066 | return mkAND1( Inf_exp, binop( Iop_CmpEQ32, mkexpr( frac_part ), mkU32( 0 ) ) ); |
| 3067 | } |
| 3068 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3069 | |
| 3070 | // Infinity: exp = 7ff and fraction is zero; s = 0/1 |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3071 | static IRExpr * is_Inf(IRTemp src, Bool sp) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3072 | { |
| 3073 | IRExpr * Inf_exp, * hi32, * low32; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3074 | IRTemp frac_part; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3075 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3076 | if (sp) |
| 3077 | return is_Inf_sp(src); |
| 3078 | |
| 3079 | frac_part = newTemp(Ity_I64); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3080 | assign( frac_part, FP_FRAC_PART(src) ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3081 | Inf_exp = binop( Iop_CmpEQ32, fp_exp_part( src, False /*not single precision*/ ), mkU32( 0x7ff ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3082 | hi32 = unop( Iop_64HIto32, mkexpr( frac_part ) ); |
| 3083 | low32 = unop( Iop_64to32, mkexpr( frac_part ) ); |
| 3084 | return mkAND1( Inf_exp, binop( Iop_CmpEQ32, binop( Iop_Or32, low32, hi32 ), |
| 3085 | mkU32( 0 ) ) ); |
| 3086 | } |
| 3087 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3088 | static IRExpr * is_Zero_sp(IRTemp src) |
| 3089 | { |
| 3090 | IRTemp sign_less_part = newTemp(Ity_I32); |
| 3091 | assign( sign_less_part, binop( Iop_And32, mkexpr( src ), mkU32( SIGN_MASK32 ) ) ); |
| 3092 | return binop( Iop_CmpEQ32, mkexpr( sign_less_part ), mkU32( 0 ) ); |
| 3093 | } |
| 3094 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3095 | // Zero: exp is zero and fraction is zero; s = 0/1 |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3096 | static IRExpr * is_Zero(IRTemp src, Bool sp) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3097 | { |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3098 | IRExpr * hi32, * low32; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3099 | IRTemp sign_less_part; |
| 3100 | if (sp) |
| 3101 | return is_Zero_sp(src); |
| 3102 | |
| 3103 | sign_less_part = newTemp(Ity_I64); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3104 | |
| 3105 | assign( sign_less_part, binop( Iop_And64, mkexpr( src ), mkU64( SIGN_MASK ) ) ); |
| 3106 | hi32 = unop( Iop_64HIto32, mkexpr( sign_less_part ) ); |
| 3107 | low32 = unop( Iop_64to32, mkexpr( sign_less_part ) ); |
| 3108 | return binop( Iop_CmpEQ32, binop( Iop_Or32, low32, hi32 ), |
| 3109 | mkU32( 0 ) ); |
| 3110 | } |
| 3111 | |
| 3112 | /* SNAN: s = 1/0; exp = 0x7ff; fraction is nonzero, with highest bit '1' |
| 3113 | * QNAN: s = 1/0; exp = 0x7ff; fraction is nonzero, with highest bit '0' |
| 3114 | * This function returns an IRExpr value of '1' for any type of NaN. |
| 3115 | */ |
| 3116 | static IRExpr * is_NaN(IRTemp src) |
| 3117 | { |
| 3118 | IRExpr * NaN_exp, * hi32, * low32; |
| 3119 | IRTemp frac_part = newTemp(Ity_I64); |
| 3120 | |
| 3121 | assign( frac_part, FP_FRAC_PART(src) ); |
| 3122 | hi32 = unop( Iop_64HIto32, mkexpr( frac_part ) ); |
| 3123 | low32 = unop( Iop_64to32, mkexpr( frac_part ) ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3124 | NaN_exp = binop( Iop_CmpEQ32, fp_exp_part( src, False /*not single precision*/ ), |
| 3125 | mkU32( 0x7ff ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 3126 | |
| 3127 | return mkAND1( NaN_exp, binop( Iop_CmpNE32, binop( Iop_Or32, low32, hi32 ), |
| 3128 | mkU32( 0 ) ) ); |
| 3129 | } |
cerion | 7622226 | 2005-02-05 13:45:57 +0000 | [diff] [blame] | 3130 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 3131 | /* This function returns an IRExpr value of '1' for any type of NaN. |
| 3132 | * The passed 'src' argument is assumed to be Ity_I32. |
| 3133 | */ |
| 3134 | static IRExpr * is_NaN_32(IRTemp src) |
| 3135 | { |
| 3136 | #define NONZERO_FRAC_MASK32 0x007fffffULL |
| 3137 | #define FP_FRAC_PART32(x) binop( Iop_And32, \ |
| 3138 | mkexpr( x ), \ |
| 3139 | mkU32( NONZERO_FRAC_MASK32 ) ) |
| 3140 | |
| 3141 | IRExpr * frac_part = FP_FRAC_PART32(src); |
| 3142 | IRExpr * exp_part = binop( Iop_And32, |
| 3143 | binop( Iop_Shr32, mkexpr( src ), mkU8( 23 ) ), |
| 3144 | mkU32( 0x0ff ) ); |
| 3145 | IRExpr * NaN_exp = binop( Iop_CmpEQ32, exp_part, mkU32( 0xff ) ); |
| 3146 | |
| 3147 | return mkAND1( NaN_exp, binop( Iop_CmpNE32, frac_part, mkU32( 0 ) ) ); |
| 3148 | } |
| 3149 | |
carll | 6fef87a | 2013-09-12 17:26:42 +0000 | [diff] [blame] | 3150 | /* This function takes an Ity_I32 input argument interpreted |
| 3151 | * as a single-precision floating point value. If src is a |
| 3152 | * SNaN, it is changed to a QNaN and returned; otherwise, |
| 3153 | * the original value is returned. |
| 3154 | */ |
| 3155 | static IRExpr * handle_SNaN_to_QNaN_32(IRExpr * src) |
| 3156 | { |
| 3157 | #define SNAN_MASK32 0x00400000 |
| 3158 | IRTemp tmp = newTemp(Ity_I32); |
| 3159 | IRTemp mask = newTemp(Ity_I32); |
| 3160 | IRTemp is_SNAN = newTemp(Ity_I1); |
| 3161 | |
| 3162 | vassert( typeOfIRExpr(irsb->tyenv, src ) == Ity_I32 ); |
| 3163 | assign(tmp, src); |
| 3164 | |
| 3165 | /* check if input is SNaN, if it is convert to QNaN */ |
| 3166 | assign( is_SNAN, |
| 3167 | mkAND1( is_NaN_32( tmp ), |
| 3168 | binop( Iop_CmpEQ32, |
| 3169 | binop( Iop_And32, mkexpr( tmp ), |
| 3170 | mkU32( SNAN_MASK32 ) ), |
| 3171 | mkU32( 0 ) ) ) ); |
| 3172 | /* create mask with QNaN bit set to make it a QNaN if tmp is SNaN */ |
| 3173 | assign ( mask, binop( Iop_And32, |
| 3174 | unop( Iop_1Sto32, mkexpr( is_SNAN ) ), |
| 3175 | mkU32( SNAN_MASK32 ) ) ); |
| 3176 | return binop( Iop_Or32, mkexpr( mask ), mkexpr( tmp) ); |
| 3177 | } |
| 3178 | |
| 3179 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 3180 | /* This helper function performs the negation part of operations of the form: |
| 3181 | * "Negate Multiply-<op>" |
| 3182 | * where "<op>" is either "Add" or "Sub". |
| 3183 | * |
| 3184 | * This function takes one argument -- the floating point intermediate result (converted to |
| 3185 | * Ity_I64 via Iop_ReinterpF64asI64) that was obtained from the "Multip-<op>" part of |
| 3186 | * the operation described above. |
| 3187 | */ |
| 3188 | static IRTemp getNegatedResult(IRTemp intermediateResult) |
| 3189 | { |
| 3190 | ULong signbit_mask = 0x8000000000000000ULL; |
| 3191 | IRTemp signbit_32 = newTemp(Ity_I32); |
| 3192 | IRTemp resultantSignbit = newTemp(Ity_I1); |
| 3193 | IRTemp negatedResult = newTemp(Ity_I64); |
| 3194 | assign( signbit_32, binop( Iop_Shr32, |
| 3195 | unop( Iop_64HIto32, |
| 3196 | binop( Iop_And64, mkexpr( intermediateResult ), |
| 3197 | mkU64( signbit_mask ) ) ), |
| 3198 | mkU8( 31 ) ) ); |
| 3199 | /* We negate the signbit if and only if the intermediate result from the |
| 3200 | * multiply-<op> was NOT a NaN. This is an XNOR predicate. |
| 3201 | */ |
| 3202 | assign( resultantSignbit, |
| 3203 | unop( Iop_Not1, |
| 3204 | binop( Iop_CmpEQ32, |
| 3205 | binop( Iop_Xor32, |
| 3206 | mkexpr( signbit_32 ), |
| 3207 | unop( Iop_1Uto32, is_NaN( intermediateResult ) ) ), |
| 3208 | mkU32( 1 ) ) ) ); |
| 3209 | |
| 3210 | assign( negatedResult, |
| 3211 | binop( Iop_Or64, |
| 3212 | binop( Iop_And64, |
| 3213 | mkexpr( intermediateResult ), |
| 3214 | mkU64( ~signbit_mask ) ), |
| 3215 | binop( Iop_32HLto64, |
| 3216 | binop( Iop_Shl32, |
| 3217 | unop( Iop_1Uto32, mkexpr( resultantSignbit ) ), |
| 3218 | mkU8( 31 ) ), |
| 3219 | mkU32( 0 ) ) ) ); |
| 3220 | |
| 3221 | return negatedResult; |
| 3222 | } |
| 3223 | |
| 3224 | /* This helper function performs the negation part of operations of the form: |
| 3225 | * "Negate Multiply-<op>" |
| 3226 | * where "<op>" is either "Add" or "Sub". |
| 3227 | * |
| 3228 | * This function takes one argument -- the floating point intermediate result (converted to |
| 3229 | * Ity_I32 via Iop_ReinterpF32asI32) that was obtained from the "Multip-<op>" part of |
| 3230 | * the operation described above. |
| 3231 | */ |
| 3232 | static IRTemp getNegatedResult_32(IRTemp intermediateResult) |
| 3233 | { |
| 3234 | UInt signbit_mask = 0x80000000; |
| 3235 | IRTemp signbit_32 = newTemp(Ity_I32); |
| 3236 | IRTemp resultantSignbit = newTemp(Ity_I1); |
| 3237 | IRTemp negatedResult = newTemp(Ity_I32); |
| 3238 | assign( signbit_32, binop( Iop_Shr32, |
| 3239 | binop( Iop_And32, mkexpr( intermediateResult ), |
| 3240 | mkU32( signbit_mask ) ), |
| 3241 | mkU8( 31 ) ) ); |
| 3242 | /* We negate the signbit if and only if the intermediate result from the |
| 3243 | * multiply-<op> was NOT a NaN. This is an XNOR predicate. |
| 3244 | */ |
| 3245 | assign( resultantSignbit, |
| 3246 | unop( Iop_Not1, |
| 3247 | binop( Iop_CmpEQ32, |
| 3248 | binop( Iop_Xor32, |
| 3249 | mkexpr( signbit_32 ), |
| 3250 | unop( Iop_1Uto32, is_NaN_32( intermediateResult ) ) ), |
| 3251 | mkU32( 1 ) ) ) ); |
| 3252 | |
| 3253 | assign( negatedResult, |
| 3254 | binop( Iop_Or32, |
| 3255 | binop( Iop_And32, |
| 3256 | mkexpr( intermediateResult ), |
| 3257 | mkU32( ~signbit_mask ) ), |
| 3258 | binop( Iop_Shl32, |
| 3259 | unop( Iop_1Uto32, mkexpr( resultantSignbit ) ), |
| 3260 | mkU8( 31 ) ) ) ); |
| 3261 | |
| 3262 | return negatedResult; |
| 3263 | } |
cerion | 7622226 | 2005-02-05 13:45:57 +0000 | [diff] [blame] | 3264 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3265 | /*------------------------------------------------------------*/ |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 3266 | /* Transactional memory helpers |
| 3267 | * |
| 3268 | *------------------------------------------------------------*/ |
| 3269 | |
| 3270 | static ULong generate_TMreason( UInt failure_code, |
| 3271 | UInt persistant, |
| 3272 | UInt nest_overflow, |
| 3273 | UInt tm_exact ) |
| 3274 | { |
| 3275 | ULong tm_err_code = |
| 3276 | ( (ULong) 0) << (63-6) /* Failure code */ |
| 3277 | | ( (ULong) persistant) << (63-7) /* Failure persistant */ |
| 3278 | | ( (ULong) 0) << (63-8) /* Disallowed */ |
| 3279 | | ( (ULong) nest_overflow) << (63-9) /* Nesting Overflow */ |
| 3280 | | ( (ULong) 0) << (63-10) /* Footprint Overflow */ |
| 3281 | | ( (ULong) 0) << (63-11) /* Self-Induced Conflict */ |
| 3282 | | ( (ULong) 0) << (63-12) /* Non-Transactional Conflict */ |
| 3283 | | ( (ULong) 0) << (63-13) /* Transactional Conflict */ |
| 3284 | | ( (ULong) 0) << (63-14) /* Translation Invalidation Conflict */ |
| 3285 | | ( (ULong) 0) << (63-15) /* Implementation-specific */ |
| 3286 | | ( (ULong) 0) << (63-16) /* Instruction Fetch Conflict */ |
| 3287 | | ( (ULong) 0) << (63-30) /* Reserved */ |
| 3288 | | ( (ULong) 0) << (63-31) /* Abort */ |
| 3289 | | ( (ULong) 0) << (63-32) /* Suspend */ |
| 3290 | | ( (ULong) 0) << (63-33) /* Reserved */ |
| 3291 | | ( (ULong) 0) << (63-35) /* Privilege */ |
| 3292 | | ( (ULong) 0) << (63-36) /* Failure Summary */ |
| 3293 | | ( (ULong) tm_exact) << (63-37) /* TFIAR Exact */ |
| 3294 | | ( (ULong) 0) << (63-38) /* ROT */ |
| 3295 | | ( (ULong) 0) << (63-51) /* Reserved */ |
| 3296 | | ( (ULong) 0) << (63-63); /* Transaction Level */ |
| 3297 | |
| 3298 | return tm_err_code; |
| 3299 | } |
| 3300 | |
| 3301 | static void storeTMfailure( Addr64 err_address, ULong tm_reason, |
| 3302 | Addr64 handler_address ) |
| 3303 | { |
| 3304 | putGST( PPC_GST_TFIAR, mkU64( err_address ) ); |
| 3305 | putGST( PPC_GST_TEXASR, mkU64( tm_reason ) ); |
| 3306 | putGST( PPC_GST_TFHAR, mkU64( handler_address ) ); |
| 3307 | } |
| 3308 | |
| 3309 | /*------------------------------------------------------------*/ |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 3310 | /*--- Integer Instruction Translation --- */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3311 | /*------------------------------------------------------------*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 3312 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3313 | /* |
| 3314 | Integer Arithmetic Instructions |
| 3315 | */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 3316 | static Bool dis_int_arith ( UInt theInstr ) |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3317 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3318 | /* D-Form, XO-Form */ |
| 3319 | UChar opc1 = ifieldOPC(theInstr); |
| 3320 | UChar rD_addr = ifieldRegDS(theInstr); |
| 3321 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3322 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3323 | UChar rB_addr = ifieldRegB(theInstr); |
| 3324 | UChar flag_OE = ifieldBIT10(theInstr); |
| 3325 | UInt opc2 = ifieldOPClo9(theInstr); |
| 3326 | UChar flag_rC = ifieldBIT0(theInstr); |
| 3327 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3328 | Long simm16 = extend_s_16to64(uimm16); |
| 3329 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 3330 | IRTemp rA = newTemp(ty); |
| 3331 | IRTemp rB = newTemp(ty); |
| 3332 | IRTemp rD = newTemp(ty); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3333 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3334 | Bool do_rc = False; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3335 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3336 | assign( rA, getIReg(rA_addr) ); |
| 3337 | assign( rB, getIReg(rB_addr) ); // XO-Form: rD, rA, rB |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3338 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3339 | switch (opc1) { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3340 | /* D-Form */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3341 | case 0x0C: // addic (Add Immediate Carrying, PPC32 p351 |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3342 | DIP("addic r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3343 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 3344 | mkSzExtendS16(ty, uimm16) ) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3345 | set_XER_CA( ty, PPCG_FLAG_OP_ADD, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3346 | mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16), |
| 3347 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 3348 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3349 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3350 | case 0x0D: // addic. (Add Immediate Carrying and Record, PPC32 p352) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3351 | DIP("addic. r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3352 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 3353 | mkSzExtendS16(ty, uimm16) ) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3354 | set_XER_CA( ty, PPCG_FLAG_OP_ADD, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3355 | mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16), |
| 3356 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3357 | do_rc = True; // Always record to CR |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3358 | flag_rC = 1; |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 3359 | break; |
| 3360 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3361 | case 0x0E: // addi (Add Immediate, PPC32 p350) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3362 | // li rD,val == addi rD,0,val |
| 3363 | // la disp(rA) == addi rD,rA,disp |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3364 | if ( rA_addr == 0 ) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3365 | DIP("li r%u,%d\n", rD_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3366 | assign( rD, mkSzExtendS16(ty, uimm16) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3367 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3368 | DIP("addi r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3369 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 3370 | mkSzExtendS16(ty, uimm16) ) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3371 | } |
| 3372 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3373 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3374 | case 0x0F: // addis (Add Immediate Shifted, PPC32 p353) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3375 | // lis rD,val == addis rD,0,val |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3376 | if ( rA_addr == 0 ) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3377 | DIP("lis r%u,%d\n", rD_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3378 | assign( rD, mkSzExtendS32(ty, uimm16 << 16) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3379 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3380 | DIP("addis r%u,r%u,0x%x\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3381 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 3382 | mkSzExtendS32(ty, uimm16 << 16) ) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3383 | } |
| 3384 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3385 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3386 | case 0x07: // mulli (Multiply Low Immediate, PPC32 p490) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3387 | DIP("mulli r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
| 3388 | if (mode64) |
| 3389 | assign( rD, unop(Iop_128to64, |
| 3390 | binop(Iop_MullS64, mkexpr(rA), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3391 | mkSzExtendS16(ty, uimm16))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3392 | else |
| 3393 | assign( rD, unop(Iop_64to32, |
| 3394 | binop(Iop_MullS32, mkexpr(rA), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3395 | mkSzExtendS16(ty, uimm16))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3396 | break; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 3397 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3398 | case 0x08: // subfic (Subtract from Immediate Carrying, PPC32 p540) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3399 | DIP("subfic r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3400 | // rD = simm16 - rA |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3401 | assign( rD, binop( mkSzOp(ty, Iop_Sub8), |
| 3402 | mkSzExtendS16(ty, uimm16), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3403 | mkexpr(rA)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3404 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFI, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3405 | mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16), |
| 3406 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3407 | break; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 3408 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3409 | /* XO-Form */ |
| 3410 | case 0x1F: |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3411 | do_rc = True; // All below record to CR |
| 3412 | |
| 3413 | switch (opc2) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3414 | case 0x10A: // add (Add, PPC32 p347) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3415 | DIP("add%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3416 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3417 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3418 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3419 | mkexpr(rA), mkexpr(rB) ) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3420 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3421 | set_XER_OV( ty, PPCG_FLAG_OP_ADD, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3422 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3423 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3424 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3425 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3426 | case 0x00A: // addc (Add Carrying, PPC32 p348) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3427 | DIP("addc%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3428 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3429 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3430 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3431 | mkexpr(rA), mkexpr(rB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3432 | set_XER_CA( ty, PPCG_FLAG_OP_ADD, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3433 | mkexpr(rD), mkexpr(rA), mkexpr(rB), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3434 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3435 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3436 | set_XER_OV( ty, PPCG_FLAG_OP_ADD, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3437 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3438 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3439 | break; |
| 3440 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3441 | case 0x08A: { // adde (Add Extended, PPC32 p349) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3442 | IRTemp old_xer_ca = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3443 | DIP("adde%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3444 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3445 | rD_addr, rA_addr, rB_addr); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3446 | // rD = rA + rB + XER[CA] |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3447 | assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3448 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 3449 | binop( mkSzOp(ty, Iop_Add8), |
| 3450 | mkexpr(rB), mkexpr(old_xer_ca))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3451 | set_XER_CA( ty, PPCG_FLAG_OP_ADDE, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3452 | mkexpr(rD), mkexpr(rA), mkexpr(rB), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3453 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3454 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3455 | set_XER_OV( ty, PPCG_FLAG_OP_ADDE, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3456 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3457 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3458 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3459 | } |
| 3460 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3461 | case 0x0EA: { // addme (Add to Minus One Extended, PPC32 p354) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3462 | IRTemp old_xer_ca = newTemp(ty); |
| 3463 | IRExpr *min_one; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3464 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3465 | vex_printf("dis_int_arith(ppc)(addme,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3466 | return False; |
| 3467 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3468 | DIP("addme%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3469 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3470 | rD_addr, rA_addr, rB_addr); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3471 | // rD = rA + (-1) + XER[CA] |
| 3472 | // => Just another form of adde |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3473 | assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3474 | min_one = mkSzImm(ty, (Long)-1); |
| 3475 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 3476 | binop( mkSzOp(ty, Iop_Add8), |
| 3477 | min_one, mkexpr(old_xer_ca)) )); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3478 | set_XER_CA( ty, PPCG_FLAG_OP_ADDE, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3479 | mkexpr(rD), mkexpr(rA), min_one, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3480 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3481 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3482 | set_XER_OV( ty, PPCG_FLAG_OP_ADDE, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3483 | mkexpr(rD), mkexpr(rA), min_one ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3484 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3485 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3486 | } |
| 3487 | |
| 3488 | case 0x0CA: { // addze (Add to Zero Extended, PPC32 p355) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3489 | IRTemp old_xer_ca = newTemp(ty); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3490 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3491 | vex_printf("dis_int_arith(ppc)(addze,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3492 | return False; |
| 3493 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3494 | DIP("addze%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3495 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3496 | rD_addr, rA_addr, rB_addr); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3497 | // rD = rA + (0) + XER[CA] |
| 3498 | // => Just another form of adde |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3499 | assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3500 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 3501 | mkexpr(rA), mkexpr(old_xer_ca)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3502 | set_XER_CA( ty, PPCG_FLAG_OP_ADDE, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3503 | mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0), |
| 3504 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3505 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3506 | set_XER_OV( ty, PPCG_FLAG_OP_ADDE, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3507 | mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3508 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3509 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3510 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3511 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3512 | case 0x1EB: // divw (Divide Word, PPC32 p388) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3513 | DIP("divw%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3514 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3515 | rD_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3516 | if (mode64) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3517 | /* Note: |
| 3518 | XER settings are mode independent, and reflect the |
| 3519 | overflow of the low-order 32bit result |
| 3520 | CR0[LT|GT|EQ] are undefined if flag_rC && mode64 |
| 3521 | */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3522 | /* rD[hi32] are undefined: setting them to sign of lo32 |
| 3523 | - makes set_CR0 happy */ |
| 3524 | IRExpr* dividend = mk64lo32Sto64( mkexpr(rA) ); |
| 3525 | IRExpr* divisor = mk64lo32Sto64( mkexpr(rB) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3526 | assign( rD, mk64lo32Uto64( binop(Iop_DivS64, dividend, |
| 3527 | divisor) ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3528 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3529 | set_XER_OV( ty, PPCG_FLAG_OP_DIVW, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3530 | mkexpr(rD), dividend, divisor ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3531 | } |
| 3532 | } else { |
| 3533 | assign( rD, binop(Iop_DivS32, mkexpr(rA), mkexpr(rB)) ); |
| 3534 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3535 | set_XER_OV( ty, PPCG_FLAG_OP_DIVW, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3536 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 3537 | } |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3538 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3539 | /* Note: |
| 3540 | if (0x8000_0000 / -1) or (x / 0) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3541 | => rD=undef, if(flag_rC) CR7=undef, if(flag_OE) XER_OV=1 |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3542 | => But _no_ exception raised. */ |
| 3543 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3544 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3545 | case 0x1CB: // divwu (Divide Word Unsigned, PPC32 p389) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3546 | DIP("divwu%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3547 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3548 | rD_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3549 | if (mode64) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3550 | /* Note: |
| 3551 | XER settings are mode independent, and reflect the |
| 3552 | overflow of the low-order 32bit result |
| 3553 | CR0[LT|GT|EQ] are undefined if flag_rC && mode64 |
| 3554 | */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3555 | IRExpr* dividend = mk64lo32Uto64( mkexpr(rA) ); |
| 3556 | IRExpr* divisor = mk64lo32Uto64( mkexpr(rB) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3557 | assign( rD, mk64lo32Uto64( binop(Iop_DivU64, dividend, |
| 3558 | divisor) ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3559 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3560 | set_XER_OV( ty, PPCG_FLAG_OP_DIVWU, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3561 | mkexpr(rD), dividend, divisor ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3562 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3563 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3564 | assign( rD, binop(Iop_DivU32, mkexpr(rA), mkexpr(rB)) ); |
| 3565 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3566 | set_XER_OV( ty, PPCG_FLAG_OP_DIVWU, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3567 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 3568 | } |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3569 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3570 | /* Note: ditto comment divw, for (x / 0) */ |
| 3571 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3572 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3573 | case 0x04B: // mulhw (Multiply High Word, PPC32 p488) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3574 | if (flag_OE != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3575 | vex_printf("dis_int_arith(ppc)(mulhw,flag_OE)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3576 | return False; |
| 3577 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3578 | DIP("mulhw%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3579 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3580 | if (mode64) { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3581 | /* rD[hi32] are undefined: setting them to sign of lo32 |
| 3582 | - makes set_CR0 happy */ |
| 3583 | assign( rD, binop(Iop_Sar64, |
| 3584 | binop(Iop_Mul64, |
| 3585 | mk64lo32Sto64( mkexpr(rA) ), |
| 3586 | mk64lo32Sto64( mkexpr(rB) )), |
| 3587 | mkU8(32)) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3588 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3589 | assign( rD, unop(Iop_64HIto32, |
| 3590 | binop(Iop_MullS32, |
| 3591 | mkexpr(rA), mkexpr(rB))) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3592 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3593 | break; |
cerion | c19d5e1 | 2005-02-01 15:56:25 +0000 | [diff] [blame] | 3594 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3595 | case 0x00B: // mulhwu (Multiply High Word Unsigned, PPC32 p489) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3596 | if (flag_OE != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3597 | vex_printf("dis_int_arith(ppc)(mulhwu,flag_OE)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3598 | return False; |
| 3599 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3600 | DIP("mulhwu%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3601 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3602 | if (mode64) { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3603 | /* rD[hi32] are undefined: setting them to sign of lo32 |
| 3604 | - makes set_CR0 happy */ |
| 3605 | assign( rD, binop(Iop_Sar64, |
| 3606 | binop(Iop_Mul64, |
| 3607 | mk64lo32Uto64( mkexpr(rA) ), |
| 3608 | mk64lo32Uto64( mkexpr(rB) ) ), |
| 3609 | mkU8(32)) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3610 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3611 | assign( rD, unop(Iop_64HIto32, |
| 3612 | binop(Iop_MullU32, |
| 3613 | mkexpr(rA), mkexpr(rB))) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3614 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3615 | break; |
| 3616 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3617 | case 0x0EB: // mullw (Multiply Low Word, PPC32 p491) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3618 | DIP("mullw%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3619 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3620 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3621 | if (mode64) { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3622 | /* rD[hi32] are undefined: setting them to sign of lo32 |
| 3623 | - set_XER_OV() and set_CR0() depend on this */ |
| 3624 | IRExpr *a = unop(Iop_64to32, mkexpr(rA) ); |
| 3625 | IRExpr *b = unop(Iop_64to32, mkexpr(rB) ); |
| 3626 | assign( rD, binop(Iop_MullS32, a, b) ); |
| 3627 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3628 | set_XER_OV( ty, PPCG_FLAG_OP_MULLW, |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3629 | mkexpr(rD), |
| 3630 | unop(Iop_32Uto64, a), unop(Iop_32Uto64, b) ); |
| 3631 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3632 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3633 | assign( rD, unop(Iop_64to32, |
| 3634 | binop(Iop_MullU32, |
| 3635 | mkexpr(rA), mkexpr(rB))) ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3636 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3637 | set_XER_OV( ty, PPCG_FLAG_OP_MULLW, |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3638 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 3639 | } |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3640 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3641 | break; |
cerion | c19d5e1 | 2005-02-01 15:56:25 +0000 | [diff] [blame] | 3642 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3643 | case 0x068: // neg (Negate, PPC32 p493) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3644 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3645 | vex_printf("dis_int_arith(ppc)(neg,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3646 | return False; |
| 3647 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3648 | DIP("neg%s%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3649 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3650 | rD_addr, rA_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3651 | // rD = (~rA) + 1 |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3652 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 3653 | unop( mkSzOp(ty, Iop_Not8), mkexpr(rA) ), |
| 3654 | mkSzImm(ty, 1)) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3655 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3656 | set_XER_OV( ty, PPCG_FLAG_OP_NEG, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3657 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3658 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3659 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3660 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3661 | case 0x028: // subf (Subtract From, PPC32 p537) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3662 | DIP("subf%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3663 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3664 | rD_addr, rA_addr, rB_addr); |
cerion | 0190847 | 2005-02-25 16:43:08 +0000 | [diff] [blame] | 3665 | // rD = rB - rA |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3666 | assign( rD, binop( mkSzOp(ty, Iop_Sub8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3667 | mkexpr(rB), mkexpr(rA)) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3668 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3669 | set_XER_OV( ty, PPCG_FLAG_OP_SUBF, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3670 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3671 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3672 | break; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 3673 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3674 | case 0x008: // subfc (Subtract from Carrying, PPC32 p538) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3675 | DIP("subfc%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3676 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3677 | rD_addr, rA_addr, rB_addr); |
cerion | 0190847 | 2005-02-25 16:43:08 +0000 | [diff] [blame] | 3678 | // rD = rB - rA |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3679 | assign( rD, binop( mkSzOp(ty, Iop_Sub8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3680 | mkexpr(rB), mkexpr(rA)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3681 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFC, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3682 | mkexpr(rD), mkexpr(rA), mkexpr(rB), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3683 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3684 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3685 | set_XER_OV( ty, PPCG_FLAG_OP_SUBFC, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3686 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3687 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3688 | break; |
| 3689 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3690 | case 0x088: {// subfe (Subtract from Extended, PPC32 p539) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3691 | IRTemp old_xer_ca = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3692 | DIP("subfe%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3693 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3694 | rD_addr, rA_addr, rB_addr); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3695 | // rD = (log not)rA + rB + XER[CA] |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3696 | assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3697 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 3698 | unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)), |
| 3699 | binop( mkSzOp(ty, Iop_Add8), |
| 3700 | mkexpr(rB), mkexpr(old_xer_ca))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3701 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFE, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3702 | mkexpr(rD), mkexpr(rA), mkexpr(rB), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3703 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3704 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3705 | set_XER_OV( ty, PPCG_FLAG_OP_SUBFE, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3706 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3707 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3708 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3709 | } |
| 3710 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3711 | case 0x0E8: { // subfme (Subtract from -1 Extended, PPC32 p541) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3712 | IRTemp old_xer_ca = newTemp(ty); |
| 3713 | IRExpr *min_one; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3714 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3715 | vex_printf("dis_int_arith(ppc)(subfme,rB_addr)\n"); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 3716 | return False; |
| 3717 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3718 | DIP("subfme%s%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3719 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3720 | rD_addr, rA_addr); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 3721 | // rD = (log not)rA + (-1) + XER[CA] |
| 3722 | // => Just another form of subfe |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3723 | assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3724 | min_one = mkSzImm(ty, (Long)-1); |
| 3725 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 3726 | unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)), |
| 3727 | binop( mkSzOp(ty, Iop_Add8), |
| 3728 | min_one, mkexpr(old_xer_ca))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3729 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFE, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3730 | mkexpr(rD), mkexpr(rA), min_one, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3731 | mkexpr(old_xer_ca) ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 3732 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3733 | set_XER_OV( ty, PPCG_FLAG_OP_SUBFE, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3734 | mkexpr(rD), mkexpr(rA), min_one ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 3735 | } |
| 3736 | break; |
| 3737 | } |
| 3738 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3739 | case 0x0C8: { // subfze (Subtract from Zero Extended, PPC32 p542) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3740 | IRTemp old_xer_ca = newTemp(ty); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3741 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3742 | vex_printf("dis_int_arith(ppc)(subfze,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3743 | return False; |
| 3744 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3745 | DIP("subfze%s%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3746 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3747 | rD_addr, rA_addr); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3748 | // rD = (log not)rA + (0) + XER[CA] |
| 3749 | // => Just another form of subfe |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3750 | assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3751 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 3752 | unop( mkSzOp(ty, Iop_Not8), |
| 3753 | mkexpr(rA)), mkexpr(old_xer_ca)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3754 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFE, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3755 | mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0), |
| 3756 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3757 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3758 | set_XER_OV( ty, PPCG_FLAG_OP_SUBFE, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3759 | mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3760 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3761 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3762 | } |
cerion | ae69462 | 2005-01-28 17:52:47 +0000 | [diff] [blame] | 3763 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3764 | |
| 3765 | /* 64bit Arithmetic */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3766 | case 0x49: // mulhd (Multiply High DWord, PPC64 p539) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3767 | if (flag_OE != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3768 | vex_printf("dis_int_arith(ppc)(mulhd,flagOE)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3769 | return False; |
| 3770 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3771 | DIP("mulhd%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3772 | rD_addr, rA_addr, rB_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3773 | assign( rD, unop(Iop_128HIto64, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3774 | binop(Iop_MullS64, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3775 | mkexpr(rA), mkexpr(rB))) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3776 | |
| 3777 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3778 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3779 | case 0x9: // mulhdu (Multiply High DWord Unsigned, PPC64 p540) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3780 | if (flag_OE != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3781 | vex_printf("dis_int_arith(ppc)(mulhdu,flagOE)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3782 | return False; |
| 3783 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3784 | DIP("mulhdu%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3785 | rD_addr, rA_addr, rB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3786 | assign( rD, unop(Iop_128HIto64, |
| 3787 | binop(Iop_MullU64, |
| 3788 | mkexpr(rA), mkexpr(rB))) ); |
| 3789 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3790 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3791 | case 0xE9: // mulld (Multiply Low DWord, PPC64 p543) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3792 | DIP("mulld%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3793 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3794 | rD_addr, rA_addr, rB_addr); |
| 3795 | assign( rD, binop(Iop_Mul64, mkexpr(rA), mkexpr(rB)) ); |
| 3796 | if (flag_OE) { |
carll | 38b79ac | 2013-09-06 22:27:34 +0000 | [diff] [blame] | 3797 | set_XER_OV( ty, PPCG_FLAG_OP_MULLD, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3798 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 3799 | } |
| 3800 | break; |
| 3801 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3802 | case 0x1E9: // divd (Divide DWord, PPC64 p419) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3803 | DIP("divd%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3804 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3805 | rD_addr, rA_addr, rB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3806 | assign( rD, binop(Iop_DivS64, mkexpr(rA), mkexpr(rB)) ); |
| 3807 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3808 | set_XER_OV( ty, PPCG_FLAG_OP_DIVW, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3809 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 3810 | } |
| 3811 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3812 | /* Note: |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3813 | if (0x8000_0000_0000_0000 / -1) or (x / 0) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3814 | => rD=undef, if(flag_rC) CR7=undef, if(flag_OE) XER_OV=1 |
| 3815 | => But _no_ exception raised. */ |
| 3816 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3817 | case 0x1C9: // divdu (Divide DWord Unsigned, PPC64 p420) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3818 | DIP("divdu%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3819 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3820 | rD_addr, rA_addr, rB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3821 | assign( rD, binop(Iop_DivU64, mkexpr(rA), mkexpr(rB)) ); |
| 3822 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3823 | set_XER_OV( ty, PPCG_FLAG_OP_DIVWU, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3824 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 3825 | } |
| 3826 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3827 | /* Note: ditto comment divd, for (x / 0) */ |
| 3828 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 3829 | case 0x18B: // divweu (Divide Word Extended Unsigned) |
| 3830 | { |
| 3831 | /* |
| 3832 | * If (RA) >= (RB), or if an attempt is made to perform the division |
| 3833 | * <anything> / 0 |
| 3834 | * then the contents of register RD are undefined as are (if Rc=1) the contents of |
| 3835 | * the LT, GT, and EQ bits of CR Field 0. In these cases, if OE=1 then OV is set |
| 3836 | * to 1. |
| 3837 | */ |
| 3838 | IRTemp res = newTemp(Ity_I32); |
| 3839 | IRExpr * dividend, * divisor; |
| 3840 | DIP("divweu%s%s r%u,r%u,r%u\n", |
| 3841 | flag_OE ? "o" : "", flag_rC ? ".":"", |
| 3842 | rD_addr, rA_addr, rB_addr); |
| 3843 | if (mode64) { |
| 3844 | dividend = unop( Iop_64to32, mkexpr( rA ) ); |
| 3845 | divisor = unop( Iop_64to32, mkexpr( rB ) ); |
| 3846 | assign( res, binop( Iop_DivU32E, dividend, divisor ) ); |
| 3847 | assign( rD, binop( Iop_32HLto64, mkU32( 0 ), mkexpr( res ) ) ); |
| 3848 | } else { |
| 3849 | dividend = mkexpr( rA ); |
| 3850 | divisor = mkexpr( rB ); |
| 3851 | assign( res, binop( Iop_DivU32E, dividend, divisor ) ); |
| 3852 | assign( rD, mkexpr( res) ); |
| 3853 | } |
| 3854 | |
| 3855 | if (flag_OE) { |
| 3856 | set_XER_OV_32( PPCG_FLAG_OP_DIVWEU, |
| 3857 | mkexpr(res), dividend, divisor ); |
| 3858 | } |
| 3859 | break; |
| 3860 | } |
| 3861 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3862 | case 0x1AB: // divwe (Divide Word Extended) |
| 3863 | { |
| 3864 | /* |
| 3865 | * If the quotient cannot be represented in 32 bits, or if an |
| 3866 | * attempt is made to perform the division |
| 3867 | * <anything> / 0 |
| 3868 | * then the contents of register RD are undefined as are (if |
| 3869 | * Rc=1) the contents of the LT, GT, and EQ bits of CR |
| 3870 | * Field 0. In these cases, if OE=1 then OV is set to 1. |
| 3871 | */ |
| 3872 | |
| 3873 | IRTemp res = newTemp(Ity_I32); |
| 3874 | IRExpr * dividend, * divisor; |
| 3875 | DIP("divwe%s%s r%u,r%u,r%u\n", |
| 3876 | flag_OE ? "o" : "", flag_rC ? ".":"", |
| 3877 | rD_addr, rA_addr, rB_addr); |
| 3878 | if (mode64) { |
| 3879 | dividend = unop( Iop_64to32, mkexpr( rA ) ); |
| 3880 | divisor = unop( Iop_64to32, mkexpr( rB ) ); |
| 3881 | assign( res, binop( Iop_DivS32E, dividend, divisor ) ); |
| 3882 | assign( rD, binop( Iop_32HLto64, mkU32( 0 ), mkexpr( res ) ) ); |
| 3883 | } else { |
| 3884 | dividend = mkexpr( rA ); |
| 3885 | divisor = mkexpr( rB ); |
| 3886 | assign( res, binop( Iop_DivS32E, dividend, divisor ) ); |
| 3887 | assign( rD, mkexpr( res) ); |
| 3888 | } |
| 3889 | |
| 3890 | if (flag_OE) { |
| 3891 | set_XER_OV_32( PPCG_FLAG_OP_DIVWE, |
| 3892 | mkexpr(res), dividend, divisor ); |
| 3893 | } |
| 3894 | break; |
| 3895 | } |
| 3896 | |
| 3897 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 3898 | case 0x1A9: // divde (Divide Doubleword Extended) |
| 3899 | /* |
| 3900 | * If the quotient cannot be represented in 64 bits, or if an |
| 3901 | * attempt is made to perform the division |
| 3902 | * <anything> / 0 |
| 3903 | * then the contents of register RD are undefined as are (if |
| 3904 | * Rc=1) the contents of the LT, GT, and EQ bits of CR |
| 3905 | * Field 0. In these cases, if OE=1 then OV is set to 1. |
| 3906 | */ |
| 3907 | DIP("divde%s%s r%u,r%u,r%u\n", |
| 3908 | flag_OE ? "o" : "", flag_rC ? ".":"", |
| 3909 | rD_addr, rA_addr, rB_addr); |
| 3910 | assign( rD, binop(Iop_DivS64E, mkexpr(rA), mkexpr(rB)) ); |
| 3911 | if (flag_OE) { |
| 3912 | set_XER_OV_64( PPCG_FLAG_OP_DIVDE, mkexpr( rD ), |
| 3913 | mkexpr( rA ), mkexpr( rB ) ); |
| 3914 | } |
| 3915 | break; |
| 3916 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 3917 | case 0x189: // divdeuo (Divide Doubleword Extended Unsigned) |
| 3918 | // Same CR and OV rules as given for divweu above |
| 3919 | DIP("divdeu%s%s r%u,r%u,r%u\n", |
| 3920 | flag_OE ? "o" : "", flag_rC ? ".":"", |
| 3921 | rD_addr, rA_addr, rB_addr); |
| 3922 | assign( rD, binop(Iop_DivU64E, mkexpr(rA), mkexpr(rB)) ); |
| 3923 | if (flag_OE) { |
| 3924 | set_XER_OV_64( PPCG_FLAG_OP_DIVDEU, mkexpr( rD ), |
| 3925 | mkexpr( rA ), mkexpr( rB ) ); |
| 3926 | } |
| 3927 | break; |
| 3928 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3929 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3930 | vex_printf("dis_int_arith(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3931 | return False; |
| 3932 | } |
| 3933 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3934 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3935 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3936 | vex_printf("dis_int_arith(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3937 | return False; |
| 3938 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3939 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3940 | putIReg( rD_addr, mkexpr(rD) ); |
| 3941 | |
| 3942 | if (do_rc && flag_rC) { |
| 3943 | set_CR0( mkexpr(rD) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3944 | } |
| 3945 | return True; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 3946 | } |
| 3947 | |
| 3948 | |
| 3949 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 3950 | /* |
| 3951 | Integer Compare Instructions |
| 3952 | */ |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3953 | static Bool dis_int_cmp ( UInt theInstr ) |
| 3954 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3955 | /* D-Form, X-Form */ |
| 3956 | UChar opc1 = ifieldOPC(theInstr); |
| 3957 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 3958 | UChar b22 = toUChar( IFIELD( theInstr, 22, 1 ) ); |
| 3959 | UChar flag_L = toUChar( IFIELD( theInstr, 21, 1 ) ); |
| 3960 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3961 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3962 | UChar rB_addr = ifieldRegB(theInstr); |
| 3963 | UInt opc2 = ifieldOPClo10(theInstr); |
| 3964 | UChar b0 = ifieldBIT0(theInstr); |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3965 | |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3966 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 3967 | IRExpr *a = getIReg(rA_addr); |
| 3968 | IRExpr *b; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3969 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3970 | if (!mode64 && flag_L==1) { // L==1 invalid for 32 bit. |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3971 | vex_printf("dis_int_cmp(ppc)(flag_L)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3972 | return False; |
| 3973 | } |
| 3974 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3975 | if (b22 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3976 | vex_printf("dis_int_cmp(ppc)(b22)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3977 | return False; |
| 3978 | } |
| 3979 | |
| 3980 | switch (opc1) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3981 | case 0x0B: // cmpi (Compare Immediate, PPC32 p368) |
| 3982 | DIP("cmpi cr%u,%u,r%u,%d\n", crfD, flag_L, rA_addr, |
| 3983 | (Int)extend_s_16to32(uimm16)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3984 | b = mkSzExtendS16( ty, uimm16 ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3985 | if (flag_L == 1) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3986 | putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64S, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3987 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3988 | a = mkNarrowTo32( ty, a ); |
| 3989 | b = mkNarrowTo32( ty, b ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3990 | putCR321(crfD, unop(Iop_32to8, binop(Iop_CmpORD32S, a, b))); |
| 3991 | } |
| 3992 | putCR0( crfD, getXER_SO() ); |
| 3993 | break; |
| 3994 | |
| 3995 | case 0x0A: // cmpli (Compare Logical Immediate, PPC32 p370) |
| 3996 | DIP("cmpli cr%u,%u,r%u,0x%x\n", crfD, flag_L, rA_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3997 | b = mkSzImm( ty, uimm16 ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3998 | if (flag_L == 1) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3999 | putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64U, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4000 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4001 | a = mkNarrowTo32( ty, a ); |
| 4002 | b = mkNarrowTo32( ty, b ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4003 | putCR321(crfD, unop(Iop_32to8, binop(Iop_CmpORD32U, a, b))); |
| 4004 | } |
| 4005 | putCR0( crfD, getXER_SO() ); |
| 4006 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4007 | |
| 4008 | /* X Form */ |
| 4009 | case 0x1F: |
| 4010 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4011 | vex_printf("dis_int_cmp(ppc)(0x1F,b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4012 | return False; |
| 4013 | } |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4014 | b = getIReg(rB_addr); |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4015 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4016 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4017 | case 0x000: // cmp (Compare, PPC32 p367) |
| 4018 | DIP("cmp cr%u,%u,r%u,r%u\n", crfD, flag_L, rA_addr, rB_addr); |
sewardj | a9cb67b | 2006-08-19 18:31:53 +0000 | [diff] [blame] | 4019 | /* Comparing a reg with itself produces a result which |
| 4020 | doesn't depend on the contents of the reg. Therefore |
| 4021 | remove the false dependency, which has been known to cause |
| 4022 | memcheck to produce false errors. */ |
sewardj | 9195aa1 | 2006-08-19 22:18:53 +0000 | [diff] [blame] | 4023 | if (rA_addr == rB_addr) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 4024 | a = b = typeOfIRExpr(irsb->tyenv,a) == Ity_I64 |
sewardj | 9195aa1 | 2006-08-19 22:18:53 +0000 | [diff] [blame] | 4025 | ? mkU64(0) : mkU32(0); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4026 | if (flag_L == 1) { |
| 4027 | putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64S, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4028 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4029 | a = mkNarrowTo32( ty, a ); |
| 4030 | b = mkNarrowTo32( ty, b ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4031 | putCR321(crfD, unop(Iop_32to8,binop(Iop_CmpORD32S, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4032 | } |
| 4033 | putCR0( crfD, getXER_SO() ); |
| 4034 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4035 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4036 | case 0x020: // cmpl (Compare Logical, PPC32 p369) |
| 4037 | DIP("cmpl cr%u,%u,r%u,r%u\n", crfD, flag_L, rA_addr, rB_addr); |
sewardj | a9cb67b | 2006-08-19 18:31:53 +0000 | [diff] [blame] | 4038 | /* Comparing a reg with itself produces a result which |
| 4039 | doesn't depend on the contents of the reg. Therefore |
| 4040 | remove the false dependency, which has been known to cause |
| 4041 | memcheck to produce false errors. */ |
sewardj | 9195aa1 | 2006-08-19 22:18:53 +0000 | [diff] [blame] | 4042 | if (rA_addr == rB_addr) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 4043 | a = b = typeOfIRExpr(irsb->tyenv,a) == Ity_I64 |
sewardj | 9195aa1 | 2006-08-19 22:18:53 +0000 | [diff] [blame] | 4044 | ? mkU64(0) : mkU32(0); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4045 | if (flag_L == 1) { |
| 4046 | putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64U, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4047 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4048 | a = mkNarrowTo32( ty, a ); |
| 4049 | b = mkNarrowTo32( ty, b ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4050 | putCR321(crfD, unop(Iop_32to8, binop(Iop_CmpORD32U, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4051 | } |
| 4052 | putCR0( crfD, getXER_SO() ); |
| 4053 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4054 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4055 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4056 | vex_printf("dis_int_cmp(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4057 | return False; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4058 | } |
| 4059 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4060 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4061 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4062 | vex_printf("dis_int_cmp(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4063 | return False; |
| 4064 | } |
| 4065 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4066 | return True; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4067 | } |
| 4068 | |
| 4069 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 4070 | /* |
| 4071 | Integer Logical Instructions |
| 4072 | */ |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4073 | static Bool dis_int_logic ( UInt theInstr ) |
| 4074 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4075 | /* D-Form, X-Form */ |
| 4076 | UChar opc1 = ifieldOPC(theInstr); |
| 4077 | UChar rS_addr = ifieldRegDS(theInstr); |
| 4078 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4079 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4080 | UChar rB_addr = ifieldRegB(theInstr); |
| 4081 | UInt opc2 = ifieldOPClo10(theInstr); |
| 4082 | UChar flag_rC = ifieldBIT0(theInstr); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4083 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4084 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 4085 | IRTemp rS = newTemp(ty); |
| 4086 | IRTemp rA = newTemp(ty); |
| 4087 | IRTemp rB = newTemp(ty); |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4088 | IRExpr* irx; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4089 | Bool do_rc = False; |
| 4090 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4091 | assign( rS, getIReg(rS_addr) ); |
| 4092 | assign( rB, getIReg(rB_addr) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4093 | |
| 4094 | switch (opc1) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4095 | case 0x1C: // andi. (AND Immediate, PPC32 p358) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4096 | DIP("andi. r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4097 | assign( rA, binop( mkSzOp(ty, Iop_And8), mkexpr(rS), |
| 4098 | mkSzImm(ty, uimm16)) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 4099 | do_rc = True; // Always record to CR |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4100 | flag_rC = 1; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4101 | break; |
| 4102 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4103 | case 0x1D: // andis. (AND Immediate Shifted, PPC32 p359) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4104 | DIP("andis r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4105 | assign( rA, binop( mkSzOp(ty, Iop_And8), mkexpr(rS), |
| 4106 | mkSzImm(ty, uimm16 << 16)) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 4107 | do_rc = True; // Always record to CR |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4108 | flag_rC = 1; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4109 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4110 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4111 | case 0x18: // ori (OR Immediate, PPC32 p497) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4112 | DIP("ori r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4113 | assign( rA, binop( mkSzOp(ty, Iop_Or8), mkexpr(rS), |
| 4114 | mkSzImm(ty, uimm16)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4115 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4116 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4117 | case 0x19: // oris (OR Immediate Shifted, PPC32 p498) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4118 | DIP("oris r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4119 | assign( rA, binop( mkSzOp(ty, Iop_Or8), mkexpr(rS), |
| 4120 | mkSzImm(ty, uimm16 << 16)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4121 | break; |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 4122 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4123 | case 0x1A: // xori (XOR Immediate, PPC32 p550) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4124 | DIP("xori r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4125 | assign( rA, binop( mkSzOp(ty, Iop_Xor8), mkexpr(rS), |
| 4126 | mkSzImm(ty, uimm16)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4127 | break; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 4128 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4129 | case 0x1B: // xoris (XOR Immediate Shifted, PPC32 p551) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4130 | DIP("xoris r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4131 | assign( rA, binop( mkSzOp(ty, Iop_Xor8), mkexpr(rS), |
| 4132 | mkSzImm(ty, uimm16 << 16)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4133 | break; |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 4134 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4135 | /* X Form */ |
| 4136 | case 0x1F: |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4137 | do_rc = True; // All below record to CR, except for where we return at case end. |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 4138 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4139 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4140 | case 0x01C: // and (AND, PPC32 p356) |
| 4141 | DIP("and%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4142 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4143 | assign(rA, binop( mkSzOp(ty, Iop_And8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4144 | mkexpr(rS), mkexpr(rB))); |
| 4145 | break; |
| 4146 | |
| 4147 | case 0x03C: // andc (AND with Complement, PPC32 p357) |
| 4148 | DIP("andc%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4149 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4150 | assign(rA, binop( mkSzOp(ty, Iop_And8), mkexpr(rS), |
| 4151 | unop( mkSzOp(ty, Iop_Not8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4152 | mkexpr(rB)))); |
| 4153 | break; |
| 4154 | |
| 4155 | case 0x01A: { // cntlzw (Count Leading Zeros Word, PPC32 p371) |
| 4156 | IRExpr* lo32; |
| 4157 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4158 | vex_printf("dis_int_logic(ppc)(cntlzw,rB_addr)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4159 | return False; |
| 4160 | } |
| 4161 | DIP("cntlzw%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4162 | flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4163 | |
| 4164 | // mode64: count in low word only |
| 4165 | lo32 = mode64 ? unop(Iop_64to32, mkexpr(rS)) : mkexpr(rS); |
| 4166 | |
| 4167 | // Iop_Clz32 undefined for arg==0, so deal with that case: |
| 4168 | irx = binop(Iop_CmpNE32, lo32, mkU32(0)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4169 | assign(rA, mkWidenFrom32(ty, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4170 | IRExpr_ITE( irx, |
| 4171 | unop(Iop_Clz32, lo32), |
| 4172 | mkU32(32)), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4173 | False)); |
| 4174 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4175 | // TODO: alternatively: assign(rA, verbose_Clz32(rS)); |
| 4176 | break; |
| 4177 | } |
| 4178 | |
| 4179 | case 0x11C: // eqv (Equivalent, PPC32 p396) |
| 4180 | DIP("eqv%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4181 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4182 | assign( rA, unop( mkSzOp(ty, Iop_Not8), |
| 4183 | binop( mkSzOp(ty, Iop_Xor8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4184 | mkexpr(rS), mkexpr(rB))) ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 4185 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4186 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4187 | case 0x3BA: // extsb (Extend Sign Byte, PPC32 p397 |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4188 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4189 | vex_printf("dis_int_logic(ppc)(extsb,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4190 | return False; |
| 4191 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4192 | DIP("extsb%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4193 | flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4194 | if (mode64) |
| 4195 | assign( rA, unop(Iop_8Sto64, unop(Iop_64to8, mkexpr(rS))) ); |
| 4196 | else |
| 4197 | assign( rA, unop(Iop_8Sto32, unop(Iop_32to8, mkexpr(rS))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4198 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4199 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4200 | case 0x39A: // extsh (Extend Sign Half Word, PPC32 p398) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4201 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4202 | vex_printf("dis_int_logic(ppc)(extsh,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4203 | return False; |
| 4204 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4205 | DIP("extsh%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4206 | flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4207 | if (mode64) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4208 | assign( rA, unop(Iop_16Sto64, |
| 4209 | unop(Iop_64to16, mkexpr(rS))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4210 | else |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4211 | assign( rA, unop(Iop_16Sto32, |
| 4212 | unop(Iop_32to16, mkexpr(rS))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4213 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4214 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4215 | case 0x1DC: // nand (NAND, PPC32 p492) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4216 | DIP("nand%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4217 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4218 | assign( rA, unop( mkSzOp(ty, Iop_Not8), |
| 4219 | binop( mkSzOp(ty, Iop_And8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4220 | mkexpr(rS), mkexpr(rB))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4221 | break; |
| 4222 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4223 | case 0x07C: // nor (NOR, PPC32 p494) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4224 | DIP("nor%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4225 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4226 | assign( rA, unop( mkSzOp(ty, Iop_Not8), |
| 4227 | binop( mkSzOp(ty, Iop_Or8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4228 | mkexpr(rS), mkexpr(rB))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4229 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4230 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4231 | case 0x1BC: // or (OR, PPC32 p495) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4232 | if ((!flag_rC) && rS_addr == rB_addr) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4233 | DIP("mr r%u,r%u\n", rA_addr, rS_addr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4234 | assign( rA, mkexpr(rS) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4235 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4236 | DIP("or%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4237 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4238 | assign( rA, binop( mkSzOp(ty, Iop_Or8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4239 | mkexpr(rS), mkexpr(rB)) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4240 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4241 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4242 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4243 | case 0x19C: // orc (OR with Complement, PPC32 p496) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4244 | DIP("orc%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4245 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4246 | assign( rA, binop( mkSzOp(ty, Iop_Or8), mkexpr(rS), |
| 4247 | unop(mkSzOp(ty, Iop_Not8), mkexpr(rB)))); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4248 | break; |
| 4249 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4250 | case 0x13C: // xor (XOR, PPC32 p549) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4251 | DIP("xor%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4252 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4253 | assign( rA, binop( mkSzOp(ty, Iop_Xor8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4254 | mkexpr(rS), mkexpr(rB)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4255 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 4256 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4257 | |
| 4258 | /* 64bit Integer Logical Instructions */ |
| 4259 | case 0x3DA: // extsw (Extend Sign Word, PPC64 p430) |
| 4260 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4261 | vex_printf("dis_int_logic(ppc)(extsw,rB_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4262 | return False; |
| 4263 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4264 | DIP("extsw%s r%u,r%u\n", flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4265 | assign(rA, unop(Iop_32Sto64, unop(Iop_64to32, mkexpr(rS)))); |
| 4266 | break; |
| 4267 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4268 | case 0x03A: // cntlzd (Count Leading Zeros DWord, PPC64 p401) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4269 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4270 | vex_printf("dis_int_logic(ppc)(cntlzd,rB_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4271 | return False; |
| 4272 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4273 | DIP("cntlzd%s r%u,r%u\n", |
| 4274 | flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4275 | // Iop_Clz64 undefined for arg==0, so deal with that case: |
| 4276 | irx = binop(Iop_CmpNE64, mkexpr(rS), mkU64(0)); |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4277 | assign(rA, IRExpr_ITE( irx, |
| 4278 | unop(Iop_Clz64, mkexpr(rS)), |
| 4279 | mkU64(64) )); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4280 | // TODO: alternatively: assign(rA, verbose_Clz64(rS)); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4281 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4282 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 4283 | case 0x1FC: // cmpb (Power6: compare bytes) |
| 4284 | DIP("cmpb r%u,r%u,r%u\n", rA_addr, rS_addr, rB_addr); |
| 4285 | |
| 4286 | if (mode64) |
| 4287 | assign( rA, unop( Iop_V128to64, |
| 4288 | binop( Iop_CmpEQ8x16, |
| 4289 | binop( Iop_64HLtoV128, mkU64(0), mkexpr(rS) ), |
| 4290 | binop( Iop_64HLtoV128, mkU64(0), mkexpr(rB) ) |
| 4291 | )) ); |
| 4292 | else |
| 4293 | assign( rA, unop( Iop_V128to32, |
| 4294 | binop( Iop_CmpEQ8x16, |
| 4295 | unop( Iop_32UtoV128, mkexpr(rS) ), |
| 4296 | unop( Iop_32UtoV128, mkexpr(rB) ) |
| 4297 | )) ); |
| 4298 | break; |
| 4299 | |
| 4300 | case 0x2DF: { // mftgpr (move floating-point to general purpose register) |
| 4301 | IRTemp frB = newTemp(Ity_F64); |
| 4302 | DIP("mftgpr r%u,fr%u\n", rS_addr, rB_addr); |
| 4303 | |
| 4304 | assign( frB, getFReg(rB_addr)); // always F64 |
| 4305 | if (mode64) |
| 4306 | assign( rA, unop( Iop_ReinterpF64asI64, mkexpr(frB)) ); |
| 4307 | else |
| 4308 | assign( rA, unop( Iop_64to32, unop( Iop_ReinterpF64asI64, mkexpr(frB))) ); |
| 4309 | |
| 4310 | putIReg( rS_addr, mkexpr(rA)); |
| 4311 | return True; |
| 4312 | } |
| 4313 | |
| 4314 | case 0x25F: { // mffgpr (move floating-point from general purpose register) |
| 4315 | IRTemp frA = newTemp(Ity_F64); |
| 4316 | DIP("mffgpr fr%u,r%u\n", rS_addr, rB_addr); |
| 4317 | |
| 4318 | if (mode64) |
| 4319 | assign( frA, unop( Iop_ReinterpI64asF64, mkexpr(rB)) ); |
| 4320 | else |
| 4321 | assign( frA, unop( Iop_ReinterpI64asF64, unop( Iop_32Uto64, mkexpr(rB))) ); |
| 4322 | |
| 4323 | putFReg( rS_addr, mkexpr(frA)); |
| 4324 | return True; |
| 4325 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 4326 | case 0x1FA: // popcntd (population count doubleword |
| 4327 | { |
| 4328 | DIP("popcntd r%u,r%u\n", rA_addr, rS_addr); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 4329 | IRTemp result = gen_POPCOUNT(ty, rS, DWORD); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 4330 | putIReg( rA_addr, mkexpr(result) ); |
| 4331 | return True; |
| 4332 | } |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 4333 | case 0x17A: // popcntw (Population Count Words) |
| 4334 | { |
| 4335 | DIP("popcntw r%u,r%u\n", rA_addr, rS_addr); |
| 4336 | if (mode64) { |
| 4337 | IRTemp resultHi, resultLo; |
| 4338 | IRTemp argLo = newTemp(Ity_I32); |
| 4339 | IRTemp argHi = newTemp(Ity_I32); |
| 4340 | assign(argLo, unop(Iop_64to32, mkexpr(rS))); |
| 4341 | assign(argHi, unop(Iop_64HIto32, mkexpr(rS))); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 4342 | resultLo = gen_POPCOUNT(Ity_I32, argLo, WORD); |
| 4343 | resultHi = gen_POPCOUNT(Ity_I32, argHi, WORD); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 4344 | putIReg( rA_addr, binop(Iop_32HLto64, mkexpr(resultHi), mkexpr(resultLo))); |
| 4345 | } else { |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 4346 | IRTemp result = gen_POPCOUNT(ty, rS, WORD); |
philippe | 738d9dd | 2012-07-06 21:56:53 +0000 | [diff] [blame] | 4347 | putIReg( rA_addr, mkexpr(result) ); |
| 4348 | } |
| 4349 | return True; |
| 4350 | } |
| 4351 | case 0x7A: // popcntb (Population Count Byte) |
| 4352 | { |
| 4353 | DIP("popcntb r%u,r%u\n", rA_addr, rS_addr); |
| 4354 | |
| 4355 | if (mode64) { |
| 4356 | IRTemp resultHi, resultLo; |
| 4357 | IRTemp argLo = newTemp(Ity_I32); |
| 4358 | IRTemp argHi = newTemp(Ity_I32); |
| 4359 | assign(argLo, unop(Iop_64to32, mkexpr(rS))); |
| 4360 | assign(argHi, unop(Iop_64HIto32, mkexpr(rS))); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 4361 | resultLo = gen_POPCOUNT(Ity_I32, argLo, BYTE); |
| 4362 | resultHi = gen_POPCOUNT(Ity_I32, argHi, BYTE); |
philippe | 738d9dd | 2012-07-06 21:56:53 +0000 | [diff] [blame] | 4363 | putIReg( rA_addr, binop(Iop_32HLto64, mkexpr(resultHi), |
| 4364 | mkexpr(resultLo))); |
| 4365 | } else { |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 4366 | IRTemp result = gen_POPCOUNT(ty, rS, BYTE); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 4367 | putIReg( rA_addr, mkexpr(result) ); |
| 4368 | } |
| 4369 | return True; |
| 4370 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 4371 | case 0x0FC: // bpermd (Bit Permute Doubleword) |
| 4372 | { |
| 4373 | /* This is a lot of rigmarole to emulate bpermd like this, as it |
| 4374 | * could be done much faster by implementing a call to the native |
| 4375 | * instruction. However, where possible I want to avoid using new |
| 4376 | * native instructions so that we can use valgrind to emulate those |
| 4377 | * instructions on older PPC64 hardware. |
| 4378 | */ |
| 4379 | #define BPERMD_IDX_MASK 0x00000000000000FFULL |
| 4380 | #define BPERMD_BIT_MASK 0x8000000000000000ULL |
| 4381 | int i; |
| 4382 | IRExpr * rS_expr = mkexpr(rS); |
| 4383 | IRExpr * res = binop(Iop_And64, mkU64(0), mkU64(0)); |
| 4384 | DIP("bpermd r%u,r%u,r%u\n", rA_addr, rS_addr, rB_addr); |
| 4385 | for (i = 0; i < 8; i++) { |
| 4386 | IRTemp idx_tmp = newTemp( Ity_I64 ); |
| 4387 | IRTemp perm_bit = newTemp( Ity_I64 ); |
| 4388 | IRTemp idx = newTemp( Ity_I8 ); |
| 4389 | IRTemp idx_LT64 = newTemp( Ity_I1 ); |
| 4390 | IRTemp idx_LT64_ity64 = newTemp( Ity_I64 ); |
| 4391 | |
| 4392 | assign( idx_tmp, |
| 4393 | binop( Iop_And64, mkU64( BPERMD_IDX_MASK ), rS_expr ) ); |
| 4394 | assign( idx_LT64, |
| 4395 | binop( Iop_CmpLT64U, mkexpr( idx_tmp ), mkU64( 64 ) ) ); |
| 4396 | assign( idx, |
| 4397 | binop( Iop_And8, |
| 4398 | unop( Iop_1Sto8, |
| 4399 | mkexpr(idx_LT64) ), |
| 4400 | unop( Iop_64to8, mkexpr( idx_tmp ) ) ) ); |
| 4401 | /* If idx_LT64 == 0, we must force the perm bit to '0'. Below, we se idx |
| 4402 | * to determine which bit of rB to use for the perm bit, and then we shift |
| 4403 | * that bit to the MSB position. We AND that with a 64-bit-ized idx_LT64 |
| 4404 | * to set the final perm bit. |
| 4405 | */ |
| 4406 | assign( idx_LT64_ity64, |
| 4407 | unop( Iop_32Uto64, unop( Iop_1Uto32, mkexpr(idx_LT64 ) ) ) ); |
| 4408 | assign( perm_bit, |
| 4409 | binop( Iop_And64, |
| 4410 | mkexpr( idx_LT64_ity64 ), |
| 4411 | binop( Iop_Shr64, |
| 4412 | binop( Iop_And64, |
| 4413 | mkU64( BPERMD_BIT_MASK ), |
| 4414 | binop( Iop_Shl64, |
| 4415 | mkexpr( rB ), |
| 4416 | mkexpr( idx ) ) ), |
| 4417 | mkU8( 63 ) ) ) ); |
| 4418 | res = binop( Iop_Or64, |
| 4419 | res, |
| 4420 | binop( Iop_Shl64, |
| 4421 | mkexpr( perm_bit ), |
| 4422 | mkU8( i ) ) ); |
| 4423 | rS_expr = binop( Iop_Shr64, rS_expr, mkU8( 8 ) ); |
| 4424 | } |
| 4425 | putIReg(rA_addr, res); |
| 4426 | return True; |
| 4427 | } |
| 4428 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4429 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4430 | vex_printf("dis_int_logic(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4431 | return False; |
| 4432 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4433 | break; |
| 4434 | |
| 4435 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4436 | vex_printf("dis_int_logic(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4437 | return False; |
| 4438 | } |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 4439 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4440 | putIReg( rA_addr, mkexpr(rA) ); |
| 4441 | |
| 4442 | if (do_rc && flag_rC) { |
| 4443 | set_CR0( mkexpr(rA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4444 | } |
| 4445 | return True; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4446 | } |
| 4447 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 4448 | /* |
| 4449 | Integer Parity Instructions |
| 4450 | */ |
| 4451 | static Bool dis_int_parity ( UInt theInstr ) |
| 4452 | { |
| 4453 | /* X-Form */ |
| 4454 | UChar opc1 = ifieldOPC(theInstr); |
| 4455 | UChar rS_addr = ifieldRegDS(theInstr); |
| 4456 | UChar rA_addr = ifieldRegA(theInstr); |
| 4457 | UChar rB_addr = ifieldRegB(theInstr); |
| 4458 | UInt opc2 = ifieldOPClo10(theInstr); |
| 4459 | UChar b0 = ifieldBIT0(theInstr); |
| 4460 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 4461 | |
| 4462 | IRTemp rS = newTemp(ty); |
| 4463 | IRTemp rA = newTemp(ty); |
| 4464 | IRTemp iTot1 = newTemp(Ity_I32); |
| 4465 | IRTemp iTot2 = newTemp(Ity_I32); |
| 4466 | IRTemp iTot3 = newTemp(Ity_I32); |
| 4467 | IRTemp iTot4 = newTemp(Ity_I32); |
| 4468 | IRTemp iTot5 = newTemp(Ity_I32); |
| 4469 | IRTemp iTot6 = newTemp(Ity_I32); |
| 4470 | IRTemp iTot7 = newTemp(Ity_I32); |
| 4471 | IRTemp iTot8 = newTemp(Ity_I32); |
| 4472 | IRTemp rS1 = newTemp(ty); |
| 4473 | IRTemp rS2 = newTemp(ty); |
| 4474 | IRTemp rS3 = newTemp(ty); |
| 4475 | IRTemp rS4 = newTemp(ty); |
| 4476 | IRTemp rS5 = newTemp(ty); |
| 4477 | IRTemp rS6 = newTemp(ty); |
| 4478 | IRTemp rS7 = newTemp(ty); |
| 4479 | IRTemp iHi = newTemp(Ity_I32); |
| 4480 | IRTemp iLo = newTemp(Ity_I32); |
| 4481 | IROp to_bit = (mode64 ? Iop_64to1 : Iop_32to1); |
| 4482 | IROp shr_op = (mode64 ? Iop_Shr64 : Iop_Shr32); |
| 4483 | |
| 4484 | if (opc1 != 0x1f || rB_addr || b0) { |
| 4485 | vex_printf("dis_int_parity(ppc)(0x1F,opc1:rB|b0)\n"); |
| 4486 | return False; |
| 4487 | } |
| 4488 | |
| 4489 | assign( rS, getIReg(rS_addr) ); |
| 4490 | |
| 4491 | switch (opc2) { |
| 4492 | case 0xba: // prtyd (Parity Doubleword, ISA 2.05 p320) |
| 4493 | DIP("prtyd r%u,r%u\n", rA_addr, rS_addr); |
| 4494 | assign( iTot1, unop(Iop_1Uto32, unop(to_bit, mkexpr(rS))) ); |
| 4495 | assign( rS1, binop(shr_op, mkexpr(rS), mkU8(8)) ); |
| 4496 | assign( iTot2, binop(Iop_Add32, |
| 4497 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS1))), |
| 4498 | mkexpr(iTot1)) ); |
| 4499 | assign( rS2, binop(shr_op, mkexpr(rS1), mkU8(8)) ); |
| 4500 | assign( iTot3, binop(Iop_Add32, |
| 4501 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS2))), |
| 4502 | mkexpr(iTot2)) ); |
| 4503 | assign( rS3, binop(shr_op, mkexpr(rS2), mkU8(8)) ); |
| 4504 | assign( iTot4, binop(Iop_Add32, |
| 4505 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS3))), |
| 4506 | mkexpr(iTot3)) ); |
| 4507 | if (mode64) { |
| 4508 | assign( rS4, binop(shr_op, mkexpr(rS3), mkU8(8)) ); |
| 4509 | assign( iTot5, binop(Iop_Add32, |
| 4510 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS4))), |
| 4511 | mkexpr(iTot4)) ); |
| 4512 | assign( rS5, binop(shr_op, mkexpr(rS4), mkU8(8)) ); |
| 4513 | assign( iTot6, binop(Iop_Add32, |
| 4514 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS5))), |
| 4515 | mkexpr(iTot5)) ); |
| 4516 | assign( rS6, binop(shr_op, mkexpr(rS5), mkU8(8)) ); |
| 4517 | assign( iTot7, binop(Iop_Add32, |
| 4518 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS6))), |
| 4519 | mkexpr(iTot6)) ); |
| 4520 | assign( rS7, binop(shr_op, mkexpr(rS6), mkU8(8)) ); |
| 4521 | assign( iTot8, binop(Iop_Add32, |
| 4522 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS7))), |
| 4523 | mkexpr(iTot7)) ); |
| 4524 | assign( rA, unop(Iop_32Uto64, |
| 4525 | binop(Iop_And32, mkexpr(iTot8), mkU32(1))) ); |
| 4526 | } else |
| 4527 | assign( rA, mkexpr(iTot4) ); |
| 4528 | |
| 4529 | break; |
| 4530 | case 0x9a: // prtyw (Parity Word, ISA 2.05 p320) |
| 4531 | assign( iTot1, unop(Iop_1Uto32, unop(to_bit, mkexpr(rS))) ); |
| 4532 | assign( rS1, binop(shr_op, mkexpr(rS), mkU8(8)) ); |
| 4533 | assign( iTot2, binop(Iop_Add32, |
| 4534 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS1))), |
| 4535 | mkexpr(iTot1)) ); |
| 4536 | assign( rS2, binop(shr_op, mkexpr(rS1), mkU8(8)) ); |
| 4537 | assign( iTot3, binop(Iop_Add32, |
| 4538 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS2))), |
| 4539 | mkexpr(iTot2)) ); |
| 4540 | assign( rS3, binop(shr_op, mkexpr(rS2), mkU8(8)) ); |
| 4541 | assign( iTot4, binop(Iop_Add32, |
| 4542 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS3))), |
| 4543 | mkexpr(iTot3)) ); |
| 4544 | assign( iLo, unop(Iop_1Uto32, unop(Iop_32to1, mkexpr(iTot4) )) ); |
| 4545 | |
| 4546 | if (mode64) { |
| 4547 | assign( rS4, binop(shr_op, mkexpr(rS3), mkU8(8)) ); |
| 4548 | assign( iTot5, unop(Iop_1Uto32, unop(to_bit, mkexpr(rS4))) ); |
| 4549 | assign( rS5, binop(shr_op, mkexpr(rS4), mkU8(8)) ); |
| 4550 | assign( iTot6, binop(Iop_Add32, |
| 4551 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS5))), |
| 4552 | mkexpr(iTot5)) ); |
| 4553 | assign( rS6, binop(shr_op, mkexpr(rS5), mkU8(8)) ); |
| 4554 | assign( iTot7, binop(Iop_Add32, |
| 4555 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS6))), |
| 4556 | mkexpr(iTot6)) ); |
| 4557 | assign( rS7, binop(shr_op, mkexpr(rS6), mkU8(8))); |
| 4558 | assign( iTot8, binop(Iop_Add32, |
| 4559 | unop(Iop_1Uto32, unop(to_bit, mkexpr(rS7))), |
| 4560 | mkexpr(iTot7)) ); |
| 4561 | assign( iHi, binop(Iop_And32, mkU32(1), mkexpr(iTot8)) ), |
| 4562 | assign( rA, binop(Iop_32HLto64, mkexpr(iHi), mkexpr(iLo)) ); |
| 4563 | } else |
| 4564 | assign( rA, binop(Iop_Or32, mkU32(0), mkexpr(iLo)) ); |
| 4565 | break; |
| 4566 | default: |
| 4567 | vex_printf("dis_int_parity(ppc)(opc2)\n"); |
| 4568 | return False; |
| 4569 | } |
| 4570 | |
| 4571 | putIReg( rA_addr, mkexpr(rA) ); |
| 4572 | |
| 4573 | return True; |
| 4574 | } |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4575 | |
| 4576 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 4577 | /* |
| 4578 | Integer Rotate Instructions |
| 4579 | */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4580 | static Bool dis_int_rot ( UInt theInstr ) |
| 4581 | { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4582 | /* M-Form, MDS-Form */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4583 | UChar opc1 = ifieldOPC(theInstr); |
| 4584 | UChar rS_addr = ifieldRegDS(theInstr); |
| 4585 | UChar rA_addr = ifieldRegA(theInstr); |
| 4586 | UChar rB_addr = ifieldRegB(theInstr); |
| 4587 | UChar sh_imm = rB_addr; |
| 4588 | UChar MaskBeg = toUChar( IFIELD( theInstr, 6, 5 ) ); |
| 4589 | UChar MaskEnd = toUChar( IFIELD( theInstr, 1, 5 ) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4590 | UChar msk_imm = toUChar( IFIELD( theInstr, 5, 6 ) ); |
| 4591 | UChar opc2 = toUChar( IFIELD( theInstr, 2, 3 ) ); |
| 4592 | UChar b1 = ifieldBIT1(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4593 | UChar flag_rC = ifieldBIT0(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4594 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4595 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 4596 | IRTemp rS = newTemp(ty); |
| 4597 | IRTemp rA = newTemp(ty); |
| 4598 | IRTemp rB = newTemp(ty); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4599 | IRTemp rot = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4600 | IRExpr *r; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4601 | UInt mask32; |
| 4602 | ULong mask64; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4603 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4604 | assign( rS, getIReg(rS_addr) ); |
| 4605 | assign( rB, getIReg(rB_addr) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4606 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4607 | switch (opc1) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4608 | case 0x14: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4609 | // rlwimi (Rotate Left Word Imm then Mask Insert, PPC32 p500) |
| 4610 | DIP("rlwimi%s r%u,r%u,%d,%d,%d\n", flag_rC ? ".":"", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4611 | rA_addr, rS_addr, sh_imm, MaskBeg, MaskEnd); |
| 4612 | if (mode64) { |
| 4613 | // tmp32 = (ROTL(rS_Lo32, Imm) |
| 4614 | // rA = ((tmp32 || tmp32) & mask64) | (rA & ~mask64) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4615 | mask64 = MASK64(31-MaskEnd, 31-MaskBeg); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4616 | r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) ); |
| 4617 | r = unop(Iop_32Uto64, r); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4618 | assign( rot, binop(Iop_Or64, r, |
| 4619 | binop(Iop_Shl64, r, mkU8(32))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4620 | assign( rA, |
| 4621 | binop(Iop_Or64, |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4622 | binop(Iop_And64, mkexpr(rot), mkU64(mask64)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4623 | binop(Iop_And64, getIReg(rA_addr), mkU64(~mask64))) ); |
sewardj | 26b3320 | 2005-10-07 09:45:16 +0000 | [diff] [blame] | 4624 | } |
| 4625 | else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4626 | // rA = (ROTL(rS, Imm) & mask) | (rA & ~mask); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4627 | mask32 = MASK32(31-MaskEnd, 31-MaskBeg); |
| 4628 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4629 | assign( rA, |
| 4630 | binop(Iop_Or32, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4631 | binop(Iop_And32, mkU32(mask32), r), |
| 4632 | binop(Iop_And32, getIReg(rA_addr), mkU32(~mask32))) ); |
sewardj | 26b3320 | 2005-10-07 09:45:16 +0000 | [diff] [blame] | 4633 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4634 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4635 | } |
cerion | 45b70ff | 2005-01-31 17:03:25 +0000 | [diff] [blame] | 4636 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4637 | case 0x15: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4638 | // rlwinm (Rotate Left Word Imm then AND with Mask, PPC32 p501) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4639 | vassert(MaskBeg < 32); |
| 4640 | vassert(MaskEnd < 32); |
| 4641 | vassert(sh_imm < 32); |
| 4642 | |
| 4643 | if (mode64) { |
sewardj | ef4433b | 2006-10-19 03:01:09 +0000 | [diff] [blame] | 4644 | IRTemp rTmp = newTemp(Ity_I64); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4645 | mask64 = MASK64(31-MaskEnd, 31-MaskBeg); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4646 | DIP("rlwinm%s r%u,r%u,%d,%d,%d\n", flag_rC ? ".":"", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4647 | rA_addr, rS_addr, sh_imm, MaskBeg, MaskEnd); |
| 4648 | // tmp32 = (ROTL(rS_Lo32, Imm) |
| 4649 | // rA = ((tmp32 || tmp32) & mask64) |
| 4650 | r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) ); |
| 4651 | r = unop(Iop_32Uto64, r); |
sewardj | ef4433b | 2006-10-19 03:01:09 +0000 | [diff] [blame] | 4652 | assign( rTmp, r ); |
| 4653 | r = NULL; |
| 4654 | assign( rot, binop(Iop_Or64, mkexpr(rTmp), |
| 4655 | binop(Iop_Shl64, mkexpr(rTmp), mkU8(32))) ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4656 | assign( rA, binop(Iop_And64, mkexpr(rot), mkU64(mask64)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4657 | } |
| 4658 | else { |
| 4659 | if (MaskBeg == 0 && sh_imm+MaskEnd == 31) { |
| 4660 | /* Special-case the ,n,0,31-n form as that is just n-bit |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4661 | shift left, PPC32 p501 */ |
| 4662 | DIP("slwi%s r%u,r%u,%d\n", flag_rC ? ".":"", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4663 | rA_addr, rS_addr, sh_imm); |
| 4664 | assign( rA, binop(Iop_Shl32, mkexpr(rS), mkU8(sh_imm)) ); |
| 4665 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4666 | else if (MaskEnd == 31 && sh_imm+MaskBeg == 32) { |
| 4667 | /* Special-case the ,32-n,n,31 form as that is just n-bit |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4668 | unsigned shift right, PPC32 p501 */ |
| 4669 | DIP("srwi%s r%u,r%u,%d\n", flag_rC ? ".":"", |
sewardj | ee4a859 | 2006-10-19 00:15:25 +0000 | [diff] [blame] | 4670 | rA_addr, rS_addr, MaskBeg); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4671 | assign( rA, binop(Iop_Shr32, mkexpr(rS), mkU8(MaskBeg)) ); |
| 4672 | } |
| 4673 | else { |
| 4674 | /* General case. */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4675 | mask32 = MASK32(31-MaskEnd, 31-MaskBeg); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4676 | DIP("rlwinm%s r%u,r%u,%d,%d,%d\n", flag_rC ? ".":"", |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4677 | rA_addr, rS_addr, sh_imm, MaskBeg, MaskEnd); |
| 4678 | // rA = ROTL(rS, Imm) & mask |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4679 | assign( rA, binop(Iop_And32, |
| 4680 | ROTL(mkexpr(rS), mkU8(sh_imm)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4681 | mkU32(mask32)) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4682 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4683 | } |
sewardj | c965953 | 2005-07-21 21:33:57 +0000 | [diff] [blame] | 4684 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4685 | } |
| 4686 | |
| 4687 | case 0x17: { |
| 4688 | // rlwnm (Rotate Left Word then AND with Mask, PPC32 p503 |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4689 | DIP("rlwnm%s r%u,r%u,r%u,%d,%d\n", flag_rC ? ".":"", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4690 | rA_addr, rS_addr, rB_addr, MaskBeg, MaskEnd); |
| 4691 | if (mode64) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4692 | mask64 = MASK64(31-MaskEnd, 31-MaskBeg); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4693 | /* weird insn alert! |
| 4694 | tmp32 = (ROTL(rS_Lo32, rB[0-4]) |
| 4695 | rA = ((tmp32 || tmp32) & mask64) |
| 4696 | */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4697 | // note, ROTL does the masking, so we don't do it here |
| 4698 | r = ROTL( unop(Iop_64to32, mkexpr(rS)), |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4699 | unop(Iop_64to8, mkexpr(rB)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4700 | r = unop(Iop_32Uto64, r); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 4701 | assign(rot, binop(Iop_Or64, r, binop(Iop_Shl64, r, mkU8(32)))); |
| 4702 | assign( rA, binop(Iop_And64, mkexpr(rot), mkU64(mask64)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4703 | } else { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4704 | mask32 = MASK32(31-MaskEnd, 31-MaskBeg); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4705 | // rA = ROTL(rS, rB[0-4]) & mask |
| 4706 | // note, ROTL does the masking, so we don't do it here |
| 4707 | assign( rA, binop(Iop_And32, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4708 | ROTL(mkexpr(rS), |
| 4709 | unop(Iop_32to8, mkexpr(rB))), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4710 | mkU32(mask32)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4711 | } |
| 4712 | break; |
| 4713 | } |
cerion | 45b70ff | 2005-01-31 17:03:25 +0000 | [diff] [blame] | 4714 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4715 | /* 64bit Integer Rotates */ |
| 4716 | case 0x1E: { |
| 4717 | msk_imm = ((msk_imm & 1) << 5) | (msk_imm >> 1); |
| 4718 | sh_imm |= b1 << 5; |
| 4719 | |
| 4720 | vassert( msk_imm < 64 ); |
| 4721 | vassert( sh_imm < 64 ); |
| 4722 | |
| 4723 | switch (opc2) { |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4724 | case 0x4: { |
| 4725 | /* r = ROTL64( rS, rB_lo6) */ |
| 4726 | r = ROTL( mkexpr(rS), unop(Iop_64to8, mkexpr(rB)) ); |
| 4727 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4728 | if (b1 == 0) { // rldcl (Rotl DWord, Clear Left, PPC64 p555) |
| 4729 | DIP("rldcl%s r%u,r%u,r%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4730 | rA_addr, rS_addr, rB_addr, msk_imm); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4731 | // note, ROTL does the masking, so we don't do it here |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4732 | mask64 = MASK64(0, 63-msk_imm); |
| 4733 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 4734 | break; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4735 | } else { // rldcr (Rotl DWord, Clear Right, PPC64 p556) |
| 4736 | DIP("rldcr%s r%u,r%u,r%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4737 | rA_addr, rS_addr, rB_addr, msk_imm); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4738 | mask64 = MASK64(63-msk_imm, 63); |
| 4739 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 4740 | break; |
| 4741 | } |
| 4742 | break; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4743 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4744 | case 0x2: // rldic (Rotl DWord Imm, Clear, PPC64 p557) |
| 4745 | DIP("rldic%s r%u,r%u,%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4746 | rA_addr, rS_addr, sh_imm, msk_imm); |
| 4747 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
| 4748 | mask64 = MASK64(sh_imm, 63-msk_imm); |
| 4749 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 4750 | break; |
| 4751 | // later: deal with special case: (msk_imm==0) => SHL(sh_imm) |
| 4752 | /* |
| 4753 | Hmm... looks like this'll do the job more simply: |
| 4754 | r = SHL(rS, sh_imm) |
| 4755 | m = ~(1 << (63-msk_imm)) |
| 4756 | assign(rA, r & m); |
| 4757 | */ |
| 4758 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4759 | case 0x0: // rldicl (Rotl DWord Imm, Clear Left, PPC64 p558) |
sewardj | ee4a859 | 2006-10-19 00:15:25 +0000 | [diff] [blame] | 4760 | if (mode64 |
| 4761 | && sh_imm + msk_imm == 64 && msk_imm >= 1 && msk_imm <= 63) { |
| 4762 | /* special-case the ,64-n,n form as that is just |
| 4763 | unsigned shift-right by n */ |
| 4764 | DIP("srdi%s r%u,r%u,%u\n", |
| 4765 | flag_rC ? ".":"", rA_addr, rS_addr, msk_imm); |
| 4766 | assign( rA, binop(Iop_Shr64, mkexpr(rS), mkU8(msk_imm)) ); |
| 4767 | } else { |
| 4768 | DIP("rldicl%s r%u,r%u,%u,%u\n", flag_rC ? ".":"", |
| 4769 | rA_addr, rS_addr, sh_imm, msk_imm); |
| 4770 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
| 4771 | mask64 = MASK64(0, 63-msk_imm); |
| 4772 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 4773 | } |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4774 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4775 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4776 | case 0x1: // rldicr (Rotl DWord Imm, Clear Right, PPC64 p559) |
sewardj | ee4a859 | 2006-10-19 00:15:25 +0000 | [diff] [blame] | 4777 | if (mode64 |
| 4778 | && sh_imm + msk_imm == 63 && sh_imm >= 1 && sh_imm <= 63) { |
| 4779 | /* special-case the ,n,63-n form as that is just |
| 4780 | shift-left by n */ |
| 4781 | DIP("sldi%s r%u,r%u,%u\n", |
| 4782 | flag_rC ? ".":"", rA_addr, rS_addr, sh_imm); |
| 4783 | assign( rA, binop(Iop_Shl64, mkexpr(rS), mkU8(sh_imm)) ); |
| 4784 | } else { |
| 4785 | DIP("rldicr%s r%u,r%u,%u,%u\n", flag_rC ? ".":"", |
| 4786 | rA_addr, rS_addr, sh_imm, msk_imm); |
| 4787 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
| 4788 | mask64 = MASK64(63-msk_imm, 63); |
| 4789 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 4790 | } |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4791 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4792 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4793 | case 0x3: { // rldimi (Rotl DWord Imm, Mask Insert, PPC64 p560) |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4794 | IRTemp rA_orig = newTemp(ty); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4795 | DIP("rldimi%s r%u,r%u,%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4796 | rA_addr, rS_addr, sh_imm, msk_imm); |
| 4797 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
| 4798 | mask64 = MASK64(sh_imm, 63-msk_imm); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4799 | assign( rA_orig, getIReg(rA_addr) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4800 | assign( rA, binop(Iop_Or64, |
| 4801 | binop(Iop_And64, mkU64(mask64), r), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4802 | binop(Iop_And64, mkU64(~mask64), |
| 4803 | mkexpr(rA_orig))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4804 | break; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4805 | } |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4806 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4807 | vex_printf("dis_int_rot(ppc)(opc2)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4808 | return False; |
| 4809 | } |
| 4810 | break; |
| 4811 | } |
| 4812 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4813 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4814 | vex_printf("dis_int_rot(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4815 | return False; |
| 4816 | } |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4817 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4818 | putIReg( rA_addr, mkexpr(rA) ); |
| 4819 | |
| 4820 | if (flag_rC) { |
| 4821 | set_CR0( mkexpr(rA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4822 | } |
| 4823 | return True; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4824 | } |
| 4825 | |
| 4826 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 4827 | /* |
| 4828 | Integer Load Instructions |
| 4829 | */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4830 | static Bool dis_int_load ( UInt theInstr ) |
| 4831 | { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4832 | /* D-Form, X-Form, DS-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4833 | UChar opc1 = ifieldOPC(theInstr); |
| 4834 | UChar rD_addr = ifieldRegDS(theInstr); |
| 4835 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4836 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4837 | UChar rB_addr = ifieldRegB(theInstr); |
| 4838 | UInt opc2 = ifieldOPClo10(theInstr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4839 | UChar b1 = ifieldBIT1(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4840 | UChar b0 = ifieldBIT0(theInstr); |
| 4841 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4842 | Int simm16 = extend_s_16to32(uimm16); |
| 4843 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4844 | IRTemp EA = newTemp(ty); |
| 4845 | IRExpr* val; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 4846 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4847 | switch (opc1) { |
| 4848 | case 0x1F: // register offset |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4849 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4850 | break; |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 4851 | case 0x38: // immediate offset: 64bit: lq: maskoff |
| 4852 | // lowest 4 bits of immediate before forming EA |
| 4853 | simm16 = simm16 & 0xFFFFFFF0; |
| 4854 | assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 4855 | break; |
sewardj | 6d83422 | 2007-03-09 14:24:38 +0000 | [diff] [blame] | 4856 | case 0x3A: // immediate offset: 64bit: ld/ldu/lwa: mask off |
| 4857 | // lowest 2 bits of immediate before forming EA |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4858 | simm16 = simm16 & 0xFFFFFFFC; |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 4859 | assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 4860 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4861 | default: // immediate offset |
| 4862 | assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 4863 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4864 | } |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4865 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4866 | switch (opc1) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4867 | case 0x22: // lbz (Load B & Zero, PPC32 p433) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4868 | DIP("lbz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4869 | val = load(Ity_I8, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4870 | putIReg( rD_addr, mkWidenFrom8(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4871 | break; |
| 4872 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4873 | case 0x23: // lbzu (Load B & Zero, Update, PPC32 p434) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4874 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4875 | vex_printf("dis_int_load(ppc)(lbzu,rA_addr|rD_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4876 | return False; |
| 4877 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4878 | DIP("lbzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4879 | val = load(Ity_I8, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4880 | putIReg( rD_addr, mkWidenFrom8(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4881 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4882 | break; |
| 4883 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4884 | case 0x2A: // lha (Load HW Alg, PPC32 p445) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4885 | DIP("lha r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4886 | val = load(Ity_I16, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4887 | putIReg( rD_addr, mkWidenFrom16(ty, val, True) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4888 | break; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4889 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4890 | case 0x2B: // lhau (Load HW Alg, Update, PPC32 p446) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4891 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4892 | vex_printf("dis_int_load(ppc)(lhau,rA_addr|rD_addr)\n"); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 4893 | return False; |
| 4894 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4895 | DIP("lhau r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4896 | val = load(Ity_I16, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4897 | putIReg( rD_addr, mkWidenFrom16(ty, val, True) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4898 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 4899 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4900 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4901 | case 0x28: // lhz (Load HW & Zero, PPC32 p450) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4902 | DIP("lhz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4903 | val = load(Ity_I16, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4904 | putIReg( rD_addr, mkWidenFrom16(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4905 | break; |
| 4906 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4907 | case 0x29: // lhzu (Load HW & and Zero, Update, PPC32 p451) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4908 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4909 | vex_printf("dis_int_load(ppc)(lhzu,rA_addr|rD_addr)\n"); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 4910 | return False; |
| 4911 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4912 | DIP("lhzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4913 | val = load(Ity_I16, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4914 | putIReg( rD_addr, mkWidenFrom16(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4915 | putIReg( rA_addr, mkexpr(EA) ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 4916 | break; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4917 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4918 | case 0x20: // lwz (Load W & Zero, PPC32 p460) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4919 | DIP("lwz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4920 | val = load(Ity_I32, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4921 | putIReg( rD_addr, mkWidenFrom32(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4922 | break; |
| 4923 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4924 | case 0x21: // lwzu (Load W & Zero, Update, PPC32 p461)) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4925 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4926 | vex_printf("dis_int_load(ppc)(lwzu,rA_addr|rD_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4927 | return False; |
| 4928 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4929 | DIP("lwzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4930 | val = load(Ity_I32, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4931 | putIReg( rD_addr, mkWidenFrom32(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4932 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4933 | break; |
| 4934 | |
| 4935 | /* X Form */ |
| 4936 | case 0x1F: |
| 4937 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4938 | vex_printf("dis_int_load(ppc)(Ox1F,b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4939 | return False; |
| 4940 | } |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4941 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4942 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4943 | case 0x077: // lbzux (Load B & Zero, Update Indexed, PPC32 p435) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4944 | DIP("lbzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4945 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4946 | vex_printf("dis_int_load(ppc)(lwzux,rA_addr|rD_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4947 | return False; |
| 4948 | } |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4949 | val = load(Ity_I8, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4950 | putIReg( rD_addr, mkWidenFrom8(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4951 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4952 | break; |
| 4953 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4954 | case 0x057: // lbzx (Load B & Zero, Indexed, PPC32 p436) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4955 | DIP("lbzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4956 | val = load(Ity_I8, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4957 | putIReg( rD_addr, mkWidenFrom8(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4958 | break; |
| 4959 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4960 | case 0x177: // lhaux (Load HW Alg, Update Indexed, PPC32 p447) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4961 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4962 | vex_printf("dis_int_load(ppc)(lhaux,rA_addr|rD_addr)\n"); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 4963 | return False; |
| 4964 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4965 | DIP("lhaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4966 | val = load(Ity_I16, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4967 | putIReg( rD_addr, mkWidenFrom16(ty, val, True) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4968 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 4969 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4970 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4971 | case 0x157: // lhax (Load HW Alg, Indexed, PPC32 p448) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4972 | DIP("lhax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4973 | val = load(Ity_I16, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4974 | putIReg( rD_addr, mkWidenFrom16(ty, val, True) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4975 | break; |
| 4976 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4977 | case 0x137: // lhzux (Load HW & Zero, Update Indexed, PPC32 p452) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4978 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4979 | vex_printf("dis_int_load(ppc)(lhzux,rA_addr|rD_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4980 | return False; |
| 4981 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4982 | DIP("lhzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4983 | val = load(Ity_I16, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4984 | putIReg( rD_addr, mkWidenFrom16(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4985 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4986 | break; |
| 4987 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4988 | case 0x117: // lhzx (Load HW & Zero, Indexed, PPC32 p453) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4989 | DIP("lhzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 4990 | val = load(Ity_I16, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 4991 | putIReg( rD_addr, mkWidenFrom16(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4992 | break; |
cerion | 44997f2 | 2005-01-31 18:45:59 +0000 | [diff] [blame] | 4993 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4994 | case 0x037: // lwzux (Load W & Zero, Update Indexed, PPC32 p462) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4995 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4996 | vex_printf("dis_int_load(ppc)(lwzux,rA_addr|rD_addr)\n"); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4997 | return False; |
| 4998 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4999 | DIP("lwzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5000 | val = load(Ity_I32, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 5001 | putIReg( rD_addr, mkWidenFrom32(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5002 | putIReg( rA_addr, mkexpr(EA) ); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 5003 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5004 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5005 | case 0x017: // lwzx (Load W & Zero, Indexed, PPC32 p463) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5006 | DIP("lwzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5007 | val = load(Ity_I32, mkexpr(EA)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 5008 | putIReg( rD_addr, mkWidenFrom32(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5009 | break; |
cerion | 44997f2 | 2005-01-31 18:45:59 +0000 | [diff] [blame] | 5010 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5011 | |
| 5012 | /* 64bit Loads */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5013 | case 0x035: // ldux (Load DWord, Update Indexed, PPC64 p475) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5014 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5015 | vex_printf("dis_int_load(ppc)(ldux,rA_addr|rD_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5016 | return False; |
| 5017 | } |
| 5018 | DIP("ldux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5019 | putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5020 | putIReg( rA_addr, mkexpr(EA) ); |
| 5021 | break; |
| 5022 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5023 | case 0x015: // ldx (Load DWord, Indexed, PPC64 p476) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5024 | DIP("ldx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5025 | putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5026 | break; |
| 5027 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5028 | case 0x175: // lwaux (Load W Alg, Update Indexed, PPC64 p501) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5029 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5030 | vex_printf("dis_int_load(ppc)(lwaux,rA_addr|rD_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5031 | return False; |
| 5032 | } |
| 5033 | DIP("lwaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5034 | putIReg( rD_addr, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5035 | unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5036 | putIReg( rA_addr, mkexpr(EA) ); |
| 5037 | break; |
| 5038 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5039 | case 0x155: // lwax (Load W Alg, Indexed, PPC64 p502) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5040 | DIP("lwax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5041 | putIReg( rD_addr, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5042 | unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5043 | break; |
| 5044 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5045 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5046 | vex_printf("dis_int_load(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5047 | return False; |
| 5048 | } |
| 5049 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5050 | |
sewardj | 6d83422 | 2007-03-09 14:24:38 +0000 | [diff] [blame] | 5051 | /* DS Form - 64bit Loads. In each case EA will have been formed |
| 5052 | with the lowest 2 bits masked off the immediate offset. */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5053 | case 0x3A: |
sewardj | 6d83422 | 2007-03-09 14:24:38 +0000 | [diff] [blame] | 5054 | switch ((b1<<1) | b0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5055 | case 0x0: // ld (Load DWord, PPC64 p472) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5056 | DIP("ld r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5057 | putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5058 | break; |
| 5059 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5060 | case 0x1: // ldu (Load DWord, Update, PPC64 p474) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5061 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5062 | vex_printf("dis_int_load(ppc)(ldu,rA_addr|rD_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5063 | return False; |
| 5064 | } |
| 5065 | DIP("ldu r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5066 | putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5067 | putIReg( rA_addr, mkexpr(EA) ); |
| 5068 | break; |
| 5069 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5070 | case 0x2: // lwa (Load Word Alg, PPC64 p499) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5071 | DIP("lwa r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5072 | putIReg( rD_addr, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5073 | unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5074 | break; |
| 5075 | |
| 5076 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5077 | vex_printf("dis_int_load(ppc)(0x3A, opc2)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5078 | return False; |
| 5079 | } |
| 5080 | break; |
| 5081 | |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 5082 | case 0x38: { |
| 5083 | IRTemp high = newTemp(ty); |
| 5084 | IRTemp low = newTemp(ty); |
| 5085 | /* DQ Form - 128bit Loads. Lowest bits [1:0] are the PT field. */ |
| 5086 | DIP("lq r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); |
| 5087 | /* NOTE: there are some changes to XER[41:42] that have not been |
| 5088 | * implemented. |
| 5089 | */ |
| 5090 | // trap if EA misaligned on 16 byte address |
| 5091 | if (mode64) { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5092 | assign(high, load(ty, mkexpr( EA ) ) ); |
| 5093 | assign(low, load(ty, binop( Iop_Add64, |
| 5094 | mkexpr( EA ), |
| 5095 | mkU64( 8 ) ) ) ); |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 5096 | } else { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5097 | assign(high, load(ty, binop( Iop_Add32, |
| 5098 | mkexpr( EA ), |
| 5099 | mkU32( 4 ) ) ) ); |
| 5100 | assign(low, load(ty, binop( Iop_Add32, |
| 5101 | mkexpr( EA ), |
| 5102 | mkU32( 12 ) ) ) ); |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 5103 | } |
| 5104 | gen_SIGBUS_if_misaligned( EA, 16 ); |
| 5105 | putIReg( rD_addr, mkexpr( high) ); |
| 5106 | putIReg( rD_addr+1, mkexpr( low) ); |
| 5107 | break; |
| 5108 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5109 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5110 | vex_printf("dis_int_load(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5111 | return False; |
| 5112 | } |
| 5113 | return True; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 5114 | } |
| 5115 | |
| 5116 | |
| 5117 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5118 | /* |
| 5119 | Integer Store Instructions |
| 5120 | */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5121 | static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi ) |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 5122 | { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5123 | /* D-Form, X-Form, DS-Form */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5124 | UChar opc1 = ifieldOPC(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5125 | UInt rS_addr = ifieldRegDS(theInstr); |
| 5126 | UInt rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5127 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5128 | UInt rB_addr = ifieldRegB(theInstr); |
| 5129 | UInt opc2 = ifieldOPClo10(theInstr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5130 | UChar b1 = ifieldBIT1(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5131 | UChar b0 = ifieldBIT0(theInstr); |
| 5132 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5133 | Int simm16 = extend_s_16to32(uimm16); |
| 5134 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 5135 | IRTemp rS = newTemp(ty); |
| 5136 | IRTemp rB = newTemp(ty); |
| 5137 | IRTemp EA = newTemp(ty); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5138 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5139 | assign( rB, getIReg(rB_addr) ); |
| 5140 | assign( rS, getIReg(rS_addr) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5141 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5142 | switch (opc1) { |
| 5143 | case 0x1F: // register offset |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5144 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5145 | break; |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 5146 | case 0x3E: // immediate offset: 64bit: std/stdu/stq: mask off |
sewardj | 6d83422 | 2007-03-09 14:24:38 +0000 | [diff] [blame] | 5147 | // lowest 2 bits of immediate before forming EA |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5148 | simm16 = simm16 & 0xFFFFFFFC; |
| 5149 | default: // immediate offset |
| 5150 | assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 5151 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5152 | } |
| 5153 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5154 | switch (opc1) { |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 5155 | case 0x26: // stb (Store B, PPC32 p509) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5156 | DIP("stb r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5157 | store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 5158 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5159 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5160 | case 0x27: // stbu (Store B, Update, PPC32 p510) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5161 | if (rA_addr == 0 ) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5162 | vex_printf("dis_int_store(ppc)(stbu,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5163 | return False; |
| 5164 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5165 | DIP("stbu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5166 | putIReg( rA_addr, mkexpr(EA) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5167 | store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5168 | break; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 5169 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5170 | case 0x2C: // sth (Store HW, PPC32 p522) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5171 | DIP("sth r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5172 | store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5173 | break; |
| 5174 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5175 | case 0x2D: // sthu (Store HW, Update, PPC32 p524) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5176 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5177 | vex_printf("dis_int_store(ppc)(sthu,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5178 | return False; |
| 5179 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5180 | DIP("sthu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5181 | putIReg( rA_addr, mkexpr(EA) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5182 | store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5183 | break; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 5184 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5185 | case 0x24: // stw (Store W, PPC32 p530) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5186 | DIP("stw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5187 | store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5188 | break; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 5189 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5190 | case 0x25: // stwu (Store W, Update, PPC32 p534) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5191 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5192 | vex_printf("dis_int_store(ppc)(stwu,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5193 | return False; |
| 5194 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5195 | DIP("stwu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5196 | putIReg( rA_addr, mkexpr(EA) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5197 | store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5198 | break; |
| 5199 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5200 | /* X Form : all these use EA_indexed */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5201 | case 0x1F: |
| 5202 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5203 | vex_printf("dis_int_store(ppc)(0x1F,b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5204 | return False; |
| 5205 | } |
cerion | 44997f2 | 2005-01-31 18:45:59 +0000 | [diff] [blame] | 5206 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5207 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5208 | case 0x0F7: // stbux (Store B, Update Indexed, PPC32 p511) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5209 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5210 | vex_printf("dis_int_store(ppc)(stbux,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5211 | return False; |
| 5212 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5213 | DIP("stbux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5214 | putIReg( rA_addr, mkexpr(EA) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5215 | store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5216 | break; |
| 5217 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5218 | case 0x0D7: // stbx (Store B Indexed, PPC32 p512) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5219 | DIP("stbx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5220 | store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5221 | break; |
| 5222 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5223 | case 0x1B7: // sthux (Store HW, Update Indexed, PPC32 p525) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5224 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5225 | vex_printf("dis_int_store(ppc)(sthux,rA_addr)\n"); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 5226 | return False; |
| 5227 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5228 | DIP("sthux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5229 | putIReg( rA_addr, mkexpr(EA) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5230 | store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 5231 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5232 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5233 | case 0x197: // sthx (Store HW Indexed, PPC32 p526) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5234 | DIP("sthx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5235 | store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5236 | break; |
| 5237 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5238 | case 0x0B7: // stwux (Store W, Update Indexed, PPC32 p535) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5239 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5240 | vex_printf("dis_int_store(ppc)(stwux,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5241 | return False; |
| 5242 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5243 | DIP("stwux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5244 | putIReg( rA_addr, mkexpr(EA) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5245 | store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5246 | break; |
cerion | 44997f2 | 2005-01-31 18:45:59 +0000 | [diff] [blame] | 5247 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5248 | case 0x097: // stwx (Store W Indexed, PPC32 p536) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5249 | DIP("stwx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5250 | store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5251 | break; |
| 5252 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5253 | |
| 5254 | /* 64bit Stores */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5255 | case 0x0B5: // stdux (Store DWord, Update Indexed, PPC64 p584) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5256 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5257 | vex_printf("dis_int_store(ppc)(stdux,rA_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5258 | return False; |
| 5259 | } |
| 5260 | DIP("stdux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
| 5261 | putIReg( rA_addr, mkexpr(EA) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5262 | store( mkexpr(EA), mkexpr(rS) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5263 | break; |
| 5264 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5265 | case 0x095: // stdx (Store DWord Indexed, PPC64 p585) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5266 | DIP("stdx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5267 | store( mkexpr(EA), mkexpr(rS) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5268 | break; |
| 5269 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5270 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5271 | vex_printf("dis_int_store(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5272 | return False; |
| 5273 | } |
| 5274 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5275 | |
sewardj | 6d83422 | 2007-03-09 14:24:38 +0000 | [diff] [blame] | 5276 | /* DS Form - 64bit Stores. In each case EA will have been formed |
| 5277 | with the lowest 2 bits masked off the immediate offset. */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5278 | case 0x3E: |
sewardj | 6d83422 | 2007-03-09 14:24:38 +0000 | [diff] [blame] | 5279 | switch ((b1<<1) | b0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5280 | case 0x0: // std (Store DWord, PPC64 p580) |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 5281 | if (!mode64) |
| 5282 | return False; |
| 5283 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5284 | DIP("std r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5285 | store( mkexpr(EA), mkexpr(rS) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5286 | break; |
| 5287 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5288 | case 0x1: // stdu (Store DWord, Update, PPC64 p583) |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 5289 | if (!mode64) |
| 5290 | return False; |
| 5291 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5292 | DIP("stdu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
| 5293 | putIReg( rA_addr, mkexpr(EA) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5294 | store( mkexpr(EA), mkexpr(rS) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5295 | break; |
| 5296 | |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 5297 | case 0x2: { // stq (Store QuadWord, Update, PPC64 p583) |
| 5298 | IRTemp EA_hi = newTemp(ty); |
| 5299 | IRTemp EA_lo = newTemp(ty); |
| 5300 | DIP("stq r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
| 5301 | |
| 5302 | if (mode64) { |
| 5303 | /* upper 64-bits */ |
| 5304 | assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 5305 | |
| 5306 | /* lower 64-bits */ |
| 5307 | assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+8 ) ); |
| 5308 | } else { |
| 5309 | /* upper half of upper 64-bits */ |
| 5310 | assign( EA_hi, ea_rAor0_simm( rA_addr, simm16+4 ) ); |
| 5311 | |
| 5312 | /* lower half of upper 64-bits */ |
| 5313 | assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+12 ) ); |
| 5314 | } |
| 5315 | putIReg( rA_addr, mkexpr(EA_hi) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5316 | store( mkexpr(EA_hi), mkexpr(rS) ); |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 5317 | putIReg( rA_addr, mkexpr( EA_lo) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5318 | store( mkexpr(EA_lo), getIReg( rS_addr+1 ) ); |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 5319 | break; |
| 5320 | } |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5321 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5322 | vex_printf("dis_int_load(ppc)(0x3A, opc2)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5323 | return False; |
| 5324 | } |
| 5325 | break; |
| 5326 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5327 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5328 | vex_printf("dis_int_store(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5329 | return False; |
| 5330 | } |
| 5331 | return True; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 5332 | } |
| 5333 | |
| 5334 | |
| 5335 | |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 5336 | /* |
| 5337 | Integer Load/Store Multiple Instructions |
| 5338 | */ |
| 5339 | static Bool dis_int_ldst_mult ( UInt theInstr ) |
| 5340 | { |
| 5341 | /* D-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5342 | UChar opc1 = ifieldOPC(theInstr); |
| 5343 | UChar rD_addr = ifieldRegDS(theInstr); |
| 5344 | UChar rS_addr = rD_addr; |
| 5345 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5346 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5347 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5348 | Int simm16 = extend_s_16to32(uimm16); |
| 5349 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
carll | 9fcbb9a | 2014-01-24 16:42:26 +0000 | [diff] [blame] | 5350 | IROp mkAdd = mode64 ? Iop_Add64 : Iop_Add32; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5351 | IRTemp EA = newTemp(ty); |
| 5352 | UInt r = 0; |
| 5353 | UInt ea_off = 0; |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 5354 | IRExpr* irx_addr; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5355 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5356 | assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 5357 | |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 5358 | switch (opc1) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5359 | case 0x2E: // lmw (Load Multiple Word, PPC32 p454) |
| 5360 | if (rA_addr >= rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5361 | vex_printf("dis_int_ldst_mult(ppc)(lmw,rA_addr)\n"); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 5362 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5363 | } |
| 5364 | DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); |
| 5365 | for (r = rD_addr; r <= 31; r++) { |
carll | 9fcbb9a | 2014-01-24 16:42:26 +0000 | [diff] [blame] | 5366 | irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5367 | putIReg( r, mkWidenFrom32(ty, load(Ity_I32, irx_addr ), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 5368 | False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5369 | ea_off += 4; |
| 5370 | } |
| 5371 | break; |
| 5372 | |
| 5373 | case 0x2F: // stmw (Store Multiple Word, PPC32 p527) |
| 5374 | DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
| 5375 | for (r = rS_addr; r <= 31; r++) { |
carll | 9fcbb9a | 2014-01-24 16:42:26 +0000 | [diff] [blame] | 5376 | irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5377 | store( irx_addr, mkNarrowTo32(ty, getIReg(r)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5378 | ea_off += 4; |
| 5379 | } |
| 5380 | break; |
| 5381 | |
| 5382 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5383 | vex_printf("dis_int_ldst_mult(ppc)(opc1)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5384 | return False; |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 5385 | } |
| 5386 | return True; |
| 5387 | } |
| 5388 | |
| 5389 | |
| 5390 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5391 | /* |
| 5392 | Integer Load/Store String Instructions |
| 5393 | */ |
| 5394 | static |
| 5395 | void generate_lsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32 |
| 5396 | IRTemp EA, // EA |
| 5397 | Int rD, // first dst register |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5398 | Int maxBytes ) // 32 or 128 |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5399 | { |
| 5400 | Int i, shift = 24; |
| 5401 | IRExpr* e_nbytes = mkexpr(tNBytes); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5402 | IRExpr* e_EA = mkexpr(EA); |
| 5403 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5404 | |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5405 | vassert(rD >= 0 && rD < 32); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5406 | rD--; if (rD < 0) rD = 31; |
| 5407 | |
| 5408 | for (i = 0; i < maxBytes; i++) { |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5409 | /* if (nBytes < (i+1)) goto NIA; */ |
| 5410 | stmt( IRStmt_Exit( binop(Iop_CmpLT32U, e_nbytes, mkU32(i+1)), |
| 5411 | Ijk_Boring, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5412 | mkSzConst( ty, nextInsnAddr()), OFFB_CIA )); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5413 | /* when crossing into a new dest register, set it to zero. */ |
| 5414 | if ((i % 4) == 0) { |
| 5415 | rD++; if (rD == 32) rD = 0; |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5416 | putIReg(rD, mkSzImm(ty, 0)); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5417 | shift = 24; |
| 5418 | } |
| 5419 | /* rD |= (8Uto32(*(EA+i))) << shift */ |
| 5420 | vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24); |
sewardj | 2ef8a37 | 2006-01-28 17:07:19 +0000 | [diff] [blame] | 5421 | putIReg( |
| 5422 | rD, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 5423 | mkWidenFrom32( |
sewardj | 2ef8a37 | 2006-01-28 17:07:19 +0000 | [diff] [blame] | 5424 | ty, |
| 5425 | binop( |
| 5426 | Iop_Or32, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 5427 | mkNarrowTo32(ty, getIReg(rD)), |
sewardj | 2ef8a37 | 2006-01-28 17:07:19 +0000 | [diff] [blame] | 5428 | binop( |
| 5429 | Iop_Shl32, |
| 5430 | unop( |
| 5431 | Iop_8Uto32, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5432 | load( Ity_I8, |
| 5433 | binop( mkSzOp(ty,Iop_Add8), |
| 5434 | e_EA, mkSzImm(ty,i))) |
sewardj | 2ef8a37 | 2006-01-28 17:07:19 +0000 | [diff] [blame] | 5435 | ), |
| 5436 | mkU8(toUChar(shift)) |
| 5437 | ) |
| 5438 | ), |
| 5439 | /*Signed*/False |
| 5440 | ) |
| 5441 | ); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5442 | shift -= 8; |
| 5443 | } |
| 5444 | } |
| 5445 | |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5446 | static |
| 5447 | void generate_stsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32 |
| 5448 | IRTemp EA, // EA |
| 5449 | Int rS, // first src register |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5450 | Int maxBytes ) // 32 or 128 |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5451 | { |
| 5452 | Int i, shift = 24; |
| 5453 | IRExpr* e_nbytes = mkexpr(tNBytes); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5454 | IRExpr* e_EA = mkexpr(EA); |
| 5455 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5456 | |
| 5457 | vassert(rS >= 0 && rS < 32); |
| 5458 | rS--; if (rS < 0) rS = 31; |
| 5459 | |
| 5460 | for (i = 0; i < maxBytes; i++) { |
| 5461 | /* if (nBytes < (i+1)) goto NIA; */ |
| 5462 | stmt( IRStmt_Exit( binop(Iop_CmpLT32U, e_nbytes, mkU32(i+1)), |
| 5463 | Ijk_Boring, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5464 | mkSzConst( ty, nextInsnAddr() ), OFFB_CIA )); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5465 | /* check for crossing into a new src register. */ |
| 5466 | if ((i % 4) == 0) { |
| 5467 | rS++; if (rS == 32) rS = 0; |
| 5468 | shift = 24; |
| 5469 | } |
| 5470 | /* *(EA+i) = 32to8(rS >> shift) */ |
| 5471 | vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5472 | store( |
| 5473 | binop( mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)), |
| 5474 | unop( Iop_32to8, |
| 5475 | binop( Iop_Shr32, |
| 5476 | mkNarrowTo32( ty, getIReg(rS) ), |
| 5477 | mkU8( toUChar(shift) ))) |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5478 | ); |
| 5479 | shift -= 8; |
| 5480 | } |
| 5481 | } |
| 5482 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5483 | static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere ) |
| 5484 | { |
| 5485 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5486 | UChar opc1 = ifieldOPC(theInstr); |
| 5487 | UChar rD_addr = ifieldRegDS(theInstr); |
| 5488 | UChar rS_addr = rD_addr; |
| 5489 | UChar rA_addr = ifieldRegA(theInstr); |
| 5490 | UChar rB_addr = ifieldRegB(theInstr); |
| 5491 | UChar NumBytes = rB_addr; |
| 5492 | UInt opc2 = ifieldOPClo10(theInstr); |
| 5493 | UChar b0 = ifieldBIT0(theInstr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5494 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5495 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 5496 | IRTemp t_EA = newTemp(ty); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5497 | IRTemp t_nbytes = IRTemp_INVALID; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5498 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5499 | *stopHere = False; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5500 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5501 | if (opc1 != 0x1F || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5502 | vex_printf("dis_int_ldst_str(ppc)(opc1)\n"); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5503 | return False; |
| 5504 | } |
| 5505 | |
| 5506 | switch (opc2) { |
| 5507 | case 0x255: // lswi (Load String Word Immediate, PPC32 p455) |
| 5508 | /* NB: does not reject the case where RA is in the range of |
| 5509 | registers to be loaded. It should. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5510 | DIP("lswi r%u,r%u,%d\n", rD_addr, rA_addr, NumBytes); |
| 5511 | assign( t_EA, ea_rAor0(rA_addr) ); |
sewardj | 2ef8a37 | 2006-01-28 17:07:19 +0000 | [diff] [blame] | 5512 | if (NumBytes == 8 && !mode64) { |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5513 | /* Special case hack */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5514 | /* rD = Mem[EA]; (rD+1)%32 = Mem[EA+4] */ |
| 5515 | putIReg( rD_addr, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5516 | load(Ity_I32, mkexpr(t_EA)) ); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5517 | putIReg( (rD_addr+1) % 32, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5518 | load(Ity_I32, |
| 5519 | binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) ); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5520 | } else { |
| 5521 | t_nbytes = newTemp(Ity_I32); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5522 | assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5523 | generate_lsw_sequence( t_nbytes, t_EA, rD_addr, 32 ); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5524 | *stopHere = True; |
| 5525 | } |
| 5526 | return True; |
| 5527 | |
| 5528 | case 0x215: // lswx (Load String Word Indexed, PPC32 p456) |
| 5529 | /* NB: does not reject the case where RA is in the range of |
| 5530 | registers to be loaded. It should. Although considering |
| 5531 | that that can only be detected at run time, it's not easy to |
| 5532 | do so. */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5533 | if (rD_addr == rA_addr || rD_addr == rB_addr) |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5534 | return False; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5535 | if (rD_addr == 0 && rA_addr == 0) |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5536 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5537 | DIP("lswx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5538 | t_nbytes = newTemp(Ity_I32); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5539 | assign( t_EA, ea_rAor0_idxd(rA_addr,rB_addr) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5540 | assign( t_nbytes, unop( Iop_8Uto32, getXER_BC() ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5541 | generate_lsw_sequence( t_nbytes, t_EA, rD_addr, 128 ); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5542 | *stopHere = True; |
| 5543 | return True; |
| 5544 | |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5545 | case 0x2D5: // stswi (Store String Word Immediate, PPC32 p528) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5546 | DIP("stswi r%u,r%u,%d\n", rS_addr, rA_addr, NumBytes); |
| 5547 | assign( t_EA, ea_rAor0(rA_addr) ); |
sewardj | 2ef8a37 | 2006-01-28 17:07:19 +0000 | [diff] [blame] | 5548 | if (NumBytes == 8 && !mode64) { |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5549 | /* Special case hack */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5550 | /* Mem[EA] = rD; Mem[EA+4] = (rD+1)%32 */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 5551 | store( mkexpr(t_EA), |
| 5552 | getIReg(rD_addr) ); |
| 5553 | store( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)), |
| 5554 | getIReg((rD_addr+1) % 32) ); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5555 | } else { |
| 5556 | t_nbytes = newTemp(Ity_I32); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5557 | assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5558 | generate_stsw_sequence( t_nbytes, t_EA, rD_addr, 32 ); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5559 | *stopHere = True; |
| 5560 | } |
| 5561 | return True; |
| 5562 | |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5563 | case 0x295: // stswx (Store String Word Indexed, PPC32 p529) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5564 | DIP("stswx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5565 | t_nbytes = newTemp(Ity_I32); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5566 | assign( t_EA, ea_rAor0_idxd(rA_addr,rB_addr) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5567 | assign( t_nbytes, unop( Iop_8Uto32, getXER_BC() ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5568 | generate_stsw_sequence( t_nbytes, t_EA, rS_addr, 128 ); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 5569 | *stopHere = True; |
| 5570 | return True; |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5571 | |
| 5572 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5573 | vex_printf("dis_int_ldst_str(ppc)(opc2)\n"); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 5574 | return False; |
| 5575 | } |
| 5576 | return True; |
| 5577 | } |
| 5578 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5579 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5580 | /* ------------------------------------------------------------------ |
| 5581 | Integer Branch Instructions |
| 5582 | ------------------------------------------------------------------ */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 5583 | |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 5584 | /* |
| 5585 | Branch helper function |
| 5586 | ok = BO[2] | ((CTR[0] != 0) ^ BO[1]) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5587 | Returns an I32 which is 0x00000000 if the ctr condition failed |
| 5588 | and 0xFFFFFFFF otherwise. |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 5589 | */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5590 | static IRExpr* /* :: Ity_I32 */ branch_ctr_ok( UInt BO ) |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 5591 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5592 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5593 | IRTemp ok = newTemp(Ity_I32); |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 5594 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5595 | if ((BO >> 2) & 1) { // independent of ctr |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5596 | assign( ok, mkU32(0xFFFFFFFF) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5597 | } else { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5598 | if ((BO >> 1) & 1) { // ctr == 0 ? |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5599 | assign( ok, unop( Iop_1Sto32, |
cerion | 4e2c2b3 | 2006-01-02 13:35:51 +0000 | [diff] [blame] | 5600 | binop( mkSzOp(ty, Iop_CmpEQ8), |
| 5601 | getGST( PPC_GST_CTR ), |
| 5602 | mkSzImm(ty,0))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5603 | } else { // ctr != 0 ? |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5604 | assign( ok, unop( Iop_1Sto32, |
cerion | 4e2c2b3 | 2006-01-02 13:35:51 +0000 | [diff] [blame] | 5605 | binop( mkSzOp(ty, Iop_CmpNE8), |
| 5606 | getGST( PPC_GST_CTR ), |
| 5607 | mkSzImm(ty,0))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5608 | } |
| 5609 | } |
| 5610 | return mkexpr(ok); |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 5611 | } |
| 5612 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5613 | |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 5614 | /* |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5615 | Branch helper function cond_ok = BO[4] | (CR[BI] == BO[3]) |
| 5616 | Returns an I32 which is either 0 if the condition failed or |
| 5617 | some arbitrary nonzero value otherwise. */ |
| 5618 | |
| 5619 | static IRExpr* /* :: Ity_I32 */ branch_cond_ok( UInt BO, UInt BI ) |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 5620 | { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5621 | Int where; |
| 5622 | IRTemp res = newTemp(Ity_I32); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5623 | IRTemp cr_bi = newTemp(Ity_I32); |
| 5624 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5625 | if ((BO >> 4) & 1) { |
| 5626 | assign( res, mkU32(1) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5627 | } else { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5628 | // ok = (CR[BI] == BO[3]) Note, the following relies on |
| 5629 | // getCRbit_anywhere returning a value which |
| 5630 | // is either zero or has exactly 1 bit set. |
| 5631 | assign( cr_bi, getCRbit_anywhere( BI, &where ) ); |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5632 | |
| 5633 | if ((BO >> 3) & 1) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5634 | /* We can use cr_bi as-is. */ |
| 5635 | assign( res, mkexpr(cr_bi) ); |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5636 | } else { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5637 | /* We have to invert the sense of the information held in |
| 5638 | cr_bi. For that we need to know which bit |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5639 | getCRbit_anywhere regards as significant. */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5640 | assign( res, binop(Iop_Xor32, mkexpr(cr_bi), |
| 5641 | mkU32(1<<where)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5642 | } |
| 5643 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5644 | return mkexpr(res); |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 5645 | } |
| 5646 | |
| 5647 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5648 | /* |
| 5649 | Integer Branch Instructions |
| 5650 | */ |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 5651 | static Bool dis_branch ( UInt theInstr, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5652 | VexAbiInfo* vbi, |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 5653 | /*OUT*/DisResult* dres, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 5654 | Bool (*resteerOkFn)(void*,Addr64), |
| 5655 | void* callback_opaque ) |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 5656 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5657 | UChar opc1 = ifieldOPC(theInstr); |
| 5658 | UChar BO = ifieldRegDS(theInstr); |
| 5659 | UChar BI = ifieldRegA(theInstr); |
| 5660 | UInt BD_u16 = ifieldUIMM16(theInstr) & 0xFFFFFFFC; /* mask off */ |
| 5661 | UChar b11to15 = ifieldRegB(theInstr); |
| 5662 | UInt opc2 = ifieldOPClo10(theInstr); |
| 5663 | UInt LI_u26 = ifieldUIMM26(theInstr) & 0xFFFFFFFC; /* mask off */ |
| 5664 | UChar flag_AA = ifieldBIT1(theInstr); |
| 5665 | UChar flag_LK = ifieldBIT0(theInstr); |
| 5666 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5667 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5668 | Addr64 tgt = 0; |
| 5669 | Int BD = extend_s_16to32(BD_u16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5670 | IRTemp do_branch = newTemp(Ity_I32); |
| 5671 | IRTemp ctr_ok = newTemp(Ity_I32); |
| 5672 | IRTemp cond_ok = newTemp(Ity_I32); |
| 5673 | IRExpr* e_nia = mkSzImm(ty, nextInsnAddr()); |
| 5674 | IRConst* c_nia = mkSzConst(ty, nextInsnAddr()); |
sewardj | df07b88 | 2005-11-29 18:19:11 +0000 | [diff] [blame] | 5675 | IRTemp lr_old = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5676 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5677 | /* Hack to pass through code that just wants to read the PC */ |
| 5678 | if (theInstr == 0x429F0005) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5679 | DIP("bcl 0x%x, 0x%x (a.k.a mr lr,cia+4)\n", BO, BI); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5680 | putGST( PPC_GST_LR, e_nia ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5681 | return True; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5682 | } |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 5683 | |
| 5684 | /* The default what-next. Individual cases can override it. */ |
| 5685 | dres->whatNext = Dis_StopHere; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5686 | vassert(dres->jk_StopHere == Ijk_INVALID); |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 5687 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5688 | switch (opc1) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5689 | case 0x12: // b (Branch, PPC32 p360) |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 5690 | if (flag_AA) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5691 | tgt = mkSzAddr( ty, extend_s_26to64(LI_u26) ); |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 5692 | } else { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5693 | tgt = mkSzAddr( ty, guest_CIA_curr_instr + |
| 5694 | (Long)extend_s_26to64(LI_u26) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5695 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5696 | if (mode64) { |
| 5697 | DIP("b%s%s 0x%llx\n", |
| 5698 | flag_LK ? "l" : "", flag_AA ? "a" : "", tgt); |
| 5699 | } else { |
| 5700 | DIP("b%s%s 0x%x\n", |
| 5701 | flag_LK ? "l" : "", flag_AA ? "a" : "", (Addr32)tgt); |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 5702 | } |
| 5703 | |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 5704 | if (flag_LK) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5705 | putGST( PPC_GST_LR, e_nia ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5706 | if (vbi->guest_ppc_zap_RZ_at_bl |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 5707 | && vbi->guest_ppc_zap_RZ_at_bl( (ULong)tgt) ) { |
| 5708 | IRTemp t_tgt = newTemp(ty); |
| 5709 | assign(t_tgt, mode64 ? mkU64(tgt) : mkU32(tgt) ); |
| 5710 | make_redzone_AbiHint( vbi, t_tgt, |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 5711 | "branch-and-link (unconditional call)" ); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 5712 | } |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 5713 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5714 | |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 5715 | if (resteerOkFn( callback_opaque, tgt )) { |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 5716 | dres->whatNext = Dis_ResteerU; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5717 | dres->continueAt = tgt; |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 5718 | } else { |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5719 | dres->jk_StopHere = flag_LK ? Ijk_Call : Ijk_Boring; ; |
| 5720 | putGST( PPC_GST_CIA, mkSzImm(ty, tgt) ); |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 5721 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5722 | break; |
| 5723 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5724 | case 0x10: // bc (Branch Conditional, PPC32 p361) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5725 | DIP("bc%s%s 0x%x, 0x%x, 0x%x\n", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5726 | flag_LK ? "l" : "", flag_AA ? "a" : "", BO, BI, BD); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5727 | |
| 5728 | if (!(BO & 0x4)) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5729 | putGST( PPC_GST_CTR, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5730 | binop(mkSzOp(ty, Iop_Sub8), |
| 5731 | getGST( PPC_GST_CTR ), mkSzImm(ty, 1)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5732 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5733 | |
| 5734 | /* This is a bit subtle. ctr_ok is either all 0s or all 1s. |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5735 | cond_ok is either zero or nonzero, since that's the cheapest |
| 5736 | way to compute it. Anding them together gives a value which |
| 5737 | is either zero or non zero and so that's what we must test |
| 5738 | for in the IRStmt_Exit. */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5739 | assign( ctr_ok, branch_ctr_ok( BO ) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5740 | assign( cond_ok, branch_cond_ok( BO, BI ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5741 | assign( do_branch, |
| 5742 | binop(Iop_And32, mkexpr(cond_ok), mkexpr(ctr_ok)) ); |
| 5743 | |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 5744 | if (flag_AA) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5745 | tgt = mkSzAddr(ty, extend_s_16to64(BD_u16)); |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 5746 | } else { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5747 | tgt = mkSzAddr(ty, guest_CIA_curr_instr + |
| 5748 | (Long)extend_s_16to64(BD_u16)); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5749 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5750 | if (flag_LK) |
| 5751 | putGST( PPC_GST_LR, e_nia ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5752 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5753 | stmt( IRStmt_Exit( |
| 5754 | binop(Iop_CmpNE32, mkexpr(do_branch), mkU32(0)), |
| 5755 | flag_LK ? Ijk_Call : Ijk_Boring, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5756 | mkSzConst(ty, tgt), OFFB_CIA ) ); |
| 5757 | |
| 5758 | dres->jk_StopHere = Ijk_Boring; |
| 5759 | putGST( PPC_GST_CIA, e_nia ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5760 | break; |
| 5761 | |
| 5762 | case 0x13: |
sewardj | 6be6723 | 2006-01-24 19:00:05 +0000 | [diff] [blame] | 5763 | /* For bclr and bcctr, it appears that the lowest two bits of |
| 5764 | b11to15 are a branch hint, and so we only need to ensure it's |
| 5765 | of the form 000XX. */ |
| 5766 | if ((b11to15 & ~3) != 0) { |
| 5767 | vex_printf("dis_int_branch(ppc)(0x13,b11to15)(%d)\n", (Int)b11to15); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5768 | return False; |
| 5769 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 5770 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5771 | switch (opc2) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5772 | case 0x210: // bcctr (Branch Cond. to Count Register, PPC32 p363) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5773 | if ((BO & 0x4) == 0) { // "decr and test CTR" option invalid |
| 5774 | vex_printf("dis_int_branch(ppc)(bcctr,BO)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5775 | return False; |
| 5776 | } |
cerion | a31e8b5 | 2005-02-21 16:30:45 +0000 | [diff] [blame] | 5777 | DIP("bcctr%s 0x%x, 0x%x\n", flag_LK ? "l" : "", BO, BI); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5778 | |
| 5779 | assign( cond_ok, branch_cond_ok( BO, BI ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5780 | |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 5781 | /* FIXME: this is confusing. lr_old holds the old value |
| 5782 | of ctr, not lr :-) */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5783 | assign( lr_old, addr_align( getGST( PPC_GST_CTR ), 4 )); |
sewardj | df07b88 | 2005-11-29 18:19:11 +0000 | [diff] [blame] | 5784 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5785 | if (flag_LK) |
| 5786 | putGST( PPC_GST_LR, e_nia ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5787 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5788 | stmt( IRStmt_Exit( |
| 5789 | binop(Iop_CmpEQ32, mkexpr(cond_ok), mkU32(0)), |
| 5790 | Ijk_Boring, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5791 | c_nia, OFFB_CIA )); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 5792 | |
| 5793 | if (flag_LK && vbi->guest_ppc_zap_RZ_at_bl) { |
| 5794 | make_redzone_AbiHint( vbi, lr_old, |
| 5795 | "b-ctr-l (indirect call)" ); |
| 5796 | } |
| 5797 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5798 | dres->jk_StopHere = flag_LK ? Ijk_Call : Ijk_Boring;; |
| 5799 | putGST( PPC_GST_CIA, mkexpr(lr_old) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5800 | break; |
| 5801 | |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 5802 | case 0x010: { // bclr (Branch Cond. to Link Register, PPC32 p365) |
| 5803 | Bool vanilla_return = False; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5804 | if ((BO & 0x14 /* 1z1zz */) == 0x14 && flag_LK == 0) { |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 5805 | DIP("blr\n"); |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 5806 | vanilla_return = True; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5807 | } else { |
| 5808 | DIP("bclr%s 0x%x, 0x%x\n", flag_LK ? "l" : "", BO, BI); |
| 5809 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 5810 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5811 | if (!(BO & 0x4)) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5812 | putGST( PPC_GST_CTR, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5813 | binop(mkSzOp(ty, Iop_Sub8), |
| 5814 | getGST( PPC_GST_CTR ), mkSzImm(ty, 1)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5815 | } |
| 5816 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5817 | /* See comments above for 'bc' about this */ |
| 5818 | assign( ctr_ok, branch_ctr_ok( BO ) ); |
| 5819 | assign( cond_ok, branch_cond_ok( BO, BI ) ); |
| 5820 | assign( do_branch, |
| 5821 | binop(Iop_And32, mkexpr(cond_ok), mkexpr(ctr_ok)) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5822 | |
sewardj | df07b88 | 2005-11-29 18:19:11 +0000 | [diff] [blame] | 5823 | assign( lr_old, addr_align( getGST( PPC_GST_LR ), 4 )); |
| 5824 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5825 | if (flag_LK) |
| 5826 | putGST( PPC_GST_LR, e_nia ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5827 | |
| 5828 | stmt( IRStmt_Exit( |
| 5829 | binop(Iop_CmpEQ32, mkexpr(do_branch), mkU32(0)), |
| 5830 | Ijk_Boring, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5831 | c_nia, OFFB_CIA )); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5832 | |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 5833 | if (vanilla_return && vbi->guest_ppc_zap_RZ_at_blr) { |
| 5834 | make_redzone_AbiHint( vbi, lr_old, |
| 5835 | "branch-to-lr (unconditional return)" ); |
| 5836 | } |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 5837 | |
sewardj | d37be03 | 2005-11-12 12:56:31 +0000 | [diff] [blame] | 5838 | /* blrl is pretty strange; it's like a return that sets the |
| 5839 | return address of its caller to the insn following this |
| 5840 | one. Mark it as a return. */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5841 | dres->jk_StopHere = Ijk_Ret; /* was flag_LK ? Ijk_Call : Ijk_Ret; */ |
| 5842 | putGST( PPC_GST_CIA, mkexpr(lr_old) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5843 | break; |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 5844 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5845 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5846 | vex_printf("dis_int_branch(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5847 | return False; |
| 5848 | } |
| 5849 | break; |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5850 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5851 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5852 | vex_printf("dis_int_branch(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5853 | return False; |
| 5854 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5855 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5856 | return True; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 5857 | } |
| 5858 | |
| 5859 | |
| 5860 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5861 | /* |
| 5862 | Condition Register Logical Instructions |
| 5863 | */ |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5864 | static Bool dis_cond_logic ( UInt theInstr ) |
| 5865 | { |
| 5866 | /* XL-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5867 | UChar opc1 = ifieldOPC(theInstr); |
| 5868 | UChar crbD_addr = ifieldRegDS(theInstr); |
| 5869 | UChar crfD_addr = toUChar( IFIELD(theInstr, 23, 3) ); |
| 5870 | UChar crbA_addr = ifieldRegA(theInstr); |
| 5871 | UChar crfS_addr = toUChar( IFIELD(theInstr, 18, 3) ); |
| 5872 | UChar crbB_addr = ifieldRegB(theInstr); |
| 5873 | UInt opc2 = ifieldOPClo10(theInstr); |
| 5874 | UChar b0 = ifieldBIT0(theInstr); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5875 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5876 | IRTemp crbD = newTemp(Ity_I32); |
| 5877 | IRTemp crbA = newTemp(Ity_I32); |
| 5878 | IRTemp crbB = newTemp(Ity_I32); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5879 | |
| 5880 | if (opc1 != 19 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5881 | vex_printf("dis_cond_logic(ppc)(opc1)\n"); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5882 | return False; |
| 5883 | } |
| 5884 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5885 | if (opc2 == 0) { // mcrf (Move Cond Reg Field, PPC32 p464) |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5886 | if (((crbD_addr & 0x3) != 0) || |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5887 | ((crbA_addr & 0x3) != 0) || (crbB_addr != 0)) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5888 | vex_printf("dis_cond_logic(ppc)(crbD|crbA|crbB != 0)\n"); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5889 | return False; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5890 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5891 | DIP("mcrf cr%u,cr%u\n", crfD_addr, crfS_addr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5892 | putCR0( crfD_addr, getCR0( crfS_addr) ); |
| 5893 | putCR321( crfD_addr, getCR321(crfS_addr) ); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5894 | } else { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5895 | assign( crbA, getCRbit(crbA_addr) ); |
cerion | a50fde5 | 2005-07-01 21:16:10 +0000 | [diff] [blame] | 5896 | if (crbA_addr == crbB_addr) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5897 | crbB = crbA; |
cerion | a50fde5 | 2005-07-01 21:16:10 +0000 | [diff] [blame] | 5898 | else |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5899 | assign( crbB, getCRbit(crbB_addr) ); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5900 | |
| 5901 | switch (opc2) { |
sewardj | 7c2dc71 | 2005-09-08 17:33:27 +0000 | [diff] [blame] | 5902 | case 0x101: // crand (Cond Reg AND, PPC32 p372) |
| 5903 | DIP("crand crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 5904 | assign( crbD, binop(Iop_And32, mkexpr(crbA), mkexpr(crbB)) ); |
| 5905 | break; |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 5906 | case 0x081: // crandc (Cond Reg AND w. Complement, PPC32 p373) |
| 5907 | DIP("crandc crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 5908 | assign( crbD, binop(Iop_And32, |
| 5909 | mkexpr(crbA), |
| 5910 | unop(Iop_Not32, mkexpr(crbB))) ); |
| 5911 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5912 | case 0x121: // creqv (Cond Reg Equivalent, PPC32 p374) |
| 5913 | DIP("creqv crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 5914 | assign( crbD, unop(Iop_Not32, |
| 5915 | binop(Iop_Xor32, mkexpr(crbA), mkexpr(crbB))) ); |
| 5916 | break; |
sewardj | 7c2dc71 | 2005-09-08 17:33:27 +0000 | [diff] [blame] | 5917 | case 0x0E1: // crnand (Cond Reg NAND, PPC32 p375) |
| 5918 | DIP("crnand crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 5919 | assign( crbD, unop(Iop_Not32, |
| 5920 | binop(Iop_And32, mkexpr(crbA), mkexpr(crbB))) ); |
| 5921 | break; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5922 | case 0x021: // crnor (Cond Reg NOR, PPC32 p376) |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5923 | DIP("crnor crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 5924 | assign( crbD, unop(Iop_Not32, |
| 5925 | binop(Iop_Or32, mkexpr(crbA), mkexpr(crbB))) ); |
| 5926 | break; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5927 | case 0x1C1: // cror (Cond Reg OR, PPC32 p377) |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5928 | DIP("cror crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 5929 | assign( crbD, binop(Iop_Or32, mkexpr(crbA), mkexpr(crbB)) ); |
| 5930 | break; |
sewardj | 7c2dc71 | 2005-09-08 17:33:27 +0000 | [diff] [blame] | 5931 | case 0x1A1: // crorc (Cond Reg OR w. Complement, PPC32 p378) |
| 5932 | DIP("crorc crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 5933 | assign( crbD, binop(Iop_Or32, |
| 5934 | mkexpr(crbA), |
| 5935 | unop(Iop_Not32, mkexpr(crbB))) ); |
| 5936 | break; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5937 | case 0x0C1: // crxor (Cond Reg XOR, PPC32 p379) |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5938 | DIP("crxor crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 5939 | assign( crbD, binop(Iop_Xor32, mkexpr(crbA), mkexpr(crbB)) ); |
| 5940 | break; |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5941 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5942 | vex_printf("dis_cond_logic(ppc)(opc2)\n"); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5943 | return False; |
| 5944 | } |
| 5945 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5946 | putCRbit( crbD_addr, mkexpr(crbD) ); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 5947 | } |
| 5948 | return True; |
| 5949 | } |
| 5950 | |
| 5951 | |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 5952 | /* |
| 5953 | Trap instructions |
| 5954 | */ |
| 5955 | |
| 5956 | /* Do the code generation for a trap. Returned Bool is true iff |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 5957 | this is an unconditional trap. If the two arg IRExpr*s are |
| 5958 | Ity_I32s then the comparison is 32-bit. If they are Ity_I64s |
| 5959 | then they are 64-bit, and we must be disassembling 64-bit |
| 5960 | instructions. */ |
| 5961 | static Bool do_trap ( UChar TO, |
| 5962 | IRExpr* argL0, IRExpr* argR0, Addr64 cia ) |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 5963 | { |
| 5964 | IRTemp argL, argR; |
| 5965 | IRExpr *argLe, *argRe, *cond, *tmp; |
| 5966 | |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 5967 | Bool is32bit = typeOfIRExpr(irsb->tyenv, argL0 ) == Ity_I32; |
| 5968 | |
| 5969 | IROp opAND = is32bit ? Iop_And32 : Iop_And64; |
| 5970 | IROp opOR = is32bit ? Iop_Or32 : Iop_Or64; |
| 5971 | IROp opCMPORDS = is32bit ? Iop_CmpORD32S : Iop_CmpORD64S; |
| 5972 | IROp opCMPORDU = is32bit ? Iop_CmpORD32U : Iop_CmpORD64U; |
| 5973 | IROp opCMPNE = is32bit ? Iop_CmpNE32 : Iop_CmpNE64; |
| 5974 | IROp opCMPEQ = is32bit ? Iop_CmpEQ32 : Iop_CmpEQ64; |
| 5975 | IRExpr* const0 = is32bit ? mkU32(0) : mkU64(0); |
| 5976 | IRExpr* const2 = is32bit ? mkU32(2) : mkU64(2); |
| 5977 | IRExpr* const4 = is32bit ? mkU32(4) : mkU64(4); |
| 5978 | IRExpr* const8 = is32bit ? mkU32(8) : mkU64(8); |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 5979 | |
| 5980 | const UChar b11100 = 0x1C; |
| 5981 | const UChar b00111 = 0x07; |
| 5982 | |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 5983 | if (is32bit) { |
| 5984 | vassert( typeOfIRExpr(irsb->tyenv, argL0) == Ity_I32 ); |
| 5985 | vassert( typeOfIRExpr(irsb->tyenv, argR0) == Ity_I32 ); |
| 5986 | } else { |
| 5987 | vassert( typeOfIRExpr(irsb->tyenv, argL0) == Ity_I64 ); |
| 5988 | vassert( typeOfIRExpr(irsb->tyenv, argR0) == Ity_I64 ); |
| 5989 | vassert( mode64 ); |
| 5990 | } |
| 5991 | |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 5992 | if ((TO & b11100) == b11100 || (TO & b00111) == b00111) { |
| 5993 | /* Unconditional trap. Just do the exit without |
| 5994 | testing the arguments. */ |
| 5995 | stmt( IRStmt_Exit( |
| 5996 | binop(opCMPEQ, const0, const0), |
sewardj | 0f50004 | 2007-08-29 09:09:17 +0000 | [diff] [blame] | 5997 | Ijk_SigTRAP, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 5998 | mode64 ? IRConst_U64(cia) : IRConst_U32((UInt)cia), |
| 5999 | OFFB_CIA |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6000 | )); |
| 6001 | return True; /* unconditional trap */ |
| 6002 | } |
| 6003 | |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 6004 | if (is32bit) { |
sewardj | 2d19fe3 | 2006-02-07 20:55:08 +0000 | [diff] [blame] | 6005 | argL = newTemp(Ity_I32); |
| 6006 | argR = newTemp(Ity_I32); |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6007 | } else { |
sewardj | 2d19fe3 | 2006-02-07 20:55:08 +0000 | [diff] [blame] | 6008 | argL = newTemp(Ity_I64); |
| 6009 | argR = newTemp(Ity_I64); |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6010 | } |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 6011 | |
| 6012 | assign( argL, argL0 ); |
| 6013 | assign( argR, argR0 ); |
| 6014 | |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6015 | argLe = mkexpr(argL); |
| 6016 | argRe = mkexpr(argR); |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 6017 | |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6018 | cond = const0; |
| 6019 | if (TO & 16) { // L <s R |
| 6020 | tmp = binop(opAND, binop(opCMPORDS, argLe, argRe), const8); |
| 6021 | cond = binop(opOR, tmp, cond); |
| 6022 | } |
| 6023 | if (TO & 8) { // L >s R |
| 6024 | tmp = binop(opAND, binop(opCMPORDS, argLe, argRe), const4); |
| 6025 | cond = binop(opOR, tmp, cond); |
| 6026 | } |
| 6027 | if (TO & 4) { // L == R |
| 6028 | tmp = binop(opAND, binop(opCMPORDS, argLe, argRe), const2); |
| 6029 | cond = binop(opOR, tmp, cond); |
| 6030 | } |
| 6031 | if (TO & 2) { // L <u R |
| 6032 | tmp = binop(opAND, binop(opCMPORDU, argLe, argRe), const8); |
| 6033 | cond = binop(opOR, tmp, cond); |
| 6034 | } |
| 6035 | if (TO & 1) { // L >u R |
| 6036 | tmp = binop(opAND, binop(opCMPORDU, argLe, argRe), const4); |
| 6037 | cond = binop(opOR, tmp, cond); |
| 6038 | } |
| 6039 | stmt( IRStmt_Exit( |
| 6040 | binop(opCMPNE, cond, const0), |
sewardj | 0f50004 | 2007-08-29 09:09:17 +0000 | [diff] [blame] | 6041 | Ijk_SigTRAP, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6042 | mode64 ? IRConst_U64(cia) : IRConst_U32((UInt)cia), |
| 6043 | OFFB_CIA |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6044 | )); |
| 6045 | return False; /* not an unconditional trap */ |
| 6046 | } |
| 6047 | |
| 6048 | static Bool dis_trapi ( UInt theInstr, |
| 6049 | /*OUT*/DisResult* dres ) |
| 6050 | { |
| 6051 | /* D-Form */ |
| 6052 | UChar opc1 = ifieldOPC(theInstr); |
| 6053 | UChar TO = ifieldRegDS(theInstr); |
| 6054 | UChar rA_addr = ifieldRegA(theInstr); |
| 6055 | UInt uimm16 = ifieldUIMM16(theInstr); |
| 6056 | ULong simm16 = extend_s_16to64(uimm16); |
| 6057 | Addr64 cia = guest_CIA_curr_instr; |
| 6058 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 6059 | Bool uncond = False; |
| 6060 | |
| 6061 | switch (opc1) { |
| 6062 | case 0x03: // twi (Trap Word Immediate, PPC32 p548) |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 6063 | uncond = do_trap( TO, |
| 6064 | mode64 ? unop(Iop_64to32, getIReg(rA_addr)) |
| 6065 | : getIReg(rA_addr), |
sewardj | b4f6d6b | 2007-08-28 16:39:52 +0000 | [diff] [blame] | 6066 | mkU32( (UInt)simm16 ), |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 6067 | cia ); |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6068 | if (TO == 4) { |
| 6069 | DIP("tweqi r%u,%d\n", (UInt)rA_addr, (Int)simm16); |
| 6070 | } else { |
| 6071 | DIP("tw%di r%u,%d\n", (Int)TO, (UInt)rA_addr, (Int)simm16); |
| 6072 | } |
| 6073 | break; |
| 6074 | case 0x02: // tdi |
| 6075 | if (!mode64) |
| 6076 | return False; |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 6077 | uncond = do_trap( TO, getIReg(rA_addr), mkU64( (ULong)simm16 ), cia ); |
sewardj | 2d19fe3 | 2006-02-07 20:55:08 +0000 | [diff] [blame] | 6078 | if (TO == 4) { |
| 6079 | DIP("tdeqi r%u,%d\n", (UInt)rA_addr, (Int)simm16); |
| 6080 | } else { |
| 6081 | DIP("td%di r%u,%d\n", (Int)TO, (UInt)rA_addr, (Int)simm16); |
| 6082 | } |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6083 | break; |
| 6084 | default: |
| 6085 | return False; |
| 6086 | } |
| 6087 | |
| 6088 | if (uncond) { |
| 6089 | /* If the trap shows signs of being unconditional, don't |
| 6090 | continue decoding past it. */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6091 | putGST( PPC_GST_CIA, mkSzImm( ty, nextInsnAddr() )); |
| 6092 | dres->jk_StopHere = Ijk_Boring; |
| 6093 | dres->whatNext = Dis_StopHere; |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6094 | } |
| 6095 | |
| 6096 | return True; |
| 6097 | } |
| 6098 | |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 6099 | static Bool dis_trap ( UInt theInstr, |
| 6100 | /*OUT*/DisResult* dres ) |
| 6101 | { |
| 6102 | /* X-Form */ |
| 6103 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6104 | UChar TO = ifieldRegDS(theInstr); |
| 6105 | UChar rA_addr = ifieldRegA(theInstr); |
| 6106 | UChar rB_addr = ifieldRegB(theInstr); |
| 6107 | Addr64 cia = guest_CIA_curr_instr; |
| 6108 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 6109 | Bool uncond = False; |
| 6110 | |
| 6111 | if (ifieldBIT0(theInstr) != 0) |
| 6112 | return False; |
| 6113 | |
| 6114 | switch (opc2) { |
| 6115 | case 0x004: // tw (Trap Word, PPC64 p540) |
| 6116 | uncond = do_trap( TO, |
| 6117 | mode64 ? unop(Iop_64to32, getIReg(rA_addr)) |
| 6118 | : getIReg(rA_addr), |
| 6119 | mode64 ? unop(Iop_64to32, getIReg(rB_addr)) |
| 6120 | : getIReg(rB_addr), |
| 6121 | cia ); |
| 6122 | if (TO == 4) { |
| 6123 | DIP("tweq r%u,r%u\n", (UInt)rA_addr, (UInt)rB_addr); |
| 6124 | } else { |
| 6125 | DIP("tw%d r%u,r%u\n", (Int)TO, (UInt)rA_addr, (UInt)rB_addr); |
| 6126 | } |
| 6127 | break; |
sewardj | b4f6d6b | 2007-08-28 16:39:52 +0000 | [diff] [blame] | 6128 | case 0x044: // td (Trap Doubleword, PPC64 p534) |
| 6129 | if (!mode64) |
| 6130 | return False; |
| 6131 | uncond = do_trap( TO, getIReg(rA_addr), getIReg(rB_addr), cia ); |
| 6132 | if (TO == 4) { |
| 6133 | DIP("tdeq r%u,r%u\n", (UInt)rA_addr, (UInt)rB_addr); |
| 6134 | } else { |
| 6135 | DIP("td%d r%u,r%u\n", (Int)TO, (UInt)rA_addr, (UInt)rB_addr); |
| 6136 | } |
| 6137 | break; |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 6138 | default: |
| 6139 | return False; |
| 6140 | } |
| 6141 | |
| 6142 | if (uncond) { |
| 6143 | /* If the trap shows signs of being unconditional, don't |
| 6144 | continue decoding past it. */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6145 | putGST( PPC_GST_CIA, mkSzImm( ty, nextInsnAddr() )); |
| 6146 | dres->jk_StopHere = Ijk_Boring; |
| 6147 | dres->whatNext = Dis_StopHere; |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 6148 | } |
| 6149 | |
| 6150 | return True; |
| 6151 | } |
| 6152 | |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 6153 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6154 | /* |
| 6155 | System Linkage Instructions |
| 6156 | */ |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 6157 | static Bool dis_syslink ( UInt theInstr, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 6158 | VexAbiInfo* abiinfo, DisResult* dres ) |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 6159 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6160 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 6161 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6162 | if (theInstr != 0x44000002) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6163 | vex_printf("dis_syslink(ppc)(theInstr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6164 | return False; |
| 6165 | } |
cerion | e1d857b | 2005-02-04 18:29:05 +0000 | [diff] [blame] | 6166 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 6167 | // sc (System Call, PPC32 p504) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6168 | DIP("sc\n"); |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 6169 | |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 6170 | /* Copy CIA into the IP_AT_SYSCALL pseudo-register, so that on AIX |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 6171 | Valgrind can back the guest up to this instruction if it needs |
| 6172 | to restart the syscall. */ |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 6173 | putGST( PPC_GST_IP_AT_SYSCALL, getGST( PPC_GST_CIA ) ); |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 6174 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6175 | /* It's important that all ArchRegs carry their up-to-date value |
| 6176 | at this point. So we declare an end-of-block here, which |
| 6177 | forces any TempRegs caching ArchRegs to be flushed. */ |
sewardj | d1526f2 | 2014-07-16 23:14:33 +0000 | [diff] [blame] | 6178 | putGST( PPC_GST_CIA, mkSzImm( ty, nextInsnAddr() )); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6179 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 6180 | dres->whatNext = Dis_StopHere; |
| 6181 | dres->jk_StopHere = Ijk_Sys_syscall; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6182 | return True; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 6183 | } |
| 6184 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6185 | |
| 6186 | /* |
| 6187 | Memory Synchronization Instructions |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6188 | |
| 6189 | Note on Reservations: |
| 6190 | We rely on the assumption that V will in fact only allow one thread at |
| 6191 | once to run. In effect, a thread can make a reservation, but we don't |
| 6192 | check any stores it does. Instead, the reservation is cancelled when |
| 6193 | the scheduler switches to another thread (run_thread_for_a_while()). |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6194 | */ |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 6195 | static Bool dis_memsync ( UInt theInstr ) |
| 6196 | { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6197 | /* X-Form, XL-Form */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6198 | UChar opc1 = ifieldOPC(theInstr); |
| 6199 | UInt b11to25 = IFIELD(theInstr, 11, 15); |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 6200 | UChar flag_L = ifieldRegDS(theInstr); |
| 6201 | UInt b11to20 = IFIELD(theInstr, 11, 10); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6202 | UChar rD_addr = ifieldRegDS(theInstr); |
| 6203 | UChar rS_addr = rD_addr; |
| 6204 | UChar rA_addr = ifieldRegA(theInstr); |
| 6205 | UChar rB_addr = ifieldRegB(theInstr); |
| 6206 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6207 | UChar b0 = ifieldBIT0(theInstr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6208 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6209 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 6210 | IRTemp EA = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6211 | |
| 6212 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
| 6213 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6214 | switch (opc1) { |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 6215 | /* XL-Form */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 6216 | case 0x13: // isync (Instruction Synchronize, PPC32 p432) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6217 | if (opc2 != 0x096) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6218 | vex_printf("dis_memsync(ppc)(0x13,opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6219 | return False; |
| 6220 | } |
| 6221 | if (b11to25 != 0 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6222 | vex_printf("dis_memsync(ppc)(0x13,b11to25|b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6223 | return False; |
| 6224 | } |
| 6225 | DIP("isync\n"); |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 6226 | stmt( IRStmt_MBE(Imbe_Fence) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6227 | break; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 6228 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6229 | /* X-Form */ |
| 6230 | case 0x1F: |
| 6231 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6232 | case 0x356: // eieio (Enforce In-Order Exec of I/O, PPC32 p394) |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 6233 | if (b11to25 != 0 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6234 | vex_printf("dis_memsync(ppc)(eiei0,b11to25|b0)\n"); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 6235 | return False; |
| 6236 | } |
| 6237 | DIP("eieio\n"); |
| 6238 | /* Insert a memory fence, just to be on the safe side. */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 6239 | stmt( IRStmt_MBE(Imbe_Fence) ); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 6240 | break; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 6241 | |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 6242 | case 0x014: { // lwarx (Load Word and Reserve Indexed, PPC32 p458) |
| 6243 | IRTemp res; |
sewardj | fe397a2 | 2008-08-06 19:13:42 +0000 | [diff] [blame] | 6244 | /* According to the PowerPC ISA version 2.05, b0 (called EH |
| 6245 | in the documentation) is merely a hint bit to the |
| 6246 | hardware, I think as to whether or not contention is |
| 6247 | likely. So we can just ignore it. */ |
| 6248 | DIP("lwarx r%u,r%u,r%u,EH=%u\n", rD_addr, rA_addr, rB_addr, (UInt)b0); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6249 | |
| 6250 | // trap if misaligned |
| 6251 | gen_SIGBUS_if_misaligned( EA, 4 ); |
| 6252 | |
| 6253 | // and actually do the load |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 6254 | res = newTemp(Ity_I32); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6255 | stmt( stmt_load(res, mkexpr(EA), NULL/*this is a load*/) ); |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 6256 | |
| 6257 | putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(res), False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6258 | break; |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 6259 | } |
| 6260 | |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 6261 | case 0x096: { |
| 6262 | // stwcx. (Store Word Conditional Indexed, PPC32 p532) |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6263 | // Note this has to handle stwcx. in both 32- and 64-bit modes, |
| 6264 | // so isn't quite as straightforward as it might otherwise be. |
| 6265 | IRTemp rS = newTemp(Ity_I32); |
| 6266 | IRTemp resSC; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6267 | if (b0 != 1) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6268 | vex_printf("dis_memsync(ppc)(stwcx.,b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6269 | return False; |
| 6270 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6271 | DIP("stwcx. r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 6272 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6273 | // trap if misaligned |
| 6274 | gen_SIGBUS_if_misaligned( EA, 4 ); |
| 6275 | |
| 6276 | // Get the data to be stored, and narrow to 32 bits if necessary |
| 6277 | assign( rS, mkNarrowTo32(ty, getIReg(rS_addr)) ); |
| 6278 | |
| 6279 | // Do the store, and get success/failure bit into resSC |
| 6280 | resSC = newTemp(Ity_I1); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6281 | stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6282 | |
| 6283 | // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure |
| 6284 | // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success |
| 6285 | putCR321(0, binop(Iop_Shl8, unop(Iop_1Uto8, mkexpr(resSC)), mkU8(1))); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 6286 | putCR0(0, getXER_SO()); |
| 6287 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6288 | /* Note: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6289 | If resaddr != lwarx_resaddr, CR0[EQ] is undefined, and |
| 6290 | whether rS is stored is dependent on that value. */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6291 | /* So I guess we can just ignore this case? */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6292 | break; |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 6293 | } |
| 6294 | |
sewardj | b029a61 | 2005-12-30 15:04:29 +0000 | [diff] [blame] | 6295 | case 0x256: // sync (Synchronize, PPC32 p543), |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 6296 | // also lwsync (L==1), ptesync (L==2) |
sewardj | b029a61 | 2005-12-30 15:04:29 +0000 | [diff] [blame] | 6297 | /* http://sources.redhat.com/ml/binutils/2000-12/msg00311.html |
| 6298 | |
| 6299 | The PowerPC architecture used in IBM chips has expanded |
| 6300 | the sync instruction into two variants: lightweight sync |
| 6301 | and heavyweight sync. The original sync instruction is |
| 6302 | the new heavyweight sync and lightweight sync is a strict |
| 6303 | subset of the heavyweight sync functionality. This allows |
| 6304 | the programmer to specify a less expensive operation on |
| 6305 | high-end systems when the full sync functionality is not |
| 6306 | necessary. |
| 6307 | |
| 6308 | The basic "sync" mnemonic now utilizes an operand. "sync" |
| 6309 | without an operand now becomes a extended mnemonic for |
| 6310 | heavyweight sync. Processors without the lwsync |
| 6311 | instruction will not decode the L field and will perform a |
| 6312 | heavyweight sync. Everything is backward compatible. |
| 6313 | |
| 6314 | sync = sync 0 |
| 6315 | lwsync = sync 1 |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 6316 | ptesync = sync 2 *** TODO - not implemented *** |
cerion | 4e2c2b3 | 2006-01-02 13:35:51 +0000 | [diff] [blame] | 6317 | */ |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 6318 | if (b11to20 != 0 || b0 != 0) { |
| 6319 | vex_printf("dis_memsync(ppc)(sync/lwsync,b11to20|b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6320 | return False; |
| 6321 | } |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 6322 | if (flag_L != 0/*sync*/ && flag_L != 1/*lwsync*/) { |
| 6323 | vex_printf("dis_memsync(ppc)(sync/lwsync,flag_L)\n"); |
| 6324 | return False; |
| 6325 | } |
| 6326 | DIP("%ssync\n", flag_L == 1 ? "lw" : ""); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6327 | /* Insert a memory fence. It's sometimes important that these |
| 6328 | are carried through to the generated code. */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 6329 | stmt( IRStmt_MBE(Imbe_Fence) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6330 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6331 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6332 | /* 64bit Memsync */ |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 6333 | case 0x054: { // ldarx (Load DWord and Reserve Indexed, PPC64 p473) |
| 6334 | IRTemp res; |
sewardj | fe397a2 | 2008-08-06 19:13:42 +0000 | [diff] [blame] | 6335 | /* According to the PowerPC ISA version 2.05, b0 (called EH |
| 6336 | in the documentation) is merely a hint bit to the |
| 6337 | hardware, I think as to whether or not contention is |
| 6338 | likely. So we can just ignore it. */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6339 | if (!mode64) |
| 6340 | return False; |
sewardj | fe397a2 | 2008-08-06 19:13:42 +0000 | [diff] [blame] | 6341 | DIP("ldarx r%u,r%u,r%u,EH=%u\n", rD_addr, rA_addr, rB_addr, (UInt)b0); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6342 | |
| 6343 | // trap if misaligned |
| 6344 | gen_SIGBUS_if_misaligned( EA, 8 ); |
| 6345 | |
| 6346 | // and actually do the load |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 6347 | res = newTemp(Ity_I64); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6348 | stmt( stmt_load( res, mkexpr(EA), NULL/*this is a load*/) ); |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 6349 | |
| 6350 | putIReg( rD_addr, mkexpr(res) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6351 | break; |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 6352 | } |
| 6353 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6354 | case 0x0D6: { // stdcx. (Store DWord Condition Indexd, PPC64 p581) |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6355 | // A marginally simplified version of the stwcx. case |
| 6356 | IRTemp rS = newTemp(Ity_I64); |
| 6357 | IRTemp resSC; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6358 | if (b0 != 1) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6359 | vex_printf("dis_memsync(ppc)(stdcx.,b0)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6360 | return False; |
| 6361 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6362 | if (!mode64) |
| 6363 | return False; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6364 | DIP("stdcx. r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6365 | |
| 6366 | // trap if misaligned |
| 6367 | gen_SIGBUS_if_misaligned( EA, 8 ); |
| 6368 | |
| 6369 | // Get the data to be stored |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6370 | assign( rS, getIReg(rS_addr) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6371 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6372 | // Do the store, and get success/failure bit into resSC |
| 6373 | resSC = newTemp(Ity_I1); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6374 | stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6375 | |
| 6376 | // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure |
| 6377 | // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success |
| 6378 | putCR321(0, binop(Iop_Shl8, unop(Iop_1Uto8, mkexpr(resSC)), mkU8(1))); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6379 | putCR0(0, getXER_SO()); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6380 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6381 | /* Note: |
| 6382 | If resaddr != lwarx_resaddr, CR0[EQ] is undefined, and |
| 6383 | whether rS is stored is dependent on that value. */ |
| 6384 | /* So I guess we can just ignore this case? */ |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6385 | break; |
| 6386 | } |
| 6387 | |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 6388 | /* 128bit Memsync */ |
| 6389 | case 0x114: { // lqarx (Load QuadWord and Reserve Indexed) |
| 6390 | IRTemp res_hi = newTemp(ty); |
| 6391 | IRTemp res_lo = newTemp(ty); |
| 6392 | |
| 6393 | /* According to the PowerPC ISA version 2.07, b0 (called EH |
| 6394 | in the documentation) is merely a hint bit to the |
| 6395 | hardware, I think as to whether or not contention is |
| 6396 | likely. So we can just ignore it. */ |
| 6397 | DIP("lqarx r%u,r%u,r%u,EH=%u\n", rD_addr, rA_addr, rB_addr, (UInt)b0); |
| 6398 | |
| 6399 | // trap if misaligned |
| 6400 | gen_SIGBUS_if_misaligned( EA, 16 ); |
| 6401 | |
| 6402 | // and actually do the load |
| 6403 | if (mode64) { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6404 | stmt( stmt_load( res_hi, |
| 6405 | mkexpr(EA), NULL/*this is a load*/) ); |
| 6406 | stmt( stmt_load( res_lo, |
| 6407 | binop(Iop_Add64, mkexpr(EA), mkU64(8) ), |
| 6408 | NULL/*this is a load*/) ); |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 6409 | } else { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6410 | stmt( stmt_load( res_hi, |
| 6411 | binop( Iop_Add32, mkexpr(EA), mkU32(4) ), |
| 6412 | NULL/*this is a load*/) ); |
| 6413 | stmt( stmt_load( res_lo, |
| 6414 | binop( Iop_Add32, mkexpr(EA), mkU32(12) ), |
| 6415 | NULL/*this is a load*/) ); |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 6416 | } |
| 6417 | putIReg( rD_addr, mkexpr(res_hi) ); |
| 6418 | putIReg( rD_addr+1, mkexpr(res_lo) ); |
| 6419 | break; |
| 6420 | } |
| 6421 | |
| 6422 | case 0x0B6: { // stqcx. (Store QuadWord Condition Indexd, PPC64) |
| 6423 | // A marginally simplified version of the stwcx. case |
| 6424 | IRTemp rS_hi = newTemp(ty); |
| 6425 | IRTemp rS_lo = newTemp(ty); |
| 6426 | IRTemp resSC; |
| 6427 | if (b0 != 1) { |
| 6428 | vex_printf("dis_memsync(ppc)(stqcx.,b0)\n"); |
| 6429 | return False; |
| 6430 | } |
| 6431 | |
| 6432 | DIP("stqcx. r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
| 6433 | |
| 6434 | // trap if misaligned |
| 6435 | gen_SIGBUS_if_misaligned( EA, 16 ); |
| 6436 | // Get the data to be stored |
| 6437 | assign( rS_hi, getIReg(rS_addr) ); |
| 6438 | assign( rS_lo, getIReg(rS_addr+1) ); |
| 6439 | |
| 6440 | // Do the store, and get success/failure bit into resSC |
| 6441 | resSC = newTemp(Ity_I1); |
| 6442 | |
| 6443 | if (mode64) { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6444 | stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS_hi) ) ); |
| 6445 | store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) ); |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 6446 | } else { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6447 | stmt( stmt_load( resSC, binop( Iop_Add32, |
| 6448 | mkexpr(EA), |
| 6449 | mkU32(4) ), |
| 6450 | mkexpr(rS_hi) ) ); |
| 6451 | store( binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) ); |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 6452 | } |
| 6453 | |
| 6454 | // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure |
| 6455 | // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success |
| 6456 | putCR321(0, binop( Iop_Shl8, |
| 6457 | unop(Iop_1Uto8, mkexpr(resSC) ), |
| 6458 | mkU8(1))); |
| 6459 | putCR0(0, getXER_SO()); |
| 6460 | break; |
| 6461 | } |
| 6462 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6463 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6464 | vex_printf("dis_memsync(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6465 | return False; |
| 6466 | } |
| 6467 | break; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 6468 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6469 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6470 | vex_printf("dis_memsync(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6471 | return False; |
| 6472 | } |
| 6473 | return True; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 6474 | } |
| 6475 | |
| 6476 | |
| 6477 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6478 | /* |
| 6479 | Integer Shift Instructions |
| 6480 | */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 6481 | static Bool dis_int_shift ( UInt theInstr ) |
| 6482 | { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6483 | /* X-Form, XS-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6484 | UChar opc1 = ifieldOPC(theInstr); |
| 6485 | UChar rS_addr = ifieldRegDS(theInstr); |
| 6486 | UChar rA_addr = ifieldRegA(theInstr); |
| 6487 | UChar rB_addr = ifieldRegB(theInstr); |
| 6488 | UChar sh_imm = rB_addr; |
| 6489 | UInt opc2 = ifieldOPClo10(theInstr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6490 | UChar b1 = ifieldBIT1(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6491 | UChar flag_rC = ifieldBIT0(theInstr); |
| 6492 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6493 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 6494 | IRTemp rA = newTemp(ty); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6495 | IRTemp rS = newTemp(ty); |
| 6496 | IRTemp rB = newTemp(ty); |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6497 | IRTemp outofrange = newTemp(Ity_I1); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6498 | IRTemp rS_lo32 = newTemp(Ity_I32); |
| 6499 | IRTemp rB_lo32 = newTemp(Ity_I32); |
| 6500 | IRExpr* e_tmp; |
| 6501 | |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6502 | assign( rS, getIReg(rS_addr) ); |
| 6503 | assign( rB, getIReg(rB_addr) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6504 | assign( rS_lo32, mkNarrowTo32(ty, mkexpr(rS)) ); |
| 6505 | assign( rB_lo32, mkNarrowTo32(ty, mkexpr(rB)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6506 | |
| 6507 | if (opc1 == 0x1F) { |
| 6508 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6509 | case 0x018: { // slw (Shift Left Word, PPC32 p505) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6510 | DIP("slw%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6511 | rA_addr, rS_addr, rB_addr); |
| 6512 | /* rA = rS << rB */ |
| 6513 | /* ppc32 semantics are: |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 6514 | slw(x,y) = (x << (y & 31)) -- primary result |
| 6515 | & ~((y << 26) >>s 31) -- make result 0 |
| 6516 | for y in 32 .. 63 |
| 6517 | */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6518 | e_tmp = |
| 6519 | binop( Iop_And32, |
| 6520 | binop( Iop_Shl32, |
| 6521 | mkexpr(rS_lo32), |
| 6522 | unop( Iop_32to8, |
| 6523 | binop(Iop_And32, |
| 6524 | mkexpr(rB_lo32), mkU32(31)))), |
| 6525 | unop( Iop_Not32, |
| 6526 | binop( Iop_Sar32, |
| 6527 | binop(Iop_Shl32, mkexpr(rB_lo32), mkU8(26)), |
| 6528 | mkU8(31))) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6529 | assign( rA, mkWidenFrom32(ty, e_tmp, /* Signed */False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6530 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6531 | } |
| 6532 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6533 | case 0x318: { // sraw (Shift Right Alg Word, PPC32 p506) |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6534 | IRTemp sh_amt = newTemp(Ity_I32); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6535 | DIP("sraw%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6536 | rA_addr, rS_addr, rB_addr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6537 | /* JRS: my reading of the (poorly worded) PPC32 doc p506 is: |
| 6538 | amt = rB & 63 |
| 6539 | rA = Sar32( rS, amt > 31 ? 31 : amt ) |
| 6540 | XER.CA = amt > 31 ? sign-of-rS : (computation as per srawi) |
| 6541 | */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6542 | assign( sh_amt, binop(Iop_And32, mkU32(0x3F), |
| 6543 | mkexpr(rB_lo32)) ); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6544 | assign( outofrange, |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6545 | binop(Iop_CmpLT32U, mkU32(31), mkexpr(sh_amt)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6546 | e_tmp = binop( Iop_Sar32, |
| 6547 | mkexpr(rS_lo32), |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 6548 | unop( Iop_32to8, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6549 | IRExpr_ITE( mkexpr(outofrange), |
| 6550 | mkU32(31), |
| 6551 | mkexpr(sh_amt)) ) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6552 | assign( rA, mkWidenFrom32(ty, e_tmp, /* Signed */True) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 6553 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6554 | set_XER_CA( ty, PPCG_FLAG_OP_SRAW, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6555 | mkexpr(rA), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6556 | mkWidenFrom32(ty, mkexpr(rS_lo32), True), |
| 6557 | mkWidenFrom32(ty, mkexpr(sh_amt), True ), |
| 6558 | mkWidenFrom32(ty, getXER_CA32(), True) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6559 | break; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6560 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6561 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6562 | case 0x338: // srawi (Shift Right Alg Word Immediate, PPC32 p507) |
| 6563 | DIP("srawi%s r%u,r%u,%d\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6564 | rA_addr, rS_addr, sh_imm); |
| 6565 | vassert(sh_imm < 32); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6566 | if (mode64) { |
| 6567 | assign( rA, binop(Iop_Sar64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6568 | binop(Iop_Shl64, getIReg(rS_addr), |
| 6569 | mkU8(32)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6570 | mkU8(32 + sh_imm)) ); |
| 6571 | } else { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6572 | assign( rA, binop(Iop_Sar32, mkexpr(rS_lo32), |
| 6573 | mkU8(sh_imm)) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6574 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 6575 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6576 | set_XER_CA( ty, PPCG_FLAG_OP_SRAWI, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6577 | mkexpr(rA), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6578 | mkWidenFrom32(ty, mkexpr(rS_lo32), /* Syned */True), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6579 | mkSzImm(ty, sh_imm), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6580 | mkWidenFrom32(ty, getXER_CA32(), /* Syned */False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6581 | break; |
| 6582 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 6583 | case 0x218: // srw (Shift Right Word, PPC32 p508) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6584 | DIP("srw%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6585 | rA_addr, rS_addr, rB_addr); |
| 6586 | /* rA = rS >>u rB */ |
| 6587 | /* ppc32 semantics are: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6588 | srw(x,y) = (x >>u (y & 31)) -- primary result |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 6589 | & ~((y << 26) >>s 31) -- make result 0 |
| 6590 | for y in 32 .. 63 |
| 6591 | */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6592 | e_tmp = |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 6593 | binop( |
| 6594 | Iop_And32, |
| 6595 | binop( Iop_Shr32, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6596 | mkexpr(rS_lo32), |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 6597 | unop( Iop_32to8, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6598 | binop(Iop_And32, mkexpr(rB_lo32), |
| 6599 | mkU32(31)))), |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 6600 | unop( Iop_Not32, |
| 6601 | binop( Iop_Sar32, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6602 | binop(Iop_Shl32, mkexpr(rB_lo32), |
| 6603 | mkU8(26)), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6604 | mkU8(31)))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6605 | assign( rA, mkWidenFrom32(ty, e_tmp, /* Signed */False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6606 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6607 | |
| 6608 | |
| 6609 | /* 64bit Shifts */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6610 | case 0x01B: // sld (Shift Left DWord, PPC64 p568) |
| 6611 | DIP("sld%s r%u,r%u,r%u\n", |
| 6612 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6613 | /* rA = rS << rB */ |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6614 | /* ppc64 semantics are: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6615 | slw(x,y) = (x << (y & 63)) -- primary result |
| 6616 | & ~((y << 57) >>s 63) -- make result 0 |
| 6617 | for y in 64 .. |
| 6618 | */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6619 | assign( rA, |
| 6620 | binop( |
| 6621 | Iop_And64, |
| 6622 | binop( Iop_Shl64, |
| 6623 | mkexpr(rS), |
| 6624 | unop( Iop_64to8, |
| 6625 | binop(Iop_And64, mkexpr(rB), mkU64(63)))), |
| 6626 | unop( Iop_Not64, |
| 6627 | binop( Iop_Sar64, |
| 6628 | binop(Iop_Shl64, mkexpr(rB), mkU8(57)), |
| 6629 | mkU8(63)))) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6630 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6631 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6632 | case 0x31A: { // srad (Shift Right Alg DWord, PPC64 p570) |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6633 | IRTemp sh_amt = newTemp(Ity_I64); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6634 | DIP("srad%s r%u,r%u,r%u\n", |
| 6635 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6636 | /* amt = rB & 127 |
| 6637 | rA = Sar64( rS, amt > 63 ? 63 : amt ) |
| 6638 | XER.CA = amt > 63 ? sign-of-rS : (computation as per srawi) |
| 6639 | */ |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6640 | assign( sh_amt, binop(Iop_And64, mkU64(0x7F), mkexpr(rB)) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6641 | assign( outofrange, |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6642 | binop(Iop_CmpLT64U, mkU64(63), mkexpr(sh_amt)) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6643 | assign( rA, |
| 6644 | binop( Iop_Sar64, |
| 6645 | mkexpr(rS), |
| 6646 | unop( Iop_64to8, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6647 | IRExpr_ITE( mkexpr(outofrange), |
| 6648 | mkU64(63), |
| 6649 | mkexpr(sh_amt)) )) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6650 | ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6651 | set_XER_CA( ty, PPCG_FLAG_OP_SRAD, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6652 | mkexpr(rA), mkexpr(rS), mkexpr(sh_amt), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6653 | mkWidenFrom32(ty, getXER_CA32(), /* Syned */False) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6654 | break; |
| 6655 | } |
| 6656 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6657 | case 0x33A: case 0x33B: // sradi (Shr Alg DWord Imm, PPC64 p571) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6658 | sh_imm |= b1<<5; |
| 6659 | vassert(sh_imm < 64); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6660 | DIP("sradi%s r%u,r%u,%u\n", |
| 6661 | flag_rC ? ".":"", rA_addr, rS_addr, sh_imm); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6662 | assign( rA, binop(Iop_Sar64, getIReg(rS_addr), mkU8(sh_imm)) ); |
| 6663 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6664 | set_XER_CA( ty, PPCG_FLAG_OP_SRADI, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6665 | mkexpr(rA), |
| 6666 | getIReg(rS_addr), |
| 6667 | mkU64(sh_imm), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6668 | mkWidenFrom32(ty, getXER_CA32(), /* Syned */False) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6669 | break; |
| 6670 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6671 | case 0x21B: // srd (Shift Right DWord, PPC64 p574) |
| 6672 | DIP("srd%s r%u,r%u,r%u\n", |
| 6673 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6674 | /* rA = rS >>u rB */ |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6675 | /* ppc semantics are: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6676 | srw(x,y) = (x >>u (y & 63)) -- primary result |
| 6677 | & ~((y << 57) >>s 63) -- make result 0 |
| 6678 | for y in 64 .. 127 |
| 6679 | */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6680 | assign( rA, |
| 6681 | binop( |
| 6682 | Iop_And64, |
| 6683 | binop( Iop_Shr64, |
| 6684 | mkexpr(rS), |
| 6685 | unop( Iop_64to8, |
| 6686 | binop(Iop_And64, mkexpr(rB), mkU64(63)))), |
| 6687 | unop( Iop_Not64, |
| 6688 | binop( Iop_Sar64, |
| 6689 | binop(Iop_Shl64, mkexpr(rB), mkU8(57)), |
| 6690 | mkU8(63)))) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6691 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6692 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6693 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6694 | vex_printf("dis_int_shift(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6695 | return False; |
| 6696 | } |
| 6697 | } else { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6698 | vex_printf("dis_int_shift(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6699 | return False; |
| 6700 | } |
cerion | 0d330c5 | 2005-02-28 16:43:16 +0000 | [diff] [blame] | 6701 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6702 | putIReg( rA_addr, mkexpr(rA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6703 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6704 | if (flag_rC) { |
| 6705 | set_CR0( mkexpr(rA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6706 | } |
| 6707 | return True; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 6708 | } |
| 6709 | |
| 6710 | |
| 6711 | |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 6712 | /* |
| 6713 | Integer Load/Store Reverse Instructions |
| 6714 | */ |
sewardj | 40d8c09 | 2006-05-05 13:26:14 +0000 | [diff] [blame] | 6715 | /* Generates code to swap the byte order in an Ity_I32. */ |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 6716 | static IRExpr* /* :: Ity_I32 */ gen_byterev32 ( IRTemp t ) |
| 6717 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 6718 | vassert(typeOfIRTemp(irsb->tyenv, t) == Ity_I32); |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 6719 | return |
| 6720 | binop(Iop_Or32, |
| 6721 | binop(Iop_Shl32, mkexpr(t), mkU8(24)), |
| 6722 | binop(Iop_Or32, |
| 6723 | binop(Iop_And32, binop(Iop_Shl32, mkexpr(t), mkU8(8)), |
| 6724 | mkU32(0x00FF0000)), |
| 6725 | binop(Iop_Or32, |
| 6726 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(8)), |
| 6727 | mkU32(0x0000FF00)), |
| 6728 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(24)), |
| 6729 | mkU32(0x000000FF) ) |
| 6730 | ))); |
| 6731 | } |
| 6732 | |
sewardj | 40d8c09 | 2006-05-05 13:26:14 +0000 | [diff] [blame] | 6733 | /* Generates code to swap the byte order in the lower half of an Ity_I32, |
| 6734 | and zeroes the upper half. */ |
| 6735 | static IRExpr* /* :: Ity_I32 */ gen_byterev16 ( IRTemp t ) |
| 6736 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 6737 | vassert(typeOfIRTemp(irsb->tyenv, t) == Ity_I32); |
sewardj | 40d8c09 | 2006-05-05 13:26:14 +0000 | [diff] [blame] | 6738 | return |
| 6739 | binop(Iop_Or32, |
| 6740 | binop(Iop_And32, binop(Iop_Shl32, mkexpr(t), mkU8(8)), |
| 6741 | mkU32(0x0000FF00)), |
| 6742 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(8)), |
| 6743 | mkU32(0x000000FF)) |
| 6744 | ); |
| 6745 | } |
| 6746 | |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 6747 | static Bool dis_int_ldst_rev ( UInt theInstr ) |
| 6748 | { |
| 6749 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6750 | UChar opc1 = ifieldOPC(theInstr); |
| 6751 | UChar rD_addr = ifieldRegDS(theInstr); |
| 6752 | UChar rS_addr = rD_addr; |
| 6753 | UChar rA_addr = ifieldRegA(theInstr); |
| 6754 | UChar rB_addr = ifieldRegB(theInstr); |
| 6755 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6756 | UChar b0 = ifieldBIT0(theInstr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6757 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6758 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 6759 | IRTemp EA = newTemp(ty); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6760 | IRTemp w1 = newTemp(Ity_I32); |
| 6761 | IRTemp w2 = newTemp(Ity_I32); |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 6762 | |
| 6763 | if (opc1 != 0x1F || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6764 | vex_printf("dis_int_ldst_rev(ppc)(opc1|b0)\n"); |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 6765 | return False; |
| 6766 | } |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 6767 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6768 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 6769 | |
| 6770 | switch (opc2) { |
sewardj | 40d8c09 | 2006-05-05 13:26:14 +0000 | [diff] [blame] | 6771 | |
| 6772 | case 0x316: // lhbrx (Load Halfword Byte-Reverse Indexed, PPC32 p449) |
| 6773 | DIP("lhbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6774 | assign( w1, unop(Iop_16Uto32, load(Ity_I16, mkexpr(EA))) ); |
sewardj | 40d8c09 | 2006-05-05 13:26:14 +0000 | [diff] [blame] | 6775 | assign( w2, gen_byterev16(w1) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6776 | putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2), |
| 6777 | /* Signed */False) ); |
sewardj | 40d8c09 | 2006-05-05 13:26:14 +0000 | [diff] [blame] | 6778 | break; |
| 6779 | |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 6780 | case 0x216: // lwbrx (Load Word Byte-Reverse Indexed, PPC32 p459) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6781 | DIP("lwbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6782 | assign( w1, load(Ity_I32, mkexpr(EA)) ); |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 6783 | assign( w2, gen_byterev32(w1) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6784 | putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2), |
| 6785 | /* Signed */False) ); |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 6786 | break; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 6787 | |
| 6788 | case 0x214: // ldbrx (Load Doubleword Byte-Reverse Indexed) |
| 6789 | { |
| 6790 | IRExpr * nextAddr; |
| 6791 | IRTemp w3 = newTemp( Ity_I32 ); |
| 6792 | IRTemp w4 = newTemp( Ity_I32 ); |
| 6793 | DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6794 | assign( w1, load( Ity_I32, mkexpr( EA ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 6795 | assign( w2, gen_byterev32( w1 ) ); |
| 6796 | nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), |
| 6797 | ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6798 | assign( w3, load( Ity_I32, nextAddr ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 6799 | assign( w4, gen_byterev32( w3 ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6800 | if (host_endness == VexEndnessLE) |
| 6801 | putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w2 ), mkexpr( w4 ) ) ); |
| 6802 | else |
| 6803 | putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 6804 | break; |
| 6805 | } |
| 6806 | |
sewardj | 413a468 | 2006-05-05 13:44:17 +0000 | [diff] [blame] | 6807 | case 0x396: // sthbrx (Store Half Word Byte-Reverse Indexed, PPC32 p523) |
| 6808 | DIP("sthbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6809 | assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6810 | store( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) ); |
sewardj | 413a468 | 2006-05-05 13:44:17 +0000 | [diff] [blame] | 6811 | break; |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 6812 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6813 | case 0x296: // stwbrx (Store Word Byte-Reverse Indxd, PPC32 p531) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6814 | DIP("stwbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6815 | assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6816 | store( mkexpr(EA), gen_byterev32(w1) ); |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 6817 | break; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 6818 | |
| 6819 | case 0x294: // stdbrx (Store Doubleword Byte-Reverse Indexed) |
| 6820 | { |
| 6821 | IRTemp lo = newTemp(Ity_I32); |
| 6822 | IRTemp hi = newTemp(Ity_I32); |
| 6823 | IRTemp rS = newTemp(Ity_I64); |
| 6824 | assign( rS, getIReg( rS_addr ) ); |
| 6825 | DIP("stdbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
| 6826 | assign(lo, unop(Iop_64HIto32, mkexpr(rS))); |
| 6827 | assign(hi, unop(Iop_64to32, mkexpr(rS))); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 6828 | store( mkexpr( EA ), |
| 6829 | binop( Iop_32HLto64, gen_byterev32( hi ), |
| 6830 | gen_byterev32( lo ) ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 6831 | break; |
| 6832 | } |
| 6833 | |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 6834 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6835 | vex_printf("dis_int_ldst_rev(ppc)(opc2)\n"); |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 6836 | return False; |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 6837 | } |
| 6838 | return True; |
| 6839 | } |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 6840 | |
| 6841 | |
| 6842 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6843 | /* |
| 6844 | Processor Control Instructions |
| 6845 | */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 6846 | static Bool dis_proc_ctl ( VexAbiInfo* vbi, UInt theInstr ) |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 6847 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6848 | UChar opc1 = ifieldOPC(theInstr); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6849 | |
| 6850 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6851 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 6852 | UChar b21to22 = toUChar( IFIELD( theInstr, 21, 2 ) ); |
| 6853 | UChar rD_addr = ifieldRegDS(theInstr); |
| 6854 | UInt b11to20 = IFIELD( theInstr, 11, 10 ); |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 6855 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6856 | /* XFX-Form */ |
| 6857 | UChar rS_addr = rD_addr; |
| 6858 | UInt SPR = b11to20; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6859 | UInt TBR = b11to20; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6860 | UChar b20 = toUChar( IFIELD( theInstr, 20, 1 ) ); |
| 6861 | UInt CRM = IFIELD( theInstr, 12, 8 ); |
| 6862 | UChar b11 = toUChar( IFIELD( theInstr, 11, 1 ) ); |
| 6863 | |
| 6864 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6865 | UChar b0 = ifieldBIT0(theInstr); |
| 6866 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 6867 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6868 | IRTemp rS = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6869 | assign( rS, getIReg(rS_addr) ); |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 6870 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6871 | /* Reorder SPR field as per PPC32 p470 */ |
| 6872 | SPR = ((SPR & 0x1F) << 5) | ((SPR >> 5) & 0x1F); |
sewardj | 73a9197 | 2005-09-06 10:25:46 +0000 | [diff] [blame] | 6873 | /* Reorder TBR field as per PPC32 p475 */ |
| 6874 | TBR = ((TBR & 31) << 5) | ((TBR >> 5) & 31); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6875 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 6876 | /* b0 = 0, inst is treated as floating point inst for reservation purposes |
| 6877 | * b0 = 1, inst is treated as vector inst for reservation purposes |
| 6878 | */ |
| 6879 | if (opc1 != 0x1F) { |
| 6880 | vex_printf("dis_proc_ctl(ppc)(opc1|b%d)\n", b0); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6881 | return False; |
| 6882 | } |
| 6883 | |
| 6884 | switch (opc2) { |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 6885 | /* X-Form */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6886 | case 0x200: { // mcrxr (Move to Cond Register from XER, PPC32 p466) |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 6887 | if (b21to22 != 0 || b11to20 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6888 | vex_printf("dis_proc_ctl(ppc)(mcrxr,b21to22|b11to20)\n"); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 6889 | return False; |
| 6890 | } |
| 6891 | DIP("mcrxr crf%d\n", crfD); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6892 | /* Move XER[0-3] (the top 4 bits of XER) to CR[crfD] */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6893 | putGST_field( PPC_GST_CR, |
| 6894 | getGST_field( PPC_GST_XER, 7 ), |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6895 | crfD ); |
sewardj | 55ccc3e | 2005-09-09 19:45:02 +0000 | [diff] [blame] | 6896 | |
| 6897 | // Clear XER[0-3] |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6898 | putXER_SO( mkU8(0) ); |
| 6899 | putXER_OV( mkU8(0) ); |
| 6900 | putXER_CA( mkU8(0) ); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 6901 | break; |
sewardj | 55ccc3e | 2005-09-09 19:45:02 +0000 | [diff] [blame] | 6902 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6903 | |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 6904 | case 0x013: |
| 6905 | // b11to20==0: mfcr (Move from Cond Register, PPC32 p467) |
| 6906 | // b20==1 & b11==0: mfocrf (Move from One CR Field) |
| 6907 | // However it seems that the 'mfcr' behaviour is an acceptable |
| 6908 | // implementation of mfocr (from the 2.02 arch spec) |
| 6909 | if (b11to20 == 0) { |
| 6910 | DIP("mfcr r%u\n", rD_addr); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6911 | putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_CR ), |
| 6912 | /* Signed */False) ); |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 6913 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6914 | } |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 6915 | if (b20 == 1 && b11 == 0) { |
| 6916 | DIP("mfocrf r%u,%u\n", rD_addr, CRM); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6917 | putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_CR ), |
| 6918 | /* Signed */False) ); |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 6919 | break; |
| 6920 | } |
| 6921 | /* not decodable */ |
| 6922 | return False; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 6923 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6924 | /* XFX-Form */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 6925 | case 0x153: // mfspr (Move from Special-Purpose Register, PPC32 p470) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 6926 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6927 | switch (SPR) { // Choose a register... |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6928 | case 0x1: |
| 6929 | DIP("mfxer r%u\n", rD_addr); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6930 | putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_XER ), |
| 6931 | /* Signed */False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6932 | break; |
| 6933 | case 0x8: |
| 6934 | DIP("mflr r%u\n", rD_addr); |
| 6935 | putIReg( rD_addr, getGST( PPC_GST_LR ) ); |
| 6936 | break; |
| 6937 | case 0x9: |
| 6938 | DIP("mfctr r%u\n", rD_addr); |
| 6939 | putIReg( rD_addr, getGST( PPC_GST_CTR ) ); |
| 6940 | break; |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 6941 | case 0x80: // 128 |
| 6942 | DIP("mfspr r%u (TFHAR)\n", rD_addr); |
| 6943 | putIReg( rD_addr, getGST( PPC_GST_TFHAR) ); |
| 6944 | break; |
| 6945 | case 0x81: // 129 |
| 6946 | DIP("mfspr r%u (TFIAR)\n", rD_addr); |
| 6947 | putIReg( rD_addr, getGST( PPC_GST_TFIAR) ); |
| 6948 | break; |
| 6949 | case 0x82: // 130 |
| 6950 | DIP("mfspr r%u (TEXASR)\n", rD_addr); |
| 6951 | putIReg( rD_addr, getGST( PPC_GST_TEXASR) ); |
| 6952 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6953 | case 0x100: |
| 6954 | DIP("mfvrsave r%u\n", rD_addr); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6955 | putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_VRSAVE ), |
| 6956 | /* Signed */False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6957 | break; |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 6958 | |
| 6959 | case 0x103: |
| 6960 | DIP("mfspr r%u, SPRG3(readonly)\n", rD_addr); |
| 6961 | putIReg( rD_addr, getGST( PPC_GST_SPRG3_RO ) ); |
| 6962 | break; |
| 6963 | |
sewardj | abb321c | 2006-12-27 18:39:46 +0000 | [diff] [blame] | 6964 | /* Even a lowly PPC7400 can run the associated helper, so no |
| 6965 | obvious need for feature testing at this point. */ |
| 6966 | case 268 /* 0x10C */: |
| 6967 | case 269 /* 0x10D */: { |
| 6968 | UInt arg = SPR==268 ? 0 : 1; |
| 6969 | IRTemp val = newTemp(Ity_I32); |
| 6970 | IRExpr** args = mkIRExprVec_1( mkU32(arg) ); |
| 6971 | IRDirty* d = unsafeIRDirty_1_N( |
| 6972 | val, |
| 6973 | 0/*regparms*/, |
| 6974 | "ppc32g_dirtyhelper_MFSPR_268_269", |
| 6975 | fnptr_to_fnentry |
| 6976 | (vbi, &ppc32g_dirtyhelper_MFSPR_268_269), |
| 6977 | args |
| 6978 | ); |
| 6979 | /* execute the dirty call, dumping the result in val. */ |
| 6980 | stmt( IRStmt_Dirty(d) ); |
sewardj | 37b2ee8 | 2009-08-02 14:35:45 +0000 | [diff] [blame] | 6981 | putIReg( rD_addr, |
| 6982 | mkWidenFrom32(ty, mkexpr(val), False/*unsigned*/) ); |
| 6983 | DIP("mfspr r%u,%u", rD_addr, (UInt)SPR); |
| 6984 | break; |
| 6985 | } |
| 6986 | |
| 6987 | /* Again, runs natively on PPC7400 (7447, really). Not |
| 6988 | bothering with a feature test. */ |
| 6989 | case 287: /* 0x11F */ { |
| 6990 | IRTemp val = newTemp(Ity_I32); |
| 6991 | IRExpr** args = mkIRExprVec_0(); |
| 6992 | IRDirty* d = unsafeIRDirty_1_N( |
| 6993 | val, |
| 6994 | 0/*regparms*/, |
| 6995 | "ppc32g_dirtyhelper_MFSPR_287", |
| 6996 | fnptr_to_fnentry |
| 6997 | (vbi, &ppc32g_dirtyhelper_MFSPR_287), |
| 6998 | args |
| 6999 | ); |
| 7000 | /* execute the dirty call, dumping the result in val. */ |
| 7001 | stmt( IRStmt_Dirty(d) ); |
| 7002 | putIReg( rD_addr, |
| 7003 | mkWidenFrom32(ty, mkexpr(val), False/*unsigned*/) ); |
sewardj | abb321c | 2006-12-27 18:39:46 +0000 | [diff] [blame] | 7004 | DIP("mfspr r%u,%u", rD_addr, (UInt)SPR); |
| 7005 | break; |
| 7006 | } |
| 7007 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7008 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7009 | vex_printf("dis_proc_ctl(ppc)(mfspr,SPR)(0x%x)\n", SPR); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7010 | return False; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7011 | } |
| 7012 | break; |
| 7013 | |
sewardj | 73a9197 | 2005-09-06 10:25:46 +0000 | [diff] [blame] | 7014 | case 0x173: { // mftb (Move from Time Base, PPC32 p475) |
| 7015 | IRTemp val = newTemp(Ity_I64); |
| 7016 | IRExpr** args = mkIRExprVec_0(); |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 7017 | IRDirty* d = unsafeIRDirty_1_N( |
| 7018 | val, |
| 7019 | 0/*regparms*/, |
| 7020 | "ppcg_dirtyhelper_MFTB", |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 7021 | fnptr_to_fnentry(vbi, &ppcg_dirtyhelper_MFTB), |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 7022 | args ); |
sewardj | 73a9197 | 2005-09-06 10:25:46 +0000 | [diff] [blame] | 7023 | /* execute the dirty call, dumping the result in val. */ |
| 7024 | stmt( IRStmt_Dirty(d) ); |
| 7025 | |
| 7026 | switch (TBR) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7027 | case 269: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7028 | DIP("mftbu r%u", rD_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7029 | putIReg( rD_addr, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7030 | mkWidenFrom32(ty, unop(Iop_64HIto32, mkexpr(val)), |
| 7031 | /* Signed */False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7032 | break; |
| 7033 | case 268: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7034 | DIP("mftb r%u", rD_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7035 | putIReg( rD_addr, (mode64) ? mkexpr(val) : |
| 7036 | unop(Iop_64to32, mkexpr(val)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7037 | break; |
| 7038 | default: |
| 7039 | return False; /* illegal instruction */ |
sewardj | 73a9197 | 2005-09-06 10:25:46 +0000 | [diff] [blame] | 7040 | } |
| 7041 | break; |
| 7042 | } |
| 7043 | |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 7044 | case 0x090: { |
| 7045 | // b20==0: mtcrf (Move to Cond Register Fields, PPC32 p477) |
| 7046 | // b20==1: mtocrf (Move to One Cond Reg Field) |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 7047 | Int cr; |
| 7048 | UChar shft; |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 7049 | if (b11 != 0) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7050 | return False; |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 7051 | if (b20 == 1) { |
| 7052 | /* ppc64 v2.02 spec says mtocrf gives undefined outcome if > |
| 7053 | 1 field is written. It seems more robust to decline to |
| 7054 | decode the insn if so. */ |
| 7055 | switch (CRM) { |
| 7056 | case 0x01: case 0x02: case 0x04: case 0x08: |
| 7057 | case 0x10: case 0x20: case 0x40: case 0x80: |
| 7058 | break; |
| 7059 | default: |
| 7060 | return False; |
| 7061 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7062 | } |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 7063 | DIP("%s 0x%x,r%u\n", b20==1 ? "mtocrf" : "mtcrf", |
| 7064 | CRM, rS_addr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 7065 | /* Write to each field specified by CRM */ |
| 7066 | for (cr = 0; cr < 8; cr++) { |
| 7067 | if ((CRM & (1 << (7-cr))) == 0) |
| 7068 | continue; |
| 7069 | shft = 4*(7-cr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7070 | putGST_field( PPC_GST_CR, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7071 | binop(Iop_Shr32, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7072 | mkNarrowTo32(ty, mkexpr(rS)), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7073 | mkU8(shft)), cr ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 7074 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7075 | break; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 7076 | } |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 7077 | |
| 7078 | case 0x1D3: // mtspr (Move to Special-Purpose Register, PPC32 p483) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7079 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7080 | switch (SPR) { // Choose a register... |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7081 | case 0x1: |
| 7082 | DIP("mtxer r%u\n", rS_addr); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7083 | putGST( PPC_GST_XER, mkNarrowTo32(ty, mkexpr(rS)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7084 | break; |
| 7085 | case 0x8: |
| 7086 | DIP("mtlr r%u\n", rS_addr); |
| 7087 | putGST( PPC_GST_LR, mkexpr(rS) ); |
| 7088 | break; |
| 7089 | case 0x9: |
| 7090 | DIP("mtctr r%u\n", rS_addr); |
| 7091 | putGST( PPC_GST_CTR, mkexpr(rS) ); |
| 7092 | break; |
| 7093 | case 0x100: |
| 7094 | DIP("mtvrsave r%u\n", rS_addr); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7095 | putGST( PPC_GST_VRSAVE, mkNarrowTo32(ty, mkexpr(rS)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7096 | break; |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 7097 | case 0x80: // 128 |
| 7098 | DIP("mtspr r%u (TFHAR)\n", rS_addr); |
| 7099 | putGST( PPC_GST_TFHAR, mkexpr(rS) ); |
| 7100 | break; |
| 7101 | case 0x81: // 129 |
| 7102 | DIP("mtspr r%u (TFIAR)\n", rS_addr); |
| 7103 | putGST( PPC_GST_TFIAR, mkexpr(rS) ); |
| 7104 | break; |
| 7105 | case 0x82: // 130 |
| 7106 | DIP("mtspr r%u (TEXASR)\n", rS_addr); |
| 7107 | putGST( PPC_GST_TEXASR, mkexpr(rS) ); |
| 7108 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7109 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7110 | vex_printf("dis_proc_ctl(ppc)(mtspr,SPR)(%u)\n", SPR); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7111 | return False; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7112 | } |
| 7113 | break; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 7114 | |
| 7115 | case 0x33: // mfvsrd |
| 7116 | { |
| 7117 | UChar XS = ifieldRegXS( theInstr ); |
| 7118 | UChar rA_addr = ifieldRegA(theInstr); |
| 7119 | IRExpr * high64; |
| 7120 | IRTemp vS = newTemp( Ity_V128 ); |
| 7121 | DIP("mfvsrd r%u,vsr%d\n", rA_addr, (UInt)XS); |
| 7122 | |
| 7123 | /* XS = SX || S |
| 7124 | * For SX=0, mfvsrd is treated as a Floating-Point |
| 7125 | * instruction in terms of resource availability. |
| 7126 | * For SX=1, mfvsrd is treated as a Vector instruction in |
| 7127 | * terms of resource availability. |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 7128 | * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 7129 | */ |
| 7130 | assign( vS, getVSReg( XS ) ); |
| 7131 | high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); |
| 7132 | putIReg( rA_addr, (mode64) ? high64 : |
| 7133 | unop( Iop_64to32, high64 ) ); |
| 7134 | break; |
| 7135 | } |
| 7136 | |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 7137 | case 0x73: // mfvsrwz |
| 7138 | { |
| 7139 | UChar XS = ifieldRegXS( theInstr ); |
| 7140 | UChar rA_addr = ifieldRegA(theInstr); |
| 7141 | IRExpr * high64; |
| 7142 | IRTemp vS = newTemp( Ity_V128 ); |
| 7143 | DIP("mfvsrwz r%u,vsr%d\n", rA_addr, (UInt)XS); |
| 7144 | /* XS = SX || S |
| 7145 | * For SX=0, mfvsrwz is treated as a Floating-Point |
| 7146 | * instruction in terms of resource availability. |
| 7147 | * For SX=1, mfvsrwz is treated as a Vector instruction in |
| 7148 | * terms of resource availability. |
| 7149 | * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART |
| 7150 | */ |
| 7151 | |
| 7152 | assign( vS, getVSReg( XS ) ); |
| 7153 | high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); |
| 7154 | /* move value to the destination setting the upper 32-bits to zero */ |
| 7155 | putIReg( rA_addr, (mode64) ? |
| 7156 | binop( Iop_And64, high64, mkU64( 0xFFFFFFFF ) ) : |
| 7157 | unop( Iop_64to32, |
| 7158 | binop( Iop_And64, high64, mkU64( 0xFFFFFFFF ) ) ) ); |
| 7159 | break; |
| 7160 | } |
| 7161 | |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 7162 | case 0xB3: // mtvsrd |
| 7163 | { |
| 7164 | UChar XT = ifieldRegXT( theInstr ); |
| 7165 | UChar rA_addr = ifieldRegA(theInstr); |
| 7166 | IRTemp rA = newTemp(ty); |
| 7167 | DIP("mtvsrd vsr%d,r%u\n", (UInt)XT, rA_addr); |
| 7168 | /* XS = SX || S |
| 7169 | * For SX=0, mfvsrd is treated as a Floating-Point |
| 7170 | * instruction in terms of resource availability. |
| 7171 | * For SX=1, mfvsrd is treated as a Vector instruction in |
| 7172 | * terms of resource availability. |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 7173 | * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 7174 | */ |
| 7175 | assign( rA, getIReg(rA_addr) ); |
| 7176 | |
| 7177 | if (mode64) |
| 7178 | putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( rA ), mkU64( 0 ) ) ); |
| 7179 | else |
| 7180 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 7181 | binop( Iop_32HLto64, |
| 7182 | mkU32( 0 ), |
| 7183 | mkexpr( rA ) ), |
| 7184 | mkU64( 0 ) ) ); |
| 7185 | break; |
| 7186 | } |
| 7187 | |
| 7188 | case 0xD3: // mtvsrwa |
| 7189 | { |
| 7190 | UChar XT = ifieldRegXT( theInstr ); |
| 7191 | UChar rA_addr = ifieldRegA(theInstr); |
| 7192 | IRTemp rA = newTemp( Ity_I32 ); |
| 7193 | DIP("mtvsrwa vsr%d,r%u\n", (UInt)XT, rA_addr); |
| 7194 | /* XS = SX || S |
| 7195 | * For SX=0, mtvsrwa is treated as a Floating-Point |
| 7196 | * instruction in terms of resource availability. |
| 7197 | * For SX=1, mtvsrwa is treated as a Vector instruction in |
| 7198 | * terms of resource availability. |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 7199 | * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 7200 | */ |
| 7201 | if (mode64) |
| 7202 | assign( rA, unop( Iop_64to32, getIReg( rA_addr ) ) ); |
| 7203 | else |
| 7204 | assign( rA, getIReg(rA_addr) ); |
| 7205 | |
| 7206 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 7207 | unop( Iop_32Sto64, mkexpr( rA ) ), |
| 7208 | mkU64( 0 ) ) ); |
| 7209 | break; |
| 7210 | } |
| 7211 | |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 7212 | case 0xF3: // mtvsrwz |
| 7213 | { |
| 7214 | UChar XT = ifieldRegXT( theInstr ); |
| 7215 | UChar rA_addr = ifieldRegA(theInstr); |
| 7216 | IRTemp rA = newTemp( Ity_I32 ); |
| 7217 | DIP("mtvsrwz vsr%d,r%u\n", rA_addr, (UInt)XT); |
| 7218 | /* XS = SX || S |
| 7219 | * For SX=0, mtvsrwz is treated as a Floating-Point |
| 7220 | * instruction in terms of resource availability. |
| 7221 | * For SX=1, mtvsrwz is treated as a Vector instruction in |
| 7222 | * terms of resource availability. |
| 7223 | * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART |
| 7224 | */ |
| 7225 | if (mode64) |
| 7226 | assign( rA, unop( Iop_64to32, getIReg( rA_addr ) ) ); |
| 7227 | else |
| 7228 | assign( rA, getIReg(rA_addr) ); |
| 7229 | |
| 7230 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 7231 | binop( Iop_32HLto64, mkU32( 0 ), mkexpr ( rA ) ), |
| 7232 | mkU64( 0 ) ) ); |
| 7233 | break; |
| 7234 | } |
| 7235 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7236 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7237 | vex_printf("dis_proc_ctl(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7238 | return False; |
| 7239 | } |
| 7240 | return True; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 7241 | } |
| 7242 | |
| 7243 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7244 | /* |
| 7245 | Cache Management Instructions |
| 7246 | */ |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 7247 | static Bool dis_cache_manage ( UInt theInstr, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7248 | DisResult* dres, |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 7249 | VexArchInfo* guest_archinfo ) |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 7250 | { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7251 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7252 | UChar opc1 = ifieldOPC(theInstr); |
| 7253 | UChar b21to25 = ifieldRegDS(theInstr); |
| 7254 | UChar rA_addr = ifieldRegA(theInstr); |
| 7255 | UChar rB_addr = ifieldRegB(theInstr); |
| 7256 | UInt opc2 = ifieldOPClo10(theInstr); |
| 7257 | UChar b0 = ifieldBIT0(theInstr); |
florian | 9138b17 | 2013-08-03 19:36:55 +0000 | [diff] [blame] | 7258 | UInt lineszB = guest_archinfo->ppc_icache_line_szB; |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 7259 | Bool is_dcbzl = False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7260 | |
| 7261 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7262 | |
carll | b77db0e | 2013-09-05 19:47:40 +0000 | [diff] [blame] | 7263 | // Check for valid hint values for dcbt and dcbtst as currently described in |
| 7264 | // ISA 2.07. If valid, then we simply set b21to25 to zero since we have no |
| 7265 | // means of modeling the hint anyway. |
| 7266 | if (opc1 == 0x1F && ((opc2 == 0x116) || (opc2 == 0xF6))) { |
carll | 9708b6a | 2013-09-06 16:49:42 +0000 | [diff] [blame] | 7267 | if (b21to25 == 0x10 || b21to25 < 0x10) |
carll | b77db0e | 2013-09-05 19:47:40 +0000 | [diff] [blame] | 7268 | b21to25 = 0; |
sewardj | 6be6723 | 2006-01-24 19:00:05 +0000 | [diff] [blame] | 7269 | } |
carll | 9708b6a | 2013-09-06 16:49:42 +0000 | [diff] [blame] | 7270 | if (opc1 == 0x1F && opc2 == 0x116 && b21to25 == 0x11) |
carll | b77db0e | 2013-09-05 19:47:40 +0000 | [diff] [blame] | 7271 | b21to25 = 0; |
| 7272 | |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 7273 | if (opc1 == 0x1F && opc2 == 0x3F6) { // dcbz |
| 7274 | if (b21to25 == 1) { |
| 7275 | is_dcbzl = True; |
| 7276 | b21to25 = 0; |
| 7277 | if (!(guest_archinfo->ppc_dcbzl_szB)) { |
| 7278 | vex_printf("dis_cache_manage(ppc)(dcbzl not supported by host)\n"); |
| 7279 | return False; |
| 7280 | } |
| 7281 | } |
| 7282 | } |
sewardj | 6be6723 | 2006-01-24 19:00:05 +0000 | [diff] [blame] | 7283 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7284 | if (opc1 != 0x1F || b21to25 != 0 || b0 != 0) { |
sewardj | 6be6723 | 2006-01-24 19:00:05 +0000 | [diff] [blame] | 7285 | if (0) vex_printf("dis_cache_manage %d %d %d\n", |
| 7286 | (Int)opc1, (Int)b21to25, (Int)b0); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7287 | vex_printf("dis_cache_manage(ppc)(opc1|b21to25|b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7288 | return False; |
| 7289 | } |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 7290 | |
| 7291 | /* stay sane .. */ |
sewardj | 2691a61 | 2013-10-14 11:40:24 +0000 | [diff] [blame] | 7292 | vassert(lineszB == 16 || lineszB == 32 || lineszB == 64 || lineszB == 128); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7293 | |
| 7294 | switch (opc2) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 7295 | //zz case 0x2F6: // dcba (Data Cache Block Allocate, PPC32 p380) |
| 7296 | //zz vassert(0); /* AWAITING TEST CASE */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7297 | //zz DIP("dcba r%u,r%u\n", rA_addr, rB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7298 | //zz if (0) vex_printf("vex ppc->IR: kludged dcba\n"); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 7299 | //zz break; |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 7300 | |
| 7301 | case 0x056: // dcbf (Data Cache Block Flush, PPC32 p382) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7302 | DIP("dcbf r%u,r%u\n", rA_addr, rB_addr); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 7303 | /* nop as far as vex is concerned */ |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 7304 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7305 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 7306 | case 0x036: // dcbst (Data Cache Block Store, PPC32 p384) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7307 | DIP("dcbst r%u,r%u\n", rA_addr, rB_addr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 7308 | /* nop as far as vex is concerned */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7309 | break; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 7310 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 7311 | case 0x116: // dcbt (Data Cache Block Touch, PPC32 p385) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7312 | DIP("dcbt r%u,r%u\n", rA_addr, rB_addr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 7313 | /* nop as far as vex is concerned */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7314 | break; |
| 7315 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 7316 | case 0x0F6: // dcbtst (Data Cache Block Touch for Store, PPC32 p386) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7317 | DIP("dcbtst r%u,r%u\n", rA_addr, rB_addr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 7318 | /* nop as far as vex is concerned */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7319 | break; |
| 7320 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7321 | case 0x3F6: { // dcbz (Data Cache Block Clear to Zero, PPC32 p387) |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 7322 | // dcbzl (Data Cache Block Clear to Zero Long, bug#135264) |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 7323 | /* Clear all bytes in cache block at (rA|0) + rB. */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7324 | IRTemp EA = newTemp(ty); |
| 7325 | IRTemp addr = newTemp(ty); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7326 | IRExpr* irx_addr; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7327 | UInt i; |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 7328 | UInt clearszB; |
| 7329 | if (is_dcbzl) { |
| 7330 | clearszB = guest_archinfo->ppc_dcbzl_szB; |
| 7331 | DIP("dcbzl r%u,r%u\n", rA_addr, rB_addr); |
| 7332 | } |
| 7333 | else { |
| 7334 | clearszB = guest_archinfo->ppc_dcbz_szB; |
| 7335 | DIP("dcbz r%u,r%u\n", rA_addr, rB_addr); |
| 7336 | } |
sewardj | cb1f68e | 2005-12-30 03:39:14 +0000 | [diff] [blame] | 7337 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7338 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7339 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7340 | if (mode64) { |
| 7341 | /* Round EA down to the start of the containing block. */ |
| 7342 | assign( addr, binop( Iop_And64, |
| 7343 | mkexpr(EA), |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 7344 | mkU64( ~((ULong)clearszB-1) )) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7345 | |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 7346 | for (i = 0; i < clearszB / 8; i++) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7347 | irx_addr = binop( Iop_Add64, mkexpr(addr), mkU64(i*8) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7348 | store( irx_addr, mkU64(0) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7349 | } |
| 7350 | } else { |
| 7351 | /* Round EA down to the start of the containing block. */ |
| 7352 | assign( addr, binop( Iop_And32, |
| 7353 | mkexpr(EA), |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 7354 | mkU32( ~(clearszB-1) )) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7355 | |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 7356 | for (i = 0; i < clearszB / 4; i++) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7357 | irx_addr = binop( Iop_Add32, mkexpr(addr), mkU32(i*4) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7358 | store( irx_addr, mkU32(0) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7359 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7360 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7361 | break; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7362 | } |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 7363 | |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 7364 | case 0x3D6: { |
| 7365 | // icbi (Instruction Cache Block Invalidate, PPC32 p431) |
| 7366 | /* Invalidate all translations containing code from the cache |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 7367 | block at (rA|0) + rB. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7368 | IRTemp EA = newTemp(ty); |
| 7369 | IRTemp addr = newTemp(ty); |
| 7370 | DIP("icbi r%u,r%u\n", rA_addr, rB_addr); |
| 7371 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 7372 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7373 | /* Round EA down to the start of the containing block. */ |
| 7374 | assign( addr, binop( mkSzOp(ty, Iop_And8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7375 | mkexpr(EA), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7376 | mkSzImm(ty, ~(((ULong)lineszB)-1) )) ); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 7377 | putGST( PPC_GST_CMSTART, mkexpr(addr) ); |
| 7378 | putGST( PPC_GST_CMLEN, mkSzImm(ty, lineszB) ); |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 7379 | |
sewardj | a8078f6 | 2005-03-15 18:27:40 +0000 | [diff] [blame] | 7380 | /* be paranoid ... */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7381 | stmt( IRStmt_MBE(Imbe_Fence) ); |
sewardj | a8078f6 | 2005-03-15 18:27:40 +0000 | [diff] [blame] | 7382 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 7383 | putGST( PPC_GST_CIA, mkSzImm(ty, nextInsnAddr())); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 7384 | dres->jk_StopHere = Ijk_InvalICache; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 7385 | dres->whatNext = Dis_StopHere; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7386 | break; |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 7387 | } |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 7388 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7389 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7390 | vex_printf("dis_cache_manage(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 7391 | return False; |
| 7392 | } |
| 7393 | return True; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 7394 | } |
| 7395 | |
| 7396 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7397 | /*------------------------------------------------------------*/ |
| 7398 | /*--- Floating Point Helpers ---*/ |
| 7399 | /*------------------------------------------------------------*/ |
| 7400 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7401 | /* --------- Synthesise a 2-bit FPU rounding mode. --------- */ |
| 7402 | /* Produces a value in 0 .. 3, which is encoded as per the type |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7403 | IRRoundingMode. PPCRoundingMode encoding is different to |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7404 | IRRoundingMode, so need to map it. |
| 7405 | */ |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7406 | static IRExpr* /* :: Ity_I32 */ get_IR_roundingmode ( void ) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7407 | { |
| 7408 | /* |
| 7409 | rounding mode | PPC | IR |
| 7410 | ------------------------ |
| 7411 | to nearest | 00 | 00 |
| 7412 | to zero | 01 | 11 |
| 7413 | to +infinity | 10 | 10 |
| 7414 | to -infinity | 11 | 01 |
| 7415 | */ |
| 7416 | IRTemp rm_PPC32 = newTemp(Ity_I32); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7417 | assign( rm_PPC32, getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN ) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7418 | |
| 7419 | // rm_IR = XOR( rm_PPC32, (rm_PPC32 << 1) & 2) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7420 | return binop( Iop_Xor32, |
| 7421 | mkexpr(rm_PPC32), |
| 7422 | binop( Iop_And32, |
| 7423 | binop(Iop_Shl32, mkexpr(rm_PPC32), mkU8(1)), |
| 7424 | mkU32(2) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7425 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7426 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 7427 | /* The DFP IR rounding modes were chosen such that the existing PPC to IR |
| 7428 | * mapping would still work with the extended three bit DFP rounding |
| 7429 | * mode designator. |
| 7430 | |
| 7431 | * rounding mode | PPC | IR |
| 7432 | * ----------------------------------------------- |
| 7433 | * to nearest, ties to even | 000 | 000 |
| 7434 | * to zero | 001 | 011 |
| 7435 | * to +infinity | 010 | 010 |
| 7436 | * to -infinity | 011 | 001 |
| 7437 | * to nearest, ties away from 0 | 100 | 100 |
| 7438 | * to nearest, ties toward 0 | 101 | 111 |
| 7439 | * to away from 0 | 110 | 110 |
| 7440 | * to prepare for shorter precision | 111 | 101 |
| 7441 | */ |
| 7442 | static IRExpr* /* :: Ity_I32 */ get_IR_roundingmode_DFP( void ) |
| 7443 | { |
| 7444 | IRTemp rm_PPC32 = newTemp( Ity_I32 ); |
| 7445 | assign( rm_PPC32, getGST_masked_upper( PPC_GST_FPSCR, MASK_FPSCR_DRN ) ); |
| 7446 | |
| 7447 | // rm_IR = XOR( rm_PPC32, (rm_PPC32 << 1) & 2) |
| 7448 | return binop( Iop_Xor32, |
| 7449 | mkexpr( rm_PPC32 ), |
| 7450 | binop( Iop_And32, |
| 7451 | binop( Iop_Shl32, mkexpr( rm_PPC32 ), mkU8( 1 ) ), |
| 7452 | mkU32( 2 ) ) ); |
| 7453 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7454 | |
sewardj | 2bcdd65 | 2012-07-14 08:22:13 +0000 | [diff] [blame] | 7455 | #define NANmaskSingle 0x7F800000 |
| 7456 | #define NANmaskDouble 0x7FF00000 |
| 7457 | |
| 7458 | static IRExpr * Check_NaN( IRExpr * value, IRExpr * Hi32Mask ) |
| 7459 | { |
| 7460 | IRTemp exp_zero = newTemp(Ity_I8); |
| 7461 | IRTemp frac_mask = newTemp(Ity_I32); |
| 7462 | IRTemp frac_not_zero = newTemp(Ity_I8); |
| 7463 | |
| 7464 | /* Check if the result is QNAN or SNAN and not +infinity or -infinity. |
| 7465 | * The input value is always 64-bits, for single precision values, the |
| 7466 | * lower 32 bits must be zero. |
| 7467 | * |
| 7468 | * Single Pricision |
| 7469 | * [62:54] exponent field is equal to 0xFF for NAN and Infinity. |
| 7470 | * [53:32] fraction field is zero for Infinity and non-zero for NAN |
| 7471 | * [31:0] unused for single precision representation |
| 7472 | * |
| 7473 | * Double Pricision |
| 7474 | * [62:51] exponent field is equal to 0xFF for NAN and Infinity. |
| 7475 | * [50:0] fraction field is zero for Infinity and non-zero for NAN |
| 7476 | * |
| 7477 | * Returned result is a U32 value of 0xFFFFFFFF for NaN and 0 otherwise. |
| 7478 | */ |
| 7479 | assign( frac_mask, unop( Iop_Not32, |
| 7480 | binop( Iop_Or32, |
| 7481 | mkU32( 0x80000000ULL ), Hi32Mask) ) ); |
| 7482 | |
| 7483 | assign( exp_zero, |
| 7484 | unop( Iop_1Sto8, |
| 7485 | binop( Iop_CmpEQ32, |
| 7486 | binop( Iop_And32, |
| 7487 | unop( Iop_64HIto32, |
| 7488 | unop( Iop_ReinterpF64asI64, |
| 7489 | value ) ), |
| 7490 | Hi32Mask ), |
| 7491 | Hi32Mask ) ) ); |
| 7492 | assign( frac_not_zero, |
| 7493 | binop( Iop_Or8, |
| 7494 | unop( Iop_1Sto8, |
| 7495 | binop( Iop_CmpNE32, |
| 7496 | binop( Iop_And32, |
| 7497 | unop( Iop_64HIto32, |
| 7498 | unop( Iop_ReinterpF64asI64, |
| 7499 | value ) ), |
| 7500 | mkexpr( frac_mask ) ), |
| 7501 | mkU32( 0x0 ) ) ), |
| 7502 | unop( Iop_1Sto8, |
| 7503 | binop( Iop_CmpNE32, |
| 7504 | binop( Iop_And32, |
| 7505 | unop( Iop_64to32, |
| 7506 | unop( Iop_ReinterpF64asI64, |
| 7507 | value ) ), |
| 7508 | mkU32( 0xFFFFFFFF ) ), |
| 7509 | mkU32( 0x0 ) ) ) ) ); |
| 7510 | return unop( Iop_8Sto32, |
| 7511 | binop( Iop_And8, |
| 7512 | mkexpr( exp_zero ), |
| 7513 | mkexpr( frac_not_zero ) ) ); |
| 7514 | } |
| 7515 | |
| 7516 | static IRExpr * Complement_non_NaN( IRExpr * value, IRExpr * nan_mask ) |
| 7517 | { |
| 7518 | /* This function will only complement the 64-bit floating point value if it |
| 7519 | * is not Nan. NaN is not a signed value. Need to do computations using |
| 7520 | * 32-bit operands to ensure it will run in 32-bit mode. |
| 7521 | */ |
| 7522 | return binop( Iop_32HLto64, |
| 7523 | binop( Iop_Or32, |
| 7524 | binop( Iop_And32, |
| 7525 | nan_mask, |
| 7526 | unop( Iop_64HIto32, |
| 7527 | unop( Iop_ReinterpF64asI64, |
| 7528 | value ) ) ), |
| 7529 | binop( Iop_And32, |
| 7530 | unop( Iop_Not32, |
| 7531 | nan_mask ), |
| 7532 | unop( Iop_64HIto32, |
| 7533 | unop( Iop_ReinterpF64asI64, |
| 7534 | unop( Iop_NegF64, |
| 7535 | value ) ) ) ) ), |
| 7536 | unop( Iop_64to32, |
| 7537 | unop( Iop_ReinterpF64asI64, value ) ) ); |
| 7538 | } |
| 7539 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7540 | /*------------------------------------------------------------*/ |
| 7541 | /*--- Floating Point Instruction Translation ---*/ |
| 7542 | /*------------------------------------------------------------*/ |
| 7543 | |
| 7544 | /* |
| 7545 | Floating Point Load Instructions |
| 7546 | */ |
| 7547 | static Bool dis_fp_load ( UInt theInstr ) |
| 7548 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7549 | /* X-Form, D-Form */ |
| 7550 | UChar opc1 = ifieldOPC(theInstr); |
| 7551 | UChar frD_addr = ifieldRegDS(theInstr); |
| 7552 | UChar rA_addr = ifieldRegA(theInstr); |
| 7553 | UChar rB_addr = ifieldRegB(theInstr); |
| 7554 | UInt opc2 = ifieldOPClo10(theInstr); |
| 7555 | UChar b0 = ifieldBIT0(theInstr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7556 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7557 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7558 | Int simm16 = extend_s_16to32(uimm16); |
| 7559 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 7560 | IRTemp EA = newTemp(ty); |
| 7561 | IRTemp rA = newTemp(ty); |
| 7562 | IRTemp rB = newTemp(ty); |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 7563 | IRTemp iHi = newTemp(Ity_I32); |
| 7564 | IRTemp iLo = newTemp(Ity_I32); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7565 | |
| 7566 | assign( rA, getIReg(rA_addr) ); |
| 7567 | assign( rB, getIReg(rB_addr) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7568 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7569 | /* These are completely straightforward from a rounding and status |
| 7570 | bits perspective: no rounding involved and no funny status or CR |
| 7571 | bits affected. */ |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7572 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7573 | switch (opc1) { |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7574 | case 0x30: // lfs (Load Float Single, PPC32 p441) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7575 | DIP("lfs fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); |
| 7576 | assign( EA, ea_rAor0_simm(rA_addr, simm16) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7577 | putFReg( frD_addr, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7578 | unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7579 | break; |
| 7580 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7581 | case 0x31: // lfsu (Load Float Single, Update, PPC32 p442) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7582 | if (rA_addr == 0) |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 7583 | return False; |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 7584 | DIP("lfsu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); |
| 7585 | assign( EA, ea_rA_simm(rA_addr, simm16) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7586 | putFReg( frD_addr, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7587 | unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) ); |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 7588 | putIReg( rA_addr, mkexpr(EA) ); |
| 7589 | break; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7590 | |
| 7591 | case 0x32: // lfd (Load Float Double, PPC32 p437) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7592 | DIP("lfd fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); |
| 7593 | assign( EA, ea_rAor0_simm(rA_addr, simm16) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7594 | putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7595 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7596 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7597 | case 0x33: // lfdu (Load Float Double, Update, PPC32 p438) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7598 | if (rA_addr == 0) |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 7599 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7600 | DIP("lfdu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); |
| 7601 | assign( EA, ea_rA_simm(rA_addr, simm16) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7602 | putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 7603 | putIReg( rA_addr, mkexpr(EA) ); |
| 7604 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7605 | |
| 7606 | case 0x1F: |
| 7607 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7608 | vex_printf("dis_fp_load(ppc)(instr,b0)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7609 | return False; |
| 7610 | } |
| 7611 | |
| 7612 | switch(opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7613 | case 0x217: // lfsx (Load Float Single Indexed, PPC32 p444) |
| 7614 | DIP("lfsx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 7615 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
| 7616 | putFReg( frD_addr, unop( Iop_F32toF64, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7617 | load(Ity_F32, mkexpr(EA))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7618 | break; |
| 7619 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7620 | case 0x237: // lfsux (Load Float Single, Update Indxd, PPC32 p443) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7621 | if (rA_addr == 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7622 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7623 | DIP("lfsux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 7624 | assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7625 | putFReg( frD_addr, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7626 | unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7627 | putIReg( rA_addr, mkexpr(EA) ); |
| 7628 | break; |
| 7629 | |
| 7630 | case 0x257: // lfdx (Load Float Double Indexed, PPC32 p440) |
| 7631 | DIP("lfdx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 7632 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7633 | putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7634 | break; |
| 7635 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7636 | case 0x277: // lfdux (Load Float Double, Update Indxd, PPC32 p439) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7637 | if (rA_addr == 0) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7638 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7639 | DIP("lfdux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 7640 | assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7641 | putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7642 | putIReg( rA_addr, mkexpr(EA) ); |
| 7643 | break; |
| 7644 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 7645 | case 0x357: // lfiwax (Load Float As Integer, Indxd, ISA 2.05 p120) |
| 7646 | DIP("lfiwax fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 7647 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7648 | assign( iLo, load(Ity_I32, mkexpr(EA)) ); |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 7649 | assign( iHi, binop(Iop_Sub32, |
| 7650 | mkU32(0), |
| 7651 | binop(Iop_Shr32, mkexpr(iLo), mkU8(31))) ); |
| 7652 | putFReg( frD_addr, unop(Iop_ReinterpI64asF64, |
| 7653 | binop(Iop_32HLto64, mkexpr(iHi), mkexpr(iLo))) ); |
| 7654 | break; |
| 7655 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 7656 | case 0x377: // lfiwzx (Load floating-point as integer word, zero indexed |
| 7657 | { |
| 7658 | IRTemp dw = newTemp( Ity_I64 ); |
| 7659 | DIP("lfiwzx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 7660 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7661 | assign( iLo, load(Ity_I32, mkexpr(EA)) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 7662 | assign( dw, binop( Iop_32HLto64, mkU32( 0 ), mkexpr( iLo ) ) ); |
| 7663 | putFReg( frD_addr, unop( Iop_ReinterpI64asF64, mkexpr( dw ) ) ); |
| 7664 | break; |
| 7665 | } |
| 7666 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7667 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7668 | vex_printf("dis_fp_load(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7669 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7670 | } |
| 7671 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7672 | |
| 7673 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7674 | vex_printf("dis_fp_load(ppc)(opc1)\n"); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7675 | return False; |
| 7676 | } |
| 7677 | return True; |
| 7678 | } |
| 7679 | |
| 7680 | |
| 7681 | |
| 7682 | /* |
| 7683 | Floating Point Store Instructions |
| 7684 | */ |
| 7685 | static Bool dis_fp_store ( UInt theInstr ) |
| 7686 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7687 | /* X-Form, D-Form */ |
| 7688 | UChar opc1 = ifieldOPC(theInstr); |
| 7689 | UChar frS_addr = ifieldRegDS(theInstr); |
| 7690 | UChar rA_addr = ifieldRegA(theInstr); |
| 7691 | UChar rB_addr = ifieldRegB(theInstr); |
| 7692 | UInt opc2 = ifieldOPClo10(theInstr); |
| 7693 | UChar b0 = ifieldBIT0(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7694 | Int uimm16 = ifieldUIMM16(theInstr); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7695 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 7696 | Int simm16 = extend_s_16to32(uimm16); |
| 7697 | IRTemp frS = newTemp(Ity_F64); |
| 7698 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 7699 | IRTemp EA = newTemp(ty); |
| 7700 | IRTemp rA = newTemp(ty); |
| 7701 | IRTemp rB = newTemp(ty); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7702 | |
| 7703 | assign( frS, getFReg(frS_addr) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 7704 | assign( rA, getIReg(rA_addr) ); |
| 7705 | assign( rB, getIReg(rB_addr) ); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7706 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7707 | /* These are straightforward from a status bits perspective: no |
| 7708 | funny status or CR bits affected. For single precision stores, |
| 7709 | the values are truncated and denormalised (not rounded) to turn |
| 7710 | them into single precision values. */ |
| 7711 | |
| 7712 | switch (opc1) { |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7713 | |
| 7714 | case 0x34: // stfs (Store Float Single, PPC32 p518) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7715 | DIP("stfs fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); |
| 7716 | assign( EA, ea_rAor0_simm(rA_addr, simm16) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7717 | /* Use Iop_TruncF64asF32 to truncate and possible denormalise |
| 7718 | the value to be stored in the correct way, without any |
| 7719 | rounding. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7720 | store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7721 | break; |
| 7722 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7723 | case 0x35: // stfsu (Store Float Single, Update, PPC32 p519) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7724 | if (rA_addr == 0) |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 7725 | return False; |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 7726 | DIP("stfsu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); |
| 7727 | assign( EA, ea_rA_simm(rA_addr, simm16) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7728 | /* See comment for stfs */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7729 | store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) ); |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 7730 | putIReg( rA_addr, mkexpr(EA) ); |
| 7731 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7732 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7733 | case 0x36: // stfd (Store Float Double, PPC32 p513) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7734 | DIP("stfd fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); |
| 7735 | assign( EA, ea_rAor0_simm(rA_addr, simm16) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7736 | store( mkexpr(EA), mkexpr(frS) ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7737 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7738 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7739 | case 0x37: // stfdu (Store Float Double, Update, PPC32 p514) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7740 | if (rA_addr == 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7741 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7742 | DIP("stfdu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); |
| 7743 | assign( EA, ea_rA_simm(rA_addr, simm16) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7744 | store( mkexpr(EA), mkexpr(frS) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7745 | putIReg( rA_addr, mkexpr(EA) ); |
| 7746 | break; |
| 7747 | |
| 7748 | case 0x1F: |
| 7749 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7750 | vex_printf("dis_fp_store(ppc)(instr,b0)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7751 | return False; |
| 7752 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7753 | switch(opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7754 | case 0x297: // stfsx (Store Float Single Indexed, PPC32 p521) |
| 7755 | DIP("stfsx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 7756 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7757 | /* See note for stfs */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7758 | store( mkexpr(EA), |
| 7759 | unop(Iop_TruncF64asF32, mkexpr(frS)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7760 | break; |
| 7761 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7762 | case 0x2B7: // stfsux (Store Float Sgl, Update Indxd, PPC32 p520) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7763 | if (rA_addr == 0) |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 7764 | return False; |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 7765 | DIP("stfsux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 7766 | assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7767 | /* See note for stfs */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7768 | store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) ); |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 7769 | putIReg( rA_addr, mkexpr(EA) ); |
| 7770 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7771 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7772 | case 0x2D7: // stfdx (Store Float Double Indexed, PPC32 p516) |
| 7773 | DIP("stfdx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 7774 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7775 | store( mkexpr(EA), mkexpr(frS) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7776 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7777 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7778 | case 0x2F7: // stfdux (Store Float Dbl, Update Indxd, PPC32 p515) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7779 | if (rA_addr == 0) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7780 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7781 | DIP("stfdux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 7782 | assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7783 | store( mkexpr(EA), mkexpr(frS) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7784 | putIReg( rA_addr, mkexpr(EA) ); |
| 7785 | break; |
sewardj | 5f63c0c | 2005-09-09 10:36:55 +0000 | [diff] [blame] | 7786 | |
sewardj | 09e88d1 | 2006-01-27 16:05:49 +0000 | [diff] [blame] | 7787 | case 0x3D7: // stfiwx (Store Float as Int, Indexed, PPC32 p517) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 7788 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
sewardj | 09e88d1 | 2006-01-27 16:05:49 +0000 | [diff] [blame] | 7789 | DIP("stfiwx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 7790 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 7791 | store( mkexpr(EA), |
| 7792 | unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))) ); |
sewardj | 09e88d1 | 2006-01-27 16:05:49 +0000 | [diff] [blame] | 7793 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7794 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7795 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7796 | vex_printf("dis_fp_store(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 7797 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7798 | } |
| 7799 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7800 | |
| 7801 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7802 | vex_printf("dis_fp_store(ppc)(opc1)\n"); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7803 | return False; |
| 7804 | } |
| 7805 | return True; |
| 7806 | } |
| 7807 | |
| 7808 | |
| 7809 | |
| 7810 | /* |
| 7811 | Floating Point Arith Instructions |
| 7812 | */ |
| 7813 | static Bool dis_fp_arith ( UInt theInstr ) |
| 7814 | { |
| 7815 | /* A-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7816 | UChar opc1 = ifieldOPC(theInstr); |
| 7817 | UChar frD_addr = ifieldRegDS(theInstr); |
| 7818 | UChar frA_addr = ifieldRegA(theInstr); |
| 7819 | UChar frB_addr = ifieldRegB(theInstr); |
| 7820 | UChar frC_addr = ifieldRegC(theInstr); |
| 7821 | UChar opc2 = ifieldOPClo5(theInstr); |
| 7822 | UChar flag_rC = ifieldBIT0(theInstr); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7823 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7824 | IRTemp frD = newTemp(Ity_F64); |
| 7825 | IRTemp frA = newTemp(Ity_F64); |
| 7826 | IRTemp frB = newTemp(Ity_F64); |
| 7827 | IRTemp frC = newTemp(Ity_F64); |
| 7828 | IRExpr* rm = get_IR_roundingmode(); |
| 7829 | |
| 7830 | /* By default, we will examine the results of the operation and set |
| 7831 | fpscr[FPRF] accordingly. */ |
| 7832 | Bool set_FPRF = True; |
| 7833 | |
| 7834 | /* By default, if flag_RC is set, we will clear cr1 after the |
| 7835 | operation. In reality we should set cr1 to indicate the |
| 7836 | exception status of the operation, but since we're not |
| 7837 | simulating exceptions, the exception status will appear to be |
| 7838 | zero. Hence cr1 should be cleared if this is a . form insn. */ |
| 7839 | Bool clear_CR1 = True; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7840 | |
| 7841 | assign( frA, getFReg(frA_addr)); |
| 7842 | assign( frB, getFReg(frB_addr)); |
| 7843 | assign( frC, getFReg(frC_addr)); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7844 | |
| 7845 | switch (opc1) { |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7846 | case 0x3B: |
| 7847 | switch (opc2) { |
| 7848 | case 0x12: // fdivs (Floating Divide Single, PPC32 p407) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7849 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7850 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7851 | DIP("fdivs%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7852 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7853 | assign( frD, triop( Iop_DivF64r32, |
| 7854 | rm, mkexpr(frA), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7855 | break; |
| 7856 | |
| 7857 | case 0x14: // fsubs (Floating Subtract Single, PPC32 p430) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7858 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7859 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7860 | DIP("fsubs%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7861 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7862 | assign( frD, triop( Iop_SubF64r32, |
| 7863 | rm, mkexpr(frA), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7864 | break; |
| 7865 | |
| 7866 | case 0x15: // fadds (Floating Add Single, PPC32 p401) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7867 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7868 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7869 | DIP("fadds%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7870 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7871 | assign( frD, triop( Iop_AddF64r32, |
| 7872 | rm, mkexpr(frA), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7873 | break; |
| 7874 | |
sewardj | 870c84b | 2006-01-24 03:33:43 +0000 | [diff] [blame] | 7875 | case 0x16: // fsqrts (Floating SqRt (Single-Precision), PPC32 p428) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 7876 | // NOTE: POWERPC OPTIONAL, "General-Purpose Group" (PPC32_FX) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7877 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | 870c84b | 2006-01-24 03:33:43 +0000 | [diff] [blame] | 7878 | return False; |
sewardj | 870c84b | 2006-01-24 03:33:43 +0000 | [diff] [blame] | 7879 | DIP("fsqrts%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 7880 | frD_addr, frB_addr); |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 7881 | // however illogically, on ppc970 this insn behaves identically |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7882 | // to fsqrt (double-precision). So use SqrtF64, not SqrtF64r32. |
| 7883 | assign( frD, binop( Iop_SqrtF64, rm, mkexpr(frB) )); |
sewardj | 870c84b | 2006-01-24 03:33:43 +0000 | [diff] [blame] | 7884 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7885 | |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 7886 | case 0x18: // fres (Floating Reciprocal Estimate Single, PPC32 p421) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 7887 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7888 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 7889 | return False; |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 7890 | DIP("fres%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 7891 | frD_addr, frB_addr); |
sewardj | 157b19b | 2006-01-31 16:32:25 +0000 | [diff] [blame] | 7892 | { IRExpr* ieee_one |
| 7893 | = IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL)); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7894 | assign( frD, triop( Iop_DivF64r32, |
| 7895 | rm, |
| 7896 | ieee_one, mkexpr(frB) )); |
sewardj | 157b19b | 2006-01-31 16:32:25 +0000 | [diff] [blame] | 7897 | } |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 7898 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7899 | |
| 7900 | case 0x19: // fmuls (Floating Multiply Single, PPC32 p414) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7901 | if (frB_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7902 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7903 | DIP("fmuls%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7904 | frD_addr, frA_addr, frC_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7905 | assign( frD, triop( Iop_MulF64r32, |
| 7906 | rm, mkexpr(frA), mkexpr(frC) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7907 | break; |
| 7908 | |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 7909 | case 0x1A: // frsqrtes (Floating Recip SqRt Est Single) |
| 7910 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
| 7911 | // Undocumented instruction? |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7912 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 7913 | return False; |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 7914 | DIP("frsqrtes%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 7915 | frD_addr, frB_addr); |
| 7916 | assign( frD, unop(Iop_Est5FRSqrt, mkexpr(frB)) ); |
| 7917 | break; |
| 7918 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7919 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7920 | vex_printf("dis_fp_arith(ppc)(3B: opc2)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7921 | return False; |
| 7922 | } |
| 7923 | break; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7924 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7925 | case 0x3F: |
| 7926 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7927 | case 0x12: // fdiv (Floating Div (Double-Precision), PPC32 p406) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7928 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7929 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7930 | DIP("fdiv%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7931 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7932 | assign( frD, triop(Iop_DivF64, rm, mkexpr(frA), mkexpr(frB)) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7933 | break; |
| 7934 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7935 | case 0x14: // fsub (Floating Sub (Double-Precision), PPC32 p429) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7936 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7937 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7938 | DIP("fsub%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7939 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7940 | assign( frD, triop(Iop_SubF64, rm, mkexpr(frA), mkexpr(frB)) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7941 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7942 | |
| 7943 | case 0x15: // fadd (Floating Add (Double-Precision), PPC32 p400) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7944 | if (frC_addr != 0) |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7945 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7946 | DIP("fadd%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7947 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7948 | assign( frD, triop(Iop_AddF64, rm, mkexpr(frA), mkexpr(frB)) ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 7949 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 7950 | |
cerion | 876ef41 | 2005-12-14 22:00:53 +0000 | [diff] [blame] | 7951 | case 0x16: // fsqrt (Floating SqRt (Double-Precision), PPC32 p427) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 7952 | // NOTE: POWERPC OPTIONAL, "General-Purpose Group" (PPC32_FX) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7953 | if (frA_addr != 0 || frC_addr != 0) |
cerion | 876ef41 | 2005-12-14 22:00:53 +0000 | [diff] [blame] | 7954 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7955 | DIP("fsqrt%s fr%u,fr%u\n", flag_rC ? ".":"", |
cerion | 876ef41 | 2005-12-14 22:00:53 +0000 | [diff] [blame] | 7956 | frD_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7957 | assign( frD, binop(Iop_SqrtF64, rm, mkexpr(frB)) ); |
cerion | 876ef41 | 2005-12-14 22:00:53 +0000 | [diff] [blame] | 7958 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7959 | |
| 7960 | case 0x17: { // fsel (Floating Select, PPC32 p426) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 7961 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7962 | IRTemp cc = newTemp(Ity_I32); |
| 7963 | IRTemp cc_b0 = newTemp(Ity_I32); |
| 7964 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7965 | DIP("fsel%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7966 | frD_addr, frA_addr, frC_addr, frB_addr); |
| 7967 | |
| 7968 | // cc: UN == 0x41, LT == 0x01, GT == 0x00, EQ == 0x40 |
| 7969 | // => GT|EQ == (cc & 0x1 == 0) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7970 | assign( cc, binop(Iop_CmpF64, mkexpr(frA), |
| 7971 | IRExpr_Const(IRConst_F64(0))) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7972 | assign( cc_b0, binop(Iop_And32, mkexpr(cc), mkU32(1)) ); |
| 7973 | |
| 7974 | // frD = (frA >= 0.0) ? frC : frB |
| 7975 | // = (cc_b0 == 0) ? frC : frB |
| 7976 | assign( frD, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7977 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 7978 | binop(Iop_CmpEQ32, mkexpr(cc_b0), mkU32(0)), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7979 | mkexpr(frC), |
| 7980 | mkexpr(frB) )); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7981 | |
| 7982 | /* One of the rare ones which don't mess with FPRF */ |
| 7983 | set_FPRF = False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 7984 | break; |
| 7985 | } |
| 7986 | |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 7987 | case 0x18: // fre (Floating Reciprocal Estimate) |
| 7988 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
| 7989 | // Note: unclear whether this insn really exists or not |
| 7990 | // ppc970 doesn't have it, but POWER5 does |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7991 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 7992 | return False; |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 7993 | DIP("fre%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 7994 | frD_addr, frB_addr); |
sewardj | 157b19b | 2006-01-31 16:32:25 +0000 | [diff] [blame] | 7995 | { IRExpr* ieee_one |
| 7996 | = IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL)); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7997 | assign( frD, triop( Iop_DivF64, |
sewardj | 56de421 | 2006-02-06 22:19:17 +0000 | [diff] [blame] | 7998 | rm, |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 7999 | ieee_one, mkexpr(frB) )); |
sewardj | 157b19b | 2006-01-31 16:32:25 +0000 | [diff] [blame] | 8000 | } |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 8001 | break; |
| 8002 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8003 | case 0x19: // fmul (Floating Mult (Double Precision), PPC32 p413) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8004 | if (frB_addr != 0) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8005 | vex_printf("dis_fp_arith(ppc)(instr,fmul)\n"); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8006 | DIP("fmul%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8007 | frD_addr, frA_addr, frC_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8008 | assign( frD, triop(Iop_MulF64, rm, mkexpr(frA), mkexpr(frC)) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8009 | break; |
| 8010 | |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 8011 | case 0x1A: // frsqrte (Floating Recip SqRt Est., PPC32 p424) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8012 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8013 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 8014 | return False; |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 8015 | DIP("frsqrte%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 8016 | frD_addr, frB_addr); |
| 8017 | assign( frD, unop(Iop_Est5FRSqrt, mkexpr(frB)) ); |
| 8018 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8019 | |
| 8020 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8021 | vex_printf("dis_fp_arith(ppc)(3F: opc2)\n"); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8022 | return False; |
| 8023 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 8024 | break; |
| 8025 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8026 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8027 | vex_printf("dis_fp_arith(ppc)(opc1)\n"); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8028 | return False; |
| 8029 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 8030 | |
| 8031 | putFReg( frD_addr, mkexpr(frD) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8032 | |
| 8033 | if (set_FPRF) { |
| 8034 | // XXX XXX XXX FIXME |
| 8035 | // set FPRF from frD |
| 8036 | } |
| 8037 | |
| 8038 | if (flag_rC && clear_CR1) { |
| 8039 | putCR321( 1, mkU8(0) ); |
| 8040 | putCR0( 1, mkU8(0) ); |
| 8041 | } |
| 8042 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8043 | return True; |
| 8044 | } |
| 8045 | |
| 8046 | |
| 8047 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8048 | /* |
| 8049 | Floating Point Mult-Add Instructions |
| 8050 | */ |
| 8051 | static Bool dis_fp_multadd ( UInt theInstr ) |
| 8052 | { |
| 8053 | /* A-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8054 | UChar opc1 = ifieldOPC(theInstr); |
| 8055 | UChar frD_addr = ifieldRegDS(theInstr); |
| 8056 | UChar frA_addr = ifieldRegA(theInstr); |
| 8057 | UChar frB_addr = ifieldRegB(theInstr); |
| 8058 | UChar frC_addr = ifieldRegC(theInstr); |
| 8059 | UChar opc2 = ifieldOPClo5(theInstr); |
| 8060 | UChar flag_rC = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8061 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8062 | IRTemp frD = newTemp(Ity_F64); |
| 8063 | IRTemp frA = newTemp(Ity_F64); |
| 8064 | IRTemp frB = newTemp(Ity_F64); |
| 8065 | IRTemp frC = newTemp(Ity_F64); |
| 8066 | IRTemp rmt = newTemp(Ity_I32); |
sewardj | 2bcdd65 | 2012-07-14 08:22:13 +0000 | [diff] [blame] | 8067 | IRTemp tmp = newTemp(Ity_F64); |
| 8068 | IRTemp sign_tmp = newTemp(Ity_I64); |
| 8069 | IRTemp nan_mask = newTemp(Ity_I32); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8070 | IRExpr* rm; |
| 8071 | |
| 8072 | /* By default, we will examine the results of the operation and set |
| 8073 | fpscr[FPRF] accordingly. */ |
| 8074 | Bool set_FPRF = True; |
| 8075 | |
| 8076 | /* By default, if flag_RC is set, we will clear cr1 after the |
| 8077 | operation. In reality we should set cr1 to indicate the |
| 8078 | exception status of the operation, but since we're not |
| 8079 | simulating exceptions, the exception status will appear to be |
| 8080 | zero. Hence cr1 should be cleared if this is a . form insn. */ |
| 8081 | Bool clear_CR1 = True; |
| 8082 | |
| 8083 | /* Bind the rounding mode expression to a temp; there's no |
| 8084 | point in creating gratuitous CSEs, as we know we'll need |
| 8085 | to use it twice. */ |
| 8086 | assign( rmt, get_IR_roundingmode() ); |
| 8087 | rm = mkexpr(rmt); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8088 | |
| 8089 | assign( frA, getFReg(frA_addr)); |
| 8090 | assign( frB, getFReg(frB_addr)); |
| 8091 | assign( frC, getFReg(frC_addr)); |
| 8092 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8093 | /* The rounding in this is all a bit dodgy. The idea is to only do |
| 8094 | one rounding. That clearly isn't achieveable without dedicated |
| 8095 | four-input IR primops, although in the single precision case we |
| 8096 | can sort-of simulate it by doing the inner multiply in double |
| 8097 | precision. |
| 8098 | |
| 8099 | In the negated cases, the negation happens after rounding. */ |
| 8100 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8101 | switch (opc1) { |
| 8102 | case 0x3B: |
| 8103 | switch (opc2) { |
| 8104 | case 0x1C: // fmsubs (Floating Mult-Subtr Single, PPC32 p412) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8105 | DIP("fmsubs%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8106 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 8107 | assign( frD, qop( Iop_MSubF64r32, rm, |
| 8108 | mkexpr(frA), mkexpr(frC), mkexpr(frB) )); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8109 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8110 | |
| 8111 | case 0x1D: // fmadds (Floating Mult-Add Single, PPC32 p409) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8112 | DIP("fmadds%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8113 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 8114 | assign( frD, qop( Iop_MAddF64r32, rm, |
| 8115 | mkexpr(frA), mkexpr(frC), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8116 | break; |
| 8117 | |
| 8118 | case 0x1E: // fnmsubs (Float Neg Mult-Subtr Single, PPC32 p420) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8119 | case 0x1F: // fnmadds (Floating Negative Multiply-Add Single, PPC32 p418) |
sewardj | 2bcdd65 | 2012-07-14 08:22:13 +0000 | [diff] [blame] | 8120 | |
| 8121 | if (opc2 == 0x1E) { |
| 8122 | DIP("fnmsubs%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
| 8123 | frD_addr, frA_addr, frC_addr, frB_addr); |
| 8124 | assign( tmp, qop( Iop_MSubF64r32, rm, |
| 8125 | mkexpr(frA), mkexpr(frC), mkexpr(frB) ) ); |
| 8126 | } else { |
| 8127 | DIP("fnmadds%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
| 8128 | frD_addr, frA_addr, frC_addr, frB_addr); |
| 8129 | assign( tmp, qop( Iop_MAddF64r32, rm, |
| 8130 | mkexpr(frA), mkexpr(frC), mkexpr(frB) ) ); |
| 8131 | } |
| 8132 | |
| 8133 | assign( nan_mask, Check_NaN( mkexpr( tmp ), |
| 8134 | mkU32( NANmaskSingle ) ) ); |
| 8135 | assign( sign_tmp, Complement_non_NaN( mkexpr( tmp ), |
| 8136 | mkexpr( nan_mask ) ) ); |
| 8137 | assign( frD, unop( Iop_ReinterpI64asF64, mkexpr( sign_tmp ) ) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8138 | break; |
| 8139 | |
| 8140 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8141 | vex_printf("dis_fp_multadd(ppc)(3B: opc2)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8142 | return False; |
| 8143 | } |
| 8144 | break; |
| 8145 | |
| 8146 | case 0x3F: |
| 8147 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8148 | case 0x1C: // fmsub (Float Mult-Sub (Dbl Precision), PPC32 p411) |
| 8149 | DIP("fmsub%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8150 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 8151 | assign( frD, qop( Iop_MSubF64, rm, |
| 8152 | mkexpr(frA), mkexpr(frC), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8153 | break; |
| 8154 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8155 | case 0x1D: // fmadd (Float Mult-Add (Dbl Precision), PPC32 p408) |
| 8156 | DIP("fmadd%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8157 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 8158 | assign( frD, qop( Iop_MAddF64, rm, |
| 8159 | mkexpr(frA), mkexpr(frC), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8160 | break; |
| 8161 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8162 | case 0x1E: // fnmsub (Float Neg Mult-Subtr (Dbl Precision), PPC32 p419) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8163 | case 0x1F: // fnmadd (Float Neg Mult-Add (Dbl Precision), PPC32 p417) |
sewardj | 2bcdd65 | 2012-07-14 08:22:13 +0000 | [diff] [blame] | 8164 | |
| 8165 | if (opc2 == 0x1E) { |
| 8166 | DIP("fnmsub%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
| 8167 | frD_addr, frA_addr, frC_addr, frB_addr); |
| 8168 | assign( tmp, qop( Iop_MSubF64, rm, |
| 8169 | mkexpr(frA), mkexpr(frC), mkexpr(frB) ) ); |
| 8170 | } else { |
| 8171 | DIP("fnmadd%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
| 8172 | frD_addr, frA_addr, frC_addr, frB_addr); |
| 8173 | assign( tmp, qop( Iop_MAddF64, rm, |
| 8174 | mkexpr(frA), mkexpr(frC), mkexpr(frB) )); |
| 8175 | } |
| 8176 | |
| 8177 | assign( nan_mask, Check_NaN( mkexpr( tmp ), |
| 8178 | mkU32( NANmaskDouble ) ) ); |
| 8179 | assign( sign_tmp, Complement_non_NaN( mkexpr( tmp ), |
| 8180 | mkexpr( nan_mask ) ) ); |
| 8181 | assign( frD, unop( Iop_ReinterpI64asF64, mkexpr( sign_tmp ) ) ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 8182 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8183 | |
| 8184 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8185 | vex_printf("dis_fp_multadd(ppc)(3F: opc2)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8186 | return False; |
| 8187 | } |
| 8188 | break; |
| 8189 | |
| 8190 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8191 | vex_printf("dis_fp_multadd(ppc)(opc1)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8192 | return False; |
| 8193 | } |
| 8194 | |
| 8195 | putFReg( frD_addr, mkexpr(frD) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8196 | |
| 8197 | if (set_FPRF) { |
| 8198 | // XXX XXX XXX FIXME |
| 8199 | // set FPRF from frD |
| 8200 | } |
| 8201 | |
| 8202 | if (flag_rC && clear_CR1) { |
| 8203 | putCR321( 1, mkU8(0) ); |
| 8204 | putCR0( 1, mkU8(0) ); |
| 8205 | } |
| 8206 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8207 | return True; |
| 8208 | } |
| 8209 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8210 | /* |
| 8211 | * fe_flag is set to 1 if any of the following conditions occurs: |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8212 | * - The floating-point operand in register FRB is a Zero, a |
| 8213 | * NaN, an Infinity, or a negative value. |
| 8214 | * - e_b is less than or equal to: -970 for double precision; -103 for single precision |
| 8215 | * Otherwise fe_flag is set to 0. |
| 8216 | * |
| 8217 | * fg_flag is set to 1 if either of the following conditions occurs. |
| 8218 | * - The floating-point operand in register FRB is a Zero, an |
| 8219 | * Infinity, or a denormalized value. |
| 8220 | * Otherwise fg_flag is set to 0. |
| 8221 | * |
| 8222 | */ |
| 8223 | static void do_fp_tsqrt(IRTemp frB_Int, Bool sp, IRTemp * fe_flag_tmp, IRTemp * fg_flag_tmp) |
| 8224 | { |
| 8225 | // The following temps are for holding intermediate results |
| 8226 | IRTemp e_b = newTemp(Ity_I32); |
| 8227 | IRExpr * fe_flag, * fg_flag; |
| 8228 | IRTemp frB_exp_shR = newTemp(Ity_I32); |
| 8229 | UInt bias = sp? 127 : 1023; |
| 8230 | IRExpr * frbNaN, * frbDenorm, * frBNeg; |
| 8231 | IRExpr * eb_LTE; |
| 8232 | IRTemp frbZero_tmp = newTemp(Ity_I1); |
| 8233 | IRTemp frbInf_tmp = newTemp(Ity_I1); |
| 8234 | *fe_flag_tmp = newTemp(Ity_I32); |
| 8235 | *fg_flag_tmp = newTemp(Ity_I32); |
| 8236 | assign( frB_exp_shR, fp_exp_part( frB_Int, sp ) ); |
| 8237 | assign(e_b, binop( Iop_Sub32, mkexpr(frB_exp_shR), mkU32( bias ) )); |
| 8238 | |
| 8239 | ////////////////// fe_flag tests BEGIN ////////////////////// |
| 8240 | /* We first do all tests that may result in setting fe_flag to '1'. |
| 8241 | * (NOTE: These tests are similar to those used for ftdiv. See do_fp_tdiv() |
| 8242 | * for details.) |
| 8243 | */ |
| 8244 | frbNaN = sp ? is_NaN_32(frB_Int) : is_NaN(frB_Int); |
| 8245 | assign( frbInf_tmp, is_Inf(frB_Int, sp) ); |
| 8246 | assign( frbZero_tmp, is_Zero(frB_Int, sp ) ); |
| 8247 | { |
| 8248 | // Test_value = -970 for double precision |
| 8249 | UInt test_value = sp ? 0xffffff99 : 0xfffffc36; |
| 8250 | eb_LTE = binop( Iop_CmpLE32S, mkexpr( e_b ), mkU32( test_value ) ); |
| 8251 | } |
| 8252 | frBNeg = binop( Iop_CmpEQ32, |
| 8253 | binop( Iop_Shr32, |
| 8254 | sp ? mkexpr( frB_Int ) : unop( Iop_64HIto32, mkexpr( frB_Int ) ), |
| 8255 | mkU8( 31 ) ), |
| 8256 | mkU32( 1 ) ); |
| 8257 | ////////////////// fe_flag tests END ////////////////////// |
| 8258 | |
| 8259 | ////////////////// fg_flag tests BEGIN ////////////////////// |
| 8260 | /* |
| 8261 | * The following tests were already performed above in the fe_flag |
| 8262 | * tests. So these conditions will result in both fe_ and fg_ flags |
| 8263 | * being set. |
| 8264 | * - Test if FRB is Zero |
| 8265 | * - Test if FRB is an Infinity |
| 8266 | */ |
| 8267 | |
| 8268 | /* |
| 8269 | * Test if FRB holds a denormalized value. A denormalized value is one where |
| 8270 | * the exp is 0 and the fraction is non-zero. |
| 8271 | */ |
| 8272 | if (sp) { |
| 8273 | IRTemp frac_part = newTemp(Ity_I32); |
| 8274 | assign( frac_part, binop( Iop_And32, mkexpr(frB_Int), mkU32(0x007fffff)) ); |
| 8275 | frbDenorm |
| 8276 | = mkAND1( binop( Iop_CmpEQ32, mkexpr( frB_exp_shR ), mkU32( 0 ) ), |
| 8277 | binop( Iop_CmpNE32, mkexpr( frac_part ), mkU32( 0 ) ) ); |
| 8278 | } else { |
| 8279 | IRExpr * hi32, * low32, * fraction_is_nonzero; |
| 8280 | IRTemp frac_part = newTemp(Ity_I64); |
| 8281 | |
| 8282 | assign( frac_part, FP_FRAC_PART(frB_Int) ); |
| 8283 | hi32 = unop( Iop_64HIto32, mkexpr( frac_part ) ); |
| 8284 | low32 = unop( Iop_64to32, mkexpr( frac_part ) ); |
| 8285 | fraction_is_nonzero = binop( Iop_CmpNE32, binop( Iop_Or32, low32, hi32 ), |
| 8286 | mkU32( 0 ) ); |
| 8287 | frbDenorm |
| 8288 | = mkAND1( binop( Iop_CmpEQ32, mkexpr( frB_exp_shR ), mkU32( 0 ) ), |
| 8289 | fraction_is_nonzero ); |
| 8290 | } |
| 8291 | ////////////////// fg_flag tests END ////////////////////// |
| 8292 | |
| 8293 | ///////////////////////// |
| 8294 | fe_flag = mkOR1( mkexpr( frbZero_tmp ), |
| 8295 | mkOR1( frbNaN, |
| 8296 | mkOR1( mkexpr( frbInf_tmp ), |
| 8297 | mkOR1( frBNeg, eb_LTE ) ) ) ); |
| 8298 | |
| 8299 | fe_flag = unop(Iop_1Uto32, fe_flag); |
| 8300 | |
| 8301 | fg_flag = mkOR1( mkexpr( frbZero_tmp ), |
| 8302 | mkOR1( mkexpr( frbInf_tmp ), frbDenorm ) ); |
| 8303 | fg_flag = unop(Iop_1Uto32, fg_flag); |
| 8304 | assign (*fg_flag_tmp, fg_flag); |
| 8305 | assign (*fe_flag_tmp, fe_flag); |
| 8306 | } |
| 8307 | /* |
| 8308 | * fe_flag is set to 1 if any of the following conditions occurs: |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8309 | * - The double-precision floating-point operand in register FRA is a NaN or an |
| 8310 | * Infinity. |
| 8311 | * - The double-precision floating-point operand in register FRB is a Zero, a |
| 8312 | * NaN, or an Infinity. |
| 8313 | * - e_b is less than or equal to -1022. |
| 8314 | * - e_b is greater than or equal to 1021. |
| 8315 | * - The double-precision floating-point operand in register FRA is not a zero |
| 8316 | * and the difference, e_a - e_b, is greater than or equal to 1023. |
| 8317 | * - The double-precision floating-point operand in register FRA is not a zero |
| 8318 | * and the difference, e_a - e_b, is less than or equal to -1021. |
| 8319 | * - The double-precision floating-point operand in register FRA is not a zero |
| 8320 | * and e_a is less than or equal to -970 |
| 8321 | * Otherwise fe_flag is set to 0. |
| 8322 | * |
| 8323 | * fg_flag is set to 1 if either of the following conditions occurs. |
| 8324 | * - The double-precision floating-point operand in register FRA is an Infinity. |
| 8325 | * - The double-precision floating-point operand in register FRB is a Zero, an |
| 8326 | * Infinity, or a denormalized value. |
| 8327 | * Otherwise fg_flag is set to 0. |
| 8328 | * |
| 8329 | */ |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8330 | static void _do_fp_tdiv(IRTemp frA_int, IRTemp frB_int, Bool sp, IRTemp * fe_flag_tmp, IRTemp * fg_flag_tmp) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8331 | { |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8332 | // The following temps are for holding intermediate results |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8333 | IRTemp e_a = newTemp(Ity_I32); |
| 8334 | IRTemp e_b = newTemp(Ity_I32); |
| 8335 | IRTemp frA_exp_shR = newTemp(Ity_I32); |
| 8336 | IRTemp frB_exp_shR = newTemp(Ity_I32); |
| 8337 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8338 | UInt bias = sp? 127 : 1023; |
| 8339 | *fe_flag_tmp = newTemp(Ity_I32); |
| 8340 | *fg_flag_tmp = newTemp(Ity_I32); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8341 | |
| 8342 | /* The following variables hold boolean results from tests |
| 8343 | * that are OR'ed together for setting the fe_ and fg_ flags. |
| 8344 | * For some cases, the booleans are used more than once, so |
| 8345 | * I make those IRTemp's instead of IRExpr's. |
| 8346 | */ |
| 8347 | IRExpr * fraNaN, * frbNaN, * frbDenorm; |
| 8348 | IRExpr * eb_LTE, * eb_GTE, * ea_eb_GTE, * ea_eb_LTE, * ea_LTE; |
| 8349 | IRTemp fraInf_tmp = newTemp(Ity_I1); |
| 8350 | IRTemp frbZero_tmp = newTemp(Ity_I1); |
| 8351 | IRTemp frbInf_tmp = newTemp(Ity_I1); |
| 8352 | IRTemp fraNotZero_tmp = newTemp(Ity_I1); |
| 8353 | |
| 8354 | /* The following are the flags that are set by OR'ing the results of |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8355 | * all the tests done for tdiv. These flags are the input to the specified CR. |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8356 | */ |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8357 | IRExpr * fe_flag, * fg_flag; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8358 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8359 | // Create temps that will be used throughout the following tests. |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8360 | assign( frA_exp_shR, fp_exp_part( frA_int, sp ) ); |
| 8361 | assign( frB_exp_shR, fp_exp_part( frB_int, sp ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8362 | /* Let e_[a|b] be the unbiased exponent: i.e. exp - 1023. */ |
| 8363 | assign(e_a, binop( Iop_Sub32, mkexpr(frA_exp_shR), mkU32( bias ) )); |
| 8364 | assign(e_b, binop( Iop_Sub32, mkexpr(frB_exp_shR), mkU32( bias ) )); |
| 8365 | |
| 8366 | |
| 8367 | ////////////////// fe_flag tests BEGIN ////////////////////// |
| 8368 | /* We first do all tests that may result in setting fe_flag to '1'. */ |
| 8369 | |
| 8370 | /* |
| 8371 | * Test if the double-precision floating-point operand in register FRA is |
| 8372 | * a NaN: |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8373 | */ |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8374 | fraNaN = sp ? is_NaN_32(frA_int) : is_NaN(frA_int); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8375 | /* |
| 8376 | * Test if the double-precision floating-point operand in register FRA is |
| 8377 | * an Infinity. |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8378 | */ |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8379 | assign(fraInf_tmp, is_Inf(frA_int, sp)); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8380 | |
| 8381 | /* |
| 8382 | * Test if the double-precision floating-point operand in register FRB is |
| 8383 | * a NaN: |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8384 | */ |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8385 | frbNaN = sp ? is_NaN_32(frB_int) : is_NaN(frB_int); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8386 | /* |
| 8387 | * Test if the double-precision floating-point operand in register FRB is |
| 8388 | * an Infinity. |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8389 | */ |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8390 | assign( frbInf_tmp, is_Inf(frB_int, sp) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8391 | /* |
| 8392 | * Test if the double-precision floating-point operand in register FRB is |
| 8393 | * a Zero. |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8394 | */ |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8395 | assign( frbZero_tmp, is_Zero(frB_int, sp) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8396 | |
| 8397 | /* |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8398 | * Test if e_b <= -1022 for double precision; |
| 8399 | * or e_b <= -126 for single precision |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8400 | */ |
| 8401 | { |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8402 | UInt test_value = sp ? 0xffffff82 : 0xfffffc02; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8403 | eb_LTE = binop(Iop_CmpLE32S, mkexpr(e_b), mkU32(test_value)); |
| 8404 | } |
| 8405 | |
| 8406 | /* |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8407 | * Test if e_b >= 1021 (i.e., 1021 < e_b) for double precision; |
| 8408 | * or e_b >= -125 (125 < e_b) for single precision |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8409 | */ |
| 8410 | { |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8411 | Int test_value = sp ? 125 : 1021; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8412 | eb_GTE = binop(Iop_CmpLT32S, mkU32(test_value), mkexpr(e_b)); |
| 8413 | } |
| 8414 | |
| 8415 | /* |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8416 | * Test if FRA != Zero and (e_a - e_b) >= bias |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8417 | */ |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8418 | assign( fraNotZero_tmp, unop( Iop_Not1, is_Zero( frA_int, sp ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8419 | ea_eb_GTE = mkAND1( mkexpr( fraNotZero_tmp ), |
| 8420 | binop( Iop_CmpLT32S, mkU32( bias ), |
| 8421 | binop( Iop_Sub32, mkexpr( e_a ), |
| 8422 | mkexpr( e_b ) ) ) ); |
| 8423 | |
| 8424 | /* |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8425 | * Test if FRA != Zero and (e_a - e_b) <= [-1021 (double precision) or -125 (single precision)] |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8426 | */ |
| 8427 | { |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8428 | UInt test_value = sp ? 0xffffff83 : 0xfffffc03; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8429 | |
| 8430 | ea_eb_LTE = mkAND1( mkexpr( fraNotZero_tmp ), |
| 8431 | binop( Iop_CmpLE32S, |
| 8432 | binop( Iop_Sub32, |
| 8433 | mkexpr( e_a ), |
| 8434 | mkexpr( e_b ) ), |
| 8435 | mkU32( test_value ) ) ); |
| 8436 | } |
| 8437 | |
| 8438 | /* |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8439 | * Test if FRA != Zero and e_a <= [-970 (double precision) or -103 (single precision)] |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8440 | */ |
| 8441 | { |
| 8442 | UInt test_value = 0xfffffc36; //Int test_value = -970; |
| 8443 | |
| 8444 | ea_LTE = mkAND1( mkexpr( fraNotZero_tmp ), binop( Iop_CmpLE32S, |
| 8445 | mkexpr( e_a ), |
| 8446 | mkU32( test_value ) ) ); |
| 8447 | } |
| 8448 | ////////////////// fe_flag tests END ////////////////////// |
| 8449 | |
| 8450 | ////////////////// fg_flag tests BEGIN ////////////////////// |
| 8451 | /* |
| 8452 | * The following tests were already performed above in the fe_flag |
| 8453 | * tests. So these conditions will result in both fe_ and fg_ flags |
| 8454 | * being set. |
| 8455 | * - Test if FRA is an Infinity |
| 8456 | * - Test if FRB ix Zero |
| 8457 | * - Test if FRB is an Infinity |
| 8458 | */ |
| 8459 | |
| 8460 | /* |
| 8461 | * Test if FRB holds a denormalized value. A denormalized value is one where |
| 8462 | * the exp is 0 and the fraction is non-zero. |
| 8463 | */ |
| 8464 | { |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8465 | IRExpr * fraction_is_nonzero; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8466 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8467 | if (sp) { |
| 8468 | fraction_is_nonzero = binop( Iop_CmpNE32, FP_FRAC_PART32(frB_int), |
| 8469 | mkU32( 0 ) ); |
| 8470 | } else { |
| 8471 | IRExpr * hi32, * low32; |
| 8472 | IRTemp frac_part = newTemp(Ity_I64); |
| 8473 | assign( frac_part, FP_FRAC_PART(frB_int) ); |
| 8474 | |
| 8475 | hi32 = unop( Iop_64HIto32, mkexpr( frac_part ) ); |
| 8476 | low32 = unop( Iop_64to32, mkexpr( frac_part ) ); |
| 8477 | fraction_is_nonzero = binop( Iop_CmpNE32, binop( Iop_Or32, low32, hi32 ), |
| 8478 | mkU32( 0 ) ); |
| 8479 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8480 | frbDenorm = mkAND1( binop( Iop_CmpEQ32, mkexpr( frB_exp_shR ), |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8481 | mkU32( 0x0 ) ), fraction_is_nonzero ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8482 | |
| 8483 | } |
| 8484 | ////////////////// fg_flag tests END ////////////////////// |
| 8485 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8486 | fe_flag |
| 8487 | = mkOR1( |
| 8488 | fraNaN, |
| 8489 | mkOR1( |
| 8490 | mkexpr( fraInf_tmp ), |
| 8491 | mkOR1( |
| 8492 | mkexpr( frbZero_tmp ), |
| 8493 | mkOR1( |
| 8494 | frbNaN, |
| 8495 | mkOR1( |
| 8496 | mkexpr( frbInf_tmp ), |
| 8497 | mkOR1( eb_LTE, |
| 8498 | mkOR1( eb_GTE, |
| 8499 | mkOR1( ea_eb_GTE, |
| 8500 | mkOR1( ea_eb_LTE, |
| 8501 | ea_LTE ) ) ) ) ) ) ) ) ); |
| 8502 | |
| 8503 | fe_flag = unop(Iop_1Uto32, fe_flag); |
| 8504 | |
| 8505 | fg_flag = mkOR1( mkexpr( fraInf_tmp ), mkOR1( mkexpr( frbZero_tmp ), |
| 8506 | mkOR1( mkexpr( frbInf_tmp ), |
| 8507 | frbDenorm ) ) ); |
| 8508 | fg_flag = unop(Iop_1Uto32, fg_flag); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8509 | assign(*fe_flag_tmp, fe_flag); |
| 8510 | assign(*fg_flag_tmp, fg_flag); |
| 8511 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8512 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8513 | /* See description for _do_fp_tdiv() above. */ |
| 8514 | static IRExpr * do_fp_tdiv(IRTemp frA_int, IRTemp frB_int) |
| 8515 | { |
| 8516 | IRTemp fe_flag, fg_flag; |
| 8517 | ///////////////////////// |
| 8518 | /* The CR field consists of fl_flag || fg_flag || fe_flag || 0b0 |
| 8519 | * where fl_flag == 1 on ppc64. |
| 8520 | */ |
| 8521 | IRExpr * fl_flag = unop(Iop_Not32, mkU32(0xFFFFFE)); |
| 8522 | fe_flag = fg_flag = IRTemp_INVALID; |
| 8523 | _do_fp_tdiv(frA_int, frB_int, False/*not single precision*/, &fe_flag, &fg_flag); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8524 | return binop( Iop_Or32, |
| 8525 | binop( Iop_Or32, |
| 8526 | binop( Iop_Shl32, fl_flag, mkU8( 3 ) ), |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8527 | binop( Iop_Shl32, mkexpr(fg_flag), mkU8( 2 ) ) ), |
| 8528 | binop( Iop_Shl32, mkexpr(fe_flag), mkU8( 1 ) ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8529 | } |
| 8530 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8531 | static Bool dis_fp_tests ( UInt theInstr ) |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8532 | { |
| 8533 | UChar opc1 = ifieldOPC(theInstr); |
| 8534 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8535 | UChar frB_addr = ifieldRegB(theInstr); |
| 8536 | UChar b0 = ifieldBIT0(theInstr); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8537 | UInt opc2 = ifieldOPClo10(theInstr); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8538 | IRTemp frB_I64 = newTemp(Ity_I64); |
| 8539 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8540 | if (opc1 != 0x3F || b0 != 0 ){ |
| 8541 | vex_printf("dis_fp_tests(ppc)(ftdiv)\n"); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8542 | return False; |
| 8543 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8544 | assign( frB_I64, unop( Iop_ReinterpF64asI64, getFReg( frB_addr ) ) ); |
| 8545 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8546 | switch (opc2) { |
| 8547 | case 0x080: // ftdiv |
| 8548 | { |
| 8549 | UChar frA_addr = ifieldRegA(theInstr); |
| 8550 | IRTemp frA_I64 = newTemp(Ity_I64); |
| 8551 | UChar b21to22 = toUChar( IFIELD( theInstr, 21, 2 ) ); |
| 8552 | if (b21to22 != 0 ) { |
| 8553 | vex_printf("dis_fp_tests(ppc)(ftdiv)\n"); |
| 8554 | return False; |
| 8555 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8556 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 8557 | assign( frA_I64, unop( Iop_ReinterpF64asI64, getFReg( frA_addr ) ) ); |
| 8558 | putGST_field( PPC_GST_CR, do_fp_tdiv(frA_I64, frB_I64), crfD ); |
| 8559 | |
| 8560 | DIP("ftdiv crf%d,fr%u,fr%u\n", crfD, frA_addr, frB_addr); |
| 8561 | break; |
| 8562 | } |
| 8563 | case 0x0A0: // ftsqrt |
| 8564 | { |
| 8565 | IRTemp flags = newTemp(Ity_I32); |
| 8566 | IRTemp fe_flag, fg_flag; |
| 8567 | fe_flag = fg_flag = IRTemp_INVALID; |
| 8568 | UChar b18to22 = toUChar( IFIELD( theInstr, 18, 5 ) ); |
| 8569 | if ( b18to22 != 0) { |
| 8570 | vex_printf("dis_fp_tests(ppc)(ftsqrt)\n"); |
| 8571 | return False; |
| 8572 | } |
| 8573 | DIP("ftsqrt crf%d,fr%u\n", crfD, frB_addr); |
| 8574 | do_fp_tsqrt(frB_I64, False /* not single precision*/, &fe_flag, &fg_flag); |
| 8575 | /* The CR field consists of fl_flag || fg_flag || fe_flag || 0b0 |
| 8576 | * where fl_flag == 1 on ppc64. |
| 8577 | */ |
| 8578 | assign( flags, |
| 8579 | binop( Iop_Or32, |
| 8580 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 8581 | binop( Iop_Shl32, mkexpr(fg_flag), mkU8( 2 ) ) ), |
| 8582 | binop( Iop_Shl32, mkexpr(fe_flag), mkU8( 1 ) ) ) ); |
| 8583 | putGST_field( PPC_GST_CR, mkexpr(flags), crfD ); |
| 8584 | break; |
| 8585 | } |
| 8586 | |
| 8587 | default: |
| 8588 | vex_printf("dis_fp_tests(ppc)(opc2)\n"); |
| 8589 | return False; |
| 8590 | |
| 8591 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8592 | return True; |
| 8593 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8594 | |
| 8595 | /* |
| 8596 | Floating Point Compare Instructions |
| 8597 | */ |
| 8598 | static Bool dis_fp_cmp ( UInt theInstr ) |
| 8599 | { |
| 8600 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8601 | UChar opc1 = ifieldOPC(theInstr); |
| 8602 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 8603 | UChar b21to22 = toUChar( IFIELD( theInstr, 21, 2 ) ); |
| 8604 | UChar frA_addr = ifieldRegA(theInstr); |
| 8605 | UChar frB_addr = ifieldRegB(theInstr); |
| 8606 | UInt opc2 = ifieldOPClo10(theInstr); |
| 8607 | UChar b0 = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8608 | |
| 8609 | IRTemp ccIR = newTemp(Ity_I32); |
| 8610 | IRTemp ccPPC32 = newTemp(Ity_I32); |
| 8611 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8612 | IRTemp frA = newTemp(Ity_F64); |
| 8613 | IRTemp frB = newTemp(Ity_F64); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8614 | |
| 8615 | if (opc1 != 0x3F || b21to22 != 0 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8616 | vex_printf("dis_fp_cmp(ppc)(instr)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8617 | return False; |
| 8618 | } |
| 8619 | |
| 8620 | assign( frA, getFReg(frA_addr)); |
| 8621 | assign( frB, getFReg(frB_addr)); |
| 8622 | |
| 8623 | assign( ccIR, binop(Iop_CmpF64, mkexpr(frA), mkexpr(frB)) ); |
| 8624 | |
| 8625 | /* Map compare result from IR to PPC32 */ |
| 8626 | /* |
| 8627 | FP cmp result | PPC | IR |
| 8628 | -------------------------- |
| 8629 | UN | 0x1 | 0x45 |
| 8630 | EQ | 0x2 | 0x40 |
| 8631 | GT | 0x4 | 0x00 |
| 8632 | LT | 0x8 | 0x01 |
| 8633 | */ |
| 8634 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8635 | // ccPPC32 = Shl(1, (~(ccIR>>5) & 2) |
| 8636 | // | ((ccIR ^ (ccIR>>6)) & 1) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8637 | assign( |
| 8638 | ccPPC32, |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8639 | binop( |
| 8640 | Iop_Shl32, |
| 8641 | mkU32(1), |
| 8642 | unop( |
| 8643 | Iop_32to8, |
| 8644 | binop( |
| 8645 | Iop_Or32, |
| 8646 | binop( |
| 8647 | Iop_And32, |
| 8648 | unop( |
| 8649 | Iop_Not32, |
| 8650 | binop(Iop_Shr32, mkexpr(ccIR), mkU8(5)) |
| 8651 | ), |
| 8652 | mkU32(2) |
| 8653 | ), |
| 8654 | binop( |
| 8655 | Iop_And32, |
| 8656 | binop( |
| 8657 | Iop_Xor32, |
| 8658 | mkexpr(ccIR), |
| 8659 | binop(Iop_Shr32, mkexpr(ccIR), mkU8(6)) |
| 8660 | ), |
| 8661 | mkU32(1) |
| 8662 | ) |
| 8663 | ) |
| 8664 | ) |
| 8665 | ) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8666 | ); |
| 8667 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8668 | putGST_field( PPC_GST_CR, mkexpr(ccPPC32), crfD ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8669 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 8670 | /* CAB: TODO?: Support writing cc to FPSCR->FPCC ? |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8671 | putGST_field( PPC_GST_FPSCR, mkexpr(ccPPC32), 4 ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 8672 | */ |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8673 | // XXX XXX XXX FIXME |
| 8674 | // Also write the result into FPRF (it's not entirely clear how) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8675 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 8676 | /* Note: Differences between fcmpu and fcmpo are only in exception |
| 8677 | flag settings, which aren't supported anyway. */ |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8678 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8679 | case 0x000: // fcmpu (Floating Compare Unordered, PPC32 p403) |
| 8680 | DIP("fcmpu crf%d,fr%u,fr%u\n", crfD, frA_addr, frB_addr); |
| 8681 | break; |
| 8682 | case 0x020: // fcmpo (Floating Compare Ordered, PPC32 p402) |
| 8683 | DIP("fcmpo crf%d,fr%u,fr%u\n", crfD, frA_addr, frB_addr); |
| 8684 | break; |
| 8685 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8686 | vex_printf("dis_fp_cmp(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8687 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8688 | } |
| 8689 | return True; |
| 8690 | } |
| 8691 | |
| 8692 | |
| 8693 | |
| 8694 | /* |
| 8695 | Floating Point Rounding/Conversion Instructions |
| 8696 | */ |
| 8697 | static Bool dis_fp_round ( UInt theInstr ) |
| 8698 | { |
| 8699 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8700 | UChar opc1 = ifieldOPC(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8701 | UChar b16to20 = ifieldRegA(theInstr); |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 8702 | UChar frD_addr = ifieldRegDS(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8703 | UChar frB_addr = ifieldRegB(theInstr); |
| 8704 | UInt opc2 = ifieldOPClo10(theInstr); |
| 8705 | UChar flag_rC = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8706 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8707 | IRTemp frD = newTemp(Ity_F64); |
| 8708 | IRTemp frB = newTemp(Ity_F64); |
| 8709 | IRTemp r_tmp32 = newTemp(Ity_I32); |
| 8710 | IRTemp r_tmp64 = newTemp(Ity_I64); |
| 8711 | IRExpr* rm = get_IR_roundingmode(); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8712 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8713 | /* By default, we will examine the results of the operation and set |
| 8714 | fpscr[FPRF] accordingly. */ |
| 8715 | Bool set_FPRF = True; |
| 8716 | |
| 8717 | /* By default, if flag_RC is set, we will clear cr1 after the |
| 8718 | operation. In reality we should set cr1 to indicate the |
| 8719 | exception status of the operation, but since we're not |
| 8720 | simulating exceptions, the exception status will appear to be |
| 8721 | zero. Hence cr1 should be cleared if this is a . form insn. */ |
| 8722 | Bool clear_CR1 = True; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8723 | if ((!(opc1 == 0x3F || opc1 == 0x3B)) || b16to20 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8724 | vex_printf("dis_fp_round(ppc)(instr)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8725 | return False; |
| 8726 | } |
| 8727 | |
| 8728 | assign( frB, getFReg(frB_addr)); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8729 | if (opc1 == 0x3B) { |
| 8730 | /* The fcfid[u]s instructions (from ISA 2.06) are a bit odd because |
| 8731 | * they're very similar to the other instructions handled here, but have |
| 8732 | * a different primary opcode. |
| 8733 | */ |
| 8734 | switch (opc2) { |
| 8735 | case 0x34E: // fcfids (Float convert from signed DWord to single precision) |
| 8736 | DIP("fcfids%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 8737 | assign( r_tmp64, unop( Iop_ReinterpF64asI64, mkexpr(frB)) ); |
| 8738 | assign( frD, binop( Iop_RoundF64toF32, rm, binop( Iop_I64StoF64, rm, |
| 8739 | mkexpr( r_tmp64 ) ) ) ); |
| 8740 | goto putFR; |
| 8741 | |
| 8742 | case 0x3Ce: // fcfidus (Float convert from unsigned DWord to single precision) |
| 8743 | DIP("fcfidus%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 8744 | assign( r_tmp64, unop( Iop_ReinterpF64asI64, mkexpr(frB)) ); |
sewardj | 95d6f3a | 2011-04-27 10:07:42 +0000 | [diff] [blame] | 8745 | assign( frD, unop( Iop_F32toF64, binop( Iop_I64UtoF32, rm, mkexpr( r_tmp64 ) ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8746 | goto putFR; |
| 8747 | } |
| 8748 | } |
| 8749 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8750 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8751 | switch (opc2) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8752 | case 0x00C: // frsp (Float Round to Single, PPC32 p423) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8753 | DIP("frsp%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8754 | assign( frD, binop( Iop_RoundF64toF32, rm, mkexpr(frB) )); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8755 | break; |
| 8756 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8757 | case 0x00E: // fctiw (Float Conv to Int, PPC32 p404) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8758 | DIP("fctiw%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 8759 | assign( r_tmp32, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8760 | binop(Iop_F64toI32S, rm, mkexpr(frB)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8761 | assign( frD, unop( Iop_ReinterpI64asF64, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 8762 | unop( Iop_32Uto64, mkexpr(r_tmp32)))); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8763 | /* FPRF is undefined after fctiw. Leave unchanged. */ |
| 8764 | set_FPRF = False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8765 | break; |
| 8766 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8767 | case 0x00F: // fctiwz (Float Conv to Int, Round to Zero, PPC32 p405) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8768 | DIP("fctiwz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8769 | assign( r_tmp32, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8770 | binop(Iop_F64toI32S, mkU32(Irrm_ZERO), mkexpr(frB) )); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8771 | assign( frD, unop( Iop_ReinterpI64asF64, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 8772 | unop( Iop_32Uto64, mkexpr(r_tmp32)))); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8773 | /* FPRF is undefined after fctiwz. Leave unchanged. */ |
| 8774 | set_FPRF = False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8775 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8776 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8777 | case 0x08F: case 0x08E: // fctiwu[z] |
| 8778 | DIP("fctiwu%s%s fr%u,fr%u\n", opc2 == 0x08F ? "z" : "", |
| 8779 | flag_rC ? ".":"", frD_addr, frB_addr); |
| 8780 | assign( r_tmp32, |
| 8781 | binop( Iop_F64toI32U, |
| 8782 | opc2 == 0x08F ? mkU32( Irrm_ZERO ) : rm, |
| 8783 | mkexpr( frB ) ) ); |
| 8784 | assign( frD, unop( Iop_ReinterpI64asF64, |
| 8785 | unop( Iop_32Uto64, mkexpr(r_tmp32)))); |
| 8786 | /* FPRF is undefined after fctiwz. Leave unchanged. */ |
| 8787 | set_FPRF = False; |
| 8788 | break; |
| 8789 | |
| 8790 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8791 | case 0x32E: // fctid (Float Conv to Int DWord, PPC64 p437) |
| 8792 | DIP("fctid%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 8793 | assign( r_tmp64, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8794 | binop(Iop_F64toI64S, rm, mkexpr(frB)) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 8795 | assign( frD, unop( Iop_ReinterpI64asF64, mkexpr(r_tmp64)) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8796 | /* FPRF is undefined after fctid. Leave unchanged. */ |
| 8797 | set_FPRF = False; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 8798 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8799 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8800 | case 0x32F: // fctidz (Float Conv to Int DWord, Round to Zero, PPC64 p437) |
| 8801 | DIP("fctidz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8802 | assign( r_tmp64, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8803 | binop(Iop_F64toI64S, mkU32(Irrm_ZERO), mkexpr(frB)) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 8804 | assign( frD, unop( Iop_ReinterpI64asF64, mkexpr(r_tmp64)) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8805 | /* FPRF is undefined after fctidz. Leave unchanged. */ |
| 8806 | set_FPRF = False; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 8807 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8808 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 8809 | case 0x3AE: case 0x3AF: // fctidu[z] (Float Conv to Int DWord Unsigned [Round to Zero]) |
| 8810 | { |
| 8811 | DIP("fctidu%s%s fr%u,fr%u\n", opc2 == 0x3AE ? "" : "z", |
| 8812 | flag_rC ? ".":"", frD_addr, frB_addr); |
| 8813 | assign( r_tmp64, |
| 8814 | binop(Iop_F64toI64U, opc2 == 0x3AE ? rm : mkU32(Irrm_ZERO), mkexpr(frB)) ); |
| 8815 | assign( frD, unop( Iop_ReinterpI64asF64, mkexpr(r_tmp64)) ); |
| 8816 | /* FPRF is undefined after fctidz. Leave unchanged. */ |
| 8817 | set_FPRF = False; |
| 8818 | break; |
| 8819 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8820 | case 0x34E: // fcfid (Float Conv from Int DWord, PPC64 p434) |
| 8821 | DIP("fcfid%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 8822 | assign( r_tmp64, unop( Iop_ReinterpF64asI64, mkexpr(frB)) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8823 | assign( frD, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8824 | binop(Iop_I64StoF64, rm, mkexpr(r_tmp64)) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 8825 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8826 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8827 | case 0x3CE: // fcfidu (Float convert from unsigned DWord) |
| 8828 | DIP("fcfidu%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 8829 | assign( r_tmp64, unop( Iop_ReinterpF64asI64, mkexpr(frB)) ); |
| 8830 | assign( frD, binop( Iop_I64UtoF64, rm, mkexpr( r_tmp64 ) ) ); |
| 8831 | break; |
| 8832 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 8833 | case 0x188: case 0x1A8: case 0x1C8: case 0x1E8: // frin, friz, frip, frim |
| 8834 | switch(opc2) { |
| 8835 | case 0x188: // frin (Floating Round to Integer Nearest) |
| 8836 | DIP("frin%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 8837 | assign( r_tmp64, |
| 8838 | binop(Iop_F64toI64S, mkU32(Irrm_NEAREST), mkexpr(frB)) ); |
| 8839 | break; |
| 8840 | case 0x1A8: // friz (Floating Round to Integer Toward Zero) |
| 8841 | DIP("friz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 8842 | assign( r_tmp64, |
| 8843 | binop(Iop_F64toI64S, mkU32(Irrm_ZERO), mkexpr(frB)) ); |
| 8844 | break; |
| 8845 | case 0x1C8: // frip (Floating Round to Integer Plus) |
| 8846 | DIP("frip%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 8847 | assign( r_tmp64, |
| 8848 | binop(Iop_F64toI64S, mkU32(Irrm_PosINF), mkexpr(frB)) ); |
| 8849 | break; |
| 8850 | case 0x1E8: // frim (Floating Round to Integer Minus) |
| 8851 | DIP("frim%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 8852 | assign( r_tmp64, |
| 8853 | binop(Iop_F64toI64S, mkU32(Irrm_NegINF), mkexpr(frB)) ); |
| 8854 | break; |
| 8855 | } |
| 8856 | |
| 8857 | /* don't use the rounded integer if frB is outside -9e18..9e18 */ |
| 8858 | /* F64 has only log10(2**52) significant digits anyway */ |
| 8859 | /* need to preserve sign of zero */ |
| 8860 | /* frD = (fabs(frB) > 9e18) ? frB : |
| 8861 | (sign(frB)) ? -fabs((double)r_tmp64) : (double)r_tmp64 */ |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 8862 | assign(frD, IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 8863 | binop(Iop_CmpNE8, |
| 8864 | unop(Iop_32to8, |
| 8865 | binop(Iop_CmpF64, |
| 8866 | IRExpr_Const(IRConst_F64(9e18)), |
| 8867 | unop(Iop_AbsF64, mkexpr(frB)))), |
| 8868 | mkU8(0)), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 8869 | mkexpr(frB), |
| 8870 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 8871 | binop(Iop_CmpNE32, |
| 8872 | binop(Iop_Shr32, |
| 8873 | unop(Iop_64HIto32, |
| 8874 | unop(Iop_ReinterpF64asI64, |
| 8875 | mkexpr(frB))), |
| 8876 | mkU8(31)), |
| 8877 | mkU32(0)), |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 8878 | unop(Iop_NegF64, |
| 8879 | unop( Iop_AbsF64, |
| 8880 | binop(Iop_I64StoF64, mkU32(0), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 8881 | mkexpr(r_tmp64)) )), |
| 8882 | binop(Iop_I64StoF64, mkU32(0), mkexpr(r_tmp64) ) |
| 8883 | ) |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 8884 | )); |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 8885 | break; |
| 8886 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8887 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8888 | vex_printf("dis_fp_round(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8889 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8890 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 8891 | putFR: |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8892 | putFReg( frD_addr, mkexpr(frD) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 8893 | |
| 8894 | if (set_FPRF) { |
| 8895 | // XXX XXX XXX FIXME |
| 8896 | // set FPRF from frD |
| 8897 | } |
| 8898 | |
| 8899 | if (flag_rC && clear_CR1) { |
| 8900 | putCR321( 1, mkU8(0) ); |
| 8901 | putCR0( 1, mkU8(0) ); |
| 8902 | } |
| 8903 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8904 | return True; |
| 8905 | } |
| 8906 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 8907 | /* |
| 8908 | Floating Point Pair Instructions |
| 8909 | */ |
| 8910 | static Bool dis_fp_pair ( UInt theInstr ) |
| 8911 | { |
| 8912 | /* X-Form/DS-Form */ |
| 8913 | UChar opc1 = ifieldOPC(theInstr); |
| 8914 | UChar frT_hi_addr = ifieldRegDS(theInstr); |
| 8915 | UChar frT_lo_addr = frT_hi_addr + 1; |
| 8916 | UChar rA_addr = ifieldRegA(theInstr); |
| 8917 | UChar rB_addr = ifieldRegB(theInstr); |
| 8918 | UInt uimm16 = ifieldUIMM16(theInstr); |
| 8919 | Int simm16 = extend_s_16to32(uimm16); |
| 8920 | UInt opc2 = ifieldOPClo10(theInstr); |
| 8921 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 8922 | IRTemp EA_hi = newTemp(ty); |
| 8923 | IRTemp EA_lo = newTemp(ty); |
| 8924 | IRTemp frT_hi = newTemp(Ity_F64); |
| 8925 | IRTemp frT_lo = newTemp(Ity_F64); |
| 8926 | UChar b0 = ifieldBIT0(theInstr); |
| 8927 | Bool is_load = 0; |
| 8928 | |
| 8929 | if ((frT_hi_addr %2) != 0) { |
| 8930 | vex_printf("dis_fp_pair(ppc) : odd frT register\n"); |
| 8931 | return False; |
| 8932 | } |
| 8933 | |
| 8934 | switch (opc1) { |
| 8935 | case 0x1F: // register offset |
| 8936 | switch(opc2) { |
| 8937 | case 0x317: // lfdpx (FP Load Double Pair X-form, ISA 2.05 p125) |
| 8938 | DIP("ldpx fr%u,r%u,r%u\n", frT_hi_addr, rA_addr, rB_addr); |
| 8939 | is_load = 1; |
| 8940 | break; |
| 8941 | case 0x397: // stfdpx (FP STORE Double Pair X-form, ISA 2.05 p125) |
| 8942 | DIP("stdpx fr%u,r%u,r%u\n", frT_hi_addr, rA_addr, rB_addr); |
| 8943 | break; |
| 8944 | default: |
| 8945 | vex_printf("dis_fp_pair(ppc) : X-form wrong opc2\n"); |
| 8946 | return False; |
| 8947 | } |
| 8948 | |
| 8949 | if (b0 != 0) { |
| 8950 | vex_printf("dis_fp_pair(ppc)(0x1F,b0)\n"); |
| 8951 | return False; |
| 8952 | } |
| 8953 | assign( EA_hi, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
| 8954 | break; |
| 8955 | case 0x39: // lfdp (FP Load Double Pair DS-form, ISA 2.05 p125) |
| 8956 | DIP("lfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr); |
| 8957 | assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 8958 | is_load = 1; |
| 8959 | break; |
| 8960 | case 0x3d: // stfdp (FP Store Double Pair DS-form, ISA 2.05 p125) |
| 8961 | DIP("stfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr); |
| 8962 | assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 8963 | break; |
| 8964 | default: // immediate offset |
| 8965 | vex_printf("dis_fp_pair(ppc)(instr)\n"); |
| 8966 | return False; |
| 8967 | } |
| 8968 | |
| 8969 | if (mode64) |
| 8970 | assign( EA_lo, binop(Iop_Add64, mkexpr(EA_hi), mkU64(8)) ); |
| 8971 | else |
| 8972 | assign( EA_lo, binop(Iop_Add32, mkexpr(EA_hi), mkU32(8)) ); |
| 8973 | |
| 8974 | assign( frT_hi, getFReg(frT_hi_addr) ); |
| 8975 | assign( frT_lo, getFReg(frT_lo_addr) ); |
| 8976 | |
| 8977 | if (is_load) { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 8978 | putFReg( frT_hi_addr, load(Ity_F64, mkexpr(EA_hi)) ); |
| 8979 | putFReg( frT_lo_addr, load(Ity_F64, mkexpr(EA_lo)) ); |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 8980 | } else { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 8981 | store( mkexpr(EA_hi), mkexpr(frT_hi) ); |
| 8982 | store( mkexpr(EA_lo), mkexpr(frT_lo) ); |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 8983 | } |
| 8984 | |
| 8985 | return True; |
| 8986 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8987 | |
| 8988 | |
| 8989 | /* |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 8990 | Floating Point Merge Instructions |
| 8991 | */ |
| 8992 | static Bool dis_fp_merge ( UInt theInstr ) |
| 8993 | { |
| 8994 | /* X-Form */ |
| 8995 | UInt opc2 = ifieldOPClo10(theInstr); |
| 8996 | UChar frD_addr = ifieldRegDS(theInstr); |
| 8997 | UChar frA_addr = ifieldRegA(theInstr); |
| 8998 | UChar frB_addr = ifieldRegB(theInstr); |
| 8999 | |
| 9000 | IRTemp frD = newTemp(Ity_F64); |
| 9001 | IRTemp frA = newTemp(Ity_F64); |
| 9002 | IRTemp frB = newTemp(Ity_F64); |
| 9003 | |
| 9004 | assign( frA, getFReg(frA_addr)); |
| 9005 | assign( frB, getFReg(frB_addr)); |
| 9006 | |
| 9007 | switch (opc2) { |
| 9008 | case 0x3c6: // fmrgew floating merge even word |
| 9009 | DIP("fmrgew fr%u,fr%u,fr%u\n", frD_addr, frA_addr, frB_addr); |
| 9010 | |
| 9011 | assign( frD, unop( Iop_ReinterpI64asF64, |
| 9012 | binop( Iop_32HLto64, |
| 9013 | unop( Iop_64HIto32, |
| 9014 | unop( Iop_ReinterpF64asI64, |
| 9015 | mkexpr(frA) ) ), |
| 9016 | unop( Iop_64HIto32, |
| 9017 | unop( Iop_ReinterpF64asI64, |
| 9018 | mkexpr(frB) ) ) ) ) ); |
| 9019 | break; |
| 9020 | |
| 9021 | case 0x346: // fmrgow floating merge odd word |
| 9022 | DIP("fmrgow fr%u,fr%u,fr%u\n", frD_addr, frA_addr, frB_addr); |
| 9023 | |
| 9024 | assign( frD, unop( Iop_ReinterpI64asF64, |
| 9025 | binop( Iop_32HLto64, |
| 9026 | unop( Iop_64to32, |
| 9027 | unop( Iop_ReinterpF64asI64, |
| 9028 | mkexpr(frA) ) ), |
| 9029 | unop( Iop_64to32, |
| 9030 | unop( Iop_ReinterpF64asI64, |
| 9031 | mkexpr(frB) ) ) ) ) ); |
| 9032 | break; |
| 9033 | |
| 9034 | default: |
| 9035 | vex_printf("dis_fp_merge(ppc)(opc2)\n"); |
| 9036 | return False; |
| 9037 | } |
| 9038 | |
| 9039 | putFReg( frD_addr, mkexpr(frD) ); |
| 9040 | return True; |
| 9041 | } |
| 9042 | |
| 9043 | /* |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9044 | Floating Point Move Instructions |
| 9045 | */ |
| 9046 | static Bool dis_fp_move ( UInt theInstr ) |
| 9047 | { |
| 9048 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9049 | UChar opc1 = ifieldOPC(theInstr); |
| 9050 | UChar frD_addr = ifieldRegDS(theInstr); |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 9051 | UChar frA_addr = ifieldRegA(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9052 | UChar frB_addr = ifieldRegB(theInstr); |
| 9053 | UInt opc2 = ifieldOPClo10(theInstr); |
| 9054 | UChar flag_rC = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9055 | |
| 9056 | IRTemp frD = newTemp(Ity_F64); |
| 9057 | IRTemp frB = newTemp(Ity_F64); |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 9058 | IRTemp itmpB = newTemp(Ity_F64); |
| 9059 | IRTemp frA; |
| 9060 | IRTemp signA; |
| 9061 | IRTemp hiD; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9062 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 9063 | if (opc1 != 0x3F || (frA_addr != 0 && opc2 != 0x008)) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9064 | vex_printf("dis_fp_move(ppc)(instr)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9065 | return False; |
| 9066 | } |
| 9067 | |
| 9068 | assign( frB, getFReg(frB_addr)); |
| 9069 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9070 | switch (opc2) { |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 9071 | case 0x008: // fcpsgn (Floating Copy Sign, ISA_V2.05 p126) |
| 9072 | DIP("fcpsgn%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frA_addr, |
| 9073 | frB_addr); |
| 9074 | signA = newTemp(Ity_I32); |
| 9075 | hiD = newTemp(Ity_I32); |
| 9076 | itmpB = newTemp(Ity_I64); |
| 9077 | frA = newTemp(Ity_F64); |
| 9078 | assign( frA, getFReg(frA_addr) ); |
| 9079 | |
| 9080 | /* get A's sign bit */ |
| 9081 | assign(signA, binop(Iop_And32, |
| 9082 | unop(Iop_64HIto32, unop(Iop_ReinterpF64asI64, |
| 9083 | mkexpr(frA))), |
| 9084 | mkU32(0x80000000)) ); |
| 9085 | |
| 9086 | assign( itmpB, unop(Iop_ReinterpF64asI64, mkexpr(frB)) ); |
| 9087 | |
| 9088 | /* mask off B's sign bit and or in A's sign bit */ |
| 9089 | assign(hiD, binop(Iop_Or32, |
| 9090 | binop(Iop_And32, |
| 9091 | unop(Iop_64HIto32, |
| 9092 | mkexpr(itmpB)), /* frB's high 32 bits */ |
| 9093 | mkU32(0x7fffffff)), |
| 9094 | mkexpr(signA)) ); |
| 9095 | |
| 9096 | /* combine hiD/loB into frD */ |
| 9097 | assign( frD, unop(Iop_ReinterpI64asF64, |
| 9098 | binop(Iop_32HLto64, |
| 9099 | mkexpr(hiD), |
| 9100 | unop(Iop_64to32, |
| 9101 | mkexpr(itmpB)))) ); /* frB's low 32 bits */ |
| 9102 | break; |
| 9103 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9104 | case 0x028: // fneg (Floating Negate, PPC32 p416) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9105 | DIP("fneg%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9106 | assign( frD, unop( Iop_NegF64, mkexpr(frB) )); |
| 9107 | break; |
| 9108 | |
| 9109 | case 0x048: // fmr (Floating Move Register, PPC32 p410) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9110 | DIP("fmr%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9111 | assign( frD, mkexpr(frB) ); |
| 9112 | break; |
| 9113 | |
| 9114 | case 0x088: // fnabs (Floating Negative Absolute Value, PPC32 p415) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9115 | DIP("fnabs%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9116 | assign( frD, unop( Iop_NegF64, unop( Iop_AbsF64, mkexpr(frB) ))); |
| 9117 | break; |
| 9118 | |
| 9119 | case 0x108: // fabs (Floating Absolute Value, PPC32 p399) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9120 | DIP("fabs%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9121 | assign( frD, unop( Iop_AbsF64, mkexpr(frB) )); |
| 9122 | break; |
| 9123 | |
| 9124 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9125 | vex_printf("dis_fp_move(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9126 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9127 | } |
| 9128 | |
| 9129 | putFReg( frD_addr, mkexpr(frD) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 9130 | |
| 9131 | /* None of these change FPRF. cr1 is set in the usual way though, |
| 9132 | if flag_rC is set. */ |
| 9133 | |
| 9134 | if (flag_rC) { |
| 9135 | putCR321( 1, mkU8(0) ); |
| 9136 | putCR0( 1, mkU8(0) ); |
| 9137 | } |
| 9138 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9139 | return True; |
| 9140 | } |
| 9141 | |
| 9142 | |
| 9143 | |
| 9144 | /* |
| 9145 | Floating Point Status/Control Register Instructions |
| 9146 | */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9147 | static Bool dis_fp_scr ( UInt theInstr, Bool GX_level ) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9148 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9149 | /* Many forms - see each switch case */ |
| 9150 | UChar opc1 = ifieldOPC(theInstr); |
| 9151 | UInt opc2 = ifieldOPClo10(theInstr); |
| 9152 | UChar flag_rC = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9153 | |
| 9154 | if (opc1 != 0x3F) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9155 | vex_printf("dis_fp_scr(ppc)(instr)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9156 | return False; |
| 9157 | } |
| 9158 | |
| 9159 | switch (opc2) { |
cerion | 3ea49ee | 2006-01-04 10:53:00 +0000 | [diff] [blame] | 9160 | case 0x026: { // mtfsb1 (Move to FPSCR Bit 1, PPC32 p479) |
| 9161 | // Bit crbD of the FPSCR is set. |
| 9162 | UChar crbD = ifieldRegDS(theInstr); |
| 9163 | UInt b11to20 = IFIELD(theInstr, 11, 10); |
| 9164 | |
| 9165 | if (b11to20 != 0) { |
| 9166 | vex_printf("dis_fp_scr(ppc)(instr,mtfsb1)\n"); |
| 9167 | return False; |
| 9168 | } |
| 9169 | DIP("mtfsb1%s crb%d \n", flag_rC ? ".":"", crbD); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9170 | putGST_masked( PPC_GST_FPSCR, mkU64( 1 <<( 31 - crbD ) ), |
| 9171 | 1ULL << ( 31 - crbD ) ); |
cerion | 3ea49ee | 2006-01-04 10:53:00 +0000 | [diff] [blame] | 9172 | break; |
| 9173 | } |
| 9174 | |
sewardj | 496b88f | 2006-10-04 17:46:11 +0000 | [diff] [blame] | 9175 | case 0x040: { // mcrfs (Move to Condition Register from FPSCR, PPC32 p465) |
| 9176 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 9177 | UChar b21to22 = toUChar( IFIELD( theInstr, 21, 2 ) ); |
| 9178 | UChar crfS = toUChar( IFIELD( theInstr, 18, 3 ) ); |
| 9179 | UChar b11to17 = toUChar( IFIELD( theInstr, 11, 7 ) ); |
| 9180 | IRTemp tmp = newTemp(Ity_I32); |
| 9181 | IRExpr* fpscr_all; |
| 9182 | if (b21to22 != 0 || b11to17 != 0 || flag_rC != 0) { |
| 9183 | vex_printf("dis_fp_scr(ppc)(instr,mcrfs)\n"); |
| 9184 | return False; |
| 9185 | } |
| 9186 | DIP("mcrfs crf%d,crf%d\n", crfD, crfS); |
| 9187 | vassert(crfD < 8); |
| 9188 | vassert(crfS < 8); |
| 9189 | fpscr_all = getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN ); |
| 9190 | assign( tmp, binop(Iop_And32, |
| 9191 | binop(Iop_Shr32,fpscr_all,mkU8(4 * (7-crfS))), |
| 9192 | mkU32(0xF)) ); |
| 9193 | putGST_field( PPC_GST_CR, mkexpr(tmp), crfD ); |
| 9194 | break; |
| 9195 | } |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 9196 | |
| 9197 | case 0x046: { // mtfsb0 (Move to FPSCR Bit 0, PPC32 p478) |
| 9198 | // Bit crbD of the FPSCR is cleared. |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9199 | UChar crbD = ifieldRegDS(theInstr); |
| 9200 | UInt b11to20 = IFIELD(theInstr, 11, 10); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 9201 | |
| 9202 | if (b11to20 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9203 | vex_printf("dis_fp_scr(ppc)(instr,mtfsb0)\n"); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 9204 | return False; |
| 9205 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9206 | DIP("mtfsb0%s crb%d\n", flag_rC ? ".":"", crbD); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9207 | putGST_masked( PPC_GST_FPSCR, mkU64( 0 ), 1ULL << ( 31 - crbD ) ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 9208 | break; |
| 9209 | } |
| 9210 | |
| 9211 | case 0x086: { // mtfsfi (Move to FPSCR Field Immediate, PPC32 p481) |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9212 | UInt crfD = IFIELD( theInstr, 23, 3 ); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9213 | UChar b16to22 = toUChar( IFIELD( theInstr, 16, 7 ) ); |
| 9214 | UChar IMM = toUChar( IFIELD( theInstr, 12, 4 ) ); |
| 9215 | UChar b11 = toUChar( IFIELD( theInstr, 11, 1 ) ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9216 | UChar Wbit; |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 9217 | |
| 9218 | if (b16to22 != 0 || b11 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9219 | vex_printf("dis_fp_scr(ppc)(instr,mtfsfi)\n"); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 9220 | return False; |
| 9221 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9222 | DIP("mtfsfi%s crf%d,%d\n", flag_rC ? ".":"", crfD, IMM); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9223 | if (GX_level) { |
| 9224 | /* This implies that Decimal Floating Point is supported, and the |
| 9225 | * FPSCR must be managed as a 64-bit register. |
| 9226 | */ |
| 9227 | Wbit = toUChar( IFIELD(theInstr, 16, 1) ); |
| 9228 | } else { |
| 9229 | Wbit = 0; |
| 9230 | } |
| 9231 | crfD = crfD + (8 * (1 - Wbit) ); |
| 9232 | putGST_field( PPC_GST_FPSCR, mkU32( IMM ), crfD ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 9233 | break; |
| 9234 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9235 | |
| 9236 | case 0x247: { // mffs (Move from FPSCR, PPC32 p468) |
sewardj | 496b88f | 2006-10-04 17:46:11 +0000 | [diff] [blame] | 9237 | UChar frD_addr = ifieldRegDS(theInstr); |
| 9238 | UInt b11to20 = IFIELD(theInstr, 11, 10); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9239 | IRExpr* fpscr_lower = getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN ); |
| 9240 | IRExpr* fpscr_upper = getGST_masked_upper( PPC_GST_FPSCR, |
| 9241 | MASK_FPSCR_DRN ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9242 | |
| 9243 | if (b11to20 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9244 | vex_printf("dis_fp_scr(ppc)(instr,mffs)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9245 | return False; |
| 9246 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9247 | DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr); |
| 9248 | putFReg( frD_addr, |
| 9249 | unop( Iop_ReinterpI64asF64, |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9250 | binop( Iop_32HLto64, fpscr_upper, fpscr_lower ) ) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9251 | break; |
| 9252 | } |
| 9253 | |
| 9254 | case 0x2C7: { // mtfsf (Move to FPSCR Fields, PPC32 p480) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9255 | UChar b25 = toUChar( IFIELD(theInstr, 25, 1) ); |
| 9256 | UChar FM = toUChar( IFIELD(theInstr, 17, 8) ); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9257 | UChar frB_addr = ifieldRegB(theInstr); |
| 9258 | IRTemp frB = newTemp(Ity_F64); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9259 | IRTemp rB_64 = newTemp( Ity_I64 ); |
| 9260 | Int i; |
| 9261 | ULong mask; |
| 9262 | UChar Wbit; |
| 9263 | #define BFP_MASK_SEED 0x3000000000000000ULL |
| 9264 | #define DFP_MASK_SEED 0x7000000000000000ULL |
| 9265 | |
| 9266 | if (GX_level) { |
| 9267 | /* This implies that Decimal Floating Point is supported, and the |
| 9268 | * FPSCR must be managed as a 64-bit register. |
| 9269 | */ |
| 9270 | Wbit = toUChar( IFIELD(theInstr, 16, 1) ); |
| 9271 | } else { |
| 9272 | Wbit = 0; |
| 9273 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9274 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 9275 | if (b25 == 1) { |
| 9276 | /* new 64 bit move variant for power 6. If L field (bit 25) is |
| 9277 | * a one do a full 64 bit move. Note, the FPSCR is not really |
| 9278 | * properly modeled. This instruciton only changes the value of |
| 9279 | * the rounding mode. The HW exception bits do not get set in |
| 9280 | * the simulator. 1/12/09 |
| 9281 | */ |
| 9282 | DIP("mtfsf%s %d,fr%u (L=1)\n", flag_rC ? ".":"", FM, frB_addr); |
| 9283 | mask = 0xFF; |
| 9284 | |
| 9285 | } else { |
| 9286 | DIP("mtfsf%s %d,fr%u\n", flag_rC ? ".":"", FM, frB_addr); |
| 9287 | // Build 32bit mask from FM: |
| 9288 | mask = 0; |
| 9289 | for (i=0; i<8; i++) { |
| 9290 | if ((FM & (1<<(7-i))) == 1) { |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9291 | /* FPSCR field k is set to the contents of the corresponding |
| 9292 | * field of register FRB, where k = i+8x(1-W). In the Power |
| 9293 | * ISA, register field numbering is from left to right, so field |
| 9294 | * 15 is the least significant field in a 64-bit register. To |
| 9295 | * generate the mask, we set all the appropriate rounding mode |
| 9296 | * bits in the highest order nibble (field 0) and shift right |
| 9297 | * 'k x nibble length'. |
| 9298 | */ |
| 9299 | if (Wbit) |
| 9300 | mask |= DFP_MASK_SEED >> ( 4 * ( i + 8 * ( 1 - Wbit ) ) ); |
| 9301 | else |
| 9302 | mask |= BFP_MASK_SEED >> ( 4 * ( i + 8 * ( 1 - Wbit ) ) ); |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 9303 | } |
| 9304 | } |
| 9305 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9306 | assign( frB, getFReg(frB_addr)); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9307 | assign( rB_64, unop( Iop_ReinterpF64asI64, mkexpr( frB ) ) ); |
| 9308 | putGST_masked( PPC_GST_FPSCR, mkexpr( rB_64 ), mask ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9309 | break; |
| 9310 | } |
| 9311 | |
| 9312 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9313 | vex_printf("dis_fp_scr(ppc)(opc2)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9314 | return False; |
| 9315 | } |
| 9316 | return True; |
| 9317 | } |
| 9318 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9319 | /*------------------------------------------------------------*/ |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9320 | /*--- Decimal Floating Point (DFP) Helper functions ---*/ |
| 9321 | /*------------------------------------------------------------*/ |
| 9322 | #define DFP_LONG 1 |
| 9323 | #define DFP_EXTND 2 |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9324 | #define DFP_LONG_BIAS 398 |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9325 | #define DFP_LONG_ENCODED_FIELD_MASK 0x1F00 |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9326 | #define DFP_EXTND_BIAS 6176 |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9327 | #define DFP_EXTND_ENCODED_FIELD_MASK 0x1F000 |
| 9328 | #define DFP_LONG_EXP_MSK 0XFF |
| 9329 | #define DFP_EXTND_EXP_MSK 0XFFF |
| 9330 | |
| 9331 | #define DFP_G_FIELD_LONG_MASK 0x7FFC0000 // upper 32-bits only |
| 9332 | #define DFP_LONG_GFIELD_RT_SHIFT (63 - 13 - 32) // adj for upper 32-bits |
| 9333 | #define DFP_G_FIELD_EXTND_MASK 0x7FFFC000 // upper 32-bits only |
| 9334 | #define DFP_EXTND_GFIELD_RT_SHIFT (63 - 17 - 32) //adj for upper 32 bits |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9335 | #define DFP_T_FIELD_LONG_MASK 0x3FFFF // mask for upper 32-bits |
| 9336 | #define DFP_T_FIELD_EXTND_MASK 0x03FFFF // mask for upper 32-bits |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9337 | #define DFP_LONG_EXP_MAX 369 // biased max |
| 9338 | #define DFP_LONG_EXP_MIN 0 // biased min |
| 9339 | #define DFP_EXTND_EXP_MAX 6111 // biased max |
| 9340 | #define DFP_EXTND_EXP_MIN 0 // biased min |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9341 | #define DFP_LONG_MAX_SIG_DIGITS 16 |
| 9342 | #define DFP_EXTND_MAX_SIG_DIGITS 34 |
| 9343 | #define MAX_DIGITS_IN_STRING 8 |
| 9344 | |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9345 | |
| 9346 | #define AND(x, y) binop( Iop_And32, x, y ) |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9347 | #define AND4(w, x, y, z) AND( AND( w, x ), AND( y, z ) ) |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9348 | #define OR(x, y) binop( Iop_Or32, x, y ) |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9349 | #define OR3(x, y, z) OR( x, OR( y, z ) ) |
| 9350 | #define OR4(w, x, y, z) OR( OR( w, x ), OR( y, z ) ) |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9351 | #define NOT(x) unop( Iop_1Uto32, unop( Iop_Not1, unop( Iop_32to1, mkexpr( x ) ) ) ) |
| 9352 | |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9353 | #define SHL(value, by) binop( Iop_Shl32, value, mkU8( by ) ) |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9354 | #define SHR(value, by) binop( Iop_Shr32, value, mkU8( by ) ) |
| 9355 | |
sewardj | cb06d5e | 2012-04-30 08:10:11 +0000 | [diff] [blame] | 9356 | #define BITS5(_b4,_b3,_b2,_b1,_b0) \ |
| 9357 | (((_b4) << 4) | ((_b3) << 3) | ((_b2) << 2) | \ |
| 9358 | ((_b1) << 1) | ((_b0) << 0)) |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9359 | |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9360 | static IRExpr * Gfield_encoding( IRExpr * lmexp, IRExpr * lmd32 ) |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9361 | { |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9362 | IRTemp lmd_07_mask = newTemp( Ity_I32 ); |
| 9363 | IRTemp lmd_8_mask = newTemp( Ity_I32 ); |
| 9364 | IRTemp lmd_9_mask = newTemp( Ity_I32 ); |
| 9365 | IRTemp lmexp_00_mask = newTemp( Ity_I32 ); |
| 9366 | IRTemp lmexp_01_mask = newTemp( Ity_I32 ); |
| 9367 | IRTemp lmexp_10_mask = newTemp( Ity_I32 ); |
| 9368 | IRTemp lmd_07_val = newTemp( Ity_I32 ); |
| 9369 | IRTemp lmd_8_val = newTemp( Ity_I32 ); |
| 9370 | IRTemp lmd_9_val = newTemp( Ity_I32 ); |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9371 | |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9372 | /* The encodig is as follows: |
| 9373 | * lmd - left most digit |
| 9374 | * lme - left most 2-bits of the exponent |
| 9375 | * |
| 9376 | * lmd |
| 9377 | * 0 - 7 (lmexp << 3) | lmd |
| 9378 | * 8 0b11000 (24 decimal) if lme=0b00; |
| 9379 | * 0b11010 (26 decimal) if lme=0b01; |
| 9380 | * 0b11100 (28 decimal) if lme=0b10; |
| 9381 | * 9 0b11001 (25 decimal) if lme=0b00; |
| 9382 | * 0b11011 (27 decimal) if lme=0b01; |
| 9383 | * 0b11101 (29 decimal) if lme=0b10; |
| 9384 | */ |
| 9385 | |
| 9386 | /* Generate the masks for each condition */ |
| 9387 | assign( lmd_07_mask, |
| 9388 | unop( Iop_1Sto32, binop( Iop_CmpLE32U, lmd32, mkU32( 7 ) ) ) ); |
| 9389 | assign( lmd_8_mask, |
| 9390 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmd32, mkU32( 8 ) ) ) ); |
| 9391 | assign( lmd_9_mask, |
| 9392 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmd32, mkU32( 9 ) ) ) ); |
| 9393 | assign( lmexp_00_mask, |
| 9394 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmexp, mkU32( 0 ) ) ) ); |
| 9395 | assign( lmexp_01_mask, |
| 9396 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmexp, mkU32( 1 ) ) ) ); |
| 9397 | assign( lmexp_10_mask, |
| 9398 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmexp, mkU32( 2 ) ) ) ); |
| 9399 | |
| 9400 | /* Generate the values for each LMD condition, assuming the condition |
| 9401 | * is TRUE. |
| 9402 | */ |
| 9403 | assign( lmd_07_val, |
| 9404 | binop( Iop_Or32, binop( Iop_Shl32, lmexp, mkU8( 3 ) ), lmd32 ) ); |
| 9405 | assign( lmd_8_val, |
| 9406 | binop( Iop_Or32, |
| 9407 | binop( Iop_Or32, |
| 9408 | binop( Iop_And32, |
| 9409 | mkexpr( lmexp_00_mask ), |
| 9410 | mkU32( 24 ) ), |
| 9411 | binop( Iop_And32, |
| 9412 | mkexpr( lmexp_01_mask ), |
| 9413 | mkU32( 26 ) ) ), |
| 9414 | binop( Iop_And32, mkexpr( lmexp_10_mask ), mkU32( 28 ) ) ) ); |
| 9415 | assign( lmd_9_val, |
| 9416 | binop( Iop_Or32, |
| 9417 | binop( Iop_Or32, |
| 9418 | binop( Iop_And32, |
| 9419 | mkexpr( lmexp_00_mask ), |
| 9420 | mkU32( 25 ) ), |
| 9421 | binop( Iop_And32, |
| 9422 | mkexpr( lmexp_01_mask ), |
| 9423 | mkU32( 27 ) ) ), |
| 9424 | binop( Iop_And32, mkexpr( lmexp_10_mask ), mkU32( 29 ) ) ) ); |
| 9425 | |
| 9426 | /* generate the result from the possible LMD values */ |
| 9427 | return binop( Iop_Or32, |
| 9428 | binop( Iop_Or32, |
| 9429 | binop( Iop_And32, |
| 9430 | mkexpr( lmd_07_mask ), |
| 9431 | mkexpr( lmd_07_val ) ), |
| 9432 | binop( Iop_And32, |
| 9433 | mkexpr( lmd_8_mask ), |
| 9434 | mkexpr( lmd_8_val ) ) ), |
| 9435 | binop( Iop_And32, mkexpr( lmd_9_mask ), mkexpr( lmd_9_val ) ) ); |
| 9436 | } |
| 9437 | |
| 9438 | static void Get_lmd( IRTemp * lmd, IRExpr * gfield_0_4 ) |
| 9439 | { |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9440 | /* Extract the exponent and the left most digit of the mantissa |
| 9441 | * from the G field bits [0:4]. |
| 9442 | */ |
| 9443 | IRTemp lmd_07_mask = newTemp( Ity_I32 ); |
| 9444 | IRTemp lmd_8_00_mask = newTemp( Ity_I32 ); |
| 9445 | IRTemp lmd_8_01_mask = newTemp( Ity_I32 ); |
| 9446 | IRTemp lmd_8_10_mask = newTemp( Ity_I32 ); |
| 9447 | IRTemp lmd_9_00_mask = newTemp( Ity_I32 ); |
| 9448 | IRTemp lmd_9_01_mask = newTemp( Ity_I32 ); |
| 9449 | IRTemp lmd_9_10_mask = newTemp( Ity_I32 ); |
| 9450 | |
| 9451 | IRTemp lmd_07_val = newTemp( Ity_I32 ); |
| 9452 | IRTemp lmd_8_val = newTemp( Ity_I32 ); |
| 9453 | IRTemp lmd_9_val = newTemp( Ity_I32 ); |
| 9454 | |
| 9455 | /* The left most digit (LMD) encoding is as follows: |
| 9456 | * lmd |
| 9457 | * 0 - 7 (lmexp << 3) | lmd |
| 9458 | * 8 0b11000 (24 decimal) if lme=0b00; |
| 9459 | * 0b11010 (26 decimal) if lme=0b01; |
| 9460 | * 0b11100 (28 decimal) if lme=0b10 |
| 9461 | * 9 0b11001 (25 decimal) if lme=0b00; |
| 9462 | * 0b11011 (27 decimal) if lme=0b01; |
| 9463 | * 0b11101 (29 decimal) if lme=0b10; |
| 9464 | */ |
| 9465 | |
| 9466 | /* Generate the masks for each condition of LMD and exponent bits */ |
sewardj | cb06d5e | 2012-04-30 08:10:11 +0000 | [diff] [blame] | 9467 | assign( lmd_07_mask, |
| 9468 | unop( Iop_1Sto32, binop( Iop_CmpLE32U, |
| 9469 | gfield_0_4, |
| 9470 | mkU32( BITS5(1,0,1,1,1) ) ) ) ); |
| 9471 | assign( lmd_8_00_mask, |
| 9472 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, |
| 9473 | gfield_0_4, |
| 9474 | mkU32( BITS5(1,1,0,0,0) ) ) ) ); |
| 9475 | assign( lmd_8_01_mask, |
| 9476 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, |
| 9477 | gfield_0_4, |
| 9478 | mkU32( BITS5(1,1,0,1,0) ) ) ) ); |
| 9479 | assign( lmd_8_10_mask, |
| 9480 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, |
| 9481 | gfield_0_4, |
| 9482 | mkU32( BITS5(1,1,1,0,0) ) ) ) ); |
| 9483 | assign( lmd_9_00_mask, |
| 9484 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, |
| 9485 | gfield_0_4, |
| 9486 | mkU32( BITS5(1,1,0,0,1) ) ) ) ); |
| 9487 | assign( lmd_9_01_mask, |
| 9488 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, |
| 9489 | gfield_0_4, |
| 9490 | mkU32( BITS5(1,1,0,1,1) ) ) ) ); |
| 9491 | assign( lmd_9_10_mask, |
| 9492 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, |
| 9493 | gfield_0_4, |
| 9494 | mkU32( BITS5(1,1,1,0,1) ) ) ) ); |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9495 | |
| 9496 | /* Generate the values for each LMD condition, assuming the condition |
| 9497 | * is TRUE. |
| 9498 | */ |
| 9499 | assign( lmd_07_val, binop( Iop_And32, gfield_0_4, mkU32( 0x7 ) ) ); |
| 9500 | assign( lmd_8_val, mkU32( 0x8 ) ); |
| 9501 | assign( lmd_9_val, mkU32( 0x9 ) ); |
| 9502 | |
| 9503 | assign( *lmd, |
| 9504 | OR( OR3 ( AND( mkexpr( lmd_07_mask ), mkexpr( lmd_07_val ) ), |
| 9505 | AND( mkexpr( lmd_8_00_mask ), mkexpr( lmd_8_val ) ), |
| 9506 | AND( mkexpr( lmd_8_01_mask ), mkexpr( lmd_8_val ) )), |
| 9507 | OR4( AND( mkexpr( lmd_8_10_mask ), mkexpr( lmd_8_val ) ), |
| 9508 | AND( mkexpr( lmd_9_00_mask ), mkexpr( lmd_9_val ) ), |
| 9509 | AND( mkexpr( lmd_9_01_mask ), mkexpr( lmd_9_val ) ), |
| 9510 | AND( mkexpr( lmd_9_10_mask ), mkexpr( lmd_9_val ) ) |
| 9511 | ) ) ); |
| 9512 | } |
| 9513 | |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9514 | #define DIGIT1_SHR 4 // shift digit 1 to bottom 4 bits |
| 9515 | #define DIGIT2_SHR 8 // shift digit 2 to bottom 4 bits |
| 9516 | #define DIGIT3_SHR 12 |
| 9517 | #define DIGIT4_SHR 16 |
| 9518 | #define DIGIT5_SHR 20 |
| 9519 | #define DIGIT6_SHR 24 |
| 9520 | #define DIGIT7_SHR 28 |
| 9521 | |
| 9522 | static IRExpr * bcd_digit_inval( IRExpr * bcd_u, IRExpr * bcd_l ) |
| 9523 | { |
| 9524 | /* 60-bit BCD string stored in two 32-bit values. Check that each, |
| 9525 | * digit is a valid BCD number, i.e. less then 9. |
| 9526 | */ |
| 9527 | IRTemp valid = newTemp( Ity_I32 ); |
| 9528 | |
| 9529 | assign( valid, |
| 9530 | AND4( AND4 ( unop( Iop_1Sto32, |
| 9531 | binop( Iop_CmpLE32U, |
| 9532 | binop( Iop_And32, |
| 9533 | bcd_l, |
| 9534 | mkU32 ( 0xF ) ), |
| 9535 | mkU32( 0x9 ) ) ), |
| 9536 | unop( Iop_1Sto32, |
| 9537 | binop( Iop_CmpLE32U, |
| 9538 | binop( Iop_And32, |
| 9539 | binop( Iop_Shr32, |
| 9540 | bcd_l, |
| 9541 | mkU8 ( DIGIT1_SHR ) ), |
| 9542 | mkU32 ( 0xF ) ), |
| 9543 | mkU32( 0x9 ) ) ), |
| 9544 | unop( Iop_1Sto32, |
| 9545 | binop( Iop_CmpLE32U, |
| 9546 | binop( Iop_And32, |
| 9547 | binop( Iop_Shr32, |
| 9548 | bcd_l, |
| 9549 | mkU8 ( DIGIT2_SHR ) ), |
| 9550 | mkU32 ( 0xF ) ), |
| 9551 | mkU32( 0x9 ) ) ), |
| 9552 | unop( Iop_1Sto32, |
| 9553 | binop( Iop_CmpLE32U, |
| 9554 | binop( Iop_And32, |
| 9555 | binop( Iop_Shr32, |
| 9556 | bcd_l, |
| 9557 | mkU8 ( DIGIT3_SHR ) ), |
| 9558 | mkU32 ( 0xF ) ), |
| 9559 | mkU32( 0x9 ) ) ) ), |
| 9560 | AND4 ( unop( Iop_1Sto32, |
| 9561 | binop( Iop_CmpLE32U, |
| 9562 | binop( Iop_And32, |
| 9563 | binop( Iop_Shr32, |
| 9564 | bcd_l, |
| 9565 | mkU8 ( DIGIT4_SHR ) ), |
| 9566 | mkU32 ( 0xF ) ), |
| 9567 | mkU32( 0x9 ) ) ), |
| 9568 | unop( Iop_1Sto32, |
| 9569 | binop( Iop_CmpLE32U, |
| 9570 | binop( Iop_And32, |
| 9571 | binop( Iop_Shr32, |
| 9572 | bcd_l, |
| 9573 | mkU8 ( DIGIT5_SHR ) ), |
| 9574 | mkU32 ( 0xF ) ), |
| 9575 | mkU32( 0x9 ) ) ), |
| 9576 | unop( Iop_1Sto32, |
| 9577 | binop( Iop_CmpLE32U, |
| 9578 | binop( Iop_And32, |
| 9579 | binop( Iop_Shr32, |
| 9580 | bcd_l, |
| 9581 | mkU8 ( DIGIT6_SHR ) ), |
| 9582 | mkU32 ( 0xF ) ), |
| 9583 | mkU32( 0x9 ) ) ), |
| 9584 | unop( Iop_1Sto32, |
| 9585 | binop( Iop_CmpLE32U, |
| 9586 | binop( Iop_And32, |
| 9587 | binop( Iop_Shr32, |
| 9588 | bcd_l, |
| 9589 | mkU8 ( DIGIT7_SHR ) ), |
| 9590 | mkU32 ( 0xF ) ), |
| 9591 | mkU32( 0x9 ) ) ) ), |
| 9592 | AND4( unop( Iop_1Sto32, |
| 9593 | binop( Iop_CmpLE32U, |
| 9594 | binop( Iop_And32, |
| 9595 | bcd_u, |
| 9596 | mkU32 ( 0xF ) ), |
| 9597 | mkU32( 0x9 ) ) ), |
| 9598 | unop( Iop_1Sto32, |
| 9599 | binop( Iop_CmpLE32U, |
| 9600 | binop( Iop_And32, |
| 9601 | binop( Iop_Shr32, |
| 9602 | bcd_u, |
| 9603 | mkU8 ( DIGIT1_SHR ) ), |
| 9604 | mkU32 ( 0xF ) ), |
| 9605 | mkU32( 0x9 ) ) ), |
| 9606 | unop( Iop_1Sto32, |
| 9607 | binop( Iop_CmpLE32U, |
| 9608 | binop( Iop_And32, |
| 9609 | binop( Iop_Shr32, |
| 9610 | bcd_u, |
| 9611 | mkU8 ( DIGIT2_SHR ) ), |
| 9612 | mkU32 ( 0xF ) ), |
| 9613 | mkU32( 0x9 ) ) ), |
| 9614 | unop( Iop_1Sto32, |
| 9615 | binop( Iop_CmpLE32U, |
| 9616 | binop( Iop_And32, |
| 9617 | binop( Iop_Shr32, |
| 9618 | bcd_u, |
| 9619 | mkU8 ( DIGIT3_SHR ) ), |
| 9620 | mkU32 ( 0xF ) ), |
| 9621 | mkU32( 0x9 ) ) ) ), |
| 9622 | AND4( unop( Iop_1Sto32, |
| 9623 | binop( Iop_CmpLE32U, |
| 9624 | binop( Iop_And32, |
| 9625 | binop( Iop_Shr32, |
| 9626 | bcd_u, |
| 9627 | mkU8 ( DIGIT4_SHR ) ), |
| 9628 | mkU32 ( 0xF ) ), |
| 9629 | mkU32( 0x9 ) ) ), |
| 9630 | unop( Iop_1Sto32, |
| 9631 | binop( Iop_CmpLE32U, |
| 9632 | binop( Iop_And32, |
| 9633 | binop( Iop_Shr32, |
| 9634 | bcd_u, |
| 9635 | mkU8 ( DIGIT5_SHR ) ), |
| 9636 | mkU32 ( 0xF ) ), |
| 9637 | mkU32( 0x9 ) ) ), |
| 9638 | unop( Iop_1Sto32, |
| 9639 | binop( Iop_CmpLE32U, |
| 9640 | binop( Iop_And32, |
| 9641 | binop( Iop_Shr32, |
| 9642 | bcd_u, |
| 9643 | mkU8 ( DIGIT6_SHR ) ), |
| 9644 | mkU32 ( 0xF ) ), |
| 9645 | mkU32( 0x9 ) ) ), |
| 9646 | unop( Iop_1Sto32, |
| 9647 | binop( Iop_CmpLE32U, |
| 9648 | binop( Iop_And32, |
| 9649 | binop( Iop_Shr32, |
| 9650 | bcd_u, |
| 9651 | mkU8 ( DIGIT7_SHR ) ), |
| 9652 | mkU32 ( 0xF ) ), |
| 9653 | mkU32( 0x9 ) ) ) ) ) ); |
| 9654 | |
| 9655 | return unop( Iop_Not32, mkexpr( valid ) ); |
| 9656 | } |
| 9657 | #undef DIGIT1_SHR |
| 9658 | #undef DIGIT2_SHR |
| 9659 | #undef DIGIT3_SHR |
| 9660 | #undef DIGIT4_SHR |
| 9661 | #undef DIGIT5_SHR |
| 9662 | #undef DIGIT6_SHR |
| 9663 | #undef DIGIT7_SHR |
| 9664 | |
| 9665 | static IRExpr * Generate_neg_sign_mask( IRExpr * sign ) |
| 9666 | { |
| 9667 | return binop( Iop_Or32, |
| 9668 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, sign, mkU32( 0xB ) ) ), |
| 9669 | unop( Iop_1Sto32, binop( Iop_CmpEQ32, sign, mkU32( 0xD ) ) ) |
| 9670 | ); |
| 9671 | } |
| 9672 | |
| 9673 | static IRExpr * Generate_pos_sign_mask( IRExpr * sign ) |
| 9674 | { |
| 9675 | return binop( Iop_Or32, |
| 9676 | binop( Iop_Or32, |
| 9677 | unop( Iop_1Sto32, |
| 9678 | binop( Iop_CmpEQ32, sign, mkU32( 0xA ) ) ), |
| 9679 | unop( Iop_1Sto32, |
| 9680 | binop( Iop_CmpEQ32, sign, mkU32( 0xC ) ) ) ), |
| 9681 | binop( Iop_Or32, |
| 9682 | unop( Iop_1Sto32, |
| 9683 | binop( Iop_CmpEQ32, sign, mkU32( 0xE ) ) ), |
| 9684 | unop( Iop_1Sto32, |
| 9685 | binop( Iop_CmpEQ32, sign, mkU32( 0xF ) ) ) ) ); |
| 9686 | } |
| 9687 | |
| 9688 | static IRExpr * Generate_sign_bit( IRExpr * pos_sign_mask, |
| 9689 | IRExpr * neg_sign_mask ) |
| 9690 | { |
| 9691 | return binop( Iop_Or32, |
| 9692 | binop( Iop_And32, neg_sign_mask, mkU32( 0x80000000 ) ), |
| 9693 | binop( Iop_And32, pos_sign_mask, mkU32( 0x00000000 ) ) ); |
| 9694 | } |
| 9695 | |
| 9696 | static IRExpr * Generate_inv_mask( IRExpr * invalid_bcd_mask, |
| 9697 | IRExpr * pos_sign_mask, |
| 9698 | IRExpr * neg_sign_mask ) |
| 9699 | /* first argument is all 1's if the BCD string had an invalid digit in it. */ |
| 9700 | { |
| 9701 | return binop( Iop_Or32, |
| 9702 | invalid_bcd_mask, |
| 9703 | unop( Iop_1Sto32, |
| 9704 | binop( Iop_CmpEQ32, |
| 9705 | binop( Iop_Or32, pos_sign_mask, neg_sign_mask ), |
| 9706 | mkU32( 0x0 ) ) ) ); |
| 9707 | } |
| 9708 | |
| 9709 | static void Generate_132_bit_bcd_string( IRExpr * frBI64_hi, IRExpr * frBI64_lo, |
| 9710 | IRTemp * top_12_l, IRTemp * mid_60_u, |
| 9711 | IRTemp * mid_60_l, IRTemp * low_60_u, |
| 9712 | IRTemp * low_60_l) |
| 9713 | { |
| 9714 | IRTemp tmplow60 = newTemp( Ity_I64 ); |
| 9715 | IRTemp tmpmid60 = newTemp( Ity_I64 ); |
| 9716 | IRTemp tmptop12 = newTemp( Ity_I64 ); |
| 9717 | IRTemp low_50 = newTemp( Ity_I64 ); |
| 9718 | IRTemp mid_50 = newTemp( Ity_I64 ); |
| 9719 | IRTemp top_10 = newTemp( Ity_I64 ); |
| 9720 | IRTemp top_12_u = newTemp( Ity_I32 ); // only needed for a dummy arg |
| 9721 | |
| 9722 | /* Convert the 110-bit densely packed BCD string to a 128-bit BCD string */ |
| 9723 | |
| 9724 | /* low_50[49:0] = ((frBI64_lo[49:32] << 14) | frBI64_lo[31:0]) */ |
| 9725 | assign( low_50, |
| 9726 | binop( Iop_32HLto64, |
| 9727 | binop( Iop_And32, |
| 9728 | unop( Iop_64HIto32, frBI64_lo ), |
| 9729 | mkU32( 0x3FFFF ) ), |
| 9730 | unop( Iop_64to32, frBI64_lo ) ) ); |
| 9731 | |
| 9732 | /* Convert the 50 bit densely packed BCD string to a 60 bit |
| 9733 | * BCD string. |
| 9734 | */ |
| 9735 | assign( tmplow60, unop( Iop_DPBtoBCD, mkexpr( low_50 ) ) ); |
| 9736 | assign( *low_60_u, unop( Iop_64HIto32, mkexpr( tmplow60 ) ) ); |
| 9737 | assign( *low_60_l, unop( Iop_64to32, mkexpr( tmplow60 ) ) ); |
| 9738 | |
| 9739 | /* mid_50[49:0] = ((frBI64_hi[35:32] << 14) | frBI64_hi[31:18]) | |
| 9740 | * ((frBI64_hi[17:0] << 14) | frBI64_lo[63:50]) |
| 9741 | */ |
| 9742 | assign( mid_50, |
| 9743 | binop( Iop_32HLto64, |
| 9744 | binop( Iop_Or32, |
| 9745 | binop( Iop_Shl32, |
| 9746 | binop( Iop_And32, |
| 9747 | unop( Iop_64HIto32, frBI64_hi ), |
| 9748 | mkU32( 0xF ) ), |
| 9749 | mkU8( 14 ) ), |
| 9750 | binop( Iop_Shr32, |
| 9751 | unop( Iop_64to32, frBI64_hi ), |
| 9752 | mkU8( 18 ) ) ), |
| 9753 | binop( Iop_Or32, |
| 9754 | binop( Iop_Shl32, |
| 9755 | unop( Iop_64to32, frBI64_hi ), |
| 9756 | mkU8( 14 ) ), |
| 9757 | binop( Iop_Shr32, |
| 9758 | unop( Iop_64HIto32, frBI64_lo ), |
| 9759 | mkU8( 18 ) ) ) ) ); |
| 9760 | |
| 9761 | /* Convert the 50 bit densely packed BCD string to a 60 bit |
| 9762 | * BCD string. |
| 9763 | */ |
| 9764 | assign( tmpmid60, unop( Iop_DPBtoBCD, mkexpr( mid_50 ) ) ); |
| 9765 | assign( *mid_60_u, unop( Iop_64HIto32, mkexpr( tmpmid60 ) ) ); |
| 9766 | assign( *mid_60_l, unop( Iop_64to32, mkexpr( tmpmid60 ) ) ); |
| 9767 | |
| 9768 | /* top_10[49:0] = frBI64_hi[45:36]) | */ |
| 9769 | assign( top_10, |
| 9770 | binop( Iop_32HLto64, |
| 9771 | mkU32( 0 ), |
| 9772 | binop( Iop_And32, |
| 9773 | binop( Iop_Shr32, |
| 9774 | unop( Iop_64HIto32, frBI64_hi ), |
| 9775 | mkU8( 4 ) ), |
| 9776 | mkU32( 0x3FF ) ) ) ); |
| 9777 | |
| 9778 | /* Convert the 10 bit densely packed BCD string to a 12 bit |
| 9779 | * BCD string. |
| 9780 | */ |
| 9781 | assign( tmptop12, unop( Iop_DPBtoBCD, mkexpr( top_10 ) ) ); |
| 9782 | assign( top_12_u, unop( Iop_64HIto32, mkexpr( tmptop12 ) ) ); |
| 9783 | assign( *top_12_l, unop( Iop_64to32, mkexpr( tmptop12 ) ) ); |
| 9784 | } |
| 9785 | |
| 9786 | static void Count_zeros( int start, IRExpr * init_cnt, IRExpr * init_flag, |
| 9787 | IRTemp * final_cnt, IRTemp * final_flag, |
| 9788 | IRExpr * string ) |
| 9789 | { |
| 9790 | IRTemp cnt[MAX_DIGITS_IN_STRING + 1];IRTemp flag[MAX_DIGITS_IN_STRING+1]; |
| 9791 | int digits = MAX_DIGITS_IN_STRING; |
| 9792 | int i; |
| 9793 | |
| 9794 | cnt[start-1] = newTemp( Ity_I8 ); |
| 9795 | flag[start-1] = newTemp( Ity_I8 ); |
| 9796 | assign( cnt[start-1], init_cnt); |
| 9797 | assign( flag[start-1], init_flag); |
| 9798 | |
| 9799 | for ( i = start; i <= digits; i++) { |
| 9800 | cnt[i] = newTemp( Ity_I8 ); |
| 9801 | flag[i] = newTemp( Ity_I8 ); |
| 9802 | assign( cnt[i], |
| 9803 | binop( Iop_Add8, |
| 9804 | mkexpr( cnt[i-1] ), |
| 9805 | binop(Iop_And8, |
| 9806 | unop( Iop_1Uto8, |
| 9807 | binop(Iop_CmpEQ32, |
| 9808 | binop(Iop_And32, |
| 9809 | string, |
| 9810 | mkU32( 0xF << |
| 9811 | ( ( digits - i ) * 4) ) ), |
| 9812 | mkU32( 0 ) ) ), |
| 9813 | binop( Iop_Xor8, /* complement flag */ |
| 9814 | mkexpr( flag[i - 1] ), |
| 9815 | mkU8( 0xFF ) ) ) ) ); |
| 9816 | |
| 9817 | /* set flag to 1 if digit was not a zero */ |
| 9818 | assign( flag[i], |
| 9819 | binop(Iop_Or8, |
| 9820 | unop( Iop_1Sto8, |
| 9821 | binop(Iop_CmpNE32, |
| 9822 | binop(Iop_And32, |
| 9823 | string, |
| 9824 | mkU32( 0xF << |
| 9825 | ( (digits - i) * 4) ) ), |
| 9826 | mkU32( 0 ) ) ), |
| 9827 | mkexpr( flag[i - 1] ) ) ); |
| 9828 | } |
| 9829 | |
| 9830 | *final_cnt = cnt[digits]; |
| 9831 | *final_flag = flag[digits]; |
| 9832 | } |
| 9833 | |
| 9834 | static IRExpr * Count_leading_zeros_60( IRExpr * lmd, IRExpr * upper_28, |
| 9835 | IRExpr * low_32 ) |
| 9836 | { |
| 9837 | IRTemp num_lmd = newTemp( Ity_I8 ); |
| 9838 | IRTemp num_upper = newTemp( Ity_I8 ); |
| 9839 | IRTemp num_low = newTemp( Ity_I8 ); |
| 9840 | IRTemp lmd_flag = newTemp( Ity_I8 ); |
| 9841 | IRTemp upper_flag = newTemp( Ity_I8 ); |
| 9842 | IRTemp low_flag = newTemp( Ity_I8 ); |
| 9843 | |
| 9844 | assign( num_lmd, unop( Iop_1Uto8, binop( Iop_CmpEQ32, lmd, mkU32( 0 ) ) ) ); |
| 9845 | assign( lmd_flag, unop( Iop_Not8, mkexpr( num_lmd ) ) ); |
| 9846 | |
| 9847 | Count_zeros( 2, |
| 9848 | mkexpr( num_lmd ), |
| 9849 | mkexpr( lmd_flag ), |
| 9850 | &num_upper, |
| 9851 | &upper_flag, |
| 9852 | upper_28 ); |
| 9853 | |
| 9854 | Count_zeros( 1, |
| 9855 | mkexpr( num_upper ), |
| 9856 | mkexpr( upper_flag ), |
| 9857 | &num_low, |
| 9858 | &low_flag, |
| 9859 | low_32 ); |
| 9860 | |
| 9861 | return mkexpr( num_low ); |
| 9862 | } |
| 9863 | |
| 9864 | static IRExpr * Count_leading_zeros_128( IRExpr * lmd, IRExpr * top_12_l, |
| 9865 | IRExpr * mid_60_u, IRExpr * mid_60_l, |
| 9866 | IRExpr * low_60_u, IRExpr * low_60_l) |
| 9867 | { |
| 9868 | IRTemp num_lmd = newTemp( Ity_I8 ); |
| 9869 | IRTemp num_top = newTemp( Ity_I8 ); |
| 9870 | IRTemp num_mid_u = newTemp( Ity_I8 ); |
| 9871 | IRTemp num_mid_l = newTemp( Ity_I8 ); |
| 9872 | IRTemp num_low_u = newTemp( Ity_I8 ); |
| 9873 | IRTemp num_low_l = newTemp( Ity_I8 ); |
| 9874 | |
| 9875 | IRTemp lmd_flag = newTemp( Ity_I8 ); |
| 9876 | IRTemp top_flag = newTemp( Ity_I8 ); |
| 9877 | IRTemp mid_u_flag = newTemp( Ity_I8 ); |
| 9878 | IRTemp mid_l_flag = newTemp( Ity_I8 ); |
| 9879 | IRTemp low_u_flag = newTemp( Ity_I8 ); |
| 9880 | IRTemp low_l_flag = newTemp( Ity_I8 ); |
| 9881 | |
| 9882 | /* Check the LMD, digit 16, to see if it is zero. */ |
| 9883 | assign( num_lmd, unop( Iop_1Uto8, binop( Iop_CmpEQ32, lmd, mkU32( 0 ) ) ) ); |
| 9884 | |
| 9885 | assign( lmd_flag, unop( Iop_Not8, mkexpr( num_lmd ) ) ); |
| 9886 | |
| 9887 | Count_zeros( 6, |
| 9888 | mkexpr( num_lmd ), |
| 9889 | mkexpr( lmd_flag ), |
| 9890 | &num_top, |
| 9891 | &top_flag, |
| 9892 | top_12_l ); |
| 9893 | |
| 9894 | Count_zeros( 1, |
| 9895 | mkexpr( num_top ), |
| 9896 | mkexpr( top_flag ), |
| 9897 | &num_mid_u, |
| 9898 | &mid_u_flag, |
| 9899 | binop( Iop_Or32, |
| 9900 | binop( Iop_Shl32, mid_60_u, mkU8( 2 ) ), |
| 9901 | binop( Iop_Shr32, mid_60_l, mkU8( 30 ) ) ) ); |
| 9902 | |
| 9903 | Count_zeros( 2, |
| 9904 | mkexpr( num_mid_u ), |
| 9905 | mkexpr( mid_u_flag ), |
| 9906 | &num_mid_l, |
| 9907 | &mid_l_flag, |
| 9908 | mid_60_l ); |
| 9909 | |
| 9910 | Count_zeros( 1, |
| 9911 | mkexpr( num_mid_l ), |
| 9912 | mkexpr( mid_l_flag ), |
| 9913 | &num_low_u, |
| 9914 | &low_u_flag, |
| 9915 | binop( Iop_Or32, |
| 9916 | binop( Iop_Shl32, low_60_u, mkU8( 2 ) ), |
| 9917 | binop( Iop_Shr32, low_60_l, mkU8( 30 ) ) ) ); |
| 9918 | |
| 9919 | Count_zeros( 2, |
| 9920 | mkexpr( num_low_u ), |
| 9921 | mkexpr( low_u_flag ), |
| 9922 | &num_low_l, |
| 9923 | &low_l_flag, |
| 9924 | low_60_l ); |
| 9925 | |
| 9926 | return mkexpr( num_low_l ); |
| 9927 | } |
| 9928 | |
| 9929 | static IRExpr * Check_unordered(IRExpr * val) |
| 9930 | { |
| 9931 | IRTemp gfield0to5 = newTemp( Ity_I32 ); |
| 9932 | |
| 9933 | /* Extract G[0:4] */ |
| 9934 | assign( gfield0to5, |
| 9935 | binop( Iop_And32, |
| 9936 | binop( Iop_Shr32, unop( Iop_64HIto32, val ), mkU8( 26 ) ), |
| 9937 | mkU32( 0x1F ) ) ); |
| 9938 | |
| 9939 | /* Check for unordered, return all 1'x if true */ |
| 9940 | return binop( Iop_Or32, /* QNaN check */ |
| 9941 | unop( Iop_1Sto32, |
| 9942 | binop( Iop_CmpEQ32, |
| 9943 | mkexpr( gfield0to5 ), |
| 9944 | mkU32( 0x1E ) ) ), |
| 9945 | unop( Iop_1Sto32, /* SNaN check */ |
| 9946 | binop( Iop_CmpEQ32, |
| 9947 | mkexpr( gfield0to5 ), |
| 9948 | mkU32( 0x1F ) ) ) ); |
| 9949 | } |
| 9950 | |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9951 | #undef AND |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9952 | #undef AND4 |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9953 | #undef OR |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9954 | #undef OR3 |
| 9955 | #undef OR4 |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 9956 | #undef NOT |
| 9957 | #undef SHR |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9958 | #undef SHL |
sewardj | cb06d5e | 2012-04-30 08:10:11 +0000 | [diff] [blame] | 9959 | #undef BITS5 |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9960 | |
| 9961 | /*------------------------------------------------------------*/ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9962 | /*--- Decimal Floating Point (DFP) instruction translation ---*/ |
| 9963 | /*------------------------------------------------------------*/ |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 9964 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9965 | /* DFP Arithmetic instructions */ |
| 9966 | static Bool dis_dfp_arith(UInt theInstr) |
| 9967 | { |
| 9968 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 9969 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 9970 | UChar frA_addr = ifieldRegA( theInstr ); |
| 9971 | UChar frB_addr = ifieldRegB( theInstr ); |
| 9972 | UChar flag_rC = ifieldBIT0( theInstr ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9973 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 9974 | IRTemp frA = newTemp( Ity_D64 ); |
| 9975 | IRTemp frB = newTemp( Ity_D64 ); |
| 9976 | IRTemp frS = newTemp( Ity_D64 ); |
| 9977 | IRExpr* round = get_IR_roundingmode_DFP(); |
| 9978 | |
| 9979 | /* By default, if flag_RC is set, we will clear cr1 after the |
| 9980 | * operation. In reality we should set cr1 to indicate the |
| 9981 | * exception status of the operation, but since we're not |
| 9982 | * simulating exceptions, the exception status will appear to be |
| 9983 | * zero. Hence cr1 should be cleared if this is a . form insn. |
| 9984 | */ |
| 9985 | Bool clear_CR1 = True; |
| 9986 | |
| 9987 | assign( frA, getDReg( frA_addr ) ); |
| 9988 | assign( frB, getDReg( frB_addr ) ); |
| 9989 | |
| 9990 | switch (opc2) { |
| 9991 | case 0x2: // dadd |
| 9992 | DIP( "dadd%s fr%u,fr%u,fr%u\n", |
| 9993 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 9994 | assign( frS, triop( Iop_AddD64, round, mkexpr( frA ), mkexpr( frB ) ) ); |
| 9995 | break; |
| 9996 | case 0x202: // dsub |
| 9997 | DIP( "dsub%s fr%u,fr%u,fr%u\n", |
| 9998 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 9999 | assign( frS, triop( Iop_SubD64, round, mkexpr( frA ), mkexpr( frB ) ) ); |
| 10000 | break; |
| 10001 | case 0x22: // dmul |
| 10002 | DIP( "dmul%s fr%u,fr%u,fr%u\n", |
| 10003 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10004 | assign( frS, triop( Iop_MulD64, round, mkexpr( frA ), mkexpr( frB ) ) ); |
| 10005 | break; |
| 10006 | case 0x222: // ddiv |
| 10007 | DIP( "ddiv%s fr%u,fr%u,fr%u\n", |
| 10008 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10009 | assign( frS, triop( Iop_DivD64, round, mkexpr( frA ), mkexpr( frB ) ) ); |
| 10010 | break; |
| 10011 | } |
| 10012 | |
| 10013 | putDReg( frS_addr, mkexpr( frS ) ); |
| 10014 | |
| 10015 | if (flag_rC && clear_CR1) { |
| 10016 | putCR321( 1, mkU8( 0 ) ); |
| 10017 | putCR0( 1, mkU8( 0 ) ); |
| 10018 | } |
| 10019 | |
| 10020 | return True; |
| 10021 | } |
| 10022 | |
| 10023 | /* Quad DFP Arithmetic instructions */ |
| 10024 | static Bool dis_dfp_arithq(UInt theInstr) |
| 10025 | { |
| 10026 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 10027 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10028 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10029 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10030 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10031 | |
| 10032 | IRTemp frA = newTemp( Ity_D128 ); |
| 10033 | IRTemp frB = newTemp( Ity_D128 ); |
| 10034 | IRTemp frS = newTemp( Ity_D128 ); |
| 10035 | IRExpr* round = get_IR_roundingmode_DFP(); |
| 10036 | |
| 10037 | /* By default, if flag_RC is set, we will clear cr1 after the |
| 10038 | * operation. In reality we should set cr1 to indicate the |
| 10039 | * exception status of the operation, but since we're not |
| 10040 | * simulating exceptions, the exception status will appear to be |
| 10041 | * zero. Hence cr1 should be cleared if this is a . form insn. |
| 10042 | */ |
| 10043 | Bool clear_CR1 = True; |
| 10044 | |
| 10045 | assign( frA, getDReg_pair( frA_addr ) ); |
| 10046 | assign( frB, getDReg_pair( frB_addr ) ); |
| 10047 | |
| 10048 | switch (opc2) { |
| 10049 | case 0x2: // daddq |
| 10050 | DIP( "daddq%s fr%u,fr%u,fr%u\n", |
| 10051 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10052 | assign( frS, triop( Iop_AddD128, round, mkexpr( frA ), mkexpr( frB ) ) ); |
| 10053 | break; |
| 10054 | case 0x202: // dsubq |
| 10055 | DIP( "dsubq%s fr%u,fr%u,fr%u\n", |
| 10056 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10057 | assign( frS, triop( Iop_SubD128, round, mkexpr( frA ), mkexpr( frB ) ) ); |
| 10058 | break; |
| 10059 | case 0x22: // dmulq |
| 10060 | DIP( "dmulq%s fr%u,fr%u,fr%u\n", |
| 10061 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10062 | assign( frS, triop( Iop_MulD128, round, mkexpr( frA ), mkexpr( frB ) ) ); |
| 10063 | break; |
| 10064 | case 0x222: // ddivq |
| 10065 | DIP( "ddivq%s fr%u,fr%u,fr%u\n", |
| 10066 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10067 | assign( frS, triop( Iop_DivD128, round, mkexpr( frA ), mkexpr( frB ) ) ); |
| 10068 | break; |
| 10069 | } |
| 10070 | |
| 10071 | putDReg_pair( frS_addr, mkexpr( frS ) ); |
| 10072 | |
| 10073 | if (flag_rC && clear_CR1) { |
| 10074 | putCR321( 1, mkU8( 0 ) ); |
| 10075 | putCR0( 1, mkU8( 0 ) ); |
| 10076 | } |
| 10077 | |
| 10078 | return True; |
| 10079 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 10080 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10081 | /* DFP 64-bit logical shift instructions */ |
| 10082 | static Bool dis_dfp_shift(UInt theInstr) { |
| 10083 | UInt opc2 = ifieldOPClo9( theInstr ); |
| 10084 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10085 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10086 | UChar shift_val = IFIELD(theInstr, 10, 6); |
| 10087 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10088 | |
| 10089 | IRTemp frA = newTemp( Ity_D64 ); |
| 10090 | IRTemp frS = newTemp( Ity_D64 ); |
| 10091 | Bool clear_CR1 = True; |
| 10092 | |
| 10093 | assign( frA, getDReg( frA_addr ) ); |
| 10094 | |
| 10095 | switch (opc2) { |
| 10096 | case 0x42: // dscli |
| 10097 | DIP( "dscli%s fr%u,fr%u,%u\n", |
| 10098 | flag_rC ? ".":"", frS_addr, frA_addr, shift_val ); |
| 10099 | assign( frS, binop( Iop_ShlD64, mkexpr( frA ), mkU8( shift_val ) ) ); |
| 10100 | break; |
| 10101 | case 0x62: // dscri |
| 10102 | DIP( "dscri%s fr%u,fr%u,%u\n", |
| 10103 | flag_rC ? ".":"", frS_addr, frA_addr, shift_val ); |
| 10104 | assign( frS, binop( Iop_ShrD64, mkexpr( frA ), mkU8( shift_val ) ) ); |
| 10105 | break; |
| 10106 | } |
| 10107 | |
| 10108 | putDReg( frS_addr, mkexpr( frS ) ); |
| 10109 | |
| 10110 | if (flag_rC && clear_CR1) { |
| 10111 | putCR321( 1, mkU8( 0 ) ); |
| 10112 | putCR0( 1, mkU8( 0 ) ); |
| 10113 | } |
| 10114 | |
| 10115 | return True; |
| 10116 | } |
| 10117 | |
| 10118 | /* Quad DFP logical shift instructions */ |
| 10119 | static Bool dis_dfp_shiftq(UInt theInstr) { |
| 10120 | UInt opc2 = ifieldOPClo9( theInstr ); |
| 10121 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10122 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10123 | UChar shift_val = IFIELD(theInstr, 10, 6); |
| 10124 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10125 | |
| 10126 | IRTemp frA = newTemp( Ity_D128 ); |
| 10127 | IRTemp frS = newTemp( Ity_D128 ); |
| 10128 | Bool clear_CR1 = True; |
| 10129 | |
| 10130 | assign( frA, getDReg_pair( frA_addr ) ); |
| 10131 | |
| 10132 | switch (opc2) { |
| 10133 | case 0x42: // dscliq |
| 10134 | DIP( "dscliq%s fr%u,fr%u,%u\n", |
| 10135 | flag_rC ? ".":"", frS_addr, frA_addr, shift_val ); |
| 10136 | assign( frS, binop( Iop_ShlD128, mkexpr( frA ), mkU8( shift_val ) ) ); |
| 10137 | break; |
| 10138 | case 0x62: // dscriq |
| 10139 | DIP( "dscriq%s fr%u,fr%u,%u\n", |
| 10140 | flag_rC ? ".":"", frS_addr, frA_addr, shift_val ); |
| 10141 | assign( frS, binop( Iop_ShrD128, mkexpr( frA ), mkU8( shift_val ) ) ); |
| 10142 | break; |
| 10143 | } |
| 10144 | |
| 10145 | putDReg_pair( frS_addr, mkexpr( frS ) ); |
| 10146 | |
| 10147 | if (flag_rC && clear_CR1) { |
| 10148 | putCR321( 1, mkU8( 0 ) ); |
| 10149 | putCR0( 1, mkU8( 0 ) ); |
| 10150 | } |
| 10151 | |
| 10152 | return True; |
| 10153 | } |
| 10154 | |
| 10155 | /* DFP 64-bit format conversion instructions */ |
| 10156 | static Bool dis_dfp_fmt_conv(UInt theInstr) { |
| 10157 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 10158 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10159 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10160 | IRExpr* round = get_IR_roundingmode_DFP(); |
| 10161 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10162 | IRTemp frB; |
| 10163 | IRTemp frS; |
| 10164 | Bool clear_CR1 = True; |
| 10165 | |
| 10166 | switch (opc2) { |
| 10167 | case 0x102: //dctdp |
| 10168 | DIP( "dctdp%s fr%u,fr%u\n", |
| 10169 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10170 | |
carll | f704eb2 | 2013-01-21 18:12:31 +0000 | [diff] [blame] | 10171 | frB = newTemp( Ity_D32 ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10172 | frS = newTemp( Ity_D64 ); |
carll | f704eb2 | 2013-01-21 18:12:31 +0000 | [diff] [blame] | 10173 | assign( frB, getDReg32( frB_addr ) ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10174 | assign( frS, unop( Iop_D32toD64, mkexpr( frB ) ) ); |
| 10175 | putDReg( frS_addr, mkexpr( frS ) ); |
| 10176 | break; |
| 10177 | case 0x302: // drsp |
| 10178 | DIP( "drsp%s fr%u,fr%u\n", |
| 10179 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10180 | frB = newTemp( Ity_D64 ); |
carll | f704eb2 | 2013-01-21 18:12:31 +0000 | [diff] [blame] | 10181 | frS = newTemp( Ity_D32 ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10182 | assign( frB, getDReg( frB_addr ) ); |
| 10183 | assign( frS, binop( Iop_D64toD32, round, mkexpr( frB ) ) ); |
carll | f704eb2 | 2013-01-21 18:12:31 +0000 | [diff] [blame] | 10184 | putDReg32( frS_addr, mkexpr( frS ) ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10185 | break; |
| 10186 | case 0x122: // dctfix |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10187 | { |
| 10188 | IRTemp tmp = newTemp( Ity_I64 ); |
| 10189 | |
| 10190 | DIP( "dctfix%s fr%u,fr%u\n", |
| 10191 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10192 | frB = newTemp( Ity_D64 ); |
| 10193 | frS = newTemp( Ity_D64 ); |
| 10194 | assign( frB, getDReg( frB_addr ) ); |
| 10195 | assign( tmp, binop( Iop_D64toI64S, round, mkexpr( frB ) ) ); |
| 10196 | assign( frS, unop( Iop_ReinterpI64asD64, mkexpr( tmp ) ) ); |
| 10197 | putDReg( frS_addr, mkexpr( frS ) ); |
| 10198 | } |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10199 | break; |
| 10200 | case 0x322: // dcffix |
| 10201 | DIP( "dcffix%s fr%u,fr%u\n", |
| 10202 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10203 | frB = newTemp( Ity_D64 ); |
| 10204 | frS = newTemp( Ity_D64 ); |
| 10205 | assign( frB, getDReg( frB_addr ) ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10206 | assign( frS, binop( Iop_I64StoD64, |
| 10207 | round, |
| 10208 | unop( Iop_ReinterpD64asI64, mkexpr( frB ) ) ) ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10209 | putDReg( frS_addr, mkexpr( frS ) ); |
| 10210 | break; |
| 10211 | } |
| 10212 | |
| 10213 | if (flag_rC && clear_CR1) { |
| 10214 | putCR321( 1, mkU8( 0 ) ); |
| 10215 | putCR0( 1, mkU8( 0 ) ); |
| 10216 | } |
| 10217 | |
| 10218 | return True; |
| 10219 | } |
| 10220 | |
| 10221 | /* Quad DFP format conversion instructions */ |
| 10222 | static Bool dis_dfp_fmt_convq(UInt theInstr) { |
| 10223 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 10224 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10225 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10226 | IRExpr* round = get_IR_roundingmode_DFP(); |
| 10227 | IRTemp frB64 = newTemp( Ity_D64 ); |
| 10228 | IRTemp frB128 = newTemp( Ity_D128 ); |
| 10229 | IRTemp frS64 = newTemp( Ity_D64 ); |
| 10230 | IRTemp frS128 = newTemp( Ity_D128 ); |
| 10231 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10232 | Bool clear_CR1 = True; |
| 10233 | |
| 10234 | switch (opc2) { |
| 10235 | case 0x102: // dctqpq |
| 10236 | DIP( "dctqpq%s fr%u,fr%u\n", |
| 10237 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10238 | assign( frB64, getDReg( frB_addr ) ); |
| 10239 | assign( frS128, unop( Iop_D64toD128, mkexpr( frB64 ) ) ); |
| 10240 | putDReg_pair( frS_addr, mkexpr( frS128 ) ); |
| 10241 | break; |
| 10242 | case 0x122: // dctfixq |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10243 | { |
| 10244 | IRTemp tmp = newTemp( Ity_I64 ); |
| 10245 | |
| 10246 | DIP( "dctfixq%s fr%u,fr%u\n", |
| 10247 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10248 | assign( frB128, getDReg_pair( frB_addr ) ); |
| 10249 | assign( tmp, binop( Iop_D128toI64S, round, mkexpr( frB128 ) ) ); |
| 10250 | assign( frS64, unop( Iop_ReinterpI64asD64, mkexpr( tmp ) ) ); |
| 10251 | putDReg( frS_addr, mkexpr( frS64 ) ); |
| 10252 | } |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10253 | break; |
| 10254 | case 0x302: //drdpq |
| 10255 | DIP( "drdpq%s fr%u,fr%u\n", |
| 10256 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10257 | assign( frB128, getDReg_pair( frB_addr ) ); |
| 10258 | assign( frS64, binop( Iop_D128toD64, round, mkexpr( frB128 ) ) ); |
| 10259 | putDReg( frS_addr, mkexpr( frS64 ) ); |
| 10260 | break; |
| 10261 | case 0x322: // dcffixq |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10262 | { |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10263 | /* Have to introduce an IOP for this instruction so it will work |
| 10264 | * on POWER 6 because emulating the instruction requires a POWER 7 |
| 10265 | * DFP instruction in the emulation code. |
| 10266 | */ |
| 10267 | DIP( "dcffixq%s fr%u,fr%u\n", |
| 10268 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10269 | assign( frB64, getDReg( frB_addr ) ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10270 | assign( frS128, unop( Iop_I64StoD128, |
| 10271 | unop( Iop_ReinterpD64asI64, |
| 10272 | mkexpr( frB64 ) ) ) ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10273 | putDReg_pair( frS_addr, mkexpr( frS128 ) ); |
| 10274 | break; |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10275 | } |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 10276 | } |
| 10277 | |
| 10278 | if (flag_rC && clear_CR1) { |
| 10279 | putCR321( 1, mkU8( 0 ) ); |
| 10280 | putCR0( 1, mkU8( 0 ) ); |
| 10281 | } |
| 10282 | |
| 10283 | return True; |
| 10284 | } |
| 10285 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10286 | static Bool dis_dfp_round( UInt theInstr ) { |
| 10287 | UChar frS_addr = ifieldRegDS(theInstr); |
| 10288 | UChar R = IFIELD(theInstr, 16, 1); |
| 10289 | UChar RMC = IFIELD(theInstr, 9, 2); |
| 10290 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10291 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10292 | IRTemp frB = newTemp( Ity_D64 ); |
| 10293 | IRTemp frS = newTemp( Ity_D64 ); |
| 10294 | UInt opc2 = ifieldOPClo8( theInstr ); |
| 10295 | Bool clear_CR1 = True; |
| 10296 | |
| 10297 | switch (opc2) { |
| 10298 | /* drintn, is the same as drintx. The only difference is this |
| 10299 | * instruction does not generate an exception for an inexact operation. |
| 10300 | * Currently not supporting inexact exceptions. |
| 10301 | */ |
| 10302 | case 0x63: // drintx |
| 10303 | case 0xE3: // drintn |
| 10304 | DIP( "drintx/drintn%s fr%u,fr%u\n", |
| 10305 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10306 | |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10307 | /* NOTE, this instruction takes a DFP value and rounds to the |
| 10308 | * neares floating point integer value, i.e. fractional part |
| 10309 | * is zero. The result is a floating point number. |
| 10310 | */ |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10311 | /* pass the value of R and RMC in the same field */ |
| 10312 | assign( frB, getDReg( frB_addr ) ); |
| 10313 | assign( frS, binop( Iop_RoundD64toInt, |
| 10314 | mkU32( ( R << 3 ) | RMC ), |
| 10315 | mkexpr( frB ) ) ); |
| 10316 | putDReg( frS_addr, mkexpr( frS ) ); |
| 10317 | break; |
| 10318 | default: |
| 10319 | vex_printf("dis_dfp_round(ppc)(opc2)\n"); |
| 10320 | return False; |
| 10321 | } |
| 10322 | |
| 10323 | if (flag_rC && clear_CR1) { |
| 10324 | putCR321( 1, mkU8( 0 ) ); |
| 10325 | putCR0( 1, mkU8( 0 ) ); |
| 10326 | } |
| 10327 | |
| 10328 | return True; |
| 10329 | } |
| 10330 | |
| 10331 | static Bool dis_dfp_roundq(UInt theInstr) { |
| 10332 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10333 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10334 | UChar R = IFIELD(theInstr, 16, 1); |
| 10335 | UChar RMC = IFIELD(theInstr, 9, 2); |
| 10336 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10337 | IRTemp frB = newTemp( Ity_D128 ); |
| 10338 | IRTemp frS = newTemp( Ity_D128 ); |
| 10339 | Bool clear_CR1 = True; |
| 10340 | UInt opc2 = ifieldOPClo8( theInstr ); |
| 10341 | |
| 10342 | switch (opc2) { |
| 10343 | /* drintnq, is the same as drintxq. The only difference is this |
| 10344 | * instruction does not generate an exception for an inexact operation. |
| 10345 | * Currently not supporting inexact exceptions. |
| 10346 | */ |
| 10347 | case 0x63: // drintxq |
| 10348 | case 0xE3: // drintnq |
| 10349 | DIP( "drintxq/drintnq%s fr%u,fr%u\n", |
| 10350 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10351 | |
| 10352 | /* pass the value of R and RMC in the same field */ |
| 10353 | assign( frB, getDReg_pair( frB_addr ) ); |
| 10354 | assign( frS, binop( Iop_RoundD128toInt, |
| 10355 | mkU32( ( R << 3 ) | RMC ), |
| 10356 | mkexpr( frB ) ) ); |
| 10357 | putDReg_pair( frS_addr, mkexpr( frS ) ); |
| 10358 | break; |
| 10359 | default: |
| 10360 | vex_printf("dis_dfp_roundq(ppc)(opc2)\n"); |
| 10361 | return False; |
| 10362 | } |
| 10363 | |
| 10364 | if (flag_rC && clear_CR1) { |
| 10365 | putCR321( 1, mkU8( 0 ) ); |
| 10366 | putCR0( 1, mkU8( 0 ) ); |
| 10367 | } |
| 10368 | |
| 10369 | return True; |
| 10370 | } |
| 10371 | |
| 10372 | static Bool dis_dfp_quantize_sig_rrnd(UInt theInstr) { |
| 10373 | UInt opc2 = ifieldOPClo8( theInstr ); |
| 10374 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10375 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10376 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10377 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10378 | UInt TE_value = IFIELD(theInstr, 16, 4); |
| 10379 | UInt TE_sign = IFIELD(theInstr, 20, 1); |
| 10380 | UInt RMC = IFIELD(theInstr, 9, 2); |
| 10381 | IRTemp frA = newTemp( Ity_D64 ); |
| 10382 | IRTemp frB = newTemp( Ity_D64 ); |
| 10383 | IRTemp frS = newTemp( Ity_D64 ); |
| 10384 | Bool clear_CR1 = True; |
| 10385 | |
| 10386 | assign( frB, getDReg( frB_addr ) ); |
| 10387 | |
| 10388 | switch (opc2) { |
| 10389 | case 0x43: // dquai |
| 10390 | DIP( "dquai%s fr%u,fr%u,fr%u\n", |
| 10391 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10392 | IRTemp TE_I64 = newTemp( Ity_I64 ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10393 | |
| 10394 | /* Generate a reference DFP value frA with the desired exponent |
| 10395 | * given by TE using significand from frB. Need to add the bias |
| 10396 | * 398 to TE. TE is stored as a 2's complement number. |
| 10397 | */ |
| 10398 | if (TE_sign == 1) { |
| 10399 | /* Take 2's complement of the 5-bit value and subtract from bias. |
| 10400 | * Bias is adjusted for the +1 required when taking 2's complement. |
| 10401 | */ |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10402 | assign( TE_I64, |
| 10403 | unop( Iop_32Uto64, |
| 10404 | binop( Iop_Sub32, mkU32( 397 ), |
| 10405 | binop( Iop_And32, mkU32( 0xF ), |
| 10406 | unop( Iop_Not32, mkU32( TE_value ) ) |
| 10407 | ) ) ) ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10408 | |
| 10409 | } else { |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10410 | assign( TE_I64, |
| 10411 | unop( Iop_32Uto64, |
| 10412 | binop( Iop_Add32, mkU32( 398 ), mkU32( TE_value ) ) |
| 10413 | ) ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10414 | } |
| 10415 | |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10416 | assign( frA, binop( Iop_InsertExpD64, mkexpr( TE_I64 ), |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10417 | unop( Iop_ReinterpI64asD64, mkU64( 1 ) ) ) ); |
| 10418 | |
| 10419 | assign( frS, triop( Iop_QuantizeD64, |
| 10420 | mkU32( RMC ), |
| 10421 | mkexpr( frA ), |
| 10422 | mkexpr( frB ) ) ); |
| 10423 | break; |
| 10424 | |
| 10425 | case 0x3: // dqua |
| 10426 | DIP( "dqua%s fr%u,fr%u,fr%u\n", |
| 10427 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10428 | assign( frA, getDReg( frA_addr ) ); |
| 10429 | assign( frS, triop( Iop_QuantizeD64, |
| 10430 | mkU32( RMC ), |
| 10431 | mkexpr( frA ), |
| 10432 | mkexpr( frB ) ) ); |
| 10433 | break; |
| 10434 | case 0x23: // drrnd |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10435 | { |
| 10436 | IRTemp tmp = newTemp( Ity_I8 ); |
| 10437 | |
| 10438 | DIP( "drrnd%s fr%u,fr%u,fr%u\n", |
| 10439 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10440 | assign( frA, getDReg( frA_addr ) ); |
| 10441 | /* Iop_64to8 not supported in 32 bit mode, do it in two steps. */ |
| 10442 | assign( tmp, unop( Iop_32to8, |
| 10443 | unop( Iop_64to32, |
| 10444 | unop( Iop_ReinterpD64asI64, |
| 10445 | mkexpr( frA ) ) ) ) ); |
| 10446 | assign( frS, triop( Iop_SignificanceRoundD64, |
| 10447 | mkU32( RMC ), |
| 10448 | mkexpr( tmp ), |
| 10449 | mkexpr( frB ) ) ); |
| 10450 | } |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10451 | break; |
| 10452 | default: |
| 10453 | vex_printf("dis_dfp_quantize_sig_rrnd(ppc)(opc2)\n"); |
| 10454 | return False; |
| 10455 | } |
| 10456 | putDReg( frS_addr, mkexpr( frS ) ); |
| 10457 | |
| 10458 | if (flag_rC && clear_CR1) { |
| 10459 | putCR321( 1, mkU8( 0 ) ); |
| 10460 | putCR0( 1, mkU8( 0 ) ); |
| 10461 | } |
| 10462 | |
| 10463 | return True; |
| 10464 | } |
| 10465 | |
| 10466 | static Bool dis_dfp_quantize_sig_rrndq(UInt theInstr) { |
| 10467 | UInt opc2 = ifieldOPClo8( theInstr ); |
| 10468 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10469 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10470 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10471 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10472 | UInt TE_value = IFIELD(theInstr, 16, 4); |
| 10473 | UInt TE_sign = IFIELD(theInstr, 20, 1); |
| 10474 | UInt RMC = IFIELD(theInstr, 9, 2); |
| 10475 | IRTemp frA = newTemp( Ity_D128 ); |
| 10476 | IRTemp frB = newTemp( Ity_D128 ); |
| 10477 | IRTemp frS = newTemp( Ity_D128 ); |
| 10478 | Bool clear_CR1 = True; |
| 10479 | |
| 10480 | assign( frB, getDReg_pair( frB_addr ) ); |
| 10481 | |
| 10482 | switch (opc2) { |
| 10483 | case 0x43: // dquaiq |
| 10484 | DIP( "dquaiq%s fr%u,fr%u,fr%u\n", |
| 10485 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10486 | IRTemp TE_I64 = newTemp( Ity_I64 ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10487 | |
| 10488 | /* Generate a reference DFP value frA with the desired exponent |
| 10489 | * given by TE using significand of 1. Need to add the bias |
| 10490 | * 6176 to TE. |
| 10491 | */ |
| 10492 | if (TE_sign == 1) { |
| 10493 | /* Take 2's complement of the 5-bit value and subtract from bias. |
| 10494 | * Bias adjusted for the +1 required when taking 2's complement. |
| 10495 | */ |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10496 | assign( TE_I64, |
| 10497 | unop( Iop_32Uto64, |
| 10498 | binop( Iop_Sub32, mkU32( 6175 ), |
| 10499 | binop( Iop_And32, mkU32( 0xF ), |
| 10500 | unop( Iop_Not32, mkU32( TE_value ) ) |
| 10501 | ) ) ) ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10502 | |
| 10503 | } else { |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10504 | assign( TE_I64, |
| 10505 | unop( Iop_32Uto64, |
| 10506 | binop( Iop_Add32, |
| 10507 | mkU32( 6176 ), |
| 10508 | mkU32( TE_value ) ) ) ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10509 | } |
| 10510 | |
| 10511 | assign( frA, |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10512 | binop( Iop_InsertExpD128, mkexpr( TE_I64 ), |
| 10513 | unop( Iop_D64toD128, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10514 | unop( Iop_ReinterpI64asD64, mkU64( 1 ) ) ) ) ); |
| 10515 | assign( frS, triop( Iop_QuantizeD128, |
| 10516 | mkU32( RMC ), |
| 10517 | mkexpr( frA ), |
| 10518 | mkexpr( frB ) ) ); |
| 10519 | break; |
| 10520 | case 0x3: // dquaq |
| 10521 | DIP( "dquaiq%s fr%u,fr%u,fr%u\n", |
| 10522 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10523 | assign( frA, getDReg_pair( frA_addr ) ); |
| 10524 | assign( frS, triop( Iop_QuantizeD128, |
| 10525 | mkU32( RMC ), |
| 10526 | mkexpr( frA ), |
| 10527 | mkexpr( frB ) ) ); |
| 10528 | break; |
| 10529 | case 0x23: // drrndq |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10530 | { |
| 10531 | IRTemp tmp = newTemp( Ity_I8 ); |
| 10532 | |
| 10533 | DIP( "drrndq%s fr%u,fr%u,fr%u\n", |
| 10534 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10535 | assign( frA, getDReg_pair( frA_addr ) ); |
| 10536 | assign( tmp, unop( Iop_32to8, |
| 10537 | unop( Iop_64to32, |
| 10538 | unop( Iop_ReinterpD64asI64, |
| 10539 | unop( Iop_D128HItoD64, |
| 10540 | mkexpr( frA ) ) ) ) ) ); |
| 10541 | assign( frS, triop( Iop_SignificanceRoundD128, |
| 10542 | mkU32( RMC ), |
| 10543 | mkexpr( tmp ), |
| 10544 | mkexpr( frB ) ) ); |
| 10545 | } |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10546 | break; |
| 10547 | default: |
| 10548 | vex_printf("dis_dfp_quantize_sig_rrndq(ppc)(opc2)\n"); |
| 10549 | return False; |
| 10550 | } |
| 10551 | putDReg_pair( frS_addr, mkexpr( frS ) ); |
| 10552 | |
| 10553 | if (flag_rC && clear_CR1) { |
| 10554 | putCR321( 1, mkU8( 0 ) ); |
| 10555 | putCR0( 1, mkU8( 0 ) ); |
| 10556 | } |
| 10557 | |
| 10558 | return True; |
| 10559 | } |
| 10560 | |
| 10561 | static Bool dis_dfp_extract_insert(UInt theInstr) { |
| 10562 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 10563 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10564 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10565 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10566 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10567 | Bool clear_CR1 = True; |
| 10568 | |
| 10569 | IRTemp frA = newTemp( Ity_D64 ); |
| 10570 | IRTemp frB = newTemp( Ity_D64 ); |
| 10571 | IRTemp frS = newTemp( Ity_D64 ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10572 | IRTemp tmp = newTemp( Ity_I64 ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10573 | |
| 10574 | assign( frA, getDReg( frA_addr ) ); |
| 10575 | assign( frB, getDReg( frB_addr ) ); |
| 10576 | |
| 10577 | switch (opc2) { |
| 10578 | case 0x162: // dxex |
| 10579 | DIP( "dxex%s fr%u,fr%u,fr%u\n", |
| 10580 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10581 | assign( tmp, unop( Iop_ExtractExpD64, mkexpr( frB ) ) ); |
| 10582 | assign( frS, unop( Iop_ReinterpI64asD64, mkexpr( tmp ) ) ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10583 | break; |
| 10584 | case 0x362: // diex |
| 10585 | DIP( "diex%s fr%u,fr%u,fr%u\n", |
| 10586 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10587 | assign( frS, binop( Iop_InsertExpD64, |
| 10588 | unop( Iop_ReinterpD64asI64, |
| 10589 | mkexpr( frA ) ), |
| 10590 | mkexpr( frB ) ) ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10591 | break; |
| 10592 | default: |
| 10593 | vex_printf("dis_dfp_extract_insert(ppc)(opc2)\n"); |
| 10594 | return False; |
| 10595 | } |
| 10596 | |
| 10597 | putDReg( frS_addr, mkexpr( frS ) ); |
| 10598 | |
| 10599 | if (flag_rC && clear_CR1) { |
| 10600 | putCR321( 1, mkU8( 0 ) ); |
| 10601 | putCR0( 1, mkU8( 0 ) ); |
| 10602 | } |
| 10603 | |
| 10604 | return True; |
| 10605 | } |
| 10606 | |
| 10607 | static Bool dis_dfp_extract_insertq(UInt theInstr) { |
| 10608 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 10609 | UChar frS_addr = ifieldRegDS( theInstr ); |
| 10610 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10611 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10612 | UChar flag_rC = ifieldBIT0( theInstr ); |
| 10613 | |
| 10614 | IRTemp frA = newTemp( Ity_D64 ); |
| 10615 | IRTemp frB = newTemp( Ity_D128 ); |
| 10616 | IRTemp frS64 = newTemp( Ity_D64 ); |
| 10617 | IRTemp frS = newTemp( Ity_D128 ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10618 | IRTemp tmp = newTemp( Ity_I64 ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10619 | Bool clear_CR1 = True; |
| 10620 | |
| 10621 | assign( frB, getDReg_pair( frB_addr ) ); |
| 10622 | |
| 10623 | switch (opc2) { |
| 10624 | case 0x162: // dxexq |
| 10625 | DIP( "dxexq%s fr%u,fr%u\n", |
| 10626 | flag_rC ? ".":"", frS_addr, frB_addr ); |
| 10627 | /* Instruction actually returns a 64-bit result. So as to be |
| 10628 | * consistent and not have to add a new struct, the emulation returns |
| 10629 | * the 64-bit result in the upper and lower register. |
| 10630 | */ |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10631 | assign( tmp, unop( Iop_ExtractExpD128, mkexpr( frB ) ) ); |
| 10632 | assign( frS64, unop( Iop_ReinterpI64asD64, mkexpr( tmp ) ) ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10633 | putDReg( frS_addr, mkexpr( frS64 ) ); |
| 10634 | break; |
| 10635 | case 0x362: // diexq |
| 10636 | DIP( "diexq%s fr%u,fr%u,fr%u\n", |
| 10637 | flag_rC ? ".":"", frS_addr, frA_addr, frB_addr ); |
| 10638 | assign( frA, getDReg( frA_addr ) ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10639 | assign( frS, binop( Iop_InsertExpD128, |
| 10640 | unop( Iop_ReinterpD64asI64, mkexpr( frA ) ), |
| 10641 | mkexpr( frB ) ) ); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 10642 | putDReg_pair( frS_addr, mkexpr( frS ) ); |
| 10643 | break; |
| 10644 | default: |
| 10645 | vex_printf("dis_dfp_extract_insertq(ppc)(opc2)\n"); |
| 10646 | return False; |
| 10647 | } |
| 10648 | |
| 10649 | if (flag_rC && clear_CR1) { |
| 10650 | putCR321( 1, mkU8( 0 ) ); |
| 10651 | putCR0( 1, mkU8( 0 ) ); |
| 10652 | } |
| 10653 | |
| 10654 | return True; |
| 10655 | } |
| 10656 | |
| 10657 | /* DFP 64-bit comparison instructions */ |
| 10658 | static Bool dis_dfp_compare(UInt theInstr) { |
| 10659 | /* X-Form */ |
| 10660 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); // AKA BF |
| 10661 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10662 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10663 | UInt opc1 = ifieldOPC( theInstr ); |
| 10664 | IRTemp frA; |
| 10665 | IRTemp frB; |
| 10666 | |
| 10667 | IRTemp ccIR = newTemp( Ity_I32 ); |
| 10668 | IRTemp ccPPC32 = newTemp( Ity_I32 ); |
| 10669 | |
| 10670 | |
| 10671 | /* Note: Differences between dcmpu and dcmpo are only in exception |
| 10672 | flag settings, which aren't supported anyway. */ |
| 10673 | switch (opc1) { |
| 10674 | case 0x3B: /* dcmpo and dcmpu, DFP 64-bit */ |
| 10675 | DIP( "dcmpo %u,fr%u,fr%u\n", crfD, frA_addr, frB_addr ); |
| 10676 | frA = newTemp( Ity_D64 ); |
| 10677 | frB = newTemp( Ity_D64 ); |
| 10678 | |
| 10679 | assign( frA, getDReg( frA_addr ) ); |
| 10680 | assign( frB, getDReg( frB_addr ) ); |
| 10681 | |
| 10682 | assign( ccIR, binop( Iop_CmpD64, mkexpr( frA ), mkexpr( frB ) ) ); |
| 10683 | break; |
| 10684 | case 0x3F: /* dcmpoq and dcmpuq,DFP 128-bit */ |
| 10685 | DIP( "dcmpoq %u,fr%u,fr%u\n", crfD, frA_addr, frB_addr ); |
| 10686 | frA = newTemp( Ity_D128 ); |
| 10687 | frB = newTemp( Ity_D128 ); |
| 10688 | |
| 10689 | assign( frA, getDReg_pair( frA_addr ) ); |
| 10690 | assign( frB, getDReg_pair( frB_addr ) ); |
| 10691 | assign( ccIR, binop( Iop_CmpD128, mkexpr( frA ), mkexpr( frB ) ) ); |
| 10692 | break; |
| 10693 | default: |
| 10694 | vex_printf("dis_dfp_compare(ppc)(opc2)\n"); |
| 10695 | return False; |
| 10696 | } |
| 10697 | |
| 10698 | /* Map compare result from IR to PPC32 */ |
| 10699 | /* |
| 10700 | FP cmp result | PPC | IR |
| 10701 | -------------------------- |
| 10702 | UN | 0x1 | 0x45 |
| 10703 | EQ | 0x2 | 0x40 |
| 10704 | GT | 0x4 | 0x00 |
| 10705 | LT | 0x8 | 0x01 |
| 10706 | */ |
| 10707 | |
| 10708 | assign( ccPPC32, |
| 10709 | binop( Iop_Shl32, |
| 10710 | mkU32( 1 ), |
| 10711 | unop( Iop_32to8, |
| 10712 | binop( Iop_Or32, |
| 10713 | binop( Iop_And32, |
| 10714 | unop( Iop_Not32, |
| 10715 | binop( Iop_Shr32, |
| 10716 | mkexpr( ccIR ), |
| 10717 | mkU8( 5 ) ) ), |
| 10718 | mkU32( 2 ) ), |
| 10719 | binop( Iop_And32, |
| 10720 | binop( Iop_Xor32, |
| 10721 | mkexpr( ccIR ), |
| 10722 | binop( Iop_Shr32, |
| 10723 | mkexpr( ccIR ), |
| 10724 | mkU8( 6 ) ) ), |
| 10725 | mkU32( 1 ) ) ) ) ) ); |
| 10726 | |
| 10727 | putGST_field( PPC_GST_CR, mkexpr( ccPPC32 ), crfD ); |
| 10728 | return True; |
| 10729 | } |
| 10730 | |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 10731 | /* Test class/group/exponent/significance instructions. */ |
| 10732 | static Bool dis_dfp_exponent_test ( UInt theInstr ) |
| 10733 | { |
| 10734 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10735 | UChar frB_addr = ifieldRegB( theInstr ); |
| 10736 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 10737 | IRTemp frA = newTemp( Ity_D64 ); |
| 10738 | IRTemp frB = newTemp( Ity_D64 ); |
| 10739 | IRTemp frA128 = newTemp( Ity_D128 ); |
| 10740 | IRTemp frB128 = newTemp( Ity_D128 ); |
| 10741 | UInt opc1 = ifieldOPC( theInstr ); |
| 10742 | IRTemp gfield_A = newTemp( Ity_I32 ); |
| 10743 | IRTemp gfield_B = newTemp( Ity_I32 ); |
| 10744 | IRTemp gfield_mask = newTemp( Ity_I32 ); |
| 10745 | IRTemp exponent_A = newTemp( Ity_I32 ); |
| 10746 | IRTemp exponent_B = newTemp( Ity_I32 ); |
| 10747 | IRTemp A_NaN_true = newTemp( Ity_I32 ); |
| 10748 | IRTemp B_NaN_true = newTemp( Ity_I32 ); |
| 10749 | IRTemp A_inf_true = newTemp( Ity_I32 ); |
| 10750 | IRTemp B_inf_true = newTemp( Ity_I32 ); |
| 10751 | IRTemp A_equals_B = newTemp( Ity_I32 ); |
| 10752 | IRTemp finite_number = newTemp( Ity_I32 ); |
| 10753 | IRTemp cc0 = newTemp( Ity_I32 ); |
| 10754 | IRTemp cc1 = newTemp( Ity_I32 ); |
| 10755 | IRTemp cc2 = newTemp( Ity_I32 ); |
| 10756 | IRTemp cc3 = newTemp( Ity_I32 ); |
| 10757 | |
| 10758 | /* The dtstex and dtstexg instructions only differ in the size of the |
| 10759 | * exponent field. The following switch statement takes care of the size |
| 10760 | * specific setup. Once the value of the exponents, the G-field shift |
| 10761 | * and mask is setup the remaining code is identical. |
| 10762 | */ |
| 10763 | switch (opc1) { |
| 10764 | case 0x3b: // dtstex Extended instruction setup |
| 10765 | DIP("dtstex %u,r%u,r%d\n", crfD, frA_addr, frB_addr); |
| 10766 | assign( frA, getDReg( frA_addr ) ); |
| 10767 | assign( frB, getDReg( frB_addr ) ); |
| 10768 | assign( gfield_mask, mkU32( DFP_G_FIELD_LONG_MASK ) ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10769 | assign(exponent_A, unop( Iop_64to32, |
| 10770 | unop( Iop_ExtractExpD64, |
| 10771 | mkexpr( frA ) ) ) ); |
| 10772 | assign(exponent_B, unop( Iop_64to32, |
| 10773 | unop( Iop_ExtractExpD64, |
| 10774 | mkexpr( frB ) ) ) ); |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 10775 | break; |
| 10776 | |
| 10777 | case 0x3F: // dtstexq Quad instruction setup |
| 10778 | DIP("dtstexq %u,r%u,r%d\n", crfD, frA_addr, frB_addr); |
| 10779 | assign( frA128, getDReg_pair( frA_addr ) ); |
| 10780 | assign( frB128, getDReg_pair( frB_addr ) ); |
| 10781 | assign( frA, unop( Iop_D128HItoD64, mkexpr( frA128 ) ) ); |
| 10782 | assign( frB, unop( Iop_D128HItoD64, mkexpr( frB128 ) ) ); |
| 10783 | assign( gfield_mask, mkU32( DFP_G_FIELD_EXTND_MASK ) ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10784 | assign( exponent_A, unop( Iop_64to32, |
| 10785 | unop( Iop_ExtractExpD128, |
| 10786 | mkexpr( frA128 ) ) ) ); |
| 10787 | assign( exponent_B, unop( Iop_64to32, |
| 10788 | unop( Iop_ExtractExpD128, |
| 10789 | mkexpr( frB128 ) ) ) ); |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 10790 | break; |
| 10791 | default: |
| 10792 | vex_printf("dis_dfp_exponent_test(ppc)(opc2)\n"); |
| 10793 | return False; |
| 10794 | } |
| 10795 | |
| 10796 | /* Extract the Gfield */ |
| 10797 | assign( gfield_A, binop( Iop_And32, |
| 10798 | mkexpr( gfield_mask ), |
| 10799 | unop( Iop_64HIto32, |
| 10800 | unop( Iop_ReinterpD64asI64, |
| 10801 | mkexpr(frA) ) ) ) ); |
| 10802 | |
| 10803 | assign( gfield_B, binop( Iop_And32, |
| 10804 | mkexpr( gfield_mask ), |
| 10805 | unop( Iop_64HIto32, |
| 10806 | unop( Iop_ReinterpD64asI64, |
| 10807 | mkexpr(frB) ) ) ) ); |
| 10808 | |
| 10809 | /* check for NAN */ |
| 10810 | assign( A_NaN_true, binop(Iop_Or32, |
| 10811 | unop( Iop_1Sto32, |
| 10812 | binop( Iop_CmpEQ32, |
| 10813 | mkexpr( gfield_A ), |
| 10814 | mkU32( 0x7C000000 ) ) ), |
| 10815 | unop( Iop_1Sto32, |
| 10816 | binop( Iop_CmpEQ32, |
| 10817 | mkexpr( gfield_A ), |
| 10818 | mkU32( 0x7E000000 ) ) |
| 10819 | ) ) ); |
| 10820 | assign( B_NaN_true, binop(Iop_Or32, |
| 10821 | unop( Iop_1Sto32, |
| 10822 | binop( Iop_CmpEQ32, |
| 10823 | mkexpr( gfield_B ), |
| 10824 | mkU32( 0x7C000000 ) ) ), |
| 10825 | unop( Iop_1Sto32, |
| 10826 | binop( Iop_CmpEQ32, |
| 10827 | mkexpr( gfield_B ), |
| 10828 | mkU32( 0x7E000000 ) ) |
| 10829 | ) ) ); |
| 10830 | |
| 10831 | /* check for infinity */ |
| 10832 | assign( A_inf_true, |
| 10833 | unop( Iop_1Sto32, |
| 10834 | binop( Iop_CmpEQ32, |
| 10835 | mkexpr( gfield_A ), |
| 10836 | mkU32( 0x78000000 ) ) ) ); |
| 10837 | |
| 10838 | assign( B_inf_true, |
| 10839 | unop( Iop_1Sto32, |
| 10840 | binop( Iop_CmpEQ32, |
| 10841 | mkexpr( gfield_B ), |
| 10842 | mkU32( 0x78000000 ) ) ) ); |
| 10843 | |
| 10844 | assign( finite_number, |
| 10845 | unop( Iop_Not32, |
| 10846 | binop( Iop_Or32, |
| 10847 | binop( Iop_Or32, |
| 10848 | mkexpr( A_NaN_true ), |
| 10849 | mkexpr( B_NaN_true ) ), |
| 10850 | binop( Iop_Or32, |
| 10851 | mkexpr( A_inf_true ), |
| 10852 | mkexpr( B_inf_true ) ) ) ) ); |
| 10853 | |
| 10854 | /* Calculate the condition code bits |
| 10855 | * If QNaN,SNaN, +infinity, -infinity then cc0, cc1 and cc2 are zero |
| 10856 | * regardless of the value of the comparisons and cc3 is 1. Otherwise, |
| 10857 | * cc0, cc1 and cc0 reflect the results of the comparisons. |
| 10858 | */ |
| 10859 | assign( A_equals_B, |
| 10860 | binop( Iop_Or32, |
| 10861 | unop( Iop_1Uto32, |
| 10862 | binop( Iop_CmpEQ32, |
| 10863 | mkexpr( exponent_A ), |
| 10864 | mkexpr( exponent_B ) ) ), |
| 10865 | binop( Iop_Or32, |
| 10866 | binop( Iop_And32, |
| 10867 | mkexpr( A_inf_true ), |
| 10868 | mkexpr( B_inf_true ) ), |
| 10869 | binop( Iop_And32, |
| 10870 | mkexpr( A_NaN_true ), |
| 10871 | mkexpr( B_NaN_true ) ) ) ) ); |
| 10872 | |
| 10873 | assign( cc0, binop( Iop_And32, |
| 10874 | mkexpr( finite_number ), |
| 10875 | binop( Iop_Shl32, |
| 10876 | unop( Iop_1Uto32, |
| 10877 | binop( Iop_CmpLT32U, |
| 10878 | mkexpr( exponent_A ), |
| 10879 | mkexpr( exponent_B ) ) ), |
| 10880 | mkU8( 3 ) ) ) ); |
| 10881 | |
| 10882 | assign( cc1, binop( Iop_And32, |
| 10883 | mkexpr( finite_number ), |
| 10884 | binop( Iop_Shl32, |
| 10885 | unop( Iop_1Uto32, |
| 10886 | binop( Iop_CmpLT32U, |
| 10887 | mkexpr( exponent_B ), |
| 10888 | mkexpr( exponent_A ) ) ), |
| 10889 | mkU8( 2 ) ) ) ); |
| 10890 | |
| 10891 | assign( cc2, binop( Iop_Shl32, |
| 10892 | binop( Iop_And32, |
| 10893 | mkexpr( A_equals_B ), |
| 10894 | mkU32( 1 ) ), |
| 10895 | mkU8( 1 ) ) ); |
| 10896 | |
| 10897 | assign( cc3, binop( Iop_And32, |
| 10898 | unop( Iop_Not32, mkexpr( A_equals_B ) ), |
| 10899 | binop( Iop_And32, |
| 10900 | mkU32( 0x1 ), |
| 10901 | binop( Iop_Or32, |
| 10902 | binop( Iop_Or32, |
| 10903 | mkexpr ( A_inf_true ), |
| 10904 | mkexpr ( B_inf_true ) ), |
| 10905 | binop( Iop_Or32, |
| 10906 | mkexpr ( A_NaN_true ), |
| 10907 | mkexpr ( B_NaN_true ) ) ) |
| 10908 | ) ) ); |
| 10909 | |
| 10910 | /* store the condition code */ |
| 10911 | putGST_field( PPC_GST_CR, |
| 10912 | binop( Iop_Or32, |
| 10913 | mkexpr( cc0 ), |
| 10914 | binop( Iop_Or32, |
| 10915 | mkexpr( cc1 ), |
| 10916 | binop( Iop_Or32, |
| 10917 | mkexpr( cc2 ), |
| 10918 | mkexpr( cc3 ) ) ) ), |
| 10919 | crfD ); |
| 10920 | return True; |
| 10921 | } |
| 10922 | |
| 10923 | /* Test class/group/exponent/significance instructions. */ |
| 10924 | static Bool dis_dfp_class_test ( UInt theInstr ) |
| 10925 | { |
| 10926 | UChar frA_addr = ifieldRegA( theInstr ); |
| 10927 | IRTemp frA = newTemp( Ity_D64 ); |
| 10928 | IRTemp abs_frA = newTemp( Ity_D64 ); |
| 10929 | IRTemp frAI64_hi = newTemp( Ity_I64 ); |
| 10930 | IRTemp frAI64_lo = newTemp( Ity_I64 ); |
| 10931 | UInt opc1 = ifieldOPC( theInstr ); |
| 10932 | UInt opc2 = ifieldOPClo9( theInstr ); |
| 10933 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); // AKA BF |
| 10934 | UInt DCM = IFIELD( theInstr, 10, 6 ); |
| 10935 | IRTemp DCM_calc = newTemp( Ity_I32 ); |
| 10936 | UInt max_exp = 0; |
| 10937 | UInt min_exp = 0; |
| 10938 | IRTemp min_subnormalD64 = newTemp( Ity_D64 ); |
| 10939 | IRTemp min_subnormalD128 = newTemp( Ity_D128 ); |
| 10940 | IRTemp significand64 = newTemp( Ity_D64 ); |
| 10941 | IRTemp significand128 = newTemp( Ity_D128 ); |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 10942 | IRTemp exp_min_normal = newTemp( Ity_I64 ); |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 10943 | IRTemp exponent = newTemp( Ity_I32 ); |
| 10944 | |
| 10945 | IRTemp infinity_true = newTemp( Ity_I32 ); |
| 10946 | IRTemp SNaN_true = newTemp( Ity_I32 ); |
| 10947 | IRTemp QNaN_true = newTemp( Ity_I32 ); |
| 10948 | IRTemp subnormal_true = newTemp( Ity_I32 ); |
| 10949 | IRTemp normal_true = newTemp( Ity_I32 ); |
| 10950 | IRTemp extreme_true = newTemp( Ity_I32 ); |
| 10951 | IRTemp lmd = newTemp( Ity_I32 ); |
| 10952 | IRTemp lmd_zero_true = newTemp( Ity_I32 ); |
| 10953 | IRTemp zero_true = newTemp( Ity_I32 ); |
| 10954 | IRTemp sign = newTemp( Ity_I32 ); |
| 10955 | IRTemp field = newTemp( Ity_I32 ); |
| 10956 | IRTemp ccIR_zero = newTemp( Ity_I32 ); |
| 10957 | IRTemp ccIR_subnormal = newTemp( Ity_I32 ); |
| 10958 | |
| 10959 | /* UInt size = DFP_LONG; JRS:unused */ |
| 10960 | IRTemp gfield = newTemp( Ity_I32 ); |
| 10961 | IRTemp gfield_0_4_shift = newTemp( Ity_I8 ); |
| 10962 | IRTemp gfield_mask = newTemp( Ity_I32 ); |
| 10963 | IRTemp dcm0 = newTemp( Ity_I32 ); |
| 10964 | IRTemp dcm1 = newTemp( Ity_I32 ); |
| 10965 | IRTemp dcm2 = newTemp( Ity_I32 ); |
| 10966 | IRTemp dcm3 = newTemp( Ity_I32 ); |
| 10967 | IRTemp dcm4 = newTemp( Ity_I32 ); |
| 10968 | IRTemp dcm5 = newTemp( Ity_I32 ); |
| 10969 | |
| 10970 | /* The only difference between the dtstdc and dtstdcq instructions is |
| 10971 | * size of the T and G fields. The calculation of the 4 bit field |
| 10972 | * is the same. Setup the parameters and values that are DFP size |
| 10973 | * specific. The rest of the code is independent of the DFP size. |
| 10974 | * |
| 10975 | * The Io_CmpD64 is used below. The instruction sets the ccIR values. |
| 10976 | * The interpretation of the ccIR values is as follows: |
| 10977 | * |
| 10978 | * DFP cmp result | IR |
| 10979 | * -------------------------- |
| 10980 | * UN | 0x45 |
| 10981 | * EQ | 0x40 |
| 10982 | * GT | 0x00 |
| 10983 | * LT | 0x01 |
| 10984 | */ |
| 10985 | |
| 10986 | assign( frA, getDReg( frA_addr ) ); |
| 10987 | assign( frAI64_hi, unop( Iop_ReinterpD64asI64, mkexpr( frA ) ) ); |
| 10988 | |
| 10989 | assign( abs_frA, unop( Iop_ReinterpI64asD64, |
| 10990 | binop( Iop_And64, |
| 10991 | unop( Iop_ReinterpD64asI64, |
| 10992 | mkexpr( frA ) ), |
| 10993 | mkU64( 0x7FFFFFFFFFFFFFFFULL ) ) ) ); |
| 10994 | assign( gfield_0_4_shift, mkU8( 31 - 5 ) ); // G-field[0:4] |
| 10995 | switch (opc1) { |
| 10996 | case 0x3b: // dtstdc, dtstdg |
| 10997 | DIP("dtstd%s %u,r%u,%d\n", opc2 == 0xc2 ? "c" : "g", |
| 10998 | crfD, frA_addr, DCM); |
| 10999 | /* setup the parameters for the long format of the two instructions */ |
| 11000 | assign( frAI64_lo, mkU64( 0 ) ); |
| 11001 | assign( gfield_mask, mkU32( DFP_G_FIELD_LONG_MASK ) ); |
| 11002 | max_exp = DFP_LONG_EXP_MAX; |
| 11003 | min_exp = DFP_LONG_EXP_MIN; |
| 11004 | |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 11005 | assign( exponent, unop( Iop_64to32, |
| 11006 | unop( Iop_ExtractExpD64, |
| 11007 | mkexpr( frA ) ) ) ); |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 11008 | assign( significand64, |
| 11009 | unop( Iop_ReinterpI64asD64, |
| 11010 | mkU64( 0x2234000000000001ULL ) ) ); // dfp 1.0 |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 11011 | assign( exp_min_normal,mkU64( 398 - 383 ) ); |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 11012 | assign( min_subnormalD64, |
| 11013 | binop( Iop_InsertExpD64, |
| 11014 | mkexpr( exp_min_normal ), |
| 11015 | mkexpr( significand64 ) ) ); |
| 11016 | |
| 11017 | assign( ccIR_subnormal, |
| 11018 | binop( Iop_CmpD64, |
| 11019 | mkexpr( abs_frA ), |
| 11020 | mkexpr( min_subnormalD64 ) ) ); |
| 11021 | |
| 11022 | /* compare absolute value of frA with zero */ |
| 11023 | assign( ccIR_zero, |
| 11024 | binop( Iop_CmpD64, |
| 11025 | mkexpr( abs_frA ), |
| 11026 | unop( Iop_ReinterpI64asD64, |
| 11027 | mkU64( 0x2238000000000000ULL ) ) ) ); |
| 11028 | |
| 11029 | /* size = DFP_LONG; JRS: unused */ |
| 11030 | break; |
| 11031 | |
| 11032 | case 0x3F: // dtstdcq, dtstdgq |
| 11033 | DIP("dtstd%sq %u,r%u,%d\n", opc2 == 0xc2 ? "c" : "g", |
| 11034 | crfD, frA_addr, DCM); |
| 11035 | /* setup the parameters for the extended format of the |
| 11036 | * two instructions |
| 11037 | */ |
| 11038 | assign( frAI64_lo, unop( Iop_ReinterpD64asI64, |
| 11039 | getDReg( frA_addr+1 ) ) ); |
| 11040 | |
| 11041 | assign( gfield_mask, mkU32( DFP_G_FIELD_EXTND_MASK ) ); |
| 11042 | max_exp = DFP_EXTND_EXP_MAX; |
| 11043 | min_exp = DFP_EXTND_EXP_MIN; |
| 11044 | assign( exponent, unop( Iop_64to32, |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 11045 | unop( Iop_ExtractExpD128, |
| 11046 | getDReg_pair( frA_addr) ) ) ); |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 11047 | |
| 11048 | /* create quand exponent for minimum normal number */ |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 11049 | assign( exp_min_normal, mkU64( 6176 - 6143 ) ); |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 11050 | assign( significand128, |
| 11051 | unop( Iop_D64toD128, |
| 11052 | unop( Iop_ReinterpI64asD64, |
| 11053 | mkU64( 0x2234000000000001ULL ) ) ) ); // dfp 1.0 |
| 11054 | |
| 11055 | assign( min_subnormalD128, |
| 11056 | binop( Iop_InsertExpD128, |
| 11057 | mkexpr( exp_min_normal ), |
| 11058 | mkexpr( significand128 ) ) ); |
| 11059 | |
| 11060 | assign( ccIR_subnormal, |
| 11061 | binop( Iop_CmpD128, |
| 11062 | binop( Iop_D64HLtoD128, |
| 11063 | unop( Iop_ReinterpI64asD64, |
| 11064 | binop( Iop_And64, |
| 11065 | unop( Iop_ReinterpD64asI64, |
| 11066 | mkexpr( frA ) ), |
| 11067 | mkU64( 0x7FFFFFFFFFFFFFFFULL ) ) ), |
| 11068 | getDReg( frA_addr+1 ) ), |
| 11069 | mkexpr( min_subnormalD128 ) ) ); |
| 11070 | assign( ccIR_zero, |
| 11071 | binop( Iop_CmpD128, |
| 11072 | binop( Iop_D64HLtoD128, |
| 11073 | mkexpr( abs_frA ), |
| 11074 | getDReg( frA_addr+1 ) ), |
| 11075 | unop( Iop_D64toD128, |
| 11076 | unop( Iop_ReinterpI64asD64, |
| 11077 | mkU64( 0x0ULL ) ) ) ) ); |
| 11078 | |
| 11079 | /* size = DFP_EXTND; JRS:unused */ |
| 11080 | break; |
| 11081 | default: |
| 11082 | vex_printf("dis_dfp_class_test(ppc)(opc2)\n"); |
| 11083 | return False; |
| 11084 | } |
| 11085 | |
| 11086 | /* The G-field is in the upper 32-bits. The I64 logical operations |
| 11087 | * do not seem to be supported in 32-bit mode so keep things as 32-bit |
| 11088 | * operations. |
| 11089 | */ |
| 11090 | assign( gfield, binop( Iop_And32, |
| 11091 | mkexpr( gfield_mask ), |
| 11092 | unop( Iop_64HIto32, |
| 11093 | mkexpr(frAI64_hi) ) ) ); |
| 11094 | |
| 11095 | /* There is a lot of code that is the same to do the class and group |
| 11096 | * instructions. Later there is an if statement to handle the specific |
| 11097 | * instruction. |
| 11098 | * |
| 11099 | * Will be using I32 values, compares, shifts and logical operations for |
| 11100 | * this code as the 64-bit compare, shifts, logical operations are not |
| 11101 | * supported in 32-bit mode. |
| 11102 | */ |
| 11103 | |
| 11104 | /* Check the bits for Infinity, QNaN or Signaling NaN */ |
| 11105 | assign( infinity_true, |
| 11106 | unop( Iop_1Sto32, |
| 11107 | binop( Iop_CmpEQ32, |
| 11108 | binop( Iop_And32, |
| 11109 | mkU32( 0x7C000000 ), |
| 11110 | mkexpr( gfield ) ), |
| 11111 | mkU32( 0x78000000 ) ) ) ); |
| 11112 | |
| 11113 | assign( SNaN_true, |
| 11114 | unop( Iop_1Sto32, |
| 11115 | binop( Iop_CmpEQ32, |
| 11116 | binop( Iop_And32, |
| 11117 | mkU32( 0x7E000000 ), |
| 11118 | mkexpr( gfield ) ), |
| 11119 | mkU32( 0x7E000000 ) ) ) ); |
| 11120 | |
| 11121 | assign( QNaN_true, |
| 11122 | binop( Iop_And32, |
| 11123 | unop( Iop_1Sto32, |
| 11124 | binop( Iop_CmpEQ32, |
| 11125 | binop( Iop_And32, |
| 11126 | mkU32( 0x7E000000 ), |
| 11127 | mkexpr( gfield ) ), |
| 11128 | mkU32( 0x7C000000 ) ) ), |
| 11129 | unop( Iop_Not32, |
| 11130 | mkexpr( SNaN_true ) ) ) ); |
| 11131 | |
| 11132 | assign( zero_true, |
| 11133 | binop( Iop_And32, |
| 11134 | unop(Iop_1Sto32, |
| 11135 | binop( Iop_CmpEQ32, |
| 11136 | mkexpr( ccIR_zero ), |
| 11137 | mkU32( 0x40 ) ) ), // ccIR code for Equal |
| 11138 | unop( Iop_Not32, |
| 11139 | binop( Iop_Or32, |
| 11140 | mkexpr( infinity_true ), |
| 11141 | binop( Iop_Or32, |
| 11142 | mkexpr( QNaN_true ), |
| 11143 | mkexpr( SNaN_true ) ) ) ) ) ); |
| 11144 | |
| 11145 | /* Do compare of frA the minimum normal value. Comparison is size |
| 11146 | * depenent and was done above to get the ccIR value. |
| 11147 | */ |
| 11148 | assign( subnormal_true, |
| 11149 | binop( Iop_And32, |
| 11150 | binop( Iop_Or32, |
| 11151 | unop( Iop_1Sto32, |
| 11152 | binop( Iop_CmpEQ32, |
| 11153 | mkexpr( ccIR_subnormal ), |
| 11154 | mkU32( 0x40 ) ) ), // ccIR code for Equal |
| 11155 | unop( Iop_1Sto32, |
| 11156 | binop( Iop_CmpEQ32, |
| 11157 | mkexpr( ccIR_subnormal ), |
| 11158 | mkU32( 0x1 ) ) ) ), // ccIR code for LT |
| 11159 | unop( Iop_Not32, |
| 11160 | binop( Iop_Or32, |
| 11161 | binop( Iop_Or32, |
| 11162 | mkexpr( infinity_true ), |
| 11163 | mkexpr( zero_true) ), |
| 11164 | binop( Iop_Or32, |
| 11165 | mkexpr( QNaN_true ), |
| 11166 | mkexpr( SNaN_true ) ) ) ) ) ); |
| 11167 | |
| 11168 | /* Normal number is not subnormal, infinity, NaN or Zero */ |
| 11169 | assign( normal_true, |
| 11170 | unop( Iop_Not32, |
| 11171 | binop( Iop_Or32, |
| 11172 | binop( Iop_Or32, |
| 11173 | mkexpr( infinity_true ), |
| 11174 | mkexpr( zero_true ) ), |
| 11175 | binop( Iop_Or32, |
| 11176 | mkexpr( subnormal_true ), |
| 11177 | binop( Iop_Or32, |
| 11178 | mkexpr( QNaN_true ), |
| 11179 | mkexpr( SNaN_true ) ) ) ) ) ); |
| 11180 | |
| 11181 | /* Calculate the DCM bit field based on the tests for the specific |
| 11182 | * instruction |
| 11183 | */ |
| 11184 | if (opc2 == 0xC2) { // dtstdc, dtstdcq |
| 11185 | /* DCM[0:5] Bit Data Class definition |
| 11186 | * 0 Zero |
| 11187 | * 1 Subnormal |
| 11188 | * 2 Normal |
| 11189 | * 3 Infinity |
| 11190 | * 4 Quiet NaN |
| 11191 | * 5 Signaling NaN |
| 11192 | */ |
| 11193 | |
| 11194 | assign( dcm0, binop( Iop_Shl32, |
| 11195 | mkexpr( zero_true ), |
| 11196 | mkU8( 5 ) ) ); |
| 11197 | assign( dcm1, binop( Iop_Shl32, |
| 11198 | binop( Iop_And32, |
| 11199 | mkexpr( subnormal_true ), |
| 11200 | mkU32( 1 ) ), |
| 11201 | mkU8( 4 ) ) ); |
| 11202 | assign( dcm2, binop( Iop_Shl32, |
| 11203 | binop( Iop_And32, |
| 11204 | mkexpr( normal_true ), |
| 11205 | mkU32( 1 ) ), |
| 11206 | mkU8( 3 ) ) ); |
| 11207 | assign( dcm3, binop( Iop_Shl32, |
| 11208 | binop( Iop_And32, |
| 11209 | mkexpr( infinity_true), |
| 11210 | mkU32( 1 ) ), |
| 11211 | mkU8( 2 ) ) ); |
| 11212 | assign( dcm4, binop( Iop_Shl32, |
| 11213 | binop( Iop_And32, |
| 11214 | mkexpr( QNaN_true ), |
| 11215 | mkU32( 1 ) ), |
| 11216 | mkU8( 1 ) ) ); |
| 11217 | assign( dcm5, binop( Iop_And32, mkexpr( SNaN_true), mkU32( 1 ) ) ); |
| 11218 | |
| 11219 | } else if (opc2 == 0xE2) { // dtstdg, dtstdgq |
| 11220 | /* check if the exponent is extreme */ |
| 11221 | assign( extreme_true, binop( Iop_Or32, |
| 11222 | unop( Iop_1Sto32, |
| 11223 | binop( Iop_CmpEQ32, |
| 11224 | mkexpr( exponent ), |
| 11225 | mkU32( max_exp ) ) ), |
| 11226 | unop( Iop_1Sto32, |
| 11227 | binop( Iop_CmpEQ32, |
| 11228 | mkexpr( exponent ), |
| 11229 | mkU32( min_exp ) ) ) ) ); |
| 11230 | |
| 11231 | /* Check if LMD is zero */ |
| 11232 | Get_lmd( &lmd, binop( Iop_Shr32, |
| 11233 | mkexpr( gfield ), mkU8( 31 - 5 ) ) ); |
| 11234 | |
| 11235 | assign( lmd_zero_true, unop( Iop_1Sto32, |
| 11236 | binop( Iop_CmpEQ32, |
| 11237 | mkexpr( lmd ), |
| 11238 | mkU32( 0 ) ) ) ); |
| 11239 | |
| 11240 | /* DCM[0:5] Bit Data Class definition |
| 11241 | * 0 Zero with non-extreme exponent |
| 11242 | * 1 Zero with extreme exponent |
| 11243 | * 2 Subnormal or (Normal with extreme exponent) |
| 11244 | * 3 Normal with non-extreme exponent and |
| 11245 | * leftmost zero digit in significand |
| 11246 | * 4 Normal with non-extreme exponent and |
| 11247 | * leftmost nonzero digit in significand |
| 11248 | * 5 Special symbol (Infinity, QNaN, or SNaN) |
| 11249 | */ |
| 11250 | assign( dcm0, binop( Iop_Shl32, |
| 11251 | binop( Iop_And32, |
| 11252 | binop( Iop_And32, |
| 11253 | unop( Iop_Not32, |
| 11254 | mkexpr( extreme_true ) ), |
| 11255 | mkexpr( zero_true ) ), |
| 11256 | mkU32( 0x1 ) ), |
| 11257 | mkU8( 5 ) ) ); |
| 11258 | |
| 11259 | assign( dcm1, binop( Iop_Shl32, |
| 11260 | binop( Iop_And32, |
| 11261 | binop( Iop_And32, |
| 11262 | mkexpr( extreme_true ), |
| 11263 | mkexpr( zero_true ) ), |
| 11264 | mkU32( 0x1 ) ), |
| 11265 | mkU8( 4 ) ) ); |
| 11266 | |
| 11267 | assign( dcm2, binop( Iop_Shl32, |
| 11268 | binop( Iop_And32, |
| 11269 | binop( Iop_Or32, |
| 11270 | binop( Iop_And32, |
| 11271 | mkexpr( extreme_true ), |
| 11272 | mkexpr( normal_true ) ), |
| 11273 | mkexpr( subnormal_true ) ), |
| 11274 | mkU32( 0x1 ) ), |
| 11275 | mkU8( 3 ) ) ); |
| 11276 | |
| 11277 | assign( dcm3, binop( Iop_Shl32, |
| 11278 | binop( Iop_And32, |
| 11279 | binop( Iop_And32, |
| 11280 | binop( Iop_And32, |
| 11281 | unop( Iop_Not32, |
| 11282 | mkexpr( extreme_true ) ), |
| 11283 | mkexpr( normal_true ) ), |
| 11284 | unop( Iop_1Sto32, |
| 11285 | binop( Iop_CmpEQ32, |
| 11286 | mkexpr( lmd ), |
| 11287 | mkU32( 0 ) ) ) ), |
| 11288 | mkU32( 0x1 ) ), |
| 11289 | mkU8( 2 ) ) ); |
| 11290 | |
| 11291 | assign( dcm4, binop( Iop_Shl32, |
| 11292 | binop( Iop_And32, |
| 11293 | binop( Iop_And32, |
| 11294 | binop( Iop_And32, |
| 11295 | unop( Iop_Not32, |
| 11296 | mkexpr( extreme_true ) ), |
| 11297 | mkexpr( normal_true ) ), |
| 11298 | unop( Iop_1Sto32, |
| 11299 | binop( Iop_CmpNE32, |
| 11300 | mkexpr( lmd ), |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 11301 | mkU32( 0 ) ) ) ), |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 11302 | mkU32( 0x1 ) ), |
| 11303 | mkU8( 1 ) ) ); |
| 11304 | |
| 11305 | assign( dcm5, binop( Iop_And32, |
| 11306 | binop( Iop_Or32, |
| 11307 | mkexpr( SNaN_true), |
| 11308 | binop( Iop_Or32, |
| 11309 | mkexpr( QNaN_true), |
| 11310 | mkexpr( infinity_true) ) ), |
| 11311 | mkU32( 0x1 ) ) ); |
| 11312 | } |
| 11313 | |
| 11314 | /* create DCM field */ |
| 11315 | assign( DCM_calc, |
| 11316 | binop( Iop_Or32, |
| 11317 | mkexpr( dcm0 ), |
| 11318 | binop( Iop_Or32, |
| 11319 | mkexpr( dcm1 ), |
| 11320 | binop( Iop_Or32, |
| 11321 | mkexpr( dcm2 ), |
| 11322 | binop( Iop_Or32, |
| 11323 | mkexpr( dcm3 ), |
| 11324 | binop( Iop_Or32, |
| 11325 | mkexpr( dcm4 ), |
| 11326 | mkexpr( dcm5 ) ) ) ) ) ) ); |
| 11327 | |
| 11328 | /* Get the sign of the DFP number, ignore sign for QNaN */ |
| 11329 | assign( sign, |
| 11330 | unop( Iop_1Uto32, |
| 11331 | binop( Iop_CmpEQ32, |
| 11332 | binop( Iop_Shr32, |
| 11333 | unop( Iop_64HIto32, mkexpr( frAI64_hi ) ), |
| 11334 | mkU8( 63 - 32 ) ), |
| 11335 | mkU32( 1 ) ) ) ); |
| 11336 | |
| 11337 | /* This instruction generates a four bit field to be stored in the |
| 11338 | * condition code register. The condition code register consists of 7 |
| 11339 | * fields. The field to be written to is specified by the BF (AKA crfD) |
| 11340 | * field. |
| 11341 | * |
| 11342 | * The field layout is as follows: |
| 11343 | * |
| 11344 | * Field Meaning |
| 11345 | * 0000 Operand positive with no match |
| 11346 | * 0100 Operand positive with at least one match |
| 11347 | * 0001 Operand negative with no match |
| 11348 | * 0101 Operand negative with at least one match |
| 11349 | */ |
| 11350 | assign( field, binop( Iop_Or32, |
| 11351 | binop( Iop_Shl32, |
| 11352 | mkexpr( sign ), |
| 11353 | mkU8( 3 ) ), |
| 11354 | binop( Iop_Shl32, |
| 11355 | unop( Iop_1Uto32, |
| 11356 | binop( Iop_CmpNE32, |
| 11357 | binop( Iop_And32, |
| 11358 | mkU32( DCM ), |
| 11359 | mkexpr( DCM_calc ) ), |
| 11360 | mkU32( 0 ) ) ), |
| 11361 | mkU8( 1 ) ) ) ); |
| 11362 | |
| 11363 | putGST_field( PPC_GST_CR, mkexpr( field ), crfD ); |
| 11364 | return True; |
| 11365 | } |
| 11366 | |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 11367 | static Bool dis_dfp_bcd(UInt theInstr) { |
| 11368 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 11369 | ULong sp = IFIELD(theInstr, 19, 2); |
| 11370 | ULong s = IFIELD(theInstr, 20, 1); |
| 11371 | UChar frT_addr = ifieldRegDS( theInstr ); |
| 11372 | UChar frB_addr = ifieldRegB( theInstr ); |
| 11373 | IRTemp frB = newTemp( Ity_D64 ); |
| 11374 | IRTemp frBI64 = newTemp( Ity_I64 ); |
| 11375 | IRTemp result = newTemp( Ity_I64 ); |
| 11376 | IRTemp resultD64 = newTemp( Ity_D64 ); |
| 11377 | IRTemp bcd64 = newTemp( Ity_I64 ); |
| 11378 | IRTemp bcd_u = newTemp( Ity_I32 ); |
| 11379 | IRTemp bcd_l = newTemp( Ity_I32 ); |
| 11380 | IRTemp dbcd_u = newTemp( Ity_I32 ); |
| 11381 | IRTemp dbcd_l = newTemp( Ity_I32 ); |
| 11382 | IRTemp lmd = newTemp( Ity_I32 ); |
| 11383 | |
| 11384 | assign( frB, getDReg( frB_addr ) ); |
| 11385 | assign( frBI64, unop( Iop_ReinterpD64asI64, mkexpr( frB ) ) ); |
| 11386 | |
| 11387 | switch ( opc2 ) { |
| 11388 | case 0x142: // ddedpd DFP Decode DPD to BCD |
| 11389 | DIP( "ddedpd %llu,r%u,r%u\n", sp, frT_addr, frB_addr ); |
| 11390 | |
| 11391 | assign( bcd64, unop( Iop_DPBtoBCD, mkexpr( frBI64 ) ) ); |
| 11392 | assign( bcd_u, unop( Iop_64HIto32, mkexpr( bcd64 ) ) ); |
| 11393 | assign( bcd_l, unop( Iop_64to32, mkexpr( bcd64 ) ) ); |
| 11394 | |
| 11395 | if ( ( sp == 0 ) || ( sp == 1 ) ) { |
| 11396 | /* Unsigned BCD string */ |
| 11397 | Get_lmd( &lmd, |
| 11398 | binop( Iop_Shr32, |
| 11399 | unop( Iop_64HIto32, mkexpr( frBI64 ) ), |
| 11400 | mkU8( 31 - 5 ) ) ); // G-field[0:4] |
| 11401 | |
| 11402 | assign( result, |
| 11403 | binop( Iop_32HLto64, |
| 11404 | binop( Iop_Or32, |
| 11405 | binop( Iop_Shl32, mkexpr( lmd ), mkU8( 28 ) ), |
| 11406 | mkexpr( bcd_u ) ), |
| 11407 | mkexpr( bcd_l ) ) ); |
| 11408 | |
| 11409 | } else { |
| 11410 | /* Signed BCD string, the cases for sp 2 and 3 only differ in how |
| 11411 | * the positive and negative values are encoded in the least |
| 11412 | * significant bits. |
| 11413 | */ |
| 11414 | IRTemp sign = newTemp( Ity_I32 ); |
| 11415 | |
| 11416 | if (sp == 2) { |
| 11417 | /* Positive sign = 0xC, negative sign = 0xD */ |
| 11418 | |
| 11419 | assign( sign, |
| 11420 | binop( Iop_Or32, |
| 11421 | binop( Iop_Shr32, |
| 11422 | unop( Iop_64HIto32, mkexpr( frBI64 ) ), |
| 11423 | mkU8( 31 ) ), |
| 11424 | mkU32( 0xC ) ) ); |
| 11425 | |
| 11426 | } else if ( sp == 3 ) { |
| 11427 | /* Positive sign = 0xF, negative sign = 0xD */ |
| 11428 | IRTemp tmp32 = newTemp( Ity_I32 ); |
| 11429 | |
| 11430 | /* Complement sign bit then OR into bit position 1 */ |
| 11431 | assign( tmp32, |
| 11432 | binop( Iop_Xor32, |
| 11433 | binop( Iop_Shr32, |
| 11434 | unop( Iop_64HIto32, mkexpr( frBI64 ) ), |
| 11435 | mkU8( 30 ) ), |
| 11436 | mkU32( 0x2 ) ) ); |
| 11437 | |
| 11438 | assign( sign, binop( Iop_Or32, mkexpr( tmp32 ), mkU32( 0xD ) ) ); |
| 11439 | |
| 11440 | } else { |
| 11441 | vpanic( "The impossible happened: dis_dfp_bcd(ppc), undefined SP field" ); |
| 11442 | } |
| 11443 | |
| 11444 | /* Put sign in bottom 4 bits, move most significant 4-bits from |
| 11445 | * bcd_l to bcd_u. |
| 11446 | */ |
| 11447 | assign( result, |
| 11448 | binop( Iop_32HLto64, |
| 11449 | binop( Iop_Or32, |
| 11450 | binop( Iop_Shr32, |
| 11451 | mkexpr( bcd_l ), |
| 11452 | mkU8( 28 ) ), |
| 11453 | binop( Iop_Shl32, |
| 11454 | mkexpr( bcd_u ), |
| 11455 | mkU8( 4 ) ) ), |
| 11456 | binop( Iop_Or32, |
| 11457 | mkexpr( sign ), |
| 11458 | binop( Iop_Shl32, |
| 11459 | mkexpr( bcd_l ), |
| 11460 | mkU8( 4 ) ) ) ) ); |
| 11461 | } |
| 11462 | |
| 11463 | putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result ) ) ); |
| 11464 | break; |
| 11465 | |
| 11466 | case 0x342: // denbcd DFP Encode BCD to DPD |
| 11467 | { |
| 11468 | IRTemp valid_mask = newTemp( Ity_I32 ); |
| 11469 | IRTemp invalid_mask = newTemp( Ity_I32 ); |
| 11470 | IRTemp without_lmd = newTemp( Ity_I64 ); |
| 11471 | IRTemp tmp64 = newTemp( Ity_I64 ); |
| 11472 | IRTemp dbcd64 = newTemp( Ity_I64 ); |
| 11473 | IRTemp left_exp = newTemp( Ity_I32 ); |
| 11474 | IRTemp g0_4 = newTemp( Ity_I32 ); |
| 11475 | |
| 11476 | DIP( "denbcd %llu,r%u,r%u\n", s, frT_addr, frB_addr ); |
| 11477 | |
| 11478 | if ( s == 0 ) { |
| 11479 | /* Unsigned BCD string */ |
| 11480 | assign( dbcd64, unop( Iop_BCDtoDPB, mkexpr(frBI64 ) ) ); |
| 11481 | assign( dbcd_u, unop( Iop_64HIto32, mkexpr( dbcd64 ) ) ); |
| 11482 | assign( dbcd_l, unop( Iop_64to32, mkexpr( dbcd64 ) ) ); |
| 11483 | |
| 11484 | assign( lmd, |
| 11485 | binop( Iop_Shr32, |
| 11486 | binop( Iop_And32, |
| 11487 | unop( Iop_64HIto32, mkexpr( frBI64 ) ), |
| 11488 | mkU32( 0xF0000000 ) ), |
| 11489 | mkU8( 28 ) ) ); |
| 11490 | |
| 11491 | assign( invalid_mask, |
| 11492 | bcd_digit_inval( unop( Iop_64HIto32, mkexpr( frBI64 ) ), |
| 11493 | unop( Iop_64to32, mkexpr( frBI64 ) ) ) ); |
| 11494 | assign( valid_mask, unop( Iop_Not32, mkexpr( invalid_mask ) ) ); |
| 11495 | |
| 11496 | assign( without_lmd, |
| 11497 | unop( Iop_ReinterpD64asI64, |
| 11498 | binop( Iop_InsertExpD64, |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 11499 | mkU64( DFP_LONG_BIAS ), |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 11500 | unop( Iop_ReinterpI64asD64, |
| 11501 | binop( Iop_32HLto64, |
| 11502 | mkexpr( dbcd_u ), |
| 11503 | mkexpr( dbcd_l ) ) ) ) ) ); |
| 11504 | assign( left_exp, |
| 11505 | binop( Iop_Shr32, |
| 11506 | binop( Iop_And32, |
| 11507 | unop( Iop_64HIto32, mkexpr( without_lmd ) ), |
| 11508 | mkU32( 0x60000000 ) ), |
| 11509 | mkU8( 29 ) ) ); |
| 11510 | |
| 11511 | assign( g0_4, |
| 11512 | binop( Iop_Shl32, |
| 11513 | Gfield_encoding( mkexpr( left_exp ), mkexpr( lmd ) ), |
| 11514 | mkU8( 26 ) ) ); |
| 11515 | |
| 11516 | assign( tmp64, |
| 11517 | binop( Iop_32HLto64, |
| 11518 | binop( Iop_Or32, |
| 11519 | binop( Iop_And32, |
| 11520 | unop( Iop_64HIto32, |
| 11521 | mkexpr( without_lmd ) ), |
| 11522 | mkU32( 0x83FFFFFF ) ), |
| 11523 | mkexpr( g0_4 ) ), |
| 11524 | unop( Iop_64to32, mkexpr( without_lmd ) ) ) ); |
| 11525 | |
| 11526 | } else if ( s == 1 ) { |
| 11527 | IRTemp sign = newTemp( Ity_I32 ); |
| 11528 | IRTemp sign_bit = newTemp( Ity_I32 ); |
| 11529 | IRTemp pos_sign_mask = newTemp( Ity_I32 ); |
| 11530 | IRTemp neg_sign_mask = newTemp( Ity_I32 ); |
| 11531 | IRTemp tmp = newTemp( Ity_I64 ); |
| 11532 | |
| 11533 | /* Signed BCD string, least significant 4 bits are sign bits |
| 11534 | * positive sign = 0xC, negative sign = 0xD |
| 11535 | */ |
| 11536 | assign( tmp, unop( Iop_BCDtoDPB, |
| 11537 | binop( Iop_32HLto64, |
| 11538 | binop( Iop_Shr32, |
| 11539 | unop( Iop_64HIto32, |
| 11540 | mkexpr( frBI64 ) ), |
| 11541 | mkU8( 4 ) ), |
| 11542 | binop( Iop_Or32, |
| 11543 | binop( Iop_Shr32, |
| 11544 | unop( Iop_64to32, |
| 11545 | mkexpr( frBI64 ) ), |
| 11546 | mkU8( 4 ) ), |
| 11547 | binop( Iop_Shl32, |
| 11548 | unop( Iop_64HIto32, |
| 11549 | mkexpr( frBI64 ) ), |
| 11550 | mkU8( 28 ) ) ) ) ) ); |
| 11551 | |
| 11552 | assign( dbcd_u, unop( Iop_64HIto32, mkexpr( tmp ) ) ); |
| 11553 | assign( dbcd_l, unop( Iop_64to32, mkexpr( tmp ) ) ); |
| 11554 | |
| 11555 | /* Get the sign of the BCD string. */ |
| 11556 | assign( sign, |
| 11557 | binop( Iop_And32, |
| 11558 | unop( Iop_64to32, mkexpr( frBI64 ) ), |
| 11559 | mkU32( 0xF ) ) ); |
| 11560 | |
| 11561 | assign( neg_sign_mask, Generate_neg_sign_mask( mkexpr( sign ) ) ); |
| 11562 | assign( pos_sign_mask, Generate_pos_sign_mask( mkexpr( sign ) ) ); |
| 11563 | assign( sign_bit, |
| 11564 | Generate_sign_bit( mkexpr( pos_sign_mask ), |
| 11565 | mkexpr( neg_sign_mask ) ) ); |
| 11566 | |
| 11567 | /* Check for invalid sign and BCD digit. Don't check the bottom |
| 11568 | * four bits of bcd_l as that is the sign value. |
| 11569 | */ |
| 11570 | assign( invalid_mask, |
| 11571 | Generate_inv_mask( |
| 11572 | bcd_digit_inval( unop( Iop_64HIto32, |
| 11573 | mkexpr( frBI64 ) ), |
| 11574 | binop( Iop_Shr32, |
| 11575 | unop( Iop_64to32, |
| 11576 | mkexpr( frBI64 ) ), |
| 11577 | mkU8( 4 ) ) ), |
| 11578 | mkexpr( pos_sign_mask ), |
| 11579 | mkexpr( neg_sign_mask ) ) ); |
| 11580 | |
| 11581 | assign( valid_mask, unop( Iop_Not32, mkexpr( invalid_mask ) ) ); |
| 11582 | |
| 11583 | /* Generate the result assuming the sign value was valid. */ |
| 11584 | assign( tmp64, |
| 11585 | unop( Iop_ReinterpD64asI64, |
| 11586 | binop( Iop_InsertExpD64, |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 11587 | mkU64( DFP_LONG_BIAS ), |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 11588 | unop( Iop_ReinterpI64asD64, |
| 11589 | binop( Iop_32HLto64, |
| 11590 | binop( Iop_Or32, |
| 11591 | mkexpr( dbcd_u ), |
| 11592 | mkexpr( sign_bit ) ), |
| 11593 | mkexpr( dbcd_l ) ) ) ) ) ); |
| 11594 | } |
| 11595 | |
| 11596 | /* Generate the value to store depending on the validity of the |
| 11597 | * sign value and the validity of the BCD digits. |
| 11598 | */ |
| 11599 | assign( resultD64, |
| 11600 | unop( Iop_ReinterpI64asD64, |
| 11601 | binop( Iop_32HLto64, |
| 11602 | binop( Iop_Or32, |
| 11603 | binop( Iop_And32, |
| 11604 | mkexpr( valid_mask ), |
| 11605 | unop( Iop_64HIto32, |
| 11606 | mkexpr( tmp64 ) ) ), |
| 11607 | binop( Iop_And32, |
| 11608 | mkU32( 0x7C000000 ), |
| 11609 | mkexpr( invalid_mask ) ) ), |
| 11610 | binop( Iop_Or32, |
| 11611 | binop( Iop_And32, |
| 11612 | mkexpr( valid_mask ), |
| 11613 | unop( Iop_64to32, mkexpr( tmp64 ) ) ), |
| 11614 | binop( Iop_And32, |
| 11615 | mkU32( 0x0 ), |
| 11616 | mkexpr( invalid_mask ) ) ) ) ) ); |
| 11617 | putDReg( frT_addr, mkexpr( resultD64 ) ); |
| 11618 | } |
| 11619 | break; |
| 11620 | default: |
| 11621 | vpanic( "ERROR: dis_dfp_bcd(ppc), undefined opc2 case " ); |
| 11622 | return False; |
| 11623 | } |
| 11624 | return True; |
| 11625 | } |
| 11626 | |
| 11627 | static Bool dis_dfp_bcdq( UInt theInstr ) |
| 11628 | { |
| 11629 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 11630 | ULong sp = IFIELD(theInstr, 19, 2); |
| 11631 | ULong s = IFIELD(theInstr, 20, 1); |
| 11632 | IRTemp frB_hi = newTemp( Ity_D64 ); |
| 11633 | IRTemp frB_lo = newTemp( Ity_D64 ); |
| 11634 | IRTemp frBI64_hi = newTemp( Ity_I64 ); |
| 11635 | IRTemp frBI64_lo = newTemp( Ity_I64 ); |
| 11636 | UChar frT_addr = ifieldRegDS( theInstr ); |
| 11637 | UChar frB_addr = ifieldRegB( theInstr ); |
| 11638 | |
| 11639 | IRTemp lmd = newTemp( Ity_I32 ); |
| 11640 | IRTemp result_hi = newTemp( Ity_I64 ); |
| 11641 | IRTemp result_lo = newTemp( Ity_I64 ); |
| 11642 | |
| 11643 | assign( frB_hi, getDReg( frB_addr ) ); |
| 11644 | assign( frB_lo, getDReg( frB_addr + 1 ) ); |
| 11645 | assign( frBI64_hi, unop( Iop_ReinterpD64asI64, mkexpr( frB_hi ) ) ); |
| 11646 | assign( frBI64_lo, unop( Iop_ReinterpD64asI64, mkexpr( frB_lo ) ) ); |
| 11647 | |
| 11648 | switch ( opc2 ) { |
| 11649 | case 0x142: // ddedpdq DFP Decode DPD to BCD |
| 11650 | { |
| 11651 | IRTemp low_60_u = newTemp( Ity_I32 ); |
| 11652 | IRTemp low_60_l = newTemp( Ity_I32 ); |
| 11653 | IRTemp mid_60_u = newTemp( Ity_I32 ); |
| 11654 | IRTemp mid_60_l = newTemp( Ity_I32 ); |
| 11655 | IRTemp top_12_l = newTemp( Ity_I32 ); |
| 11656 | |
| 11657 | DIP( "ddedpdq %llu,r%u,r%u\n", sp, frT_addr, frB_addr ); |
| 11658 | |
| 11659 | /* Note, instruction only stores the lower 32 BCD digits in |
| 11660 | * the result |
| 11661 | */ |
| 11662 | Generate_132_bit_bcd_string( mkexpr( frBI64_hi ), |
| 11663 | mkexpr( frBI64_lo ), |
| 11664 | &top_12_l, |
| 11665 | &mid_60_u, |
| 11666 | &mid_60_l, |
| 11667 | &low_60_u, |
| 11668 | &low_60_l ); |
| 11669 | |
| 11670 | if ( ( sp == 0 ) || ( sp == 1 ) ) { |
| 11671 | /* Unsigned BCD string */ |
| 11672 | assign( result_hi, |
| 11673 | binop( Iop_32HLto64, |
| 11674 | binop( Iop_Or32, |
| 11675 | binop( Iop_Shl32, |
| 11676 | mkexpr( top_12_l ), |
| 11677 | mkU8( 24 ) ), |
| 11678 | binop( Iop_Shr32, |
| 11679 | mkexpr( mid_60_u ), |
| 11680 | mkU8( 4 ) ) ), |
| 11681 | binop( Iop_Or32, |
| 11682 | binop( Iop_Shl32, |
| 11683 | mkexpr( mid_60_u ), |
| 11684 | mkU8( 28 ) ), |
| 11685 | binop( Iop_Shr32, |
| 11686 | mkexpr( mid_60_l ), |
| 11687 | mkU8( 4 ) ) ) ) ); |
| 11688 | |
| 11689 | assign( result_lo, |
| 11690 | binop( Iop_32HLto64, |
| 11691 | binop( Iop_Or32, |
| 11692 | binop( Iop_Shl32, |
| 11693 | mkexpr( mid_60_l ), |
| 11694 | mkU8( 28 ) ), |
| 11695 | mkexpr( low_60_u ) ), |
| 11696 | mkexpr( low_60_l ) ) ); |
| 11697 | |
| 11698 | } else { |
| 11699 | /* Signed BCD string, the cases for sp 2 and 3 only differ in how |
| 11700 | * the positive and negative values are encoded in the least |
| 11701 | * significant bits. |
| 11702 | */ |
| 11703 | IRTemp sign = newTemp( Ity_I32 ); |
| 11704 | |
| 11705 | if ( sp == 2 ) { |
| 11706 | /* Positive sign = 0xC, negative sign = 0xD */ |
| 11707 | assign( sign, |
| 11708 | binop( Iop_Or32, |
| 11709 | binop( Iop_Shr32, |
| 11710 | unop( Iop_64HIto32, mkexpr( frBI64_hi ) ), |
| 11711 | mkU8( 31 ) ), |
| 11712 | mkU32( 0xC ) ) ); |
| 11713 | |
| 11714 | } else if ( sp == 3 ) { |
| 11715 | IRTemp tmp32 = newTemp( Ity_I32 ); |
| 11716 | |
| 11717 | /* Positive sign = 0xF, negative sign = 0xD. |
| 11718 | * Need to complement sign bit then OR into bit position 1. |
| 11719 | */ |
| 11720 | assign( tmp32, |
| 11721 | binop( Iop_Xor32, |
| 11722 | binop( Iop_Shr32, |
| 11723 | unop( Iop_64HIto32, mkexpr( frBI64_hi ) ), |
| 11724 | mkU8( 30 ) ), |
| 11725 | mkU32( 0x2 ) ) ); |
| 11726 | |
| 11727 | assign( sign, binop( Iop_Or32, mkexpr( tmp32 ), mkU32( 0xD ) ) ); |
| 11728 | |
| 11729 | } else { |
| 11730 | vpanic( "The impossible happened: dis_dfp_bcd(ppc), undefined SP field" ); |
| 11731 | } |
| 11732 | |
| 11733 | assign( result_hi, |
| 11734 | binop( Iop_32HLto64, |
| 11735 | binop( Iop_Or32, |
| 11736 | binop( Iop_Shl32, |
| 11737 | mkexpr( top_12_l ), |
| 11738 | mkU8( 28 ) ), |
| 11739 | mkexpr( mid_60_u ) ), |
| 11740 | mkexpr( mid_60_l ) ) ); |
| 11741 | |
| 11742 | assign( result_lo, |
| 11743 | binop( Iop_32HLto64, |
| 11744 | binop( Iop_Or32, |
| 11745 | binop( Iop_Shl32, |
| 11746 | mkexpr( low_60_u ), |
| 11747 | mkU8( 4 ) ), |
| 11748 | binop( Iop_Shr32, |
| 11749 | mkexpr( low_60_l ), |
| 11750 | mkU8( 28 ) ) ), |
| 11751 | binop( Iop_Or32, |
| 11752 | binop( Iop_Shl32, |
| 11753 | mkexpr( low_60_l ), |
| 11754 | mkU8( 4 ) ), |
| 11755 | mkexpr( sign ) ) ) ); |
| 11756 | } |
| 11757 | |
| 11758 | putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result_hi ) ) ); |
| 11759 | putDReg( frT_addr + 1, |
| 11760 | unop( Iop_ReinterpI64asD64, mkexpr( result_lo ) ) ); |
| 11761 | } |
| 11762 | break; |
| 11763 | case 0x342: // denbcdq DFP Encode BCD to DPD |
| 11764 | { |
| 11765 | IRTemp valid_mask = newTemp( Ity_I32 ); |
| 11766 | IRTemp invalid_mask = newTemp( Ity_I32 ); |
| 11767 | IRTemp result128 = newTemp( Ity_D128 ); |
| 11768 | IRTemp dfp_significand = newTemp( Ity_D128 ); |
| 11769 | IRTemp tmp_hi = newTemp( Ity_I64 ); |
| 11770 | IRTemp tmp_lo = newTemp( Ity_I64 ); |
| 11771 | IRTemp dbcd_top_l = newTemp( Ity_I32 ); |
| 11772 | IRTemp dbcd_mid_u = newTemp( Ity_I32 ); |
| 11773 | IRTemp dbcd_mid_l = newTemp( Ity_I32 ); |
| 11774 | IRTemp dbcd_low_u = newTemp( Ity_I32 ); |
| 11775 | IRTemp dbcd_low_l = newTemp( Ity_I32 ); |
| 11776 | IRTemp bcd_top_8 = newTemp( Ity_I64 ); |
| 11777 | IRTemp bcd_mid_60 = newTemp( Ity_I64 ); |
| 11778 | IRTemp bcd_low_60 = newTemp( Ity_I64 ); |
| 11779 | IRTemp sign_bit = newTemp( Ity_I32 ); |
| 11780 | IRTemp tmptop10 = newTemp( Ity_I64 ); |
| 11781 | IRTemp tmpmid50 = newTemp( Ity_I64 ); |
| 11782 | IRTemp tmplow50 = newTemp( Ity_I64 ); |
| 11783 | IRTemp inval_bcd_digit_mask = newTemp( Ity_I32 ); |
| 11784 | |
| 11785 | DIP( "denbcd %llu,r%u,r%u\n", s, frT_addr, frB_addr ); |
| 11786 | |
| 11787 | if ( s == 0 ) { |
| 11788 | /* Unsigned BCD string */ |
| 11789 | assign( sign_bit, mkU32( 0 ) ); // set to zero for unsigned string |
| 11790 | |
| 11791 | assign( bcd_top_8, |
| 11792 | binop( Iop_32HLto64, |
| 11793 | mkU32( 0 ), |
| 11794 | binop( Iop_And32, |
| 11795 | binop( Iop_Shr32, |
| 11796 | unop( Iop_64HIto32, |
| 11797 | mkexpr( frBI64_hi ) ), |
| 11798 | mkU8( 24 ) ), |
| 11799 | mkU32( 0xFF ) ) ) ); |
| 11800 | assign( bcd_mid_60, |
| 11801 | binop( Iop_32HLto64, |
| 11802 | binop( Iop_Or32, |
| 11803 | binop( Iop_Shr32, |
| 11804 | unop( Iop_64to32, |
| 11805 | mkexpr( frBI64_hi ) ), |
| 11806 | mkU8( 28 ) ), |
| 11807 | binop( Iop_Shl32, |
| 11808 | unop( Iop_64HIto32, |
| 11809 | mkexpr( frBI64_hi ) ), |
| 11810 | mkU8( 4 ) ) ), |
| 11811 | binop( Iop_Or32, |
| 11812 | binop( Iop_Shl32, |
| 11813 | unop( Iop_64to32, |
| 11814 | mkexpr( frBI64_hi ) ), |
| 11815 | mkU8( 4 ) ), |
| 11816 | binop( Iop_Shr32, |
| 11817 | unop( Iop_64HIto32, |
| 11818 | mkexpr( frBI64_lo ) ), |
| 11819 | mkU8( 28 ) ) ) ) ); |
| 11820 | |
| 11821 | /* Note, the various helper functions ignores top 4-bits */ |
| 11822 | assign( bcd_low_60, mkexpr( frBI64_lo ) ); |
| 11823 | |
| 11824 | assign( tmptop10, unop( Iop_BCDtoDPB, mkexpr( bcd_top_8 ) ) ); |
| 11825 | assign( dbcd_top_l, unop( Iop_64to32, mkexpr( tmptop10 ) ) ); |
| 11826 | |
| 11827 | assign( tmpmid50, unop( Iop_BCDtoDPB, mkexpr( bcd_mid_60 ) ) ); |
| 11828 | assign( dbcd_mid_u, unop( Iop_64HIto32, mkexpr( tmpmid50 ) ) ); |
| 11829 | assign( dbcd_mid_l, unop( Iop_64to32, mkexpr( tmpmid50 ) ) ); |
| 11830 | |
| 11831 | assign( tmplow50, unop( Iop_BCDtoDPB, mkexpr( bcd_low_60 ) ) ); |
| 11832 | assign( dbcd_low_u, unop( Iop_64HIto32, mkexpr( tmplow50 ) ) ); |
| 11833 | assign( dbcd_low_l, unop( Iop_64to32, mkexpr( tmplow50 ) ) ); |
| 11834 | |
| 11835 | /* The entire BCD string fits in lower 110-bits. The LMD = 0, |
| 11836 | * value is not part of the final result. Only the right most |
| 11837 | * BCD digits are stored. |
| 11838 | */ |
| 11839 | assign( lmd, mkU32( 0 ) ); |
| 11840 | |
| 11841 | assign( invalid_mask, |
| 11842 | binop( Iop_Or32, |
| 11843 | bcd_digit_inval( mkU32( 0 ), |
| 11844 | unop( Iop_64to32, |
| 11845 | mkexpr( bcd_top_8 ) ) ), |
| 11846 | binop( Iop_Or32, |
| 11847 | bcd_digit_inval( unop( Iop_64HIto32, |
| 11848 | mkexpr( bcd_mid_60 ) ), |
| 11849 | unop( Iop_64to32, |
| 11850 | mkexpr( bcd_mid_60 ) ) ), |
| 11851 | bcd_digit_inval( unop( Iop_64HIto32, |
| 11852 | mkexpr( bcd_low_60 ) ), |
| 11853 | unop( Iop_64to32, |
| 11854 | mkexpr( bcd_low_60 ) ) |
| 11855 | ) ) ) ); |
| 11856 | |
| 11857 | } else if ( s == 1 ) { |
| 11858 | IRTemp sign = newTemp( Ity_I32 ); |
| 11859 | IRTemp zero = newTemp( Ity_I32 ); |
| 11860 | IRTemp pos_sign_mask = newTemp( Ity_I32 ); |
| 11861 | IRTemp neg_sign_mask = newTemp( Ity_I32 ); |
| 11862 | |
| 11863 | /* The sign of the BCD string is stored in lower 4 bits */ |
| 11864 | assign( sign, |
| 11865 | binop( Iop_And32, |
| 11866 | unop( Iop_64to32, mkexpr( frBI64_lo ) ), |
| 11867 | mkU32( 0xF ) ) ); |
| 11868 | assign( neg_sign_mask, Generate_neg_sign_mask( mkexpr( sign ) ) ); |
| 11869 | assign( pos_sign_mask, Generate_pos_sign_mask( mkexpr( sign ) ) ); |
| 11870 | assign( sign_bit, |
| 11871 | Generate_sign_bit( mkexpr( pos_sign_mask ), |
| 11872 | mkexpr( neg_sign_mask ) ) ); |
| 11873 | |
| 11874 | /* Generate the value assuminig the sign and BCD digits are vaild */ |
| 11875 | assign( bcd_top_8, |
| 11876 | binop( Iop_32HLto64, |
| 11877 | mkU32( 0x0 ), |
| 11878 | binop( Iop_Shr32, |
| 11879 | unop( Iop_64HIto32, mkexpr( frBI64_hi ) ), |
| 11880 | mkU8( 28 ) ) ) ); |
| 11881 | |
| 11882 | /* The various helper routines ignore the upper 4-bits */ |
| 11883 | assign( bcd_mid_60, mkexpr( frBI64_hi ) ); |
| 11884 | |
| 11885 | /* Remove bottom four sign bits */ |
| 11886 | assign( bcd_low_60, |
| 11887 | binop( Iop_32HLto64, |
| 11888 | binop( Iop_Shr32, |
| 11889 | unop( Iop_64HIto32, |
| 11890 | mkexpr( frBI64_lo ) ), |
| 11891 | mkU8( 4 ) ), |
| 11892 | binop( Iop_Or32, |
| 11893 | binop( Iop_Shl32, |
| 11894 | unop( Iop_64HIto32, |
| 11895 | mkexpr( frBI64_lo ) ), |
| 11896 | mkU8( 28 ) ), |
| 11897 | binop( Iop_Shr32, |
| 11898 | unop( Iop_64to32, |
| 11899 | mkexpr( frBI64_lo ) ), |
| 11900 | mkU8( 4 ) ) ) ) ); |
| 11901 | assign( tmptop10, unop( Iop_BCDtoDPB, mkexpr(bcd_top_8 ) ) ); |
| 11902 | assign( dbcd_top_l, unop( Iop_64to32, mkexpr( tmptop10 ) ) ); |
| 11903 | |
| 11904 | assign( tmpmid50, unop( Iop_BCDtoDPB, mkexpr(bcd_mid_60 ) ) ); |
| 11905 | assign( dbcd_mid_u, unop( Iop_64HIto32, mkexpr( tmpmid50 ) ) ); |
| 11906 | assign( dbcd_mid_l, unop( Iop_64to32, mkexpr( tmpmid50 ) ) ); |
| 11907 | |
| 11908 | assign( tmplow50, unop( Iop_BCDtoDPB, mkexpr( bcd_low_60 ) ) ); |
| 11909 | assign( dbcd_low_u, unop( Iop_64HIto32, mkexpr( tmplow50 ) ) ); |
| 11910 | assign( dbcd_low_l, unop( Iop_64to32, mkexpr( tmplow50 ) ) ); |
| 11911 | |
| 11912 | /* The entire BCD string fits in lower 110-bits. The LMD value |
| 11913 | * is not stored in the final result for the DFP Long instruction. |
| 11914 | */ |
| 11915 | assign( lmd, mkU32( 0 ) ); |
| 11916 | |
| 11917 | /* Check for invalid sign and invalid BCD digit. Don't check the |
| 11918 | * bottom four bits of frBI64_lo as that is the sign value. |
| 11919 | */ |
| 11920 | assign( zero, mkU32( 0 ) ); |
| 11921 | assign( inval_bcd_digit_mask, |
| 11922 | binop( Iop_Or32, |
| 11923 | bcd_digit_inval( mkexpr( zero ), |
| 11924 | unop( Iop_64to32, |
| 11925 | mkexpr( bcd_top_8 ) ) ), |
| 11926 | binop( Iop_Or32, |
| 11927 | bcd_digit_inval( unop( Iop_64HIto32, |
| 11928 | mkexpr( bcd_mid_60 ) ), |
| 11929 | unop( Iop_64to32, |
| 11930 | mkexpr( bcd_mid_60 ) ) ), |
| 11931 | bcd_digit_inval( unop( Iop_64HIto32, |
| 11932 | mkexpr( frBI64_lo ) ), |
| 11933 | binop( Iop_Shr32, |
| 11934 | unop( Iop_64to32, |
| 11935 | mkexpr( frBI64_lo ) ), |
| 11936 | mkU8( 4 ) ) ) ) ) ); |
| 11937 | assign( invalid_mask, |
| 11938 | Generate_inv_mask( mkexpr( inval_bcd_digit_mask ), |
| 11939 | mkexpr( pos_sign_mask ), |
| 11940 | mkexpr( neg_sign_mask ) ) ); |
| 11941 | |
| 11942 | } |
| 11943 | |
| 11944 | assign( valid_mask, unop( Iop_Not32, mkexpr( invalid_mask ) ) ); |
| 11945 | |
| 11946 | /* Calculate the value of the result assuming sign and BCD digits |
| 11947 | * are all valid. |
| 11948 | */ |
| 11949 | assign( dfp_significand, |
| 11950 | binop( Iop_D64HLtoD128, |
| 11951 | unop( Iop_ReinterpI64asD64, |
| 11952 | binop( Iop_32HLto64, |
| 11953 | binop( Iop_Or32, |
| 11954 | mkexpr( sign_bit ), |
| 11955 | mkexpr( dbcd_top_l ) ), |
| 11956 | binop( Iop_Or32, |
| 11957 | binop( Iop_Shl32, |
| 11958 | mkexpr( dbcd_mid_u ), |
| 11959 | mkU8( 18 ) ), |
| 11960 | binop( Iop_Shr32, |
| 11961 | mkexpr( dbcd_mid_l ), |
| 11962 | mkU8( 14 ) ) ) ) ), |
| 11963 | unop( Iop_ReinterpI64asD64, |
| 11964 | binop( Iop_32HLto64, |
| 11965 | binop( Iop_Or32, |
| 11966 | mkexpr( dbcd_low_u ), |
| 11967 | binop( Iop_Shl32, |
| 11968 | mkexpr( dbcd_mid_l ), |
| 11969 | mkU8( 18 ) ) ), |
| 11970 | mkexpr( dbcd_low_l ) ) ) ) ); |
| 11971 | |
| 11972 | /* Break the result back down to 32-bit chunks and replace chunks. |
| 11973 | * If there was an invalid BCD digit or invalid sign value, replace |
| 11974 | * the calculated result with the invalid bit string. |
| 11975 | */ |
| 11976 | assign( result128, |
| 11977 | binop( Iop_InsertExpD128, |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 11978 | mkU64( DFP_EXTND_BIAS ), |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 11979 | mkexpr( dfp_significand ) ) ); |
| 11980 | |
| 11981 | assign( tmp_hi, |
| 11982 | unop( Iop_ReinterpD64asI64, |
| 11983 | unop( Iop_D128HItoD64, mkexpr( result128 ) ) ) ); |
| 11984 | |
| 11985 | assign( tmp_lo, |
| 11986 | unop( Iop_ReinterpD64asI64, |
| 11987 | unop( Iop_D128LOtoD64, mkexpr( result128 ) ) ) ); |
| 11988 | |
| 11989 | assign( result_hi, |
| 11990 | binop( Iop_32HLto64, |
| 11991 | binop( Iop_Or32, |
| 11992 | binop( Iop_And32, |
| 11993 | mkexpr( valid_mask ), |
| 11994 | unop( Iop_64HIto32, mkexpr( tmp_hi ) ) ), |
| 11995 | binop( Iop_And32, |
| 11996 | mkU32( 0x7C000000 ), |
| 11997 | mkexpr( invalid_mask ) ) ), |
| 11998 | binop( Iop_Or32, |
| 11999 | binop( Iop_And32, |
| 12000 | mkexpr( valid_mask ), |
| 12001 | unop( Iop_64to32, mkexpr( tmp_hi ) ) ), |
| 12002 | binop( Iop_And32, |
| 12003 | mkU32( 0x0 ), |
| 12004 | mkexpr( invalid_mask ) ) ) ) ); |
| 12005 | |
| 12006 | assign( result_lo, |
| 12007 | binop( Iop_32HLto64, |
| 12008 | binop( Iop_Or32, |
| 12009 | binop( Iop_And32, |
| 12010 | mkexpr( valid_mask ), |
| 12011 | unop( Iop_64HIto32, mkexpr( tmp_lo ) ) ), |
| 12012 | binop( Iop_And32, |
| 12013 | mkU32( 0x0 ), |
| 12014 | mkexpr( invalid_mask ) ) ), |
| 12015 | binop( Iop_Or32, |
| 12016 | binop( Iop_And32, |
| 12017 | mkexpr( valid_mask ), |
| 12018 | unop( Iop_64to32, mkexpr( tmp_lo ) ) ), |
| 12019 | binop( Iop_And32, |
| 12020 | mkU32( 0x0 ), |
| 12021 | mkexpr( invalid_mask ) ) ) ) ); |
| 12022 | |
| 12023 | putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result_hi ) ) ); |
| 12024 | putDReg( frT_addr + 1, |
| 12025 | unop( Iop_ReinterpI64asD64, mkexpr( result_lo ) ) ); |
| 12026 | |
| 12027 | } |
| 12028 | break; |
| 12029 | default: |
| 12030 | vpanic( "ERROR: dis_dfp_bcdq(ppc), undefined opc2 case " ); |
| 12031 | break; |
| 12032 | } |
| 12033 | return True; |
| 12034 | } |
| 12035 | |
| 12036 | static Bool dis_dfp_significant_digits( UInt theInstr ) |
| 12037 | { |
| 12038 | UChar frA_addr = ifieldRegA( theInstr ); |
| 12039 | UChar frB_addr = ifieldRegB( theInstr ); |
| 12040 | IRTemp frA = newTemp( Ity_D64 ); |
| 12041 | UInt opc1 = ifieldOPC( theInstr ); |
| 12042 | IRTemp B_sig = newTemp( Ity_I8 ); |
| 12043 | IRTemp K = newTemp( Ity_I8 ); |
| 12044 | IRTemp lmd_B = newTemp( Ity_I32 ); |
| 12045 | IRTemp field = newTemp( Ity_I32 ); |
| 12046 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); // AKA BF |
| 12047 | IRTemp Unordered_true = newTemp( Ity_I32 ); |
| 12048 | IRTemp Eq_true_mask = newTemp( Ity_I32 ); |
| 12049 | IRTemp Lt_true_mask = newTemp( Ity_I32 ); |
| 12050 | IRTemp Gt_true_mask = newTemp( Ity_I32 ); |
| 12051 | IRTemp KisZero_true_mask = newTemp( Ity_I32 ); |
| 12052 | IRTemp KisZero_false_mask = newTemp( Ity_I32 ); |
| 12053 | |
| 12054 | /* Get the reference singificance stored in frA */ |
| 12055 | assign( frA, getDReg( frA_addr ) ); |
| 12056 | |
| 12057 | /* Convert from 64 bit to 8 bits in two steps. The Iop_64to8 is not |
| 12058 | * supported in 32-bit mode. |
| 12059 | */ |
| 12060 | assign( K, unop( Iop_32to8, |
| 12061 | binop( Iop_And32, |
| 12062 | unop( Iop_64to32, |
| 12063 | unop( Iop_ReinterpD64asI64, |
| 12064 | mkexpr( frA ) ) ), |
| 12065 | mkU32( 0x3F ) ) ) ); |
| 12066 | |
| 12067 | switch ( opc1 ) { |
| 12068 | case 0x3b: // dtstsf DFP Test Significance |
| 12069 | { |
| 12070 | IRTemp frB = newTemp( Ity_D64 ); |
| 12071 | IRTemp frBI64 = newTemp( Ity_I64 ); |
| 12072 | IRTemp B_bcd_u = newTemp( Ity_I32 ); |
| 12073 | IRTemp B_bcd_l = newTemp( Ity_I32 ); |
| 12074 | IRTemp tmp64 = newTemp( Ity_I64 ); |
| 12075 | |
| 12076 | DIP( "dtstsf %u,r%u,r%u\n", crfD, frA_addr, frB_addr ); |
| 12077 | |
| 12078 | assign( frB, getDReg( frB_addr ) ); |
| 12079 | assign( frBI64, unop( Iop_ReinterpD64asI64, mkexpr( frB ) ) ); |
| 12080 | |
| 12081 | /* Get the BCD string for the value stored in a series of I32 values. |
| 12082 | * Count the number of leading zeros. Subtract the number of leading |
| 12083 | * zeros from 16 (maximum number of significant digits in DFP |
| 12084 | * Long). |
| 12085 | */ |
| 12086 | Get_lmd( &lmd_B, |
| 12087 | binop( Iop_Shr32, |
| 12088 | unop( Iop_64HIto32, mkexpr( frBI64 ) ), |
| 12089 | mkU8( 31 - 5 ) ) ); // G-field[0:4] |
| 12090 | |
| 12091 | assign( tmp64, unop( Iop_DPBtoBCD, mkexpr( frBI64 ) ) ); |
| 12092 | assign( B_bcd_u, unop( Iop_64HIto32, mkexpr( tmp64 ) ) ); |
| 12093 | assign( B_bcd_l, unop( Iop_64to32, mkexpr( tmp64 ) ) ); |
| 12094 | |
| 12095 | assign( B_sig, |
| 12096 | binop( Iop_Sub8, |
| 12097 | mkU8( DFP_LONG_MAX_SIG_DIGITS ), |
| 12098 | Count_leading_zeros_60( mkexpr( lmd_B ), |
| 12099 | mkexpr( B_bcd_u ), |
| 12100 | mkexpr( B_bcd_l ) ) ) ); |
| 12101 | assign( Unordered_true, Check_unordered( mkexpr( frBI64 ) ) ); |
| 12102 | } |
| 12103 | break; |
| 12104 | case 0x3F: // dtstsfq DFP Test Significance |
| 12105 | { |
| 12106 | IRTemp frB_hi = newTemp( Ity_D64 ); |
| 12107 | IRTemp frB_lo = newTemp( Ity_D64 ); |
| 12108 | IRTemp frBI64_hi = newTemp( Ity_I64 ); |
| 12109 | IRTemp frBI64_lo = newTemp( Ity_I64 ); |
| 12110 | IRTemp B_low_60_u = newTemp( Ity_I32 ); |
| 12111 | IRTemp B_low_60_l = newTemp( Ity_I32 ); |
| 12112 | IRTemp B_mid_60_u = newTemp( Ity_I32 ); |
| 12113 | IRTemp B_mid_60_l = newTemp( Ity_I32 ); |
| 12114 | IRTemp B_top_12_l = newTemp( Ity_I32 ); |
| 12115 | |
| 12116 | DIP( "dtstsfq %u,r%u,r%u\n", crfD, frA_addr, frB_addr ); |
| 12117 | |
| 12118 | assign( frB_hi, getDReg( frB_addr ) ); |
| 12119 | assign( frB_lo, getDReg( frB_addr + 1 ) ); |
| 12120 | |
| 12121 | assign( frBI64_hi, unop( Iop_ReinterpD64asI64, mkexpr( frB_hi ) ) ); |
| 12122 | assign( frBI64_lo, unop( Iop_ReinterpD64asI64, mkexpr( frB_lo ) ) ); |
| 12123 | |
| 12124 | /* Get the BCD string for the value stored in a series of I32 values. |
| 12125 | * Count the number of leading zeros. Subtract the number of leading |
| 12126 | * zeros from 32 (maximum number of significant digits in DFP |
| 12127 | * extended). |
| 12128 | */ |
| 12129 | Get_lmd( &lmd_B, |
| 12130 | binop( Iop_Shr32, |
| 12131 | unop( Iop_64HIto32, mkexpr( frBI64_hi ) ), |
| 12132 | mkU8( 31 - 5 ) ) ); // G-field[0:4] |
| 12133 | |
| 12134 | Generate_132_bit_bcd_string( mkexpr( frBI64_hi ), |
| 12135 | mkexpr( frBI64_lo ), |
| 12136 | &B_top_12_l, |
| 12137 | &B_mid_60_u, |
| 12138 | &B_mid_60_l, |
| 12139 | &B_low_60_u, |
| 12140 | &B_low_60_l ); |
| 12141 | |
| 12142 | assign( B_sig, |
| 12143 | binop( Iop_Sub8, |
| 12144 | mkU8( DFP_EXTND_MAX_SIG_DIGITS ), |
| 12145 | Count_leading_zeros_128( mkexpr( lmd_B ), |
| 12146 | mkexpr( B_top_12_l ), |
| 12147 | mkexpr( B_mid_60_u ), |
| 12148 | mkexpr( B_mid_60_l ), |
| 12149 | mkexpr( B_low_60_u ), |
| 12150 | mkexpr( B_low_60_l ) ) ) ); |
| 12151 | |
| 12152 | assign( Unordered_true, Check_unordered( mkexpr( frBI64_hi ) ) ); |
| 12153 | } |
| 12154 | break; |
| 12155 | } |
| 12156 | |
| 12157 | /* Compare (16 - cnt[0]) against K and set the condition code field |
| 12158 | * accordingly. |
| 12159 | * |
| 12160 | * The field layout is as follows: |
| 12161 | * |
| 12162 | * bit[3:0] Description |
| 12163 | * 3 K != 0 and K < Number of significant digits if FRB |
| 12164 | * 2 K != 0 and K > Number of significant digits if FRB OR K = 0 |
| 12165 | * 1 K != 0 and K = Number of significant digits if FRB |
| 12166 | * 0 K ? Number of significant digits if FRB |
| 12167 | */ |
| 12168 | assign( Eq_true_mask, |
| 12169 | unop( Iop_1Sto32, |
| 12170 | binop( Iop_CmpEQ32, |
| 12171 | unop( Iop_8Uto32, mkexpr( K ) ), |
| 12172 | unop( Iop_8Uto32, mkexpr( B_sig ) ) ) ) ); |
| 12173 | assign( Lt_true_mask, |
| 12174 | unop( Iop_1Sto32, |
| 12175 | binop( Iop_CmpLT32U, |
| 12176 | unop( Iop_8Uto32, mkexpr( K ) ), |
| 12177 | unop( Iop_8Uto32, mkexpr( B_sig ) ) ) ) ); |
| 12178 | assign( Gt_true_mask, |
| 12179 | unop( Iop_1Sto32, |
| 12180 | binop( Iop_CmpLT32U, |
| 12181 | unop( Iop_8Uto32, mkexpr( B_sig ) ), |
| 12182 | unop( Iop_8Uto32, mkexpr( K ) ) ) ) ); |
| 12183 | |
| 12184 | assign( KisZero_true_mask, |
| 12185 | unop( Iop_1Sto32, |
| 12186 | binop( Iop_CmpEQ32, |
| 12187 | unop( Iop_8Uto32, mkexpr( K ) ), |
| 12188 | mkU32( 0 ) ) ) ); |
| 12189 | assign( KisZero_false_mask, |
| 12190 | unop( Iop_1Sto32, |
| 12191 | binop( Iop_CmpNE32, |
| 12192 | unop( Iop_8Uto32, mkexpr( K ) ), |
| 12193 | mkU32( 0 ) ) ) ); |
| 12194 | |
| 12195 | assign( field, |
| 12196 | binop( Iop_Or32, |
| 12197 | binop( Iop_And32, |
| 12198 | mkexpr( KisZero_false_mask ), |
| 12199 | binop( Iop_Or32, |
| 12200 | binop( Iop_And32, |
| 12201 | mkexpr( Lt_true_mask ), |
| 12202 | mkU32( 0x8 ) ), |
| 12203 | binop( Iop_Or32, |
| 12204 | binop( Iop_And32, |
| 12205 | mkexpr( Gt_true_mask ), |
| 12206 | mkU32( 0x4 ) ), |
| 12207 | binop( Iop_And32, |
| 12208 | mkexpr( Eq_true_mask ), |
| 12209 | mkU32( 0x2 ) ) ) ) ), |
| 12210 | binop( Iop_And32, |
| 12211 | mkexpr( KisZero_true_mask ), |
| 12212 | mkU32( 0x4 ) ) ) ); |
| 12213 | |
| 12214 | putGST_field( PPC_GST_CR, |
| 12215 | binop( Iop_Or32, |
| 12216 | binop( Iop_And32, |
| 12217 | mkexpr( Unordered_true ), |
| 12218 | mkU32( 0x1 ) ), |
| 12219 | binop( Iop_And32, |
| 12220 | unop( Iop_Not32, mkexpr( Unordered_true ) ), |
| 12221 | mkexpr( field ) ) ), |
| 12222 | crfD ); |
| 12223 | |
| 12224 | return True; |
| 12225 | } |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 12226 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12227 | /*------------------------------------------------------------*/ |
| 12228 | /*--- AltiVec Instruction Translation ---*/ |
| 12229 | /*------------------------------------------------------------*/ |
| 12230 | |
| 12231 | /* |
| 12232 | Altivec Cache Control Instructions (Data Streams) |
| 12233 | */ |
| 12234 | static Bool dis_av_datastream ( UInt theInstr ) |
| 12235 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 12236 | /* X-Form */ |
| 12237 | UChar opc1 = ifieldOPC(theInstr); |
| 12238 | UChar flag_T = toUChar( IFIELD( theInstr, 25, 1 ) ); |
| 12239 | UChar flag_A = flag_T; |
| 12240 | UChar b23to24 = toUChar( IFIELD( theInstr, 23, 2 ) ); |
| 12241 | UChar STRM = toUChar( IFIELD( theInstr, 21, 2 ) ); |
| 12242 | UChar rA_addr = ifieldRegA(theInstr); |
| 12243 | UChar rB_addr = ifieldRegB(theInstr); |
| 12244 | UInt opc2 = ifieldOPClo10(theInstr); |
| 12245 | UChar b0 = ifieldBIT0(theInstr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12246 | |
| 12247 | if (opc1 != 0x1F || b23to24 != 0 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 12248 | vex_printf("dis_av_datastream(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12249 | return False; |
| 12250 | } |
| 12251 | |
| 12252 | switch (opc2) { |
| 12253 | case 0x156: // dst (Data Stream Touch, AV p115) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 12254 | DIP("dst%s r%u,r%u,%d\n", flag_T ? "t" : "", |
| 12255 | rA_addr, rB_addr, STRM); |
sewardj | 923c65b | 2006-12-27 23:59:31 +0000 | [diff] [blame] | 12256 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12257 | |
| 12258 | case 0x176: // dstst (Data Stream Touch for Store, AV p117) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 12259 | DIP("dstst%s r%u,r%u,%d\n", flag_T ? "t" : "", |
| 12260 | rA_addr, rB_addr, STRM); |
sewardj | 923c65b | 2006-12-27 23:59:31 +0000 | [diff] [blame] | 12261 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12262 | |
| 12263 | case 0x336: // dss (Data Stream Stop, AV p114) |
| 12264 | if (rA_addr != 0 || rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 12265 | vex_printf("dis_av_datastream(ppc)(opc2,dst)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12266 | return False; |
| 12267 | } |
| 12268 | if (flag_A == 0) { |
| 12269 | DIP("dss %d\n", STRM); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12270 | } else { |
| 12271 | DIP("dssall\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12272 | } |
sewardj | 923c65b | 2006-12-27 23:59:31 +0000 | [diff] [blame] | 12273 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12274 | |
| 12275 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 12276 | vex_printf("dis_av_datastream(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12277 | return False; |
| 12278 | } |
| 12279 | return True; |
| 12280 | } |
| 12281 | |
| 12282 | /* |
| 12283 | AltiVec Processor Control Instructions |
| 12284 | */ |
| 12285 | static Bool dis_av_procctl ( UInt theInstr ) |
| 12286 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 12287 | /* VX-Form */ |
| 12288 | UChar opc1 = ifieldOPC(theInstr); |
| 12289 | UChar vD_addr = ifieldRegDS(theInstr); |
| 12290 | UChar vA_addr = ifieldRegA(theInstr); |
| 12291 | UChar vB_addr = ifieldRegB(theInstr); |
| 12292 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12293 | |
| 12294 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 12295 | vex_printf("dis_av_procctl(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12296 | return False; |
| 12297 | } |
| 12298 | |
| 12299 | switch (opc2) { |
| 12300 | case 0x604: // mfvscr (Move from VSCR, AV p129) |
| 12301 | if (vA_addr != 0 || vB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 12302 | vex_printf("dis_av_procctl(ppc)(opc2,dst)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12303 | return False; |
| 12304 | } |
| 12305 | DIP("mfvscr v%d\n", vD_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 12306 | putVReg( vD_addr, unop(Iop_32UtoV128, getGST( PPC_GST_VSCR )) ); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 12307 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12308 | |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 12309 | case 0x644: { // mtvscr (Move to VSCR, AV p130) |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 12310 | IRTemp vB = newTemp(Ity_V128); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12311 | if (vD_addr != 0 || vA_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 12312 | vex_printf("dis_av_procctl(ppc)(opc2,dst)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12313 | return False; |
| 12314 | } |
| 12315 | DIP("mtvscr v%d\n", vB_addr); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 12316 | assign( vB, getVReg(vB_addr)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 12317 | putGST( PPC_GST_VSCR, unop(Iop_V128to32, mkexpr(vB)) ); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 12318 | break; |
| 12319 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12320 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 12321 | vex_printf("dis_av_procctl(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 12322 | return False; |
| 12323 | } |
| 12324 | return True; |
| 12325 | } |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 12326 | |
| 12327 | /* |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12328 | * VSX scalar and vector convert instructions |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 12329 | */ |
| 12330 | static Bool |
| 12331 | dis_vx_conv ( UInt theInstr, UInt opc2 ) |
| 12332 | { |
| 12333 | /* XX2-Form */ |
| 12334 | UChar opc1 = ifieldOPC( theInstr ); |
| 12335 | UChar XT = ifieldRegXT( theInstr ); |
| 12336 | UChar XB = ifieldRegXB( theInstr ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12337 | IRTemp xB, xB2; |
| 12338 | IRTemp b3, b2, b1, b0; |
| 12339 | xB = xB2 = IRTemp_INVALID; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 12340 | |
| 12341 | if (opc1 != 0x3C) { |
| 12342 | vex_printf( "dis_vx_conv(ppc)(instr)\n" ); |
| 12343 | return False; |
| 12344 | } |
| 12345 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12346 | /* Create and assign temps only as needed for the given instruction. */ |
| 12347 | switch (opc2) { |
| 12348 | // scalar double-precision floating point argument |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 12349 | case 0x2B0: case 0x0b0: case 0x290: case 0x212: case 0x216: case 0x090: |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12350 | xB = newTemp(Ity_F64); |
| 12351 | assign( xB, |
| 12352 | unop( Iop_ReinterpI64asF64, |
| 12353 | unop( Iop_V128HIto64, getVSReg( XB ) ) ) ); |
| 12354 | break; |
| 12355 | // vector double-precision floating point arguments |
| 12356 | case 0x1b0: case 0x312: case 0x390: case 0x190: case 0x3B0: |
| 12357 | |
| 12358 | xB = newTemp(Ity_F64); |
| 12359 | xB2 = newTemp(Ity_F64); |
| 12360 | assign( xB, |
| 12361 | unop( Iop_ReinterpI64asF64, |
| 12362 | unop( Iop_V128HIto64, getVSReg( XB ) ) ) ); |
| 12363 | assign( xB2, |
| 12364 | unop( Iop_ReinterpI64asF64, |
| 12365 | unop( Iop_V128to64, getVSReg( XB ) ) ) ); |
| 12366 | break; |
| 12367 | // vector single precision or [un]signed integer word arguments |
| 12368 | case 0x130: case 0x392: case 0x330: case 0x310: case 0x110: |
| 12369 | case 0x1f0: case 0x1d0: |
| 12370 | b3 = b2 = b1 = b0 = IRTemp_INVALID; |
| 12371 | breakV128to4x32(getVSReg(XB), &b3, &b2, &b1, &b0); |
| 12372 | break; |
| 12373 | // vector [un]signed integer doubleword argument |
| 12374 | case 0x3f0: case 0x370: case 0x3d0: case 0x350: |
| 12375 | xB = newTemp(Ity_I64); |
| 12376 | assign( xB, unop( Iop_V128HIto64, getVSReg( XB ) ) ); |
| 12377 | xB2 = newTemp(Ity_I64); |
| 12378 | assign( xB2, unop( Iop_V128to64, getVSReg( XB ) ) ); |
| 12379 | break; |
| 12380 | // scalar [un]signed integer doubleword argument |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 12381 | case 0x250: case 0x270: case 0x2D0: case 0x2F0: |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12382 | xB = newTemp(Ity_I64); |
| 12383 | assign( xB, unop( Iop_V128HIto64, getVSReg( XB ) ) ); |
| 12384 | break; |
| 12385 | // scalar single precision argument |
| 12386 | case 0x292: // xscvspdp |
carll | 6fef87a | 2013-09-12 17:26:42 +0000 | [diff] [blame] | 12387 | xB = newTemp(Ity_I32); |
| 12388 | |
| 12389 | assign( xB, handle_SNaN_to_QNaN_32(unop( Iop_64HIto32, |
| 12390 | unop( Iop_V128HIto64, |
| 12391 | getVSReg( XB ) ) ) ) ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12392 | break; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 12393 | case 0x296: // xscvspdpn (non signaling version of xscvpdp) |
| 12394 | xB = newTemp(Ity_I32); |
| 12395 | assign( xB, |
| 12396 | unop( Iop_64HIto32, unop( Iop_V128HIto64, getVSReg( XB ) ) ) ); |
| 12397 | break; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12398 | |
| 12399 | /* Certain instructions have their complete implementation in the main switch statement |
| 12400 | * that follows this one; thus we have a "do nothing" case for those instructions here. |
| 12401 | */ |
| 12402 | case 0x170: case 0x150: |
| 12403 | break; // do nothing |
| 12404 | |
| 12405 | default: |
| 12406 | vex_printf( "dis_vx_conv(ppc)(opc2)\n" ); |
| 12407 | return False; |
| 12408 | } |
| 12409 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 12410 | |
| 12411 | switch (opc2) { |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12412 | case 0x2B0: |
| 12413 | // xscvdpsxds (VSX Scalar truncate Double-Precision to integer and Convert |
| 12414 | // to Signed Integer Doubleword format with Saturate) |
| 12415 | DIP("xscvdpsxds v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12416 | putVSReg( XT, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 12417 | binop( Iop_64HLtoV128, binop( Iop_F64toI64S, |
| 12418 | mkU32( Irrm_ZERO ), |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12419 | mkexpr( xB ) ), mkU64( 0 ) ) ); |
| 12420 | break; |
| 12421 | case 0x0b0: // xscvdpsxws (VSX Scalar truncate Double-Precision to integer and |
| 12422 | // Convert to Signed Integer Word format with Saturate) |
| 12423 | DIP("xscvdpsxws v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12424 | putVSReg( XT, |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12425 | binop( Iop_64HLtoV128, |
| 12426 | unop( Iop_32Sto64, |
| 12427 | binop( Iop_F64toI32S, |
| 12428 | mkU32( Irrm_ZERO ), |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12429 | mkexpr( xB ) ) ), |
| 12430 | mkU64( 0ULL ) ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12431 | break; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12432 | case 0x290: // xscvdpuxds (VSX Scalar truncate Double-Precision integer and Convert |
| 12433 | // to Unsigned Integer Doubleword format with Saturate) |
| 12434 | DIP("xscvdpuxds v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12435 | putVSReg( XT, |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12436 | binop( Iop_64HLtoV128, |
| 12437 | binop( Iop_F64toI64U, |
| 12438 | mkU32( Irrm_ZERO ), |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12439 | mkexpr( xB ) ), |
| 12440 | mkU64( 0ULL ) ) ); |
| 12441 | break; |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 12442 | case 0x270: |
| 12443 | // xscvsxdsp (VSX Scalar Convert and round Signed Integer Doubleword |
| 12444 | // to Single-Precision format) |
| 12445 | DIP("xscvsxdsp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12446 | putVSReg( XT, |
| 12447 | binop( Iop_64HLtoV128, |
| 12448 | unop( Iop_ReinterpF64asI64, |
| 12449 | binop( Iop_RoundF64toF32, |
| 12450 | get_IR_roundingmode(), |
| 12451 | binop( Iop_I64StoF64, |
| 12452 | get_IR_roundingmode(), |
| 12453 | mkexpr( xB ) ) ) ), |
| 12454 | mkU64( 0 ) ) ); |
| 12455 | break; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12456 | case 0x2F0: |
| 12457 | // xscvsxddp (VSX Scalar Convert and round Signed Integer Doubleword to |
| 12458 | // Double-Precision format) |
| 12459 | DIP("xscvsxddp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12460 | putVSReg( XT, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 12461 | binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64, |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12462 | binop( Iop_I64StoF64, get_IR_roundingmode(), |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12463 | mkexpr( xB ) ) ), |
| 12464 | mkU64( 0 ) ) ); |
| 12465 | break; |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 12466 | case 0x250: |
| 12467 | // xscvuxdsp (VSX Scalar Convert and round Unsigned Integer |
| 12468 | // Doubleword to Singel-Precision format) |
| 12469 | DIP("xscvuxdsp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12470 | putVSReg( XT, |
| 12471 | binop( Iop_64HLtoV128, |
| 12472 | unop( Iop_ReinterpF64asI64, |
| 12473 | binop( Iop_RoundF64toF32, |
| 12474 | get_IR_roundingmode(), |
| 12475 | binop( Iop_I64UtoF64, |
| 12476 | get_IR_roundingmode(), |
| 12477 | mkexpr( xB ) ) ) ), |
| 12478 | mkU64( 0 ) ) ); |
| 12479 | break; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12480 | case 0x2D0: |
| 12481 | // xscvuxddp (VSX Scalar Convert and round Unsigned Integer Doubleword to |
| 12482 | // Double-Precision format) |
| 12483 | DIP("xscvuxddp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12484 | putVSReg( XT, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 12485 | binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64, |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12486 | binop( Iop_I64UtoF64, get_IR_roundingmode(), |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12487 | mkexpr( xB ) ) ), |
| 12488 | mkU64( 0 ) ) ); |
| 12489 | break; |
| 12490 | case 0x1b0: // xvcvdpsxws (VSX Vector truncate Double-Precision to integer and Convert |
| 12491 | // to Signed Integer Word format with Saturate) |
| 12492 | { |
| 12493 | IRTemp hiResult_32 = newTemp(Ity_I32); |
| 12494 | IRTemp loResult_32 = newTemp(Ity_I32); |
| 12495 | IRExpr* rmZero = mkU32(Irrm_ZERO); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 12496 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12497 | DIP("xvcvdpsxws v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12498 | assign(hiResult_32, binop(Iop_F64toI32S, rmZero, mkexpr(xB))); |
| 12499 | assign(loResult_32, binop(Iop_F64toI32S, rmZero, mkexpr(xB2))); |
| 12500 | putVSReg( XT, |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12501 | binop( Iop_64HLtoV128, |
| 12502 | unop( Iop_32Sto64, mkexpr( hiResult_32 ) ), |
| 12503 | unop( Iop_32Sto64, mkexpr( loResult_32 ) ) ) ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12504 | break; |
| 12505 | } |
| 12506 | case 0x130: case 0x110: // xvcvspsxws, xvcvspuxws |
| 12507 | // (VSX Vector truncate Single-Precision to integer and |
| 12508 | // Convert to [Un]signed Integer Word format with Saturate) |
| 12509 | { |
| 12510 | IRExpr * b0_result, * b1_result, * b2_result, * b3_result; |
| 12511 | IRTemp tempResult = newTemp(Ity_V128); |
| 12512 | IRTemp res0 = newTemp(Ity_I32); |
| 12513 | IRTemp res1 = newTemp(Ity_I32); |
| 12514 | IRTemp res2 = newTemp(Ity_I32); |
| 12515 | IRTemp res3 = newTemp(Ity_I32); |
| 12516 | IRTemp hi64 = newTemp(Ity_I64); |
| 12517 | IRTemp lo64 = newTemp(Ity_I64); |
| 12518 | Bool un_signed = (opc2 == 0x110); |
| 12519 | IROp op = un_signed ? Iop_QFtoI32Ux4_RZ : Iop_QFtoI32Sx4_RZ; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12520 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12521 | DIP("xvcvsp%sxws v%u,v%u\n", un_signed ? "u" : "s", (UInt)XT, (UInt)XB); |
| 12522 | /* The xvcvsp{s|u}xws instruction is similar to vct{s|u}xs, except if src is a NaN, |
| 12523 | * then result is set to 0x80000000. */ |
| 12524 | assign(tempResult, unop(op, getVSReg(XB))); |
| 12525 | assign( hi64, unop(Iop_V128HIto64, mkexpr(tempResult)) ); |
| 12526 | assign( lo64, unop(Iop_V128to64, mkexpr(tempResult)) ); |
| 12527 | assign( res3, unop(Iop_64HIto32, mkexpr(hi64)) ); |
| 12528 | assign( res2, unop(Iop_64to32, mkexpr(hi64)) ); |
| 12529 | assign( res1, unop(Iop_64HIto32, mkexpr(lo64)) ); |
| 12530 | assign( res0, unop(Iop_64to32, mkexpr(lo64)) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12531 | |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 12532 | b3_result = IRExpr_ITE(is_NaN_32(b3), |
| 12533 | // then: result is 0x{8|0}80000000 |
| 12534 | mkU32(un_signed ? 0x00000000 : 0x80000000), |
| 12535 | // else: result is from the Iop_QFtoI32{s|u}x4_RZ |
| 12536 | mkexpr(res3)); |
| 12537 | b2_result = IRExpr_ITE(is_NaN_32(b2), |
| 12538 | // then: result is 0x{8|0}80000000 |
| 12539 | mkU32(un_signed ? 0x00000000 : 0x80000000), |
| 12540 | // else: result is from the Iop_QFtoI32{s|u}x4_RZ |
| 12541 | mkexpr(res2)); |
| 12542 | b1_result = IRExpr_ITE(is_NaN_32(b1), |
| 12543 | // then: result is 0x{8|0}80000000 |
| 12544 | mkU32(un_signed ? 0x00000000 : 0x80000000), |
| 12545 | // else: result is from the Iop_QFtoI32{s|u}x4_RZ |
| 12546 | mkexpr(res1)); |
| 12547 | b0_result = IRExpr_ITE(is_NaN_32(b0), |
| 12548 | // then: result is 0x{8|0}80000000 |
| 12549 | mkU32(un_signed ? 0x00000000 : 0x80000000), |
| 12550 | // else: result is from the Iop_QFtoI32{s|u}x4_RZ |
| 12551 | mkexpr(res0)); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12552 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12553 | putVSReg( XT, |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12554 | binop( Iop_64HLtoV128, |
| 12555 | binop( Iop_32HLto64, b3_result, b2_result ), |
| 12556 | binop( Iop_32HLto64, b1_result, b0_result ) ) ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12557 | break; |
| 12558 | } |
| 12559 | case 0x212: // xscvdpsp (VSX Scalar round Double-Precision to single-precision and |
| 12560 | // Convert to Single-Precision format |
| 12561 | DIP("xscvdpsp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12562 | putVSReg( XT, |
| 12563 | binop( Iop_64HLtoV128, |
| 12564 | binop( Iop_32HLto64, |
| 12565 | unop( Iop_ReinterpF32asI32, |
| 12566 | unop( Iop_TruncF64asF32, |
| 12567 | binop( Iop_RoundF64toF32, |
| 12568 | get_IR_roundingmode(), |
| 12569 | mkexpr( xB ) ) ) ), |
| 12570 | mkU32( 0 ) ), |
| 12571 | mkU64( 0ULL ) ) ); |
| 12572 | break; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 12573 | case 0x216: /* xscvdpspn (VSX Scalar convert scalar Single-Precision to |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 12574 | vector Single-Precision non-signalling */ |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 12575 | DIP("xscvdpspn v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12576 | putVSReg( XT, |
| 12577 | binop( Iop_64HLtoV128, |
| 12578 | binop( Iop_32HLto64, |
| 12579 | unop( Iop_ReinterpF32asI32, |
| 12580 | unop( Iop_TruncF64asF32, |
| 12581 | mkexpr( xB ) ) ), |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 12582 | mkU32( 0 ) ), |
| 12583 | mkU64( 0ULL ) ) ); |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 12584 | break; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12585 | case 0x090: // xscvdpuxws (VSX Scalar truncate Double-Precision to integer |
| 12586 | // and Convert to Unsigned Integer Word format with Saturate) |
| 12587 | DIP("xscvdpuxws v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12588 | putVSReg( XT, |
| 12589 | binop( Iop_64HLtoV128, |
| 12590 | binop( Iop_32HLto64, |
| 12591 | mkU32( 0 ), |
| 12592 | binop( Iop_F64toI32U, |
| 12593 | mkU32( Irrm_ZERO ), |
| 12594 | mkexpr( xB ) ) ), |
| 12595 | mkU64( 0ULL ) ) ); |
| 12596 | break; |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 12597 | case 0x292: // xscvspdp (VSX Scalar Convert Single-Precision to Double-Precision format, signaling) |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12598 | DIP("xscvspdp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12599 | putVSReg( XT, |
| 12600 | binop( Iop_64HLtoV128, |
| 12601 | unop( Iop_ReinterpF64asI64, |
| 12602 | unop( Iop_F32toF64, |
| 12603 | unop( Iop_ReinterpI32asF32, mkexpr( xB ) ) ) ), |
| 12604 | mkU64( 0ULL ) ) ); |
| 12605 | break; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 12606 | case 0x296: // xscvspdpn (VSX Scalar Convert Single-Precision to Double-Precision format Non signaling) |
| 12607 | DIP("xscvspdpn v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12608 | putVSReg( XT, |
| 12609 | binop( Iop_64HLtoV128, |
| 12610 | unop( Iop_ReinterpF64asI64, |
| 12611 | unop( Iop_F32toF64, |
| 12612 | unop( Iop_ReinterpI32asF32, mkexpr( xB ) ) ) ), |
| 12613 | mkU64( 0ULL ) ) ); |
| 12614 | break; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12615 | case 0x312: // xvcvdpsp (VSX Vector round Double-Precision to single-precision |
| 12616 | // and Convert to Single-Precision format) |
| 12617 | DIP("xvcvdpsp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12618 | putVSReg( XT, |
| 12619 | binop( Iop_64HLtoV128, |
| 12620 | binop( Iop_32HLto64, |
| 12621 | unop( Iop_ReinterpF32asI32, |
| 12622 | unop( Iop_TruncF64asF32, |
| 12623 | binop( Iop_RoundF64toF32, |
| 12624 | get_IR_roundingmode(), |
| 12625 | mkexpr( xB ) ) ) ), |
| 12626 | mkU32( 0 ) ), |
| 12627 | binop( Iop_32HLto64, |
| 12628 | unop( Iop_ReinterpF32asI32, |
| 12629 | unop( Iop_TruncF64asF32, |
| 12630 | binop( Iop_RoundF64toF32, |
| 12631 | get_IR_roundingmode(), |
| 12632 | mkexpr( xB2 ) ) ) ), |
| 12633 | mkU32( 0 ) ) ) ); |
| 12634 | break; |
| 12635 | case 0x390: // xvcvdpuxds (VSX Vector truncate Double-Precision to integer |
| 12636 | // and Convert to Unsigned Integer Doubleword format |
| 12637 | // with Saturate) |
| 12638 | DIP("xvcvdpuxds v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12639 | putVSReg( XT, |
| 12640 | binop( Iop_64HLtoV128, |
| 12641 | binop( Iop_F64toI64U, mkU32( Irrm_ZERO ), mkexpr( xB ) ), |
| 12642 | binop( Iop_F64toI64U, mkU32( Irrm_ZERO ), mkexpr( xB2 ) ) ) ); |
| 12643 | break; |
| 12644 | case 0x190: // xvcvdpuxws (VSX Vector truncate Double-Precision to integer and |
| 12645 | // Convert to Unsigned Integer Word format with Saturate) |
| 12646 | DIP("xvcvdpuxws v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12647 | putVSReg( XT, |
| 12648 | binop( Iop_64HLtoV128, |
| 12649 | binop( Iop_32HLto64, |
| 12650 | binop( Iop_F64toI32U, |
| 12651 | mkU32( Irrm_ZERO ), |
| 12652 | mkexpr( xB ) ), |
| 12653 | mkU32( 0 ) ), |
| 12654 | binop( Iop_32HLto64, |
| 12655 | binop( Iop_F64toI32U, |
| 12656 | mkU32( Irrm_ZERO ), |
| 12657 | mkexpr( xB2 ) ), |
| 12658 | mkU32( 0 ) ) ) ); |
| 12659 | break; |
| 12660 | case 0x392: // xvcvspdp (VSX Vector Convert Single-Precision to Double-Precision format) |
| 12661 | DIP("xvcvspdp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12662 | putVSReg( XT, |
| 12663 | binop( Iop_64HLtoV128, |
| 12664 | unop( Iop_ReinterpF64asI64, |
| 12665 | unop( Iop_F32toF64, |
carll | 6fef87a | 2013-09-12 17:26:42 +0000 | [diff] [blame] | 12666 | unop( Iop_ReinterpI32asF32, |
| 12667 | handle_SNaN_to_QNaN_32( mkexpr( b3 ) ) ) ) ), |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12668 | unop( Iop_ReinterpF64asI64, |
| 12669 | unop( Iop_F32toF64, |
carll | 6fef87a | 2013-09-12 17:26:42 +0000 | [diff] [blame] | 12670 | unop( Iop_ReinterpI32asF32, |
| 12671 | handle_SNaN_to_QNaN_32( mkexpr( b1 ) ) ) ) ) ) ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12672 | break; |
| 12673 | case 0x330: // xvcvspsxds (VSX Vector truncate Single-Precision to integer and |
| 12674 | // Convert to Signed Integer Doubleword format with Saturate) |
| 12675 | DIP("xvcvspsxds v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12676 | putVSReg( XT, |
| 12677 | binop( Iop_64HLtoV128, |
| 12678 | binop( Iop_F64toI64S, |
| 12679 | mkU32( Irrm_ZERO ), |
| 12680 | unop( Iop_F32toF64, |
| 12681 | unop( Iop_ReinterpI32asF32, mkexpr( b3 ) ) ) ), |
| 12682 | binop( Iop_F64toI64S, |
| 12683 | mkU32( Irrm_ZERO ), |
| 12684 | unop( Iop_F32toF64, |
| 12685 | unop( Iop_ReinterpI32asF32, mkexpr( b1 ) ) ) ) ) ); |
| 12686 | break; |
| 12687 | case 0x310: // xvcvspuxds (VSX Vector truncate Single-Precision to integer and |
| 12688 | // Convert to Unsigned Integer Doubleword format with Saturate) |
| 12689 | DIP("xvcvspuxds v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12690 | putVSReg( XT, |
| 12691 | binop( Iop_64HLtoV128, |
| 12692 | binop( Iop_F64toI64U, |
| 12693 | mkU32( Irrm_ZERO ), |
| 12694 | unop( Iop_F32toF64, |
| 12695 | unop( Iop_ReinterpI32asF32, mkexpr( b3 ) ) ) ), |
| 12696 | binop( Iop_F64toI64U, |
| 12697 | mkU32( Irrm_ZERO ), |
| 12698 | unop( Iop_F32toF64, |
| 12699 | unop( Iop_ReinterpI32asF32, mkexpr( b1 ) ) ) ) ) ); |
| 12700 | break; |
| 12701 | case 0x3B0: // xvcvdpsxds (VSX Vector truncate Double-Precision to integer and |
| 12702 | // Convert to Signed Integer Doubleword format with Saturate) |
| 12703 | DIP("xvcvdpsxds v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12704 | putVSReg( XT, |
| 12705 | binop( Iop_64HLtoV128, |
| 12706 | binop( Iop_F64toI64S, mkU32( Irrm_ZERO ), mkexpr( xB ) ), |
| 12707 | binop( Iop_F64toI64S, mkU32( Irrm_ZERO ), mkexpr( xB2 ) ) ) ); |
| 12708 | break; |
| 12709 | case 0x3f0: // xvcvsxddp (VSX Vector Convert and round Signed Integer Doubleword |
| 12710 | // to Double-Precision format) |
| 12711 | DIP("xvcvsxddp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12712 | putVSReg( XT, |
| 12713 | binop( Iop_64HLtoV128, |
| 12714 | unop( Iop_ReinterpF64asI64, |
| 12715 | binop( Iop_I64StoF64, |
| 12716 | get_IR_roundingmode(), |
| 12717 | mkexpr( xB ) ) ), |
| 12718 | unop( Iop_ReinterpF64asI64, |
| 12719 | binop( Iop_I64StoF64, |
| 12720 | get_IR_roundingmode(), |
| 12721 | mkexpr( xB2 ) ) ) ) ); |
| 12722 | break; |
| 12723 | case 0x3d0: // xvcvuxddp (VSX Vector Convert and round Unsigned Integer Doubleword |
| 12724 | // to Double-Precision format) |
| 12725 | DIP("xvcvuxddp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12726 | putVSReg( XT, |
| 12727 | binop( Iop_64HLtoV128, |
| 12728 | unop( Iop_ReinterpF64asI64, |
| 12729 | binop( Iop_I64UtoF64, |
| 12730 | get_IR_roundingmode(), |
| 12731 | mkexpr( xB ) ) ), |
| 12732 | unop( Iop_ReinterpF64asI64, |
| 12733 | binop( Iop_I64UtoF64, |
| 12734 | get_IR_roundingmode(), |
| 12735 | mkexpr( xB2 ) ) ) ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12736 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12737 | break; |
| 12738 | case 0x370: // xvcvsxdsp (VSX Vector Convert and round Signed Integer Doubleword |
| 12739 | // to Single-Precision format) |
| 12740 | DIP("xvcvsxddp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12741 | putVSReg( XT, |
| 12742 | binop( Iop_64HLtoV128, |
| 12743 | binop( Iop_32HLto64, |
| 12744 | unop( Iop_ReinterpF32asI32, |
| 12745 | unop( Iop_TruncF64asF32, |
| 12746 | binop( Iop_RoundF64toF32, |
| 12747 | get_IR_roundingmode(), |
| 12748 | binop( Iop_I64StoF64, |
| 12749 | get_IR_roundingmode(), |
| 12750 | mkexpr( xB ) ) ) ) ), |
| 12751 | mkU32( 0 ) ), |
| 12752 | binop( Iop_32HLto64, |
| 12753 | unop( Iop_ReinterpF32asI32, |
| 12754 | unop( Iop_TruncF64asF32, |
| 12755 | binop( Iop_RoundF64toF32, |
| 12756 | get_IR_roundingmode(), |
| 12757 | binop( Iop_I64StoF64, |
| 12758 | get_IR_roundingmode(), |
| 12759 | mkexpr( xB2 ) ) ) ) ), |
| 12760 | mkU32( 0 ) ) ) ); |
| 12761 | break; |
| 12762 | case 0x350: // xvcvuxdsp (VSX Vector Convert and round Unsigned Integer Doubleword |
| 12763 | // to Single-Precision format) |
| 12764 | DIP("xvcvuxddp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12765 | putVSReg( XT, |
| 12766 | binop( Iop_64HLtoV128, |
| 12767 | binop( Iop_32HLto64, |
| 12768 | unop( Iop_ReinterpF32asI32, |
| 12769 | unop( Iop_TruncF64asF32, |
| 12770 | binop( Iop_RoundF64toF32, |
| 12771 | get_IR_roundingmode(), |
| 12772 | binop( Iop_I64UtoF64, |
| 12773 | get_IR_roundingmode(), |
| 12774 | mkexpr( xB ) ) ) ) ), |
| 12775 | mkU32( 0 ) ), |
| 12776 | binop( Iop_32HLto64, |
| 12777 | unop( Iop_ReinterpF32asI32, |
| 12778 | unop( Iop_TruncF64asF32, |
| 12779 | binop( Iop_RoundF64toF32, |
| 12780 | get_IR_roundingmode(), |
| 12781 | binop( Iop_I64UtoF64, |
| 12782 | get_IR_roundingmode(), |
| 12783 | mkexpr( xB2 ) ) ) ) ), |
| 12784 | mkU32( 0 ) ) ) ); |
| 12785 | break; |
| 12786 | |
| 12787 | case 0x1f0: // xvcvsxwdp (VSX Vector Convert Signed Integer Word to Double-Precision format) |
| 12788 | DIP("xvcvsxwdp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12789 | putVSReg( XT, |
| 12790 | binop( Iop_64HLtoV128, |
| 12791 | unop( Iop_ReinterpF64asI64, |
| 12792 | binop( Iop_I64StoF64, get_IR_roundingmode(), |
| 12793 | unop( Iop_32Sto64, mkexpr( b3 ) ) ) ), |
| 12794 | unop( Iop_ReinterpF64asI64, |
| 12795 | binop( Iop_I64StoF64, get_IR_roundingmode(), |
| 12796 | unop( Iop_32Sto64, mkexpr( b1 ) ) ) ) ) ); |
| 12797 | break; |
| 12798 | case 0x1d0: // xvcvuxwdp (VSX Vector Convert Unsigned Integer Word to Double-Precision format) |
| 12799 | DIP("xvcvuxwdp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12800 | putVSReg( XT, |
| 12801 | binop( Iop_64HLtoV128, |
| 12802 | unop( Iop_ReinterpF64asI64, |
| 12803 | binop( Iop_I64UtoF64, get_IR_roundingmode(), |
| 12804 | unop( Iop_32Uto64, mkexpr( b3 ) ) ) ), |
| 12805 | unop( Iop_ReinterpF64asI64, |
| 12806 | binop( Iop_I64UtoF64, get_IR_roundingmode(), |
| 12807 | unop( Iop_32Uto64, mkexpr( b1 ) ) ) ) ) ); |
| 12808 | break; |
| 12809 | case 0x170: // xvcvsxwsp (VSX Vector Convert Signed Integer Word to Single-Precision format) |
| 12810 | DIP("xvcvsxwsp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12811 | putVSReg( XT, unop( Iop_I32StoFx4, getVSReg( XB ) ) ); |
| 12812 | break; |
| 12813 | case 0x150: // xvcvuxwsp (VSX Vector Convert Unsigned Integer Word to Single-Precision format) |
| 12814 | DIP("xvcvuxwsp v%u,v%u\n", (UInt)XT, (UInt)XB); |
| 12815 | putVSReg( XT, unop( Iop_I32UtoFx4, getVSReg( XB ) ) ); |
| 12816 | break; |
| 12817 | |
| 12818 | default: |
| 12819 | vex_printf( "dis_vx_conv(ppc)(opc2)\n" ); |
| 12820 | return False; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 12821 | } |
| 12822 | return True; |
| 12823 | } |
| 12824 | |
| 12825 | /* |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12826 | * VSX vector Double Precision Floating Point Arithmetic Instructions |
| 12827 | */ |
| 12828 | static Bool |
| 12829 | dis_vxv_dp_arith ( UInt theInstr, UInt opc2 ) |
| 12830 | { |
| 12831 | /* XX3-Form */ |
| 12832 | UChar opc1 = ifieldOPC( theInstr ); |
| 12833 | UChar XT = ifieldRegXT( theInstr ); |
| 12834 | UChar XA = ifieldRegXA( theInstr ); |
| 12835 | UChar XB = ifieldRegXB( theInstr ); |
| 12836 | IRExpr* rm = get_IR_roundingmode(); |
| 12837 | IRTemp frA = newTemp(Ity_F64); |
| 12838 | IRTemp frB = newTemp(Ity_F64); |
| 12839 | IRTemp frA2 = newTemp(Ity_F64); |
| 12840 | IRTemp frB2 = newTemp(Ity_F64); |
| 12841 | |
| 12842 | if (opc1 != 0x3C) { |
| 12843 | vex_printf( "dis_vxv_dp_arith(ppc)(instr)\n" ); |
| 12844 | return False; |
| 12845 | } |
| 12846 | |
| 12847 | assign(frA, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XA )))); |
| 12848 | assign(frB, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XB )))); |
| 12849 | assign(frA2, unop(Iop_ReinterpI64asF64, unop(Iop_V128to64, getVSReg( XA )))); |
| 12850 | assign(frB2, unop(Iop_ReinterpI64asF64, unop(Iop_V128to64, getVSReg( XB )))); |
| 12851 | |
| 12852 | switch (opc2) { |
| 12853 | case 0x1E0: // xvdivdp (VSX Vector Divide Double-Precision) |
| 12854 | case 0x1C0: // xvmuldp (VSX Vector Multiply Double-Precision) |
| 12855 | case 0x180: // xvadddp (VSX Vector Add Double-Precision) |
| 12856 | case 0x1A0: // xvsubdp (VSX Vector Subtract Double-Precision) |
| 12857 | { |
| 12858 | IROp mOp; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 12859 | const HChar * oper_name; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12860 | switch (opc2) { |
| 12861 | case 0x1E0: |
| 12862 | mOp = Iop_DivF64; |
| 12863 | oper_name = "div"; |
| 12864 | break; |
| 12865 | case 0x1C0: |
| 12866 | mOp = Iop_MulF64; |
| 12867 | oper_name = "mul"; |
| 12868 | break; |
| 12869 | case 0x180: |
| 12870 | mOp = Iop_AddF64; |
| 12871 | oper_name = "add"; |
| 12872 | break; |
| 12873 | case 0x1A0: |
| 12874 | mOp = Iop_SubF64; |
| 12875 | oper_name = "sub"; |
| 12876 | break; |
| 12877 | |
| 12878 | default: |
| 12879 | vpanic("The impossible happened: dis_vxv_dp_arith(ppc)"); |
| 12880 | } |
| 12881 | IRTemp hiResult = newTemp(Ity_I64); |
| 12882 | IRTemp loResult = newTemp(Ity_I64); |
| 12883 | DIP("xv%sdp v%d,v%d,v%d\n", oper_name, (UInt)XT, (UInt)XA, (UInt)XB); |
| 12884 | |
| 12885 | assign( hiResult, |
| 12886 | unop( Iop_ReinterpF64asI64, |
| 12887 | triop( mOp, rm, mkexpr( frA ), mkexpr( frB ) ) ) ); |
| 12888 | assign( loResult, |
| 12889 | unop( Iop_ReinterpF64asI64, |
| 12890 | triop( mOp, rm, mkexpr( frA2 ), mkexpr( frB2 ) ) ) ); |
| 12891 | putVSReg( XT, |
| 12892 | binop( Iop_64HLtoV128, mkexpr( hiResult ), mkexpr( loResult ) ) ); |
| 12893 | break; |
| 12894 | } |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12895 | case 0x196: // xvsqrtdp |
| 12896 | { |
| 12897 | IRTemp hiResult = newTemp(Ity_I64); |
| 12898 | IRTemp loResult = newTemp(Ity_I64); |
| 12899 | DIP("xvsqrtdp v%d,v%d\n", (UInt)XT, (UInt)XB); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12900 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12901 | assign( hiResult, |
| 12902 | unop( Iop_ReinterpF64asI64, |
| 12903 | binop( Iop_SqrtF64, rm, mkexpr( frB ) ) ) ); |
| 12904 | assign( loResult, |
| 12905 | unop( Iop_ReinterpF64asI64, |
| 12906 | binop( Iop_SqrtF64, rm, mkexpr( frB2 ) ) ) ); |
| 12907 | putVSReg( XT, |
| 12908 | binop( Iop_64HLtoV128, mkexpr( hiResult ), mkexpr( loResult ) ) ); |
| 12909 | break; |
| 12910 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12911 | case 0x184: case 0x1A4: // xvmaddadp, xvmaddmdp (VSX Vector Multiply-Add Double-Precision) |
| 12912 | case 0x1C4: case 0x1E4: // xvmsubadp, xvmsubmdp (VSX Vector Multiply-Subtract Double-Precision) |
| 12913 | case 0x384: case 0x3A4: // xvnmaddadp, xvnmaddmdp (VSX Vector Negate Multiply-Add Double-Precision) |
| 12914 | case 0x3C4: case 0x3E4: // xvnmsubadp, xvnmsubmdp (VSX Vector Negate Multiply-Subtract Double-Precision) |
| 12915 | { |
| 12916 | /* xvm{add|sub}mdp XT,XA,XB is element-wise equivalent to fm{add|sub} FRT,FRA,FRC,FRB with . . . |
| 12917 | * XT == FRC |
| 12918 | * XA == FRA |
| 12919 | * XB == FRB |
| 12920 | * |
| 12921 | * and for xvm{add|sub}adp . . . |
| 12922 | * XT == FRB |
| 12923 | * XA == FRA |
| 12924 | * XB == FRC |
| 12925 | */ |
| 12926 | Bool negate; |
| 12927 | IROp mOp = Iop_INVALID; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 12928 | const HChar * oper_name = NULL; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 12929 | Bool mdp = False; |
| 12930 | |
| 12931 | switch (opc2) { |
| 12932 | case 0x184: case 0x1A4: |
| 12933 | case 0x384: case 0x3A4: |
| 12934 | mOp = Iop_MAddF64; |
| 12935 | oper_name = "add"; |
| 12936 | mdp = (opc2 & 0x0FF) == 0x0A4; |
| 12937 | break; |
| 12938 | |
| 12939 | case 0x1C4: case 0x1E4: |
| 12940 | case 0x3C4: case 0x3E4: |
| 12941 | mOp = Iop_MSubF64; |
| 12942 | oper_name = "sub"; |
| 12943 | mdp = (opc2 & 0x0FF) == 0x0E4; |
| 12944 | break; |
| 12945 | |
| 12946 | default: |
| 12947 | vpanic("The impossible happened: dis_vxv_sp_arith(ppc)"); |
| 12948 | } |
| 12949 | |
| 12950 | switch (opc2) { |
| 12951 | case 0x384: case 0x3A4: |
| 12952 | case 0x3C4: case 0x3E4: |
| 12953 | negate = True; |
| 12954 | break; |
| 12955 | default: |
| 12956 | negate = False; |
| 12957 | } |
| 12958 | IRTemp hiResult = newTemp(Ity_I64); |
| 12959 | IRTemp loResult = newTemp(Ity_I64); |
| 12960 | IRTemp frT = newTemp(Ity_F64); |
| 12961 | IRTemp frT2 = newTemp(Ity_F64); |
| 12962 | DIP("xv%sm%s%s v%d,v%d,v%d\n", negate ? "n" : "", oper_name, mdp ? "mdp" : "adp", |
| 12963 | (UInt)XT, (UInt)XA, (UInt)XB); |
| 12964 | assign(frT, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XT ) ) ) ); |
| 12965 | assign(frT2, unop(Iop_ReinterpI64asF64, unop(Iop_V128to64, getVSReg( XT ) ) ) ); |
| 12966 | |
| 12967 | assign( hiResult, |
| 12968 | unop( Iop_ReinterpF64asI64, |
| 12969 | qop( mOp, |
| 12970 | rm, |
| 12971 | mkexpr( frA ), |
| 12972 | mkexpr( mdp ? frT : frB ), |
| 12973 | mkexpr( mdp ? frB : frT ) ) ) ); |
| 12974 | assign( loResult, |
| 12975 | unop( Iop_ReinterpF64asI64, |
| 12976 | qop( mOp, |
| 12977 | rm, |
| 12978 | mkexpr( frA2 ), |
| 12979 | mkexpr( mdp ? frT2 : frB2 ), |
| 12980 | mkexpr( mdp ? frB2 : frT2 ) ) ) ); |
| 12981 | putVSReg( XT, |
| 12982 | binop( Iop_64HLtoV128, |
| 12983 | mkexpr( negate ? getNegatedResult( hiResult ) |
| 12984 | : hiResult ), |
| 12985 | mkexpr( negate ? getNegatedResult( loResult ) |
| 12986 | : loResult ) ) ); |
| 12987 | break; |
| 12988 | } |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 12989 | case 0x1D4: // xvtsqrtdp (VSX Vector Test for software Square Root Double-Precision) |
| 12990 | { |
| 12991 | IRTemp frBHi_I64 = newTemp(Ity_I64); |
| 12992 | IRTemp frBLo_I64 = newTemp(Ity_I64); |
| 12993 | IRTemp flagsHi = newTemp(Ity_I32); |
| 12994 | IRTemp flagsLo = newTemp(Ity_I32); |
| 12995 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 12996 | IRTemp fe_flagHi, fg_flagHi, fe_flagLo, fg_flagLo; |
| 12997 | fe_flagHi = fg_flagHi = fe_flagLo = fg_flagLo = IRTemp_INVALID; |
| 12998 | |
| 12999 | DIP("xvtsqrtdp cr%d,v%d\n", (UInt)crfD, (UInt)XB); |
| 13000 | assign( frBHi_I64, unop(Iop_V128HIto64, getVSReg( XB )) ); |
| 13001 | assign( frBLo_I64, unop(Iop_V128to64, getVSReg( XB )) ); |
| 13002 | do_fp_tsqrt(frBHi_I64, False /*not single precision*/, &fe_flagHi, &fg_flagHi); |
| 13003 | do_fp_tsqrt(frBLo_I64, False /*not single precision*/, &fe_flagLo, &fg_flagLo); |
| 13004 | /* The CR field consists of fl_flag || fg_flag || fe_flag || 0b0 |
| 13005 | * where fl_flag == 1 on ppc64. |
| 13006 | */ |
| 13007 | assign( flagsHi, |
| 13008 | binop( Iop_Or32, |
| 13009 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13010 | binop( Iop_Shl32, mkexpr(fg_flagHi), mkU8( 2 ) ) ), |
| 13011 | binop( Iop_Shl32, mkexpr(fe_flagHi), mkU8( 1 ) ) ) ); |
| 13012 | assign( flagsLo, |
| 13013 | binop( Iop_Or32, |
| 13014 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13015 | binop( Iop_Shl32, mkexpr(fg_flagLo), mkU8( 2 ) ) ), |
| 13016 | binop( Iop_Shl32, mkexpr(fe_flagLo), mkU8( 1 ) ) ) ); |
| 13017 | putGST_field( PPC_GST_CR, |
| 13018 | binop( Iop_Or32, mkexpr( flagsHi ), mkexpr( flagsLo ) ), |
| 13019 | crfD ); |
| 13020 | break; |
| 13021 | } |
| 13022 | case 0x1F4: // xvtdivdp (VSX Vector Test for software Divide Double-Precision) |
| 13023 | { |
| 13024 | IRTemp frBHi_I64 = newTemp(Ity_I64); |
| 13025 | IRTemp frBLo_I64 = newTemp(Ity_I64); |
| 13026 | IRTemp frAHi_I64 = newTemp(Ity_I64); |
| 13027 | IRTemp frALo_I64 = newTemp(Ity_I64); |
| 13028 | IRTemp flagsHi = newTemp(Ity_I32); |
| 13029 | IRTemp flagsLo = newTemp(Ity_I32); |
| 13030 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 13031 | IRTemp fe_flagHi, fg_flagHi, fe_flagLo, fg_flagLo; |
| 13032 | fe_flagHi = fg_flagHi = fe_flagLo = fg_flagLo = IRTemp_INVALID; |
| 13033 | |
| 13034 | DIP("xvtdivdp cr%d,v%d,v%d\n", (UInt)crfD, (UInt)XA, (UInt)XB); |
| 13035 | assign( frAHi_I64, unop(Iop_V128HIto64, getVSReg( XA )) ); |
| 13036 | assign( frALo_I64, unop(Iop_V128to64, getVSReg( XA )) ); |
| 13037 | assign( frBHi_I64, unop(Iop_V128HIto64, getVSReg( XB )) ); |
| 13038 | assign( frBLo_I64, unop(Iop_V128to64, getVSReg( XB )) ); |
| 13039 | |
| 13040 | _do_fp_tdiv(frAHi_I64, frBHi_I64, False/*dp*/, &fe_flagHi, &fg_flagHi); |
| 13041 | _do_fp_tdiv(frALo_I64, frBLo_I64, False/*dp*/, &fe_flagLo, &fg_flagLo); |
| 13042 | /* The CR field consists of fl_flag || fg_flag || fe_flag || 0b0 |
| 13043 | * where fl_flag == 1 on ppc64. |
| 13044 | */ |
| 13045 | assign( flagsHi, |
| 13046 | binop( Iop_Or32, |
| 13047 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13048 | binop( Iop_Shl32, mkexpr(fg_flagHi), mkU8( 2 ) ) ), |
| 13049 | binop( Iop_Shl32, mkexpr(fe_flagHi), mkU8( 1 ) ) ) ); |
| 13050 | assign( flagsLo, |
| 13051 | binop( Iop_Or32, |
| 13052 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13053 | binop( Iop_Shl32, mkexpr(fg_flagLo), mkU8( 2 ) ) ), |
| 13054 | binop( Iop_Shl32, mkexpr(fe_flagLo), mkU8( 1 ) ) ) ); |
| 13055 | putGST_field( PPC_GST_CR, |
| 13056 | binop( Iop_Or32, mkexpr( flagsHi ), mkexpr( flagsLo ) ), |
| 13057 | crfD ); |
| 13058 | break; |
| 13059 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13060 | |
| 13061 | default: |
| 13062 | vex_printf( "dis_vxv_dp_arith(ppc)(opc2)\n" ); |
| 13063 | return False; |
| 13064 | } |
| 13065 | return True; |
| 13066 | } |
| 13067 | |
| 13068 | /* |
| 13069 | * VSX vector Single Precision Floating Point Arithmetic Instructions |
| 13070 | */ |
| 13071 | static Bool |
| 13072 | dis_vxv_sp_arith ( UInt theInstr, UInt opc2 ) |
| 13073 | { |
| 13074 | /* XX3-Form */ |
| 13075 | UChar opc1 = ifieldOPC( theInstr ); |
| 13076 | UChar XT = ifieldRegXT( theInstr ); |
| 13077 | UChar XA = ifieldRegXA( theInstr ); |
| 13078 | UChar XB = ifieldRegXB( theInstr ); |
| 13079 | IRExpr* rm = get_IR_roundingmode(); |
| 13080 | IRTemp a3, a2, a1, a0; |
| 13081 | IRTemp b3, b2, b1, b0; |
| 13082 | IRTemp res0 = newTemp(Ity_I32); |
| 13083 | IRTemp res1 = newTemp(Ity_I32); |
| 13084 | IRTemp res2 = newTemp(Ity_I32); |
| 13085 | IRTemp res3 = newTemp(Ity_I32); |
| 13086 | |
| 13087 | a3 = a2 = a1 = a0 = IRTemp_INVALID; |
| 13088 | b3 = b2 = b1 = b0 = IRTemp_INVALID; |
| 13089 | |
| 13090 | if (opc1 != 0x3C) { |
| 13091 | vex_printf( "dis_vxv_sp_arith(ppc)(instr)\n" ); |
| 13092 | return False; |
| 13093 | } |
| 13094 | |
| 13095 | switch (opc2) { |
| 13096 | case 0x100: // xvaddsp (VSX Vector Add Single-Precision) |
| 13097 | DIP("xvaddsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 13098 | // WARNING: BOGUS! The backend ignores rm on Iop_Add32Fx4 |
| 13099 | putVSReg( XT, triop(Iop_Add32Fx4, rm, |
| 13100 | getVSReg( XA ), getVSReg( XB )) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13101 | break; |
| 13102 | |
| 13103 | case 0x140: // xvmulsp (VSX Vector Multiply Single-Precision) |
| 13104 | DIP("xvmulsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 13105 | // WARNING: BOGUS! The backend ignores rm on Iop_Mul32Fx4 |
| 13106 | putVSReg( XT, triop(Iop_Mul32Fx4, rm, |
| 13107 | getVSReg( XA ), getVSReg( XB )) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13108 | break; |
| 13109 | |
| 13110 | case 0x120: // xvsubsp (VSX Vector Subtract Single-Precision) |
| 13111 | DIP("xvsubsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 13112 | // WARNING: BOGUS! The backend ignores rm on Iop_Sub32Fx4 |
| 13113 | putVSReg( XT, triop(Iop_Sub32Fx4, rm, |
| 13114 | getVSReg( XA ), getVSReg( XB )) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13115 | break; |
| 13116 | |
| 13117 | case 0x160: // xvdivsp (VSX Vector Divide Single-Precision) |
| 13118 | { |
| 13119 | /* Iop_Div32Fx4 is not implemented for ppc64 (in host_ppc_{isel|defs}.c. |
| 13120 | * So there are two choices: |
| 13121 | * 1. Implement the xvdivsp with a native insn; or |
| 13122 | * 2. Extract the 4 single precision floats from each vector |
| 13123 | * register inputs and perform fdivs on each pair |
| 13124 | * I will do the latter, due to the general philosophy of |
| 13125 | * reusing existing implementations when practical. |
| 13126 | */ |
| 13127 | DIP("xvdivsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 13128 | breakV128to4xF64( getVSReg( XA ), &a3, &a2, &a1, &a0 ); |
| 13129 | breakV128to4xF64( getVSReg( XB ), &b3, &b2, &b1, &b0 ); |
| 13130 | |
| 13131 | assign( res0, |
| 13132 | unop( Iop_ReinterpF32asI32, |
| 13133 | unop( Iop_TruncF64asF32, |
| 13134 | triop( Iop_DivF64r32, rm, mkexpr( a0 ), mkexpr( b0 ) ) ) ) ); |
| 13135 | assign( res1, |
| 13136 | unop( Iop_ReinterpF32asI32, |
| 13137 | unop( Iop_TruncF64asF32, |
| 13138 | triop( Iop_DivF64r32, rm, mkexpr( a1 ), mkexpr( b1 ) ) ) ) ); |
| 13139 | assign( res2, |
| 13140 | unop( Iop_ReinterpF32asI32, |
| 13141 | unop( Iop_TruncF64asF32, |
| 13142 | triop( Iop_DivF64r32, rm, mkexpr( a2 ), mkexpr( b2 ) ) ) ) ); |
| 13143 | assign( res3, |
| 13144 | unop( Iop_ReinterpF32asI32, |
| 13145 | unop( Iop_TruncF64asF32, |
| 13146 | triop( Iop_DivF64r32, rm, mkexpr( a3 ), mkexpr( b3 ) ) ) ) ); |
| 13147 | |
| 13148 | putVSReg( XT, |
| 13149 | binop( Iop_64HLtoV128, |
| 13150 | binop( Iop_32HLto64, mkexpr( res3 ), mkexpr( res2 ) ), |
| 13151 | binop( Iop_32HLto64, mkexpr( res1 ), mkexpr( res0 ) ) ) ); |
| 13152 | break; |
| 13153 | } |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13154 | case 0x116: // xvsqrtsp (VSX Vector Square Root Single-Precision) |
| 13155 | { |
| 13156 | DIP("xvsqrtsp v%d,v%d\n", (UInt)XT, (UInt)XB); |
| 13157 | breakV128to4xF64( getVSReg( XB ), &b3, &b2, &b1, &b0 ); |
| 13158 | /* Note: The native xvsqrtsp insruction does not always give the same precision |
| 13159 | * as what we get with Iop_SqrtF64. But it doesn't seem worthwhile to implement |
| 13160 | * an Iop_SqrtF32 that would give us a lower precision result, albeit more true |
| 13161 | * to the actual instruction. |
| 13162 | */ |
| 13163 | |
| 13164 | assign( res0, |
| 13165 | unop( Iop_ReinterpF32asI32, |
| 13166 | unop( Iop_TruncF64asF32, |
| 13167 | binop(Iop_SqrtF64, rm, mkexpr( b0 ) ) ) ) ); |
| 13168 | assign( res1, |
| 13169 | unop( Iop_ReinterpF32asI32, |
| 13170 | unop( Iop_TruncF64asF32, |
| 13171 | binop(Iop_SqrtF64, rm, mkexpr( b1 ) ) ) ) ); |
| 13172 | assign( res2, |
| 13173 | unop( Iop_ReinterpF32asI32, |
| 13174 | unop( Iop_TruncF64asF32, |
| 13175 | binop(Iop_SqrtF64, rm, mkexpr( b2) ) ) ) ); |
| 13176 | assign( res3, |
| 13177 | unop( Iop_ReinterpF32asI32, |
| 13178 | unop( Iop_TruncF64asF32, |
| 13179 | binop(Iop_SqrtF64, rm, mkexpr( b3 ) ) ) ) ); |
| 13180 | |
| 13181 | putVSReg( XT, |
| 13182 | binop( Iop_64HLtoV128, |
| 13183 | binop( Iop_32HLto64, mkexpr( res3 ), mkexpr( res2 ) ), |
| 13184 | binop( Iop_32HLto64, mkexpr( res1 ), mkexpr( res0 ) ) ) ); |
| 13185 | break; |
| 13186 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13187 | |
| 13188 | case 0x104: case 0x124: // xvmaddasp, xvmaddmsp (VSX Vector Multiply-Add Single-Precision) |
| 13189 | case 0x144: case 0x164: // xvmsubasp, xvmsubmsp (VSX Vector Multiply-Subtract Single-Precision) |
| 13190 | case 0x304: case 0x324: // xvnmaddasp, xvnmaddmsp (VSX Vector Negate Multiply-Add Single-Precision) |
| 13191 | case 0x344: case 0x364: // xvnmsubasp, xvnmsubmsp (VSX Vector Negate Multiply-Subtract Single-Precision) |
| 13192 | { |
| 13193 | IRTemp t3, t2, t1, t0; |
| 13194 | Bool msp = False; |
| 13195 | Bool negate; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 13196 | const HChar * oper_name = NULL; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13197 | IROp mOp = Iop_INVALID; |
| 13198 | switch (opc2) { |
| 13199 | case 0x104: case 0x124: |
| 13200 | case 0x304: case 0x324: |
| 13201 | msp = (opc2 & 0x0FF) == 0x024; |
| 13202 | mOp = Iop_MAddF64r32; |
| 13203 | oper_name = "madd"; |
| 13204 | break; |
| 13205 | |
| 13206 | case 0x144: case 0x164: |
| 13207 | case 0x344: case 0x364: |
| 13208 | msp = (opc2 & 0x0FF) == 0x064; |
| 13209 | mOp = Iop_MSubF64r32; |
| 13210 | oper_name = "sub"; |
| 13211 | break; |
| 13212 | |
| 13213 | default: |
| 13214 | vpanic("The impossible happened: dis_vxv_sp_arith(ppc)"); |
| 13215 | } |
| 13216 | |
| 13217 | switch (opc2) { |
| 13218 | case 0x304: case 0x324: |
| 13219 | case 0x344: case 0x364: |
| 13220 | negate = True; |
| 13221 | break; |
| 13222 | |
| 13223 | default: |
| 13224 | negate = False; |
| 13225 | } |
| 13226 | |
| 13227 | DIP("xv%sm%s%s v%d,v%d,v%d\n", negate ? "n" : "", oper_name, msp ? "msp" : "asp", |
| 13228 | (UInt)XT, (UInt)XA, (UInt)XB); |
| 13229 | |
| 13230 | t3 = t2 = t1 = t0 = IRTemp_INVALID; |
| 13231 | breakV128to4xF64( getVSReg( XA ), &a3, &a2, &a1, &a0 ); |
| 13232 | breakV128to4xF64( getVSReg( XB ), &b3, &b2, &b1, &b0 ); |
| 13233 | breakV128to4xF64( getVSReg( XT ), &t3, &t2, &t1, &t0 ); |
| 13234 | |
| 13235 | assign( res0, |
| 13236 | unop( Iop_ReinterpF32asI32, |
| 13237 | unop( Iop_TruncF64asF32, |
| 13238 | qop( mOp, |
| 13239 | rm, |
| 13240 | mkexpr( a0 ), |
| 13241 | mkexpr( msp ? t0 : b0 ), |
| 13242 | mkexpr( msp ? b0 : t0 ) ) ) ) ); |
| 13243 | assign( res1, |
| 13244 | unop( Iop_ReinterpF32asI32, |
| 13245 | unop( Iop_TruncF64asF32, |
| 13246 | qop( mOp, |
| 13247 | rm, |
| 13248 | mkexpr( a1 ), |
| 13249 | mkexpr( msp ? t1 : b1 ), |
| 13250 | mkexpr( msp ? b1 : t1 ) ) ) ) ); |
| 13251 | assign( res2, |
| 13252 | unop( Iop_ReinterpF32asI32, |
| 13253 | unop( Iop_TruncF64asF32, |
| 13254 | qop( mOp, |
| 13255 | rm, |
| 13256 | mkexpr( a2 ), |
| 13257 | mkexpr( msp ? t2 : b2 ), |
| 13258 | mkexpr( msp ? b2 : t2 ) ) ) ) ); |
| 13259 | assign( res3, |
| 13260 | unop( Iop_ReinterpF32asI32, |
| 13261 | unop( Iop_TruncF64asF32, |
| 13262 | qop( mOp, |
| 13263 | rm, |
| 13264 | mkexpr( a3 ), |
| 13265 | mkexpr( msp ? t3 : b3 ), |
| 13266 | mkexpr( msp ? b3 : t3 ) ) ) ) ); |
| 13267 | |
| 13268 | putVSReg( XT, |
| 13269 | binop( Iop_64HLtoV128, |
| 13270 | binop( Iop_32HLto64, mkexpr( negate ? getNegatedResult_32( res3 ) : res3 ), |
| 13271 | mkexpr( negate ? getNegatedResult_32( res2 ) : res2 ) ), |
| 13272 | binop( Iop_32HLto64, mkexpr( negate ? getNegatedResult_32( res1 ) : res1 ), |
| 13273 | mkexpr( negate ? getNegatedResult_32( res0 ) : res0 ) ) ) ); |
| 13274 | |
| 13275 | break; |
| 13276 | } |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13277 | case 0x154: // xvtsqrtsp (VSX Vector Test for software Square Root Single-Precision) |
| 13278 | { |
| 13279 | IRTemp flags0 = newTemp(Ity_I32); |
| 13280 | IRTemp flags1 = newTemp(Ity_I32); |
| 13281 | IRTemp flags2 = newTemp(Ity_I32); |
| 13282 | IRTemp flags3 = newTemp(Ity_I32); |
| 13283 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 13284 | IRTemp fe_flag0, fg_flag0, fe_flag1, fg_flag1; |
| 13285 | IRTemp fe_flag2, fg_flag2, fe_flag3, fg_flag3; |
| 13286 | fe_flag0 = fg_flag0 = fe_flag1 = fg_flag1 = IRTemp_INVALID; |
| 13287 | fe_flag2 = fg_flag2 = fe_flag3 = fg_flag3 = IRTemp_INVALID; |
| 13288 | DIP("xvtsqrtsp cr%d,v%d\n", (UInt)crfD, (UInt)XB); |
| 13289 | |
| 13290 | breakV128to4x32( getVSReg( XB ), &b3, &b2, &b1, &b0 ); |
| 13291 | do_fp_tsqrt(b0, True /* single precision*/, &fe_flag0, &fg_flag0); |
| 13292 | do_fp_tsqrt(b1, True /* single precision*/, &fe_flag1, &fg_flag1); |
| 13293 | do_fp_tsqrt(b2, True /* single precision*/, &fe_flag2, &fg_flag2); |
| 13294 | do_fp_tsqrt(b3, True /* single precision*/, &fe_flag3, &fg_flag3); |
| 13295 | |
| 13296 | /* The CR field consists of fl_flag || fg_flag || fe_flag || 0b0 |
| 13297 | * where fl_flag == 1 on ppc64. |
| 13298 | */ |
| 13299 | assign( flags0, |
| 13300 | binop( Iop_Or32, |
| 13301 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13302 | binop( Iop_Shl32, mkexpr(fg_flag0), mkU8( 2 ) ) ), |
| 13303 | binop( Iop_Shl32, mkexpr(fe_flag0), mkU8( 1 ) ) ) ); |
| 13304 | assign( flags1, |
| 13305 | binop( Iop_Or32, |
| 13306 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13307 | binop( Iop_Shl32, mkexpr(fg_flag1), mkU8( 2 ) ) ), |
| 13308 | binop( Iop_Shl32, mkexpr(fe_flag1), mkU8( 1 ) ) ) ); |
| 13309 | assign( flags2, |
| 13310 | binop( Iop_Or32, |
| 13311 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13312 | binop( Iop_Shl32, mkexpr(fg_flag2), mkU8( 2 ) ) ), |
| 13313 | binop( Iop_Shl32, mkexpr(fe_flag2), mkU8( 1 ) ) ) ); |
| 13314 | assign( flags3, |
| 13315 | binop( Iop_Or32, |
| 13316 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13317 | binop( Iop_Shl32, mkexpr(fg_flag3), mkU8( 2 ) ) ), |
| 13318 | binop( Iop_Shl32, mkexpr(fe_flag3), mkU8( 1 ) ) ) ); |
| 13319 | putGST_field( PPC_GST_CR, |
| 13320 | binop( Iop_Or32, |
| 13321 | mkexpr( flags0 ), |
| 13322 | binop( Iop_Or32, |
| 13323 | mkexpr( flags1 ), |
| 13324 | binop( Iop_Or32, |
| 13325 | mkexpr( flags2 ), |
| 13326 | mkexpr( flags3 ) ) ) ), |
| 13327 | crfD ); |
| 13328 | |
| 13329 | break; |
| 13330 | } |
| 13331 | case 0x174: // xvtdivsp (VSX Vector Test for software Divide Single-Precision) |
| 13332 | { |
| 13333 | IRTemp flags0 = newTemp(Ity_I32); |
| 13334 | IRTemp flags1 = newTemp(Ity_I32); |
| 13335 | IRTemp flags2 = newTemp(Ity_I32); |
| 13336 | IRTemp flags3 = newTemp(Ity_I32); |
| 13337 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 13338 | IRTemp fe_flag0, fg_flag0, fe_flag1, fg_flag1; |
| 13339 | IRTemp fe_flag2, fg_flag2, fe_flag3, fg_flag3; |
| 13340 | fe_flag0 = fg_flag0 = fe_flag1 = fg_flag1 = IRTemp_INVALID; |
| 13341 | fe_flag2 = fg_flag2 = fe_flag3 = fg_flag3 = IRTemp_INVALID; |
| 13342 | DIP("xvtdivsp cr%d,v%d,v%d\n", (UInt)crfD, (UInt)XA, (UInt)XB); |
| 13343 | |
| 13344 | breakV128to4x32( getVSReg( XA ), &a3, &a2, &a1, &a0 ); |
| 13345 | breakV128to4x32( getVSReg( XB ), &b3, &b2, &b1, &b0 ); |
| 13346 | _do_fp_tdiv(a0, b0, True /* single precision*/, &fe_flag0, &fg_flag0); |
| 13347 | _do_fp_tdiv(a1, b1, True /* single precision*/, &fe_flag1, &fg_flag1); |
| 13348 | _do_fp_tdiv(a2, b2, True /* single precision*/, &fe_flag2, &fg_flag2); |
| 13349 | _do_fp_tdiv(a3, b3, True /* single precision*/, &fe_flag3, &fg_flag3); |
| 13350 | |
| 13351 | /* The CR field consists of fl_flag || fg_flag || fe_flag || 0b0 |
| 13352 | * where fl_flag == 1 on ppc64. |
| 13353 | */ |
| 13354 | assign( flags0, |
| 13355 | binop( Iop_Or32, |
| 13356 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13357 | binop( Iop_Shl32, mkexpr(fg_flag0), mkU8( 2 ) ) ), |
| 13358 | binop( Iop_Shl32, mkexpr(fe_flag0), mkU8( 1 ) ) ) ); |
| 13359 | assign( flags1, |
| 13360 | binop( Iop_Or32, |
| 13361 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13362 | binop( Iop_Shl32, mkexpr(fg_flag1), mkU8( 2 ) ) ), |
| 13363 | binop( Iop_Shl32, mkexpr(fe_flag1), mkU8( 1 ) ) ) ); |
| 13364 | assign( flags2, |
| 13365 | binop( Iop_Or32, |
| 13366 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13367 | binop( Iop_Shl32, mkexpr(fg_flag2), mkU8( 2 ) ) ), |
| 13368 | binop( Iop_Shl32, mkexpr(fe_flag2), mkU8( 1 ) ) ) ); |
| 13369 | assign( flags3, |
| 13370 | binop( Iop_Or32, |
| 13371 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 13372 | binop( Iop_Shl32, mkexpr(fg_flag3), mkU8( 2 ) ) ), |
| 13373 | binop( Iop_Shl32, mkexpr(fe_flag3), mkU8( 1 ) ) ) ); |
| 13374 | putGST_field( PPC_GST_CR, |
| 13375 | binop( Iop_Or32, |
| 13376 | mkexpr( flags0 ), |
| 13377 | binop( Iop_Or32, |
| 13378 | mkexpr( flags1 ), |
| 13379 | binop( Iop_Or32, |
| 13380 | mkexpr( flags2 ), |
| 13381 | mkexpr( flags3 ) ) ) ), |
| 13382 | crfD ); |
| 13383 | |
| 13384 | break; |
| 13385 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13386 | |
| 13387 | default: |
| 13388 | vex_printf( "dis_vxv_sp_arith(ppc)(opc2)\n" ); |
| 13389 | return False; |
| 13390 | } |
| 13391 | return True; |
| 13392 | } |
| 13393 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 13394 | /* |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 13395 | * Vector Population Count/bit matrix transpose |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 13396 | */ |
| 13397 | static Bool |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 13398 | dis_av_count_bitTranspose ( UInt theInstr, UInt opc2 ) |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 13399 | { |
| 13400 | UChar vRB_addr = ifieldRegB(theInstr); |
| 13401 | UChar vRT_addr = ifieldRegDS(theInstr); |
| 13402 | UChar opc1 = ifieldOPC( theInstr ); |
| 13403 | IRTemp vB = newTemp(Ity_V128); |
| 13404 | assign( vB, getVReg(vRB_addr)); |
| 13405 | |
| 13406 | if (opc1 != 0x4) { |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 13407 | vex_printf( "dis_av_count_bitTranspose(ppc)(instr)\n" ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 13408 | return False; |
| 13409 | } |
| 13410 | |
| 13411 | switch (opc2) { |
| 13412 | case 0x702: // vclzb |
| 13413 | DIP("vclzb v%d,v%d\n", vRT_addr, vRB_addr); |
sewardj | a8c7b0f | 2014-06-26 08:18:08 +0000 | [diff] [blame] | 13414 | putVReg( vRT_addr, unop(Iop_Clz8x16, mkexpr( vB ) ) ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 13415 | break; |
| 13416 | |
| 13417 | case 0x742: // vclzh |
| 13418 | DIP("vclzh v%d,v%d\n", vRT_addr, vRB_addr); |
sewardj | a8c7b0f | 2014-06-26 08:18:08 +0000 | [diff] [blame] | 13419 | putVReg( vRT_addr, unop(Iop_Clz16x8, mkexpr( vB ) ) ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 13420 | break; |
| 13421 | |
| 13422 | case 0x782: // vclzw |
| 13423 | DIP("vclzw v%d,v%d\n", vRT_addr, vRB_addr); |
sewardj | a8c7b0f | 2014-06-26 08:18:08 +0000 | [diff] [blame] | 13424 | putVReg( vRT_addr, unop(Iop_Clz32x4, mkexpr( vB ) ) ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 13425 | break; |
| 13426 | |
| 13427 | case 0x7C2: // vclzd |
| 13428 | DIP("vclzd v%d,v%d\n", vRT_addr, vRB_addr); |
| 13429 | putVReg( vRT_addr, unop(Iop_Clz64x2, mkexpr( vB ) ) ); |
| 13430 | break; |
| 13431 | |
| 13432 | case 0x703: // vpopcntb |
| 13433 | { |
| 13434 | /* Break vector into 32-bit words and do the population count |
| 13435 | * on byte in the words |
| 13436 | */ |
| 13437 | IRType ty = Ity_I32; |
| 13438 | IRTemp bits0_31, bits32_63, bits64_95, bits96_127; |
| 13439 | bits0_31 = bits32_63 = bits64_95 = bits96_127 = IRTemp_INVALID; |
| 13440 | IRTemp cnt_bits0_31, cnt_bits32_63, cnt_bits64_95, cnt_bits96_127; |
| 13441 | cnt_bits0_31 = cnt_bits32_63 = cnt_bits64_95 = cnt_bits96_127 = IRTemp_INVALID; |
| 13442 | |
| 13443 | DIP("vpopcntb v%d,v%d\n", vRT_addr, vRB_addr); |
| 13444 | breakV128to4x32(mkexpr( vB), &bits96_127, &bits64_95, &bits32_63, &bits0_31 ); |
| 13445 | cnt_bits0_31 = gen_POPCOUNT(ty, bits0_31, BYTE); |
| 13446 | cnt_bits32_63 = gen_POPCOUNT(ty, bits32_63, BYTE); |
| 13447 | cnt_bits64_95 = gen_POPCOUNT(ty, bits64_95, BYTE); |
| 13448 | cnt_bits96_127 = gen_POPCOUNT(ty, bits96_127, BYTE); |
| 13449 | |
| 13450 | putVReg( vRT_addr, mkV128from32(cnt_bits96_127, cnt_bits64_95, |
| 13451 | cnt_bits32_63, cnt_bits0_31) ); |
| 13452 | break; |
| 13453 | } |
| 13454 | |
| 13455 | case 0x743: // vpopcnth |
| 13456 | { |
| 13457 | /* Break vector into 32-bit words and do the population count |
| 13458 | * for each half word |
| 13459 | */ |
| 13460 | IRType ty = Ity_I32; |
| 13461 | IRTemp bits0_31, bits32_63, bits64_95, bits96_127; |
| 13462 | bits0_31 = bits32_63 = bits64_95 = bits96_127 = IRTemp_INVALID; |
| 13463 | IRTemp cnt_bits0_31, cnt_bits32_63, cnt_bits64_95, cnt_bits96_127; |
| 13464 | cnt_bits0_31 = cnt_bits32_63 = cnt_bits64_95 = cnt_bits96_127 = IRTemp_INVALID; |
| 13465 | |
| 13466 | DIP("vpopcnth v%d,v%d\n", vRT_addr, vRB_addr); |
| 13467 | breakV128to4x32(mkexpr( vB), &bits96_127, &bits64_95, &bits32_63, &bits0_31 ); |
| 13468 | |
| 13469 | cnt_bits0_31 = gen_POPCOUNT(ty, bits0_31, HWORD); |
| 13470 | cnt_bits32_63 = gen_POPCOUNT(ty, bits32_63, HWORD); |
| 13471 | cnt_bits64_95 = gen_POPCOUNT(ty, bits64_95, HWORD); |
| 13472 | cnt_bits96_127 = gen_POPCOUNT(ty, bits96_127, HWORD); |
| 13473 | |
| 13474 | putVReg( vRT_addr, mkV128from32(cnt_bits96_127, cnt_bits64_95, |
| 13475 | cnt_bits32_63, cnt_bits0_31) ); |
| 13476 | break; |
| 13477 | } |
| 13478 | |
| 13479 | case 0x783: // vpopcntw |
| 13480 | { |
| 13481 | /* Break vector into 32-bit words and do the population count |
| 13482 | * on each word. |
| 13483 | */ |
| 13484 | IRType ty = Ity_I32; |
| 13485 | IRTemp bits0_31, bits32_63, bits64_95, bits96_127; |
| 13486 | bits0_31 = bits32_63 = bits64_95 = bits96_127 = IRTemp_INVALID; |
| 13487 | IRTemp cnt_bits0_31, cnt_bits32_63, cnt_bits64_95, cnt_bits96_127; |
| 13488 | cnt_bits0_31 = cnt_bits32_63 = cnt_bits64_95 = cnt_bits96_127 = IRTemp_INVALID; |
| 13489 | |
| 13490 | DIP("vpopcntw v%d,v%d\n", vRT_addr, vRB_addr); |
| 13491 | breakV128to4x32(mkexpr( vB), &bits96_127, &bits64_95, &bits32_63, &bits0_31 ); |
| 13492 | |
| 13493 | cnt_bits0_31 = gen_POPCOUNT(ty, bits0_31, WORD); |
| 13494 | cnt_bits32_63 = gen_POPCOUNT(ty, bits32_63, WORD); |
| 13495 | cnt_bits64_95 = gen_POPCOUNT(ty, bits64_95, WORD); |
| 13496 | cnt_bits96_127 = gen_POPCOUNT(ty, bits96_127, WORD); |
| 13497 | |
| 13498 | putVReg( vRT_addr, mkV128from32(cnt_bits96_127, cnt_bits64_95, |
| 13499 | cnt_bits32_63, cnt_bits0_31) ); |
| 13500 | break; |
| 13501 | } |
| 13502 | |
| 13503 | case 0x7C3: // vpopcntd |
| 13504 | { |
| 13505 | if (mode64) { |
| 13506 | /* Break vector into 64-bit double words and do the population count |
| 13507 | * on each double word. |
| 13508 | */ |
| 13509 | IRType ty = Ity_I64; |
| 13510 | IRTemp bits0_63 = newTemp(Ity_I64); |
| 13511 | IRTemp bits64_127 = newTemp(Ity_I64); |
| 13512 | IRTemp cnt_bits0_63 = newTemp(Ity_I64); |
| 13513 | IRTemp cnt_bits64_127 = newTemp(Ity_I64); |
| 13514 | |
| 13515 | DIP("vpopcntd v%d,v%d\n", vRT_addr, vRB_addr); |
| 13516 | |
| 13517 | assign(bits0_63, unop( Iop_V128to64, mkexpr( vB ) ) ); |
| 13518 | assign(bits64_127, unop( Iop_V128HIto64, mkexpr( vB ) ) ); |
| 13519 | cnt_bits0_63 = gen_POPCOUNT(ty, bits0_63, DWORD); |
| 13520 | cnt_bits64_127 = gen_POPCOUNT(ty, bits64_127, DWORD); |
| 13521 | |
| 13522 | putVReg( vRT_addr, binop( Iop_64HLtoV128, |
| 13523 | mkexpr( cnt_bits64_127 ), |
| 13524 | mkexpr( cnt_bits0_63 ) ) ); |
| 13525 | } else { |
| 13526 | /* Break vector into 32-bit words and do the population count |
| 13527 | * on each doubleword. |
| 13528 | */ |
| 13529 | IRTemp bits0_31, bits32_63, bits64_95, bits96_127; |
| 13530 | bits0_31 = bits32_63 = bits64_95 = bits96_127 = IRTemp_INVALID; |
| 13531 | IRTemp cnt_bits0_63 = newTemp(Ity_I64); |
| 13532 | IRTemp cnt_bits64_127 = newTemp(Ity_I64); |
| 13533 | |
| 13534 | DIP("vpopcntd v%d,v%d\n", vRT_addr, vRB_addr); |
| 13535 | breakV128to4x32(mkexpr( vB), &bits96_127, &bits64_95, &bits32_63, &bits0_31 ); |
| 13536 | |
| 13537 | cnt_bits0_63 = gen_vpopcntd_mode32(bits0_31, bits32_63); |
| 13538 | cnt_bits64_127 = gen_vpopcntd_mode32(bits64_95, bits96_127); |
| 13539 | |
| 13540 | putVReg( vRT_addr, binop( Iop_64HLtoV128, |
| 13541 | mkexpr( cnt_bits64_127 ), |
| 13542 | mkexpr( cnt_bits0_63 ) ) ); |
| 13543 | } |
| 13544 | break; |
| 13545 | } |
| 13546 | |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 13547 | case 0x50C: // vgbbd Vector Gather Bits by Bytes by Doubleword |
| 13548 | DIP("vgbbd v%d,v%d\n", vRT_addr, vRB_addr); |
| 13549 | putVReg( vRT_addr, unop( Iop_PwBitMtxXpose64x2, mkexpr( vB ) ) ); |
| 13550 | break; |
| 13551 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 13552 | default: |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 13553 | vex_printf("dis_av_count_bitTranspose(ppc)(opc2)\n"); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 13554 | return False; |
| 13555 | break; |
| 13556 | } |
| 13557 | return True; |
| 13558 | } |
| 13559 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13560 | typedef enum { |
| 13561 | PPC_CMP_EQ = 2, |
| 13562 | PPC_CMP_GT = 4, |
| 13563 | PPC_CMP_GE = 6, |
| 13564 | PPC_CMP_LT = 8 |
| 13565 | } ppc_cmp_t; |
| 13566 | |
| 13567 | |
| 13568 | /* |
| 13569 | This helper function takes as input the IRExpr returned |
| 13570 | from a binop( Iop_CmpF64, fpA, fpB), whose result is returned |
| 13571 | in IR form. This helper function converts it to PPC form. |
| 13572 | |
| 13573 | Map compare result from IR to PPC |
| 13574 | |
| 13575 | FP cmp result | PPC | IR |
| 13576 | -------------------------- |
| 13577 | UN | 0x1 | 0x45 |
| 13578 | EQ | 0x2 | 0x40 |
| 13579 | GT | 0x4 | 0x00 |
| 13580 | LT | 0x8 | 0x01 |
| 13581 | |
| 13582 | condcode = Shl(1, (~(ccIR>>5) & 2) |
| 13583 | | ((ccIR ^ (ccIR>>6)) & 1) |
| 13584 | */ |
| 13585 | static IRTemp |
| 13586 | get_fp_cmp_CR_val (IRExpr * ccIR_expr) |
| 13587 | { |
| 13588 | IRTemp condcode = newTemp( Ity_I32 ); |
| 13589 | IRTemp ccIR = newTemp( Ity_I32 ); |
| 13590 | |
| 13591 | assign(ccIR, ccIR_expr); |
| 13592 | assign( condcode, |
| 13593 | binop( Iop_Shl32, |
| 13594 | mkU32( 1 ), |
| 13595 | unop( Iop_32to8, |
| 13596 | binop( Iop_Or32, |
| 13597 | binop( Iop_And32, |
| 13598 | unop( Iop_Not32, |
| 13599 | binop( Iop_Shr32, |
| 13600 | mkexpr( ccIR ), |
| 13601 | mkU8( 5 ) ) ), |
| 13602 | mkU32( 2 ) ), |
| 13603 | binop( Iop_And32, |
| 13604 | binop( Iop_Xor32, |
| 13605 | mkexpr( ccIR ), |
| 13606 | binop( Iop_Shr32, |
| 13607 | mkexpr( ccIR ), |
| 13608 | mkU8( 6 ) ) ), |
| 13609 | mkU32( 1 ) ) ) ) ) ); |
| 13610 | return condcode; |
| 13611 | } |
| 13612 | |
| 13613 | /* |
| 13614 | * Helper function for get_max_min_fp for ascertaining the max or min between two doubles |
| 13615 | * following these special rules: |
| 13616 | * - The max/min of a QNaN and any value is that value |
| 13617 | * (When two QNaNs are being compared, the frA QNaN is the return value.) |
| 13618 | * - The max/min of any value and an SNaN is that SNaN converted to a QNaN |
| 13619 | * (When two SNaNs are being compared, the frA SNaN is converted to a QNaN.) |
| 13620 | */ |
| 13621 | static IRExpr * _get_maxmin_fp_NaN(IRTemp frA_I64, IRTemp frB_I64) |
| 13622 | { |
| 13623 | IRTemp frA_isNaN = newTemp(Ity_I1); |
| 13624 | IRTemp frB_isNaN = newTemp(Ity_I1); |
| 13625 | IRTemp frA_isSNaN = newTemp(Ity_I1); |
| 13626 | IRTemp frB_isSNaN = newTemp(Ity_I1); |
| 13627 | IRTemp frA_isQNaN = newTemp(Ity_I1); |
| 13628 | IRTemp frB_isQNaN = newTemp(Ity_I1); |
| 13629 | |
| 13630 | assign( frA_isNaN, is_NaN( frA_I64 ) ); |
| 13631 | assign( frB_isNaN, is_NaN( frB_I64 ) ); |
| 13632 | // If operand is a NAN and bit 12 is '0', then it's an SNaN |
| 13633 | assign( frA_isSNaN, |
| 13634 | mkAND1( mkexpr(frA_isNaN), |
| 13635 | binop( Iop_CmpEQ32, |
| 13636 | binop( Iop_And32, |
| 13637 | unop( Iop_64HIto32, mkexpr( frA_I64 ) ), |
| 13638 | mkU32( 0x00080000 ) ), |
| 13639 | mkU32( 0 ) ) ) ); |
| 13640 | assign( frB_isSNaN, |
| 13641 | mkAND1( mkexpr(frB_isNaN), |
| 13642 | binop( Iop_CmpEQ32, |
| 13643 | binop( Iop_And32, |
| 13644 | unop( Iop_64HIto32, mkexpr( frB_I64 ) ), |
| 13645 | mkU32( 0x00080000 ) ), |
| 13646 | mkU32( 0 ) ) ) ); |
| 13647 | assign( frA_isQNaN, |
| 13648 | mkAND1( mkexpr( frA_isNaN ), unop( Iop_Not1, mkexpr( frA_isSNaN ) ) ) ); |
| 13649 | assign( frB_isQNaN, |
| 13650 | mkAND1( mkexpr( frB_isNaN ), unop( Iop_Not1, mkexpr( frB_isSNaN ) ) ) ); |
| 13651 | |
| 13652 | /* Based on the rules specified in the function prologue, the algorithm is as follows: |
| 13653 | * <<<<<<<<<>>>>>>>>>>>>>>>>>> |
| 13654 | * if frA is a SNaN |
| 13655 | * result = frA converted to QNaN |
| 13656 | * else if frB is a SNaN |
| 13657 | * result = frB converted to QNaN |
| 13658 | * else if frB is a QNaN |
| 13659 | * result = frA |
| 13660 | * // One of frA or frB was a NaN in order for this function to be called, so |
| 13661 | * // if we get to this point, we KNOW that frA must be a QNaN. |
| 13662 | * else // frA is a QNaN |
| 13663 | * result = frB |
| 13664 | * <<<<<<<<<>>>>>>>>>>>>>>>>>> |
| 13665 | */ |
| 13666 | |
| 13667 | #define SNAN_MASK 0x0008000000000000ULL |
| 13668 | return |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 13669 | IRExpr_ITE(mkexpr(frA_isSNaN), |
| 13670 | /* then: result = frA converted to QNaN */ |
| 13671 | binop(Iop_Or64, mkexpr(frA_I64), mkU64(SNAN_MASK)), |
| 13672 | /* else: if frB is a SNaN */ |
| 13673 | IRExpr_ITE(mkexpr(frB_isSNaN), |
| 13674 | /* then: result = frB converted to QNaN */ |
| 13675 | binop(Iop_Or64, mkexpr(frB_I64), mkU64(SNAN_MASK)), |
| 13676 | /* else: if frB is a QNaN */ |
| 13677 | IRExpr_ITE(mkexpr(frB_isQNaN), |
| 13678 | /* then: result = frA */ |
| 13679 | mkexpr(frA_I64), |
| 13680 | /* else: frA is a QNaN, so result = frB */ |
| 13681 | mkexpr(frB_I64)))); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13682 | } |
| 13683 | |
| 13684 | /* |
| 13685 | * Helper function for get_max_min_fp. |
| 13686 | */ |
| 13687 | static IRExpr * _get_maxmin_fp_cmp(IRTemp src1, IRTemp src2, Bool isMin) |
| 13688 | { |
| 13689 | IRTemp src1cmpsrc2 = get_fp_cmp_CR_val( binop( Iop_CmpF64, |
| 13690 | unop( Iop_ReinterpI64asF64, |
| 13691 | mkexpr( src1 ) ), |
| 13692 | unop( Iop_ReinterpI64asF64, |
| 13693 | mkexpr( src2 ) ) ) ); |
| 13694 | |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 13695 | return IRExpr_ITE( binop( Iop_CmpEQ32, |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 13696 | mkexpr( src1cmpsrc2 ), |
| 13697 | mkU32( isMin ? PPC_CMP_LT : PPC_CMP_GT ) ), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 13698 | /* then: use src1 */ |
| 13699 | mkexpr( src1 ), |
| 13700 | /* else: use src2 */ |
| 13701 | mkexpr( src2 ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13702 | } |
| 13703 | |
| 13704 | /* |
| 13705 | * Helper function for "Maximum/Minimum Double Precision" operations. |
| 13706 | * Arguments: frA and frb are Ity_I64 |
| 13707 | * Returns Ity_I64 IRExpr that answers the "which is Maxiumum/Minimum" question |
| 13708 | */ |
| 13709 | static IRExpr * get_max_min_fp(IRTemp frA_I64, IRTemp frB_I64, Bool isMin) |
| 13710 | { |
| 13711 | /* There are three special cases where get_fp_cmp_CR_val is not helpful |
| 13712 | * for ascertaining the maximum between two doubles: |
| 13713 | * 1. The max/min of +0 and -0 is +0. |
| 13714 | * 2. The max/min of a QNaN and any value is that value. |
| 13715 | * 3. The max/min of any value and an SNaN is that SNaN converted to a QNaN. |
| 13716 | * We perform the check for [+/-]0 here in this function and use the |
| 13717 | * _get_maxmin_fp_NaN helper for the two NaN cases; otherwise we call _get_maxmin_fp_cmp |
| 13718 | * to do the standard comparison function. |
| 13719 | */ |
| 13720 | IRTemp anyNaN = newTemp(Ity_I1); |
| 13721 | IRTemp frA_isZero = newTemp(Ity_I1); |
| 13722 | IRTemp frB_isZero = newTemp(Ity_I1); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13723 | assign(frA_isZero, is_Zero(frA_I64, False /*not single precision*/ )); |
| 13724 | assign(frB_isZero, is_Zero(frB_I64, False /*not single precision*/ )); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13725 | assign(anyNaN, mkOR1(is_NaN(frA_I64), is_NaN(frB_I64))); |
| 13726 | #define MINUS_ZERO 0x8000000000000000ULL |
| 13727 | |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 13728 | return IRExpr_ITE( /* If both arguments are zero . . . */ |
| 13729 | mkAND1( mkexpr( frA_isZero ), mkexpr( frB_isZero ) ), |
| 13730 | /* then: if frA is -0 and isMin==True, return -0; |
| 13731 | * else if frA is +0 and isMin==False; return +0; |
| 13732 | * otherwise, simply return frB. */ |
| 13733 | IRExpr_ITE( binop( Iop_CmpEQ32, |
| 13734 | unop( Iop_64HIto32, |
| 13735 | mkexpr( frA_I64 ) ), |
| 13736 | mkU32( isMin ? 0x80000000 : 0 ) ), |
| 13737 | mkU64( isMin ? MINUS_ZERO : 0ULL ), |
| 13738 | mkexpr( frB_I64 ) ), |
| 13739 | /* else: check if either input is a NaN*/ |
| 13740 | IRExpr_ITE( mkexpr( anyNaN ), |
| 13741 | /* then: use "NaN helper" */ |
| 13742 | _get_maxmin_fp_NaN( frA_I64, frB_I64 ), |
| 13743 | /* else: use "comparison helper" */ |
| 13744 | _get_maxmin_fp_cmp( frB_I64, frA_I64, isMin ) )); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13745 | } |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13746 | |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 13747 | static const HChar * _get_vsx_rdpi_suffix(UInt opc2) |
| 13748 | { |
| 13749 | switch (opc2 & 0x7F) { |
| 13750 | case 0x72: |
| 13751 | return "m"; |
| 13752 | case 0x52: |
| 13753 | return "p"; |
| 13754 | case 0x56: |
| 13755 | return "c"; |
| 13756 | case 0x32: |
| 13757 | return "z"; |
| 13758 | case 0x12: |
| 13759 | return ""; |
| 13760 | |
| 13761 | default: // Impossible to get here |
| 13762 | vex_printf("Unrecognized opcode %x\n", opc2); |
| 13763 | vpanic("_get_vsx_rdpi_suffix(ppc)(opc2)"); |
| 13764 | } |
| 13765 | } |
| 13766 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13767 | /* |
| 13768 | * Helper function for vector/scalar double precision fp round to integer instructions. |
| 13769 | */ |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 13770 | static IRExpr * _do_vsx_fp_roundToInt(IRTemp frB_I64, UInt opc2) |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13771 | { |
| 13772 | |
| 13773 | /* The same rules apply for x{s|v}rdpi{m|p|c|z} as for floating point round operations (fri{m|n|p|z}). */ |
| 13774 | IRTemp frB = newTemp(Ity_F64); |
| 13775 | IRTemp frD = newTemp(Ity_F64); |
| 13776 | IRTemp intermediateResult = newTemp(Ity_I64); |
| 13777 | IRTemp is_SNAN = newTemp(Ity_I1); |
| 13778 | IRExpr * hi32; |
| 13779 | IRExpr * rxpi_rm; |
| 13780 | switch (opc2 & 0x7F) { |
| 13781 | case 0x72: |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13782 | rxpi_rm = mkU32(Irrm_NegINF); |
| 13783 | break; |
| 13784 | case 0x52: |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13785 | rxpi_rm = mkU32(Irrm_PosINF); |
| 13786 | break; |
| 13787 | case 0x56: |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13788 | rxpi_rm = get_IR_roundingmode(); |
| 13789 | break; |
| 13790 | case 0x32: |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13791 | rxpi_rm = mkU32(Irrm_ZERO); |
| 13792 | break; |
| 13793 | case 0x12: |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13794 | rxpi_rm = mkU32(Irrm_NEAREST); |
| 13795 | break; |
| 13796 | |
| 13797 | default: // Impossible to get here |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 13798 | vex_printf("Unrecognized opcode %x\n", opc2); |
| 13799 | vpanic("_do_vsx_fp_roundToInt(ppc)(opc2)"); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13800 | } |
| 13801 | assign(frB, unop(Iop_ReinterpI64asF64, mkexpr(frB_I64))); |
| 13802 | assign( intermediateResult, |
| 13803 | binop( Iop_F64toI64S, rxpi_rm, |
| 13804 | mkexpr( frB ) ) ); |
| 13805 | |
| 13806 | /* don't use the rounded integer if frB is outside -9e18..9e18 */ |
| 13807 | /* F64 has only log10(2**52) significant digits anyway */ |
| 13808 | /* need to preserve sign of zero */ |
| 13809 | /* frD = (fabs(frB) > 9e18) ? frB : |
| 13810 | (sign(frB)) ? -fabs((double)intermediateResult) : (double)intermediateResult */ |
| 13811 | assign( frD, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 13812 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 13813 | binop( Iop_CmpNE8, |
| 13814 | unop( Iop_32to8, |
| 13815 | binop( Iop_CmpF64, |
| 13816 | IRExpr_Const( IRConst_F64( 9e18 ) ), |
| 13817 | unop( Iop_AbsF64, mkexpr( frB ) ) ) ), |
| 13818 | mkU8(0) ), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 13819 | mkexpr( frB ), |
| 13820 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 13821 | binop( Iop_CmpNE32, |
| 13822 | binop( Iop_Shr32, |
| 13823 | unop( Iop_64HIto32, |
| 13824 | mkexpr( frB_I64 ) ), |
| 13825 | mkU8( 31 ) ), |
| 13826 | mkU32(0) ), |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 13827 | unop( Iop_NegF64, |
| 13828 | unop( Iop_AbsF64, |
| 13829 | binop( Iop_I64StoF64, |
| 13830 | mkU32( 0 ), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 13831 | mkexpr( intermediateResult ) ) ) ), |
| 13832 | binop( Iop_I64StoF64, |
| 13833 | mkU32( 0 ), |
| 13834 | mkexpr( intermediateResult ) ) |
| 13835 | ) |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 13836 | ) |
| 13837 | ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13838 | |
| 13839 | /* See Appendix "Floating-Point Round to Integer Model" in ISA doc. |
| 13840 | * If frB is a SNAN, then frD <- frB, with bit 12 set to '1'. |
| 13841 | */ |
| 13842 | #define SNAN_MASK 0x0008000000000000ULL |
| 13843 | hi32 = unop( Iop_64HIto32, mkexpr(frB_I64) ); |
| 13844 | assign( is_SNAN, |
| 13845 | mkAND1( is_NaN( frB_I64 ), |
| 13846 | binop( Iop_CmpEQ32, |
| 13847 | binop( Iop_And32, hi32, mkU32( 0x00080000 ) ), |
| 13848 | mkU32( 0 ) ) ) ); |
| 13849 | |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 13850 | return IRExpr_ITE( mkexpr( is_SNAN ), |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13851 | unop( Iop_ReinterpI64asF64, |
| 13852 | binop( Iop_Xor64, |
| 13853 | mkU64( SNAN_MASK ), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 13854 | mkexpr( frB_I64 ) ) ), |
| 13855 | mkexpr( frD )); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13856 | } |
| 13857 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13858 | /* |
| 13859 | * Miscellaneous VSX vector instructions |
| 13860 | */ |
| 13861 | static Bool |
| 13862 | dis_vxv_misc ( UInt theInstr, UInt opc2 ) |
| 13863 | { |
| 13864 | /* XX3-Form */ |
| 13865 | UChar opc1 = ifieldOPC( theInstr ); |
| 13866 | UChar XT = ifieldRegXT( theInstr ); |
| 13867 | UChar XB = ifieldRegXB( theInstr ); |
| 13868 | |
| 13869 | if (opc1 != 0x3C) { |
| 13870 | vex_printf( "dis_vxv_misc(ppc)(instr)\n" ); |
| 13871 | return False; |
| 13872 | } |
| 13873 | |
| 13874 | switch (opc2) { |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13875 | case 0x1B4: // xvredp (VSX Vector Reciprocal Estimate Double-Precision) |
| 13876 | case 0x194: // xvrsqrtedp (VSX Vector Reciprocal Square Root Estimate |
| 13877 | // Double-Precision) |
| 13878 | { |
| 13879 | IRExpr* ieee_one = IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL)); |
| 13880 | IRExpr* rm = get_IR_roundingmode(); |
| 13881 | IRTemp frB = newTemp(Ity_I64); |
| 13882 | IRTemp frB2 = newTemp(Ity_I64); |
| 13883 | Bool redp = opc2 == 0x1B4; |
| 13884 | IRTemp sqrtHi = newTemp(Ity_F64); |
| 13885 | IRTemp sqrtLo = newTemp(Ity_F64); |
| 13886 | assign(frB, unop(Iop_V128HIto64, getVSReg( XB ))); |
| 13887 | assign(frB2, unop(Iop_V128to64, getVSReg( XB ))); |
| 13888 | |
| 13889 | DIP("%s v%d,v%d\n", redp ? "xvredp" : "xvrsqrtedp", (UInt)XT, (UInt)XB); |
| 13890 | if (!redp) { |
| 13891 | assign( sqrtHi, |
| 13892 | binop( Iop_SqrtF64, |
| 13893 | rm, |
| 13894 | unop( Iop_ReinterpI64asF64, mkexpr( frB ) ) ) ); |
| 13895 | assign( sqrtLo, |
| 13896 | binop( Iop_SqrtF64, |
| 13897 | rm, |
| 13898 | unop( Iop_ReinterpI64asF64, mkexpr( frB2 ) ) ) ); |
| 13899 | } |
| 13900 | putVSReg( XT, |
| 13901 | binop( Iop_64HLtoV128, |
| 13902 | unop( Iop_ReinterpF64asI64, |
| 13903 | triop( Iop_DivF64, |
| 13904 | rm, |
| 13905 | ieee_one, |
| 13906 | redp ? unop( Iop_ReinterpI64asF64, |
| 13907 | mkexpr( frB ) ) |
| 13908 | : mkexpr( sqrtHi ) ) ), |
| 13909 | unop( Iop_ReinterpF64asI64, |
| 13910 | triop( Iop_DivF64, |
| 13911 | rm, |
| 13912 | ieee_one, |
| 13913 | redp ? unop( Iop_ReinterpI64asF64, |
| 13914 | mkexpr( frB2 ) ) |
| 13915 | : mkexpr( sqrtLo ) ) ) ) ); |
| 13916 | break; |
| 13917 | |
| 13918 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13919 | case 0x134: // xvresp (VSX Vector Reciprocal Estimate Single-Precision) |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13920 | case 0x114: // xvrsqrtesp (VSX Vector Reciprocal Square Root Estimate Single-Precision) |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13921 | { |
| 13922 | IRTemp b3, b2, b1, b0; |
| 13923 | IRTemp res0 = newTemp(Ity_I32); |
| 13924 | IRTemp res1 = newTemp(Ity_I32); |
| 13925 | IRTemp res2 = newTemp(Ity_I32); |
| 13926 | IRTemp res3 = newTemp(Ity_I32); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13927 | IRTemp sqrt3 = newTemp(Ity_F64); |
| 13928 | IRTemp sqrt2 = newTemp(Ity_F64); |
| 13929 | IRTemp sqrt1 = newTemp(Ity_F64); |
| 13930 | IRTemp sqrt0 = newTemp(Ity_F64); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13931 | IRExpr* rm = get_IR_roundingmode(); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13932 | Bool resp = opc2 == 0x134; |
| 13933 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13934 | IRExpr* ieee_one = IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL)); |
| 13935 | |
| 13936 | b3 = b2 = b1 = b0 = IRTemp_INVALID; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13937 | DIP("%s v%d,v%d\n", resp ? "xvresp" : "xvrsqrtesp", (UInt)XT, (UInt)XB); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13938 | breakV128to4xF64( getVSReg( XB ), &b3, &b2, &b1, &b0 ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13939 | |
| 13940 | if (!resp) { |
| 13941 | assign( sqrt3, binop( Iop_SqrtF64, rm, mkexpr( b3 ) ) ); |
| 13942 | assign( sqrt2, binop( Iop_SqrtF64, rm, mkexpr( b2 ) ) ); |
| 13943 | assign( sqrt1, binop( Iop_SqrtF64, rm, mkexpr( b1 ) ) ); |
| 13944 | assign( sqrt0, binop( Iop_SqrtF64, rm, mkexpr( b0 ) ) ); |
| 13945 | } |
| 13946 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13947 | assign( res0, |
| 13948 | unop( Iop_ReinterpF32asI32, |
| 13949 | unop( Iop_TruncF64asF32, |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13950 | triop( Iop_DivF64r32, |
| 13951 | rm, |
| 13952 | ieee_one, |
| 13953 | resp ? mkexpr( b0 ) : mkexpr( sqrt0 ) ) ) ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13954 | assign( res1, |
| 13955 | unop( Iop_ReinterpF32asI32, |
| 13956 | unop( Iop_TruncF64asF32, |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13957 | triop( Iop_DivF64r32, |
| 13958 | rm, |
| 13959 | ieee_one, |
| 13960 | resp ? mkexpr( b1 ) : mkexpr( sqrt1 ) ) ) ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13961 | assign( res2, |
| 13962 | unop( Iop_ReinterpF32asI32, |
| 13963 | unop( Iop_TruncF64asF32, |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13964 | triop( Iop_DivF64r32, |
| 13965 | rm, |
| 13966 | ieee_one, |
| 13967 | resp ? mkexpr( b2 ) : mkexpr( sqrt2 ) ) ) ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13968 | assign( res3, |
| 13969 | unop( Iop_ReinterpF32asI32, |
| 13970 | unop( Iop_TruncF64asF32, |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 13971 | triop( Iop_DivF64r32, |
| 13972 | rm, |
| 13973 | ieee_one, |
| 13974 | resp ? mkexpr( b3 ) : mkexpr( sqrt3 ) ) ) ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 13975 | putVSReg( XT, |
| 13976 | binop( Iop_64HLtoV128, |
| 13977 | binop( Iop_32HLto64, mkexpr( res3 ), mkexpr( res2 ) ), |
| 13978 | binop( Iop_32HLto64, mkexpr( res1 ), mkexpr( res0 ) ) ) ); |
| 13979 | break; |
| 13980 | } |
| 13981 | case 0x300: // xvmaxsp (VSX Vector Maximum Single-Precision) |
| 13982 | case 0x320: // xvminsp (VSX Vector Minimum Single-Precision) |
| 13983 | { |
| 13984 | UChar XA = ifieldRegXA( theInstr ); |
| 13985 | IRTemp a3, a2, a1, a0; |
| 13986 | IRTemp b3, b2, b1, b0; |
| 13987 | IRTemp res0 = newTemp( Ity_I32 ); |
| 13988 | IRTemp res1 = newTemp( Ity_I32 ); |
| 13989 | IRTemp res2 = newTemp( Ity_I32 ); |
| 13990 | IRTemp res3 = newTemp( Ity_I32 ); |
| 13991 | IRTemp a0_I64 = newTemp( Ity_I64 ); |
| 13992 | IRTemp a1_I64 = newTemp( Ity_I64 ); |
| 13993 | IRTemp a2_I64 = newTemp( Ity_I64 ); |
| 13994 | IRTemp a3_I64 = newTemp( Ity_I64 ); |
| 13995 | IRTemp b0_I64 = newTemp( Ity_I64 ); |
| 13996 | IRTemp b1_I64 = newTemp( Ity_I64 ); |
| 13997 | IRTemp b2_I64 = newTemp( Ity_I64 ); |
| 13998 | IRTemp b3_I64 = newTemp( Ity_I64 ); |
| 13999 | |
| 14000 | Bool isMin = opc2 == 0x320 ? True : False; |
| 14001 | |
| 14002 | a3 = a2 = a1 = a0 = IRTemp_INVALID; |
| 14003 | b3 = b2 = b1 = b0 = IRTemp_INVALID; |
| 14004 | DIP("%s v%d,v%d v%d\n", isMin ? "xvminsp" : "xvmaxsp", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14005 | breakV128to4xF64( getVSReg( XA ), &a3, &a2, &a1, &a0 ); |
| 14006 | breakV128to4xF64( getVSReg( XB ), &b3, &b2, &b1, &b0 ); |
| 14007 | assign( a0_I64, unop( Iop_ReinterpF64asI64, mkexpr( a0 ) ) ); |
| 14008 | assign( b0_I64, unop( Iop_ReinterpF64asI64, mkexpr( b0 ) ) ); |
| 14009 | assign( a1_I64, unop( Iop_ReinterpF64asI64, mkexpr( a1 ) ) ); |
| 14010 | assign( b1_I64, unop( Iop_ReinterpF64asI64, mkexpr( b1 ) ) ); |
| 14011 | assign( a2_I64, unop( Iop_ReinterpF64asI64, mkexpr( a2 ) ) ); |
| 14012 | assign( b2_I64, unop( Iop_ReinterpF64asI64, mkexpr( b2 ) ) ); |
| 14013 | assign( a3_I64, unop( Iop_ReinterpF64asI64, mkexpr( a3 ) ) ); |
| 14014 | assign( b3_I64, unop( Iop_ReinterpF64asI64, mkexpr( b3 ) ) ); |
| 14015 | assign( res0, |
| 14016 | unop( Iop_ReinterpF32asI32, |
| 14017 | unop( Iop_TruncF64asF32, |
| 14018 | unop( Iop_ReinterpI64asF64, |
| 14019 | get_max_min_fp( a0_I64, b0_I64, isMin ) ) ) ) ); |
| 14020 | assign( res1, |
| 14021 | unop( Iop_ReinterpF32asI32, |
| 14022 | unop( Iop_TruncF64asF32, |
| 14023 | unop( Iop_ReinterpI64asF64, |
| 14024 | get_max_min_fp( a1_I64, b1_I64, isMin ) ) ) ) ); |
| 14025 | assign( res2, |
| 14026 | unop( Iop_ReinterpF32asI32, |
| 14027 | unop( Iop_TruncF64asF32, |
| 14028 | unop( Iop_ReinterpI64asF64, |
| 14029 | get_max_min_fp( a2_I64, b2_I64, isMin ) ) ) ) ); |
| 14030 | assign( res3, |
| 14031 | unop( Iop_ReinterpF32asI32, |
| 14032 | unop( Iop_TruncF64asF32, |
| 14033 | unop( Iop_ReinterpI64asF64, |
| 14034 | get_max_min_fp( a3_I64, b3_I64, isMin ) ) ) ) ); |
| 14035 | putVSReg( XT, |
| 14036 | binop( Iop_64HLtoV128, |
| 14037 | binop( Iop_32HLto64, mkexpr( res3 ), mkexpr( res2 ) ), |
| 14038 | binop( Iop_32HLto64, mkexpr( res1 ), mkexpr( res0 ) ) ) ); |
| 14039 | break; |
| 14040 | } |
| 14041 | case 0x380: // xvmaxdp (VSX Vector Maximum Double-Precision) |
| 14042 | case 0x3A0: // xvmindp (VSX Vector Minimum Double-Precision) |
| 14043 | { |
| 14044 | UChar XA = ifieldRegXA( theInstr ); |
| 14045 | IRTemp frA = newTemp(Ity_I64); |
| 14046 | IRTemp frB = newTemp(Ity_I64); |
| 14047 | IRTemp frA2 = newTemp(Ity_I64); |
| 14048 | IRTemp frB2 = newTemp(Ity_I64); |
| 14049 | Bool isMin = opc2 == 0x3A0 ? True : False; |
| 14050 | |
| 14051 | assign(frA, unop(Iop_V128HIto64, getVSReg( XA ))); |
| 14052 | assign(frB, unop(Iop_V128HIto64, getVSReg( XB ))); |
| 14053 | assign(frA2, unop(Iop_V128to64, getVSReg( XA ))); |
| 14054 | assign(frB2, unop(Iop_V128to64, getVSReg( XB ))); |
| 14055 | DIP("%s v%d,v%d v%d\n", isMin ? "xvmindp" : "xvmaxdp", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14056 | putVSReg( XT, binop( Iop_64HLtoV128, get_max_min_fp(frA, frB, isMin), get_max_min_fp(frA2, frB2, isMin) ) ); |
| 14057 | |
| 14058 | break; |
| 14059 | } |
| 14060 | case 0x3c0: // xvcpsgndp (VSX Vector Copy Sign Double-Precision) |
| 14061 | { |
| 14062 | UChar XA = ifieldRegXA( theInstr ); |
| 14063 | IRTemp frA = newTemp(Ity_I64); |
| 14064 | IRTemp frB = newTemp(Ity_I64); |
| 14065 | IRTemp frA2 = newTemp(Ity_I64); |
| 14066 | IRTemp frB2 = newTemp(Ity_I64); |
| 14067 | assign(frA, unop(Iop_V128HIto64, getVSReg( XA ))); |
| 14068 | assign(frB, unop(Iop_V128HIto64, getVSReg( XB ))); |
| 14069 | assign(frA2, unop(Iop_V128to64, getVSReg( XA ))); |
| 14070 | assign(frB2, unop(Iop_V128to64, getVSReg( XB ))); |
| 14071 | |
| 14072 | DIP("xvcpsgndp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14073 | putVSReg( XT, |
| 14074 | binop( Iop_64HLtoV128, |
| 14075 | binop( Iop_Or64, |
| 14076 | binop( Iop_And64, |
| 14077 | mkexpr( frA ), |
| 14078 | mkU64( SIGN_BIT ) ), |
| 14079 | binop( Iop_And64, |
| 14080 | mkexpr( frB ), |
| 14081 | mkU64( SIGN_MASK ) ) ), |
| 14082 | binop( Iop_Or64, |
| 14083 | binop( Iop_And64, |
| 14084 | mkexpr( frA2 ), |
| 14085 | mkU64( SIGN_BIT ) ), |
| 14086 | binop( Iop_And64, |
| 14087 | mkexpr( frB2 ), |
| 14088 | mkU64( SIGN_MASK ) ) ) ) ); |
| 14089 | break; |
| 14090 | } |
| 14091 | case 0x340: // xvcpsgnsp |
| 14092 | { |
| 14093 | UChar XA = ifieldRegXA( theInstr ); |
| 14094 | IRTemp a3_I64, a2_I64, a1_I64, a0_I64; |
| 14095 | IRTemp b3_I64, b2_I64, b1_I64, b0_I64; |
| 14096 | IRTemp resHi = newTemp(Ity_I64); |
| 14097 | IRTemp resLo = newTemp(Ity_I64); |
| 14098 | |
| 14099 | a3_I64 = a2_I64 = a1_I64 = a0_I64 = IRTemp_INVALID; |
| 14100 | b3_I64 = b2_I64 = b1_I64 = b0_I64 = IRTemp_INVALID; |
| 14101 | DIP("xvcpsgnsp v%d,v%d v%d\n",(UInt)XT, (UInt)XA, (UInt)XB); |
| 14102 | breakV128to4x64U( getVSReg( XA ), &a3_I64, &a2_I64, &a1_I64, &a0_I64 ); |
| 14103 | breakV128to4x64U( getVSReg( XB ), &b3_I64, &b2_I64, &b1_I64, &b0_I64 ); |
| 14104 | |
| 14105 | assign( resHi, |
| 14106 | binop( Iop_32HLto64, |
| 14107 | binop( Iop_Or32, |
| 14108 | binop( Iop_And32, |
| 14109 | unop(Iop_64to32, mkexpr( a3_I64 ) ), |
| 14110 | mkU32( SIGN_BIT32 ) ), |
| 14111 | binop( Iop_And32, |
| 14112 | unop(Iop_64to32, mkexpr( b3_I64 ) ), |
| 14113 | mkU32( SIGN_MASK32) ) ), |
| 14114 | |
| 14115 | binop( Iop_Or32, |
| 14116 | binop( Iop_And32, |
| 14117 | unop(Iop_64to32, mkexpr( a2_I64 ) ), |
| 14118 | mkU32( SIGN_BIT32 ) ), |
| 14119 | binop( Iop_And32, |
| 14120 | unop(Iop_64to32, mkexpr( b2_I64 ) ), |
| 14121 | mkU32( SIGN_MASK32 ) ) ) ) ); |
| 14122 | assign( resLo, |
| 14123 | binop( Iop_32HLto64, |
| 14124 | binop( Iop_Or32, |
| 14125 | binop( Iop_And32, |
| 14126 | unop(Iop_64to32, mkexpr( a1_I64 ) ), |
| 14127 | mkU32( SIGN_BIT32 ) ), |
| 14128 | binop( Iop_And32, |
| 14129 | unop(Iop_64to32, mkexpr( b1_I64 ) ), |
| 14130 | mkU32( SIGN_MASK32 ) ) ), |
| 14131 | |
| 14132 | binop( Iop_Or32, |
| 14133 | binop( Iop_And32, |
| 14134 | unop(Iop_64to32, mkexpr( a0_I64 ) ), |
| 14135 | mkU32( SIGN_BIT32 ) ), |
| 14136 | binop( Iop_And32, |
| 14137 | unop(Iop_64to32, mkexpr( b0_I64 ) ), |
| 14138 | mkU32( SIGN_MASK32 ) ) ) ) ); |
| 14139 | putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( resHi ), mkexpr( resLo ) ) ); |
| 14140 | break; |
| 14141 | } |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14142 | case 0x3B2: // xvabsdp (VSX Vector Absolute Value Double-Precision) |
| 14143 | case 0x3D2: // xvnabsdp VSX Vector Negative Absolute Value Double-Precision) |
| 14144 | { |
| 14145 | IRTemp frB = newTemp(Ity_F64); |
| 14146 | IRTemp frB2 = newTemp(Ity_F64); |
| 14147 | IRTemp abs_resultHi = newTemp(Ity_F64); |
| 14148 | IRTemp abs_resultLo = newTemp(Ity_F64); |
| 14149 | Bool make_negative = (opc2 == 0x3D2) ? True : False; |
| 14150 | assign(frB, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XB )))); |
| 14151 | assign(frB2, unop(Iop_ReinterpI64asF64, unop(Iop_V128to64, getVSReg(XB)))); |
| 14152 | |
| 14153 | DIP("xv%sabsdp v%d,v%d\n", make_negative ? "n" : "", (UInt)XT, (UInt)XB); |
| 14154 | if (make_negative) { |
| 14155 | assign(abs_resultHi, unop( Iop_NegF64, unop( Iop_AbsF64, mkexpr( frB ) ) ) ); |
| 14156 | assign(abs_resultLo, unop( Iop_NegF64, unop( Iop_AbsF64, mkexpr( frB2 ) ) ) ); |
| 14157 | |
| 14158 | } else { |
| 14159 | assign(abs_resultHi, unop( Iop_AbsF64, mkexpr( frB ) ) ); |
| 14160 | assign(abs_resultLo, unop( Iop_AbsF64, mkexpr( frB2 ) ) ); |
| 14161 | } |
| 14162 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 14163 | unop( Iop_ReinterpF64asI64, mkexpr( abs_resultHi ) ), |
| 14164 | unop( Iop_ReinterpF64asI64, mkexpr( abs_resultLo ) ) ) ); |
| 14165 | break; |
| 14166 | } |
| 14167 | case 0x332: // xvabssp (VSX Vector Absolute Value Single-Precision) |
| 14168 | case 0x352: // xvnabssp (VSX Vector Negative Absolute Value Single-Precision) |
| 14169 | { |
| 14170 | /* |
| 14171 | * The Iop_AbsF32 IRop is not implemented for ppc64 since, up until introduction |
| 14172 | * of xvabssp, there has not been an abs(sp) type of instruction. But since emulation |
| 14173 | * of this function is so easy using shifts, I choose to emulate this instruction that |
| 14174 | * way versus a native instruction method of implementation. |
| 14175 | */ |
| 14176 | Bool make_negative = (opc2 == 0x352) ? True : False; |
| 14177 | IRTemp shiftVector = newTemp(Ity_V128); |
| 14178 | IRTemp absVal_vector = newTemp(Ity_V128); |
| 14179 | assign( shiftVector, |
| 14180 | binop( Iop_64HLtoV128, |
| 14181 | binop( Iop_32HLto64, mkU32( 1 ), mkU32( 1 ) ), |
| 14182 | binop( Iop_32HLto64, mkU32( 1 ), mkU32( 1 ) ) ) ); |
| 14183 | assign( absVal_vector, |
| 14184 | binop( Iop_Shr32x4, |
| 14185 | binop( Iop_Shl32x4, |
| 14186 | getVSReg( XB ), |
| 14187 | mkexpr( shiftVector ) ), |
| 14188 | mkexpr( shiftVector ) ) ); |
| 14189 | if (make_negative) { |
| 14190 | IRTemp signBit_vector = newTemp(Ity_V128); |
| 14191 | assign( signBit_vector, |
| 14192 | binop( Iop_64HLtoV128, |
| 14193 | binop( Iop_32HLto64, |
| 14194 | mkU32( 0x80000000 ), |
| 14195 | mkU32( 0x80000000 ) ), |
| 14196 | binop( Iop_32HLto64, |
| 14197 | mkU32( 0x80000000 ), |
| 14198 | mkU32( 0x80000000 ) ) ) ); |
| 14199 | putVSReg( XT, |
| 14200 | binop( Iop_OrV128, |
| 14201 | mkexpr( absVal_vector ), |
| 14202 | mkexpr( signBit_vector ) ) ); |
| 14203 | } else { |
| 14204 | putVSReg( XT, mkexpr( absVal_vector ) ); |
| 14205 | } |
| 14206 | break; |
| 14207 | } |
| 14208 | case 0x3F2: // xvnegdp (VSX Vector Negate Double-Precision) |
| 14209 | { |
| 14210 | IRTemp frB = newTemp(Ity_F64); |
| 14211 | IRTemp frB2 = newTemp(Ity_F64); |
| 14212 | assign(frB, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XB )))); |
| 14213 | assign(frB2, unop(Iop_ReinterpI64asF64, unop(Iop_V128to64, getVSReg(XB)))); |
| 14214 | DIP("xvnegdp v%d,v%d\n", (UInt)XT, (UInt)XB); |
| 14215 | putVSReg( XT, |
| 14216 | binop( Iop_64HLtoV128, |
| 14217 | unop( Iop_ReinterpF64asI64, |
| 14218 | unop( Iop_NegF64, mkexpr( frB ) ) ), |
| 14219 | unop( Iop_ReinterpF64asI64, |
| 14220 | unop( Iop_NegF64, mkexpr( frB2 ) ) ) ) ); |
| 14221 | break; |
| 14222 | } |
| 14223 | case 0x192: // xvrdpi (VSX Vector Round to Double-Precision Integer using round toward Nearest Away) |
| 14224 | case 0x1D6: // xvrdpic (VSX Vector Round to Double-Precision Integer using Current rounding mode) |
| 14225 | case 0x1F2: // xvrdpim (VSX Vector Round to Double-Precision Integer using round toward -Infinity) |
| 14226 | case 0x1D2: // xvrdpip (VSX Vector Round to Double-Precision Integer using round toward +Infinity) |
| 14227 | case 0x1B2: // xvrdpiz (VSX Vector Round to Double-Precision Integer using round toward Zero) |
| 14228 | { |
| 14229 | IRTemp frBHi_I64 = newTemp(Ity_I64); |
| 14230 | IRTemp frBLo_I64 = newTemp(Ity_I64); |
| 14231 | IRExpr * frD_fp_roundHi = NULL; |
| 14232 | IRExpr * frD_fp_roundLo = NULL; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14233 | |
| 14234 | assign( frBHi_I64, unop( Iop_V128HIto64, getVSReg( XB ) ) ); |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 14235 | frD_fp_roundHi = _do_vsx_fp_roundToInt(frBHi_I64, opc2); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14236 | assign( frBLo_I64, unop( Iop_V128to64, getVSReg( XB ) ) ); |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 14237 | frD_fp_roundLo = _do_vsx_fp_roundToInt(frBLo_I64, opc2); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14238 | |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 14239 | DIP("xvrdpi%s v%d,v%d\n", _get_vsx_rdpi_suffix(opc2), (UInt)XT, (UInt)XB); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14240 | putVSReg( XT, |
| 14241 | binop( Iop_64HLtoV128, |
| 14242 | unop( Iop_ReinterpF64asI64, frD_fp_roundHi ), |
| 14243 | unop( Iop_ReinterpF64asI64, frD_fp_roundLo ) ) ); |
| 14244 | break; |
| 14245 | } |
| 14246 | case 0x112: // xvrspi (VSX Vector Round to Single-Precision Integer using round toward Nearest Away) |
| 14247 | case 0x156: // xvrspic (VSX Vector Round to SinglePrecision Integer using Current rounding mode) |
| 14248 | case 0x172: // xvrspim (VSX Vector Round to SinglePrecision Integer using round toward -Infinity) |
| 14249 | case 0x152: // xvrspip (VSX Vector Round to SinglePrecision Integer using round toward +Infinity) |
| 14250 | case 0x132: // xvrspiz (VSX Vector Round to SinglePrecision Integer using round toward Zero) |
| 14251 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 14252 | const HChar * insn_suffix = NULL; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14253 | IROp op; |
| 14254 | if (opc2 != 0x156) { |
| 14255 | // Use pre-defined IRop's for vrfi{m|n|p|z} |
| 14256 | switch (opc2) { |
| 14257 | case 0x112: |
| 14258 | insn_suffix = ""; |
| 14259 | op = Iop_RoundF32x4_RN; |
| 14260 | break; |
| 14261 | case 0x172: |
| 14262 | insn_suffix = "m"; |
| 14263 | op = Iop_RoundF32x4_RM; |
| 14264 | break; |
| 14265 | case 0x152: |
| 14266 | insn_suffix = "p"; |
| 14267 | op = Iop_RoundF32x4_RP; |
| 14268 | break; |
| 14269 | case 0x132: |
| 14270 | insn_suffix = "z"; |
| 14271 | op = Iop_RoundF32x4_RZ; |
| 14272 | break; |
| 14273 | |
| 14274 | default: |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 14275 | vex_printf("Unrecognized opcode %x\n", opc2); |
| 14276 | vpanic("dis_vxv_misc(ppc)(vrspi<x>)(opc2)\n"); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14277 | } |
| 14278 | DIP("xvrspi%s v%d,v%d\n", insn_suffix, (UInt)XT, (UInt)XB); |
| 14279 | putVSReg( XT, unop( op, getVSReg(XB) ) ); |
| 14280 | } else { |
| 14281 | // Handle xvrspic. Unfortunately there is no corresponding "vfric" instruction. |
| 14282 | IRExpr * frD_fp_roundb3, * frD_fp_roundb2, * frD_fp_roundb1, * frD_fp_roundb0; |
| 14283 | IRTemp b3_F64, b2_F64, b1_F64, b0_F64; |
| 14284 | IRTemp b3_I64 = newTemp(Ity_I64); |
| 14285 | IRTemp b2_I64 = newTemp(Ity_I64); |
| 14286 | IRTemp b1_I64 = newTemp(Ity_I64); |
| 14287 | IRTemp b0_I64 = newTemp(Ity_I64); |
| 14288 | |
| 14289 | b3_F64 = b2_F64 = b1_F64 = b0_F64 = IRTemp_INVALID; |
| 14290 | frD_fp_roundb3 = frD_fp_roundb2 = frD_fp_roundb1 = frD_fp_roundb0 = NULL; |
| 14291 | breakV128to4xF64( getVSReg(XB), &b3_F64, &b2_F64, &b1_F64, &b0_F64); |
| 14292 | assign(b3_I64, unop(Iop_ReinterpF64asI64, mkexpr(b3_F64))); |
| 14293 | assign(b2_I64, unop(Iop_ReinterpF64asI64, mkexpr(b2_F64))); |
| 14294 | assign(b1_I64, unop(Iop_ReinterpF64asI64, mkexpr(b1_F64))); |
| 14295 | assign(b0_I64, unop(Iop_ReinterpF64asI64, mkexpr(b0_F64))); |
| 14296 | frD_fp_roundb3 = unop(Iop_TruncF64asF32, |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 14297 | _do_vsx_fp_roundToInt(b3_I64, opc2)); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14298 | frD_fp_roundb2 = unop(Iop_TruncF64asF32, |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 14299 | _do_vsx_fp_roundToInt(b2_I64, opc2)); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14300 | frD_fp_roundb1 = unop(Iop_TruncF64asF32, |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 14301 | _do_vsx_fp_roundToInt(b1_I64, opc2)); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14302 | frD_fp_roundb0 = unop(Iop_TruncF64asF32, |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 14303 | _do_vsx_fp_roundToInt(b0_I64, opc2)); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14304 | DIP("xvrspic v%d,v%d\n", (UInt)XT, (UInt)XB); |
| 14305 | putVSReg( XT, |
| 14306 | binop( Iop_64HLtoV128, |
| 14307 | binop( Iop_32HLto64, |
| 14308 | unop( Iop_ReinterpF32asI32, frD_fp_roundb3 ), |
| 14309 | unop( Iop_ReinterpF32asI32, frD_fp_roundb2 ) ), |
| 14310 | binop( Iop_32HLto64, |
| 14311 | unop( Iop_ReinterpF32asI32, frD_fp_roundb1 ), |
| 14312 | unop( Iop_ReinterpF32asI32, frD_fp_roundb0 ) ) ) ); |
| 14313 | } |
| 14314 | break; |
| 14315 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14316 | |
| 14317 | default: |
| 14318 | vex_printf( "dis_vxv_misc(ppc)(opc2)\n" ); |
| 14319 | return False; |
| 14320 | } |
| 14321 | return True; |
| 14322 | } |
| 14323 | |
| 14324 | |
| 14325 | /* |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14326 | * VSX Scalar Floating Point Arithmetic Instructions |
| 14327 | */ |
| 14328 | static Bool |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14329 | dis_vxs_arith ( UInt theInstr, UInt opc2 ) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14330 | { |
| 14331 | /* XX3-Form */ |
| 14332 | UChar opc1 = ifieldOPC( theInstr ); |
| 14333 | UChar XT = ifieldRegXT( theInstr ); |
| 14334 | UChar XA = ifieldRegXA( theInstr ); |
| 14335 | UChar XB = ifieldRegXB( theInstr ); |
| 14336 | IRExpr* rm = get_IR_roundingmode(); |
| 14337 | IRTemp frA = newTemp(Ity_F64); |
| 14338 | IRTemp frB = newTemp(Ity_F64); |
| 14339 | |
| 14340 | if (opc1 != 0x3C) { |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14341 | vex_printf( "dis_vxs_arith(ppc)(instr)\n" ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14342 | return False; |
| 14343 | } |
| 14344 | |
| 14345 | assign(frA, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XA )))); |
| 14346 | assign(frB, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XB )))); |
| 14347 | |
| 14348 | /* For all the VSX sclar arithmetic instructions, the contents of doubleword element 1 |
| 14349 | * of VSX[XT] are undefined after the operation; therefore, we can simply set |
| 14350 | * element to zero where it makes sense to do so. |
| 14351 | */ |
| 14352 | switch (opc2) { |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 14353 | case 0x000: // xsaddsp (VSX Scalar Add Single-Precision) |
| 14354 | DIP("xsaddsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14355 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 14356 | unop( Iop_ReinterpF64asI64, |
| 14357 | binop( Iop_RoundF64toF32, rm, |
| 14358 | triop( Iop_AddF64, rm, |
| 14359 | mkexpr( frA ), |
| 14360 | mkexpr( frB ) ) ) ), |
| 14361 | mkU64( 0 ) ) ); |
| 14362 | break; |
| 14363 | case 0x020: // xssubsp (VSX Scalar Subtract Single-Precision) |
| 14364 | DIP("xssubsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14365 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 14366 | unop( Iop_ReinterpF64asI64, |
| 14367 | binop( Iop_RoundF64toF32, rm, |
| 14368 | triop( Iop_SubF64, rm, |
| 14369 | mkexpr( frA ), |
| 14370 | mkexpr( frB ) ) ) ), |
| 14371 | mkU64( 0 ) ) ); |
| 14372 | break; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14373 | case 0x080: // xsadddp (VSX scalar add double-precision) |
| 14374 | DIP("xsadddp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14375 | putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64, |
| 14376 | triop( Iop_AddF64, rm, |
| 14377 | mkexpr( frA ), |
| 14378 | mkexpr( frB ) ) ), |
| 14379 | mkU64( 0 ) ) ); |
| 14380 | break; |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 14381 | case 0x060: // xsdivsp (VSX scalar divide single-precision) |
| 14382 | DIP("xsdivsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14383 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 14384 | unop( Iop_ReinterpF64asI64, |
| 14385 | binop( Iop_RoundF64toF32, rm, |
| 14386 | triop( Iop_DivF64, rm, |
| 14387 | mkexpr( frA ), |
| 14388 | mkexpr( frB ) ) ) ), |
| 14389 | mkU64( 0 ) ) ); |
| 14390 | break; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14391 | case 0x0E0: // xsdivdp (VSX scalar divide double-precision) |
| 14392 | DIP("xsdivdp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14393 | putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64, |
| 14394 | triop( Iop_DivF64, rm, |
| 14395 | mkexpr( frA ), |
| 14396 | mkexpr( frB ) ) ), |
| 14397 | mkU64( 0 ) ) ); |
| 14398 | break; |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 14399 | case 0x004: case 0x024: /* xsmaddasp, xsmaddmsp (VSX scalar multiply-add |
| 14400 | * single-precision) |
| 14401 | */ |
| 14402 | { |
| 14403 | IRTemp frT = newTemp(Ity_F64); |
| 14404 | Bool mdp = opc2 == 0x024; |
| 14405 | DIP("xsmadd%ssp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14406 | assign( frT, unop( Iop_ReinterpI64asF64, unop( Iop_V128HIto64, |
| 14407 | getVSReg( XT ) ) ) ); |
| 14408 | putVSReg( XT, |
| 14409 | binop( Iop_64HLtoV128, |
| 14410 | unop( Iop_ReinterpF64asI64, |
| 14411 | binop( Iop_RoundF64toF32, rm, |
| 14412 | qop( Iop_MAddF64, rm, |
| 14413 | mkexpr( frA ), |
| 14414 | mkexpr( mdp ? frT : frB ), |
| 14415 | mkexpr( mdp ? frB : frT ) ) ) ), |
| 14416 | mkU64( 0 ) ) ); |
| 14417 | break; |
| 14418 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14419 | case 0x084: case 0x0A4: // xsmaddadp, xsmaddmdp (VSX scalar multiply-add double-precision) |
| 14420 | { |
| 14421 | IRTemp frT = newTemp(Ity_F64); |
| 14422 | Bool mdp = opc2 == 0x0A4; |
| 14423 | DIP("xsmadd%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14424 | assign( frT, unop( Iop_ReinterpI64asF64, unop( Iop_V128HIto64, |
| 14425 | getVSReg( XT ) ) ) ); |
| 14426 | putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64, |
| 14427 | qop( Iop_MAddF64, rm, |
| 14428 | mkexpr( frA ), |
| 14429 | mkexpr( mdp ? frT : frB ), |
| 14430 | mkexpr( mdp ? frB : frT ) ) ), |
| 14431 | mkU64( 0 ) ) ); |
| 14432 | break; |
| 14433 | } |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 14434 | case 0x044: case 0x064: /* xsmsubasp, xsmsubmsp (VSX scalar |
| 14435 | * multiply-subtract single-precision) |
| 14436 | */ |
| 14437 | { |
| 14438 | IRTemp frT = newTemp(Ity_F64); |
| 14439 | Bool mdp = opc2 == 0x064; |
| 14440 | DIP("xsmsub%ssp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14441 | assign( frT, unop( Iop_ReinterpI64asF64, unop( Iop_V128HIto64, |
| 14442 | getVSReg( XT ) ) ) ); |
| 14443 | putVSReg( XT, |
| 14444 | binop( Iop_64HLtoV128, |
| 14445 | unop( Iop_ReinterpF64asI64, |
| 14446 | binop( Iop_RoundF64toF32, rm, |
| 14447 | qop( Iop_MSubF64, rm, |
| 14448 | mkexpr( frA ), |
| 14449 | mkexpr( mdp ? frT : frB ), |
| 14450 | mkexpr( mdp ? frB : frT ) ) ) ), |
| 14451 | mkU64( 0 ) ) ); |
| 14452 | break; |
| 14453 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14454 | case 0x0C4: case 0x0E4: // xsmsubadp, xsmsubmdp (VSX scalar multiply-subtract double-precision) |
| 14455 | { |
| 14456 | IRTemp frT = newTemp(Ity_F64); |
| 14457 | Bool mdp = opc2 == 0x0E4; |
| 14458 | DIP("xsmsub%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14459 | assign( frT, unop( Iop_ReinterpI64asF64, unop( Iop_V128HIto64, |
| 14460 | getVSReg( XT ) ) ) ); |
| 14461 | putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64, |
| 14462 | qop( Iop_MSubF64, rm, |
| 14463 | mkexpr( frA ), |
| 14464 | mkexpr( mdp ? frT : frB ), |
| 14465 | mkexpr( mdp ? frB : frT ) ) ), |
| 14466 | mkU64( 0 ) ) ); |
| 14467 | break; |
| 14468 | } |
| 14469 | case 0x284: case 0x2A4: // xsnmaddadp, xsnmaddmdp (VSX scalar multiply-add double-precision) |
| 14470 | { |
| 14471 | /* TODO: mpj -- Naturally, I expected to be able to leverage the implementation |
| 14472 | * of fnmadd and use pretty much the same code. However, that code has a bug in the |
| 14473 | * way it blindly negates the signbit, even if the floating point result is a NaN. |
| 14474 | * So, the TODO is to fix fnmadd (which I'll do in a different patch). |
sewardj | 2bcdd65 | 2012-07-14 08:22:13 +0000 | [diff] [blame] | 14475 | * FIXED 7/1/2012: carll fnmadd and fnmsubs fixed to not negate sign |
| 14476 | * bit for NaN result. |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14477 | */ |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14478 | Bool mdp = opc2 == 0x2A4; |
| 14479 | IRTemp frT = newTemp(Ity_F64); |
| 14480 | IRTemp maddResult = newTemp(Ity_I64); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14481 | |
| 14482 | DIP("xsnmadd%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14483 | assign( frT, unop( Iop_ReinterpI64asF64, unop( Iop_V128HIto64, |
| 14484 | getVSReg( XT ) ) ) ); |
| 14485 | assign( maddResult, unop( Iop_ReinterpF64asI64, qop( Iop_MAddF64, rm, |
| 14486 | mkexpr( frA ), |
| 14487 | mkexpr( mdp ? frT : frB ), |
| 14488 | mkexpr( mdp ? frB : frT ) ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14489 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14490 | putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( getNegatedResult(maddResult) ), |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14491 | mkU64( 0 ) ) ); |
| 14492 | break; |
| 14493 | } |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 14494 | case 0x204: case 0x224: /* xsnmaddasp, xsnmaddmsp (VSX scalar |
| 14495 | * multiply-add single-precision) |
| 14496 | */ |
| 14497 | { |
| 14498 | Bool mdp = opc2 == 0x224; |
| 14499 | IRTemp frT = newTemp(Ity_F64); |
| 14500 | IRTemp maddResult = newTemp(Ity_I64); |
| 14501 | |
| 14502 | DIP("xsnmadd%ssp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14503 | assign( frT, unop( Iop_ReinterpI64asF64, unop( Iop_V128HIto64, |
| 14504 | getVSReg( XT ) ) ) ); |
| 14505 | assign( maddResult, |
| 14506 | unop( Iop_ReinterpF64asI64, |
| 14507 | binop( Iop_RoundF64toF32, rm, |
| 14508 | qop( Iop_MAddF64, rm, |
| 14509 | mkexpr( frA ), |
| 14510 | mkexpr( mdp ? frT : frB ), |
| 14511 | mkexpr( mdp ? frB : frT ) ) ) ) ); |
| 14512 | |
| 14513 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 14514 | mkexpr( getNegatedResult(maddResult) ), |
| 14515 | mkU64( 0 ) ) ); |
| 14516 | break; |
| 14517 | } |
| 14518 | case 0x244: case 0x264: /* xsnmsubasp, xsnmsubmsp (VSX Scalar Negative |
| 14519 | * Multiply-Subtract Single-Precision) |
| 14520 | */ |
| 14521 | { |
| 14522 | IRTemp frT = newTemp(Ity_F64); |
| 14523 | Bool mdp = opc2 == 0x264; |
| 14524 | IRTemp msubResult = newTemp(Ity_I64); |
| 14525 | |
| 14526 | DIP("xsnmsub%ssp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14527 | assign( frT, unop( Iop_ReinterpI64asF64, unop( Iop_V128HIto64, |
| 14528 | getVSReg( XT ) ) ) ); |
| 14529 | assign( msubResult, |
| 14530 | unop( Iop_ReinterpF64asI64, |
| 14531 | binop( Iop_RoundF64toF32, rm, |
| 14532 | qop( Iop_MSubF64, rm, |
| 14533 | mkexpr( frA ), |
| 14534 | mkexpr( mdp ? frT : frB ), |
| 14535 | mkexpr( mdp ? frB : frT ) ) ) ) ); |
| 14536 | |
| 14537 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 14538 | mkexpr( getNegatedResult(msubResult) ), |
| 14539 | mkU64( 0 ) ) ); |
| 14540 | |
| 14541 | break; |
| 14542 | } |
| 14543 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14544 | case 0x2C4: case 0x2E4: // xsnmsubadp, xsnmsubmdp (VSX Scalar Negative Multiply-Subtract Double-Precision) |
| 14545 | { |
| 14546 | IRTemp frT = newTemp(Ity_F64); |
| 14547 | Bool mdp = opc2 == 0x2E4; |
| 14548 | IRTemp msubResult = newTemp(Ity_I64); |
| 14549 | |
| 14550 | DIP("xsnmsub%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14551 | assign( frT, unop( Iop_ReinterpI64asF64, unop( Iop_V128HIto64, |
| 14552 | getVSReg( XT ) ) ) ); |
| 14553 | assign(msubResult, unop( Iop_ReinterpF64asI64, |
| 14554 | qop( Iop_MSubF64, |
| 14555 | rm, |
| 14556 | mkexpr( frA ), |
| 14557 | mkexpr( mdp ? frT : frB ), |
| 14558 | mkexpr( mdp ? frB : frT ) ) )); |
| 14559 | |
| 14560 | putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( getNegatedResult(msubResult) ), mkU64( 0 ) ) ); |
| 14561 | |
| 14562 | break; |
| 14563 | } |
| 14564 | |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 14565 | case 0x040: // xsmulsp (VSX Scalar Multiply Single-Precision) |
| 14566 | DIP("xsmulsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14567 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 14568 | unop( Iop_ReinterpF64asI64, |
| 14569 | binop( Iop_RoundF64toF32, rm, |
| 14570 | triop( Iop_MulF64, rm, |
| 14571 | mkexpr( frA ), |
| 14572 | mkexpr( frB ) ) ) ), |
| 14573 | mkU64( 0 ) ) ); |
| 14574 | break; |
| 14575 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14576 | case 0x0C0: // xsmuldp (VSX Scalar Multiply Double-Precision) |
| 14577 | DIP("xsmuldp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14578 | putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64, |
| 14579 | triop( Iop_MulF64, rm, |
| 14580 | mkexpr( frA ), |
| 14581 | mkexpr( frB ) ) ), |
| 14582 | mkU64( 0 ) ) ); |
| 14583 | break; |
| 14584 | case 0x0A0: // xssubdp (VSX Scalar Subtract Double-Precision) |
| 14585 | DIP("xssubdp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 14586 | putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64, |
| 14587 | triop( Iop_SubF64, rm, |
| 14588 | mkexpr( frA ), |
| 14589 | mkexpr( frB ) ) ), |
| 14590 | mkU64( 0 ) ) ); |
| 14591 | break; |
| 14592 | |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 14593 | case 0x016: // xssqrtsp (VSX Scalar Square Root Single-Precision) |
| 14594 | DIP("xssqrtsp v%d,v%d\n", (UInt)XT, (UInt)XB); |
| 14595 | putVSReg( XT, |
| 14596 | binop( Iop_64HLtoV128, |
| 14597 | unop( Iop_ReinterpF64asI64, |
| 14598 | binop( Iop_RoundF64toF32, rm, |
| 14599 | binop( Iop_SqrtF64, rm, |
| 14600 | mkexpr( frB ) ) ) ), |
| 14601 | mkU64( 0 ) ) ); |
| 14602 | break; |
| 14603 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14604 | case 0x096: // xssqrtdp (VSX Scalar Square Root Double-Precision) |
| 14605 | DIP("xssqrtdp v%d,v%d\n", (UInt)XT, (UInt)XB); |
| 14606 | putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64, |
| 14607 | binop( Iop_SqrtF64, rm, |
| 14608 | mkexpr( frB ) ) ), |
| 14609 | mkU64( 0 ) ) ); |
| 14610 | break; |
| 14611 | |
| 14612 | case 0x0F4: // xstdivdp (VSX Scalar Test for software Divide Double-Precision) |
| 14613 | { |
| 14614 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 14615 | IRTemp frA_I64 = newTemp(Ity_I64); |
| 14616 | IRTemp frB_I64 = newTemp(Ity_I64); |
| 14617 | DIP("xstdivdp crf%d,v%d,v%d\n", crfD, (UInt)XA, (UInt)XB); |
| 14618 | assign( frA_I64, unop( Iop_ReinterpF64asI64, mkexpr( frA ) ) ); |
| 14619 | assign( frB_I64, unop( Iop_ReinterpF64asI64, mkexpr( frB ) ) ); |
| 14620 | putGST_field( PPC_GST_CR, do_fp_tdiv(frA_I64, frB_I64), crfD ); |
| 14621 | break; |
| 14622 | } |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 14623 | case 0x0D4: // xstsqrtdp (VSX Vector Test for software Square Root Double-Precision) |
| 14624 | { |
| 14625 | IRTemp frB_I64 = newTemp(Ity_I64); |
| 14626 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 14627 | IRTemp flags = newTemp(Ity_I32); |
| 14628 | IRTemp fe_flag, fg_flag; |
| 14629 | fe_flag = fg_flag = IRTemp_INVALID; |
| 14630 | DIP("xstsqrtdp v%d,v%d\n", (UInt)XT, (UInt)XB); |
| 14631 | assign( frB_I64, unop(Iop_V128HIto64, getVSReg( XB )) ); |
| 14632 | do_fp_tsqrt(frB_I64, False /*not single precision*/, &fe_flag, &fg_flag); |
| 14633 | /* The CR field consists of fl_flag || fg_flag || fe_flag || 0b0 |
| 14634 | * where fl_flag == 1 on ppc64. |
| 14635 | */ |
| 14636 | assign( flags, |
| 14637 | binop( Iop_Or32, |
| 14638 | binop( Iop_Or32, mkU32( 8 ), // fl_flag |
| 14639 | binop( Iop_Shl32, mkexpr(fg_flag), mkU8( 2 ) ) ), |
| 14640 | binop( Iop_Shl32, mkexpr(fe_flag), mkU8( 1 ) ) ) ); |
| 14641 | putGST_field( PPC_GST_CR, mkexpr(flags), crfD ); |
| 14642 | break; |
| 14643 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14644 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14645 | default: |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14646 | vex_printf( "dis_vxs_arith(ppc)(opc2)\n" ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14647 | return False; |
| 14648 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14649 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14650 | return True; |
| 14651 | } |
| 14652 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14653 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14654 | /* |
| 14655 | * VSX Floating Point Compare Instructions |
| 14656 | */ |
| 14657 | static Bool |
| 14658 | dis_vx_cmp( UInt theInstr, UInt opc2 ) |
| 14659 | { |
| 14660 | /* XX3-Form and XX2-Form */ |
| 14661 | UChar opc1 = ifieldOPC( theInstr ); |
| 14662 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14663 | IRTemp ccPPC32; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14664 | UChar XA = ifieldRegXA ( theInstr ); |
| 14665 | UChar XB = ifieldRegXB ( theInstr ); |
| 14666 | IRTemp frA = newTemp(Ity_F64); |
| 14667 | IRTemp frB = newTemp(Ity_F64); |
| 14668 | |
| 14669 | if (opc1 != 0x3C) { |
| 14670 | vex_printf( "dis_vx_cmp(ppc)(instr)\n" ); |
| 14671 | return False; |
| 14672 | } |
| 14673 | |
| 14674 | assign(frA, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XA )))); |
| 14675 | assign(frB, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XB )))); |
| 14676 | switch (opc2) { |
| 14677 | case 0x08C: case 0x0AC: // xscmpudp, xscmpodp |
| 14678 | /* Note: Differences between xscmpudp and xscmpodp are only in |
| 14679 | * exception flag settings, which aren't supported anyway. */ |
| 14680 | DIP("xscmp%sdp crf%d,fr%u,fr%u\n", opc2 == 0x08c ? "u" : "o", |
| 14681 | crfD, (UInt)XA, (UInt)XB); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14682 | ccPPC32 = get_fp_cmp_CR_val( binop(Iop_CmpF64, mkexpr(frA), mkexpr(frB))); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14683 | putGST_field( PPC_GST_CR, mkexpr(ccPPC32), crfD ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14684 | break; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14685 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14686 | default: |
| 14687 | vex_printf( "dis_vx_cmp(ppc)(opc2)\n" ); |
| 14688 | return False; |
| 14689 | } |
| 14690 | return True; |
| 14691 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14692 | |
| 14693 | static void |
| 14694 | do_vvec_fp_cmp ( IRTemp vA, IRTemp vB, UChar XT, UChar flag_rC, |
| 14695 | ppc_cmp_t cmp_type ) |
| 14696 | { |
| 14697 | IRTemp frA_hi = newTemp(Ity_F64); |
| 14698 | IRTemp frB_hi = newTemp(Ity_F64); |
| 14699 | IRTemp frA_lo = newTemp(Ity_F64); |
| 14700 | IRTemp frB_lo = newTemp(Ity_F64); |
| 14701 | IRTemp ccPPC32 = newTemp(Ity_I32); |
| 14702 | IRTemp ccIR_hi; |
| 14703 | IRTemp ccIR_lo; |
| 14704 | |
| 14705 | IRTemp hiResult = newTemp(Ity_I64); |
| 14706 | IRTemp loResult = newTemp(Ity_I64); |
| 14707 | IRTemp hiEQlo = newTemp(Ity_I1); |
| 14708 | IRTemp all_elem_true = newTemp(Ity_I32); |
| 14709 | IRTemp all_elem_false = newTemp(Ity_I32); |
| 14710 | |
| 14711 | assign(frA_hi, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, mkexpr( vA )))); |
| 14712 | assign(frB_hi, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, mkexpr( vB )))); |
| 14713 | assign(frA_lo, unop(Iop_ReinterpI64asF64, unop(Iop_V128to64, mkexpr( vA )))); |
| 14714 | assign(frB_lo, unop(Iop_ReinterpI64asF64, unop(Iop_V128to64, mkexpr( vB )))); |
| 14715 | |
| 14716 | ccIR_hi = get_fp_cmp_CR_val( binop( Iop_CmpF64, |
| 14717 | mkexpr( frA_hi ), |
| 14718 | mkexpr( frB_hi ) ) ); |
| 14719 | ccIR_lo = get_fp_cmp_CR_val( binop( Iop_CmpF64, |
| 14720 | mkexpr( frA_lo ), |
| 14721 | mkexpr( frB_lo ) ) ); |
| 14722 | |
| 14723 | if (cmp_type != PPC_CMP_GE) { |
| 14724 | assign( hiResult, |
| 14725 | unop( Iop_1Sto64, |
| 14726 | binop( Iop_CmpEQ32, mkexpr( ccIR_hi ), mkU32( cmp_type ) ) ) ); |
| 14727 | assign( loResult, |
| 14728 | unop( Iop_1Sto64, |
| 14729 | binop( Iop_CmpEQ32, mkexpr( ccIR_lo ), mkU32( cmp_type ) ) ) ); |
| 14730 | } else { |
| 14731 | // For PPC_CMP_GE, one element compare may return "4" (for "greater than") and |
| 14732 | // the other element compare may return "2" (for "equal to"). |
| 14733 | IRTemp lo_GE = newTemp(Ity_I1); |
| 14734 | IRTemp hi_GE = newTemp(Ity_I1); |
| 14735 | |
| 14736 | assign(hi_GE, mkOR1( binop( Iop_CmpEQ32, mkexpr( ccIR_hi ), mkU32( 2 ) ), |
| 14737 | binop( Iop_CmpEQ32, mkexpr( ccIR_hi ), mkU32( 4 ) ) ) ); |
| 14738 | assign( hiResult,unop( Iop_1Sto64, mkexpr( hi_GE ) ) ); |
| 14739 | |
| 14740 | assign(lo_GE, mkOR1( binop( Iop_CmpEQ32, mkexpr( ccIR_lo ), mkU32( 2 ) ), |
| 14741 | binop( Iop_CmpEQ32, mkexpr( ccIR_lo ), mkU32( 4 ) ) ) ); |
| 14742 | assign( loResult, unop( Iop_1Sto64, mkexpr( lo_GE ) ) ); |
| 14743 | } |
| 14744 | |
| 14745 | // The [hi/lo]Result will be all 1's or all 0's. We just look at the lower word. |
| 14746 | assign( hiEQlo, |
| 14747 | binop( Iop_CmpEQ32, |
| 14748 | unop( Iop_64to32, mkexpr( hiResult ) ), |
| 14749 | unop( Iop_64to32, mkexpr( loResult ) ) ) ); |
| 14750 | putVSReg( XT, |
| 14751 | binop( Iop_64HLtoV128, mkexpr( hiResult ), mkexpr( loResult ) ) ); |
| 14752 | |
| 14753 | assign( all_elem_true, |
| 14754 | unop( Iop_1Uto32, |
| 14755 | mkAND1( mkexpr( hiEQlo ), |
| 14756 | binop( Iop_CmpEQ32, |
| 14757 | mkU32( 0xffffffff ), |
| 14758 | unop( Iop_64to32, |
| 14759 | mkexpr( hiResult ) ) ) ) ) ); |
| 14760 | |
| 14761 | assign( all_elem_false, |
| 14762 | unop( Iop_1Uto32, |
| 14763 | mkAND1( mkexpr( hiEQlo ), |
| 14764 | binop( Iop_CmpEQ32, |
| 14765 | mkU32( 0 ), |
| 14766 | unop( Iop_64to32, |
| 14767 | mkexpr( hiResult ) ) ) ) ) ); |
| 14768 | assign( ccPPC32, |
| 14769 | binop( Iop_Or32, |
| 14770 | binop( Iop_Shl32, mkexpr( all_elem_false ), mkU8( 1 ) ), |
| 14771 | binop( Iop_Shl32, mkexpr( all_elem_true ), mkU8( 3 ) ) ) ); |
| 14772 | |
| 14773 | if (flag_rC) { |
| 14774 | putGST_field( PPC_GST_CR, mkexpr(ccPPC32), 6 ); |
| 14775 | } |
| 14776 | } |
| 14777 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14778 | /* |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14779 | * VSX Vector Compare Instructions |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14780 | */ |
| 14781 | static Bool |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14782 | dis_vvec_cmp( UInt theInstr, UInt opc2 ) |
| 14783 | { |
| 14784 | /* XX3-Form */ |
| 14785 | UChar opc1 = ifieldOPC( theInstr ); |
| 14786 | UChar XT = ifieldRegXT ( theInstr ); |
| 14787 | UChar XA = ifieldRegXA ( theInstr ); |
| 14788 | UChar XB = ifieldRegXB ( theInstr ); |
| 14789 | UChar flag_rC = ifieldBIT10(theInstr); |
| 14790 | IRTemp vA = newTemp( Ity_V128 ); |
| 14791 | IRTemp vB = newTemp( Ity_V128 ); |
| 14792 | |
| 14793 | if (opc1 != 0x3C) { |
| 14794 | vex_printf( "dis_vvec_cmp(ppc)(instr)\n" ); |
| 14795 | return False; |
| 14796 | } |
| 14797 | |
| 14798 | assign( vA, getVSReg( XA ) ); |
| 14799 | assign( vB, getVSReg( XB ) ); |
| 14800 | |
| 14801 | switch (opc2) { |
| 14802 | case 0x18C: case 0x38C: // xvcmpeqdp[.] (VSX Vector Compare Equal To Double-Precision [ & Record ]) |
| 14803 | { |
| 14804 | DIP("xvcmpeqdp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""), |
| 14805 | (UInt)XT, (UInt)XA, (UInt)XB); |
| 14806 | do_vvec_fp_cmp(vA, vB, XT, flag_rC, PPC_CMP_EQ); |
| 14807 | break; |
| 14808 | } |
| 14809 | |
| 14810 | case 0x1CC: case 0x3CC: // xvcmpgedp[.] (VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ]) |
| 14811 | { |
| 14812 | DIP("xvcmpgedp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""), |
| 14813 | (UInt)XT, (UInt)XA, (UInt)XB); |
| 14814 | do_vvec_fp_cmp(vA, vB, XT, flag_rC, PPC_CMP_GE); |
| 14815 | break; |
| 14816 | } |
| 14817 | |
| 14818 | case 0x1AC: case 0x3AC: // xvcmpgtdp[.] (VSX Vector Compare Greater Than Double-Precision [ & Record ]) |
| 14819 | { |
| 14820 | DIP("xvcmpgtdp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""), |
| 14821 | (UInt)XT, (UInt)XA, (UInt)XB); |
| 14822 | do_vvec_fp_cmp(vA, vB, XT, flag_rC, PPC_CMP_GT); |
| 14823 | break; |
| 14824 | } |
| 14825 | |
| 14826 | case 0x10C: case 0x30C: // xvcmpeqsp[.] (VSX Vector Compare Equal To Single-Precision [ & Record ]) |
| 14827 | { |
| 14828 | IRTemp vD = newTemp(Ity_V128); |
| 14829 | |
| 14830 | DIP("xvcmpeqsp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""), |
| 14831 | (UInt)XT, (UInt)XA, (UInt)XB); |
| 14832 | assign( vD, binop(Iop_CmpEQ32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 14833 | putVSReg( XT, mkexpr(vD) ); |
| 14834 | if (flag_rC) { |
| 14835 | set_AV_CR6( mkexpr(vD), True ); |
| 14836 | } |
| 14837 | break; |
| 14838 | } |
| 14839 | |
| 14840 | case 0x14C: case 0x34C: // xvcmpgesp[.] (VSX Vector Compare Greater Than or Equal To Single-Precision [ & Record ]) |
| 14841 | { |
| 14842 | IRTemp vD = newTemp(Ity_V128); |
| 14843 | |
| 14844 | DIP("xvcmpgesp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""), |
| 14845 | (UInt)XT, (UInt)XA, (UInt)XB); |
| 14846 | assign( vD, binop(Iop_CmpGE32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 14847 | putVSReg( XT, mkexpr(vD) ); |
| 14848 | if (flag_rC) { |
| 14849 | set_AV_CR6( mkexpr(vD), True ); |
| 14850 | } |
| 14851 | break; |
| 14852 | } |
| 14853 | |
| 14854 | case 0x12C: case 0x32C: //xvcmpgtsp[.] (VSX Vector Compare Greater Than Single-Precision [ & Record ]) |
| 14855 | { |
| 14856 | IRTemp vD = newTemp(Ity_V128); |
| 14857 | |
| 14858 | DIP("xvcmpgtsp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""), |
| 14859 | (UInt)XT, (UInt)XA, (UInt)XB); |
| 14860 | assign( vD, binop(Iop_CmpGT32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 14861 | putVSReg( XT, mkexpr(vD) ); |
| 14862 | if (flag_rC) { |
| 14863 | set_AV_CR6( mkexpr(vD), True ); |
| 14864 | } |
| 14865 | break; |
| 14866 | } |
| 14867 | |
| 14868 | default: |
| 14869 | vex_printf( "dis_vvec_cmp(ppc)(opc2)\n" ); |
| 14870 | return False; |
| 14871 | } |
| 14872 | return True; |
| 14873 | } |
| 14874 | /* |
| 14875 | * Miscellaneous VSX Scalar Instructions |
| 14876 | */ |
| 14877 | static Bool |
| 14878 | dis_vxs_misc( UInt theInstr, UInt opc2 ) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14879 | { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 14880 | #define VG_PPC_SIGN_MASK 0x7fffffffffffffffULL |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14881 | /* XX3-Form and XX2-Form */ |
| 14882 | UChar opc1 = ifieldOPC( theInstr ); |
| 14883 | UChar XT = ifieldRegXT ( theInstr ); |
| 14884 | UChar XA = ifieldRegXA ( theInstr ); |
| 14885 | UChar XB = ifieldRegXB ( theInstr ); |
| 14886 | IRTemp vA = newTemp( Ity_V128 ); |
| 14887 | IRTemp vB = newTemp( Ity_V128 ); |
| 14888 | |
| 14889 | if (opc1 != 0x3C) { |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14890 | vex_printf( "dis_vxs_misc(ppc)(instr)\n" ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14891 | return False; |
| 14892 | } |
| 14893 | |
| 14894 | assign( vA, getVSReg( XA ) ); |
| 14895 | assign( vB, getVSReg( XB ) ); |
| 14896 | |
| 14897 | /* For all the VSX move instructions, the contents of doubleword element 1 |
| 14898 | * of VSX[XT] are undefined after the operation; therefore, we can simply |
| 14899 | * move the entire array element where it makes sense to do so. |
| 14900 | */ |
| 14901 | |
| 14902 | switch (opc2) { |
| 14903 | case 0x2B2: // xsabsdp (VSX scalar absolute value double-precision |
| 14904 | { |
| 14905 | /* Move abs val of dw 0 of VSX[XB] to dw 0 of VSX[XT]. */ |
| 14906 | IRTemp absVal = newTemp(Ity_V128); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 14907 | if (host_endness == VexEndnessLE) { |
| 14908 | IRTemp hi64 = newTemp(Ity_I64); |
| 14909 | IRTemp lo64 = newTemp(Ity_I64); |
| 14910 | assign( hi64, unop( Iop_V128HIto64, mkexpr(vB) ) ); |
| 14911 | assign( lo64, unop( Iop_V128to64, mkexpr(vB) ) ); |
| 14912 | assign( absVal, binop( Iop_64HLtoV128, |
| 14913 | binop( Iop_And64, mkexpr(hi64), |
| 14914 | mkU64(VG_PPC_SIGN_MASK) ), |
| 14915 | mkexpr(lo64) ) ); |
| 14916 | } else { |
| 14917 | assign(absVal, binop(Iop_ShrV128, |
| 14918 | binop(Iop_ShlV128, mkexpr(vB), |
| 14919 | mkU8(1)), mkU8(1))); |
| 14920 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14921 | DIP("xsabsdp v%d,v%d\n", (UInt)XT, (UInt)XB); |
| 14922 | putVSReg(XT, mkexpr(absVal)); |
| 14923 | break; |
| 14924 | } |
| 14925 | case 0x2C0: // xscpsgndp |
| 14926 | { |
| 14927 | /* Scalar copy sign double-precision */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 14928 | IRTemp vecA_signed = newTemp(Ity_I64); |
| 14929 | IRTemp vecB_unsigned = newTemp(Ity_I64); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14930 | IRTemp vec_result = newTemp(Ity_V128); |
| 14931 | DIP("xscpsgndp v%d,v%d v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 14932 | assign( vecA_signed, binop( Iop_And64, |
| 14933 | unop( Iop_V128HIto64, |
| 14934 | mkexpr(vA)), |
| 14935 | mkU64(~VG_PPC_SIGN_MASK) ) ); |
| 14936 | assign( vecB_unsigned, binop( Iop_And64, |
| 14937 | unop( Iop_V128HIto64, |
| 14938 | mkexpr(vB) ), |
| 14939 | mkU64(VG_PPC_SIGN_MASK) ) ); |
| 14940 | assign( vec_result, binop( Iop_64HLtoV128, |
| 14941 | binop( Iop_Or64, |
| 14942 | mkexpr(vecA_signed), |
| 14943 | mkexpr(vecB_unsigned) ), |
| 14944 | mkU64(0x0ULL))); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14945 | putVSReg(XT, mkexpr(vec_result)); |
| 14946 | break; |
| 14947 | } |
| 14948 | case 0x2D2: // xsnabsdp |
| 14949 | { |
| 14950 | /* Scalar negative absolute value double-precision */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 14951 | IRTemp BHi_signed = newTemp(Ity_I64); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14952 | DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 14953 | assign( BHi_signed, binop( Iop_Or64, |
| 14954 | unop( Iop_V128HIto64, |
| 14955 | mkexpr(vB) ), |
| 14956 | mkU64(~VG_PPC_SIGN_MASK) ) ); |
| 14957 | putVSReg(XT, binop( Iop_64HLtoV128, |
| 14958 | mkexpr(BHi_signed), mkU64(0x0ULL) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14959 | break; |
| 14960 | } |
| 14961 | case 0x2F2: // xsnegdp |
| 14962 | { |
| 14963 | /* Scalar negate double-precision */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 14964 | IRTemp BHi_signed = newTemp(Ity_I64); |
| 14965 | IRTemp BHi_unsigned = newTemp(Ity_I64); |
| 14966 | IRTemp BHi_negated = newTemp(Ity_I64); |
| 14967 | IRTemp BHi_negated_signbit = newTemp(Ity_I1); |
| 14968 | IRTemp vec_result = newTemp(Ity_V128); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14969 | DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 14970 | assign( BHi_signed, unop( Iop_V128HIto64, mkexpr(vB) ) ); |
| 14971 | assign( BHi_unsigned, binop( Iop_And64, mkexpr(BHi_signed), |
| 14972 | mkU64(VG_PPC_SIGN_MASK) ) ); |
| 14973 | assign( BHi_negated_signbit, |
| 14974 | unop( Iop_Not1, |
| 14975 | unop( Iop_32to1, |
| 14976 | binop( Iop_Shr32, |
| 14977 | unop( Iop_64HIto32, |
| 14978 | binop( Iop_And64, |
| 14979 | mkexpr(BHi_signed), |
| 14980 | mkU64(~VG_PPC_SIGN_MASK) ) |
| 14981 | ), |
| 14982 | mkU8(31) ) ) ) ); |
| 14983 | assign( BHi_negated, |
| 14984 | binop( Iop_Or64, |
| 14985 | binop( Iop_32HLto64, |
| 14986 | binop( Iop_Shl32, |
| 14987 | unop( Iop_1Uto32, |
| 14988 | mkexpr(BHi_negated_signbit) ), |
| 14989 | mkU8(31) ), |
| 14990 | mkU32(0) ), |
| 14991 | mkexpr(BHi_unsigned) ) ); |
| 14992 | assign( vec_result, binop( Iop_64HLtoV128, mkexpr(BHi_negated), |
| 14993 | mkU64(0x0ULL))); |
| 14994 | putVSReg( XT, mkexpr(vec_result)); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 14995 | break; |
| 14996 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 14997 | case 0x280: // xsmaxdp (VSX Scalar Maximum Double-Precision) |
| 14998 | case 0x2A0: // xsmindp (VSX Scalar Minimum Double-Precision) |
| 14999 | { |
| 15000 | IRTemp frA = newTemp(Ity_I64); |
| 15001 | IRTemp frB = newTemp(Ity_I64); |
| 15002 | Bool isMin = opc2 == 0x2A0 ? True : False; |
| 15003 | DIP("%s v%d,v%d v%d\n", isMin ? "xsmaxdp" : "xsmindp", (UInt)XT, (UInt)XA, (UInt)XB); |
| 15004 | |
| 15005 | assign(frA, unop(Iop_V128HIto64, mkexpr( vA ))); |
| 15006 | assign(frB, unop(Iop_V128HIto64, mkexpr( vB ))); |
| 15007 | putVSReg( XT, binop( Iop_64HLtoV128, get_max_min_fp(frA, frB, isMin), mkU64( 0 ) ) ); |
| 15008 | |
| 15009 | break; |
| 15010 | } |
| 15011 | case 0x0F2: // xsrdpim (VSX Scalar Round to Double-Precision Integer using round toward -Infinity) |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 15012 | case 0x0D2: // xsrdpip (VSX Scalar Round to Double-Precision Integer using round toward +Infinity) |
| 15013 | case 0x0D6: // xsrdpic (VSX Scalar Round to Double-Precision Integer using Current rounding mode) |
| 15014 | case 0x0B2: // xsrdpiz (VSX Scalar Round to Double-Precision Integer using round toward Zero) |
| 15015 | case 0x092: // xsrdpi (VSX Scalar Round to Double-Precision Integer using round toward Nearest Away) |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15016 | { |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15017 | IRTemp frB_I64 = newTemp(Ity_I64); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 15018 | IRExpr * frD_fp_round = NULL; |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 15019 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15020 | assign(frB_I64, unop(Iop_V128HIto64, mkexpr( vB ))); |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 15021 | frD_fp_round = _do_vsx_fp_roundToInt(frB_I64, opc2); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15022 | |
carll | 9884af0 | 2013-01-30 18:39:57 +0000 | [diff] [blame] | 15023 | DIP("xsrdpi%s v%d,v%d\n", _get_vsx_rdpi_suffix(opc2), (UInt)XT, (UInt)XB); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15024 | putVSReg( XT, |
| 15025 | binop( Iop_64HLtoV128, |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 15026 | unop( Iop_ReinterpF64asI64, frD_fp_round), |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15027 | mkU64( 0 ) ) ); |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 15028 | break; |
| 15029 | } |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15030 | case 0x034: // xsresp (VSX Scalar Reciprocal Estimate single-Precision) |
| 15031 | case 0x014: /* xsrsqrtesp (VSX Scalar Reciprocal Square Root Estimate |
| 15032 | * single-Precision) |
| 15033 | */ |
| 15034 | { |
| 15035 | IRTemp frB = newTemp(Ity_F64); |
| 15036 | IRTemp sqrt = newTemp(Ity_F64); |
| 15037 | IRExpr* ieee_one = IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL)); |
| 15038 | IRExpr* rm = get_IR_roundingmode(); |
| 15039 | Bool redp = opc2 == 0x034; |
| 15040 | DIP("%s v%d,v%d\n", redp ? "xsresp" : "xsrsqrtesp", (UInt)XT, |
| 15041 | (UInt)XB); |
| 15042 | |
| 15043 | assign( frB, |
| 15044 | unop( Iop_ReinterpI64asF64, |
| 15045 | unop( Iop_V128HIto64, mkexpr( vB ) ) ) ); |
| 15046 | |
| 15047 | if (!redp) |
| 15048 | assign( sqrt, |
| 15049 | binop( Iop_SqrtF64, |
| 15050 | rm, |
| 15051 | mkexpr(frB) ) ); |
| 15052 | putVSReg( XT, |
| 15053 | binop( Iop_64HLtoV128, |
| 15054 | unop( Iop_ReinterpF64asI64, |
| 15055 | binop( Iop_RoundF64toF32, rm, |
| 15056 | triop( Iop_DivF64, |
| 15057 | rm, |
| 15058 | ieee_one, |
| 15059 | redp ? mkexpr( frB ) : |
| 15060 | mkexpr( sqrt ) ) ) ), |
| 15061 | mkU64( 0 ) ) ); |
| 15062 | break; |
| 15063 | } |
| 15064 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 15065 | case 0x0B4: // xsredp (VSX Scalar Reciprocal Estimate Double-Precision) |
| 15066 | case 0x094: // xsrsqrtedp (VSX Scalar Reciprocal Square Root Estimate Double-Precision) |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15067 | |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 15068 | { |
| 15069 | IRTemp frB = newTemp(Ity_F64); |
| 15070 | IRTemp sqrt = newTemp(Ity_F64); |
| 15071 | IRExpr* ieee_one = IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL)); |
| 15072 | IRExpr* rm = get_IR_roundingmode(); |
| 15073 | Bool redp = opc2 == 0x0B4; |
| 15074 | DIP("%s v%d,v%d\n", redp ? "xsredp" : "xsrsqrtedp", (UInt)XT, (UInt)XB); |
| 15075 | assign( frB, |
| 15076 | unop( Iop_ReinterpI64asF64, |
| 15077 | unop( Iop_V128HIto64, mkexpr( vB ) ) ) ); |
| 15078 | |
| 15079 | if (!redp) |
| 15080 | assign( sqrt, |
| 15081 | binop( Iop_SqrtF64, |
| 15082 | rm, |
| 15083 | mkexpr(frB) ) ); |
| 15084 | putVSReg( XT, |
| 15085 | binop( Iop_64HLtoV128, |
| 15086 | unop( Iop_ReinterpF64asI64, |
| 15087 | triop( Iop_DivF64, |
| 15088 | rm, |
| 15089 | ieee_one, |
| 15090 | redp ? mkexpr( frB ) : mkexpr( sqrt ) ) ), |
| 15091 | mkU64( 0 ) ) ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15092 | break; |
| 15093 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15094 | |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15095 | case 0x232: // xsrsp (VSX Scalar Round to Single-Precision) |
| 15096 | { |
| 15097 | IRTemp frB = newTemp(Ity_F64); |
| 15098 | IRExpr* rm = get_IR_roundingmode(); |
| 15099 | DIP("xsrsp v%d, v%d\n", (UInt)XT, (UInt)XB); |
| 15100 | assign( frB, |
| 15101 | unop( Iop_ReinterpI64asF64, |
| 15102 | unop( Iop_V128HIto64, mkexpr( vB ) ) ) ); |
| 15103 | |
| 15104 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 15105 | unop( Iop_ReinterpF64asI64, |
| 15106 | binop( Iop_RoundF64toF32, |
| 15107 | rm, |
| 15108 | mkexpr( frB ) ) ), |
| 15109 | mkU64( 0 ) ) ); |
| 15110 | break; |
| 15111 | } |
| 15112 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15113 | default: |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15114 | vex_printf( "dis_vxs_misc(ppc)(opc2)\n" ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15115 | return False; |
| 15116 | } |
| 15117 | return True; |
| 15118 | } |
| 15119 | |
| 15120 | /* |
| 15121 | * VSX Logical Instructions |
| 15122 | */ |
| 15123 | static Bool |
| 15124 | dis_vx_logic ( UInt theInstr, UInt opc2 ) |
| 15125 | { |
| 15126 | /* XX3-Form */ |
| 15127 | UChar opc1 = ifieldOPC( theInstr ); |
| 15128 | UChar XT = ifieldRegXT ( theInstr ); |
| 15129 | UChar XA = ifieldRegXA ( theInstr ); |
| 15130 | UChar XB = ifieldRegXB ( theInstr ); |
| 15131 | IRTemp vA = newTemp( Ity_V128 ); |
| 15132 | IRTemp vB = newTemp( Ity_V128 ); |
| 15133 | |
| 15134 | if (opc1 != 0x3C) { |
| 15135 | vex_printf( "dis_vx_logic(ppc)(instr)\n" ); |
| 15136 | return False; |
| 15137 | } |
| 15138 | |
| 15139 | assign( vA, getVSReg( XA ) ); |
| 15140 | assign( vB, getVSReg( XB ) ); |
| 15141 | |
| 15142 | switch (opc2) { |
| 15143 | case 0x268: // xxlxor |
| 15144 | DIP("xxlxor v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 15145 | putVSReg( XT, binop( Iop_XorV128, mkexpr( vA ), mkexpr( vB ) ) ); |
| 15146 | break; |
| 15147 | case 0x248: // xxlor |
| 15148 | DIP("xxlor v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 15149 | putVSReg( XT, binop( Iop_OrV128, mkexpr( vA ), mkexpr( vB ) ) ); |
| 15150 | break; |
| 15151 | case 0x288: // xxlnor |
| 15152 | DIP("xxlnor v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 15153 | putVSReg( XT, unop( Iop_NotV128, binop( Iop_OrV128, mkexpr( vA ), |
| 15154 | mkexpr( vB ) ) ) ); |
| 15155 | break; |
| 15156 | case 0x208: // xxland |
| 15157 | DIP("xxland v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 15158 | putVSReg( XT, binop( Iop_AndV128, mkexpr( vA ), mkexpr( vB ) ) ); |
| 15159 | break; |
| 15160 | case 0x228: //xxlandc |
| 15161 | DIP("xxlandc v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 15162 | putVSReg( XT, binop( Iop_AndV128, mkexpr( vA ), unop( Iop_NotV128, |
| 15163 | mkexpr( vB ) ) ) ); |
| 15164 | break; |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15165 | case 0x2A8: // xxlorc (VSX Logical OR with complement) |
| 15166 | DIP("xxlorc v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 15167 | putVSReg( XT, binop( Iop_OrV128, |
| 15168 | mkexpr( vA ), |
| 15169 | unop( Iop_NotV128, mkexpr( vB ) ) ) ); |
| 15170 | break; |
| 15171 | case 0x2C8: // xxlnand (VSX Logical NAND) |
| 15172 | DIP("xxlnand v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 15173 | putVSReg( XT, unop( Iop_NotV128, |
| 15174 | binop( Iop_AndV128, mkexpr( vA ), |
| 15175 | mkexpr( vB ) ) ) ); |
| 15176 | break; |
| 15177 | case 0x2E8: // xxleqv (VSX Logical Equivalence) |
| 15178 | DIP("xxleqv v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); |
| 15179 | putVSReg( XT, unop( Iop_NotV128, |
| 15180 | binop( Iop_XorV128, |
| 15181 | mkexpr( vA ), mkexpr( vB ) ) ) ); |
| 15182 | break; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15183 | default: |
| 15184 | vex_printf( "dis_vx_logic(ppc)(opc2)\n" ); |
| 15185 | return False; |
| 15186 | } |
| 15187 | return True; |
| 15188 | } |
| 15189 | |
| 15190 | /* |
| 15191 | * VSX Load Instructions |
| 15192 | * NOTE: VSX supports word-aligned storage access. |
| 15193 | */ |
| 15194 | static Bool |
| 15195 | dis_vx_load ( UInt theInstr ) |
| 15196 | { |
| 15197 | /* XX1-Form */ |
| 15198 | UChar opc1 = ifieldOPC( theInstr ); |
| 15199 | UChar XT = ifieldRegXT ( theInstr ); |
| 15200 | UChar rA_addr = ifieldRegA( theInstr ); |
| 15201 | UChar rB_addr = ifieldRegB( theInstr ); |
| 15202 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 15203 | |
| 15204 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 15205 | IRTemp EA = newTemp( ty ); |
| 15206 | |
| 15207 | if (opc1 != 0x1F) { |
| 15208 | vex_printf( "dis_vx_load(ppc)(instr)\n" ); |
| 15209 | return False; |
| 15210 | } |
| 15211 | |
| 15212 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
| 15213 | |
| 15214 | switch (opc2) { |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15215 | case 0x00C: // lxsiwzx (Load VSX Scalar as Integer Word and Zero Indexed) |
| 15216 | { |
| 15217 | IRExpr * exp; |
| 15218 | DIP("lxsiwzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15219 | exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) ); |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15220 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 15221 | unop( Iop_32Uto64, exp), |
| 15222 | mkU64(0) ) ); |
| 15223 | break; |
| 15224 | } |
| 15225 | case 0x04C: // lxsiwax (Load VSX Scalar as Integer Word Algebraic Indexed) |
| 15226 | { |
| 15227 | IRExpr * exp; |
| 15228 | DIP("lxsiwax %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15229 | exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) ); |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15230 | putVSReg( XT, binop( Iop_64HLtoV128, |
| 15231 | unop( Iop_32Sto64, exp), |
| 15232 | mkU64(0) ) ); |
| 15233 | break; |
| 15234 | } |
| 15235 | case 0x20C: // lxsspx (Load VSX Scalar Single-Precision Indexed) |
| 15236 | { |
| 15237 | IRExpr * exp; |
| 15238 | DIP("lxsspx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); |
| 15239 | /* Take 32-bit floating point value in the upper half of the fetched |
| 15240 | * 64-bit value, convert to 64-bit floating point value and load into |
| 15241 | * top word of V128. |
| 15242 | */ |
| 15243 | exp = unop( Iop_ReinterpF64asI64, |
| 15244 | unop( Iop_F32toF64, |
| 15245 | unop( Iop_ReinterpI32asF32, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15246 | load( Ity_I32, mkexpr( EA ) ) ) ) ); |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15247 | |
| 15248 | putVSReg( XT, binop( Iop_64HLtoV128, exp, mkU64( 0 ) ) ); |
| 15249 | break; |
| 15250 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15251 | case 0x24C: // lxsdx |
| 15252 | { |
| 15253 | IRExpr * exp; |
| 15254 | DIP("lxsdx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15255 | exp = load( Ity_I64, mkexpr( EA ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15256 | // We need to pass an expression of type Ity_V128 with putVSReg, but the load |
| 15257 | // we just performed is only a DW. But since the contents of VSR[XT] element 1 |
| 15258 | // are undefined after this operation, we can just do a splat op. |
| 15259 | putVSReg( XT, binop( Iop_64HLtoV128, exp, exp ) ); |
| 15260 | break; |
| 15261 | } |
| 15262 | case 0x34C: // lxvd2x |
| 15263 | { |
| 15264 | IROp addOp = ty == Ity_I64 ? Iop_Add64 : Iop_Add32; |
| 15265 | IRExpr * high, *low; |
| 15266 | ULong ea_off = 8; |
| 15267 | IRExpr* high_addr; |
| 15268 | DIP("lxvd2x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15269 | high = load( Ity_I64, mkexpr( EA ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15270 | high_addr = binop( addOp, mkexpr( EA ), ty == Ity_I64 ? mkU64( ea_off ) |
| 15271 | : mkU32( ea_off ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15272 | low = load( Ity_I64, high_addr ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15273 | putVSReg( XT, binop( Iop_64HLtoV128, high, low ) ); |
| 15274 | break; |
| 15275 | } |
| 15276 | case 0x14C: // lxvdsx |
| 15277 | { |
| 15278 | IRTemp data = newTemp(Ity_I64); |
| 15279 | DIP("lxvdsx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15280 | assign( data, load( Ity_I64, mkexpr( EA ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15281 | putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( data ), mkexpr( data ) ) ); |
| 15282 | break; |
| 15283 | } |
| 15284 | case 0x30C: |
| 15285 | { |
| 15286 | IRExpr * t3, *t2, *t1, *t0; |
| 15287 | UInt ea_off = 0; |
| 15288 | IRExpr* irx_addr; |
| 15289 | |
| 15290 | DIP("lxvw4x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15291 | t3 = load( Ity_I32, mkexpr( EA ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15292 | ea_off += 4; |
| 15293 | irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), |
| 15294 | ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15295 | t2 = load( Ity_I32, irx_addr ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15296 | ea_off += 4; |
| 15297 | irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), |
| 15298 | ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15299 | t1 = load( Ity_I32, irx_addr ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15300 | ea_off += 4; |
| 15301 | irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), |
| 15302 | ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15303 | t0 = load( Ity_I32, irx_addr ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15304 | putVSReg( XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, t3, t2 ), |
| 15305 | binop( Iop_32HLto64, t1, t0 ) ) ); |
| 15306 | break; |
| 15307 | } |
| 15308 | default: |
| 15309 | vex_printf( "dis_vx_load(ppc)(opc2)\n" ); |
| 15310 | return False; |
| 15311 | } |
| 15312 | return True; |
| 15313 | } |
| 15314 | |
| 15315 | /* |
| 15316 | * VSX Store Instructions |
| 15317 | * NOTE: VSX supports word-aligned storage access. |
| 15318 | */ |
| 15319 | static Bool |
| 15320 | dis_vx_store ( UInt theInstr ) |
| 15321 | { |
| 15322 | /* XX1-Form */ |
| 15323 | UChar opc1 = ifieldOPC( theInstr ); |
| 15324 | UChar XS = ifieldRegXS( theInstr ); |
| 15325 | UChar rA_addr = ifieldRegA( theInstr ); |
| 15326 | UChar rB_addr = ifieldRegB( theInstr ); |
| 15327 | IRTemp vS = newTemp( Ity_V128 ); |
| 15328 | UInt opc2 = ifieldOPClo10( theInstr ); |
| 15329 | |
| 15330 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 15331 | IRTemp EA = newTemp( ty ); |
| 15332 | |
| 15333 | if (opc1 != 0x1F) { |
| 15334 | vex_printf( "dis_vx_store(ppc)(instr)\n" ); |
| 15335 | return False; |
| 15336 | } |
| 15337 | |
| 15338 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
| 15339 | assign( vS, getVSReg( XS ) ); |
| 15340 | |
| 15341 | switch (opc2) { |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15342 | case 0x08C: |
| 15343 | { |
| 15344 | /* Need the next to the most significant 32-bit word from |
| 15345 | * the 128-bit vector. |
| 15346 | */ |
| 15347 | IRExpr * high64, * low32; |
| 15348 | DIP("stxsiwx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); |
| 15349 | high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); |
| 15350 | low32 = unop( Iop_64to32, high64 ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15351 | store( mkexpr( EA ), low32 ); |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15352 | break; |
| 15353 | } |
| 15354 | case 0x28C: |
| 15355 | { |
| 15356 | IRTemp high64 = newTemp(Ity_F64); |
| 15357 | IRTemp val32 = newTemp(Ity_I32); |
| 15358 | DIP("stxsspx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); |
| 15359 | assign(high64, unop( Iop_ReinterpI64asF64, |
| 15360 | unop( Iop_V128HIto64, mkexpr( vS ) ) ) ); |
| 15361 | assign(val32, unop( Iop_ReinterpF32asI32, |
| 15362 | unop( Iop_TruncF64asF32, |
| 15363 | mkexpr(high64) ) ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15364 | store( mkexpr( EA ), mkexpr( val32 ) ); |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 15365 | break; |
| 15366 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15367 | case 0x2CC: |
| 15368 | { |
| 15369 | IRExpr * high64; |
| 15370 | DIP("stxsdx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); |
| 15371 | high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15372 | store( mkexpr( EA ), high64 ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15373 | break; |
| 15374 | } |
| 15375 | case 0x3CC: |
| 15376 | { |
| 15377 | IRExpr * high64, *low64; |
| 15378 | DIP("stxvd2x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); |
| 15379 | high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); |
| 15380 | low64 = unop( Iop_V128to64, mkexpr( vS ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15381 | store( mkexpr( EA ), high64 ); |
| 15382 | store( binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), |
| 15383 | ty == Ity_I64 ? mkU64( 8 ) : mkU32( 8 ) ), low64 ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15384 | break; |
| 15385 | } |
| 15386 | case 0x38C: |
| 15387 | { |
| 15388 | UInt ea_off = 0; |
| 15389 | IRExpr* irx_addr; |
| 15390 | IRTemp hi64 = newTemp( Ity_I64 ); |
| 15391 | IRTemp lo64 = newTemp( Ity_I64 ); |
| 15392 | |
| 15393 | DIP("stxvw4x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); |
| 15394 | |
| 15395 | // This instruction supports word-aligned stores, so EA may not be |
| 15396 | // quad-word aligned. Therefore, do 4 individual word-size stores. |
| 15397 | assign( hi64, unop( Iop_V128HIto64, mkexpr( vS ) ) ); |
| 15398 | assign( lo64, unop( Iop_V128to64, mkexpr( vS ) ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15399 | store( mkexpr( EA ), unop( Iop_64HIto32, mkexpr( hi64 ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15400 | ea_off += 4; |
| 15401 | irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), |
| 15402 | ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15403 | store( irx_addr, unop( Iop_64to32, mkexpr( hi64 ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15404 | ea_off += 4; |
| 15405 | irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), |
| 15406 | ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15407 | store( irx_addr, unop( Iop_64HIto32, mkexpr( lo64 ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15408 | ea_off += 4; |
| 15409 | irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), |
| 15410 | ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15411 | store( irx_addr, unop( Iop_64to32, mkexpr( lo64 ) ) ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15412 | |
| 15413 | break; |
| 15414 | } |
| 15415 | default: |
| 15416 | vex_printf( "dis_vx_store(ppc)(opc2)\n" ); |
| 15417 | return False; |
| 15418 | } |
| 15419 | return True; |
| 15420 | } |
| 15421 | |
| 15422 | /* |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15423 | * VSX permute and other miscealleous instructions |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15424 | */ |
| 15425 | static Bool |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15426 | dis_vx_permute_misc( UInt theInstr, UInt opc2 ) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15427 | { |
| 15428 | /* XX3-Form */ |
| 15429 | UChar opc1 = ifieldOPC( theInstr ); |
| 15430 | UChar XT = ifieldRegXT ( theInstr ); |
| 15431 | UChar XA = ifieldRegXA ( theInstr ); |
| 15432 | UChar XB = ifieldRegXB ( theInstr ); |
| 15433 | IRTemp vT = newTemp( Ity_V128 ); |
| 15434 | IRTemp vA = newTemp( Ity_V128 ); |
| 15435 | IRTemp vB = newTemp( Ity_V128 ); |
| 15436 | |
| 15437 | if (opc1 != 0x3C) { |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15438 | vex_printf( "dis_vx_permute_misc(ppc)(instr)\n" ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15439 | return False; |
| 15440 | } |
| 15441 | |
| 15442 | assign( vA, getVSReg( XA ) ); |
| 15443 | assign( vB, getVSReg( XB ) ); |
| 15444 | |
| 15445 | switch (opc2) { |
| 15446 | case 0x8: // xxsldwi (VSX Shift Left Double by Word Immediate) |
| 15447 | { |
| 15448 | UChar SHW = ifieldSHW ( theInstr ); |
| 15449 | IRTemp result = newTemp(Ity_V128); |
| 15450 | if ( SHW != 0 ) { |
| 15451 | IRTemp hi = newTemp(Ity_V128); |
| 15452 | IRTemp lo = newTemp(Ity_V128); |
| 15453 | assign( hi, binop(Iop_ShlV128, mkexpr(vA), mkU8(SHW*32)) ); |
| 15454 | assign( lo, binop(Iop_ShrV128, mkexpr(vB), mkU8(128-SHW*32)) ); |
| 15455 | assign ( result, binop(Iop_OrV128, mkexpr(hi), mkexpr(lo)) ); |
| 15456 | } else |
| 15457 | assign ( result, mkexpr(vA) ); |
| 15458 | DIP("xxsldwi v%d,v%d,v%d,%d\n", (UInt)XT, (UInt)XA, (UInt)XB, (UInt)SHW); |
| 15459 | putVSReg( XT, mkexpr(result) ); |
| 15460 | break; |
| 15461 | } |
| 15462 | case 0x28: // xpermdi (VSX Permute Doubleword Immediate) |
| 15463 | { |
| 15464 | UChar DM = ifieldDM ( theInstr ); |
| 15465 | IRTemp hi = newTemp(Ity_I64); |
| 15466 | IRTemp lo = newTemp(Ity_I64); |
| 15467 | |
| 15468 | if (DM & 0x2) |
| 15469 | assign( hi, unop(Iop_V128to64, mkexpr(vA)) ); |
| 15470 | else |
| 15471 | assign( hi, unop(Iop_V128HIto64, mkexpr(vA)) ); |
| 15472 | |
| 15473 | if (DM & 0x1) |
| 15474 | assign( lo, unop(Iop_V128to64, mkexpr(vB)) ); |
| 15475 | else |
| 15476 | assign( lo, unop(Iop_V128HIto64, mkexpr(vB)) ); |
| 15477 | |
| 15478 | assign( vT, binop(Iop_64HLtoV128, mkexpr(hi), mkexpr(lo)) ); |
| 15479 | |
| 15480 | DIP("xxpermdi v%d,v%d,v%d,0x%x\n", (UInt)XT, (UInt)XA, (UInt)XB, (UInt)DM); |
| 15481 | putVSReg( XT, mkexpr( vT ) ); |
| 15482 | break; |
| 15483 | } |
| 15484 | case 0x48: // xxmrghw (VSX Merge High Word) |
| 15485 | case 0xc8: // xxmrglw (VSX Merge Low Word) |
| 15486 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 15487 | const HChar type = (opc2 == 0x48) ? 'h' : 'l'; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15488 | IROp word_op = (opc2 == 0x48) ? Iop_V128HIto64 : Iop_V128to64; |
| 15489 | IRTemp a64 = newTemp(Ity_I64); |
| 15490 | IRTemp ahi32 = newTemp(Ity_I32); |
| 15491 | IRTemp alo32 = newTemp(Ity_I32); |
| 15492 | IRTemp b64 = newTemp(Ity_I64); |
| 15493 | IRTemp bhi32 = newTemp(Ity_I32); |
| 15494 | IRTemp blo32 = newTemp(Ity_I32); |
| 15495 | |
| 15496 | assign( a64, unop(word_op, mkexpr(vA)) ); |
| 15497 | assign( ahi32, unop(Iop_64HIto32, mkexpr(a64)) ); |
| 15498 | assign( alo32, unop(Iop_64to32, mkexpr(a64)) ); |
| 15499 | |
| 15500 | assign( b64, unop(word_op, mkexpr(vB)) ); |
| 15501 | assign( bhi32, unop(Iop_64HIto32, mkexpr(b64)) ); |
| 15502 | assign( blo32, unop(Iop_64to32, mkexpr(b64)) ); |
| 15503 | |
| 15504 | assign( vT, binop(Iop_64HLtoV128, |
| 15505 | binop(Iop_32HLto64, mkexpr(ahi32), mkexpr(bhi32)), |
| 15506 | binop(Iop_32HLto64, mkexpr(alo32), mkexpr(blo32))) ); |
| 15507 | |
| 15508 | DIP("xxmrg%cw v%d,v%d,v%d\n", type, (UInt)XT, (UInt)XA, (UInt)XB); |
| 15509 | putVSReg( XT, mkexpr( vT ) ); |
| 15510 | break; |
| 15511 | } |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15512 | case 0x018: // xxsel (VSX Select) |
| 15513 | { |
| 15514 | UChar XC = ifieldRegXC(theInstr); |
| 15515 | IRTemp vC = newTemp( Ity_V128 ); |
| 15516 | assign( vC, getVSReg( XC ) ); |
| 15517 | DIP("xxsel v%d,v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB, (UInt)XC); |
| 15518 | /* vD = (vA & ~vC) | (vB & vC) */ |
| 15519 | putVSReg( XT, binop(Iop_OrV128, |
| 15520 | binop(Iop_AndV128, mkexpr(vA), unop(Iop_NotV128, mkexpr(vC))), |
| 15521 | binop(Iop_AndV128, mkexpr(vB), mkexpr(vC))) ); |
| 15522 | break; |
| 15523 | } |
| 15524 | case 0x148: // xxspltw (VSX Splat Word) |
| 15525 | { |
| 15526 | UChar UIM = ifieldRegA(theInstr) & 3; |
| 15527 | UChar sh_uim = (3 - (UIM)) * 32; |
| 15528 | DIP("xxspltw v%d,v%d,%d\n", (UInt)XT, (UInt)XB, UIM); |
| 15529 | putVSReg( XT, |
| 15530 | unop( Iop_Dup32x4, |
| 15531 | unop( Iop_V128to32, |
| 15532 | binop( Iop_ShrV128, mkexpr( vB ), mkU8( sh_uim ) ) ) ) ); |
| 15533 | break; |
| 15534 | } |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15535 | |
| 15536 | default: |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 15537 | vex_printf( "dis_vx_permute_misc(ppc)(opc2)\n" ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 15538 | return False; |
| 15539 | } |
| 15540 | return True; |
| 15541 | } |
| 15542 | |
| 15543 | /* |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15544 | AltiVec Load Instructions |
| 15545 | */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 15546 | static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr ) |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15547 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 15548 | /* X-Form */ |
| 15549 | UChar opc1 = ifieldOPC(theInstr); |
| 15550 | UChar vD_addr = ifieldRegDS(theInstr); |
| 15551 | UChar rA_addr = ifieldRegA(theInstr); |
| 15552 | UChar rB_addr = ifieldRegB(theInstr); |
| 15553 | UInt opc2 = ifieldOPClo10(theInstr); |
| 15554 | UChar b0 = ifieldBIT0(theInstr); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15555 | |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 15556 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 15557 | IRTemp EA = newTemp(ty); |
| 15558 | IRTemp EA_align16 = newTemp(ty); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 15559 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15560 | if (opc1 != 0x1F || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15561 | vex_printf("dis_av_load(ppc)(instr)\n"); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15562 | return False; |
| 15563 | } |
| 15564 | |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 15565 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
| 15566 | assign( EA_align16, addr_align( mkexpr(EA), 16 ) ); |
cerion | a50fde5 | 2005-07-01 21:16:10 +0000 | [diff] [blame] | 15567 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15568 | switch (opc2) { |
| 15569 | |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15570 | case 0x006: { // lvsl (Load Vector for Shift Left, AV p123) |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 15571 | IRDirty* d; |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 15572 | UInt vD_off = vectorGuestRegOffset(vD_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15573 | IRExpr** args_be = mkIRExprVec_5( |
florian | 9041956 | 2013-08-15 20:54:52 +0000 | [diff] [blame] | 15574 | IRExpr_BBPTR(), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15575 | mkU32(vD_off), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15576 | binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)), |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 15577 | mkU32(0xF)), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15578 | mkU32(0)/*left*/, |
| 15579 | mkU32(1)/*Big Endian*/); |
| 15580 | IRExpr** args_le = mkIRExprVec_5( |
| 15581 | IRExpr_BBPTR(), |
| 15582 | mkU32(vD_off), |
| 15583 | binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)), |
| 15584 | mkU32(0xF)), |
| 15585 | mkU32(0)/*left*/, |
| 15586 | mkU32(0)/*Little Endian*/); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15587 | if (!mode64) { |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 15588 | d = unsafeIRDirty_0_N ( |
| 15589 | 0/*regparms*/, |
| 15590 | "ppc32g_dirtyhelper_LVS", |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 15591 | fnptr_to_fnentry(vbi, &ppc32g_dirtyhelper_LVS), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15592 | args_be ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15593 | } else { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15594 | if (host_endness == VexEndnessBE) |
| 15595 | d = unsafeIRDirty_0_N ( |
| 15596 | 0/*regparms*/, |
| 15597 | "ppc64g_dirtyhelper_LVS", |
| 15598 | fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS), |
| 15599 | args_be ); |
| 15600 | else |
| 15601 | d = unsafeIRDirty_0_N ( |
| 15602 | 0/*regparms*/, |
| 15603 | "ppc64g_dirtyhelper_LVS", |
| 15604 | &ppc64g_dirtyhelper_LVS, |
| 15605 | args_le ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15606 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15607 | DIP("lvsl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15608 | /* declare guest state effects */ |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15609 | d->nFxState = 1; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 15610 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15611 | d->fxState[0].fx = Ifx_Write; |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 15612 | d->fxState[0].offset = vD_off; |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15613 | d->fxState[0].size = sizeof(U128); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15614 | |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15615 | /* execute the dirty call, side-effecting guest state */ |
| 15616 | stmt( IRStmt_Dirty(d) ); |
| 15617 | break; |
| 15618 | } |
| 15619 | case 0x026: { // lvsr (Load Vector for Shift Right, AV p125) |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 15620 | IRDirty* d; |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 15621 | UInt vD_off = vectorGuestRegOffset(vD_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15622 | IRExpr** args_be = mkIRExprVec_5( |
| 15623 | IRExpr_BBPTR(), |
| 15624 | mkU32(vD_off), |
| 15625 | binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)), |
| 15626 | mkU32(0xF)), |
| 15627 | mkU32(1)/*right*/, |
| 15628 | mkU32(1)/*Big Endian*/); |
| 15629 | IRExpr** args_le = mkIRExprVec_5( |
| 15630 | IRExpr_BBPTR(), |
| 15631 | mkU32(vD_off), |
| 15632 | binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)), |
| 15633 | mkU32(0xF)), |
| 15634 | mkU32(1)/*right*/, |
| 15635 | mkU32(0)/*Little Endian*/); |
| 15636 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15637 | if (!mode64) { |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 15638 | d = unsafeIRDirty_0_N ( |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15639 | 0/*regparms*/, |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 15640 | "ppc32g_dirtyhelper_LVS", |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 15641 | fnptr_to_fnentry(vbi, &ppc32g_dirtyhelper_LVS), |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15642 | args_be ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15643 | } else { |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15644 | if (host_endness == VexEndnessBE) |
| 15645 | d = unsafeIRDirty_0_N ( |
| 15646 | 0/*regparms*/, |
| 15647 | "ppc64g_dirtyhelper_LVS", |
| 15648 | fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS), |
| 15649 | args_be ); |
| 15650 | else |
| 15651 | d = unsafeIRDirty_0_N ( |
| 15652 | 0/*regparms*/, |
| 15653 | "ppc64g_dirtyhelper_LVS", |
| 15654 | &ppc64g_dirtyhelper_LVS, |
| 15655 | args_le ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15656 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15657 | DIP("lvsr v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15658 | /* declare guest state effects */ |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15659 | d->nFxState = 1; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 15660 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15661 | d->fxState[0].fx = Ifx_Write; |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 15662 | d->fxState[0].offset = vD_off; |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15663 | d->fxState[0].size = sizeof(U128); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15664 | |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 15665 | /* execute the dirty call, side-effecting guest state */ |
| 15666 | stmt( IRStmt_Dirty(d) ); |
| 15667 | break; |
| 15668 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15669 | case 0x007: // lvebx (Load Vector Element Byte Indexed, AV p119) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15670 | DIP("lvebx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15671 | /* loads addressed byte into vector[EA[0:3] |
| 15672 | since all other destination bytes are undefined, |
| 15673 | can simply load entire vector from 16-aligned EA */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15674 | putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15675 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15676 | |
| 15677 | case 0x027: // lvehx (Load Vector Element Half Word Indexed, AV p121) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15678 | DIP("lvehx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15679 | /* see note for lvebx */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15680 | putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15681 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15682 | |
| 15683 | case 0x047: // lvewx (Load Vector Element Word Indexed, AV p122) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15684 | DIP("lvewx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15685 | /* see note for lvebx */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15686 | putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15687 | break; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15688 | |
| 15689 | case 0x067: // lvx (Load Vector Indexed, AV p127) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15690 | DIP("lvx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15691 | putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); |
cerion | a50fde5 | 2005-07-01 21:16:10 +0000 | [diff] [blame] | 15692 | break; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15693 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15694 | case 0x167: // lvxl (Load Vector Indexed LRU, AV p128) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15695 | DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15696 | putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); |
sewardj | d2fd864 | 2006-12-27 21:21:14 +0000 | [diff] [blame] | 15697 | break; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15698 | |
| 15699 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15700 | vex_printf("dis_av_load(ppc)(opc2)\n"); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15701 | return False; |
| 15702 | } |
| 15703 | return True; |
| 15704 | } |
| 15705 | |
| 15706 | /* |
| 15707 | AltiVec Store Instructions |
| 15708 | */ |
| 15709 | static Bool dis_av_store ( UInt theInstr ) |
| 15710 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 15711 | /* X-Form */ |
| 15712 | UChar opc1 = ifieldOPC(theInstr); |
| 15713 | UChar vS_addr = ifieldRegDS(theInstr); |
| 15714 | UChar rA_addr = ifieldRegA(theInstr); |
| 15715 | UChar rB_addr = ifieldRegB(theInstr); |
| 15716 | UInt opc2 = ifieldOPClo10(theInstr); |
| 15717 | UChar b0 = ifieldBIT0(theInstr); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15718 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 15719 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 15720 | IRTemp EA = newTemp(ty); |
cerion | dba87e2 | 2006-01-02 15:15:45 +0000 | [diff] [blame] | 15721 | IRTemp addr_aligned = newTemp(ty); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 15722 | IRTemp vS = newTemp(Ity_V128); |
| 15723 | IRTemp eb = newTemp(Ity_I8); |
| 15724 | IRTemp idx = newTemp(Ity_I8); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15725 | |
| 15726 | if (opc1 != 0x1F || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15727 | vex_printf("dis_av_store(ppc)(instr)\n"); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15728 | return False; |
| 15729 | } |
| 15730 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15731 | assign( vS, getVReg(vS_addr)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 15732 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15733 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15734 | switch (opc2) { |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15735 | case 0x087: { // stvebx (Store Vector Byte Indexed, AV p131) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15736 | DIP("stvebx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15737 | assign( eb, binop(Iop_And8, mkU8(0xF), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 15738 | unop(Iop_32to8, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15739 | mkNarrowTo32(ty, mkexpr(EA)) )) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15740 | if (host_endness == VexEndnessLE) { |
| 15741 | assign( idx, binop(Iop_Shl8, mkexpr(eb), mkU8(3)) ); |
| 15742 | } else { |
| 15743 | assign( idx, binop(Iop_Shl8, |
| 15744 | binop(Iop_Sub8, mkU8(15), mkexpr(eb)), |
| 15745 | mkU8(3)) ); |
| 15746 | } |
| 15747 | store( mkexpr(EA), |
| 15748 | unop( Iop_32to8, unop(Iop_V128to32, |
| 15749 | binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15750 | break; |
| 15751 | } |
| 15752 | case 0x0A7: { // stvehx (Store Vector Half Word Indexed, AV p132) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15753 | DIP("stvehx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
cerion | dba87e2 | 2006-01-02 15:15:45 +0000 | [diff] [blame] | 15754 | assign( addr_aligned, addr_align(mkexpr(EA), 2) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15755 | assign( eb, binop(Iop_And8, mkU8(0xF), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15756 | mkNarrowTo8(ty, mkexpr(addr_aligned) )) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15757 | if (host_endness == VexEndnessLE) { |
| 15758 | assign( idx, binop(Iop_Shl8, mkexpr(eb), mkU8(3)) ); |
| 15759 | } else { |
| 15760 | assign( idx, binop(Iop_Shl8, |
| 15761 | binop(Iop_Sub8, mkU8(14), mkexpr(eb)), |
| 15762 | mkU8(3)) ); |
| 15763 | } |
| 15764 | store( mkexpr(addr_aligned), |
| 15765 | unop( Iop_32to16, unop(Iop_V128to32, |
| 15766 | binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15767 | break; |
| 15768 | } |
| 15769 | case 0x0C7: { // stvewx (Store Vector Word Indexed, AV p133) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15770 | DIP("stvewx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
cerion | dba87e2 | 2006-01-02 15:15:45 +0000 | [diff] [blame] | 15771 | assign( addr_aligned, addr_align(mkexpr(EA), 4) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15772 | assign( eb, binop(Iop_And8, mkU8(0xF), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15773 | mkNarrowTo8(ty, mkexpr(addr_aligned) )) ); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15774 | if (host_endness == VexEndnessLE) { |
| 15775 | assign( idx, binop(Iop_Shl8, mkexpr(eb), mkU8(3)) ); |
| 15776 | } else { |
| 15777 | assign( idx, binop(Iop_Shl8, |
| 15778 | binop(Iop_Sub8, mkU8(12), mkexpr(eb)), |
| 15779 | mkU8(3)) ); |
| 15780 | } |
| 15781 | store( mkexpr( addr_aligned), |
| 15782 | unop( Iop_V128to32, |
| 15783 | binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx))) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 15784 | break; |
| 15785 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15786 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15787 | case 0x0E7: // stvx (Store Vector Indexed, AV p134) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15788 | DIP("stvx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15789 | store( addr_align( mkexpr(EA), 16 ), mkexpr(vS) ); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15790 | break; |
| 15791 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15792 | case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 15793 | DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 15794 | store( addr_align( mkexpr(EA), 16 ), mkexpr(vS) ); |
sewardj | d2fd864 | 2006-12-27 21:21:14 +0000 | [diff] [blame] | 15795 | break; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15796 | |
| 15797 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15798 | vex_printf("dis_av_store(ppc)(opc2)\n"); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 15799 | return False; |
| 15800 | } |
| 15801 | return True; |
| 15802 | } |
| 15803 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15804 | /* |
| 15805 | AltiVec Arithmetic Instructions |
| 15806 | */ |
| 15807 | static Bool dis_av_arith ( UInt theInstr ) |
| 15808 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 15809 | /* VX-Form */ |
| 15810 | UChar opc1 = ifieldOPC(theInstr); |
| 15811 | UChar vD_addr = ifieldRegDS(theInstr); |
| 15812 | UChar vA_addr = ifieldRegA(theInstr); |
| 15813 | UChar vB_addr = ifieldRegB(theInstr); |
| 15814 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15815 | |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 15816 | IRTemp vA = newTemp(Ity_V128); |
| 15817 | IRTemp vB = newTemp(Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 15818 | IRTemp z3 = newTemp(Ity_I64); |
| 15819 | IRTemp z2 = newTemp(Ity_I64); |
| 15820 | IRTemp z1 = newTemp(Ity_I64); |
| 15821 | IRTemp z0 = newTemp(Ity_I64); |
| 15822 | IRTemp aEvn, aOdd; |
| 15823 | IRTemp a15, a14, a13, a12, a11, a10, a9, a8; |
| 15824 | IRTemp a7, a6, a5, a4, a3, a2, a1, a0; |
| 15825 | IRTemp b3, b2, b1, b0; |
| 15826 | |
| 15827 | aEvn = aOdd = IRTemp_INVALID; |
| 15828 | a15 = a14 = a13 = a12 = a11 = a10 = a9 = a8 = IRTemp_INVALID; |
| 15829 | a7 = a6 = a5 = a4 = a3 = a2 = a1 = a0 = IRTemp_INVALID; |
| 15830 | b3 = b2 = b1 = b0 = IRTemp_INVALID; |
| 15831 | |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 15832 | assign( vA, getVReg(vA_addr)); |
| 15833 | assign( vB, getVReg(vB_addr)); |
| 15834 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15835 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15836 | vex_printf("dis_av_arith(ppc)(opc1 != 0x4)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15837 | return False; |
| 15838 | } |
| 15839 | |
| 15840 | switch (opc2) { |
| 15841 | /* Add */ |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 15842 | case 0x180: { // vaddcuw (Add Carryout Unsigned Word, AV p136) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15843 | DIP("vaddcuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15844 | /* unsigned_ov(x+y) = (y >u not(x)) */ |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 15845 | putVReg( vD_addr, binop(Iop_ShrN32x4, |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15846 | binop(Iop_CmpGT32Ux4, mkexpr(vB), |
| 15847 | unop(Iop_NotV128, mkexpr(vA))), |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 15848 | mkU8(31)) ); |
| 15849 | break; |
| 15850 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15851 | case 0x000: // vaddubm (Add Unsigned Byte Modulo, AV p141) |
| 15852 | DIP("vaddubm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15853 | putVReg( vD_addr, binop(Iop_Add8x16, mkexpr(vA), mkexpr(vB)) ); |
| 15854 | break; |
| 15855 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15856 | case 0x040: // vadduhm (Add Unsigned Half Word Modulo, AV p143) |
| 15857 | DIP("vadduhm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15858 | putVReg( vD_addr, binop(Iop_Add16x8, mkexpr(vA), mkexpr(vB)) ); |
| 15859 | break; |
| 15860 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15861 | case 0x080: // vadduwm (Add Unsigned Word Modulo, AV p145) |
| 15862 | DIP("vadduwm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15863 | putVReg( vD_addr, binop(Iop_Add32x4, mkexpr(vA), mkexpr(vB)) ); |
| 15864 | break; |
| 15865 | |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 15866 | case 0x0C0: // vaddudm (Add Unsigned Double Word Modulo) |
| 15867 | DIP("vaddudm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 15868 | putVReg( vD_addr, binop(Iop_Add64x2, mkexpr(vA), mkexpr(vB)) ); |
| 15869 | break; |
| 15870 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15871 | case 0x200: // vaddubs (Add Unsigned Byte Saturate, AV p142) |
| 15872 | DIP("vaddubs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15873 | putVReg( vD_addr, binop(Iop_QAdd8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 15874 | // TODO: set VSCR[SAT], perhaps via new primop: Iop_SatOfQAdd8Ux16 |
| 15875 | break; |
| 15876 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15877 | case 0x240: // vadduhs (Add Unsigned Half Word Saturate, AV p144) |
| 15878 | DIP("vadduhs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15879 | putVReg( vD_addr, binop(Iop_QAdd16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 15880 | // TODO: set VSCR[SAT] |
| 15881 | break; |
| 15882 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15883 | case 0x280: // vadduws (Add Unsigned Word Saturate, AV p146) |
| 15884 | DIP("vadduws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15885 | putVReg( vD_addr, binop(Iop_QAdd32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 15886 | // TODO: set VSCR[SAT] |
| 15887 | break; |
| 15888 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15889 | case 0x300: // vaddsbs (Add Signed Byte Saturate, AV p138) |
| 15890 | DIP("vaddsbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15891 | putVReg( vD_addr, binop(Iop_QAdd8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 15892 | // TODO: set VSCR[SAT] |
| 15893 | break; |
| 15894 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15895 | case 0x340: // vaddshs (Add Signed Half Word Saturate, AV p139) |
| 15896 | DIP("vaddshs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15897 | putVReg( vD_addr, binop(Iop_QAdd16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 15898 | // TODO: set VSCR[SAT] |
| 15899 | break; |
| 15900 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15901 | case 0x380: // vaddsws (Add Signed Word Saturate, AV p140) |
| 15902 | DIP("vaddsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15903 | putVReg( vD_addr, binop(Iop_QAdd32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 15904 | // TODO: set VSCR[SAT] |
| 15905 | break; |
| 15906 | |
| 15907 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15908 | /* Subtract */ |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15909 | case 0x580: { // vsubcuw (Subtract Carryout Unsigned Word, AV p260) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15910 | DIP("vsubcuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15911 | /* unsigned_ov(x-y) = (y >u x) */ |
| 15912 | putVReg( vD_addr, binop(Iop_ShrN32x4, |
| 15913 | unop(Iop_NotV128, |
| 15914 | binop(Iop_CmpGT32Ux4, mkexpr(vB), |
| 15915 | mkexpr(vA))), |
| 15916 | mkU8(31)) ); |
| 15917 | break; |
| 15918 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15919 | case 0x400: // vsububm (Subtract Unsigned Byte Modulo, AV p265) |
| 15920 | DIP("vsububm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15921 | putVReg( vD_addr, binop(Iop_Sub8x16, mkexpr(vA), mkexpr(vB)) ); |
| 15922 | break; |
| 15923 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15924 | case 0x440: // vsubuhm (Subtract Unsigned Half Word Modulo, AV p267) |
| 15925 | DIP("vsubuhm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15926 | putVReg( vD_addr, binop(Iop_Sub16x8, mkexpr(vA), mkexpr(vB)) ); |
| 15927 | break; |
| 15928 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15929 | case 0x480: // vsubuwm (Subtract Unsigned Word Modulo, AV p269) |
| 15930 | DIP("vsubuwm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15931 | putVReg( vD_addr, binop(Iop_Sub32x4, mkexpr(vA), mkexpr(vB)) ); |
| 15932 | break; |
| 15933 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 15934 | case 0x4C0: // vsubudm (Subtract Unsigned Double Word Modulo) |
| 15935 | DIP("vsubudm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 15936 | putVReg( vD_addr, binop(Iop_Sub64x2, mkexpr(vA), mkexpr(vB)) ); |
| 15937 | break; |
| 15938 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15939 | case 0x600: // vsububs (Subtract Unsigned Byte Saturate, AV p266) |
| 15940 | DIP("vsububs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15941 | putVReg( vD_addr, binop(Iop_QSub8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 15942 | // TODO: set VSCR[SAT] |
| 15943 | break; |
| 15944 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 15945 | case 0x640: // vsubuhs (Subtract Unsigned HWord Saturate, AV p268) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15946 | DIP("vsubuhs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15947 | putVReg( vD_addr, binop(Iop_QSub16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 15948 | // TODO: set VSCR[SAT] |
| 15949 | break; |
| 15950 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15951 | case 0x680: // vsubuws (Subtract Unsigned Word Saturate, AV p270) |
| 15952 | DIP("vsubuws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15953 | putVReg( vD_addr, binop(Iop_QSub32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 15954 | // TODO: set VSCR[SAT] |
| 15955 | break; |
| 15956 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15957 | case 0x700: // vsubsbs (Subtract Signed Byte Saturate, AV p262) |
| 15958 | DIP("vsubsbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15959 | putVReg( vD_addr, binop(Iop_QSub8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 15960 | // TODO: set VSCR[SAT] |
| 15961 | break; |
| 15962 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15963 | case 0x740: // vsubshs (Subtract Signed Half Word Saturate, AV p263) |
| 15964 | DIP("vsubshs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15965 | putVReg( vD_addr, binop(Iop_QSub16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 15966 | // TODO: set VSCR[SAT] |
| 15967 | break; |
| 15968 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15969 | case 0x780: // vsubsws (Subtract Signed Word Saturate, AV p264) |
| 15970 | DIP("vsubsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15971 | putVReg( vD_addr, binop(Iop_QSub32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 15972 | // TODO: set VSCR[SAT] |
| 15973 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15974 | |
| 15975 | |
| 15976 | /* Maximum */ |
| 15977 | case 0x002: // vmaxub (Maximum Unsigned Byte, AV p182) |
| 15978 | DIP("vmaxub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15979 | putVReg( vD_addr, binop(Iop_Max8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 15980 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15981 | |
| 15982 | case 0x042: // vmaxuh (Maximum Unsigned Half Word, AV p183) |
| 15983 | DIP("vmaxuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15984 | putVReg( vD_addr, binop(Iop_Max16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 15985 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15986 | |
| 15987 | case 0x082: // vmaxuw (Maximum Unsigned Word, AV p184) |
| 15988 | DIP("vmaxuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15989 | putVReg( vD_addr, binop(Iop_Max32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 15990 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15991 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 15992 | case 0x0C2: // vmaxud (Maximum Unsigned Double word) |
| 15993 | DIP("vmaxud v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 15994 | putVReg( vD_addr, binop(Iop_Max64Ux2, mkexpr(vA), mkexpr(vB)) ); |
| 15995 | break; |
| 15996 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 15997 | case 0x102: // vmaxsb (Maximum Signed Byte, AV p179) |
| 15998 | DIP("vmaxsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 15999 | putVReg( vD_addr, binop(Iop_Max8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 16000 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16001 | |
| 16002 | case 0x142: // vmaxsh (Maximum Signed Half Word, AV p180) |
| 16003 | DIP("vmaxsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16004 | putVReg( vD_addr, binop(Iop_Max16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 16005 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16006 | |
| 16007 | case 0x182: // vmaxsw (Maximum Signed Word, AV p181) |
| 16008 | DIP("vmaxsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16009 | putVReg( vD_addr, binop(Iop_Max32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 16010 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16011 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16012 | case 0x1C2: // vmaxsd (Maximum Signed Double word) |
| 16013 | DIP("vmaxsd v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16014 | putVReg( vD_addr, binop(Iop_Max64Sx2, mkexpr(vA), mkexpr(vB)) ); |
| 16015 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16016 | |
| 16017 | /* Minimum */ |
| 16018 | case 0x202: // vminub (Minimum Unsigned Byte, AV p191) |
| 16019 | DIP("vminub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16020 | putVReg( vD_addr, binop(Iop_Min8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 16021 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16022 | |
| 16023 | case 0x242: // vminuh (Minimum Unsigned Half Word, AV p192) |
| 16024 | DIP("vminuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16025 | putVReg( vD_addr, binop(Iop_Min16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 16026 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16027 | |
| 16028 | case 0x282: // vminuw (Minimum Unsigned Word, AV p193) |
| 16029 | DIP("vminuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16030 | putVReg( vD_addr, binop(Iop_Min32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 16031 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16032 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16033 | case 0x2C2: // vminud (Minimum Unsigned Double Word) |
| 16034 | DIP("vminud v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16035 | putVReg( vD_addr, binop(Iop_Min64Ux2, mkexpr(vA), mkexpr(vB)) ); |
| 16036 | break; |
| 16037 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16038 | case 0x302: // vminsb (Minimum Signed Byte, AV p188) |
| 16039 | DIP("vminsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16040 | putVReg( vD_addr, binop(Iop_Min8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 16041 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16042 | |
| 16043 | case 0x342: // vminsh (Minimum Signed Half Word, AV p189) |
| 16044 | DIP("vminsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16045 | putVReg( vD_addr, binop(Iop_Min16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 16046 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16047 | |
| 16048 | case 0x382: // vminsw (Minimum Signed Word, AV p190) |
| 16049 | DIP("vminsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16050 | putVReg( vD_addr, binop(Iop_Min32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 16051 | break; |
| 16052 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16053 | case 0x3C2: // vminsd (Minimum Signed Double Word) |
| 16054 | DIP("vminsd v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16055 | putVReg( vD_addr, binop(Iop_Min64Sx2, mkexpr(vA), mkexpr(vB)) ); |
| 16056 | break; |
| 16057 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16058 | |
| 16059 | /* Average */ |
| 16060 | case 0x402: // vavgub (Average Unsigned Byte, AV p152) |
| 16061 | DIP("vavgub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16062 | putVReg( vD_addr, binop(Iop_Avg8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 16063 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16064 | |
| 16065 | case 0x442: // vavguh (Average Unsigned Half Word, AV p153) |
| 16066 | DIP("vavguh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16067 | putVReg( vD_addr, binop(Iop_Avg16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 16068 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16069 | |
| 16070 | case 0x482: // vavguw (Average Unsigned Word, AV p154) |
| 16071 | DIP("vavguw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16072 | putVReg( vD_addr, binop(Iop_Avg32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 16073 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16074 | |
| 16075 | case 0x502: // vavgsb (Average Signed Byte, AV p149) |
| 16076 | DIP("vavgsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16077 | putVReg( vD_addr, binop(Iop_Avg8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 16078 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16079 | |
| 16080 | case 0x542: // vavgsh (Average Signed Half Word, AV p150) |
| 16081 | DIP("vavgsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16082 | putVReg( vD_addr, binop(Iop_Avg16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 16083 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16084 | |
| 16085 | case 0x582: // vavgsw (Average Signed Word, AV p151) |
| 16086 | DIP("vavgsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16087 | putVReg( vD_addr, binop(Iop_Avg32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 16088 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16089 | |
| 16090 | |
| 16091 | /* Multiply */ |
| 16092 | case 0x008: // vmuloub (Multiply Odd Unsigned Byte, AV p213) |
| 16093 | DIP("vmuloub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16094 | putVReg( vD_addr, |
| 16095 | binop(Iop_MullEven8Ux16, mkexpr(vA), mkexpr(vB))); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16096 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16097 | |
| 16098 | case 0x048: // vmulouh (Multiply Odd Unsigned Half Word, AV p214) |
| 16099 | DIP("vmulouh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16100 | putVReg( vD_addr, |
| 16101 | binop(Iop_MullEven16Ux8, mkexpr(vA), mkexpr(vB))); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16102 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16103 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16104 | case 0x088: // vmulouw (Multiply Odd Unsigned Word) |
| 16105 | DIP("vmulouw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16106 | putVReg( vD_addr, binop( Iop_MullEven32Ux4, mkexpr(vA), mkexpr(vB) ) ); |
| 16107 | break; |
| 16108 | |
| 16109 | case 0x089: // vmuluwm (Multiply Unsigned Word Modulo) |
| 16110 | DIP("vmuluwm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16111 | putVReg( vD_addr, binop( Iop_Mul32x4, mkexpr(vA), mkexpr(vB) ) ); |
| 16112 | break; |
| 16113 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16114 | case 0x108: // vmulosb (Multiply Odd Signed Byte, AV p211) |
| 16115 | DIP("vmulosb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16116 | putVReg( vD_addr, |
| 16117 | binop(Iop_MullEven8Sx16, mkexpr(vA), mkexpr(vB))); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16118 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16119 | |
| 16120 | case 0x148: // vmulosh (Multiply Odd Signed Half Word, AV p212) |
| 16121 | DIP("vmulosh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16122 | putVReg( vD_addr, |
| 16123 | binop(Iop_MullEven16Sx8, mkexpr(vA), mkexpr(vB))); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16124 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16125 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16126 | case 0x188: // vmulosw (Multiply Odd Signed Word) |
| 16127 | DIP("vmulosw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16128 | putVReg( vD_addr, binop( Iop_MullEven32Sx4, mkexpr(vA), mkexpr(vB) ) ); |
| 16129 | break; |
| 16130 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16131 | case 0x208: // vmuleub (Multiply Even Unsigned Byte, AV p209) |
| 16132 | DIP("vmuleub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16133 | putVReg( vD_addr, MK_Iop_MullOdd8Ux16( mkexpr(vA), mkexpr(vB) )); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16134 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16135 | |
| 16136 | case 0x248: // vmuleuh (Multiply Even Unsigned Half Word, AV p210) |
| 16137 | DIP("vmuleuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16138 | putVReg( vD_addr, MK_Iop_MullOdd16Ux8( mkexpr(vA), mkexpr(vB) )); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16139 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16140 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16141 | case 0x288: // vmuleuw (Multiply Even Unsigned Word) |
| 16142 | DIP("vmuleuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16143 | putVReg( vD_addr, MK_Iop_MullOdd32Ux4( mkexpr(vA), mkexpr(vB) ) ); |
| 16144 | break; |
| 16145 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16146 | case 0x308: // vmulesb (Multiply Even Signed Byte, AV p207) |
| 16147 | DIP("vmulesb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16148 | putVReg( vD_addr, MK_Iop_MullOdd8Sx16( mkexpr(vA), mkexpr(vB) )); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16149 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16150 | |
| 16151 | case 0x348: // vmulesh (Multiply Even Signed Half Word, AV p208) |
| 16152 | DIP("vmulesh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16153 | putVReg( vD_addr, MK_Iop_MullOdd16Sx8( mkexpr(vA), mkexpr(vB) )); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 16154 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16155 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16156 | case 0x388: // vmulesw (Multiply Even Signed Word) |
| 16157 | DIP("vmulesw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16158 | putVReg( vD_addr, MK_Iop_MullOdd32Sx4( mkexpr(vA), mkexpr(vB) ) ); |
| 16159 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16160 | |
| 16161 | /* Sum Across Partial */ |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16162 | case 0x608: { // vsum4ubs (Sum Partial (1/4) UB Saturate, AV p275) |
| 16163 | IRTemp aEE, aEO, aOE, aOO; |
| 16164 | aEE = aEO = aOE = aOO = IRTemp_INVALID; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16165 | DIP("vsum4ubs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16166 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16167 | /* vA: V128_8Ux16 -> 4 x V128_32Ux4, sign-extended */ |
| 16168 | expand8Ux16( mkexpr(vA), &aEvn, &aOdd ); // (15,13...),(14,12...) |
| 16169 | expand16Ux8( mkexpr(aEvn), &aEE, &aEO ); // (15,11...),(13, 9...) |
| 16170 | expand16Ux8( mkexpr(aOdd), &aOE, &aOO ); // (14,10...),(12, 8...) |
| 16171 | |
| 16172 | /* break V128 to 4xI32's, zero-extending to I64's */ |
| 16173 | breakV128to4x64U( mkexpr(aEE), &a15, &a11, &a7, &a3 ); |
| 16174 | breakV128to4x64U( mkexpr(aOE), &a14, &a10, &a6, &a2 ); |
| 16175 | breakV128to4x64U( mkexpr(aEO), &a13, &a9, &a5, &a1 ); |
| 16176 | breakV128to4x64U( mkexpr(aOO), &a12, &a8, &a4, &a0 ); |
| 16177 | breakV128to4x64U( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 16178 | |
| 16179 | /* add lanes */ |
| 16180 | assign( z3, binop(Iop_Add64, mkexpr(b3), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16181 | binop(Iop_Add64, |
| 16182 | binop(Iop_Add64, mkexpr(a15), mkexpr(a14)), |
| 16183 | binop(Iop_Add64, mkexpr(a13), mkexpr(a12)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16184 | assign( z2, binop(Iop_Add64, mkexpr(b2), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16185 | binop(Iop_Add64, |
| 16186 | binop(Iop_Add64, mkexpr(a11), mkexpr(a10)), |
| 16187 | binop(Iop_Add64, mkexpr(a9), mkexpr(a8)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16188 | assign( z1, binop(Iop_Add64, mkexpr(b1), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16189 | binop(Iop_Add64, |
| 16190 | binop(Iop_Add64, mkexpr(a7), mkexpr(a6)), |
| 16191 | binop(Iop_Add64, mkexpr(a5), mkexpr(a4)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16192 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16193 | binop(Iop_Add64, |
| 16194 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2)), |
| 16195 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16196 | |
| 16197 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 16198 | putVReg( vD_addr, mkV128from4x64U( mkexpr(z3), mkexpr(z2), |
| 16199 | mkexpr(z1), mkexpr(z0)) ); |
| 16200 | break; |
| 16201 | } |
| 16202 | case 0x708: { // vsum4sbs (Sum Partial (1/4) SB Saturate, AV p273) |
| 16203 | IRTemp aEE, aEO, aOE, aOO; |
| 16204 | aEE = aEO = aOE = aOO = IRTemp_INVALID; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16205 | DIP("vsum4sbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16206 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16207 | /* vA: V128_8Sx16 -> 4 x V128_32Sx4, sign-extended */ |
| 16208 | expand8Sx16( mkexpr(vA), &aEvn, &aOdd ); // (15,13...),(14,12...) |
| 16209 | expand16Sx8( mkexpr(aEvn), &aEE, &aEO ); // (15,11...),(13, 9...) |
| 16210 | expand16Sx8( mkexpr(aOdd), &aOE, &aOO ); // (14,10...),(12, 8...) |
| 16211 | |
| 16212 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 16213 | breakV128to4x64S( mkexpr(aEE), &a15, &a11, &a7, &a3 ); |
| 16214 | breakV128to4x64S( mkexpr(aOE), &a14, &a10, &a6, &a2 ); |
| 16215 | breakV128to4x64S( mkexpr(aEO), &a13, &a9, &a5, &a1 ); |
| 16216 | breakV128to4x64S( mkexpr(aOO), &a12, &a8, &a4, &a0 ); |
| 16217 | breakV128to4x64S( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 16218 | |
| 16219 | /* add lanes */ |
| 16220 | assign( z3, binop(Iop_Add64, mkexpr(b3), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16221 | binop(Iop_Add64, |
| 16222 | binop(Iop_Add64, mkexpr(a15), mkexpr(a14)), |
| 16223 | binop(Iop_Add64, mkexpr(a13), mkexpr(a12)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16224 | assign( z2, binop(Iop_Add64, mkexpr(b2), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16225 | binop(Iop_Add64, |
| 16226 | binop(Iop_Add64, mkexpr(a11), mkexpr(a10)), |
| 16227 | binop(Iop_Add64, mkexpr(a9), mkexpr(a8)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16228 | assign( z1, binop(Iop_Add64, mkexpr(b1), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16229 | binop(Iop_Add64, |
| 16230 | binop(Iop_Add64, mkexpr(a7), mkexpr(a6)), |
| 16231 | binop(Iop_Add64, mkexpr(a5), mkexpr(a4)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16232 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16233 | binop(Iop_Add64, |
| 16234 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2)), |
| 16235 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16236 | |
| 16237 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 16238 | putVReg( vD_addr, mkV128from4x64S( mkexpr(z3), mkexpr(z2), |
| 16239 | mkexpr(z1), mkexpr(z0)) ); |
| 16240 | break; |
| 16241 | } |
| 16242 | case 0x648: { // vsum4shs (Sum Partial (1/4) SHW Saturate, AV p274) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16243 | DIP("vsum4shs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16244 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16245 | /* vA: V128_16Sx8 -> 2 x V128_32Sx4, sign-extended */ |
| 16246 | expand16Sx8( mkexpr(vA), &aEvn, &aOdd ); // (7,5...),(6,4...) |
| 16247 | |
| 16248 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 16249 | breakV128to4x64S( mkexpr(aEvn), &a7, &a5, &a3, &a1 ); |
| 16250 | breakV128to4x64S( mkexpr(aOdd), &a6, &a4, &a2, &a0 ); |
| 16251 | breakV128to4x64S( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 16252 | |
| 16253 | /* add lanes */ |
| 16254 | assign( z3, binop(Iop_Add64, mkexpr(b3), |
| 16255 | binop(Iop_Add64, mkexpr(a7), mkexpr(a6)))); |
| 16256 | assign( z2, binop(Iop_Add64, mkexpr(b2), |
| 16257 | binop(Iop_Add64, mkexpr(a5), mkexpr(a4)))); |
| 16258 | assign( z1, binop(Iop_Add64, mkexpr(b1), |
| 16259 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2)))); |
| 16260 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
| 16261 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0)))); |
| 16262 | |
| 16263 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 16264 | putVReg( vD_addr, mkV128from4x64S( mkexpr(z3), mkexpr(z2), |
| 16265 | mkexpr(z1), mkexpr(z0)) ); |
| 16266 | break; |
| 16267 | } |
| 16268 | case 0x688: { // vsum2sws (Sum Partial (1/2) SW Saturate, AV p272) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16269 | DIP("vsum2sws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16270 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16271 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 16272 | breakV128to4x64S( mkexpr(vA), &a3, &a2, &a1, &a0 ); |
| 16273 | breakV128to4x64S( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 16274 | |
| 16275 | /* add lanes */ |
| 16276 | assign( z2, binop(Iop_Add64, mkexpr(b2), |
| 16277 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2))) ); |
| 16278 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
| 16279 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0))) ); |
| 16280 | |
| 16281 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 16282 | putVReg( vD_addr, mkV128from4x64S( mkU64(0), mkexpr(z2), |
| 16283 | mkU64(0), mkexpr(z0)) ); |
| 16284 | break; |
| 16285 | } |
| 16286 | case 0x788: { // vsumsws (Sum SW Saturate, AV p271) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16287 | DIP("vsumsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16288 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16289 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 16290 | breakV128to4x64S( mkexpr(vA), &a3, &a2, &a1, &a0 ); |
| 16291 | breakV128to4x64S( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 16292 | |
| 16293 | /* add lanes */ |
| 16294 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16295 | binop(Iop_Add64, |
| 16296 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2)), |
| 16297 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16298 | |
| 16299 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 16300 | putVReg( vD_addr, mkV128from4x64S( mkU64(0), mkU64(0), |
| 16301 | mkU64(0), mkexpr(z0)) ); |
| 16302 | break; |
| 16303 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16304 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16305 | vex_printf("dis_av_arith(ppc)(opc2=0x%x)\n", opc2); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16306 | return False; |
| 16307 | } |
| 16308 | return True; |
| 16309 | } |
| 16310 | |
| 16311 | /* |
| 16312 | AltiVec Logic Instructions |
| 16313 | */ |
| 16314 | static Bool dis_av_logic ( UInt theInstr ) |
| 16315 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 16316 | /* VX-Form */ |
| 16317 | UChar opc1 = ifieldOPC(theInstr); |
| 16318 | UChar vD_addr = ifieldRegDS(theInstr); |
| 16319 | UChar vA_addr = ifieldRegA(theInstr); |
| 16320 | UChar vB_addr = ifieldRegB(theInstr); |
| 16321 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16322 | |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 16323 | IRTemp vA = newTemp(Ity_V128); |
| 16324 | IRTemp vB = newTemp(Ity_V128); |
| 16325 | assign( vA, getVReg(vA_addr)); |
| 16326 | assign( vB, getVReg(vB_addr)); |
| 16327 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16328 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16329 | vex_printf("dis_av_logic(ppc)(opc1 != 0x4)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16330 | return False; |
| 16331 | } |
| 16332 | |
| 16333 | switch (opc2) { |
| 16334 | case 0x404: // vand (And, AV p147) |
| 16335 | DIP("vand v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 16336 | putVReg( vD_addr, binop(Iop_AndV128, mkexpr(vA), mkexpr(vB)) ); |
| 16337 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16338 | |
| 16339 | case 0x444: // vandc (And, AV p148) |
| 16340 | DIP("vandc v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 16341 | putVReg( vD_addr, binop(Iop_AndV128, mkexpr(vA), |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 16342 | unop(Iop_NotV128, mkexpr(vB))) ); |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 16343 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16344 | |
| 16345 | case 0x484: // vor (Or, AV p217) |
| 16346 | DIP("vor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 16347 | putVReg( vD_addr, binop(Iop_OrV128, mkexpr(vA), mkexpr(vB)) ); |
| 16348 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16349 | |
| 16350 | case 0x4C4: // vxor (Xor, AV p282) |
| 16351 | DIP("vxor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 16352 | putVReg( vD_addr, binop(Iop_XorV128, mkexpr(vA), mkexpr(vB)) ); |
| 16353 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16354 | |
| 16355 | case 0x504: // vnor (Nor, AV p216) |
| 16356 | DIP("vnor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 16357 | putVReg( vD_addr, |
| 16358 | unop(Iop_NotV128, binop(Iop_OrV128, mkexpr(vA), mkexpr(vB))) ); |
| 16359 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16360 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 16361 | case 0x544: // vorc (vA Or'd with complement of vb) |
| 16362 | DIP("vorc v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16363 | putVReg( vD_addr, binop( Iop_OrV128, |
| 16364 | mkexpr( vA ), |
| 16365 | unop( Iop_NotV128, mkexpr( vB ) ) ) ); |
| 16366 | break; |
| 16367 | |
| 16368 | case 0x584: // vnand (Nand) |
| 16369 | DIP("vnand v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16370 | putVReg( vD_addr, unop( Iop_NotV128, |
| 16371 | binop(Iop_AndV128, mkexpr( vA ), |
| 16372 | mkexpr( vB ) ) ) ); |
| 16373 | break; |
| 16374 | |
| 16375 | case 0x684: // veqv (complemented XOr) |
| 16376 | DIP("veqv v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16377 | putVReg( vD_addr, unop( Iop_NotV128, |
| 16378 | binop( Iop_XorV128, mkexpr( vA ), |
| 16379 | mkexpr( vB ) ) ) ); |
| 16380 | break; |
| 16381 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16382 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16383 | vex_printf("dis_av_logic(ppc)(opc2=0x%x)\n", opc2); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16384 | return False; |
| 16385 | } |
| 16386 | return True; |
| 16387 | } |
| 16388 | |
| 16389 | /* |
| 16390 | AltiVec Compare Instructions |
| 16391 | */ |
| 16392 | static Bool dis_av_cmp ( UInt theInstr ) |
| 16393 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 16394 | /* VXR-Form */ |
| 16395 | UChar opc1 = ifieldOPC(theInstr); |
| 16396 | UChar vD_addr = ifieldRegDS(theInstr); |
| 16397 | UChar vA_addr = ifieldRegA(theInstr); |
| 16398 | UChar vB_addr = ifieldRegB(theInstr); |
| 16399 | UChar flag_rC = ifieldBIT10(theInstr); |
| 16400 | UInt opc2 = IFIELD( theInstr, 0, 10 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16401 | |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16402 | IRTemp vA = newTemp(Ity_V128); |
| 16403 | IRTemp vB = newTemp(Ity_V128); |
| 16404 | IRTemp vD = newTemp(Ity_V128); |
| 16405 | assign( vA, getVReg(vA_addr)); |
| 16406 | assign( vB, getVReg(vB_addr)); |
| 16407 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16408 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16409 | vex_printf("dis_av_cmp(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16410 | return False; |
| 16411 | } |
| 16412 | |
| 16413 | switch (opc2) { |
| 16414 | case 0x006: // vcmpequb (Compare Equal-to Unsigned B, AV p160) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16415 | DIP("vcmpequb%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16416 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16417 | assign( vD, binop(Iop_CmpEQ8x16, mkexpr(vA), mkexpr(vB)) ); |
| 16418 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16419 | |
| 16420 | case 0x046: // vcmpequh (Compare Equal-to Unsigned HW, AV p161) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16421 | DIP("vcmpequh%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16422 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16423 | assign( vD, binop(Iop_CmpEQ16x8, mkexpr(vA), mkexpr(vB)) ); |
| 16424 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16425 | |
| 16426 | case 0x086: // vcmpequw (Compare Equal-to Unsigned W, AV p162) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16427 | DIP("vcmpequw%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16428 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16429 | assign( vD, binop(Iop_CmpEQ32x4, mkexpr(vA), mkexpr(vB)) ); |
| 16430 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16431 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16432 | case 0x0C7: // vcmpequd (Compare Equal-to Unsigned Doubleword) |
| 16433 | DIP("vcmpequd%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16434 | vD_addr, vA_addr, vB_addr); |
| 16435 | assign( vD, binop(Iop_CmpEQ64x2, mkexpr(vA), mkexpr(vB)) ); |
| 16436 | break; |
| 16437 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16438 | case 0x206: // vcmpgtub (Compare Greater-than Unsigned B, AV p168) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16439 | DIP("vcmpgtub%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16440 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16441 | assign( vD, binop(Iop_CmpGT8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 16442 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16443 | |
| 16444 | case 0x246: // vcmpgtuh (Compare Greater-than Unsigned HW, AV p169) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16445 | DIP("vcmpgtuh%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16446 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16447 | assign( vD, binop(Iop_CmpGT16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 16448 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16449 | |
| 16450 | case 0x286: // vcmpgtuw (Compare Greater-than Unsigned W, AV p170) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16451 | DIP("vcmpgtuw%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16452 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16453 | assign( vD, binop(Iop_CmpGT32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 16454 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16455 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16456 | case 0x2C7: // vcmpgtud (Compare Greater-than Unsigned double) |
| 16457 | DIP("vcmpgtud%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16458 | vD_addr, vA_addr, vB_addr); |
| 16459 | assign( vD, binop(Iop_CmpGT64Ux2, mkexpr(vA), mkexpr(vB)) ); |
| 16460 | break; |
| 16461 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16462 | case 0x306: // vcmpgtsb (Compare Greater-than Signed B, AV p165) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16463 | DIP("vcmpgtsb%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16464 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16465 | assign( vD, binop(Iop_CmpGT8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 16466 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16467 | |
| 16468 | case 0x346: // vcmpgtsh (Compare Greater-than Signed HW, AV p166) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16469 | DIP("vcmpgtsh%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16470 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16471 | assign( vD, binop(Iop_CmpGT16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 16472 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16473 | |
| 16474 | case 0x386: // vcmpgtsw (Compare Greater-than Signed W, AV p167) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16475 | DIP("vcmpgtsw%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16476 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16477 | assign( vD, binop(Iop_CmpGT32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 16478 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16479 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16480 | case 0x3C7: // vcmpgtsd (Compare Greater-than Signed double) |
| 16481 | DIP("vcmpgtsd%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 16482 | vD_addr, vA_addr, vB_addr); |
| 16483 | assign( vD, binop(Iop_CmpGT64Sx2, mkexpr(vA), mkexpr(vB)) ); |
| 16484 | break; |
| 16485 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16486 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16487 | vex_printf("dis_av_cmp(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16488 | return False; |
| 16489 | } |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16490 | |
| 16491 | putVReg( vD_addr, mkexpr(vD) ); |
| 16492 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 16493 | if (flag_rC) { |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 16494 | set_AV_CR6( mkexpr(vD), True ); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 16495 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16496 | return True; |
| 16497 | } |
| 16498 | |
| 16499 | /* |
| 16500 | AltiVec Multiply-Sum Instructions |
| 16501 | */ |
| 16502 | static Bool dis_av_multarith ( UInt theInstr ) |
| 16503 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 16504 | /* VA-Form */ |
| 16505 | UChar opc1 = ifieldOPC(theInstr); |
| 16506 | UChar vD_addr = ifieldRegDS(theInstr); |
| 16507 | UChar vA_addr = ifieldRegA(theInstr); |
| 16508 | UChar vB_addr = ifieldRegB(theInstr); |
| 16509 | UChar vC_addr = ifieldRegC(theInstr); |
| 16510 | UChar opc2 = toUChar( IFIELD( theInstr, 0, 6 ) ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16511 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16512 | IRTemp vA = newTemp(Ity_V128); |
| 16513 | IRTemp vB = newTemp(Ity_V128); |
| 16514 | IRTemp vC = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 16515 | IRTemp zeros = newTemp(Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16516 | IRTemp aLo = newTemp(Ity_V128); |
| 16517 | IRTemp bLo = newTemp(Ity_V128); |
| 16518 | IRTemp cLo = newTemp(Ity_V128); |
| 16519 | IRTemp zLo = newTemp(Ity_V128); |
| 16520 | IRTemp aHi = newTemp(Ity_V128); |
| 16521 | IRTemp bHi = newTemp(Ity_V128); |
| 16522 | IRTemp cHi = newTemp(Ity_V128); |
| 16523 | IRTemp zHi = newTemp(Ity_V128); |
| 16524 | IRTemp abEvn = newTemp(Ity_V128); |
| 16525 | IRTemp abOdd = newTemp(Ity_V128); |
| 16526 | IRTemp z3 = newTemp(Ity_I64); |
| 16527 | IRTemp z2 = newTemp(Ity_I64); |
| 16528 | IRTemp z1 = newTemp(Ity_I64); |
| 16529 | IRTemp z0 = newTemp(Ity_I64); |
| 16530 | IRTemp ab7, ab6, ab5, ab4, ab3, ab2, ab1, ab0; |
| 16531 | IRTemp c3, c2, c1, c0; |
| 16532 | |
| 16533 | ab7 = ab6 = ab5 = ab4 = ab3 = ab2 = ab1 = ab0 = IRTemp_INVALID; |
| 16534 | c3 = c2 = c1 = c0 = IRTemp_INVALID; |
| 16535 | |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16536 | assign( vA, getVReg(vA_addr)); |
| 16537 | assign( vB, getVReg(vB_addr)); |
| 16538 | assign( vC, getVReg(vC_addr)); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16539 | assign( zeros, unop(Iop_Dup32x4, mkU32(0)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16540 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16541 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16542 | vex_printf("dis_av_multarith(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16543 | return False; |
| 16544 | } |
| 16545 | |
| 16546 | switch (opc2) { |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16547 | /* Multiply-Add */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16548 | case 0x20: { // vmhaddshs (Mult Hi, Add Signed HW Saturate, AV p185) |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16549 | IRTemp cSigns = newTemp(Ity_V128); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16550 | DIP("vmhaddshs v%d,v%d,v%d,v%d\n", |
| 16551 | vD_addr, vA_addr, vB_addr, vC_addr); |
| 16552 | assign(cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC))); |
| 16553 | assign(aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA))); |
| 16554 | assign(bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB))); |
| 16555 | assign(cLo, binop(Iop_InterleaveLO16x8, mkexpr(cSigns),mkexpr(vC))); |
| 16556 | assign(aHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vA))); |
| 16557 | assign(bHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vB))); |
| 16558 | assign(cHi, binop(Iop_InterleaveHI16x8, mkexpr(cSigns),mkexpr(vC))); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16559 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16560 | assign( zLo, binop(Iop_Add32x4, mkexpr(cLo), |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16561 | binop(Iop_SarN32x4, |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 16562 | binop(Iop_MullEven16Sx8, |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16563 | mkexpr(aLo), mkexpr(bLo)), |
| 16564 | mkU8(15))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16565 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16566 | assign( zHi, binop(Iop_Add32x4, mkexpr(cHi), |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16567 | binop(Iop_SarN32x4, |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 16568 | binop(Iop_MullEven16Sx8, |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16569 | mkexpr(aHi), mkexpr(bHi)), |
| 16570 | mkU8(15))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16571 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16572 | putVReg( vD_addr, |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 16573 | binop(Iop_QNarrowBin32Sto16Sx8, mkexpr(zHi), mkexpr(zLo)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16574 | break; |
| 16575 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16576 | case 0x21: { // vmhraddshs (Mult High Round, Add Signed HW Saturate, AV p186) |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16577 | IRTemp zKonst = newTemp(Ity_V128); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16578 | IRTemp cSigns = newTemp(Ity_V128); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16579 | DIP("vmhraddshs v%d,v%d,v%d,v%d\n", |
| 16580 | vD_addr, vA_addr, vB_addr, vC_addr); |
| 16581 | assign(cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC)) ); |
| 16582 | assign(aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA))); |
| 16583 | assign(bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB))); |
| 16584 | assign(cLo, binop(Iop_InterleaveLO16x8, mkexpr(cSigns),mkexpr(vC))); |
| 16585 | assign(aHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vA))); |
| 16586 | assign(bHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vB))); |
| 16587 | assign(cHi, binop(Iop_InterleaveHI16x8, mkexpr(cSigns),mkexpr(vC))); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16588 | |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16589 | /* shifting our const avoids store/load version of Dup */ |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16590 | assign( zKonst, binop(Iop_ShlN32x4, unop(Iop_Dup32x4, mkU32(0x1)), |
| 16591 | mkU8(14)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16592 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16593 | assign( zLo, binop(Iop_Add32x4, mkexpr(cLo), |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16594 | binop(Iop_SarN32x4, |
| 16595 | binop(Iop_Add32x4, mkexpr(zKonst), |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 16596 | binop(Iop_MullEven16Sx8, |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16597 | mkexpr(aLo), mkexpr(bLo))), |
| 16598 | mkU8(15))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16599 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16600 | assign( zHi, binop(Iop_Add32x4, mkexpr(cHi), |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16601 | binop(Iop_SarN32x4, |
| 16602 | binop(Iop_Add32x4, mkexpr(zKonst), |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 16603 | binop(Iop_MullEven16Sx8, |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16604 | mkexpr(aHi), mkexpr(bHi))), |
| 16605 | mkU8(15))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16606 | |
sewardj | c9bff7d | 2011-06-15 15:09:37 +0000 | [diff] [blame] | 16607 | putVReg( vD_addr, |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 16608 | binop(Iop_QNarrowBin32Sto16Sx8, mkexpr(zHi), mkexpr(zLo)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16609 | break; |
| 16610 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16611 | case 0x22: { // vmladduhm (Mult Low, Add Unsigned HW Modulo, AV p194) |
| 16612 | DIP("vmladduhm v%d,v%d,v%d,v%d\n", |
| 16613 | vD_addr, vA_addr, vB_addr, vC_addr); |
| 16614 | assign(aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA))); |
| 16615 | assign(bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB))); |
| 16616 | assign(cLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vC))); |
| 16617 | assign(aHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vA))); |
| 16618 | assign(bHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vB))); |
| 16619 | assign(cHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vC))); |
| 16620 | assign(zLo, binop(Iop_Add32x4, |
| 16621 | binop(Iop_MullEven16Ux8, mkexpr(aLo), mkexpr(bLo)), |
| 16622 | mkexpr(cLo)) ); |
| 16623 | assign(zHi, binop(Iop_Add32x4, |
| 16624 | binop(Iop_MullEven16Ux8, mkexpr(aHi), mkexpr(bHi)), |
| 16625 | mkexpr(cHi))); |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 16626 | putVReg( vD_addr, |
| 16627 | binop(Iop_NarrowBin32to16x8, mkexpr(zHi), mkexpr(zLo)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16628 | break; |
| 16629 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16630 | |
| 16631 | |
| 16632 | /* Multiply-Sum */ |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16633 | case 0x24: { // vmsumubm (Multiply Sum Unsigned B Modulo, AV p204) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16634 | IRTemp abEE, abEO, abOE, abOO; |
| 16635 | abEE = abEO = abOE = abOO = IRTemp_INVALID; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16636 | DIP("vmsumubm v%d,v%d,v%d,v%d\n", |
| 16637 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16638 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16639 | /* multiply vA,vB (unsigned, widening) */ |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16640 | assign( abEvn, MK_Iop_MullOdd8Ux16( mkexpr(vA), mkexpr(vB) )); |
| 16641 | assign( abOdd, binop(Iop_MullEven8Ux16, mkexpr(vA), mkexpr(vB)) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16642 | |
| 16643 | /* evn,odd: V128_16Ux8 -> 2 x V128_32Ux4, zero-extended */ |
| 16644 | expand16Ux8( mkexpr(abEvn), &abEE, &abEO ); |
| 16645 | expand16Ux8( mkexpr(abOdd), &abOE, &abOO ); |
| 16646 | |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16647 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16648 | binop(Iop_Add32x4, mkexpr(vC), |
| 16649 | binop(Iop_Add32x4, |
| 16650 | binop(Iop_Add32x4, mkexpr(abEE), mkexpr(abEO)), |
| 16651 | binop(Iop_Add32x4, mkexpr(abOE), mkexpr(abOO)))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16652 | break; |
| 16653 | } |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16654 | case 0x25: { // vmsummbm (Multiply Sum Mixed-Sign B Modulo, AV p201) |
| 16655 | IRTemp aEvn, aOdd, bEvn, bOdd; |
| 16656 | IRTemp abEE = newTemp(Ity_V128); |
| 16657 | IRTemp abEO = newTemp(Ity_V128); |
| 16658 | IRTemp abOE = newTemp(Ity_V128); |
| 16659 | IRTemp abOO = newTemp(Ity_V128); |
| 16660 | aEvn = aOdd = bEvn = bOdd = IRTemp_INVALID; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16661 | DIP("vmsummbm v%d,v%d,v%d,v%d\n", |
| 16662 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16663 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16664 | /* sign-extend vA, zero-extend vB, for mixed-sign multiply |
| 16665 | (separating out adjacent lanes to different vectors) */ |
| 16666 | expand8Sx16( mkexpr(vA), &aEvn, &aOdd ); |
| 16667 | expand8Ux16( mkexpr(vB), &bEvn, &bOdd ); |
| 16668 | |
| 16669 | /* multiply vA, vB, again separating adjacent lanes */ |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16670 | assign( abEE, MK_Iop_MullOdd16Sx8( mkexpr(aEvn), mkexpr(bEvn) )); |
| 16671 | assign( abEO, binop(Iop_MullEven16Sx8, mkexpr(aEvn), mkexpr(bEvn)) ); |
| 16672 | assign( abOE, MK_Iop_MullOdd16Sx8( mkexpr(aOdd), mkexpr(bOdd) )); |
| 16673 | assign( abOO, binop(Iop_MullEven16Sx8, mkexpr(aOdd), mkexpr(bOdd)) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16674 | |
| 16675 | /* add results together, + vC */ |
| 16676 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16677 | binop(Iop_QAdd32Sx4, mkexpr(vC), |
| 16678 | binop(Iop_QAdd32Sx4, |
| 16679 | binop(Iop_QAdd32Sx4, mkexpr(abEE), mkexpr(abEO)), |
| 16680 | binop(Iop_QAdd32Sx4, mkexpr(abOE), mkexpr(abOO)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16681 | break; |
| 16682 | } |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16683 | case 0x26: { // vmsumuhm (Multiply Sum Unsigned HW Modulo, AV p205) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16684 | DIP("vmsumuhm v%d,v%d,v%d,v%d\n", |
| 16685 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16686 | assign( abEvn, MK_Iop_MullOdd16Ux8( mkexpr(vA), mkexpr(vB) )); |
| 16687 | assign( abOdd, binop(Iop_MullEven16Ux8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16688 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16689 | binop(Iop_Add32x4, mkexpr(vC), |
| 16690 | binop(Iop_Add32x4, mkexpr(abEvn), mkexpr(abOdd))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16691 | break; |
| 16692 | } |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16693 | case 0x27: { // vmsumuhs (Multiply Sum Unsigned HW Saturate, AV p206) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16694 | DIP("vmsumuhs v%d,v%d,v%d,v%d\n", |
| 16695 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16696 | /* widening multiply, separating lanes */ |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16697 | assign( abEvn, MK_Iop_MullOdd16Ux8(mkexpr(vA), mkexpr(vB) )); |
| 16698 | assign( abOdd, binop(Iop_MullEven16Ux8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16699 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16700 | /* break V128 to 4xI32's, zero-extending to I64's */ |
| 16701 | breakV128to4x64U( mkexpr(abEvn), &ab7, &ab5, &ab3, &ab1 ); |
| 16702 | breakV128to4x64U( mkexpr(abOdd), &ab6, &ab4, &ab2, &ab0 ); |
| 16703 | breakV128to4x64U( mkexpr(vC), &c3, &c2, &c1, &c0 ); |
| 16704 | |
| 16705 | /* add lanes */ |
| 16706 | assign( z3, binop(Iop_Add64, mkexpr(c3), |
| 16707 | binop(Iop_Add64, mkexpr(ab7), mkexpr(ab6)))); |
| 16708 | assign( z2, binop(Iop_Add64, mkexpr(c2), |
| 16709 | binop(Iop_Add64, mkexpr(ab5), mkexpr(ab4)))); |
| 16710 | assign( z1, binop(Iop_Add64, mkexpr(c1), |
| 16711 | binop(Iop_Add64, mkexpr(ab3), mkexpr(ab2)))); |
| 16712 | assign( z0, binop(Iop_Add64, mkexpr(c0), |
| 16713 | binop(Iop_Add64, mkexpr(ab1), mkexpr(ab0)))); |
| 16714 | |
| 16715 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 16716 | putVReg( vD_addr, mkV128from4x64U( mkexpr(z3), mkexpr(z2), |
| 16717 | mkexpr(z1), mkexpr(z0)) ); |
| 16718 | |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 16719 | break; |
| 16720 | } |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16721 | case 0x28: { // vmsumshm (Multiply Sum Signed HW Modulo, AV p202) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16722 | DIP("vmsumshm v%d,v%d,v%d,v%d\n", |
| 16723 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16724 | assign( abEvn, MK_Iop_MullOdd16Sx8( mkexpr(vA), mkexpr(vB) )); |
| 16725 | assign( abOdd, binop(Iop_MullEven16Sx8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16726 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16727 | binop(Iop_Add32x4, mkexpr(vC), |
| 16728 | binop(Iop_Add32x4, mkexpr(abOdd), mkexpr(abEvn))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16729 | break; |
| 16730 | } |
| 16731 | case 0x29: { // vmsumshs (Multiply Sum Signed HW Saturate, AV p203) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16732 | DIP("vmsumshs v%d,v%d,v%d,v%d\n", |
| 16733 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16734 | /* widening multiply, separating lanes */ |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 16735 | assign( abEvn, MK_Iop_MullOdd16Sx8( mkexpr(vA), mkexpr(vB) )); |
| 16736 | assign( abOdd, binop(Iop_MullEven16Sx8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16737 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 16738 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 16739 | breakV128to4x64S( mkexpr(abEvn), &ab7, &ab5, &ab3, &ab1 ); |
| 16740 | breakV128to4x64S( mkexpr(abOdd), &ab6, &ab4, &ab2, &ab0 ); |
| 16741 | breakV128to4x64S( mkexpr(vC), &c3, &c2, &c1, &c0 ); |
| 16742 | |
| 16743 | /* add lanes */ |
| 16744 | assign( z3, binop(Iop_Add64, mkexpr(c3), |
| 16745 | binop(Iop_Add64, mkexpr(ab7), mkexpr(ab6)))); |
| 16746 | assign( z2, binop(Iop_Add64, mkexpr(c2), |
| 16747 | binop(Iop_Add64, mkexpr(ab5), mkexpr(ab4)))); |
| 16748 | assign( z1, binop(Iop_Add64, mkexpr(c1), |
| 16749 | binop(Iop_Add64, mkexpr(ab3), mkexpr(ab2)))); |
| 16750 | assign( z0, binop(Iop_Add64, mkexpr(c0), |
| 16751 | binop(Iop_Add64, mkexpr(ab1), mkexpr(ab0)))); |
| 16752 | |
| 16753 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 16754 | putVReg( vD_addr, mkV128from4x64S( mkexpr(z3), mkexpr(z2), |
| 16755 | mkexpr(z1), mkexpr(z0)) ); |
| 16756 | break; |
| 16757 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16758 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16759 | vex_printf("dis_av_multarith(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16760 | return False; |
| 16761 | } |
| 16762 | return True; |
| 16763 | } |
| 16764 | |
| 16765 | /* |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 16766 | AltiVec Polynomial Multiply-Sum Instructions |
| 16767 | */ |
| 16768 | static Bool dis_av_polymultarith ( UInt theInstr ) |
| 16769 | { |
| 16770 | /* VA-Form */ |
| 16771 | UChar opc1 = ifieldOPC(theInstr); |
| 16772 | UChar vD_addr = ifieldRegDS(theInstr); |
| 16773 | UChar vA_addr = ifieldRegA(theInstr); |
| 16774 | UChar vB_addr = ifieldRegB(theInstr); |
| 16775 | UChar vC_addr = ifieldRegC(theInstr); |
| 16776 | UInt opc2 = IFIELD(theInstr, 0, 11); |
| 16777 | IRTemp vA = newTemp(Ity_V128); |
| 16778 | IRTemp vB = newTemp(Ity_V128); |
| 16779 | IRTemp vC = newTemp(Ity_V128); |
| 16780 | |
| 16781 | assign( vA, getVReg(vA_addr)); |
| 16782 | assign( vB, getVReg(vB_addr)); |
| 16783 | assign( vC, getVReg(vC_addr)); |
| 16784 | |
| 16785 | if (opc1 != 0x4) { |
| 16786 | vex_printf("dis_av_polymultarith(ppc)(instr)\n"); |
| 16787 | return False; |
| 16788 | } |
| 16789 | |
| 16790 | switch (opc2) { |
| 16791 | /* Polynomial Multiply-Add */ |
| 16792 | case 0x408: // vpmsumb Vector Polynomial Multipy-sum Byte |
| 16793 | DIP("vpmsumb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16794 | putVReg( vD_addr, binop(Iop_PolynomialMulAdd8x16, |
| 16795 | mkexpr(vA), mkexpr(vB)) ); |
| 16796 | break; |
| 16797 | case 0x448: // vpmsumd Vector Polynomial Multipy-sum Double Word |
| 16798 | DIP("vpmsumd v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16799 | putVReg( vD_addr, binop(Iop_PolynomialMulAdd64x2, |
| 16800 | mkexpr(vA), mkexpr(vB)) ); |
| 16801 | break; |
| 16802 | case 0x488: // vpmsumw Vector Polynomial Multipy-sum Word |
| 16803 | DIP("vpmsumw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16804 | putVReg( vD_addr, binop(Iop_PolynomialMulAdd32x4, |
| 16805 | mkexpr(vA), mkexpr(vB)) ); |
| 16806 | break; |
| 16807 | case 0x4C8: // vpmsumh Vector Polynomial Multipy-sum Half Word |
| 16808 | DIP("vpmsumh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16809 | putVReg( vD_addr, binop(Iop_PolynomialMulAdd16x8, |
| 16810 | mkexpr(vA), mkexpr(vB)) ); |
| 16811 | break; |
| 16812 | default: |
| 16813 | vex_printf("dis_av_polymultarith(ppc)(opc2=0x%x)\n", opc2); |
| 16814 | return False; |
| 16815 | } |
| 16816 | return True; |
| 16817 | } |
| 16818 | |
| 16819 | /* |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16820 | AltiVec Shift/Rotate Instructions |
| 16821 | */ |
| 16822 | static Bool dis_av_shift ( UInt theInstr ) |
| 16823 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 16824 | /* VX-Form */ |
| 16825 | UChar opc1 = ifieldOPC(theInstr); |
| 16826 | UChar vD_addr = ifieldRegDS(theInstr); |
| 16827 | UChar vA_addr = ifieldRegA(theInstr); |
| 16828 | UChar vB_addr = ifieldRegB(theInstr); |
| 16829 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16830 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 16831 | IRTemp vA = newTemp(Ity_V128); |
| 16832 | IRTemp vB = newTemp(Ity_V128); |
| 16833 | assign( vA, getVReg(vA_addr)); |
| 16834 | assign( vB, getVReg(vB_addr)); |
| 16835 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16836 | if (opc1 != 0x4){ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16837 | vex_printf("dis_av_shift(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16838 | return False; |
| 16839 | } |
| 16840 | |
| 16841 | switch (opc2) { |
| 16842 | /* Rotate */ |
| 16843 | case 0x004: // vrlb (Rotate Left Integer B, AV p234) |
| 16844 | DIP("vrlb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 16845 | putVReg( vD_addr, binop(Iop_Rol8x16, mkexpr(vA), mkexpr(vB)) ); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16846 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16847 | |
| 16848 | case 0x044: // vrlh (Rotate Left Integer HW, AV p235) |
| 16849 | DIP("vrlh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 16850 | putVReg( vD_addr, binop(Iop_Rol16x8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16851 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16852 | |
| 16853 | case 0x084: // vrlw (Rotate Left Integer W, AV p236) |
| 16854 | DIP("vrlw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 16855 | putVReg( vD_addr, binop(Iop_Rol32x4, mkexpr(vA), mkexpr(vB)) ); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16856 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16857 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16858 | case 0x0C4: // vrld (Rotate Left Integer Double Word) |
| 16859 | DIP("vrld v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16860 | putVReg( vD_addr, binop(Iop_Rol64x2, mkexpr(vA), mkexpr(vB)) ); |
| 16861 | break; |
| 16862 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16863 | |
| 16864 | /* Shift Left */ |
| 16865 | case 0x104: // vslb (Shift Left Integer B, AV p240) |
| 16866 | DIP("vslb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16867 | putVReg( vD_addr, binop(Iop_Shl8x16, mkexpr(vA), mkexpr(vB)) ); |
| 16868 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16869 | |
| 16870 | case 0x144: // vslh (Shift Left Integer HW, AV p242) |
| 16871 | DIP("vslh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16872 | putVReg( vD_addr, binop(Iop_Shl16x8, mkexpr(vA), mkexpr(vB)) ); |
| 16873 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16874 | |
| 16875 | case 0x184: // vslw (Shift Left Integer W, AV p244) |
| 16876 | DIP("vslw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16877 | putVReg( vD_addr, binop(Iop_Shl32x4, mkexpr(vA), mkexpr(vB)) ); |
| 16878 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16879 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16880 | case 0x5C4: // vsld (Shift Left Integer Double Word) |
| 16881 | DIP("vsld v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16882 | putVReg( vD_addr, binop(Iop_Shl64x2, mkexpr(vA), mkexpr(vB)) ); |
| 16883 | break; |
| 16884 | |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16885 | case 0x1C4: { // vsl (Shift Left, AV p239) |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16886 | IRTemp sh = newTemp(Ity_I8); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 16887 | DIP("vsl v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16888 | assign( sh, binop(Iop_And8, mkU8(0x7), |
| 16889 | unop(Iop_32to8, |
| 16890 | unop(Iop_V128to32, mkexpr(vB)))) ); |
| 16891 | putVReg( vD_addr, |
| 16892 | binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) ); |
| 16893 | break; |
| 16894 | } |
| 16895 | case 0x40C: { // vslo (Shift Left by Octet, AV p243) |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16896 | IRTemp sh = newTemp(Ity_I8); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 16897 | DIP("vslo v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16898 | assign( sh, binop(Iop_And8, mkU8(0x78), |
| 16899 | unop(Iop_32to8, |
| 16900 | unop(Iop_V128to32, mkexpr(vB)))) ); |
| 16901 | putVReg( vD_addr, |
| 16902 | binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) ); |
| 16903 | break; |
| 16904 | } |
| 16905 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16906 | |
| 16907 | /* Shift Right */ |
| 16908 | case 0x204: // vsrb (Shift Right B, AV p256) |
| 16909 | DIP("vsrb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16910 | putVReg( vD_addr, binop(Iop_Shr8x16, mkexpr(vA), mkexpr(vB)) ); |
| 16911 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16912 | |
| 16913 | case 0x244: // vsrh (Shift Right HW, AV p257) |
| 16914 | DIP("vsrh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16915 | putVReg( vD_addr, binop(Iop_Shr16x8, mkexpr(vA), mkexpr(vB)) ); |
| 16916 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16917 | |
| 16918 | case 0x284: // vsrw (Shift Right W, AV p259) |
| 16919 | DIP("vsrw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16920 | putVReg( vD_addr, binop(Iop_Shr32x4, mkexpr(vA), mkexpr(vB)) ); |
| 16921 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16922 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 16923 | case 0x2C4: { // vsr (Shift Right, AV p251) |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 16924 | IRTemp sh = newTemp(Ity_I8); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 16925 | DIP("vsr v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 16926 | assign( sh, binop(Iop_And8, mkU8(0x7), |
| 16927 | unop(Iop_32to8, |
| 16928 | unop(Iop_V128to32, mkexpr(vB)))) ); |
| 16929 | putVReg( vD_addr, |
| 16930 | binop(Iop_ShrV128, mkexpr(vA), mkexpr(sh)) ); |
| 16931 | break; |
| 16932 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16933 | case 0x304: // vsrab (Shift Right Alg B, AV p253) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16934 | DIP("vsrab v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16935 | putVReg( vD_addr, binop(Iop_Sar8x16, mkexpr(vA), mkexpr(vB)) ); |
| 16936 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16937 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16938 | case 0x344: // vsrah (Shift Right Alg HW, AV p254) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16939 | DIP("vsrah v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16940 | putVReg( vD_addr, binop(Iop_Sar16x8, mkexpr(vA), mkexpr(vB)) ); |
| 16941 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16942 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16943 | case 0x384: // vsraw (Shift Right Alg W, AV p255) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16944 | DIP("vsraw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16945 | putVReg( vD_addr, binop(Iop_Sar32x4, mkexpr(vA), mkexpr(vB)) ); |
| 16946 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16947 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16948 | case 0x3C4: // vsrad (Shift Right Alg Double Word) |
| 16949 | DIP("vsrad v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16950 | putVReg( vD_addr, binop(Iop_Sar64x2, mkexpr(vA), mkexpr(vB)) ); |
| 16951 | break; |
| 16952 | |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16953 | case 0x44C: { // vsro (Shift Right by Octet, AV p258) |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16954 | IRTemp sh = newTemp(Ity_I8); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 16955 | DIP("vsro v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 16956 | assign( sh, binop(Iop_And8, mkU8(0x78), |
| 16957 | unop(Iop_32to8, |
| 16958 | unop(Iop_V128to32, mkexpr(vB)))) ); |
| 16959 | putVReg( vD_addr, |
| 16960 | binop(Iop_ShrV128, mkexpr(vA), mkexpr(sh)) ); |
| 16961 | break; |
| 16962 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16963 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 16964 | case 0x6C4: // vsrd (Shift Right Double Word) |
| 16965 | DIP("vsrd v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 16966 | putVReg( vD_addr, binop(Iop_Shr64x2, mkexpr(vA), mkexpr(vB)) ); |
| 16967 | break; |
| 16968 | |
| 16969 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16970 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 16971 | vex_printf("dis_av_shift(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16972 | return False; |
| 16973 | } |
| 16974 | return True; |
| 16975 | } |
| 16976 | |
| 16977 | /* |
| 16978 | AltiVec Permute Instructions |
| 16979 | */ |
| 16980 | static Bool dis_av_permute ( UInt theInstr ) |
| 16981 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 16982 | /* VA-Form, VX-Form */ |
| 16983 | UChar opc1 = ifieldOPC(theInstr); |
| 16984 | UChar vD_addr = ifieldRegDS(theInstr); |
| 16985 | UChar vA_addr = ifieldRegA(theInstr); |
| 16986 | UChar UIMM_5 = vA_addr; |
| 16987 | UChar vB_addr = ifieldRegB(theInstr); |
| 16988 | UChar vC_addr = ifieldRegC(theInstr); |
| 16989 | UChar b10 = ifieldBIT10(theInstr); |
| 16990 | UChar SHB_uimm4 = toUChar( IFIELD( theInstr, 6, 4 ) ); |
| 16991 | UInt opc2 = toUChar( IFIELD( theInstr, 0, 6 ) ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16992 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 16993 | UChar SIMM_8 = extend_s_5to8(UIMM_5); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 16994 | |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 16995 | IRTemp vA = newTemp(Ity_V128); |
| 16996 | IRTemp vB = newTemp(Ity_V128); |
| 16997 | IRTemp vC = newTemp(Ity_V128); |
| 16998 | assign( vA, getVReg(vA_addr)); |
| 16999 | assign( vB, getVReg(vB_addr)); |
| 17000 | assign( vC, getVReg(vC_addr)); |
| 17001 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17002 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17003 | vex_printf("dis_av_permute(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17004 | return False; |
| 17005 | } |
| 17006 | |
| 17007 | switch (opc2) { |
| 17008 | case 0x2A: // vsel (Conditional Select, AV p238) |
| 17009 | DIP("vsel v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 17010 | /* vD = (vA & ~vC) | (vB & vC) */ |
| 17011 | putVReg( vD_addr, binop(Iop_OrV128, |
| 17012 | binop(Iop_AndV128, mkexpr(vA), unop(Iop_NotV128, mkexpr(vC))), |
| 17013 | binop(Iop_AndV128, mkexpr(vB), mkexpr(vC))) ); |
| 17014 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17015 | |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17016 | case 0x2B: { // vperm (Permute, AV p218) |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17017 | /* limited to two args for IR, so have to play games... */ |
sewardj | dc1f913 | 2005-10-22 12:49:49 +0000 | [diff] [blame] | 17018 | IRTemp a_perm = newTemp(Ity_V128); |
| 17019 | IRTemp b_perm = newTemp(Ity_V128); |
| 17020 | IRTemp mask = newTemp(Ity_V128); |
| 17021 | IRTemp vC_andF = newTemp(Ity_V128); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17022 | DIP("vperm v%d,v%d,v%d,v%d\n", |
| 17023 | vD_addr, vA_addr, vB_addr, vC_addr); |
sewardj | dc1f913 | 2005-10-22 12:49:49 +0000 | [diff] [blame] | 17024 | /* Limit the Perm8x16 steering values to 0 .. 15 as that is what |
| 17025 | IR specifies, and also to hide irrelevant bits from |
| 17026 | memcheck */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17027 | assign( vC_andF, |
| 17028 | binop(Iop_AndV128, mkexpr(vC), |
| 17029 | unop(Iop_Dup8x16, mkU8(0xF))) ); |
| 17030 | assign( a_perm, |
| 17031 | binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) ); |
| 17032 | assign( b_perm, |
| 17033 | binop(Iop_Perm8x16, mkexpr(vB), mkexpr(vC_andF)) ); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17034 | // mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0 |
| 17035 | assign( mask, binop(Iop_SarN8x16, |
| 17036 | binop(Iop_ShlN8x16, mkexpr(vC), mkU8(3)), |
| 17037 | mkU8(7)) ); |
| 17038 | // dst = (a & ~mask) | (b & mask) |
| 17039 | putVReg( vD_addr, binop(Iop_OrV128, |
| 17040 | binop(Iop_AndV128, mkexpr(a_perm), |
| 17041 | unop(Iop_NotV128, mkexpr(mask))), |
| 17042 | binop(Iop_AndV128, mkexpr(b_perm), |
| 17043 | mkexpr(mask))) ); |
| 17044 | return True; |
| 17045 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17046 | case 0x2C: // vsldoi (Shift Left Double by Octet Imm, AV p241) |
| 17047 | if (b10 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17048 | vex_printf("dis_av_permute(ppc)(vsldoi)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17049 | return False; |
| 17050 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17051 | DIP("vsldoi v%d,v%d,v%d,%d\n", |
| 17052 | vD_addr, vA_addr, vB_addr, SHB_uimm4); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17053 | if (SHB_uimm4 == 0) |
| 17054 | putVReg( vD_addr, mkexpr(vA) ); |
| 17055 | else |
| 17056 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17057 | binop(Iop_OrV128, |
| 17058 | binop(Iop_ShlV128, mkexpr(vA), mkU8(SHB_uimm4*8)), |
| 17059 | binop(Iop_ShrV128, mkexpr(vB), mkU8((16-SHB_uimm4)*8))) ); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17060 | return True; |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 17061 | case 0x2D: { // vpermxor (Vector Permute and Exclusive-OR) |
| 17062 | IRTemp a_perm = newTemp(Ity_V128); |
| 17063 | IRTemp b_perm = newTemp(Ity_V128); |
| 17064 | IRTemp vrc_a = newTemp(Ity_V128); |
| 17065 | IRTemp vrc_b = newTemp(Ity_V128); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17066 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 17067 | /* IBM index is 0:7, Change index value to index 7:0 */ |
| 17068 | assign( vrc_b, binop( Iop_AndV128, mkexpr( vC ), |
| 17069 | unop( Iop_Dup8x16, mkU8( 0xF ) ) ) ); |
| 17070 | assign( vrc_a, binop( Iop_ShrV128, |
| 17071 | binop( Iop_AndV128, mkexpr( vC ), |
| 17072 | unop( Iop_Dup8x16, mkU8( 0xF0 ) ) ), |
| 17073 | mkU8 ( 4 ) ) ); |
| 17074 | assign( a_perm, binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( vrc_a ) ) ); |
| 17075 | assign( b_perm, binop( Iop_Perm8x16, mkexpr( vB ), mkexpr( vrc_b ) ) ); |
| 17076 | putVReg( vD_addr, binop( Iop_XorV128, |
| 17077 | mkexpr( a_perm ), mkexpr( b_perm) ) ); |
| 17078 | return True; |
| 17079 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17080 | default: |
| 17081 | break; // Fall through... |
| 17082 | } |
| 17083 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 17084 | opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17085 | switch (opc2) { |
| 17086 | |
| 17087 | /* Merge */ |
| 17088 | case 0x00C: // vmrghb (Merge High B, AV p195) |
| 17089 | DIP("vmrghb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17090 | putVReg( vD_addr, |
| 17091 | binop(Iop_InterleaveHI8x16, mkexpr(vA), mkexpr(vB)) ); |
| 17092 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17093 | |
| 17094 | case 0x04C: // vmrghh (Merge High HW, AV p196) |
| 17095 | DIP("vmrghh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17096 | putVReg( vD_addr, |
| 17097 | binop(Iop_InterleaveHI16x8, mkexpr(vA), mkexpr(vB)) ); |
| 17098 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17099 | |
| 17100 | case 0x08C: // vmrghw (Merge High W, AV p197) |
| 17101 | DIP("vmrghw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17102 | putVReg( vD_addr, |
| 17103 | binop(Iop_InterleaveHI32x4, mkexpr(vA), mkexpr(vB)) ); |
| 17104 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17105 | |
| 17106 | case 0x10C: // vmrglb (Merge Low B, AV p198) |
| 17107 | DIP("vmrglb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17108 | putVReg( vD_addr, |
| 17109 | binop(Iop_InterleaveLO8x16, mkexpr(vA), mkexpr(vB)) ); |
| 17110 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17111 | |
| 17112 | case 0x14C: // vmrglh (Merge Low HW, AV p199) |
| 17113 | DIP("vmrglh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17114 | putVReg( vD_addr, |
| 17115 | binop(Iop_InterleaveLO16x8, mkexpr(vA), mkexpr(vB)) ); |
| 17116 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17117 | |
| 17118 | case 0x18C: // vmrglw (Merge Low W, AV p200) |
| 17119 | DIP("vmrglw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17120 | putVReg( vD_addr, |
| 17121 | binop(Iop_InterleaveLO32x4, mkexpr(vA), mkexpr(vB)) ); |
| 17122 | break; |
| 17123 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17124 | |
| 17125 | /* Splat */ |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17126 | case 0x20C: { // vspltb (Splat Byte, AV p245) |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17127 | /* vD = Dup8x16( vB[UIMM_5] ) */ |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 17128 | UChar sh_uimm = (15 - (UIMM_5 & 15)) * 8; |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17129 | DIP("vspltb v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17130 | putVReg( vD_addr, unop(Iop_Dup8x16, |
| 17131 | unop(Iop_32to8, unop(Iop_V128to32, |
| 17132 | binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) ); |
| 17133 | break; |
| 17134 | } |
| 17135 | case 0x24C: { // vsplth (Splat Half Word, AV p246) |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 17136 | UChar sh_uimm = (7 - (UIMM_5 & 7)) * 16; |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17137 | DIP("vsplth v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17138 | putVReg( vD_addr, unop(Iop_Dup16x8, |
| 17139 | unop(Iop_32to16, unop(Iop_V128to32, |
| 17140 | binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) ); |
| 17141 | break; |
| 17142 | } |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 17143 | case 0x28C: { // vspltw (Splat Word, AV p250) |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 17144 | /* vD = Dup32x4( vB[UIMM_5] ) */ |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 17145 | UChar sh_uimm = (3 - (UIMM_5 & 3)) * 32; |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17146 | DIP("vspltw v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 17147 | putVReg( vD_addr, unop(Iop_Dup32x4, |
| 17148 | unop(Iop_V128to32, |
| 17149 | binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm)))) ); |
| 17150 | break; |
| 17151 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17152 | case 0x30C: // vspltisb (Splat Immediate Signed B, AV p247) |
| 17153 | DIP("vspltisb v%d,%d\n", vD_addr, (Char)SIMM_8); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17154 | putVReg( vD_addr, unop(Iop_Dup8x16, mkU8(SIMM_8)) ); |
| 17155 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17156 | |
| 17157 | case 0x34C: // vspltish (Splat Immediate Signed HW, AV p248) |
| 17158 | DIP("vspltish v%d,%d\n", vD_addr, (Char)SIMM_8); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17159 | putVReg( vD_addr, |
| 17160 | unop(Iop_Dup16x8, mkU16(extend_s_8to32(SIMM_8))) ); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17161 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17162 | |
| 17163 | case 0x38C: // vspltisw (Splat Immediate Signed W, AV p249) |
| 17164 | DIP("vspltisw v%d,%d\n", vD_addr, (Char)SIMM_8); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17165 | putVReg( vD_addr, |
| 17166 | unop(Iop_Dup32x4, mkU32(extend_s_8to32(SIMM_8))) ); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 17167 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17168 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 17169 | case 0x68C: // vmrgow (Merge Odd Word) |
| 17170 | DIP("vmrgow v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17171 | /* VD[0] <- VA[1] |
| 17172 | VD[1] <- VB[1] |
| 17173 | VD[2] <- VA[3] |
| 17174 | VD[3] <- VB[3] |
| 17175 | */ |
| 17176 | putVReg( vD_addr, |
| 17177 | binop(Iop_CatOddLanes32x4, mkexpr(vA), mkexpr(vB) ) ); |
| 17178 | break; |
| 17179 | |
| 17180 | case 0x78C: // vmrgew (Merge Even Word) |
| 17181 | DIP("vmrgew v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17182 | /* VD[0] <- VA[0] |
| 17183 | VD[1] <- VB[0] |
| 17184 | VD[2] <- VA[2] |
| 17185 | VD[3] <- VB[2] |
| 17186 | */ |
| 17187 | putVReg( vD_addr, |
| 17188 | binop(Iop_CatEvenLanes32x4, mkexpr(vA), mkexpr(vB) ) ); |
| 17189 | break; |
| 17190 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17191 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17192 | vex_printf("dis_av_permute(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17193 | return False; |
| 17194 | } |
| 17195 | return True; |
| 17196 | } |
| 17197 | |
| 17198 | /* |
| 17199 | AltiVec Pack/Unpack Instructions |
| 17200 | */ |
| 17201 | static Bool dis_av_pack ( UInt theInstr ) |
| 17202 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 17203 | /* VX-Form */ |
| 17204 | UChar opc1 = ifieldOPC(theInstr); |
| 17205 | UChar vD_addr = ifieldRegDS(theInstr); |
| 17206 | UChar vA_addr = ifieldRegA(theInstr); |
| 17207 | UChar vB_addr = ifieldRegB(theInstr); |
| 17208 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17209 | |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17210 | IRTemp signs = IRTemp_INVALID; |
| 17211 | IRTemp zeros = IRTemp_INVALID; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 17212 | IRTemp vA = newTemp(Ity_V128); |
| 17213 | IRTemp vB = newTemp(Ity_V128); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17214 | assign( vA, getVReg(vA_addr)); |
| 17215 | assign( vB, getVReg(vB_addr)); |
| 17216 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17217 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17218 | vex_printf("dis_av_pack(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17219 | return False; |
| 17220 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17221 | switch (opc2) { |
| 17222 | /* Packing */ |
| 17223 | case 0x00E: // vpkuhum (Pack Unsigned HW Unsigned Modulo, AV p224) |
| 17224 | DIP("vpkuhum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 17225 | putVReg( vD_addr, |
| 17226 | binop(Iop_NarrowBin16to8x16, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17227 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17228 | |
| 17229 | case 0x04E: // vpkuwum (Pack Unsigned W Unsigned Modulo, AV p226) |
| 17230 | DIP("vpkuwum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 17231 | putVReg( vD_addr, |
| 17232 | binop(Iop_NarrowBin32to16x8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17233 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17234 | |
| 17235 | case 0x08E: // vpkuhus (Pack Unsigned HW Unsigned Saturate, AV p225) |
| 17236 | DIP("vpkuhus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17237 | putVReg( vD_addr, |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 17238 | binop(Iop_QNarrowBin16Uto8Ux16, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17239 | // TODO: set VSCR[SAT] |
| 17240 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17241 | |
| 17242 | case 0x0CE: // vpkuwus (Pack Unsigned W Unsigned Saturate, AV p227) |
| 17243 | DIP("vpkuwus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17244 | putVReg( vD_addr, |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 17245 | binop(Iop_QNarrowBin32Uto16Ux8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17246 | // TODO: set VSCR[SAT] |
| 17247 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17248 | |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17249 | case 0x10E: { // vpkshus (Pack Signed HW Unsigned Saturate, AV p221) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17250 | // This insn does a signed->unsigned saturating conversion. |
| 17251 | // Conversion done here, then uses unsigned->unsigned vpk insn: |
| 17252 | // => UnsignedSaturatingNarrow( x & ~ (x >>s 15) ) |
| 17253 | IRTemp vA_tmp = newTemp(Ity_V128); |
| 17254 | IRTemp vB_tmp = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17255 | DIP("vpkshus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17256 | assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA), |
| 17257 | unop(Iop_NotV128, |
| 17258 | binop(Iop_SarN16x8, |
| 17259 | mkexpr(vA), mkU8(15)))) ); |
| 17260 | assign( vB_tmp, binop(Iop_AndV128, mkexpr(vB), |
| 17261 | unop(Iop_NotV128, |
| 17262 | binop(Iop_SarN16x8, |
| 17263 | mkexpr(vB), mkU8(15)))) ); |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 17264 | putVReg( vD_addr, binop(Iop_QNarrowBin16Uto8Ux16, |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17265 | mkexpr(vA_tmp), mkexpr(vB_tmp)) ); |
| 17266 | // TODO: set VSCR[SAT] |
| 17267 | return True; |
| 17268 | } |
| 17269 | case 0x14E: { // vpkswus (Pack Signed W Unsigned Saturate, AV p223) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17270 | // This insn does a signed->unsigned saturating conversion. |
| 17271 | // Conversion done here, then uses unsigned->unsigned vpk insn: |
| 17272 | // => UnsignedSaturatingNarrow( x & ~ (x >>s 31) ) |
| 17273 | IRTemp vA_tmp = newTemp(Ity_V128); |
| 17274 | IRTemp vB_tmp = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17275 | DIP("vpkswus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17276 | assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA), |
| 17277 | unop(Iop_NotV128, |
| 17278 | binop(Iop_SarN32x4, |
| 17279 | mkexpr(vA), mkU8(31)))) ); |
| 17280 | assign( vB_tmp, binop(Iop_AndV128, mkexpr(vB), |
| 17281 | unop(Iop_NotV128, |
| 17282 | binop(Iop_SarN32x4, |
| 17283 | mkexpr(vB), mkU8(31)))) ); |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 17284 | putVReg( vD_addr, binop(Iop_QNarrowBin32Uto16Ux8, |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17285 | mkexpr(vA_tmp), mkexpr(vB_tmp)) ); |
| 17286 | // TODO: set VSCR[SAT] |
| 17287 | return True; |
| 17288 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17289 | case 0x18E: // vpkshss (Pack Signed HW Signed Saturate, AV p220) |
| 17290 | DIP("vpkshss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17291 | putVReg( vD_addr, |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 17292 | binop(Iop_QNarrowBin16Sto8Sx16, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17293 | // TODO: set VSCR[SAT] |
| 17294 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17295 | |
| 17296 | case 0x1CE: // vpkswss (Pack Signed W Signed Saturate, AV p222) |
| 17297 | DIP("vpkswss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17298 | putVReg( vD_addr, |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 17299 | binop(Iop_QNarrowBin32Sto16Sx8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17300 | // TODO: set VSCR[SAT] |
| 17301 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17302 | |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17303 | case 0x30E: { // vpkpx (Pack Pixel, AV p219) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17304 | /* CAB: Worth a new primop? */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17305 | /* Using shifts to compact pixel elements, then packing them */ |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17306 | IRTemp a1 = newTemp(Ity_V128); |
| 17307 | IRTemp a2 = newTemp(Ity_V128); |
| 17308 | IRTemp a3 = newTemp(Ity_V128); |
| 17309 | IRTemp a_tmp = newTemp(Ity_V128); |
| 17310 | IRTemp b1 = newTemp(Ity_V128); |
| 17311 | IRTemp b2 = newTemp(Ity_V128); |
| 17312 | IRTemp b3 = newTemp(Ity_V128); |
| 17313 | IRTemp b_tmp = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17314 | DIP("vpkpx v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17315 | assign( a1, binop(Iop_ShlN16x8, |
| 17316 | binop(Iop_ShrN32x4, mkexpr(vA), mkU8(19)), |
| 17317 | mkU8(10)) ); |
| 17318 | assign( a2, binop(Iop_ShlN16x8, |
| 17319 | binop(Iop_ShrN16x8, mkexpr(vA), mkU8(11)), |
| 17320 | mkU8(5)) ); |
| 17321 | assign( a3, binop(Iop_ShrN16x8, |
| 17322 | binop(Iop_ShlN16x8, mkexpr(vA), mkU8(8)), |
| 17323 | mkU8(11)) ); |
| 17324 | assign( a_tmp, binop(Iop_OrV128, mkexpr(a1), |
| 17325 | binop(Iop_OrV128, mkexpr(a2), mkexpr(a3))) ); |
| 17326 | |
| 17327 | assign( b1, binop(Iop_ShlN16x8, |
| 17328 | binop(Iop_ShrN32x4, mkexpr(vB), mkU8(19)), |
| 17329 | mkU8(10)) ); |
| 17330 | assign( b2, binop(Iop_ShlN16x8, |
| 17331 | binop(Iop_ShrN16x8, mkexpr(vB), mkU8(11)), |
| 17332 | mkU8(5)) ); |
| 17333 | assign( b3, binop(Iop_ShrN16x8, |
| 17334 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(8)), |
| 17335 | mkU8(11)) ); |
| 17336 | assign( b_tmp, binop(Iop_OrV128, mkexpr(b1), |
| 17337 | binop(Iop_OrV128, mkexpr(b2), mkexpr(b3))) ); |
| 17338 | |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 17339 | putVReg( vD_addr, binop(Iop_NarrowBin32to16x8, |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17340 | mkexpr(a_tmp), mkexpr(b_tmp)) ); |
| 17341 | return True; |
| 17342 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17343 | |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 17344 | case 0x44E: // vpkudum (Pack Unsigned Double Word Unsigned Modulo) |
| 17345 | DIP("vpkudum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17346 | putVReg( vD_addr, |
| 17347 | binop(Iop_NarrowBin64to32x4, mkexpr(vA), mkexpr(vB)) ); |
| 17348 | return True; |
| 17349 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 17350 | case 0x4CE: // vpkudus (Pack Unsigned Double Word Unsigned Saturate) |
| 17351 | DIP("vpkudus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17352 | putVReg( vD_addr, |
| 17353 | binop(Iop_QNarrowBin64Uto32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 17354 | // TODO: set VSCR[SAT] |
| 17355 | return True; |
| 17356 | |
| 17357 | case 0x54E: { // vpksdus (Pack Signed Double Word Unsigned Saturate) |
| 17358 | // This insn does a doubled signed->double unsigned saturating conversion |
| 17359 | // Conversion done here, then uses unsigned->unsigned vpk insn: |
| 17360 | // => UnsignedSaturatingNarrow( x & ~ (x >>s 31) ) |
| 17361 | // This is similar to the technique used for vpkswus, except done |
| 17362 | // with double word integers versus word integers. |
| 17363 | IRTemp vA_tmp = newTemp(Ity_V128); |
| 17364 | IRTemp vB_tmp = newTemp(Ity_V128); |
| 17365 | DIP("vpksdus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17366 | assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA), |
| 17367 | unop(Iop_NotV128, |
| 17368 | binop(Iop_SarN64x2, |
| 17369 | mkexpr(vA), mkU8(63)))) ); |
| 17370 | assign( vB_tmp, binop(Iop_AndV128, mkexpr(vB), |
| 17371 | unop(Iop_NotV128, |
| 17372 | binop(Iop_SarN64x2, |
| 17373 | mkexpr(vB), mkU8(63)))) ); |
| 17374 | putVReg( vD_addr, binop(Iop_QNarrowBin64Uto32Ux4, |
| 17375 | mkexpr(vA_tmp), mkexpr(vB_tmp)) ); |
| 17376 | // TODO: set VSCR[SAT] |
| 17377 | return True; |
| 17378 | } |
| 17379 | |
| 17380 | case 0x5CE: // vpksdss (Pack Signed double word Signed Saturate) |
| 17381 | DIP("vpksdss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17382 | putVReg( vD_addr, |
| 17383 | binop(Iop_QNarrowBin64Sto32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 17384 | // TODO: set VSCR[SAT] |
| 17385 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17386 | default: |
| 17387 | break; // Fall through... |
| 17388 | } |
| 17389 | |
| 17390 | |
| 17391 | if (vA_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17392 | vex_printf("dis_av_pack(ppc)(vA_addr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17393 | return False; |
| 17394 | } |
| 17395 | |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17396 | signs = newTemp(Ity_V128); |
| 17397 | zeros = newTemp(Ity_V128); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17398 | assign( zeros, unop(Iop_Dup32x4, mkU32(0)) ); |
| 17399 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17400 | switch (opc2) { |
| 17401 | /* Unpacking */ |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17402 | case 0x20E: { // vupkhsb (Unpack High Signed B, AV p277) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17403 | DIP("vupkhsb v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17404 | assign( signs, binop(Iop_CmpGT8Sx16, mkexpr(zeros), mkexpr(vB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17405 | putVReg( vD_addr, |
| 17406 | binop(Iop_InterleaveHI8x16, mkexpr(signs), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17407 | break; |
| 17408 | } |
| 17409 | case 0x24E: { // vupkhsh (Unpack High Signed HW, AV p278) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17410 | DIP("vupkhsh v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17411 | assign( signs, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17412 | putVReg( vD_addr, |
| 17413 | binop(Iop_InterleaveHI16x8, mkexpr(signs), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17414 | break; |
| 17415 | } |
| 17416 | case 0x28E: { // vupklsb (Unpack Low Signed B, AV p280) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17417 | DIP("vupklsb v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17418 | assign( signs, binop(Iop_CmpGT8Sx16, mkexpr(zeros), mkexpr(vB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17419 | putVReg( vD_addr, |
| 17420 | binop(Iop_InterleaveLO8x16, mkexpr(signs), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17421 | break; |
| 17422 | } |
| 17423 | case 0x2CE: { // vupklsh (Unpack Low Signed HW, AV p281) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17424 | DIP("vupklsh v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17425 | assign( signs, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17426 | putVReg( vD_addr, |
| 17427 | binop(Iop_InterleaveLO16x8, mkexpr(signs), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17428 | break; |
| 17429 | } |
| 17430 | case 0x34E: { // vupkhpx (Unpack High Pixel16, AV p276) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17431 | /* CAB: Worth a new primop? */ |
| 17432 | /* Using shifts to isolate pixel elements, then expanding them */ |
| 17433 | IRTemp z0 = newTemp(Ity_V128); |
| 17434 | IRTemp z1 = newTemp(Ity_V128); |
| 17435 | IRTemp z01 = newTemp(Ity_V128); |
| 17436 | IRTemp z2 = newTemp(Ity_V128); |
| 17437 | IRTemp z3 = newTemp(Ity_V128); |
| 17438 | IRTemp z23 = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17439 | DIP("vupkhpx v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17440 | assign( z0, binop(Iop_ShlN16x8, |
| 17441 | binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)), |
| 17442 | mkU8(8)) ); |
| 17443 | assign( z1, binop(Iop_ShrN16x8, |
| 17444 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(1)), |
| 17445 | mkU8(11)) ); |
| 17446 | assign( z01, binop(Iop_InterleaveHI16x8, mkexpr(zeros), |
| 17447 | binop(Iop_OrV128, mkexpr(z0), mkexpr(z1))) ); |
| 17448 | assign( z2, binop(Iop_ShrN16x8, |
| 17449 | binop(Iop_ShlN16x8, |
| 17450 | binop(Iop_ShrN16x8, mkexpr(vB), mkU8(5)), |
| 17451 | mkU8(11)), |
| 17452 | mkU8(3)) ); |
| 17453 | assign( z3, binop(Iop_ShrN16x8, |
| 17454 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(11)), |
| 17455 | mkU8(11)) ); |
| 17456 | assign( z23, binop(Iop_InterleaveHI16x8, mkexpr(zeros), |
| 17457 | binop(Iop_OrV128, mkexpr(z2), mkexpr(z3))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17458 | putVReg( vD_addr, |
| 17459 | binop(Iop_OrV128, |
| 17460 | binop(Iop_ShlN32x4, mkexpr(z01), mkU8(16)), |
| 17461 | mkexpr(z23)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17462 | break; |
| 17463 | } |
| 17464 | case 0x3CE: { // vupklpx (Unpack Low Pixel16, AV p279) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17465 | /* identical to vupkhpx, except interleaving LO */ |
| 17466 | IRTemp z0 = newTemp(Ity_V128); |
| 17467 | IRTemp z1 = newTemp(Ity_V128); |
| 17468 | IRTemp z01 = newTemp(Ity_V128); |
| 17469 | IRTemp z2 = newTemp(Ity_V128); |
| 17470 | IRTemp z3 = newTemp(Ity_V128); |
| 17471 | IRTemp z23 = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 17472 | DIP("vupklpx v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17473 | assign( z0, binop(Iop_ShlN16x8, |
| 17474 | binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)), |
| 17475 | mkU8(8)) ); |
| 17476 | assign( z1, binop(Iop_ShrN16x8, |
| 17477 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(1)), |
| 17478 | mkU8(11)) ); |
| 17479 | assign( z01, binop(Iop_InterleaveLO16x8, mkexpr(zeros), |
| 17480 | binop(Iop_OrV128, mkexpr(z0), mkexpr(z1))) ); |
| 17481 | assign( z2, binop(Iop_ShrN16x8, |
| 17482 | binop(Iop_ShlN16x8, |
| 17483 | binop(Iop_ShrN16x8, mkexpr(vB), mkU8(5)), |
| 17484 | mkU8(11)), |
| 17485 | mkU8(3)) ); |
| 17486 | assign( z3, binop(Iop_ShrN16x8, |
| 17487 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(11)), |
| 17488 | mkU8(11)) ); |
| 17489 | assign( z23, binop(Iop_InterleaveLO16x8, mkexpr(zeros), |
| 17490 | binop(Iop_OrV128, mkexpr(z2), mkexpr(z3))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17491 | putVReg( vD_addr, |
| 17492 | binop(Iop_OrV128, |
| 17493 | binop(Iop_ShlN32x4, mkexpr(z01), mkU8(16)), |
| 17494 | mkexpr(z23)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 17495 | break; |
| 17496 | } |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 17497 | case 0x64E: { // vupkhsw (Unpack High Signed Word) |
| 17498 | DIP("vupkhsw v%d,v%d\n", vD_addr, vB_addr); |
| 17499 | assign( signs, binop(Iop_CmpGT32Sx4, mkexpr(zeros), mkexpr(vB)) ); |
| 17500 | putVReg( vD_addr, |
| 17501 | binop(Iop_InterleaveHI32x4, mkexpr(signs), mkexpr(vB)) ); |
| 17502 | break; |
| 17503 | } |
| 17504 | case 0x6CE: { // vupklsw (Unpack Low Signed Word) |
| 17505 | DIP("vupklsw v%d,v%d\n", vD_addr, vB_addr); |
| 17506 | assign( signs, binop(Iop_CmpGT32Sx4, mkexpr(zeros), mkexpr(vB)) ); |
| 17507 | putVReg( vD_addr, |
| 17508 | binop(Iop_InterleaveLO32x4, mkexpr(signs), mkexpr(vB)) ); |
| 17509 | break; |
| 17510 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17511 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17512 | vex_printf("dis_av_pack(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17513 | return False; |
| 17514 | } |
| 17515 | return True; |
| 17516 | } |
| 17517 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 17518 | /* |
| 17519 | AltiVec Cipher Instructions |
| 17520 | */ |
| 17521 | static Bool dis_av_cipher ( UInt theInstr ) |
| 17522 | { |
| 17523 | /* VX-Form */ |
| 17524 | UChar opc1 = ifieldOPC(theInstr); |
| 17525 | UChar vD_addr = ifieldRegDS(theInstr); |
| 17526 | UChar vA_addr = ifieldRegA(theInstr); |
| 17527 | UChar vB_addr = ifieldRegB(theInstr); |
| 17528 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
| 17529 | |
| 17530 | IRTemp vA = newTemp(Ity_V128); |
| 17531 | IRTemp vB = newTemp(Ity_V128); |
| 17532 | assign( vA, getVReg(vA_addr)); |
| 17533 | assign( vB, getVReg(vB_addr)); |
| 17534 | |
| 17535 | if (opc1 != 0x4) { |
| 17536 | vex_printf("dis_av_cipher(ppc)(instr)\n"); |
| 17537 | return False; |
| 17538 | } |
| 17539 | switch (opc2) { |
| 17540 | case 0x508: // vcipher (Vector Inverser Cipher) |
| 17541 | DIP("vcipher v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17542 | putVReg( vD_addr, |
| 17543 | binop(Iop_CipherV128, mkexpr(vA), mkexpr(vB)) ); |
| 17544 | return True; |
| 17545 | |
| 17546 | case 0x509: // vcipherlast (Vector Inverser Cipher Last) |
| 17547 | DIP("vcipherlast v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17548 | putVReg( vD_addr, |
| 17549 | binop(Iop_CipherLV128, mkexpr(vA), mkexpr(vB)) ); |
| 17550 | return True; |
| 17551 | |
| 17552 | case 0x548: // vncipher (Vector Inverser Cipher) |
| 17553 | DIP("vncipher v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17554 | putVReg( vD_addr, |
| 17555 | binop(Iop_NCipherV128, mkexpr(vA), mkexpr(vB)) ); |
| 17556 | return True; |
| 17557 | |
| 17558 | case 0x549: // vncipherlast (Vector Inverser Cipher Last) |
| 17559 | DIP("vncipherlast v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
| 17560 | putVReg( vD_addr, |
| 17561 | binop(Iop_NCipherLV128, mkexpr(vA), mkexpr(vB)) ); |
| 17562 | return True; |
| 17563 | |
| 17564 | case 0x5C8: /* vsbox (Vector SubBytes, this does the cipher |
| 17565 | * subBytes transform) |
| 17566 | */ |
| 17567 | DIP("vsbox v%d,v%d\n", vD_addr, vA_addr); |
| 17568 | putVReg( vD_addr, |
| 17569 | unop(Iop_CipherSV128, mkexpr(vA) ) ); |
| 17570 | return True; |
| 17571 | |
| 17572 | default: |
| 17573 | vex_printf("dis_av_cipher(ppc)(opc2)\n"); |
| 17574 | return False; |
| 17575 | } |
| 17576 | return True; |
| 17577 | } |
| 17578 | |
| 17579 | /* |
| 17580 | AltiVec Secure Hash Instructions |
| 17581 | */ |
| 17582 | static Bool dis_av_hash ( UInt theInstr ) |
| 17583 | { |
| 17584 | /* VX-Form */ |
| 17585 | UChar opc1 = ifieldOPC(theInstr); |
| 17586 | UChar vRT_addr = ifieldRegDS(theInstr); |
| 17587 | UChar vRA_addr = ifieldRegA(theInstr); |
| 17588 | UChar s_field = IFIELD( theInstr, 11, 5 ); // st and six field |
| 17589 | UChar st = IFIELD( theInstr, 15, 1 ); // st |
| 17590 | UChar six = IFIELD( theInstr, 11, 4 ); // six field |
| 17591 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
| 17592 | |
| 17593 | IRTemp vA = newTemp(Ity_V128); |
| 17594 | IRTemp dst = newTemp(Ity_V128); |
| 17595 | assign( vA, getVReg(vRA_addr)); |
| 17596 | |
| 17597 | if (opc1 != 0x4) { |
| 17598 | vex_printf("dis_av_hash(ppc)(instr)\n"); |
| 17599 | return False; |
| 17600 | } |
| 17601 | |
| 17602 | switch (opc2) { |
| 17603 | case 0x682: // vshasigmaw |
| 17604 | DIP("vshasigmaw v%d,v%d,%u,%u\n", vRT_addr, vRA_addr, st, six); |
| 17605 | assign( dst, binop( Iop_SHA256, mkexpr( vA ), mkU8( s_field) ) ); |
| 17606 | putVReg( vRT_addr, mkexpr(dst)); |
| 17607 | return True; |
| 17608 | |
| 17609 | case 0x6C2: // vshasigmad, |
| 17610 | DIP("vshasigmad v%d,v%d,%u,%u\n", vRT_addr, vRA_addr, st, six); |
| 17611 | putVReg( vRT_addr, binop( Iop_SHA512, mkexpr( vA ), mkU8( s_field) ) ); |
| 17612 | return True; |
| 17613 | |
| 17614 | default: |
| 17615 | vex_printf("dis_av_hash(ppc)(opc2)\n"); |
| 17616 | return False; |
| 17617 | } |
| 17618 | return True; |
| 17619 | } |
| 17620 | |
| 17621 | /* |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 17622 | * This function is used by the Vector add/subtract [extended] modulo/carry |
| 17623 | * instructions. |
| 17624 | * - For the non-extended add instructions, the cin arg is set to zero. |
| 17625 | * - For the extended add instructions, cin is the integer value of |
| 17626 | * src3.bit[127]. |
| 17627 | * - For the non-extended subtract instructions, src1 is added to the one's |
| 17628 | * complement of src2 + 1. We re-use the cin argument to hold the '1' |
| 17629 | * value for this operation. |
| 17630 | * - For the extended subtract instructions, cin is the integer value of src3.bit[127]. |
| 17631 | */ |
| 17632 | static IRTemp _get_quad_modulo_or_carry(IRExpr * vecA, IRExpr * vecB, |
| 17633 | IRExpr * cin, Bool modulo) |
| 17634 | { |
| 17635 | IRTemp _vecA_32 = IRTemp_INVALID; |
| 17636 | IRTemp _vecB_32 = IRTemp_INVALID; |
| 17637 | IRTemp res_32 = IRTemp_INVALID; |
| 17638 | IRTemp result = IRTemp_INVALID; |
| 17639 | IRTemp tmp_result = IRTemp_INVALID; |
| 17640 | IRTemp carry = IRTemp_INVALID; |
| 17641 | Int i; |
| 17642 | IRExpr * _vecA_low64 = unop( Iop_V128to64, vecA ); |
| 17643 | IRExpr * _vecB_low64 = unop( Iop_V128to64, vecB ); |
| 17644 | IRExpr * _vecA_high64 = unop( Iop_V128HIto64, vecA ); |
| 17645 | IRExpr * _vecB_high64 = unop( Iop_V128HIto64, vecB ); |
| 17646 | |
| 17647 | for (i = 0; i < 4; i++) { |
| 17648 | _vecA_32 = newTemp(Ity_I32); |
| 17649 | _vecB_32 = newTemp(Ity_I32); |
| 17650 | res_32 = newTemp(Ity_I32); |
| 17651 | switch (i) { |
| 17652 | case 0: |
| 17653 | assign(_vecA_32, unop( Iop_64to32, _vecA_low64 ) ); |
| 17654 | assign(_vecB_32, unop( Iop_64to32, _vecB_low64 ) ); |
| 17655 | break; |
| 17656 | case 1: |
| 17657 | assign(_vecA_32, unop( Iop_64HIto32, _vecA_low64 ) ); |
| 17658 | assign(_vecB_32, unop( Iop_64HIto32, _vecB_low64 ) ); |
| 17659 | break; |
| 17660 | case 2: |
| 17661 | assign(_vecA_32, unop( Iop_64to32, _vecA_high64 ) ); |
| 17662 | assign(_vecB_32, unop( Iop_64to32, _vecB_high64 ) ); |
| 17663 | break; |
| 17664 | case 3: |
| 17665 | assign(_vecA_32, unop( Iop_64HIto32, _vecA_high64 ) ); |
| 17666 | assign(_vecB_32, unop( Iop_64HIto32, _vecB_high64 ) ); |
| 17667 | break; |
| 17668 | } |
| 17669 | |
| 17670 | assign(res_32, binop( Iop_Add32, |
| 17671 | binop( Iop_Add32, |
| 17672 | binop ( Iop_Add32, |
| 17673 | mkexpr(_vecA_32), |
| 17674 | mkexpr(_vecB_32) ), |
| 17675 | (i == 0) ? mkU32(0) : mkexpr(carry) ), |
| 17676 | (i == 0) ? cin : mkU32(0) ) ); |
| 17677 | if (modulo) { |
| 17678 | result = newTemp(Ity_V128); |
| 17679 | assign(result, binop( Iop_OrV128, |
| 17680 | (i == 0) ? binop( Iop_64HLtoV128, |
| 17681 | mkU64(0), |
| 17682 | mkU64(0) ) : mkexpr(tmp_result), |
| 17683 | binop( Iop_ShlV128, |
| 17684 | binop( Iop_64HLtoV128, |
| 17685 | mkU64(0), |
| 17686 | binop( Iop_32HLto64, |
| 17687 | mkU32(0), |
| 17688 | mkexpr(res_32) ) ), |
| 17689 | mkU8(i * 32) ) ) ); |
| 17690 | tmp_result = newTemp(Ity_V128); |
| 17691 | assign(tmp_result, mkexpr(result)); |
| 17692 | } |
| 17693 | carry = newTemp(Ity_I32); |
| 17694 | assign(carry, unop(Iop_1Uto32, binop( Iop_CmpLT32U, |
| 17695 | mkexpr(res_32), |
| 17696 | mkexpr(_vecA_32 ) ) ) ); |
| 17697 | } |
| 17698 | if (modulo) |
| 17699 | return result; |
| 17700 | else |
| 17701 | return carry; |
| 17702 | } |
| 17703 | |
| 17704 | |
| 17705 | static Bool dis_av_quad ( UInt theInstr ) |
| 17706 | { |
| 17707 | /* VX-Form */ |
| 17708 | UChar opc1 = ifieldOPC(theInstr); |
| 17709 | UChar vRT_addr = ifieldRegDS(theInstr); |
| 17710 | UChar vRA_addr = ifieldRegA(theInstr); |
| 17711 | UChar vRB_addr = ifieldRegB(theInstr); |
| 17712 | UChar vRC_addr; |
| 17713 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
| 17714 | |
| 17715 | IRTemp vA = newTemp(Ity_V128); |
| 17716 | IRTemp vB = newTemp(Ity_V128); |
| 17717 | IRTemp vC = IRTemp_INVALID; |
| 17718 | IRTemp cin = IRTemp_INVALID; |
| 17719 | assign( vA, getVReg(vRA_addr)); |
| 17720 | assign( vB, getVReg(vRB_addr)); |
| 17721 | |
| 17722 | if (opc1 != 0x4) { |
| 17723 | vex_printf("dis_av_quad(ppc)(instr)\n"); |
| 17724 | return False; |
| 17725 | } |
| 17726 | |
| 17727 | switch (opc2) { |
| 17728 | case 0x140: // vaddcuq |
| 17729 | DIP("vaddcuq v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr); |
| 17730 | putVReg( vRT_addr, unop( Iop_32UtoV128, |
| 17731 | mkexpr(_get_quad_modulo_or_carry(mkexpr(vA), |
| 17732 | mkexpr(vB), |
| 17733 | mkU32(0), False) ) ) ); |
| 17734 | return True; |
| 17735 | case 0x100: // vadduqm |
| 17736 | DIP("vadduqm v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr); |
| 17737 | putVReg( vRT_addr, mkexpr(_get_quad_modulo_or_carry(mkexpr(vA), |
| 17738 | mkexpr(vB), mkU32(0), True) ) ); |
| 17739 | return True; |
| 17740 | case 0x540: // vsubcuq |
| 17741 | DIP("vsubcuq v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr); |
| 17742 | putVReg( vRT_addr, |
| 17743 | unop( Iop_32UtoV128, |
| 17744 | mkexpr(_get_quad_modulo_or_carry(mkexpr(vA), |
| 17745 | unop( Iop_NotV128, |
| 17746 | mkexpr(vB) ), |
| 17747 | mkU32(1), False) ) ) ); |
| 17748 | return True; |
| 17749 | case 0x500: // vsubuqm |
| 17750 | DIP("vsubuqm v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr); |
| 17751 | putVReg( vRT_addr, |
| 17752 | mkexpr(_get_quad_modulo_or_carry(mkexpr(vA), |
| 17753 | unop( Iop_NotV128, mkexpr(vB) ), |
| 17754 | mkU32(1), True) ) ); |
| 17755 | return True; |
| 17756 | case 0x054C: // vbpermq |
| 17757 | { |
| 17758 | #define BPERMD_IDX_MASK 0x00000000000000FFULL |
| 17759 | #define BPERMD_BIT_MASK 0x8000000000000000ULL |
| 17760 | int i; |
| 17761 | IRExpr * vB_expr = mkexpr(vB); |
| 17762 | IRExpr * res = binop(Iop_AndV128, mkV128(0), mkV128(0)); |
| 17763 | DIP("vbpermq v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr); |
| 17764 | for (i = 0; i < 16; i++) { |
| 17765 | IRTemp idx_tmp = newTemp( Ity_V128 ); |
| 17766 | IRTemp perm_bit = newTemp( Ity_V128 ); |
| 17767 | IRTemp idx = newTemp( Ity_I8 ); |
| 17768 | IRTemp idx_LT127 = newTemp( Ity_I1 ); |
| 17769 | IRTemp idx_LT127_ity128 = newTemp( Ity_V128 ); |
| 17770 | |
| 17771 | assign( idx_tmp, |
| 17772 | binop( Iop_AndV128, |
| 17773 | binop( Iop_64HLtoV128, |
| 17774 | mkU64(0), |
| 17775 | mkU64(BPERMD_IDX_MASK) ), |
| 17776 | vB_expr ) ); |
| 17777 | assign( idx_LT127, |
| 17778 | binop( Iop_CmpEQ32, |
| 17779 | unop ( Iop_64to32, |
| 17780 | unop( Iop_V128to64, binop( Iop_ShrV128, |
| 17781 | mkexpr(idx_tmp), |
| 17782 | mkU8(7) ) ) ), |
| 17783 | mkU32(0) ) ); |
| 17784 | |
| 17785 | /* Below, we set idx to determine which bit of vA to use for the |
| 17786 | * perm bit. If idx_LT127 is 0, the perm bit is forced to '0'. |
| 17787 | */ |
| 17788 | assign( idx, |
| 17789 | binop( Iop_And8, |
| 17790 | unop( Iop_1Sto8, |
| 17791 | mkexpr(idx_LT127) ), |
| 17792 | unop( Iop_32to8, |
| 17793 | unop( Iop_V128to32, mkexpr( idx_tmp ) ) ) ) ); |
| 17794 | |
| 17795 | assign( idx_LT127_ity128, |
| 17796 | binop( Iop_64HLtoV128, |
| 17797 | mkU64(0), |
| 17798 | unop( Iop_32Uto64, |
| 17799 | unop( Iop_1Uto32, mkexpr(idx_LT127 ) ) ) ) ); |
| 17800 | assign( perm_bit, |
| 17801 | binop( Iop_AndV128, |
| 17802 | mkexpr( idx_LT127_ity128 ), |
| 17803 | binop( Iop_ShrV128, |
| 17804 | binop( Iop_AndV128, |
| 17805 | binop (Iop_64HLtoV128, |
| 17806 | mkU64( BPERMD_BIT_MASK ), |
| 17807 | mkU64(0)), |
| 17808 | binop( Iop_ShlV128, |
| 17809 | mkexpr( vA ), |
| 17810 | mkexpr( idx ) ) ), |
| 17811 | mkU8( 127 ) ) ) ); |
| 17812 | res = binop( Iop_OrV128, |
| 17813 | res, |
| 17814 | binop( Iop_ShlV128, |
| 17815 | mkexpr( perm_bit ), |
| 17816 | mkU8( i ) ) ); |
| 17817 | vB_expr = binop( Iop_ShrV128, vB_expr, mkU8( 8 ) ); |
| 17818 | } |
| 17819 | putVReg( vRT_addr, res); |
| 17820 | return True; |
| 17821 | #undef BPERMD_IDX_MASK |
| 17822 | #undef BPERMD_BIT_MASK |
| 17823 | } |
| 17824 | |
| 17825 | default: |
| 17826 | break; // fall through |
| 17827 | } |
| 17828 | |
| 17829 | opc2 = IFIELD( theInstr, 0, 6 ); |
| 17830 | vRC_addr = ifieldRegC(theInstr); |
| 17831 | vC = newTemp(Ity_V128); |
| 17832 | cin = newTemp(Ity_I32); |
| 17833 | switch (opc2) { |
| 17834 | case 0x3D: // vaddecuq |
| 17835 | assign( vC, getVReg(vRC_addr)); |
| 17836 | DIP("vaddecuq v%d,v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr, |
| 17837 | vRC_addr); |
| 17838 | assign(cin, binop( Iop_And32, |
| 17839 | unop( Iop_64to32, |
| 17840 | unop( Iop_V128to64, mkexpr(vC) ) ), |
| 17841 | mkU32(1) ) ); |
| 17842 | putVReg( vRT_addr, |
| 17843 | unop( Iop_32UtoV128, |
| 17844 | mkexpr(_get_quad_modulo_or_carry(mkexpr(vA), mkexpr(vB), |
| 17845 | mkexpr(cin), |
| 17846 | False) ) ) ); |
| 17847 | return True; |
| 17848 | case 0x3C: // vaddeuqm |
| 17849 | assign( vC, getVReg(vRC_addr)); |
| 17850 | DIP("vaddeuqm v%d,v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr, |
| 17851 | vRC_addr); |
| 17852 | assign(cin, binop( Iop_And32, |
| 17853 | unop( Iop_64to32, |
| 17854 | unop( Iop_V128to64, mkexpr(vC) ) ), |
| 17855 | mkU32(1) ) ); |
| 17856 | putVReg( vRT_addr, |
| 17857 | mkexpr(_get_quad_modulo_or_carry(mkexpr(vA), mkexpr(vB), |
| 17858 | mkexpr(cin), |
| 17859 | True) ) ); |
| 17860 | return True; |
| 17861 | case 0x3F: // vsubecuq |
| 17862 | assign( vC, getVReg(vRC_addr)); |
| 17863 | DIP("vsubecuq v%d,v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr, |
| 17864 | vRC_addr); |
| 17865 | assign(cin, binop( Iop_And32, |
| 17866 | unop( Iop_64to32, |
| 17867 | unop( Iop_V128to64, mkexpr(vC) ) ), |
| 17868 | mkU32(1) ) ); |
| 17869 | putVReg( vRT_addr, |
| 17870 | unop( Iop_32UtoV128, |
| 17871 | mkexpr(_get_quad_modulo_or_carry(mkexpr(vA), |
| 17872 | unop( Iop_NotV128, |
| 17873 | mkexpr(vB) ), |
| 17874 | mkexpr(cin), |
| 17875 | False) ) ) ); |
| 17876 | return True; |
| 17877 | case 0x3E: // vsubeuqm |
| 17878 | assign( vC, getVReg(vRC_addr)); |
| 17879 | DIP("vsubeuqm v%d,v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr, |
| 17880 | vRC_addr); |
| 17881 | assign(cin, binop( Iop_And32, |
| 17882 | unop( Iop_64to32, |
| 17883 | unop( Iop_V128to64, mkexpr(vC) ) ), |
| 17884 | mkU32(1) ) ); |
| 17885 | putVReg( vRT_addr, |
| 17886 | mkexpr(_get_quad_modulo_or_carry(mkexpr(vA), |
| 17887 | unop( Iop_NotV128, mkexpr(vB) ), |
| 17888 | mkexpr(cin), |
| 17889 | True) ) ); |
| 17890 | return True; |
| 17891 | default: |
| 17892 | vex_printf("dis_av_quad(ppc)(opc2.2)\n"); |
| 17893 | return False; |
| 17894 | } |
| 17895 | |
| 17896 | return True; |
| 17897 | } |
| 17898 | |
| 17899 | |
| 17900 | /* |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 17901 | AltiVec BCD Arithmetic instructions. |
| 17902 | These instructions modify CR6 for various conditions in the result, |
| 17903 | including when an overflow occurs. We could easily detect all conditions |
| 17904 | except when an overflow occurs. But since we can't be 100% accurate |
| 17905 | in our emulation of CR6, it seems best to just not support it all. |
| 17906 | */ |
| 17907 | static Bool dis_av_bcd ( UInt theInstr ) |
| 17908 | { |
| 17909 | /* VX-Form */ |
| 17910 | UChar opc1 = ifieldOPC(theInstr); |
| 17911 | UChar vRT_addr = ifieldRegDS(theInstr); |
| 17912 | UChar vRA_addr = ifieldRegA(theInstr); |
| 17913 | UChar vRB_addr = ifieldRegB(theInstr); |
| 17914 | UChar ps = IFIELD( theInstr, 9, 1 ); |
| 17915 | UInt opc2 = IFIELD( theInstr, 0, 9 ); |
| 17916 | |
| 17917 | IRTemp vA = newTemp(Ity_V128); |
| 17918 | IRTemp vB = newTemp(Ity_V128); |
| 17919 | IRTemp dst = newTemp(Ity_V128); |
| 17920 | assign( vA, getVReg(vRA_addr)); |
| 17921 | assign( vB, getVReg(vRB_addr)); |
| 17922 | |
| 17923 | if (opc1 != 0x4) { |
| 17924 | vex_printf("dis_av_bcd(ppc)(instr)\n"); |
| 17925 | return False; |
| 17926 | } |
| 17927 | |
| 17928 | switch (opc2) { |
| 17929 | case 0x1: // bcdadd |
| 17930 | DIP("bcdadd. v%d,v%d,v%d,%u\n", vRT_addr, vRA_addr, vRB_addr, ps); |
| 17931 | assign( dst, triop( Iop_BCDAdd, mkexpr( vA ), |
| 17932 | mkexpr( vB ), mkU8( ps ) ) ); |
| 17933 | putVReg( vRT_addr, mkexpr(dst)); |
| 17934 | return True; |
| 17935 | |
| 17936 | case 0x41: // bcdsub |
| 17937 | DIP("bcdsub. v%d,v%d,v%d,%u\n", vRT_addr, vRA_addr, vRB_addr, ps); |
| 17938 | assign( dst, triop( Iop_BCDSub, mkexpr( vA ), |
| 17939 | mkexpr( vB ), mkU8( ps ) ) ); |
| 17940 | putVReg( vRT_addr, mkexpr(dst)); |
| 17941 | return True; |
| 17942 | |
| 17943 | default: |
| 17944 | vex_printf("dis_av_bcd(ppc)(opc2)\n"); |
| 17945 | return False; |
| 17946 | } |
| 17947 | return True; |
| 17948 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17949 | |
| 17950 | /* |
| 17951 | AltiVec Floating Point Arithmetic Instructions |
| 17952 | */ |
| 17953 | static Bool dis_av_fp_arith ( UInt theInstr ) |
| 17954 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 17955 | /* VA-Form */ |
| 17956 | UChar opc1 = ifieldOPC(theInstr); |
| 17957 | UChar vD_addr = ifieldRegDS(theInstr); |
| 17958 | UChar vA_addr = ifieldRegA(theInstr); |
| 17959 | UChar vB_addr = ifieldRegB(theInstr); |
| 17960 | UChar vC_addr = ifieldRegC(theInstr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17961 | UInt opc2=0; |
| 17962 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 17963 | IRTemp vA = newTemp(Ity_V128); |
| 17964 | IRTemp vB = newTemp(Ity_V128); |
| 17965 | IRTemp vC = newTemp(Ity_V128); |
| 17966 | assign( vA, getVReg(vA_addr)); |
| 17967 | assign( vB, getVReg(vB_addr)); |
| 17968 | assign( vC, getVReg(vC_addr)); |
| 17969 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17970 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17971 | vex_printf("dis_av_fp_arith(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17972 | return False; |
| 17973 | } |
| 17974 | |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 17975 | IRTemp rm = newTemp(Ity_I32); |
| 17976 | assign(rm, get_IR_roundingmode()); |
| 17977 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 17978 | opc2 = IFIELD( theInstr, 0, 6 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17979 | switch (opc2) { |
| 17980 | case 0x2E: // vmaddfp (Multiply Add FP, AV p177) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17981 | DIP("vmaddfp v%d,v%d,v%d,v%d\n", |
| 17982 | vD_addr, vA_addr, vC_addr, vB_addr); |
| 17983 | putVReg( vD_addr, |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 17984 | triop(Iop_Add32Fx4, mkU32(Irrm_NEAREST), |
| 17985 | mkexpr(vB), |
| 17986 | triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), |
| 17987 | mkexpr(vA), mkexpr(vC))) ); |
cerion | f3f173c | 2005-11-14 02:37:44 +0000 | [diff] [blame] | 17988 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 17989 | |
cerion | f3f173c | 2005-11-14 02:37:44 +0000 | [diff] [blame] | 17990 | case 0x2F: { // vnmsubfp (Negative Multiply-Subtract FP, AV p215) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17991 | DIP("vnmsubfp v%d,v%d,v%d,v%d\n", |
| 17992 | vD_addr, vA_addr, vC_addr, vB_addr); |
| 17993 | putVReg( vD_addr, |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 17994 | triop(Iop_Sub32Fx4, mkU32(Irrm_NEAREST), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 17995 | mkexpr(vB), |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 17996 | triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), |
| 17997 | mkexpr(vA), mkexpr(vC))) ); |
cerion | f3f173c | 2005-11-14 02:37:44 +0000 | [diff] [blame] | 17998 | return True; |
| 17999 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18000 | |
| 18001 | default: |
| 18002 | break; // Fall through... |
| 18003 | } |
| 18004 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 18005 | opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18006 | switch (opc2) { |
| 18007 | case 0x00A: // vaddfp (Add FP, AV p137) |
| 18008 | DIP("vaddfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 18009 | putVReg( vD_addr, triop(Iop_Add32Fx4, |
| 18010 | mkU32(Irrm_NEAREST), mkexpr(vA), mkexpr(vB)) ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18011 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18012 | |
| 18013 | case 0x04A: // vsubfp (Subtract FP, AV p261) |
| 18014 | DIP("vsubfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 18015 | putVReg( vD_addr, triop(Iop_Sub32Fx4, |
| 18016 | mkU32(Irrm_NEAREST), mkexpr(vA), mkexpr(vB)) ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18017 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18018 | |
| 18019 | case 0x40A: // vmaxfp (Maximum FP, AV p178) |
| 18020 | DIP("vmaxfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18021 | putVReg( vD_addr, binop(Iop_Max32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 18022 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18023 | |
| 18024 | case 0x44A: // vminfp (Minimum FP, AV p187) |
| 18025 | DIP("vminfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18026 | putVReg( vD_addr, binop(Iop_Min32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 18027 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18028 | |
| 18029 | default: |
| 18030 | break; // Fall through... |
| 18031 | } |
| 18032 | |
| 18033 | |
| 18034 | if (vA_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18035 | vex_printf("dis_av_fp_arith(ppc)(vA_addr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18036 | return False; |
| 18037 | } |
| 18038 | |
| 18039 | switch (opc2) { |
| 18040 | case 0x10A: // vrefp (Reciprocal Esimate FP, AV p228) |
| 18041 | DIP("vrefp v%d,v%d\n", vD_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18042 | putVReg( vD_addr, unop(Iop_Recip32Fx4, mkexpr(vB)) ); |
| 18043 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18044 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18045 | case 0x14A: // vrsqrtefp (Reciprocal Sqrt Estimate FP, AV p237) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18046 | DIP("vrsqrtefp v%d,v%d\n", vD_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18047 | putVReg( vD_addr, unop(Iop_RSqrt32Fx4, mkexpr(vB)) ); |
| 18048 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18049 | |
| 18050 | case 0x18A: // vexptefp (2 Raised to the Exp Est FP, AV p173) |
| 18051 | DIP("vexptefp v%d,v%d\n", vD_addr, vB_addr); |
| 18052 | DIP(" => not implemented\n"); |
| 18053 | return False; |
| 18054 | |
| 18055 | case 0x1CA: // vlogefp (Log2 Estimate FP, AV p175) |
| 18056 | DIP("vlogefp v%d,v%d\n", vD_addr, vB_addr); |
| 18057 | DIP(" => not implemented\n"); |
| 18058 | return False; |
| 18059 | |
| 18060 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18061 | vex_printf("dis_av_fp_arith(ppc)(opc2=0x%x)\n",opc2); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18062 | return False; |
| 18063 | } |
| 18064 | return True; |
| 18065 | } |
| 18066 | |
| 18067 | /* |
| 18068 | AltiVec Floating Point Compare Instructions |
| 18069 | */ |
| 18070 | static Bool dis_av_fp_cmp ( UInt theInstr ) |
| 18071 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 18072 | /* VXR-Form */ |
| 18073 | UChar opc1 = ifieldOPC(theInstr); |
| 18074 | UChar vD_addr = ifieldRegDS(theInstr); |
| 18075 | UChar vA_addr = ifieldRegA(theInstr); |
| 18076 | UChar vB_addr = ifieldRegB(theInstr); |
| 18077 | UChar flag_rC = ifieldBIT10(theInstr); |
| 18078 | UInt opc2 = IFIELD( theInstr, 0, 10 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18079 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18080 | Bool cmp_bounds = False; |
| 18081 | |
| 18082 | IRTemp vA = newTemp(Ity_V128); |
| 18083 | IRTemp vB = newTemp(Ity_V128); |
| 18084 | IRTemp vD = newTemp(Ity_V128); |
| 18085 | assign( vA, getVReg(vA_addr)); |
| 18086 | assign( vB, getVReg(vB_addr)); |
| 18087 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18088 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18089 | vex_printf("dis_av_fp_cmp(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18090 | return False; |
| 18091 | } |
| 18092 | |
| 18093 | switch (opc2) { |
| 18094 | case 0x0C6: // vcmpeqfp (Compare Equal-to FP, AV p159) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18095 | DIP("vcmpeqfp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 18096 | vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18097 | assign( vD, binop(Iop_CmpEQ32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 18098 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18099 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18100 | case 0x1C6: // vcmpgefp (Compare Greater-than-or-Equal-to, AV p163) |
| 18101 | DIP("vcmpgefp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 18102 | vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18103 | assign( vD, binop(Iop_CmpGE32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 18104 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18105 | |
| 18106 | case 0x2C6: // vcmpgtfp (Compare Greater-than FP, AV p164) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18107 | DIP("vcmpgtfp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 18108 | vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18109 | assign( vD, binop(Iop_CmpGT32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 18110 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18111 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18112 | case 0x3C6: { // vcmpbfp (Compare Bounds FP, AV p157) |
| 18113 | IRTemp gt = newTemp(Ity_V128); |
| 18114 | IRTemp lt = newTemp(Ity_V128); |
| 18115 | IRTemp zeros = newTemp(Ity_V128); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18116 | DIP("vcmpbfp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 18117 | vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18118 | cmp_bounds = True; |
| 18119 | assign( zeros, unop(Iop_Dup32x4, mkU32(0)) ); |
| 18120 | |
| 18121 | /* Note: making use of fact that the ppc backend for compare insns |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18122 | return zero'd lanes if either of the corresponding arg lanes is |
| 18123 | a nan. |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18124 | |
| 18125 | Perhaps better to have an irop Iop_isNan32Fx4, but then we'd |
| 18126 | need this for the other compares too (vcmpeqfp etc)... |
| 18127 | Better still, tighten down the spec for compare irops. |
| 18128 | */ |
| 18129 | assign( gt, unop(Iop_NotV128, |
| 18130 | binop(Iop_CmpLE32Fx4, mkexpr(vA), mkexpr(vB))) ); |
| 18131 | assign( lt, unop(Iop_NotV128, |
| 18132 | binop(Iop_CmpGE32Fx4, mkexpr(vA), |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 18133 | triop(Iop_Sub32Fx4, mkU32(Irrm_NEAREST), |
| 18134 | mkexpr(zeros), |
| 18135 | mkexpr(vB)))) ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18136 | |
| 18137 | // finally, just shift gt,lt to correct position |
| 18138 | assign( vD, binop(Iop_ShlN32x4, |
| 18139 | binop(Iop_OrV128, |
| 18140 | binop(Iop_AndV128, mkexpr(gt), |
| 18141 | unop(Iop_Dup32x4, mkU32(0x2))), |
| 18142 | binop(Iop_AndV128, mkexpr(lt), |
| 18143 | unop(Iop_Dup32x4, mkU32(0x1)))), |
| 18144 | mkU8(30)) ); |
| 18145 | break; |
| 18146 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18147 | |
| 18148 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18149 | vex_printf("dis_av_fp_cmp(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18150 | return False; |
| 18151 | } |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18152 | |
| 18153 | putVReg( vD_addr, mkexpr(vD) ); |
| 18154 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 18155 | if (flag_rC) { |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 18156 | set_AV_CR6( mkexpr(vD), !cmp_bounds ); |
| 18157 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18158 | return True; |
| 18159 | } |
| 18160 | |
| 18161 | /* |
| 18162 | AltiVec Floating Point Convert/Round Instructions |
| 18163 | */ |
| 18164 | static Bool dis_av_fp_convert ( UInt theInstr ) |
| 18165 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 18166 | /* VX-Form */ |
| 18167 | UChar opc1 = ifieldOPC(theInstr); |
| 18168 | UChar vD_addr = ifieldRegDS(theInstr); |
| 18169 | UChar UIMM_5 = ifieldRegA(theInstr); |
| 18170 | UChar vB_addr = ifieldRegB(theInstr); |
| 18171 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18172 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 18173 | IRTemp vB = newTemp(Ity_V128); |
| 18174 | IRTemp vScale = newTemp(Ity_V128); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18175 | IRTemp vInvScale = newTemp(Ity_V128); |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 18176 | |
| 18177 | float scale, inv_scale; |
| 18178 | |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18179 | assign( vB, getVReg(vB_addr)); |
| 18180 | |
| 18181 | /* scale = 2^UIMM, cast to float, reinterpreted as uint */ |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 18182 | scale = (float)( (unsigned int) 1<<UIMM_5 ); |
sewardj | 2ead522 | 2005-11-23 03:53:45 +0000 | [diff] [blame] | 18183 | assign( vScale, unop(Iop_Dup32x4, mkU32( float_to_bits(scale) )) ); |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 18184 | inv_scale = 1/scale; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18185 | assign( vInvScale, |
| 18186 | unop(Iop_Dup32x4, mkU32( float_to_bits(inv_scale) )) ); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18187 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18188 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18189 | vex_printf("dis_av_fp_convert(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18190 | return False; |
| 18191 | } |
| 18192 | |
| 18193 | switch (opc2) { |
| 18194 | case 0x30A: // vcfux (Convert from Unsigned Fixed-Point W, AV p156) |
| 18195 | DIP("vcfux v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 18196 | putVReg( vD_addr, triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18197 | unop(Iop_I32UtoFx4, mkexpr(vB)), |
| 18198 | mkexpr(vInvScale)) ); |
| 18199 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18200 | |
| 18201 | case 0x34A: // vcfsx (Convert from Signed Fixed-Point W, AV p155) |
| 18202 | DIP("vcfsx v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18203 | |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 18204 | putVReg( vD_addr, triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18205 | unop(Iop_I32StoFx4, mkexpr(vB)), |
| 18206 | mkexpr(vInvScale)) ); |
| 18207 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18208 | |
| 18209 | case 0x38A: // vctuxs (Convert to Unsigned Fixed-Point W Saturate, AV p172) |
| 18210 | DIP("vctuxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18211 | putVReg( vD_addr, |
| 18212 | unop(Iop_QFtoI32Ux4_RZ, |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 18213 | triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), |
| 18214 | mkexpr(vB), mkexpr(vScale))) ); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18215 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18216 | |
| 18217 | case 0x3CA: // vctsxs (Convert to Signed Fixed-Point W Saturate, AV p171) |
| 18218 | DIP("vctsxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18219 | putVReg( vD_addr, |
| 18220 | unop(Iop_QFtoI32Sx4_RZ, |
sewardj | 20a760e | 2014-05-05 10:03:56 +0000 | [diff] [blame] | 18221 | triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), |
| 18222 | mkexpr(vB), mkexpr(vScale))) ); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18223 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18224 | |
| 18225 | default: |
| 18226 | break; // Fall through... |
| 18227 | } |
| 18228 | |
| 18229 | if (UIMM_5 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18230 | vex_printf("dis_av_fp_convert(ppc)(UIMM_5)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18231 | return False; |
| 18232 | } |
| 18233 | |
| 18234 | switch (opc2) { |
| 18235 | case 0x20A: // vrfin (Round to FP Integer Nearest, AV p231) |
| 18236 | DIP("vrfin v%d,v%d\n", vD_addr, vB_addr); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18237 | putVReg( vD_addr, unop(Iop_RoundF32x4_RN, mkexpr(vB)) ); |
| 18238 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18239 | |
| 18240 | case 0x24A: // vrfiz (Round to FP Integer toward zero, AV p233) |
| 18241 | DIP("vrfiz v%d,v%d\n", vD_addr, vB_addr); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18242 | putVReg( vD_addr, unop(Iop_RoundF32x4_RZ, mkexpr(vB)) ); |
| 18243 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18244 | |
| 18245 | case 0x28A: // vrfip (Round to FP Integer toward +inf, AV p232) |
| 18246 | DIP("vrfip v%d,v%d\n", vD_addr, vB_addr); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18247 | putVReg( vD_addr, unop(Iop_RoundF32x4_RP, mkexpr(vB)) ); |
| 18248 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18249 | |
| 18250 | case 0x2CA: // vrfim (Round to FP Integer toward -inf, AV p230) |
| 18251 | DIP("vrfim v%d,v%d\n", vD_addr, vB_addr); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 18252 | putVReg( vD_addr, unop(Iop_RoundF32x4_RM, mkexpr(vB)) ); |
| 18253 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18254 | |
| 18255 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18256 | vex_printf("dis_av_fp_convert(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 18257 | return False; |
| 18258 | } |
| 18259 | return True; |
| 18260 | } |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 18261 | |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 18262 | static Bool dis_transactional_memory ( UInt theInstr, UInt nextInstr, |
| 18263 | VexAbiInfo* vbi, |
| 18264 | /*OUT*/DisResult* dres, |
| 18265 | Bool (*resteerOkFn)(void*,Addr64), |
| 18266 | void* callback_opaque ) |
| 18267 | { |
| 18268 | UInt opc2 = IFIELD( theInstr, 1, 10 ); |
| 18269 | |
| 18270 | switch (opc2) { |
| 18271 | case 0x28E: { //tbegin. |
| 18272 | /* The current implementation is to just fail the tbegin and execute |
| 18273 | * the failure path. The failure path is assumed to be functionaly |
| 18274 | * equivalent to the transactional path with the needed data locking |
| 18275 | * to ensure correctness. The tend is just a noop and shouldn't |
| 18276 | * actually get executed. |
| 18277 | * 1) set cr0 to 0x2 |
| 18278 | * 2) Initialize TFHAR to CIA+4 |
| 18279 | * 3) Initialize TEXASR |
| 18280 | * 4) Initialize TFIAR (probably to CIA, ie, the address of tbegin.) |
| 18281 | * 5) Continue executing at the next instruction. |
| 18282 | */ |
| 18283 | UInt R = IFIELD( theInstr, 21, 1 ); |
| 18284 | |
| 18285 | ULong tm_reason; |
| 18286 | UInt failure_code = 0; /* Forcing failure, will not be due to tabort |
| 18287 | * or treclaim. |
| 18288 | */ |
| 18289 | UInt persistant = 1; /* set persistant since we are always failing |
| 18290 | * the tbegin. |
| 18291 | */ |
| 18292 | UInt nest_overflow = 1; /* Alowed nesting depth overflow, we use this |
| 18293 | as the reason for failing the trasaction */ |
| 18294 | UInt tm_exact = 1; /* have exact address for failure */ |
| 18295 | |
| 18296 | DIP("tbegin. %d\n", R); |
| 18297 | |
| 18298 | /* Set the CR0 field to indicate the tbegin failed. Then let |
| 18299 | * the code do the branch to the failure path. |
| 18300 | * |
| 18301 | * 000 || 0 Transaction initiation successful, |
| 18302 | * unnested (Transaction state of |
| 18303 | * Non-transactional prior to tbegin.) |
| 18304 | * 010 || 0 Transaction initiation successful, nested |
| 18305 | * (Transaction state of Transactional |
| 18306 | * prior to tbegin.) |
| 18307 | * 001 || 0 Transaction initiation unsuccessful, |
| 18308 | * (Transaction state of Suspended prior |
| 18309 | * to tbegin.) |
| 18310 | */ |
| 18311 | putCR321( 0, mkU8( 0x2 ) ); |
| 18312 | |
| 18313 | tm_reason = generate_TMreason( failure_code, persistant, |
| 18314 | nest_overflow, tm_exact ); |
| 18315 | |
| 18316 | storeTMfailure( guest_CIA_curr_instr, tm_reason, |
| 18317 | guest_CIA_curr_instr+4 ); |
| 18318 | |
| 18319 | return True; |
| 18320 | |
| 18321 | break; |
| 18322 | } |
| 18323 | |
| 18324 | case 0x2AE: { //tend. |
| 18325 | /* The tend. is just a noop. Do nothing */ |
| 18326 | UInt A = IFIELD( theInstr, 25, 1 ); |
| 18327 | |
| 18328 | DIP("tend. %d\n", A); |
| 18329 | break; |
| 18330 | } |
| 18331 | |
| 18332 | case 0x2EE: { //tsr. |
| 18333 | /* The tsr. is just a noop. Do nothing */ |
| 18334 | UInt L = IFIELD( theInstr, 21, 1 ); |
| 18335 | |
| 18336 | DIP("tsr. %d\n", L); |
| 18337 | break; |
| 18338 | } |
| 18339 | |
| 18340 | case 0x2CE: { //tcheck. |
| 18341 | /* The tcheck. is just a noop. Do nothing */ |
| 18342 | UInt BF = IFIELD( theInstr, 25, 1 ); |
| 18343 | |
| 18344 | DIP("tcheck. %d\n", BF); |
| 18345 | break; |
| 18346 | } |
| 18347 | |
| 18348 | case 0x30E: { //tbortwc. |
| 18349 | /* The tabortwc. is just a noop. Do nothing */ |
| 18350 | UInt TO = IFIELD( theInstr, 25, 1 ); |
| 18351 | UInt RA = IFIELD( theInstr, 16, 5 ); |
| 18352 | UInt RB = IFIELD( theInstr, 11, 5 ); |
| 18353 | |
| 18354 | DIP("tabortwc. %d,%d,%d\n", TO, RA, RB); |
| 18355 | break; |
| 18356 | } |
| 18357 | |
| 18358 | case 0x32E: { //tbortdc. |
| 18359 | /* The tabortdc. is just a noop. Do nothing */ |
| 18360 | UInt TO = IFIELD( theInstr, 25, 1 ); |
| 18361 | UInt RA = IFIELD( theInstr, 16, 5 ); |
| 18362 | UInt RB = IFIELD( theInstr, 11, 5 ); |
| 18363 | |
| 18364 | DIP("tabortdc. %d,%d,%d\n", TO, RA, RB); |
| 18365 | break; |
| 18366 | } |
| 18367 | |
| 18368 | case 0x34E: { //tbortwci. |
| 18369 | /* The tabortwci. is just a noop. Do nothing */ |
| 18370 | UInt TO = IFIELD( theInstr, 25, 1 ); |
| 18371 | UInt RA = IFIELD( theInstr, 16, 5 ); |
| 18372 | UInt SI = IFIELD( theInstr, 11, 5 ); |
| 18373 | |
| 18374 | DIP("tabortwci. %d,%d,%d\n", TO, RA, SI); |
| 18375 | break; |
| 18376 | } |
| 18377 | |
| 18378 | case 0x36E: { //tbortdci. |
| 18379 | /* The tabortdci. is just a noop. Do nothing */ |
| 18380 | UInt TO = IFIELD( theInstr, 25, 1 ); |
| 18381 | UInt RA = IFIELD( theInstr, 16, 5 ); |
| 18382 | UInt SI = IFIELD( theInstr, 11, 5 ); |
| 18383 | |
| 18384 | DIP("tabortdci. %d,%d,%d\n", TO, RA, SI); |
| 18385 | break; |
| 18386 | } |
| 18387 | |
| 18388 | case 0x38E: { //tbort. |
| 18389 | /* The tabort. is just a noop. Do nothing */ |
| 18390 | UInt RA = IFIELD( theInstr, 16, 5 ); |
| 18391 | |
| 18392 | DIP("tabort. %d\n", RA); |
| 18393 | break; |
| 18394 | } |
| 18395 | |
carll | fcce5f8 | 2013-10-09 17:52:01 +0000 | [diff] [blame] | 18396 | case 0x3AE: { //treclaim. |
| 18397 | /* The treclaim. is just a noop. Do nothing */ |
| 18398 | UInt RA = IFIELD( theInstr, 16, 5 ); |
| 18399 | |
| 18400 | DIP("treclaim. %d\n", RA); |
| 18401 | break; |
| 18402 | } |
| 18403 | |
| 18404 | case 0x3EE: { //trechkpt. |
| 18405 | /* The trechkpt. is just a noop. Do nothing */ |
| 18406 | DIP("trechkpt.\n"); |
| 18407 | break; |
| 18408 | } |
| 18409 | |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 18410 | default: |
| 18411 | vex_printf("dis_transactional_memory(ppc): unrecognized instruction\n"); |
| 18412 | return False; |
| 18413 | } |
| 18414 | |
| 18415 | return True; |
| 18416 | } |
| 18417 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 18418 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18419 | /* The 0x3C primary opcode (VSX category) uses several different forms of |
| 18420 | * extended opcodes: |
| 18421 | * o XX2-form: |
| 18422 | * - [10:2] (IBM notation [21:29]) |
| 18423 | * o XX3-form variants: |
| 18424 | * - variant 1: [10:3] (IBM notation [21:28]) |
| 18425 | * - variant 2: [9:3] (IBM notation [22:28]) |
| 18426 | * - variant 3: [7:3] (IBM notation [24:28]) |
| 18427 | * o XX-4 form: |
| 18428 | * - [10:6] (IBM notation [21:25]) |
| 18429 | * |
| 18430 | * The XX2-form needs bit 0 masked from the standard extended opcode |
| 18431 | * as returned by ifieldOPClo10; the XX3-form needs bits 0 and 1 masked; |
| 18432 | * and the XX4-form needs bits 0, 1, and 2 masked. Additionally, the |
| 18433 | * XX4 and XX3 (variants 2 and 3) forms need certain bits masked on the |
| 18434 | * front end since their encoding does not begin at bit 21 like the standard |
| 18435 | * format. |
| 18436 | * |
| 18437 | * The get_VSX60_opc2() function uses the vsx_insn array below to obtain the |
| 18438 | * secondary opcode for such VSX instructions. |
| 18439 | * |
| 18440 | */ |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 18441 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 18442 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18443 | struct vsx_insn { |
| 18444 | UInt opcode; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 18445 | const HChar * name; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18446 | }; |
| 18447 | |
| 18448 | // ATTENTION: Keep this array sorted on the opcocde!!! |
| 18449 | static struct vsx_insn vsx_all[] = { |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18450 | { 0x0, "xsaddsp" }, |
| 18451 | { 0x4, "xsmaddasp" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18452 | { 0x8, "xxsldwi" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18453 | { 0x14, "xsrsqrtesp" }, |
| 18454 | { 0x16, "xssqrtsp" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18455 | { 0x18, "xxsel" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18456 | { 0x20, "xssubsp" }, |
| 18457 | { 0x24, "xsmaddmsp" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18458 | { 0x28, "xxpermdi" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18459 | { 0x34, "xsresp" }, |
| 18460 | { 0x40, "xsmulsp" }, |
| 18461 | { 0x44, "xsmsubasp" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18462 | { 0x48, "xxmrghw" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18463 | { 0x60, "xsdivsp" }, |
| 18464 | { 0x64, "xsmsubmsp" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18465 | { 0x80, "xsadddp" }, |
| 18466 | { 0x84, "xsmaddadp" }, |
| 18467 | { 0x8c, "xscmpudp" }, |
| 18468 | { 0x90, "xscvdpuxws" }, |
| 18469 | { 0x92, "xsrdpi" }, |
| 18470 | { 0x94, "xsrsqrtedp" }, |
| 18471 | { 0x96, "xssqrtdp" }, |
| 18472 | { 0xa0, "xssubdp" }, |
| 18473 | { 0xa4, "xsmaddmdp" }, |
| 18474 | { 0xac, "xscmpodp" }, |
| 18475 | { 0xb0, "xscvdpsxws" }, |
| 18476 | { 0xb2, "xsrdpiz" }, |
| 18477 | { 0xb4, "xsredp" }, |
| 18478 | { 0xc0, "xsmuldp" }, |
| 18479 | { 0xc4, "xsmsubadp" }, |
| 18480 | { 0xc8, "xxmrglw" }, |
| 18481 | { 0xd2, "xsrdpip" }, |
| 18482 | { 0xd4, "xstsqrtdp" }, |
| 18483 | { 0xd6, "xsrdpic" }, |
| 18484 | { 0xe0, "xsdivdp" }, |
| 18485 | { 0xe4, "xsmsubmdp" }, |
| 18486 | { 0xf2, "xsrdpim" }, |
| 18487 | { 0xf4, "xstdivdp" }, |
| 18488 | { 0x100, "xvaddsp" }, |
| 18489 | { 0x104, "xvmaddasp" }, |
| 18490 | { 0x10c, "xvcmpeqsp" }, |
| 18491 | { 0x110, "xvcvspuxws" }, |
| 18492 | { 0x112, "xvrspi" }, |
| 18493 | { 0x114, "xvrsqrtesp" }, |
| 18494 | { 0x116, "xvsqrtsp" }, |
| 18495 | { 0x120, "xvsubsp" }, |
| 18496 | { 0x124, "xvmaddmsp" }, |
| 18497 | { 0x12c, "xvcmpgtsp" }, |
| 18498 | { 0x130, "xvcvspsxws" }, |
| 18499 | { 0x132, "xvrspiz" }, |
| 18500 | { 0x134, "xvresp" }, |
| 18501 | { 0x140, "xvmulsp" }, |
| 18502 | { 0x144, "xvmsubasp" }, |
| 18503 | { 0x148, "xxspltw" }, |
| 18504 | { 0x14c, "xvcmpgesp" }, |
| 18505 | { 0x150, "xvcvuxwsp" }, |
| 18506 | { 0x152, "xvrspip" }, |
| 18507 | { 0x154, "xvtsqrtsp" }, |
| 18508 | { 0x156, "xvrspic" }, |
| 18509 | { 0x160, "xvdivsp" }, |
| 18510 | { 0x164, "xvmsubmsp" }, |
| 18511 | { 0x170, "xvcvsxwsp" }, |
| 18512 | { 0x172, "xvrspim" }, |
| 18513 | { 0x174, "xvtdivsp" }, |
| 18514 | { 0x180, "xvadddp" }, |
| 18515 | { 0x184, "xvmaddadp" }, |
| 18516 | { 0x18c, "xvcmpeqdp" }, |
| 18517 | { 0x190, "xvcvdpuxws" }, |
| 18518 | { 0x192, "xvrdpi" }, |
| 18519 | { 0x194, "xvrsqrtedp" }, |
| 18520 | { 0x196, "xvsqrtdp" }, |
| 18521 | { 0x1a0, "xvsubdp" }, |
| 18522 | { 0x1a4, "xvmaddmdp" }, |
| 18523 | { 0x1ac, "xvcmpgtdp" }, |
| 18524 | { 0x1b0, "xvcvdpsxws" }, |
| 18525 | { 0x1b2, "xvrdpiz" }, |
| 18526 | { 0x1b4, "xvredp" }, |
| 18527 | { 0x1c0, "xvmuldp" }, |
| 18528 | { 0x1c4, "xvmsubadp" }, |
| 18529 | { 0x1cc, "xvcmpgedp" }, |
| 18530 | { 0x1d0, "xvcvuxwdp" }, |
| 18531 | { 0x1d2, "xvrdpip" }, |
| 18532 | { 0x1d4, "xvtsqrtdp" }, |
| 18533 | { 0x1d6, "xvrdpic" }, |
| 18534 | { 0x1e0, "xvdivdp" }, |
| 18535 | { 0x1e4, "xvmsubmdp" }, |
| 18536 | { 0x1f0, "xvcvsxwdp" }, |
| 18537 | { 0x1f2, "xvrdpim" }, |
| 18538 | { 0x1f4, "xvtdivdp" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18539 | { 0x204, "xsnmaddasp" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18540 | { 0x208, "xxland" }, |
| 18541 | { 0x212, "xscvdpsp" }, |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 18542 | { 0x216, "xscvdpspn" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18543 | { 0x224, "xsnmaddmsp" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18544 | { 0x228, "xxlandc" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18545 | { 0x232, "xxrsp" }, |
| 18546 | { 0x244, "xsnmsubasp" }, |
| 18547 | { 0x248, "xxlor" }, |
| 18548 | { 0x250, "xscvuxdsp" }, |
| 18549 | { 0x264, "xsnmsubmsp" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18550 | { 0x268, "xxlxor" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18551 | { 0x270, "xscvsxdsp" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18552 | { 0x280, "xsmaxdp" }, |
| 18553 | { 0x284, "xsnmaddadp" }, |
| 18554 | { 0x288, "xxlnor" }, |
| 18555 | { 0x290, "xscvdpuxds" }, |
| 18556 | { 0x292, "xscvspdp" }, |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 18557 | { 0x296, "xscvspdpn" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18558 | { 0x2a0, "xsmindp" }, |
| 18559 | { 0x2a4, "xsnmaddmdp" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18560 | { 0x2a8, "xxlorc" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18561 | { 0x2b0, "xscvdpsxds" }, |
| 18562 | { 0x2b2, "xsabsdp" }, |
| 18563 | { 0x2c0, "xscpsgndp" }, |
| 18564 | { 0x2c4, "xsnmsubadp" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18565 | { 0x2c8, "xxlnand" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18566 | { 0x2d0, "xscvuxddp" }, |
| 18567 | { 0x2d2, "xsnabsdp" }, |
| 18568 | { 0x2e4, "xsnmsubmdp" }, |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 18569 | { 0x2e8, "xxleqv" }, |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18570 | { 0x2f0, "xscvsxddp" }, |
| 18571 | { 0x2f2, "xsnegdp" }, |
| 18572 | { 0x300, "xvmaxsp" }, |
| 18573 | { 0x304, "xvnmaddasp" }, |
| 18574 | { 0x30c, "xvcmpeqsp." }, |
| 18575 | { 0x310, "xvcvspuxds" }, |
| 18576 | { 0x312, "xvcvdpsp" }, |
| 18577 | { 0x320, "xvminsp" }, |
| 18578 | { 0x324, "xvnmaddmsp" }, |
| 18579 | { 0x32c, "xvcmpgtsp." }, |
| 18580 | { 0x330, "xvcvspsxds" }, |
| 18581 | { 0x332, "xvabssp" }, |
| 18582 | { 0x340, "xvcpsgnsp" }, |
| 18583 | { 0x344, "xvnmsubasp" }, |
| 18584 | { 0x34c, "xvcmpgesp." }, |
| 18585 | { 0x350, "xvcvuxdsp" }, |
| 18586 | { 0x352, "xvnabssp" }, |
| 18587 | { 0x364, "xvnmsubmsp" }, |
| 18588 | { 0x370, "xvcvsxdsp" }, |
| 18589 | { 0x372, "xvnegsp" }, |
| 18590 | { 0x380, "xvmaxdp" }, |
| 18591 | { 0x384, "xvnmaddadp" }, |
| 18592 | { 0x38c, "xvcmpeqdp." }, |
| 18593 | { 0x390, "xvcvdpuxds" }, |
| 18594 | { 0x392, "xvcvspdp" }, |
| 18595 | { 0x3a0, "xvmindp" }, |
| 18596 | { 0x3a4, "xvnmaddmdp" }, |
| 18597 | { 0x3ac, "xvcmpgtdp." }, |
| 18598 | { 0x3b0, "xvcvdpsxds" }, |
| 18599 | { 0x3b2, "xvabsdp" }, |
| 18600 | { 0x3c0, "xvcpsgndp" }, |
| 18601 | { 0x3c4, "xvnmsubadp" }, |
| 18602 | { 0x3cc, "xvcmpgedp." }, |
| 18603 | { 0x3d0, "xvcvuxddp" }, |
| 18604 | { 0x3d2, "xvnabsdp" }, |
| 18605 | { 0x3e4, "xvnmsubmdp" }, |
| 18606 | { 0x3f0, "xvcvsxddp" }, |
| 18607 | { 0x3f2, "xvnegdp" } |
| 18608 | }; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 18609 | #define VSX_ALL_LEN (sizeof vsx_all / sizeof *vsx_all) |
| 18610 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18611 | |
| 18612 | // ATTENTION: This search function assumes vsx_all array is sorted. |
| 18613 | static Int findVSXextOpCode(UInt opcode) |
| 18614 | { |
| 18615 | Int low, mid, high; |
| 18616 | low = 0; |
| 18617 | high = VSX_ALL_LEN - 1; |
| 18618 | while (low <= high) { |
| 18619 | mid = (low + high)/2; |
| 18620 | if (opcode < vsx_all[mid].opcode) |
| 18621 | high = mid - 1; |
| 18622 | else if (opcode > vsx_all[mid].opcode) |
| 18623 | low = mid + 1; |
| 18624 | else |
| 18625 | return mid; |
| 18626 | } |
| 18627 | return -1; |
| 18628 | } |
| 18629 | |
| 18630 | |
| 18631 | /* The full 10-bit extended opcode retrieved via ifieldOPClo10 is |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 18632 | * passed, and we then try to match it up with one of the VSX forms |
| 18633 | * below. |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18634 | */ |
| 18635 | static UInt get_VSX60_opc2(UInt opc2_full) |
| 18636 | { |
| 18637 | #define XX2_MASK 0x000003FE |
| 18638 | #define XX3_1_MASK 0x000003FC |
| 18639 | #define XX3_2_MASK 0x000001FC |
| 18640 | #define XX3_3_MASK 0x0000007C |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 18641 | #define XX4_MASK 0x00000018 |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18642 | Int ret; |
| 18643 | UInt vsxExtOpcode = 0; |
| 18644 | |
| 18645 | if (( ret = findVSXextOpCode(opc2_full & XX2_MASK)) >= 0) |
| 18646 | vsxExtOpcode = vsx_all[ret].opcode; |
| 18647 | else if (( ret = findVSXextOpCode(opc2_full & XX3_1_MASK)) >= 0) |
| 18648 | vsxExtOpcode = vsx_all[ret].opcode; |
| 18649 | else if (( ret = findVSXextOpCode(opc2_full & XX3_2_MASK)) >= 0) |
| 18650 | vsxExtOpcode = vsx_all[ret].opcode; |
| 18651 | else if (( ret = findVSXextOpCode(opc2_full & XX3_3_MASK)) >= 0) |
| 18652 | vsxExtOpcode = vsx_all[ret].opcode; |
| 18653 | else if (( ret = findVSXextOpCode(opc2_full & XX4_MASK)) >= 0) |
| 18654 | vsxExtOpcode = vsx_all[ret].opcode; |
| 18655 | |
| 18656 | return vsxExtOpcode; |
| 18657 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 18658 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18659 | /*------------------------------------------------------------*/ |
| 18660 | /*--- Disassemble a single instruction ---*/ |
| 18661 | /*------------------------------------------------------------*/ |
| 18662 | |
| 18663 | /* Disassemble a single instruction into IR. The instruction |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 18664 | is located in host memory at &guest_code[delta]. */ |
| 18665 | |
| 18666 | static |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 18667 | DisResult disInstr_PPC_WRK ( |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 18668 | Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 18669 | Bool resteerCisOk, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 18670 | void* callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 18671 | Long delta64, |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 18672 | VexArchInfo* archinfo, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 18673 | VexAbiInfo* abiinfo, |
| 18674 | Bool sigill_diag |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 18675 | ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18676 | { |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 18677 | UChar opc1; |
| 18678 | UInt opc2; |
| 18679 | DisResult dres; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18680 | UInt theInstr; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 18681 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18682 | Bool allow_F = False; |
| 18683 | Bool allow_V = False; |
| 18684 | Bool allow_FX = False; |
| 18685 | Bool allow_GX = False; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 18686 | Bool allow_VX = False; // Equates to "supports Power ISA 2.06 |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 18687 | Bool allow_DFP = False; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 18688 | Bool allow_isa_2_07 = False; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18689 | UInt hwcaps = archinfo->hwcaps; |
| 18690 | Long delta; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18691 | |
sewardj | 059601a | 2005-11-13 00:53:05 +0000 | [diff] [blame] | 18692 | /* What insn variants are we supporting today? */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18693 | if (mode64) { |
| 18694 | allow_F = True; |
| 18695 | allow_V = (0 != (hwcaps & VEX_HWCAPS_PPC64_V)); |
| 18696 | allow_FX = (0 != (hwcaps & VEX_HWCAPS_PPC64_FX)); |
| 18697 | allow_GX = (0 != (hwcaps & VEX_HWCAPS_PPC64_GX)); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18698 | allow_VX = (0 != (hwcaps & VEX_HWCAPS_PPC64_VX)); |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 18699 | allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC64_DFP)); |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 18700 | allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA2_07)); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18701 | } else { |
| 18702 | allow_F = (0 != (hwcaps & VEX_HWCAPS_PPC32_F)); |
| 18703 | allow_V = (0 != (hwcaps & VEX_HWCAPS_PPC32_V)); |
| 18704 | allow_FX = (0 != (hwcaps & VEX_HWCAPS_PPC32_FX)); |
| 18705 | allow_GX = (0 != (hwcaps & VEX_HWCAPS_PPC32_GX)); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18706 | allow_VX = (0 != (hwcaps & VEX_HWCAPS_PPC32_VX)); |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 18707 | allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC32_DFP)); |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 18708 | allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA2_07)); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18709 | } |
sewardj | 059601a | 2005-11-13 00:53:05 +0000 | [diff] [blame] | 18710 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 18711 | /* The running delta */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18712 | delta = (Long)mkSzAddr(ty, (ULong)delta64); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 18713 | |
| 18714 | /* Set result defaults. */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 18715 | dres.whatNext = Dis_Continue; |
| 18716 | dres.len = 0; |
| 18717 | dres.continueAt = 0; |
| 18718 | dres.jk_StopHere = Ijk_INVALID; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18719 | |
cerion | 1515db9 | 2005-01-25 17:21:23 +0000 | [diff] [blame] | 18720 | /* At least this is simple on PPC32: insns are all 4 bytes long, and |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18721 | 4-aligned. So just fish the whole thing out of memory right now |
| 18722 | and have done. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18723 | theInstr = getUIntPPCendianly( (UChar*)(&guest_code[delta]) ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18724 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18725 | if (0) vex_printf("insn: 0x%x\n", theInstr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 18726 | |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 18727 | DIP("\t0x%llx: ", (ULong)guest_CIA_curr_instr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 18728 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18729 | /* Spot "Special" instructions (see comment at top of file). */ |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 18730 | { |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18731 | UChar* code = (UChar*)(guest_code + delta); |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 18732 | /* Spot the 16-byte preamble: |
| 18733 | 32-bit mode: |
sewardj | 2171afd | 2014-02-10 12:27:29 +0000 | [diff] [blame] | 18734 | 5400183E rlwinm 0,0,3,0,31 |
| 18735 | 5400683E rlwinm 0,0,13,0,31 |
| 18736 | 5400E83E rlwinm 0,0,29,0,31 |
| 18737 | 5400983E rlwinm 0,0,19,0,31 |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 18738 | 64-bit mode: |
| 18739 | 78001800 rotldi 0,0,3 |
| 18740 | 78006800 rotldi 0,0,13 |
| 18741 | 7800E802 rotldi 0,0,61 |
| 18742 | 78009802 rotldi 0,0,51 |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18743 | */ |
sewardj | 2171afd | 2014-02-10 12:27:29 +0000 | [diff] [blame] | 18744 | UInt word1 = mode64 ? 0x78001800 : 0x5400183E; |
| 18745 | UInt word2 = mode64 ? 0x78006800 : 0x5400683E; |
| 18746 | UInt word3 = mode64 ? 0x7800E802 : 0x5400E83E; |
| 18747 | UInt word4 = mode64 ? 0x78009802 : 0x5400983E; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18748 | if (getUIntPPCendianly(code+ 0) == word1 && |
| 18749 | getUIntPPCendianly(code+ 4) == word2 && |
| 18750 | getUIntPPCendianly(code+ 8) == word3 && |
| 18751 | getUIntPPCendianly(code+12) == word4) { |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18752 | /* Got a "Special" instruction preamble. Which one is it? */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18753 | if (getUIntPPCendianly(code+16) == 0x7C210B78 /* or 1,1,1 */) { |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18754 | /* %R3 = client_request ( %R4 ) */ |
| 18755 | DIP("r3 = client_request ( %%r4 )\n"); |
| 18756 | delta += 20; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 18757 | putGST( PPC_GST_CIA, mkSzImm( ty, guest_CIA_bbstart + delta )); |
| 18758 | dres.jk_StopHere = Ijk_ClientReq; |
| 18759 | dres.whatNext = Dis_StopHere; |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18760 | goto decode_success; |
| 18761 | } |
| 18762 | else |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18763 | if (getUIntPPCendianly(code+16) == 0x7C421378 /* or 2,2,2 */) { |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18764 | /* %R3 = guest_NRADDR */ |
| 18765 | DIP("r3 = guest_NRADDR\n"); |
| 18766 | delta += 20; |
| 18767 | dres.len = 20; |
| 18768 | putIReg(3, IRExpr_Get( OFFB_NRADDR, ty )); |
| 18769 | goto decode_success; |
| 18770 | } |
| 18771 | else |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18772 | if (getUIntPPCendianly(code+16) == 0x7C631B78 /* or 3,3,3 */) { |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18773 | delta += 20; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18774 | if (host_endness == VexEndnessLE) { |
| 18775 | /* branch-and-link-to-noredir %R12 */ |
| 18776 | DIP("branch-and-link-to-noredir r12\n"); |
| 18777 | putGST( PPC_GST_LR, |
| 18778 | mkSzImm(ty, guest_CIA_bbstart + (Long)delta) ); |
| 18779 | putGST( PPC_GST_CIA, getIReg(12)); |
| 18780 | } else { |
| 18781 | /* branch-and-link-to-noredir %R11 */ |
| 18782 | DIP("branch-and-link-to-noredir r11\n"); |
| 18783 | putGST( PPC_GST_LR, |
| 18784 | mkSzImm(ty, guest_CIA_bbstart + (Long)delta) ); |
| 18785 | putGST( PPC_GST_CIA, getIReg(11)); |
| 18786 | } |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 18787 | dres.jk_StopHere = Ijk_NoRedir; |
| 18788 | dres.whatNext = Dis_StopHere; |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18789 | goto decode_success; |
| 18790 | } |
sewardj | 5ff11dd | 2006-01-20 14:19:25 +0000 | [diff] [blame] | 18791 | else |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18792 | if (getUIntPPCendianly(code+16) == 0x7C842378 /* or 4,4,4 */) { |
sewardj | 5ff11dd | 2006-01-20 14:19:25 +0000 | [diff] [blame] | 18793 | /* %R3 = guest_NRADDR_GPR2 */ |
| 18794 | DIP("r3 = guest_NRADDR_GPR2\n"); |
| 18795 | delta += 20; |
| 18796 | dres.len = 20; |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 18797 | putIReg(3, IRExpr_Get( OFFB_NRADDR_GPR2, ty )); |
sewardj | 5ff11dd | 2006-01-20 14:19:25 +0000 | [diff] [blame] | 18798 | goto decode_success; |
| 18799 | } |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 18800 | else |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18801 | if (getUIntPPCendianly(code+16) == 0x7CA52B78 /* or 5,5,5 */) { |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 18802 | DIP("IR injection\n"); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18803 | if (host_endness == VexEndnessBE) |
| 18804 | vex_inject_ir(irsb, Iend_BE); |
| 18805 | else |
| 18806 | vex_inject_ir(irsb, Iend_LE); |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 18807 | |
| 18808 | delta += 20; |
| 18809 | dres.len = 20; |
| 18810 | |
| 18811 | // Invalidate the current insn. The reason is that the IRop we're |
| 18812 | // injecting here can change. In which case the translation has to |
| 18813 | // be redone. For ease of handling, we simply invalidate all the |
| 18814 | // time. |
florian | 9e23873 | 2012-08-29 15:00:13 +0000 | [diff] [blame] | 18815 | |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 18816 | stmt(IRStmt_Put(OFFB_CMSTART, mkSzImm(ty, guest_CIA_curr_instr))); |
| 18817 | stmt(IRStmt_Put(OFFB_CMLEN, mkSzImm(ty, 20))); |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 18818 | |
| 18819 | putGST( PPC_GST_CIA, mkSzImm( ty, guest_CIA_bbstart + delta )); |
| 18820 | dres.whatNext = Dis_StopHere; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 18821 | dres.jk_StopHere = Ijk_InvalICache; |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 18822 | goto decode_success; |
| 18823 | } |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18824 | /* We don't know what it is. Set opc1/opc2 so decode_failure |
| 18825 | can print the insn following the Special-insn preamble. */ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 18826 | theInstr = getUIntPPCendianly(code+16); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 18827 | opc1 = ifieldOPC(theInstr); |
| 18828 | opc2 = ifieldOPClo10(theInstr); |
| 18829 | goto decode_failure; |
| 18830 | /*NOTREACHED*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18831 | } |
| 18832 | } |
| 18833 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 18834 | opc1 = ifieldOPC(theInstr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 18835 | opc2 = ifieldOPClo10(theInstr); |
cerion | 932ad94 | 2005-01-30 10:18:50 +0000 | [diff] [blame] | 18836 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 18837 | // Note: all 'reserved' bits must be cleared, else invalid |
| 18838 | switch (opc1) { |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18839 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 18840 | /* Integer Arithmetic Instructions */ |
| 18841 | case 0x0C: case 0x0D: case 0x0E: // addic, addic., addi |
| 18842 | case 0x0F: case 0x07: case 0x08: // addis, mulli, subfic |
| 18843 | if (dis_int_arith( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 18844 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 18845 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 18846 | /* Integer Compare Instructions */ |
| 18847 | case 0x0B: case 0x0A: // cmpi, cmpli |
| 18848 | if (dis_int_cmp( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 18849 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 18850 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 18851 | /* Integer Logical Instructions */ |
| 18852 | case 0x1C: case 0x1D: case 0x18: // andi., andis., ori |
| 18853 | case 0x19: case 0x1A: case 0x1B: // oris, xori, xoris |
| 18854 | if (dis_int_logic( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 18855 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 18856 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 18857 | /* Integer Rotate Instructions */ |
| 18858 | case 0x14: case 0x15: case 0x17: // rlwimi, rlwinm, rlwnm |
| 18859 | if (dis_int_rot( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 18860 | goto decode_failure; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 18861 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 18862 | /* 64bit Integer Rotate Instructions */ |
| 18863 | case 0x1E: // rldcl, rldcr, rldic, rldicl, rldicr, rldimi |
carll | bb3f401 | 2012-10-29 20:23:41 +0000 | [diff] [blame] | 18864 | if (!mode64) goto decode_failure; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 18865 | if (dis_int_rot( theInstr )) goto decode_success; |
| 18866 | goto decode_failure; |
| 18867 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 18868 | /* Integer Load Instructions */ |
| 18869 | case 0x22: case 0x23: case 0x2A: // lbz, lbzu, lha |
| 18870 | case 0x2B: case 0x28: case 0x29: // lhau, lhz, lhzu |
| 18871 | case 0x20: case 0x21: // lwz, lwzu |
| 18872 | if (dis_int_load( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 18873 | goto decode_failure; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 18874 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 18875 | /* Integer Store Instructions */ |
| 18876 | case 0x26: case 0x27: case 0x2C: // stb, stbu, sth |
| 18877 | case 0x2D: case 0x24: case 0x25: // sthu, stw, stwu |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 18878 | if (dis_int_store( theInstr, abiinfo )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 18879 | goto decode_failure; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 18880 | |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 18881 | /* Integer Load and Store Multiple Instructions */ |
| 18882 | case 0x2E: case 0x2F: // lmw, stmw |
| 18883 | if (dis_int_ldst_mult( theInstr )) goto decode_success; |
| 18884 | goto decode_failure; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 18885 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 18886 | /* Branch Instructions */ |
| 18887 | case 0x12: case 0x10: // b, bc |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 18888 | if (dis_branch(theInstr, abiinfo, &dres, |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 18889 | resteerOkFn, callback_opaque)) |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 18890 | goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 18891 | goto decode_failure; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 18892 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 18893 | /* System Linkage Instructions */ |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 18894 | case 0x11: // sc |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 18895 | if (dis_syslink(theInstr, abiinfo, &dres)) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 18896 | goto decode_failure; |
cerion | 26d07b2 | 2005-02-02 17:13:28 +0000 | [diff] [blame] | 18897 | |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 18898 | /* Trap Instructions */ |
carll | bb3f401 | 2012-10-29 20:23:41 +0000 | [diff] [blame] | 18899 | case 0x02: // tdi |
| 18900 | if (!mode64) goto decode_failure; |
| 18901 | if (dis_trapi(theInstr, &dres)) goto decode_success; |
| 18902 | goto decode_failure; |
| 18903 | |
| 18904 | case 0x03: // twi |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 18905 | if (dis_trapi(theInstr, &dres)) goto decode_success; |
| 18906 | goto decode_failure; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 18907 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 18908 | /* Floating Point Load Instructions */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 18909 | case 0x30: case 0x31: case 0x32: // lfs, lfsu, lfd |
| 18910 | case 0x33: // lfdu |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18911 | if (!allow_F) goto decode_noF; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 18912 | if (dis_fp_load( theInstr )) goto decode_success; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 18913 | goto decode_failure; |
cerion | 995bc36 | 2005-02-03 11:03:31 +0000 | [diff] [blame] | 18914 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 18915 | /* Floating Point Store Instructions */ |
| 18916 | case 0x34: case 0x35: case 0x36: // stfsx, stfsux, stfdx |
| 18917 | case 0x37: // stfdux |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18918 | if (!allow_F) goto decode_noF; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 18919 | if (dis_fp_store( theInstr )) goto decode_success; |
| 18920 | goto decode_failure; |
| 18921 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 18922 | /* Floating Point Load Double Pair Instructions */ |
| 18923 | case 0x39: case 0x3D: |
| 18924 | if (!allow_F) goto decode_noF; |
| 18925 | if (dis_fp_pair( theInstr )) goto decode_success; |
| 18926 | goto decode_failure; |
| 18927 | |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 18928 | /* 128-bit Integer Load */ |
| 18929 | case 0x38: // lq |
| 18930 | if (dis_int_load( theInstr )) goto decode_success; |
| 18931 | goto decode_failure; |
| 18932 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 18933 | /* 64bit Integer Loads */ |
| 18934 | case 0x3A: // ld, ldu, lwa |
| 18935 | if (!mode64) goto decode_failure; |
| 18936 | if (dis_int_load( theInstr )) goto decode_success; |
| 18937 | goto decode_failure; |
| 18938 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 18939 | case 0x3B: |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 18940 | if (!allow_F) goto decode_noF; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18941 | opc2 = ifieldOPClo10(theInstr); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 18942 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18943 | switch (opc2) { |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 18944 | case 0x2: // dadd - DFP Add |
| 18945 | case 0x202: // dsub - DFP Subtract |
| 18946 | case 0x22: // dmul - DFP Mult |
| 18947 | case 0x222: // ddiv - DFP Divide |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 18948 | if (!allow_DFP) goto decode_noDFP; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 18949 | if (dis_dfp_arith( theInstr )) |
| 18950 | goto decode_success; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 18951 | case 0x82: // dcmpo, DFP comparison ordered instruction |
| 18952 | case 0x282: // dcmpu, DFP comparison unordered instruction |
| 18953 | if (!allow_DFP) |
| 18954 | goto decode_failure; |
| 18955 | if (dis_dfp_compare( theInstr ) ) |
| 18956 | goto decode_success; |
| 18957 | goto decode_failure; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 18958 | case 0x102: // dctdp - DFP convert to DFP long |
| 18959 | case 0x302: // drsp - DFP round to dfp short |
| 18960 | case 0x122: // dctfix - DFP convert to fixed |
| 18961 | if (!allow_DFP) |
| 18962 | goto decode_failure; |
| 18963 | if (dis_dfp_fmt_conv( theInstr )) |
| 18964 | goto decode_success; |
| 18965 | goto decode_failure; |
| 18966 | case 0x322: // POWER 7 inst, dcffix - DFP convert from fixed |
| 18967 | if (!allow_VX) |
| 18968 | goto decode_failure; |
| 18969 | if (dis_dfp_fmt_conv( theInstr )) |
| 18970 | goto decode_success; |
| 18971 | goto decode_failure; |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 18972 | case 0x2A2: // dtstsf - DFP number of significant digits |
| 18973 | if (!allow_DFP) |
| 18974 | goto decode_failure; |
| 18975 | if (dis_dfp_significant_digits(theInstr)) |
| 18976 | goto decode_success; |
| 18977 | goto decode_failure; |
| 18978 | case 0x142: // ddedpd DFP Decode DPD to BCD |
| 18979 | case 0x342: // denbcd DFP Encode BCD to DPD |
| 18980 | if (!allow_DFP) |
| 18981 | goto decode_failure; |
| 18982 | if (dis_dfp_bcd(theInstr)) |
| 18983 | goto decode_success; |
| 18984 | goto decode_failure; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 18985 | case 0x162: // dxex - Extract exponent |
| 18986 | case 0x362: // diex - Insert exponent |
| 18987 | if (!allow_DFP) |
| 18988 | goto decode_failure; |
| 18989 | if (dis_dfp_extract_insert( theInstr ) ) |
| 18990 | goto decode_success; |
| 18991 | goto decode_failure; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 18992 | case 0x3CE: // fcfidus (implemented as native insn) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 18993 | if (!allow_VX) |
| 18994 | goto decode_noVX; |
| 18995 | if (dis_fp_round( theInstr )) |
| 18996 | goto decode_success; |
| 18997 | goto decode_failure; |
| 18998 | case 0x34E: // fcfids |
| 18999 | if (dis_fp_round( theInstr )) |
| 19000 | goto decode_success; |
| 19001 | goto decode_failure; |
| 19002 | } |
| 19003 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 19004 | opc2 = ifieldOPClo9( theInstr ); |
| 19005 | switch (opc2) { |
| 19006 | case 0x42: // dscli, DFP shift left |
| 19007 | case 0x62: // dscri, DFP shift right |
| 19008 | if (!allow_DFP) |
| 19009 | goto decode_failure; |
| 19010 | if (dis_dfp_shift( theInstr )) |
| 19011 | goto decode_success; |
| 19012 | goto decode_failure; |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 19013 | case 0xc2: // dtstdc, DFP test data class |
| 19014 | case 0xe2: // dtstdg, DFP test data group |
| 19015 | if (!allow_DFP) |
| 19016 | goto decode_failure; |
| 19017 | if (dis_dfp_class_test( theInstr )) |
| 19018 | goto decode_success; |
| 19019 | goto decode_failure; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 19020 | } |
| 19021 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 19022 | opc2 = ifieldOPClo8( theInstr ); |
| 19023 | switch (opc2) { |
| 19024 | case 0x3: // dqua - DFP Quantize |
| 19025 | case 0x23: // drrnd - DFP Reround |
| 19026 | case 0x43: // dquai - DFP Quantize immediate |
| 19027 | if (!allow_DFP) |
| 19028 | goto decode_failure; |
| 19029 | if (dis_dfp_quantize_sig_rrnd( theInstr ) ) |
| 19030 | goto decode_success; |
| 19031 | goto decode_failure; |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 19032 | case 0xA2: // dtstex - DFP Test exponent |
| 19033 | if (!allow_DFP) |
| 19034 | goto decode_failure; |
| 19035 | if (dis_dfp_exponent_test( theInstr ) ) |
| 19036 | goto decode_success; |
| 19037 | goto decode_failure; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 19038 | case 0x63: // drintx - Round to an integer value |
| 19039 | case 0xE3: // drintn - Round to an integer value |
| 19040 | if (!allow_DFP) |
| 19041 | goto decode_failure; |
| 19042 | if (dis_dfp_round( theInstr ) ) { |
| 19043 | goto decode_success; |
| 19044 | } |
| 19045 | goto decode_failure; |
| 19046 | default: |
| 19047 | break; /* fall through to next opc2 check */ |
| 19048 | } |
| 19049 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 19050 | opc2 = IFIELD(theInstr, 1, 5); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19051 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19052 | /* Floating Point Arith Instructions */ |
| 19053 | case 0x12: case 0x14: case 0x15: // fdivs, fsubs, fadds |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19054 | case 0x19: // fmuls |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19055 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 19056 | goto decode_failure; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19057 | case 0x16: // fsqrts |
| 19058 | if (!allow_FX) goto decode_noFX; |
| 19059 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 19060 | goto decode_failure; |
| 19061 | case 0x18: // fres |
| 19062 | if (!allow_GX) goto decode_noGX; |
| 19063 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 19064 | goto decode_failure; |
| 19065 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19066 | /* Floating Point Mult-Add Instructions */ |
| 19067 | case 0x1C: case 0x1D: case 0x1E: // fmsubs, fmadds, fnmsubs |
| 19068 | case 0x1F: // fnmadds |
| 19069 | if (dis_fp_multadd(theInstr)) goto decode_success; |
| 19070 | goto decode_failure; |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 19071 | |
| 19072 | case 0x1A: // frsqrtes |
| 19073 | if (!allow_GX) goto decode_noGX; |
| 19074 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 19075 | goto decode_failure; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19076 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19077 | default: |
| 19078 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19079 | } |
| 19080 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 19081 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19082 | case 0x3C: // VSX instructions (except load/store) |
| 19083 | { |
florian | dc7948f | 2012-02-15 04:05:05 +0000 | [diff] [blame] | 19084 | // All of these VSX instructions use some VMX facilities, so |
| 19085 | // if allow_V is not set, we'll skip trying to decode. |
| 19086 | if (!allow_V) goto decode_noVX; |
| 19087 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19088 | UInt vsxOpc2 = get_VSX60_opc2(opc2); |
| 19089 | /* The vsxOpc2 returned is the "normalized" value, representing the |
| 19090 | * instructions secondary opcode as taken from the standard secondary |
| 19091 | * opcode field [21:30] (IBM notatition), even if the actual field |
| 19092 | * is non-standard. These normalized values are given in the opcode |
| 19093 | * appendices of the ISA 2.06 document. |
| 19094 | */ |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19095 | |
| 19096 | switch (vsxOpc2) { |
| 19097 | case 0x8: case 0x28: case 0x48: case 0xc8: // xxsldwi, xxpermdi, xxmrghw, xxmrglw |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19098 | case 0x018: case 0x148: // xxsel, xxspltw |
| 19099 | if (dis_vx_permute_misc(theInstr, vsxOpc2)) goto decode_success; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19100 | goto decode_failure; |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19101 | case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor, |
| 19102 | case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc |
| 19103 | case 0x2C8: case 0x2E8: // xxlnand, xxleqv |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19104 | if (dis_vx_logic(theInstr, vsxOpc2)) goto decode_success; |
| 19105 | goto decode_failure; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19106 | case 0x2B2: case 0x2C0: // xsabsdp, xscpsgndp |
| 19107 | case 0x2D2: case 0x2F2: // xsnabsdp, xsnegdp |
| 19108 | case 0x280: case 0x2A0: // xsmaxdp, xsmindp |
| 19109 | case 0x0F2: case 0x0D2: // xsrdpim, xsrdpip |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19110 | case 0x034: case 0x014: // xsresp, xsrsqrtesp |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19111 | case 0x0B4: case 0x094: // xsredp, xsrsqrtedp |
| 19112 | case 0x0D6: case 0x0B2: // xsrdpic, xsrdpiz |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19113 | case 0x092: case 0x232: // xsrdpi, xsrsp |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19114 | if (dis_vxs_misc(theInstr, vsxOpc2)) goto decode_success; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19115 | goto decode_failure; |
| 19116 | case 0x08C: case 0x0AC: // xscmpudp, xscmpodp |
| 19117 | if (dis_vx_cmp(theInstr, vsxOpc2)) goto decode_success; |
| 19118 | goto decode_failure; |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19119 | case 0x0: case 0x020: // xsaddsp, xssubsp |
| 19120 | case 0x080: // xsadddp |
| 19121 | case 0x060: case 0x0E0: // xsdivsp, xsdivdp |
| 19122 | case 0x004: case 0x024: // xsmaddasp, xsmaddmsp |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19123 | case 0x084: case 0x0A4: // xsmaddadp, xsmaddmdp |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19124 | case 0x044: case 0x064: // xsmsubasp, xsmsubmsp |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19125 | case 0x0C4: case 0x0E4: // xsmsubadp, xsmsubmdp |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19126 | case 0x204: case 0x224: // xsnmaddasp, xsnmaddmsp |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19127 | case 0x284: case 0x2A4: // xsnmaddadp, xsnmaddmdp |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19128 | case 0x244: case 0x264: // xsnmsubasp, xsnmsubmsp |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19129 | case 0x2C4: case 0x2E4: // xsnmsubadp, xsnmsubmdp |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19130 | case 0x040: case 0x0C0: // xsmulsp, xsmuldp |
| 19131 | case 0x0A0: // xssubdp |
| 19132 | case 0x016: case 0x096: // xssqrtsp,xssqrtdp |
| 19133 | case 0x0F4: case 0x0D4: // xstdivdp, xstsqrtdp |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19134 | if (dis_vxs_arith(theInstr, vsxOpc2)) goto decode_success; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19135 | goto decode_failure; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19136 | case 0x180: // xvadddp |
| 19137 | case 0x1E0: // xvdivdp |
| 19138 | case 0x1C0: // xvmuldp |
| 19139 | case 0x1A0: // xvsubdp |
| 19140 | case 0x184: case 0x1A4: // xvmaddadp, xvmaddmdp |
| 19141 | case 0x1C4: case 0x1E4: // xvmsubadp, xvmsubmdp |
| 19142 | case 0x384: case 0x3A4: // xvnmaddadp, xvnmaddmdp |
| 19143 | case 0x3C4: case 0x3E4: // xvnmsubadp, xvnmsubmdp |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19144 | case 0x1D4: case 0x1F4: // xvtsqrtdp, xvtdivdp |
| 19145 | case 0x196: // xvsqrtdp |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19146 | if (dis_vxv_dp_arith(theInstr, vsxOpc2)) goto decode_success; |
| 19147 | goto decode_failure; |
| 19148 | case 0x100: // xvaddsp |
| 19149 | case 0x160: // xvdivsp |
| 19150 | case 0x140: // xvmulsp |
| 19151 | case 0x120: // xvsubsp |
| 19152 | case 0x104: case 0x124: // xvmaddasp, xvmaddmsp |
| 19153 | case 0x144: case 0x164: // xvmsubasp, xvmsubmsp |
| 19154 | case 0x304: case 0x324: // xvnmaddasp, xvnmaddmsp |
| 19155 | case 0x344: case 0x364: // xvnmsubasp, xvnmsubmsp |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19156 | case 0x154: case 0x174: // xvtsqrtsp, xvtdivsp |
| 19157 | case 0x116: // xvsqrtsp |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19158 | if (dis_vxv_sp_arith(theInstr, vsxOpc2)) goto decode_success; |
| 19159 | goto decode_failure; |
| 19160 | |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19161 | case 0x250: // xscvuxdsp |
florian | dc7948f | 2012-02-15 04:05:05 +0000 | [diff] [blame] | 19162 | case 0x2D0: case 0x3d0: // xscvuxddp, xvcvuxddp |
| 19163 | case 0x350: case 0x1d0: // xvcvuxdsp, xvcvuxwdp |
| 19164 | case 0x090: // xscvdpuxws |
| 19165 | // The above VSX conversion instructions employ some ISA 2.06 |
| 19166 | // floating point conversion instructions under the covers, |
| 19167 | // so if allow_VX (which means "supports ISA 2.06") is not set, |
| 19168 | // we'll skip the decode. |
| 19169 | if (!allow_VX) goto decode_noVX; |
| 19170 | if (dis_vx_conv(theInstr, vsxOpc2)) goto decode_success; |
| 19171 | goto decode_failure; |
| 19172 | |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19173 | case 0x2B0: // xscvdpsxds |
| 19174 | case 0x270: case 0x2F0: // xscvsxdsp, xscvsxddp |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19175 | case 0x1b0: case 0x130: // xvcvdpsxws, xvcvspsxws |
| 19176 | case 0x0b0: case 0x290: // xscvdpsxws, xscvdpuxds |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 19177 | case 0x212: case 0x216: // xscvdpsp, xscvdpspn |
| 19178 | case 0x292: case 0x296: // xscvspdp, xscvspdpn |
| 19179 | case 0x312: // xvcvdpsp |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19180 | case 0x390: case 0x190: // xvcvdpuxds, xvcvdpuxws |
| 19181 | case 0x3B0: case 0x310: // xvcvdpsxds, xvcvspuxds |
| 19182 | case 0x392: case 0x330: // xvcvspdp, xvcvspsxds |
| 19183 | case 0x110: case 0x3f0: // xvcvspuxws, xvcvsxddp |
| 19184 | case 0x370: case 0x1f0: // xvcvsxdsp, xvcvsxwdp |
| 19185 | case 0x170: case 0x150: // xvcvsxwsp, xvcvuxwsp |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19186 | if (dis_vx_conv(theInstr, vsxOpc2)) goto decode_success; |
| 19187 | goto decode_failure; |
| 19188 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19189 | case 0x18C: case 0x38C: // xvcmpeqdp[.] |
| 19190 | case 0x10C: case 0x30C: // xvcmpeqsp[.] |
| 19191 | case 0x14C: case 0x34C: // xvcmpgesp[.] |
| 19192 | case 0x12C: case 0x32C: // xvcmpgtsp[.] |
| 19193 | case 0x1CC: case 0x3CC: // xvcmpgedp[.] |
| 19194 | case 0x1AC: case 0x3AC: // xvcmpgtdp[.] |
| 19195 | if (dis_vvec_cmp(theInstr, vsxOpc2)) goto decode_success; |
| 19196 | goto decode_failure; |
| 19197 | |
| 19198 | case 0x134: // xvresp |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19199 | case 0x1B4: // xvredp |
| 19200 | case 0x194: case 0x114: // xvrsqrtedp, xvrsqrtesp |
| 19201 | case 0x380: case 0x3A0: // xvmaxdp, xvmindp |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19202 | case 0x300: case 0x320: // xvmaxsp, xvminsp |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19203 | case 0x3C0: case 0x340: // xvcpsgndp, xvcpsgnsp |
| 19204 | case 0x3B2: case 0x332: // xvabsdp, xvabssp |
| 19205 | case 0x3D2: case 0x352: // xvnabsdp, xvnabssp |
| 19206 | case 0x192: case 0x1D6: // xvrdpi, xvrdpic |
| 19207 | case 0x1F2: case 0x1D2: // xvrdpim, xvrdpip |
| 19208 | case 0x1B2: case 0x3F2: // xvrdpiz, xvnegdp |
| 19209 | case 0x112: case 0x156: // xvrspi, xvrspic |
| 19210 | case 0x172: case 0x152: // xvrspim, xvrspip |
| 19211 | case 0x132: // xvrspiz |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19212 | if (dis_vxv_misc(theInstr, vsxOpc2)) goto decode_success; |
| 19213 | goto decode_failure; |
| 19214 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19215 | default: |
| 19216 | goto decode_failure; |
| 19217 | } |
| 19218 | break; |
| 19219 | } |
| 19220 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19221 | /* 64bit Integer Stores */ |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 19222 | case 0x3E: // std, stdu, stq |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 19223 | if (dis_int_store( theInstr, abiinfo )) goto decode_success; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19224 | goto decode_failure; |
| 19225 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 19226 | case 0x3F: |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19227 | if (!allow_F) goto decode_noF; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 19228 | /* Instrs using opc[1:5] never overlap instrs using opc[1:10], |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 19229 | so we can simply fall through the first switch statement */ |
| 19230 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 19231 | opc2 = IFIELD(theInstr, 1, 5); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 19232 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19233 | /* Floating Point Arith Instructions */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19234 | case 0x12: case 0x14: case 0x15: // fdiv, fsub, fadd |
| 19235 | case 0x19: // fmul |
| 19236 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 19237 | goto decode_failure; |
| 19238 | case 0x16: // fsqrt |
| 19239 | if (!allow_FX) goto decode_noFX; |
| 19240 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 19241 | goto decode_failure; |
| 19242 | case 0x17: case 0x1A: // fsel, frsqrte |
| 19243 | if (!allow_GX) goto decode_noGX; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19244 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 19245 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19246 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19247 | /* Floating Point Mult-Add Instructions */ |
| 19248 | case 0x1C: case 0x1D: case 0x1E: // fmsub, fmadd, fnmsub |
| 19249 | case 0x1F: // fnmadd |
| 19250 | if (dis_fp_multadd(theInstr)) goto decode_success; |
| 19251 | goto decode_failure; |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 19252 | |
| 19253 | case 0x18: // fre |
| 19254 | if (!allow_GX) goto decode_noGX; |
| 19255 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 19256 | goto decode_failure; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 19257 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19258 | default: |
| 19259 | break; // Fall through |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 19260 | } |
| 19261 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 19262 | opc2 = IFIELD(theInstr, 1, 10); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19263 | switch (opc2) { |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 19264 | /* 128-bit DFP instructions */ |
| 19265 | case 0x2: // daddq - DFP Add |
| 19266 | case 0x202: // dsubq - DFP Subtract |
| 19267 | case 0x22: // dmulq - DFP Mult |
| 19268 | case 0x222: // ddivq - DFP Divide |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 19269 | if (!allow_DFP) goto decode_noDFP; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 19270 | if (dis_dfp_arithq( theInstr )) |
| 19271 | goto decode_success; |
| 19272 | goto decode_failure; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 19273 | case 0x162: // dxexq - DFP Extract exponent |
| 19274 | case 0x362: // diexq - DFP Insert exponent |
| 19275 | if (!allow_DFP) |
| 19276 | goto decode_failure; |
| 19277 | if (dis_dfp_extract_insertq( theInstr )) |
| 19278 | goto decode_success; |
| 19279 | goto decode_failure; |
| 19280 | |
| 19281 | case 0x82: // dcmpoq, DFP comparison ordered instruction |
| 19282 | case 0x282: // dcmpuq, DFP comparison unordered instruction |
| 19283 | if (!allow_DFP) |
| 19284 | goto decode_failure; |
| 19285 | if (dis_dfp_compare( theInstr ) ) |
| 19286 | goto decode_success; |
| 19287 | goto decode_failure; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 19288 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 19289 | case 0x102: // dctqpq - DFP convert to DFP extended |
| 19290 | case 0x302: // drdpq - DFP round to dfp Long |
| 19291 | case 0x122: // dctfixq - DFP convert to fixed quad |
| 19292 | case 0x322: // dcffixq - DFP convert from fixed quad |
| 19293 | if (!allow_DFP) |
| 19294 | goto decode_failure; |
| 19295 | if (dis_dfp_fmt_convq( theInstr )) |
| 19296 | goto decode_success; |
| 19297 | goto decode_failure; |
| 19298 | |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 19299 | case 0x2A2: // dtstsfq - DFP number of significant digits |
| 19300 | if (!allow_DFP) |
| 19301 | goto decode_failure; |
| 19302 | if (dis_dfp_significant_digits(theInstr)) |
| 19303 | goto decode_success; |
| 19304 | goto decode_failure; |
| 19305 | |
| 19306 | case 0x142: // ddedpdq DFP Decode DPD to BCD |
| 19307 | case 0x342: // denbcdq DFP Encode BCD to DPD |
| 19308 | if (!allow_DFP) |
| 19309 | goto decode_failure; |
| 19310 | if (dis_dfp_bcdq(theInstr)) |
| 19311 | goto decode_success; |
| 19312 | goto decode_failure; |
| 19313 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19314 | /* Floating Point Compare Instructions */ |
| 19315 | case 0x000: // fcmpu |
| 19316 | case 0x020: // fcmpo |
| 19317 | if (dis_fp_cmp(theInstr)) goto decode_success; |
| 19318 | goto decode_failure; |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 19319 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19320 | case 0x080: // ftdiv |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19321 | case 0x0A0: // ftsqrt |
| 19322 | if (dis_fp_tests(theInstr)) goto decode_success; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19323 | goto decode_failure; |
| 19324 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19325 | /* Floating Point Rounding/Conversion Instructions */ |
| 19326 | case 0x00C: // frsp |
| 19327 | case 0x00E: // fctiw |
| 19328 | case 0x00F: // fctiwz |
sewardj | 6be6723 | 2006-01-24 19:00:05 +0000 | [diff] [blame] | 19329 | case 0x32E: // fctid |
| 19330 | case 0x32F: // fctidz |
| 19331 | case 0x34E: // fcfid |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19332 | if (dis_fp_round(theInstr)) goto decode_success; |
| 19333 | goto decode_failure; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19334 | case 0x3CE: case 0x3AE: case 0x3AF: // fcfidu, fctidu[z] (implemented as native insns) |
| 19335 | case 0x08F: case 0x08E: // fctiwu[z] (implemented as native insns) |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19336 | if (!allow_VX) goto decode_noVX; |
| 19337 | if (dis_fp_round(theInstr)) goto decode_success; |
| 19338 | goto decode_failure; |
| 19339 | |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 19340 | /* Power6 rounding stuff */ |
| 19341 | case 0x1E8: // frim |
| 19342 | case 0x1C8: // frip |
| 19343 | case 0x188: // frin |
| 19344 | case 0x1A8: // friz |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 19345 | /* A hack to check for P6 capability . . . */ |
| 19346 | if ((allow_F && allow_V && allow_FX && allow_GX) && |
| 19347 | (dis_fp_round(theInstr))) |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 19348 | goto decode_success; |
| 19349 | goto decode_failure; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19350 | |
| 19351 | /* Floating Point Move Instructions */ |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 19352 | case 0x008: // fcpsgn |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19353 | case 0x028: // fneg |
| 19354 | case 0x048: // fmr |
| 19355 | case 0x088: // fnabs |
| 19356 | case 0x108: // fabs |
| 19357 | if (dis_fp_move( theInstr )) goto decode_success; |
| 19358 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19359 | |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 19360 | case 0x3c6: case 0x346: // fmrgew, fmrgow |
| 19361 | if (dis_fp_merge( theInstr )) goto decode_success; |
| 19362 | goto decode_failure; |
| 19363 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19364 | /* Floating Point Status/Control Register Instructions */ |
cerion | 3ea49ee | 2006-01-04 10:53:00 +0000 | [diff] [blame] | 19365 | case 0x026: // mtfsb1 |
sewardj | 496b88f | 2006-10-04 17:46:11 +0000 | [diff] [blame] | 19366 | case 0x040: // mcrfs |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19367 | case 0x046: // mtfsb0 |
| 19368 | case 0x086: // mtfsfi |
| 19369 | case 0x247: // mffs |
| 19370 | case 0x2C7: // mtfsf |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 19371 | // Some of the above instructions need to know more about the |
| 19372 | // ISA level supported by the host. |
| 19373 | if (dis_fp_scr( theInstr, allow_GX )) goto decode_success; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19374 | goto decode_failure; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19375 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19376 | default: |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 19377 | break; // Fall through... |
| 19378 | } |
| 19379 | |
| 19380 | opc2 = ifieldOPClo9( theInstr ); |
| 19381 | switch (opc2) { |
| 19382 | case 0x42: // dscli, DFP shift left |
| 19383 | case 0x62: // dscri, DFP shift right |
| 19384 | if (!allow_DFP) |
| 19385 | goto decode_failure; |
| 19386 | if (dis_dfp_shiftq( theInstr )) |
| 19387 | goto decode_success; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19388 | goto decode_failure; |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 19389 | case 0xc2: // dtstdc, DFP test data class |
| 19390 | case 0xe2: // dtstdg, DFP test data group |
| 19391 | if (!allow_DFP) |
| 19392 | goto decode_failure; |
| 19393 | if (dis_dfp_class_test( theInstr )) |
| 19394 | goto decode_success; |
| 19395 | goto decode_failure; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 19396 | default: |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 19397 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19398 | } |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 19399 | |
| 19400 | opc2 = ifieldOPClo8( theInstr ); |
| 19401 | switch (opc2) { |
| 19402 | case 0x3: // dquaq - DFP Quantize Quad |
| 19403 | case 0x23: // drrndq - DFP Reround Quad |
| 19404 | case 0x43: // dquaiq - DFP Quantize immediate Quad |
| 19405 | if (!allow_DFP) |
| 19406 | goto decode_failure; |
| 19407 | if (dis_dfp_quantize_sig_rrndq( theInstr )) |
| 19408 | goto decode_success; |
| 19409 | goto decode_failure; |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 19410 | case 0xA2: // dtstexq - DFP Test exponent Quad |
| 19411 | if (dis_dfp_exponent_test( theInstr ) ) |
| 19412 | goto decode_success; |
| 19413 | goto decode_failure; |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 19414 | case 0x63: // drintxq - DFP Round to an integer value |
| 19415 | case 0xE3: // drintnq - DFP Round to an integer value |
| 19416 | if (!allow_DFP) |
| 19417 | goto decode_failure; |
| 19418 | if (dis_dfp_roundq( theInstr )) |
| 19419 | goto decode_success; |
| 19420 | goto decode_failure; |
| 19421 | |
| 19422 | default: |
| 19423 | goto decode_failure; |
| 19424 | } |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 19425 | break; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 19426 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 19427 | case 0x13: |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19428 | switch (opc2) { |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 19429 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19430 | /* Condition Register Logical Instructions */ |
| 19431 | case 0x101: case 0x081: case 0x121: // crand, crandc, creqv |
| 19432 | case 0x0E1: case 0x021: case 0x1C1: // crnand, crnor, cror |
| 19433 | case 0x1A1: case 0x0C1: case 0x000: // crorc, crxor, mcrf |
| 19434 | if (dis_cond_logic( theInstr )) goto decode_success; |
| 19435 | goto decode_failure; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19436 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19437 | /* Branch Instructions */ |
| 19438 | case 0x210: case 0x010: // bcctr, bclr |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 19439 | if (dis_branch(theInstr, abiinfo, &dres, |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 19440 | resteerOkFn, callback_opaque)) |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 19441 | goto decode_success; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19442 | goto decode_failure; |
| 19443 | |
| 19444 | /* Memory Synchronization Instructions */ |
| 19445 | case 0x096: // isync |
| 19446 | if (dis_memsync( theInstr )) goto decode_success; |
| 19447 | goto decode_failure; |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 19448 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19449 | default: |
| 19450 | goto decode_failure; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19451 | } |
| 19452 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 19453 | |
| 19454 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19455 | case 0x1F: |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19456 | |
| 19457 | /* For arith instns, bit10 is the OE flag (overflow enable) */ |
| 19458 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 19459 | opc2 = IFIELD(theInstr, 1, 9); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19460 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19461 | /* Integer Arithmetic Instructions */ |
| 19462 | case 0x10A: case 0x00A: case 0x08A: // add, addc, adde |
| 19463 | case 0x0EA: case 0x0CA: case 0x1EB: // addme, addze, divw |
| 19464 | case 0x1CB: case 0x04B: case 0x00B: // divwu, mulhw, mulhwu |
| 19465 | case 0x0EB: case 0x068: case 0x028: // mullw, neg, subf |
| 19466 | case 0x008: case 0x088: case 0x0E8: // subfc, subfe, subfme |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19467 | case 0x0C8: // subfze |
| 19468 | if (dis_int_arith( theInstr )) goto decode_success; |
| 19469 | goto decode_failure; |
| 19470 | |
| 19471 | case 0x18B: // divweu (implemented as native insn) |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19472 | case 0x1AB: // divwe (implemented as native insn) |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19473 | if (!allow_VX) goto decode_noVX; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19474 | if (dis_int_arith( theInstr )) goto decode_success; |
| 19475 | goto decode_failure; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19476 | |
| 19477 | /* 64bit Integer Arithmetic */ |
| 19478 | case 0x009: case 0x049: case 0x0E9: // mulhdu, mulhd, mulld |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19479 | case 0x1C9: case 0x1E9: // divdu, divd |
| 19480 | if (!mode64) goto decode_failure; |
| 19481 | if (dis_int_arith( theInstr )) goto decode_success; |
| 19482 | goto decode_failure; |
| 19483 | |
| 19484 | case 0x1A9: // divde (implemented as native insn) |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19485 | case 0x189: // divdeuo (implemented as native insn) |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19486 | if (!allow_VX) goto decode_noVX; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19487 | if (!mode64) goto decode_failure; |
| 19488 | if (dis_int_arith( theInstr )) goto decode_success; |
| 19489 | goto decode_failure; |
| 19490 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 19491 | case 0x1FC: // cmpb |
| 19492 | if (dis_int_logic( theInstr )) goto decode_success; |
| 19493 | goto decode_failure; |
| 19494 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 19495 | default: |
| 19496 | break; // Fall through... |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19497 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 19498 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19499 | /* All remaining opcodes use full 10 bits. */ |
| 19500 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 19501 | opc2 = IFIELD(theInstr, 1, 10); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19502 | switch (opc2) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19503 | /* Integer Compare Instructions */ |
| 19504 | case 0x000: case 0x020: // cmp, cmpl |
| 19505 | if (dis_int_cmp( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19506 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 19507 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19508 | /* Integer Logical Instructions */ |
| 19509 | case 0x01C: case 0x03C: case 0x01A: // and, andc, cntlzw |
| 19510 | case 0x11C: case 0x3BA: case 0x39A: // eqv, extsb, extsh |
| 19511 | case 0x1DC: case 0x07C: case 0x1BC: // nand, nor, or |
| 19512 | case 0x19C: case 0x13C: // orc, xor |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 19513 | case 0x2DF: case 0x25F: // mftgpr, mffgpr |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19514 | if (dis_int_logic( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19515 | goto decode_failure; |
cerion | 932ad94 | 2005-01-30 10:18:50 +0000 | [diff] [blame] | 19516 | |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 19517 | case 0x28E: case 0x2AE: // tbegin., tend. |
| 19518 | case 0x2EE: case 0x2CE: case 0x30E: // tsr., tcheck., tabortwc. |
| 19519 | case 0x32E: case 0x34E: case 0x36E: // tabortdc., tabortwci., tabortdci. |
carll | fcce5f8 | 2013-10-09 17:52:01 +0000 | [diff] [blame] | 19520 | case 0x38E: case 0x3AE: case 0x3EE: // tabort., treclaim., trechkpt. |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 19521 | if (dis_transactional_memory( theInstr, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 19522 | getUIntPPCendianly( (UChar*)(&guest_code[delta + 4])), |
carll | 8943d02 | 2013-10-02 16:25:57 +0000 | [diff] [blame] | 19523 | abiinfo, &dres, |
| 19524 | resteerOkFn, callback_opaque)) |
| 19525 | goto decode_success; |
| 19526 | goto decode_failure; |
| 19527 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19528 | /* 64bit Integer Logical Instructions */ |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 19529 | case 0x3DA: case 0x03A: // extsw, cntlzd |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19530 | if (!mode64) goto decode_failure; |
| 19531 | if (dis_int_logic( theInstr )) goto decode_success; |
| 19532 | goto decode_failure; |
| 19533 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 19534 | /* 64bit Integer Parity Instructions */ |
carll | bb3f401 | 2012-10-29 20:23:41 +0000 | [diff] [blame] | 19535 | case 0xba: // prtyd |
| 19536 | if (!mode64) goto decode_failure; |
| 19537 | if (dis_int_parity( theInstr )) goto decode_success; |
| 19538 | goto decode_failure; |
| 19539 | |
| 19540 | case 0x9a: // prtyw |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 19541 | if (dis_int_parity( theInstr )) goto decode_success; |
| 19542 | goto decode_failure; |
| 19543 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19544 | /* Integer Shift Instructions */ |
| 19545 | case 0x018: case 0x318: case 0x338: // slw, sraw, srawi |
| 19546 | case 0x218: // srw |
| 19547 | if (dis_int_shift( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19548 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 19549 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19550 | /* 64bit Integer Shift Instructions */ |
| 19551 | case 0x01B: case 0x31A: // sld, srad |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 19552 | case 0x33A: case 0x33B: // sradi |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19553 | case 0x21B: // srd |
| 19554 | if (!mode64) goto decode_failure; |
| 19555 | if (dis_int_shift( theInstr )) goto decode_success; |
| 19556 | goto decode_failure; |
| 19557 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19558 | /* Integer Load Instructions */ |
| 19559 | case 0x057: case 0x077: case 0x157: // lbzx, lbzux, lhax |
| 19560 | case 0x177: case 0x117: case 0x137: // lhaux, lhzx, lhzux |
| 19561 | case 0x017: case 0x037: // lwzx, lwzux |
| 19562 | if (dis_int_load( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19563 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 19564 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19565 | /* 64bit Integer Load Instructions */ |
| 19566 | case 0x035: case 0x015: // ldux, ldx |
| 19567 | case 0x175: case 0x155: // lwaux, lwax |
| 19568 | if (!mode64) goto decode_failure; |
| 19569 | if (dis_int_load( theInstr )) goto decode_success; |
| 19570 | goto decode_failure; |
| 19571 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 19572 | /* Integer Store Instructions */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19573 | case 0x0F7: case 0x0D7: case 0x1B7: // stbux, stbx, sthux |
| 19574 | case 0x197: case 0x0B7: case 0x097: // sthx, stwux, stwx |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 19575 | if (dis_int_store( theInstr, abiinfo )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19576 | goto decode_failure; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 19577 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19578 | /* 64bit Integer Store Instructions */ |
| 19579 | case 0x0B5: case 0x095: // stdux, stdx |
| 19580 | if (!mode64) goto decode_failure; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 19581 | if (dis_int_store( theInstr, abiinfo )) goto decode_success; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19582 | goto decode_failure; |
| 19583 | |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 19584 | /* Integer Load and Store with Byte Reverse Instructions */ |
carll | bb3f401 | 2012-10-29 20:23:41 +0000 | [diff] [blame] | 19585 | case 0x214: case 0x294: // ldbrx, stdbrx |
| 19586 | if (!mode64) goto decode_failure; |
| 19587 | if (dis_int_ldst_rev( theInstr )) goto decode_success; |
| 19588 | goto decode_failure; |
| 19589 | |
| 19590 | case 0x216: case 0x316: case 0x296: // lwbrx, lhbrx, stwbrx |
| 19591 | case 0x396: // sthbrx |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 19592 | if (dis_int_ldst_rev( theInstr )) goto decode_success; |
| 19593 | goto decode_failure; |
| 19594 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 19595 | /* Integer Load and Store String Instructions */ |
| 19596 | case 0x255: case 0x215: case 0x2D5: // lswi, lswx, stswi |
| 19597 | case 0x295: { // stswx |
| 19598 | Bool stopHere = False; |
| 19599 | Bool ok = dis_int_ldst_str( theInstr, &stopHere ); |
| 19600 | if (!ok) goto decode_failure; |
| 19601 | if (stopHere) { |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 19602 | putGST( PPC_GST_CIA, mkSzImm(ty, nextInsnAddr()) ); |
| 19603 | dres.jk_StopHere = Ijk_Boring; |
| 19604 | dres.whatNext = Dis_StopHere; |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 19605 | } |
| 19606 | goto decode_success; |
| 19607 | } |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 19608 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19609 | /* Memory Synchronization Instructions */ |
| 19610 | case 0x356: case 0x014: case 0x096: // eieio, lwarx, stwcx. |
| 19611 | case 0x256: // sync |
| 19612 | if (dis_memsync( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19613 | goto decode_failure; |
| 19614 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 19615 | /* 64bit Memory Synchronization Instructions */ |
| 19616 | case 0x054: case 0x0D6: // ldarx, stdcx. |
| 19617 | if (!mode64) goto decode_failure; |
| 19618 | if (dis_memsync( theInstr )) goto decode_success; |
| 19619 | goto decode_failure; |
| 19620 | |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 19621 | case 0x114: case 0x0B6: // lqarx, stqcx. |
| 19622 | if (dis_memsync( theInstr )) goto decode_success; |
| 19623 | goto decode_failure; |
| 19624 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19625 | /* Processor Control Instructions */ |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 19626 | case 0x33: case 0x73: // mfvsrd, mfvsrwz |
| 19627 | case 0xB3: case 0xD3: case 0xF3: // mtvsrd, mtvsrwa, mtvsrwz |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19628 | case 0x200: case 0x013: case 0x153: // mcrxr, mfcr, mfspr |
| 19629 | case 0x173: case 0x090: case 0x1D3: // mftb, mtcrf, mtspr |
carll | 78850ae | 2013-09-10 18:46:40 +0000 | [diff] [blame] | 19630 | case 0x220: // mcrxrt |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 19631 | if (dis_proc_ctl( abiinfo, theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19632 | goto decode_failure; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 19633 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 19634 | /* Cache Management Instructions */ |
| 19635 | case 0x2F6: case 0x056: case 0x036: // dcba, dcbf, dcbst |
| 19636 | case 0x116: case 0x0F6: case 0x3F6: // dcbt, dcbtst, dcbz |
| 19637 | case 0x3D6: // icbi |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 19638 | if (dis_cache_manage( theInstr, &dres, archinfo )) |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 19639 | goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 19640 | goto decode_failure; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 19641 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 19642 | //zz /* External Control Instructions */ |
| 19643 | //zz case 0x136: case 0x1B6: // eciwx, ecowx |
| 19644 | //zz DIP("external control op => not implemented\n"); |
| 19645 | //zz goto decode_failure; |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 19646 | |
| 19647 | /* Trap Instructions */ |
carll | bb3f401 | 2012-10-29 20:23:41 +0000 | [diff] [blame] | 19648 | case 0x004: // tw |
| 19649 | if (dis_trap(theInstr, &dres)) goto decode_success; |
| 19650 | goto decode_failure; |
| 19651 | |
| 19652 | case 0x044: // td |
| 19653 | if (!mode64) goto decode_failure; |
sewardj | 59c0d8f | 2007-08-28 14:48:35 +0000 | [diff] [blame] | 19654 | if (dis_trap(theInstr, &dres)) goto decode_success; |
| 19655 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19656 | |
| 19657 | /* Floating Point Load Instructions */ |
| 19658 | case 0x217: case 0x237: case 0x257: // lfsx, lfsux, lfdx |
| 19659 | case 0x277: // lfdux |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19660 | if (!allow_F) goto decode_noF; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19661 | if (dis_fp_load( theInstr )) goto decode_success; |
| 19662 | goto decode_failure; |
| 19663 | |
| 19664 | /* Floating Point Store Instructions */ |
| 19665 | case 0x297: case 0x2B7: case 0x2D7: // stfs, stfsu, stfd |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19666 | case 0x2F7: // stfdu, stfiwx |
| 19667 | if (!allow_F) goto decode_noF; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19668 | if (dis_fp_store( theInstr )) goto decode_success; |
| 19669 | goto decode_failure; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19670 | case 0x3D7: // stfiwx |
| 19671 | if (!allow_F) goto decode_noF; |
| 19672 | if (!allow_GX) goto decode_noGX; |
| 19673 | if (dis_fp_store( theInstr )) goto decode_success; |
| 19674 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 19675 | |
sewardj | 7e84630 | 2010-09-03 23:37:02 +0000 | [diff] [blame] | 19676 | /* Floating Point Double Pair Indexed Instructions */ |
| 19677 | case 0x317: // lfdpx (Power6) |
| 19678 | case 0x397: // stfdpx (Power6) |
| 19679 | if (!allow_F) goto decode_noF; |
| 19680 | if (dis_fp_pair(theInstr)) goto decode_success; |
| 19681 | goto decode_failure; |
| 19682 | |
| 19683 | case 0x357: // lfiwax |
| 19684 | if (!allow_F) goto decode_noF; |
| 19685 | if (dis_fp_load( theInstr )) goto decode_success; |
| 19686 | goto decode_failure; |
| 19687 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19688 | case 0x377: // lfiwzx |
| 19689 | if (!allow_F) goto decode_noF; |
| 19690 | if (dis_fp_load( theInstr )) goto decode_success; |
| 19691 | goto decode_failure; |
| 19692 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19693 | /* AltiVec instructions */ |
| 19694 | |
| 19695 | /* AV Cache Control - Data streams */ |
| 19696 | case 0x156: case 0x176: case 0x336: // dst, dstst, dss |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19697 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19698 | if (dis_av_datastream( theInstr )) goto decode_success; |
| 19699 | goto decode_failure; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 19700 | |
| 19701 | /* AV Load */ |
| 19702 | case 0x006: case 0x026: // lvsl, lvsr |
| 19703 | case 0x007: case 0x027: case 0x047: // lvebx, lvehx, lvewx |
| 19704 | case 0x067: case 0x167: // lvx, lvxl |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19705 | if (!allow_V) goto decode_noV; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 19706 | if (dis_av_load( abiinfo, theInstr )) goto decode_success; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 19707 | goto decode_failure; |
| 19708 | |
| 19709 | /* AV Store */ |
| 19710 | case 0x087: case 0x0A7: case 0x0C7: // stvebx, stvehx, stvewx |
| 19711 | case 0x0E7: case 0x1E7: // stvx, stvxl |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19712 | if (!allow_V) goto decode_noV; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 19713 | if (dis_av_store( theInstr )) goto decode_success; |
| 19714 | goto decode_failure; |
| 19715 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19716 | /* VSX Load */ |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19717 | case 0x00C: // lxsiwzx |
| 19718 | case 0x04C: // lxsiwax |
| 19719 | case 0x20C: // lxsspx |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19720 | case 0x24C: // lxsdx |
| 19721 | case 0x34C: // lxvd2x |
| 19722 | case 0x14C: // lxvdsx |
| 19723 | case 0x30C: // lxvw4x |
florian | dc7948f | 2012-02-15 04:05:05 +0000 | [diff] [blame] | 19724 | // All of these VSX load instructions use some VMX facilities, so |
| 19725 | // if allow_V is not set, we'll skip trying to decode. |
| 19726 | if (!allow_V) goto decode_noV; |
| 19727 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 19728 | if (dis_vx_load( theInstr )) goto decode_success; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19729 | goto decode_failure; |
| 19730 | |
| 19731 | /* VSX Store */ |
carll | 6c758b6 | 2013-10-03 21:38:45 +0000 | [diff] [blame] | 19732 | case 0x08C: // stxsiwx |
| 19733 | case 0x28C: // stxsspx |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19734 | case 0x2CC: // stxsdx |
| 19735 | case 0x3CC: // stxvd2x |
| 19736 | case 0x38C: // stxvw4x |
florian | dc7948f | 2012-02-15 04:05:05 +0000 | [diff] [blame] | 19737 | // All of these VSX store instructions use some VMX facilities, so |
| 19738 | // if allow_V is not set, we'll skip trying to decode. |
| 19739 | if (!allow_V) goto decode_noV; |
| 19740 | |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 19741 | if (dis_vx_store( theInstr )) goto decode_success; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19742 | goto decode_failure; |
| 19743 | |
| 19744 | /* Miscellaneous ISA 2.06 instructions */ |
| 19745 | case 0x1FA: // popcntd |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 19746 | case 0x17A: // popcntw |
philippe | 738d9dd | 2012-07-06 21:56:53 +0000 | [diff] [blame] | 19747 | case 0x7A: // popcntb |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 19748 | if (dis_int_logic( theInstr )) goto decode_success; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 19749 | goto decode_failure; |
| 19750 | |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19751 | case 0x0FC: // bpermd |
carll | bb3f401 | 2012-10-29 20:23:41 +0000 | [diff] [blame] | 19752 | if (!mode64) goto decode_failure; |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 19753 | if (dis_int_logic( theInstr )) goto decode_success; |
| 19754 | goto decode_failure; |
| 19755 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 19756 | default: |
sewardj | cb07be2 | 2008-11-06 09:02:34 +0000 | [diff] [blame] | 19757 | /* Deal with some other cases that we would otherwise have |
| 19758 | punted on. */ |
| 19759 | /* --- ISEL (PowerISA_V2.05.pdf, p74) --- */ |
sewardj | 1685c28 | 2008-11-06 09:22:05 +0000 | [diff] [blame] | 19760 | /* only decode this insn when reserved bit 0 (31 in IBM's |
| 19761 | notation) is zero */ |
| 19762 | if (IFIELD(theInstr, 0, 6) == (15<<1)) { |
sewardj | cb07be2 | 2008-11-06 09:02:34 +0000 | [diff] [blame] | 19763 | UInt rT = ifieldRegDS( theInstr ); |
| 19764 | UInt rA = ifieldRegA( theInstr ); |
| 19765 | UInt rB = ifieldRegB( theInstr ); |
| 19766 | UInt bi = ifieldRegC( theInstr ); |
| 19767 | putIReg( |
| 19768 | rT, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 19769 | IRExpr_ITE( binop(Iop_CmpNE32, getCRbit( bi ), mkU32(0)), |
| 19770 | rA == 0 ? (mode64 ? mkU64(0) : mkU32(0)) |
| 19771 | : getIReg(rA), |
| 19772 | getIReg(rB)) |
| 19773 | |
sewardj | cb07be2 | 2008-11-06 09:02:34 +0000 | [diff] [blame] | 19774 | ); |
| 19775 | DIP("isel r%u,r%u,r%u,crb%u\n", rT,rA,rB,bi); |
| 19776 | goto decode_success; |
| 19777 | } |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 19778 | goto decode_failure; |
| 19779 | } |
| 19780 | break; |
| 19781 | |
| 19782 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19783 | case 0x04: |
| 19784 | /* AltiVec instructions */ |
| 19785 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 19786 | opc2 = IFIELD(theInstr, 0, 6); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19787 | switch (opc2) { |
| 19788 | /* AV Mult-Add, Mult-Sum */ |
| 19789 | case 0x20: case 0x21: case 0x22: // vmhaddshs, vmhraddshs, vmladduhm |
| 19790 | case 0x24: case 0x25: case 0x26: // vmsumubm, vmsummbm, vmsumuhm |
| 19791 | case 0x27: case 0x28: case 0x29: // vmsumuhs, vmsumshm, vmsumshs |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19792 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19793 | if (dis_av_multarith( theInstr )) goto decode_success; |
| 19794 | goto decode_failure; |
| 19795 | |
| 19796 | /* AV Permutations */ |
| 19797 | case 0x2A: // vsel |
| 19798 | case 0x2B: // vperm |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19799 | case 0x2C: // vsldoi |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19800 | if (!allow_V) goto decode_noV; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 19801 | if (dis_av_permute( theInstr )) goto decode_success; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19802 | goto decode_failure; |
| 19803 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 19804 | case 0x2D: // vpermxor |
| 19805 | if (!allow_isa_2_07) goto decode_noP8; |
| 19806 | if (dis_av_permute( theInstr )) goto decode_success; |
| 19807 | goto decode_failure; |
| 19808 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19809 | /* AV Floating Point Mult-Add/Sub */ |
| 19810 | case 0x2E: case 0x2F: // vmaddfp, vnmsubfp |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19811 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19812 | if (dis_av_fp_arith( theInstr )) goto decode_success; |
| 19813 | goto decode_failure; |
| 19814 | |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 19815 | case 0x3D: case 0x3C: // vaddecuq, vaddeuqm |
| 19816 | case 0x3F: case 0x3E: // vsubecuq, vsubeuqm |
| 19817 | if (!allow_V) goto decode_noV; |
| 19818 | if (dis_av_quad( theInstr)) goto decode_success; |
| 19819 | goto decode_failure; |
| 19820 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19821 | default: |
| 19822 | break; // Fall through... |
| 19823 | } |
| 19824 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 19825 | opc2 = IFIELD(theInstr, 0, 9); |
| 19826 | switch (opc2) { |
| 19827 | /* BCD arithmetic */ |
| 19828 | case 0x1: case 0x41: // bcdadd, bcdsub |
| 19829 | if (!allow_isa_2_07) goto decode_noP8; |
| 19830 | if (dis_av_bcd( theInstr )) goto decode_success; |
| 19831 | goto decode_failure; |
| 19832 | |
| 19833 | default: |
| 19834 | break; // Fall through... |
| 19835 | } |
| 19836 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 19837 | opc2 = IFIELD(theInstr, 0, 11); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19838 | switch (opc2) { |
| 19839 | /* AV Arithmetic */ |
| 19840 | case 0x180: // vaddcuw |
| 19841 | case 0x000: case 0x040: case 0x080: // vaddubm, vadduhm, vadduwm |
| 19842 | case 0x200: case 0x240: case 0x280: // vaddubs, vadduhs, vadduws |
| 19843 | case 0x300: case 0x340: case 0x380: // vaddsbs, vaddshs, vaddsws |
| 19844 | case 0x580: // vsubcuw |
| 19845 | case 0x400: case 0x440: case 0x480: // vsububm, vsubuhm, vsubuwm |
| 19846 | case 0x600: case 0x640: case 0x680: // vsububs, vsubuhs, vsubuws |
| 19847 | case 0x700: case 0x740: case 0x780: // vsubsbs, vsubshs, vsubsws |
| 19848 | case 0x402: case 0x442: case 0x482: // vavgub, vavguh, vavguw |
| 19849 | case 0x502: case 0x542: case 0x582: // vavgsb, vavgsh, vavgsw |
| 19850 | case 0x002: case 0x042: case 0x082: // vmaxub, vmaxuh, vmaxuw |
| 19851 | case 0x102: case 0x142: case 0x182: // vmaxsb, vmaxsh, vmaxsw |
| 19852 | case 0x202: case 0x242: case 0x282: // vminub, vminuh, vminuw |
| 19853 | case 0x302: case 0x342: case 0x382: // vminsb, vminsh, vminsw |
| 19854 | case 0x008: case 0x048: // vmuloub, vmulouh |
| 19855 | case 0x108: case 0x148: // vmulosb, vmulosh |
| 19856 | case 0x208: case 0x248: // vmuleub, vmuleuh |
| 19857 | case 0x308: case 0x348: // vmulesb, vmulesh |
| 19858 | case 0x608: case 0x708: case 0x648: // vsum4ubs, vsum4sbs, vsum4shs |
| 19859 | case 0x688: case 0x788: // vsum2sws, vsumsws |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19860 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19861 | if (dis_av_arith( theInstr )) goto decode_success; |
| 19862 | goto decode_failure; |
| 19863 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 19864 | case 0x088: case 0x089: // vmulouw, vmuluwm |
| 19865 | case 0x0C0: case 0x0C2: // vaddudm, vmaxud |
| 19866 | case 0x1C2: case 0x2C2: case 0x3C2: // vnaxsd, vminud, vminsd |
| 19867 | case 0x188: case 0x288: case 0x388: // vmulosw, vmuleuw, vmulesw |
| 19868 | case 0x4C0: // vsubudm |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 19869 | if (!allow_isa_2_07) goto decode_noP8; |
| 19870 | if (dis_av_arith( theInstr )) goto decode_success; |
| 19871 | goto decode_failure; |
| 19872 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 19873 | /* AV Polynomial Vector Multiply Add */ |
| 19874 | case 0x408: case 0x448: // vpmsumb, vpmsumd |
| 19875 | case 0x488: case 0x4C8: // vpmsumw, vpmsumh |
| 19876 | if (!allow_isa_2_07) goto decode_noP8; |
| 19877 | if (dis_av_polymultarith( theInstr )) goto decode_success; |
| 19878 | goto decode_failure; |
| 19879 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19880 | /* AV Rotate, Shift */ |
| 19881 | case 0x004: case 0x044: case 0x084: // vrlb, vrlh, vrlw |
| 19882 | case 0x104: case 0x144: case 0x184: // vslb, vslh, vslw |
| 19883 | case 0x204: case 0x244: case 0x284: // vsrb, vsrh, vsrw |
| 19884 | case 0x304: case 0x344: case 0x384: // vsrab, vsrah, vsraw |
| 19885 | case 0x1C4: case 0x2C4: // vsl, vsr |
| 19886 | case 0x40C: case 0x44C: // vslo, vsro |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19887 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19888 | if (dis_av_shift( theInstr )) goto decode_success; |
| 19889 | goto decode_failure; |
| 19890 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 19891 | case 0x0C4: // vrld |
| 19892 | case 0x3C4: case 0x5C4: case 0x6C4: // vsrad, vsld, vsrd |
| 19893 | if (!allow_isa_2_07) goto decode_noP8; |
| 19894 | if (dis_av_shift( theInstr )) goto decode_success; |
| 19895 | goto decode_failure; |
| 19896 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19897 | /* AV Logic */ |
| 19898 | case 0x404: case 0x444: case 0x484: // vand, vandc, vor |
| 19899 | case 0x4C4: case 0x504: // vxor, vnor |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19900 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19901 | if (dis_av_logic( theInstr )) goto decode_success; |
| 19902 | goto decode_failure; |
| 19903 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 19904 | case 0x544: // vorc |
| 19905 | case 0x584: case 0x684: // vnand, veqv |
| 19906 | if (!allow_isa_2_07) goto decode_noP8; |
| 19907 | if (dis_av_logic( theInstr )) goto decode_success; |
| 19908 | goto decode_failure; |
| 19909 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19910 | /* AV Processor Control */ |
| 19911 | case 0x604: case 0x644: // mfvscr, mtvscr |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19912 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19913 | if (dis_av_procctl( theInstr )) goto decode_success; |
| 19914 | goto decode_failure; |
| 19915 | |
| 19916 | /* AV Floating Point Arithmetic */ |
| 19917 | case 0x00A: case 0x04A: // vaddfp, vsubfp |
| 19918 | case 0x10A: case 0x14A: case 0x18A: // vrefp, vrsqrtefp, vexptefp |
| 19919 | case 0x1CA: // vlogefp |
| 19920 | case 0x40A: case 0x44A: // vmaxfp, vminfp |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19921 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19922 | if (dis_av_fp_arith( theInstr )) goto decode_success; |
| 19923 | goto decode_failure; |
| 19924 | |
| 19925 | /* AV Floating Point Round/Convert */ |
| 19926 | case 0x20A: case 0x24A: case 0x28A: // vrfin, vrfiz, vrfip |
| 19927 | case 0x2CA: // vrfim |
| 19928 | case 0x30A: case 0x34A: case 0x38A: // vcfux, vcfsx, vctuxs |
| 19929 | case 0x3CA: // vctsxs |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19930 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19931 | if (dis_av_fp_convert( theInstr )) goto decode_success; |
| 19932 | goto decode_failure; |
| 19933 | |
| 19934 | /* AV Merge, Splat */ |
| 19935 | case 0x00C: case 0x04C: case 0x08C: // vmrghb, vmrghh, vmrghw |
| 19936 | case 0x10C: case 0x14C: case 0x18C: // vmrglb, vmrglh, vmrglw |
| 19937 | case 0x20C: case 0x24C: case 0x28C: // vspltb, vsplth, vspltw |
| 19938 | case 0x30C: case 0x34C: case 0x38C: // vspltisb, vspltish, vspltisw |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 19939 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19940 | if (dis_av_permute( theInstr )) goto decode_success; |
| 19941 | goto decode_failure; |
| 19942 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 19943 | case 0x68C: case 0x78C: // vmrgow, vmrgew |
| 19944 | if (!allow_isa_2_07) goto decode_noP8; |
| 19945 | if (dis_av_permute( theInstr )) goto decode_success; |
| 19946 | goto decode_failure; |
| 19947 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19948 | /* AV Pack, Unpack */ |
| 19949 | case 0x00E: case 0x04E: case 0x08E: // vpkuhum, vpkuwum, vpkuhus |
| 19950 | case 0x0CE: // vpkuwus |
| 19951 | case 0x10E: case 0x14E: case 0x18E: // vpkshus, vpkswus, vpkshss |
| 19952 | case 0x1CE: // vpkswss |
| 19953 | case 0x20E: case 0x24E: case 0x28E: // vupkhsb, vupkhsh, vupklsb |
| 19954 | case 0x2CE: // vupklsh |
| 19955 | case 0x30E: case 0x34E: case 0x3CE: // vpkpx, vupkhpx, vupklpx |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 19956 | if (!allow_V) goto decode_noV; |
| 19957 | if (dis_av_pack( theInstr )) goto decode_success; |
| 19958 | goto decode_failure; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 19959 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 19960 | case 0x44E: case 0x4CE: case 0x54E: // vpkudum, vpkudus, vpksdus |
| 19961 | case 0x5CE: case 0x64E: case 0x6cE: // vpksdss, vupkhsw, vupklsw |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 19962 | if (!allow_isa_2_07) goto decode_noP8; |
| 19963 | if (dis_av_pack( theInstr )) goto decode_success; |
| 19964 | goto decode_failure; |
| 19965 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 19966 | case 0x508: case 0x509: // vcipher, vcipherlast |
| 19967 | case 0x548: case 0x549: // vncipher, vncipherlast |
| 19968 | case 0x5C8: // vsbox |
| 19969 | if (!allow_isa_2_07) goto decode_noP8; |
| 19970 | if (dis_av_cipher( theInstr )) goto decode_success; |
| 19971 | goto decode_failure; |
| 19972 | |
| 19973 | case 0x6C2: case 0x682: // vshasigmaw, vshasigmad |
| 19974 | if (!allow_isa_2_07) goto decode_noP8; |
| 19975 | if (dis_av_hash( theInstr )) goto decode_success; |
| 19976 | goto decode_failure; |
| 19977 | |
| 19978 | case 0x702: case 0x742: // vclzb, vclzh |
| 19979 | case 0x782: case 0x7c2: // vclzw, vclzd |
| 19980 | if (!allow_isa_2_07) goto decode_noP8; |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 19981 | if (dis_av_count_bitTranspose( theInstr, opc2 )) goto decode_success; |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 19982 | goto decode_failure; |
| 19983 | |
| 19984 | case 0x703: case 0x743: // vpopcntb, vpopcnth |
| 19985 | case 0x783: case 0x7c3: // vpopcntw, vpopcntd |
| 19986 | if (!allow_isa_2_07) goto decode_noP8; |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 19987 | if (dis_av_count_bitTranspose( theInstr, opc2 )) goto decode_success; |
| 19988 | goto decode_failure; |
| 19989 | |
| 19990 | case 0x50c: // vgbbd |
| 19991 | if (!allow_isa_2_07) goto decode_noP8; |
| 19992 | if (dis_av_count_bitTranspose( theInstr, opc2 )) goto decode_success; |
| 19993 | goto decode_failure; |
| 19994 | |
| 19995 | case 0x140: case 0x100: // vaddcuq, vadduqm |
| 19996 | case 0x540: case 0x500: // vsubcuq, vsubuqm |
| 19997 | case 0x54C: // vbpermq |
| 19998 | if (!allow_V) goto decode_noV; |
| 19999 | if (dis_av_quad( theInstr)) goto decode_success; |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 20000 | goto decode_failure; |
| 20001 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 20002 | default: |
| 20003 | break; // Fall through... |
| 20004 | } |
| 20005 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 20006 | opc2 = IFIELD(theInstr, 0, 10); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 20007 | switch (opc2) { |
| 20008 | |
| 20009 | /* AV Compare */ |
| 20010 | case 0x006: case 0x046: case 0x086: // vcmpequb, vcmpequh, vcmpequw |
| 20011 | case 0x206: case 0x246: case 0x286: // vcmpgtub, vcmpgtuh, vcmpgtuw |
| 20012 | case 0x306: case 0x346: case 0x386: // vcmpgtsb, vcmpgtsh, vcmpgtsw |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20013 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 20014 | if (dis_av_cmp( theInstr )) goto decode_success; |
| 20015 | goto decode_failure; |
| 20016 | |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 20017 | case 0x0C7: // vcmpequd |
| 20018 | case 0x2C7: // vcmpgtud |
| 20019 | case 0x3C7: // vcmpgtsd |
| 20020 | if (!allow_isa_2_07) goto decode_noP8; |
| 20021 | if (dis_av_cmp( theInstr )) goto decode_success; |
| 20022 | goto decode_failure; |
| 20023 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 20024 | /* AV Floating Point Compare */ |
| 20025 | case 0x0C6: case 0x1C6: case 0x2C6: // vcmpeqfp, vcmpgefp, vcmpgtfp |
| 20026 | case 0x3C6: // vcmpbfp |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20027 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 20028 | if (dis_av_fp_cmp( theInstr )) goto decode_success; |
| 20029 | goto decode_failure; |
| 20030 | |
| 20031 | default: |
| 20032 | goto decode_failure; |
| 20033 | } |
| 20034 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 20035 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 20036 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 20037 | goto decode_failure; |
| 20038 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20039 | decode_noF: |
| 20040 | vassert(!allow_F); |
| 20041 | vex_printf("disInstr(ppc): declined to decode an FP insn.\n"); |
| 20042 | goto decode_failure; |
| 20043 | decode_noV: |
| 20044 | vassert(!allow_V); |
| 20045 | vex_printf("disInstr(ppc): declined to decode an AltiVec insn.\n"); |
| 20046 | goto decode_failure; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 20047 | decode_noVX: |
| 20048 | vassert(!allow_VX); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 20049 | vex_printf("disInstr(ppc): declined to decode a Power ISA 2.06 insn.\n"); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 20050 | goto decode_failure; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20051 | decode_noFX: |
sewardj | 7c54586 | 2006-01-27 21:52:19 +0000 | [diff] [blame] | 20052 | vassert(!allow_FX); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20053 | vex_printf("disInstr(ppc): " |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 20054 | "declined to decode a GeneralPurpose-Optional insn.\n"); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20055 | goto decode_failure; |
| 20056 | decode_noGX: |
sewardj | 7c54586 | 2006-01-27 21:52:19 +0000 | [diff] [blame] | 20057 | vassert(!allow_GX); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20058 | vex_printf("disInstr(ppc): " |
| 20059 | "declined to decode a Graphics-Optional insn.\n"); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 20060 | goto decode_failure; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 20061 | decode_noDFP: |
| 20062 | vassert(!allow_DFP); |
| 20063 | vex_printf("disInstr(ppc): " |
| 20064 | "declined to decode a Decimal Floating Point insn.\n"); |
| 20065 | goto decode_failure; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 20066 | decode_noP8: |
| 20067 | vassert(!allow_isa_2_07); |
| 20068 | vex_printf("disInstr(ppc): " |
| 20069 | "declined to decode a Power 8 insn.\n"); |
| 20070 | goto decode_failure; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 20071 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 20072 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 20073 | decode_failure: |
| 20074 | /* All decode failures end up here. */ |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 20075 | opc2 = (theInstr) & 0x7FF; |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 20076 | if (sigill_diag) { |
| 20077 | vex_printf("disInstr(ppc): unhandled instruction: " |
| 20078 | "0x%x\n", theInstr); |
| 20079 | vex_printf(" primary %d(0x%x), secondary %u(0x%x)\n", |
| 20080 | opc1, opc1, opc2, opc2); |
| 20081 | } |
cerion | 995bc36 | 2005-02-03 11:03:31 +0000 | [diff] [blame] | 20082 | |
sewardj | 01a9e80 | 2005-02-01 20:46:00 +0000 | [diff] [blame] | 20083 | /* Tell the dispatcher that this insn cannot be decoded, and so has |
| 20084 | not been executed, and (is currently) the next to be executed. |
| 20085 | CIA should be up-to-date since it made so at the start of each |
| 20086 | insn, but nevertheless be paranoid and update it again right |
| 20087 | now. */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 20088 | putGST( PPC_GST_CIA, mkSzImm(ty, guest_CIA_curr_instr) ); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 20089 | dres.whatNext = Dis_StopHere; |
| 20090 | dres.jk_StopHere = Ijk_NoDecode; |
| 20091 | dres.len = 0; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 20092 | return dres; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 20093 | |
| 20094 | } /* switch (opc) for the main (primary) opcode switch. */ |
| 20095 | |
| 20096 | decode_success: |
| 20097 | /* All decode successes end up here. */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 20098 | switch (dres.whatNext) { |
| 20099 | case Dis_Continue: |
| 20100 | putGST( PPC_GST_CIA, mkSzImm(ty, guest_CIA_curr_instr + 4)); |
| 20101 | break; |
| 20102 | case Dis_ResteerU: |
| 20103 | case Dis_ResteerC: |
| 20104 | putGST( PPC_GST_CIA, mkSzImm(ty, dres.continueAt)); |
| 20105 | break; |
| 20106 | case Dis_StopHere: |
| 20107 | break; |
| 20108 | default: |
| 20109 | vassert(0); |
| 20110 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 20111 | DIP("\n"); |
| 20112 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 20113 | if (dres.len == 0) { |
| 20114 | dres.len = 4; |
| 20115 | } else { |
| 20116 | vassert(dres.len == 20); |
| 20117 | } |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 20118 | return dres; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 20119 | } |
| 20120 | |
| 20121 | #undef DIP |
| 20122 | #undef DIS |
| 20123 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 20124 | |
| 20125 | /*------------------------------------------------------------*/ |
| 20126 | /*--- Top-level fn ---*/ |
| 20127 | /*------------------------------------------------------------*/ |
| 20128 | |
| 20129 | /* Disassemble a single instruction into IR. The instruction |
| 20130 | is located in host memory at &guest_code[delta]. */ |
| 20131 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 20132 | DisResult disInstr_PPC ( IRSB* irsb_IN, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 20133 | Bool (*resteerOkFn) ( void*, Addr64 ), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 20134 | Bool resteerCisOk, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 20135 | void* callback_opaque, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 20136 | UChar* guest_code_IN, |
| 20137 | Long delta, |
| 20138 | Addr64 guest_IP, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 20139 | VexArch guest_arch, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 20140 | VexArchInfo* archinfo, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 20141 | VexAbiInfo* abiinfo, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 20142 | VexEndness host_endness_IN, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 20143 | Bool sigill_diag_IN ) |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 20144 | { |
sewardj | 5df65bb | 2005-11-29 14:47:04 +0000 | [diff] [blame] | 20145 | IRType ty; |
| 20146 | DisResult dres; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20147 | UInt mask32, mask64; |
| 20148 | UInt hwcaps_guest = archinfo->hwcaps; |
| 20149 | |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 20150 | vassert(guest_arch == VexArchPPC32 || guest_arch == VexArchPPC64); |
sewardj | 5df65bb | 2005-11-29 14:47:04 +0000 | [diff] [blame] | 20151 | |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 20152 | /* global -- ick */ |
| 20153 | mode64 = guest_arch == VexArchPPC64; |
| 20154 | ty = mode64 ? Ity_I64 : Ity_I32; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 20155 | if (!mode64 && (host_endness_IN == VexEndnessLE)) { |
| 20156 | vex_printf("disInstr(ppc): Little Endian 32-bit mode is not supported\n"); |
| 20157 | dres.whatNext = Dis_StopHere; |
| 20158 | dres.jk_StopHere = Ijk_NoDecode; |
| 20159 | dres.len = 0; |
| 20160 | return dres; |
| 20161 | } |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 20162 | |
| 20163 | /* do some sanity checks */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20164 | mask32 = VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 20165 | | VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX | VEX_HWCAPS_PPC32_VX |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 20166 | | VEX_HWCAPS_PPC32_DFP | VEX_HWCAPS_PPC32_ISA2_07; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20167 | |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 20168 | mask64 = VEX_HWCAPS_PPC64_V | VEX_HWCAPS_PPC64_FX |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 20169 | | VEX_HWCAPS_PPC64_GX | VEX_HWCAPS_PPC64_VX | VEX_HWCAPS_PPC64_DFP |
| 20170 | | VEX_HWCAPS_PPC64_ISA2_07; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 20171 | |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 20172 | if (mode64) { |
| 20173 | vassert((hwcaps_guest & mask32) == 0); |
| 20174 | } else { |
| 20175 | vassert((hwcaps_guest & mask64) == 0); |
| 20176 | } |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 20177 | |
| 20178 | /* Set globals (see top of this file) */ |
| 20179 | guest_code = guest_code_IN; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 20180 | irsb = irsb_IN; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 20181 | host_endness = host_endness_IN; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 20182 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 20183 | guest_CIA_curr_instr = mkSzAddr(ty, guest_IP); |
| 20184 | guest_CIA_bbstart = mkSzAddr(ty, guest_IP - delta); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 20185 | |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 20186 | dres = disInstr_PPC_WRK ( resteerOkFn, resteerCisOk, callback_opaque, |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame^] | 20187 | delta, archinfo, abiinfo, sigill_diag_IN); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 20188 | |
| 20189 | return dres; |
| 20190 | } |
| 20191 | |
| 20192 | |
sewardj | c808ef7 | 2005-08-18 11:50:43 +0000 | [diff] [blame] | 20193 | /*------------------------------------------------------------*/ |
| 20194 | /*--- Unused stuff ---*/ |
| 20195 | /*------------------------------------------------------------*/ |
| 20196 | |
| 20197 | ///* A potentially more memcheck-friendly implementation of Clz32, with |
| 20198 | // the boundary case Clz32(0) = 32, which is what ppc requires. */ |
| 20199 | // |
| 20200 | //static IRExpr* /* :: Ity_I32 */ verbose_Clz32 ( IRTemp arg ) |
| 20201 | //{ |
| 20202 | // /* Welcome ... to SSA R Us. */ |
| 20203 | // IRTemp n1 = newTemp(Ity_I32); |
| 20204 | // IRTemp n2 = newTemp(Ity_I32); |
| 20205 | // IRTemp n3 = newTemp(Ity_I32); |
| 20206 | // IRTemp n4 = newTemp(Ity_I32); |
| 20207 | // IRTemp n5 = newTemp(Ity_I32); |
| 20208 | // IRTemp n6 = newTemp(Ity_I32); |
| 20209 | // IRTemp n7 = newTemp(Ity_I32); |
| 20210 | // IRTemp n8 = newTemp(Ity_I32); |
| 20211 | // IRTemp n9 = newTemp(Ity_I32); |
| 20212 | // IRTemp n10 = newTemp(Ity_I32); |
| 20213 | // IRTemp n11 = newTemp(Ity_I32); |
| 20214 | // IRTemp n12 = newTemp(Ity_I32); |
| 20215 | // |
| 20216 | // /* First, propagate the most significant 1-bit into all lower |
| 20217 | // positions in the word. */ |
| 20218 | // /* unsigned int clz ( unsigned int n ) |
| 20219 | // { |
| 20220 | // n |= (n >> 1); |
| 20221 | // n |= (n >> 2); |
| 20222 | // n |= (n >> 4); |
| 20223 | // n |= (n >> 8); |
| 20224 | // n |= (n >> 16); |
| 20225 | // return bitcount(~n); |
| 20226 | // } |
| 20227 | // */ |
| 20228 | // assign(n1, mkexpr(arg)); |
| 20229 | // assign(n2, binop(Iop_Or32, mkexpr(n1), binop(Iop_Shr32, mkexpr(n1), mkU8(1)))); |
| 20230 | // assign(n3, binop(Iop_Or32, mkexpr(n2), binop(Iop_Shr32, mkexpr(n2), mkU8(2)))); |
| 20231 | // assign(n4, binop(Iop_Or32, mkexpr(n3), binop(Iop_Shr32, mkexpr(n3), mkU8(4)))); |
| 20232 | // assign(n5, binop(Iop_Or32, mkexpr(n4), binop(Iop_Shr32, mkexpr(n4), mkU8(8)))); |
| 20233 | // assign(n6, binop(Iop_Or32, mkexpr(n5), binop(Iop_Shr32, mkexpr(n5), mkU8(16)))); |
| 20234 | // /* This gives a word of the form 0---01---1. Now invert it, giving |
| 20235 | // a word of the form 1---10---0, then do a population-count idiom |
| 20236 | // (to count the 1s, which is the number of leading zeroes, or 32 |
| 20237 | // if the original word was 0. */ |
| 20238 | // assign(n7, unop(Iop_Not32, mkexpr(n6))); |
| 20239 | // |
| 20240 | // /* unsigned int bitcount ( unsigned int n ) |
| 20241 | // { |
| 20242 | // n = n - ((n >> 1) & 0x55555555); |
| 20243 | // n = (n & 0x33333333) + ((n >> 2) & 0x33333333); |
| 20244 | // n = (n + (n >> 4)) & 0x0F0F0F0F; |
| 20245 | // n = n + (n >> 8); |
| 20246 | // n = (n + (n >> 16)) & 0x3F; |
| 20247 | // return n; |
| 20248 | // } |
| 20249 | // */ |
| 20250 | // assign(n8, |
| 20251 | // binop(Iop_Sub32, |
| 20252 | // mkexpr(n7), |
| 20253 | // binop(Iop_And32, |
| 20254 | // binop(Iop_Shr32, mkexpr(n7), mkU8(1)), |
| 20255 | // mkU32(0x55555555)))); |
| 20256 | // assign(n9, |
| 20257 | // binop(Iop_Add32, |
| 20258 | // binop(Iop_And32, mkexpr(n8), mkU32(0x33333333)), |
| 20259 | // binop(Iop_And32, |
| 20260 | // binop(Iop_Shr32, mkexpr(n8), mkU8(2)), |
| 20261 | // mkU32(0x33333333)))); |
| 20262 | // assign(n10, |
| 20263 | // binop(Iop_And32, |
| 20264 | // binop(Iop_Add32, |
| 20265 | // mkexpr(n9), |
| 20266 | // binop(Iop_Shr32, mkexpr(n9), mkU8(4))), |
| 20267 | // mkU32(0x0F0F0F0F))); |
| 20268 | // assign(n11, |
| 20269 | // binop(Iop_Add32, |
| 20270 | // mkexpr(n10), |
| 20271 | // binop(Iop_Shr32, mkexpr(n10), mkU8(8)))); |
| 20272 | // assign(n12, |
| 20273 | // binop(Iop_Add32, |
| 20274 | // mkexpr(n11), |
| 20275 | // binop(Iop_Shr32, mkexpr(n11), mkU8(16)))); |
| 20276 | // return |
| 20277 | // binop(Iop_And32, mkexpr(n12), mkU32(0x3F)); |
| 20278 | //} |
| 20279 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 20280 | /*--------------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 20281 | /*--- end guest_ppc_toIR.c ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 20282 | /*--------------------------------------------------------------------*/ |