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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef CMD_H
26#define CMD_H
27
28#include "intel.h"
29#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "view.h"
31
32struct intel_pipeline;
33struct intel_pipeline_delta;
34struct intel_viewport_state;
35struct intel_raster_state;
36struct intel_msaa_state;
37struct intel_blend_state;
38struct intel_ds_state;
39struct intel_dset;
40
Chia-I Wu958d1b72014-08-21 11:28:11 +080041struct intel_cmd_reloc;
42
Chia-I Wub2755562014-08-20 13:38:52 +080043/*
44 * States bounded to the command buffer. We want to write states directly to
45 * the command buffer when possible, and reduce this struct.
46 */
47struct intel_cmd_bind {
48 struct {
49 const struct intel_pipeline *graphics;
50 const struct intel_pipeline *compute;
51 const struct intel_pipeline_delta *graphics_delta;
52 const struct intel_pipeline_delta *compute_delta;
53 } pipeline;
54
55 struct {
56 const struct intel_viewport_state *viewport;
57 const struct intel_raster_state *raster;
58 const struct intel_msaa_state *msaa;
59 const struct intel_blend_state *blend;
60 const struct intel_ds_state *ds;
61 } state;
62
63 struct {
64 const struct intel_dset *graphics;
65 XGL_UINT graphics_offset;
66 const struct intel_dset *compute;
67 XGL_UINT compute_offset;
68 } dset;
69
70 struct {
71 struct intel_mem_view graphics;
72 struct intel_mem_view compute;
Chia-I Wu9f1722c2014-08-25 10:17:58 +080073 } dyn_view;
Chia-I Wub2755562014-08-20 13:38:52 +080074
75 struct {
76 const struct intel_mem *mem;
77 XGL_GPU_SIZE offset;
78 XGL_INDEX_TYPE type;
79 } index;
80
81 struct {
82 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
83 XGL_UINT rt_count;
84
85 const struct intel_ds_view *ds;
86 } att;
87};
Chia-I Wu09142132014-08-11 15:42:55 +080088
Chia-I Wue24c3292014-08-21 14:05:23 +080089struct intel_cmd_writer {
90 struct intel_bo *bo;
91 void *ptr_opaque;
92
93 /* in DWords */
94 XGL_UINT size;
95 XGL_UINT used;
96};
97
Chia-I Wu730e5362014-08-19 12:15:09 +080098struct intel_cmd {
99 struct intel_obj obj;
100
101 struct intel_dev *dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800102 struct intel_bo *scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800103 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800104
Chia-I Wu343b1372014-08-20 16:39:20 +0800105 struct intel_cmd_reloc *relocs;
106 XGL_UINT reloc_count;
107
Chia-I Wu730e5362014-08-19 12:15:09 +0800108 XGL_FLAGS flags;
109
Chia-I Wue24c3292014-08-21 14:05:23 +0800110 struct intel_cmd_writer batch;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800111 struct intel_cmd_writer state;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800112 struct intel_cmd_writer kernel;
Chia-I Wu730e5362014-08-19 12:15:09 +0800113
Chia-I Wu343b1372014-08-20 16:39:20 +0800114 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800115 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800116
117 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800118};
119
120static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
121{
122 return (struct intel_cmd *) cmd;
123}
124
125static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
126{
127 return (struct intel_cmd *) obj;
128}
129
130XGL_RESULT intel_cmd_create(struct intel_dev *dev,
131 const XGL_CMD_BUFFER_CREATE_INFO *info,
132 struct intel_cmd **cmd_ret);
133void intel_cmd_destroy(struct intel_cmd *cmd);
134
135XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
136XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
137
Chia-I Wue24c3292014-08-21 14:05:23 +0800138static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
139 XGL_GPU_SIZE *used)
140{
141 const struct intel_cmd_writer *writer = &cmd->batch;
142
143 if (used)
144 *used = sizeof(uint32_t) * writer->used;
145
146 return writer->bo;
147}
148
Chia-I Wu09142132014-08-11 15:42:55 +0800149XGL_RESULT XGLAPI intelCreateCommandBuffer(
150 XGL_DEVICE device,
151 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
152 XGL_CMD_BUFFER* pCmdBuffer);
153
154XGL_RESULT XGLAPI intelBeginCommandBuffer(
155 XGL_CMD_BUFFER cmdBuffer,
156 XGL_FLAGS flags);
157
158XGL_RESULT XGLAPI intelEndCommandBuffer(
159 XGL_CMD_BUFFER cmdBuffer);
160
161XGL_RESULT XGLAPI intelResetCommandBuffer(
162 XGL_CMD_BUFFER cmdBuffer);
163
164XGL_VOID XGLAPI intelCmdBindPipeline(
165 XGL_CMD_BUFFER cmdBuffer,
166 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
167 XGL_PIPELINE pipeline);
168
169XGL_VOID XGLAPI intelCmdBindPipelineDelta(
170 XGL_CMD_BUFFER cmdBuffer,
171 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
172 XGL_PIPELINE_DELTA delta);
173
174XGL_VOID XGLAPI intelCmdBindStateObject(
175 XGL_CMD_BUFFER cmdBuffer,
176 XGL_STATE_BIND_POINT stateBindPoint,
177 XGL_STATE_OBJECT state);
178
179XGL_VOID XGLAPI intelCmdBindDescriptorSet(
180 XGL_CMD_BUFFER cmdBuffer,
181 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
182 XGL_UINT index,
183 XGL_DESCRIPTOR_SET descriptorSet,
184 XGL_UINT slotOffset);
185
186XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
187 XGL_CMD_BUFFER cmdBuffer,
188 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
189 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
190
191XGL_VOID XGLAPI intelCmdBindIndexData(
192 XGL_CMD_BUFFER cmdBuffer,
193 XGL_GPU_MEMORY mem,
194 XGL_GPU_SIZE offset,
195 XGL_INDEX_TYPE indexType);
196
197XGL_VOID XGLAPI intelCmdBindAttachments(
198 XGL_CMD_BUFFER cmdBuffer,
199 XGL_UINT colorAttachmentCount,
200 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
201 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
202
203XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
204 XGL_CMD_BUFFER cmdBuffer,
205 XGL_UINT transitionCount,
206 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
207
208XGL_VOID XGLAPI intelCmdPrepareImages(
209 XGL_CMD_BUFFER cmdBuffer,
210 XGL_UINT transitionCount,
211 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
212
213XGL_VOID XGLAPI intelCmdDraw(
214 XGL_CMD_BUFFER cmdBuffer,
215 XGL_UINT firstVertex,
216 XGL_UINT vertexCount,
217 XGL_UINT firstInstance,
218 XGL_UINT instanceCount);
219
220XGL_VOID XGLAPI intelCmdDrawIndexed(
221 XGL_CMD_BUFFER cmdBuffer,
222 XGL_UINT firstIndex,
223 XGL_UINT indexCount,
224 XGL_INT vertexOffset,
225 XGL_UINT firstInstance,
226 XGL_UINT instanceCount);
227
228XGL_VOID XGLAPI intelCmdDrawIndirect(
229 XGL_CMD_BUFFER cmdBuffer,
230 XGL_GPU_MEMORY mem,
231 XGL_GPU_SIZE offset,
232 XGL_UINT32 count,
233 XGL_UINT32 stride);
234
235XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
236 XGL_CMD_BUFFER cmdBuffer,
237 XGL_GPU_MEMORY mem,
238 XGL_GPU_SIZE offset,
239 XGL_UINT32 count,
240 XGL_UINT32 stride);
241
242XGL_VOID XGLAPI intelCmdDispatch(
243 XGL_CMD_BUFFER cmdBuffer,
244 XGL_UINT x,
245 XGL_UINT y,
246 XGL_UINT z);
247
248XGL_VOID XGLAPI intelCmdDispatchIndirect(
249 XGL_CMD_BUFFER cmdBuffer,
250 XGL_GPU_MEMORY mem,
251 XGL_GPU_SIZE offset);
252
253XGL_VOID XGLAPI intelCmdCopyMemory(
254 XGL_CMD_BUFFER cmdBuffer,
255 XGL_GPU_MEMORY srcMem,
256 XGL_GPU_MEMORY destMem,
257 XGL_UINT regionCount,
258 const XGL_MEMORY_COPY* pRegions);
259
260XGL_VOID XGLAPI intelCmdCopyImage(
261 XGL_CMD_BUFFER cmdBuffer,
262 XGL_IMAGE srcImage,
263 XGL_IMAGE destImage,
264 XGL_UINT regionCount,
265 const XGL_IMAGE_COPY* pRegions);
266
267XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
268 XGL_CMD_BUFFER cmdBuffer,
269 XGL_GPU_MEMORY srcMem,
270 XGL_IMAGE destImage,
271 XGL_UINT regionCount,
272 const XGL_MEMORY_IMAGE_COPY* pRegions);
273
274XGL_VOID XGLAPI intelCmdCopyImageToMemory(
275 XGL_CMD_BUFFER cmdBuffer,
276 XGL_IMAGE srcImage,
277 XGL_GPU_MEMORY destMem,
278 XGL_UINT regionCount,
279 const XGL_MEMORY_IMAGE_COPY* pRegions);
280
281XGL_VOID XGLAPI intelCmdCloneImageData(
282 XGL_CMD_BUFFER cmdBuffer,
283 XGL_IMAGE srcImage,
284 XGL_IMAGE_STATE srcImageState,
285 XGL_IMAGE destImage,
286 XGL_IMAGE_STATE destImageState);
287
288XGL_VOID XGLAPI intelCmdUpdateMemory(
289 XGL_CMD_BUFFER cmdBuffer,
290 XGL_GPU_MEMORY destMem,
291 XGL_GPU_SIZE destOffset,
292 XGL_GPU_SIZE dataSize,
293 const XGL_UINT32* pData);
294
295XGL_VOID XGLAPI intelCmdFillMemory(
296 XGL_CMD_BUFFER cmdBuffer,
297 XGL_GPU_MEMORY destMem,
298 XGL_GPU_SIZE destOffset,
299 XGL_GPU_SIZE fillSize,
300 XGL_UINT32 data);
301
302XGL_VOID XGLAPI intelCmdClearColorImage(
303 XGL_CMD_BUFFER cmdBuffer,
304 XGL_IMAGE image,
305 const XGL_FLOAT color[4],
306 XGL_UINT rangeCount,
307 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
308
309XGL_VOID XGLAPI intelCmdClearColorImageRaw(
310 XGL_CMD_BUFFER cmdBuffer,
311 XGL_IMAGE image,
312 const XGL_UINT32 color[4],
313 XGL_UINT rangeCount,
314 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
315
316XGL_VOID XGLAPI intelCmdClearDepthStencil(
317 XGL_CMD_BUFFER cmdBuffer,
318 XGL_IMAGE image,
319 XGL_FLOAT depth,
320 XGL_UINT32 stencil,
321 XGL_UINT rangeCount,
322 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
323
324XGL_VOID XGLAPI intelCmdResolveImage(
325 XGL_CMD_BUFFER cmdBuffer,
326 XGL_IMAGE srcImage,
327 XGL_IMAGE destImage,
328 XGL_UINT rectCount,
329 const XGL_IMAGE_RESOLVE* pRects);
330
331XGL_VOID XGLAPI intelCmdSetEvent(
332 XGL_CMD_BUFFER cmdBuffer,
333 XGL_EVENT event);
334
335XGL_VOID XGLAPI intelCmdResetEvent(
336 XGL_CMD_BUFFER cmdBuffer,
337 XGL_EVENT event);
338
339XGL_VOID XGLAPI intelCmdMemoryAtomic(
340 XGL_CMD_BUFFER cmdBuffer,
341 XGL_GPU_MEMORY destMem,
342 XGL_GPU_SIZE destOffset,
343 XGL_UINT64 srcData,
344 XGL_ATOMIC_OP atomicOp);
345
346XGL_VOID XGLAPI intelCmdBeginQuery(
347 XGL_CMD_BUFFER cmdBuffer,
348 XGL_QUERY_POOL queryPool,
349 XGL_UINT slot,
350 XGL_FLAGS flags);
351
352XGL_VOID XGLAPI intelCmdEndQuery(
353 XGL_CMD_BUFFER cmdBuffer,
354 XGL_QUERY_POOL queryPool,
355 XGL_UINT slot);
356
357XGL_VOID XGLAPI intelCmdResetQueryPool(
358 XGL_CMD_BUFFER cmdBuffer,
359 XGL_QUERY_POOL queryPool,
360 XGL_UINT startQuery,
361 XGL_UINT queryCount);
362
363XGL_VOID XGLAPI intelCmdWriteTimestamp(
364 XGL_CMD_BUFFER cmdBuffer,
365 XGL_TIMESTAMP_TYPE timestampType,
366 XGL_GPU_MEMORY destMem,
367 XGL_GPU_SIZE destOffset);
368
369XGL_VOID XGLAPI intelCmdInitAtomicCounters(
370 XGL_CMD_BUFFER cmdBuffer,
371 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
372 XGL_UINT startCounter,
373 XGL_UINT counterCount,
374 const XGL_UINT32* pData);
375
376XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
377 XGL_CMD_BUFFER cmdBuffer,
378 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
379 XGL_UINT startCounter,
380 XGL_UINT counterCount,
381 XGL_GPU_MEMORY srcMem,
382 XGL_GPU_SIZE srcOffset);
383
384XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
385 XGL_CMD_BUFFER cmdBuffer,
386 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
387 XGL_UINT startCounter,
388 XGL_UINT counterCount,
389 XGL_GPU_MEMORY destMem,
390 XGL_GPU_SIZE destOffset);
391
392XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
393 XGL_CMD_BUFFER cmdBuffer,
394 const XGL_CHAR* pMarker);
395
396XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
397 XGL_CMD_BUFFER cmdBuffer);
398
399#endif /* CMD_H */