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Chia-I Wu00a23b22014-08-20 15:28:08 +08001/*
Courtney Goeltzenleuchter9cc421e2015-04-08 15:36:08 -06002 * Vulkan
Chia-I Wu00a23b22014-08-20 15:28:08 +08003 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu00a23b22014-08-20 15:28:08 +080026 */
27
28#ifndef CMD_PRIV_H
29#define CMD_PRIV_H
30
Chia-I Wue24c3292014-08-21 14:05:23 +080031#include "genhw/genhw.h"
Chia-I Wu32710d72014-08-20 16:05:22 +080032#include "dev.h"
Chia-I Wubdeed152015-07-09 12:16:29 +080033#include "fb.h"
Chia-I Wu32710d72014-08-20 16:05:22 +080034#include "gpu.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080035#include "cmd.h"
36
Chia-I Wu32710d72014-08-20 16:05:22 +080037#define CMD_ASSERT(cmd, min_gen, max_gen) \
38 INTEL_GPU_ASSERT((cmd)->dev->gpu, (min_gen), (max_gen))
39
Chia-I Wu00b51a82014-09-09 12:07:37 +080040enum intel_cmd_item_type {
41 /* for state buffer */
42 INTEL_CMD_ITEM_BLOB,
43 INTEL_CMD_ITEM_CLIP_VIEWPORT,
44 INTEL_CMD_ITEM_SF_VIEWPORT,
45 INTEL_CMD_ITEM_SCISSOR_RECT,
46 INTEL_CMD_ITEM_CC_VIEWPORT,
47 INTEL_CMD_ITEM_COLOR_CALC,
48 INTEL_CMD_ITEM_DEPTH_STENCIL,
49 INTEL_CMD_ITEM_BLEND,
50 INTEL_CMD_ITEM_SAMPLER,
51
52 /* for surface buffer */
53 INTEL_CMD_ITEM_SURFACE,
54 INTEL_CMD_ITEM_BINDING_TABLE,
55
56 /* for instruction buffer */
57 INTEL_CMD_ITEM_KERNEL,
58
59 INTEL_CMD_ITEM_COUNT,
60};
61
62struct intel_cmd_item {
63 enum intel_cmd_item_type type;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060064 size_t offset;
65 size_t size;
Chia-I Wu00b51a82014-09-09 12:07:37 +080066};
67
Chia-I Wud7d1e482014-10-18 13:25:10 +080068#define INTEL_CMD_RELOC_TARGET_IS_WRITER (1u << 31)
Chia-I Wu958d1b72014-08-21 11:28:11 +080069struct intel_cmd_reloc {
Chia-I Wu68f319d2014-09-09 09:43:21 +080070 enum intel_cmd_writer_type which;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060071 size_t offset;
Chia-I Wu958d1b72014-08-21 11:28:11 +080072
Chia-I Wud7d1e482014-10-18 13:25:10 +080073 intptr_t target;
74 uint32_t target_offset;
Chia-I Wu958d1b72014-08-21 11:28:11 +080075
Chia-I Wu32a22462014-08-26 14:13:46 +080076 uint32_t flags;
Chia-I Wu958d1b72014-08-21 11:28:11 +080077};
78
Chia-I Wu3d4d4a62015-07-09 10:34:10 +080079struct intel_att_view;
Chia-I Wuc14d1562014-10-17 09:49:22 +080080
Chia-I Wu29e6f502014-11-24 14:27:29 +080081enum intel_cmd_meta_mode {
82 /*
Chia-I Wu4d344e62014-12-20 21:06:04 +080083 * Draw POINTLIST of (width * height) vertices with only VS enabled. The
84 * vertex id is from 0 to (width * height - 1).
Chia-I Wu29e6f502014-11-24 14:27:29 +080085 */
86 INTEL_CMD_META_VS_POINTS,
87
88 /*
89 * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height)
90 * with only FS enabled.
91 */
92 INTEL_CMD_META_FS_RECT,
93
94 /*
95 * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height)
96 * with only depth/stencil enabled.
97 */
98 INTEL_CMD_META_DEPTH_STENCIL_RECT,
99};
100
Chia-I Wu73520ac2015-02-19 11:17:45 -0700101enum intel_cmd_meta_ds_op {
102 INTEL_CMD_META_DS_NOP,
103 INTEL_CMD_META_DS_HIZ_CLEAR,
104 INTEL_CMD_META_DS_HIZ_RESOLVE,
105 INTEL_CMD_META_DS_RESOLVE,
106};
107
Chia-I Wuc14d1562014-10-17 09:49:22 +0800108struct intel_cmd_meta {
Chia-I Wu29e6f502014-11-24 14:27:29 +0800109 enum intel_cmd_meta_mode mode;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800110 enum intel_dev_meta_shader shader_id;
111
112 struct {
113 bool valid;
114
115 uint32_t surface[8];
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600116 uint32_t surface_len;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800117
118 intptr_t reloc_target;
119 uint32_t reloc_offset;
120 uint32_t reloc_flags;
121
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600122 uint32_t lod, layer;
123 uint32_t x, y;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800124 } src, dst;
125
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800126 struct {
Courtney Goeltzenleuchter1856d6f2015-09-01 17:30:39 -0600127 struct intel_att_view view;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700128 uint32_t stencil_ref;
Courtney Goeltzenleuchter382489d2015-04-10 08:34:15 -0600129 VkImageAspect aspect;
Chia-I Wu73520ac2015-02-19 11:17:45 -0700130
131 enum intel_cmd_meta_ds_op op;
132 bool optimal;
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800133 } ds;
134
Chia-I Wuc14d1562014-10-17 09:49:22 +0800135 uint32_t clear_val[4];
136
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600137 uint32_t width, height;
138 uint32_t samples;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800139};
140
Chia-I Wu9f039862014-08-20 15:39:56 +0800141static inline int cmd_gen(const struct intel_cmd *cmd)
142{
143 return intel_gpu_gen(cmd->dev->gpu);
144}
145
Courtney Goeltzenleuchter382489d2015-04-10 08:34:15 -0600146static inline void cmd_fail(struct intel_cmd *cmd, VkResult result)
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700147{
Courtney Goeltzenleuchter1c7c65d2015-06-10 17:39:03 -0600148 intel_dev_log(cmd->dev, VK_DBG_REPORT_ERROR_BIT,
149 &cmd->obj.base, 0, 0,
150 "command building error");
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700151
152 cmd->result = result;
153}
154
Chia-I Wucdff0592014-08-22 09:27:36 +0800155static inline void cmd_reserve_reloc(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600156 uint32_t reloc_len)
Chia-I Wucdff0592014-08-22 09:27:36 +0800157{
158 /* fail silently */
159 if (cmd->reloc_used + reloc_len > cmd->reloc_count) {
160 cmd->reloc_used = 0;
Courtney Goeltzenleuchterac834522015-05-01 17:56:13 -0600161 cmd_fail(cmd, VK_ERROR_UNKNOWN);
Chia-I Wucdff0592014-08-22 09:27:36 +0800162 }
163 assert(cmd->reloc_used + reloc_len <= cmd->reloc_count);
164}
165
Chia-I Wue24c3292014-08-21 14:05:23 +0800166void cmd_writer_grow(struct intel_cmd *cmd,
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800167 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600168 size_t new_size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800169
Chia-I Wu00b51a82014-09-09 12:07:37 +0800170void cmd_writer_record(struct intel_cmd *cmd,
171 enum intel_cmd_writer_type which,
172 enum intel_cmd_item_type type,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600173 size_t offset, size_t size);
Chia-I Wu00b51a82014-09-09 12:07:37 +0800174
Chia-I Wu72292b72014-09-09 10:48:33 +0800175/**
176 * Return an offset to a region that is aligned to \p alignment and has at
177 * least \p size bytes.
178 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600179static inline size_t cmd_writer_reserve(struct intel_cmd *cmd,
180 enum intel_cmd_writer_type which,
181 size_t alignment, size_t size)
Chia-I Wu72292b72014-09-09 10:48:33 +0800182{
183 struct intel_cmd_writer *writer = &cmd->writers[which];
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600184 size_t offset;
Chia-I Wu72292b72014-09-09 10:48:33 +0800185
186 assert(alignment && u_is_pow2(alignment));
187 offset = u_align(writer->used, alignment);
188
189 if (offset + size > writer->size) {
190 cmd_writer_grow(cmd, which, offset + size);
191 /* align again in case of errors */
192 offset = u_align(writer->used, alignment);
193
194 assert(offset + size <= writer->size);
195 }
196
197 return offset;
198}
Chia-I Wu00a23b22014-08-20 15:28:08 +0800199
Chia-I Wu32710d72014-08-20 16:05:22 +0800200/**
Chia-I Wubda55fd2014-08-25 12:46:10 +0800201 * Add a reloc at \p pos. No error checking.
Chia-I Wucdff0592014-08-22 09:27:36 +0800202 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800203static inline void cmd_writer_reloc(struct intel_cmd *cmd,
204 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600205 size_t offset, intptr_t target,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800206 uint32_t target_offset, uint32_t flags)
Chia-I Wucdff0592014-08-22 09:27:36 +0800207{
208 struct intel_cmd_reloc *reloc = &cmd->relocs[cmd->reloc_used];
209
210 assert(cmd->reloc_used < cmd->reloc_count);
211
Chia-I Wu68f319d2014-09-09 09:43:21 +0800212 reloc->which = which;
Chia-I Wu72292b72014-09-09 10:48:33 +0800213 reloc->offset = offset;
Chia-I Wud7d1e482014-10-18 13:25:10 +0800214 reloc->target = target;
215 reloc->target_offset = target_offset;
Chia-I Wu32a22462014-08-26 14:13:46 +0800216 reloc->flags = flags;
Chia-I Wucdff0592014-08-22 09:27:36 +0800217
218 cmd->reloc_used++;
219}
220
221/**
Chia-I Wu5da476a2014-12-10 08:50:28 +0800222 * Reserve a region from the state buffer. The offset, in bytes, to the
223 * reserved region is returned.
Chia-I Wu72292b72014-09-09 10:48:33 +0800224 *
225 * Note that \p alignment is in bytes and \p len is in DWords.
Chia-I Wue24c3292014-08-21 14:05:23 +0800226 */
Chia-I Wu5da476a2014-12-10 08:50:28 +0800227static inline uint32_t cmd_state_reserve(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800228 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600229 size_t alignment, uint32_t len)
Chia-I Wue24c3292014-08-21 14:05:23 +0800230{
Chia-I Wu72292b72014-09-09 10:48:33 +0800231 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600232 const size_t size = len << 2;
233 const size_t offset = cmd_writer_reserve(cmd, which, alignment, size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800234 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wue24c3292014-08-21 14:05:23 +0800235
Chia-I Wu72292b72014-09-09 10:48:33 +0800236 /* all states are at least aligned to 32-bytes */
237 assert(alignment % 32 == 0);
238
Chia-I Wu72292b72014-09-09 10:48:33 +0800239 writer->used = offset + size;
240
Chia-I Wu465fe212015-02-11 11:27:06 -0700241 if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG))
Chia-I Wu00b51a82014-09-09 12:07:37 +0800242 cmd_writer_record(cmd, which, item, offset, size);
243
Chia-I Wu72292b72014-09-09 10:48:33 +0800244 return offset;
Chia-I Wue24c3292014-08-21 14:05:23 +0800245}
246
247/**
Chia-I Wu5da476a2014-12-10 08:50:28 +0800248 * Get the pointer to a reserved region for updating. The pointer is only
249 * valid until the next reserve call.
250 */
251static inline void cmd_state_update(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600252 uint32_t offset, uint32_t len,
Chia-I Wu5da476a2014-12-10 08:50:28 +0800253 uint32_t **dw)
254{
255 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE;
256 struct intel_cmd_writer *writer = &cmd->writers[which];
257
258 assert(offset + (len << 2) <= writer->used);
259
260 *dw = (uint32_t *) ((char *) writer->ptr + offset);
261}
262
263/**
264 * Reserve a region from the state buffer. Both the offset, in bytes, and the
265 * pointer to the reserved region are returned. The pointer is only valid
266 * until the next reserve call.
267 *
268 * Note that \p alignment is in bytes and \p len is in DWords.
269 */
270static inline uint32_t cmd_state_pointer(struct intel_cmd *cmd,
271 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600272 size_t alignment, uint32_t len,
Chia-I Wu5da476a2014-12-10 08:50:28 +0800273 uint32_t **dw)
274{
275 const uint32_t offset = cmd_state_reserve(cmd, item, alignment, len);
276
277 cmd_state_update(cmd, offset, len, dw);
278
279 return offset;
280}
281
282/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800283 * Write a dynamic state to the state buffer.
Chia-I Wucdff0592014-08-22 09:27:36 +0800284 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800285static inline uint32_t cmd_state_write(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800286 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600287 size_t alignment, uint32_t len,
Chia-I Wu72292b72014-09-09 10:48:33 +0800288 const uint32_t *dw)
Chia-I Wucdff0592014-08-22 09:27:36 +0800289{
Chia-I Wu72292b72014-09-09 10:48:33 +0800290 uint32_t offset, *dst;
291
Chia-I Wu00b51a82014-09-09 12:07:37 +0800292 offset = cmd_state_pointer(cmd, item, alignment, len, &dst);
Chia-I Wu72292b72014-09-09 10:48:33 +0800293 memcpy(dst, dw, len << 2);
294
295 return offset;
Chia-I Wucdff0592014-08-22 09:27:36 +0800296}
297
298/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800299 * Write a surface state to the surface buffer. The offset, in bytes, of the
300 * state is returned.
301 *
302 * Note that \p alignment is in bytes and \p len is in DWords.
Chia-I Wue24c3292014-08-21 14:05:23 +0800303 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800304static inline uint32_t cmd_surface_write(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800305 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600306 size_t alignment, uint32_t len,
Chia-I Wu72292b72014-09-09 10:48:33 +0800307 const uint32_t *dw)
Chia-I Wue24c3292014-08-21 14:05:23 +0800308{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800309 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wuf98dd882015-02-10 04:17:47 +0800310 const size_t size = len << 2;
Chia-I Wu15cccf72015-02-10 04:07:40 +0800311 const uint32_t offset = cmd_writer_reserve(cmd, which, alignment, size);
312 struct intel_cmd_writer *writer = &cmd->writers[which];
313 uint32_t *dst;
314
Chia-I Wu00b51a82014-09-09 12:07:37 +0800315 assert(item == INTEL_CMD_ITEM_SURFACE ||
316 item == INTEL_CMD_ITEM_BINDING_TABLE);
317
Chia-I Wu15cccf72015-02-10 04:07:40 +0800318 /* all states are at least aligned to 32-bytes */
319 assert(alignment % 32 == 0);
320
321 writer->used = offset + size;
322
323 if (intel_debug & INTEL_DEBUG_BATCH)
324 cmd_writer_record(cmd, which, item, offset, size);
325
326 dst = (uint32_t *) ((char *) writer->ptr + offset);
327 memcpy(dst, dw, size);
328
329 return offset;
Chia-I Wue24c3292014-08-21 14:05:23 +0800330}
331
332/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800333 * Add a relocation entry for a DWord of a surface state.
Chia-I Wucdff0592014-08-22 09:27:36 +0800334 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800335static inline void cmd_surface_reloc(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600336 uint32_t offset, uint32_t dw_index,
Chia-I Wu72292b72014-09-09 10:48:33 +0800337 struct intel_bo *bo,
338 uint32_t bo_offset, uint32_t reloc_flags)
Chia-I Wucdff0592014-08-22 09:27:36 +0800339{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800340 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wucdff0592014-08-22 09:27:36 +0800341
Chia-I Wu72292b72014-09-09 10:48:33 +0800342 cmd_writer_reloc(cmd, which, offset + (dw_index << 2),
Chia-I Wud7d1e482014-10-18 13:25:10 +0800343 (intptr_t) bo, bo_offset, reloc_flags);
344}
345
346static inline void cmd_surface_reloc_writer(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600347 uint32_t offset, uint32_t dw_index,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800348 enum intel_cmd_writer_type writer,
349 uint32_t writer_offset)
350{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800351 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wud7d1e482014-10-18 13:25:10 +0800352
353 cmd_writer_reloc(cmd, which, offset + (dw_index << 2),
354 (intptr_t) writer, writer_offset,
355 INTEL_CMD_RELOC_TARGET_IS_WRITER);
Chia-I Wucdff0592014-08-22 09:27:36 +0800356}
357
358/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800359 * Write a kernel to the instruction buffer. The offset, in bytes, of the
360 * kernel is returned.
Chia-I Wue24c3292014-08-21 14:05:23 +0800361 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800362static inline uint32_t cmd_instruction_write(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600363 size_t size,
Chia-I Wu72292b72014-09-09 10:48:33 +0800364 const void *kernel)
Chia-I Wue24c3292014-08-21 14:05:23 +0800365{
Chia-I Wu72292b72014-09-09 10:48:33 +0800366 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_INSTRUCTION;
367 /*
368 * From the Sandy Bridge PRM, volume 4 part 2, page 112:
369 *
370 * "Due to prefetch of the instruction stream, the EUs may attempt to
371 * access up to 8 instructions (128 bytes) beyond the end of the
372 * kernel program - possibly into the next memory page. Although
373 * these instructions will not be executed, software must account for
374 * the prefetch in order to avoid invalid page access faults."
375 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600376 const size_t reserved_size = size + 128;
Chia-I Wu72292b72014-09-09 10:48:33 +0800377 /* kernels are aligned to 64 bytes */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600378 const size_t alignment = 64;
379 const size_t offset = cmd_writer_reserve(cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800380 which, alignment, reserved_size);
381 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wue24c3292014-08-21 14:05:23 +0800382
Chia-I Wu72292b72014-09-09 10:48:33 +0800383 memcpy((char *) writer->ptr + offset, kernel, size);
Chia-I Wu5e25c272014-08-21 20:19:12 +0800384
Chia-I Wu72292b72014-09-09 10:48:33 +0800385 writer->used = offset + size;
386
Chia-I Wu465fe212015-02-11 11:27:06 -0700387 if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG))
Chia-I Wu00b51a82014-09-09 12:07:37 +0800388 cmd_writer_record(cmd, which, INTEL_CMD_ITEM_KERNEL, offset, size);
389
Chia-I Wu72292b72014-09-09 10:48:33 +0800390 return offset;
391}
392
393/**
394 * Reserve a region from the batch buffer. Both the offset, in DWords, and
Chia-I Wu5da476a2014-12-10 08:50:28 +0800395 * the pointer to the reserved region are returned. The pointer is only valid
396 * until the next reserve call.
Chia-I Wu72292b72014-09-09 10:48:33 +0800397 *
398 * Note that \p len is in DWords.
399 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600400static inline uint32_t cmd_batch_pointer(struct intel_cmd *cmd,
401 uint32_t len, uint32_t **dw)
Chia-I Wu72292b72014-09-09 10:48:33 +0800402{
403 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
404 /*
405 * We know the batch bo is always aligned. Using 1 here should allow the
406 * compiler to optimize away aligning.
407 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600408 const size_t alignment = 1;
409 const size_t size = len << 2;
410 const size_t offset = cmd_writer_reserve(cmd, which, alignment, size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800411 struct intel_cmd_writer *writer = &cmd->writers[which];
412
413 assert(offset % 4 == 0);
414 *dw = (uint32_t *) ((char *) writer->ptr + offset);
415
416 writer->used = offset + size;
417
418 return offset >> 2;
419}
420
421/**
422 * Write a command to the batch buffer.
423 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600424static inline uint32_t cmd_batch_write(struct intel_cmd *cmd,
425 uint32_t len, const uint32_t *dw)
Chia-I Wu72292b72014-09-09 10:48:33 +0800426{
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600427 uint32_t pos;
Chia-I Wu72292b72014-09-09 10:48:33 +0800428 uint32_t *dst;
429
430 pos = cmd_batch_pointer(cmd, len, &dst);
431 memcpy(dst, dw, len << 2);
432
433 return pos;
434}
435
436/**
437 * Add a relocation entry for a DWord of a command.
438 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600439static inline void cmd_batch_reloc(struct intel_cmd *cmd, uint32_t pos,
Chia-I Wu72292b72014-09-09 10:48:33 +0800440 struct intel_bo *bo,
441 uint32_t bo_offset, uint32_t reloc_flags)
442{
443 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
444
Chia-I Wud7d1e482014-10-18 13:25:10 +0800445 cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) bo, bo_offset, reloc_flags);
446}
447
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600448static inline void cmd_batch_reloc_writer(struct intel_cmd *cmd, uint32_t pos,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800449 enum intel_cmd_writer_type writer,
450 uint32_t writer_offset)
451{
452 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
453
454 cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) writer, writer_offset,
455 INTEL_CMD_RELOC_TARGET_IS_WRITER);
Chia-I Wue24c3292014-08-21 14:05:23 +0800456}
457
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800458void cmd_batch_state_base_address(struct intel_cmd *cmd);
Chia-I Wu7c853562015-02-27 14:35:08 -0700459void cmd_batch_push_const_alloc(struct intel_cmd *cmd);
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800460
Chia-I Wue24c3292014-08-21 14:05:23 +0800461/**
Chia-I Wu48c283d2014-08-25 23:13:46 +0800462 * Begin the batch buffer.
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800463 */
464static inline void cmd_batch_begin(struct intel_cmd *cmd)
465{
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800466 cmd_batch_state_base_address(cmd);
Chia-I Wu7c853562015-02-27 14:35:08 -0700467 cmd_batch_push_const_alloc(cmd);
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800468}
469
470/**
Chia-I Wue24c3292014-08-21 14:05:23 +0800471 * End the batch buffer.
472 */
473static inline void cmd_batch_end(struct intel_cmd *cmd)
474{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800475 struct intel_cmd_writer *writer = &cmd->writers[INTEL_CMD_WRITER_BATCH];
Chia-I Wu72292b72014-09-09 10:48:33 +0800476 uint32_t *dw;
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800477
Chia-I Wu72292b72014-09-09 10:48:33 +0800478 if (writer->used & 0x7) {
479 cmd_batch_pointer(cmd, 1, &dw);
480 dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
Chia-I Wue24c3292014-08-21 14:05:23 +0800481 } else {
Chia-I Wu72292b72014-09-09 10:48:33 +0800482 cmd_batch_pointer(cmd, 2, &dw);
483 dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
484 dw[1] = GEN6_MI_CMD(MI_NOOP);
Chia-I Wue24c3292014-08-21 14:05:23 +0800485 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800486}
487
Chia-I Wub5af7c52015-02-18 14:51:59 -0700488static inline void cmd_begin_render_pass(struct intel_cmd *cmd,
Courtney Goeltzenleuchtere3b0f3a2015-04-03 15:25:24 -0600489 const struct intel_render_pass *rp,
Chia-I Wu513ae5b2015-07-01 19:04:59 +0800490 const struct intel_fb *fb,
Cody Northrop16898b02015-08-11 11:35:58 -0600491 const uint32_t sp,
Chia-I Wu513ae5b2015-07-01 19:04:59 +0800492 VkRenderPassContents contents)
Chia-I Wub5af7c52015-02-18 14:51:59 -0700493{
Cody Northrop16898b02015-08-11 11:35:58 -0600494 assert(sp < rp->subpass_count);
495
Chia-I Wubbc7d912015-02-27 14:59:50 -0700496 cmd->bind.render_pass_changed = true;
Chia-I Wubdeed152015-07-09 12:16:29 +0800497 cmd->bind.render_pass = rp;
Cody Northrop16898b02015-08-11 11:35:58 -0600498 cmd->bind.render_pass_subpass = &rp->subpasses[sp];
Courtney Goeltzenleuchtere3b0f3a2015-04-03 15:25:24 -0600499 cmd->bind.fb = fb;
Chia-I Wu513ae5b2015-07-01 19:04:59 +0800500 cmd->bind.render_pass_contents = contents;
Chia-I Wub5af7c52015-02-18 14:51:59 -0700501}
502
Chia-I Wu88eaa3b2015-06-26 15:34:39 +0800503static inline void cmd_end_render_pass(struct intel_cmd *cmd)
Chia-I Wub5af7c52015-02-18 14:51:59 -0700504{
505 //note what to do if rp != bound rp
506 cmd->bind.render_pass = 0;
Courtney Goeltzenleuchtere3b0f3a2015-04-03 15:25:24 -0600507 cmd->bind.fb = 0;
Chia-I Wub5af7c52015-02-18 14:51:59 -0700508}
509
Chia-I Wu525c6602014-08-27 10:22:34 +0800510void cmd_batch_flush(struct intel_cmd *cmd, uint32_t pipe_control_dw0);
Chia-I Wu3fb47ce2014-10-28 11:19:36 +0800511void cmd_batch_flush_all(struct intel_cmd *cmd);
Chia-I Wu525c6602014-08-27 10:22:34 +0800512
Chia-I Wu759fa2e2014-08-30 18:44:47 +0800513void cmd_batch_depth_count(struct intel_cmd *cmd,
514 struct intel_bo *bo,
Tony Barbour8205d902015-04-16 15:59:00 -0600515 VkDeviceSize offset);
Chia-I Wu759fa2e2014-08-30 18:44:47 +0800516
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800517void cmd_batch_timestamp(struct intel_cmd *cmd,
518 struct intel_bo *bo,
Tony Barbour8205d902015-04-16 15:59:00 -0600519 VkDeviceSize offset);
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800520
521void cmd_batch_immediate(struct intel_cmd *cmd,
Mike Stroyan55658c22014-12-04 11:08:39 +0000522 uint32_t pipe_control_flags,
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800523 struct intel_bo *bo,
Tony Barbour8205d902015-04-16 15:59:00 -0600524 VkDeviceSize offset,
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800525 uint64_t val);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800526
Chia-I Wuc14d1562014-10-17 09:49:22 +0800527void cmd_draw_meta(struct intel_cmd *cmd, const struct intel_cmd_meta *meta);
528
Chia-I Wu73520ac2015-02-19 11:17:45 -0700529void cmd_meta_ds_op(struct intel_cmd *cmd,
530 enum intel_cmd_meta_ds_op op,
531 struct intel_img *img,
Courtney Goeltzenleuchter382489d2015-04-10 08:34:15 -0600532 const VkImageSubresourceRange *range);
Chia-I Wu73520ac2015-02-19 11:17:45 -0700533
Chris Forbesfff9bf42015-06-15 15:26:19 +1200534void cmd_meta_clear_color_image(
535 VkCmdBuffer cmdBuffer,
Tony Barbourde4124d2015-07-03 10:33:54 -0600536 struct intel_img *img,
Chris Forbesfff9bf42015-06-15 15:26:19 +1200537 VkImageLayout imageLayout,
Chris Forbese3105972015-06-24 14:34:53 +1200538 const VkClearColorValue *pClearColor,
Chris Forbesfff9bf42015-06-15 15:26:19 +1200539 uint32_t rangeCount,
540 const VkImageSubresourceRange *pRanges);
541
Chris Forbes4cf9d102015-06-22 18:46:05 +1200542void cmd_meta_clear_depth_stencil_image(
543 VkCmdBuffer cmdBuffer,
Tony Barbourde4124d2015-07-03 10:33:54 -0600544 struct intel_img* img,
Chris Forbes4cf9d102015-06-22 18:46:05 +1200545 VkImageLayout imageLayout,
546 float depth,
547 uint32_t stencil,
548 uint32_t rangeCount,
549 const VkImageSubresourceRange* pRanges);
550
Chia-I Wu00a23b22014-08-20 15:28:08 +0800551#endif /* CMD_PRIV_H */