blob: d5d3250a7641cb765512656567329842510d3f95 [file] [log] [blame]
Chia-I Wu82f50aa2014-08-05 10:43:03 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu82f50aa2014-08-05 10:43:03 +080026 */
27
Chia-I Wude2bb862014-08-19 14:32:47 +080028#include "dispatch.h"
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -060029#include "dev.h"
Chia-I Wu9e61c0d2014-09-15 15:12:06 +080030#include "gpu.h"
31#include "mem.h"
Chia-I Wu82f50aa2014-08-05 10:43:03 +080032#include "obj.h"
33
34/**
35 * Return true if an (not so) arbitrary pointer casted to intel_base points to
36 * a valid intel_base. This assumes at least the first sizeof(void*) bytes of
37 * the address are accessible, and they does not happen to be our magic
38 * values.
39 */
40bool intel_base_is_valid(const struct intel_base *base)
41{
Chia-I Wu6a42c2a2014-08-19 14:36:47 +080042 if (base->dispatch != intel_dispatch_get(true) &&
43 base->dispatch != intel_dispatch_get(false))
Chia-I Wu82f50aa2014-08-05 10:43:03 +080044 return false;
45
46 return !intel_gpu_is_valid((const struct intel_gpu *) base);
47}
48
Chia-I Wu26f0bd02014-08-07 10:38:40 +080049XGL_RESULT intel_base_get_info(struct intel_base *base, int type,
50 XGL_SIZE *size, XGL_VOID *data)
51{
52 XGL_RESULT ret = XGL_SUCCESS;
53 XGL_SIZE s;
54
55 switch (type) {
56 case XGL_INFO_TYPE_MEMORY_REQUIREMENTS:
57 s = sizeof(XGL_MEMORY_REQUIREMENTS);
58 memset(data, 0, s);
59 *size = s;
60 break;
61 default:
62 ret = XGL_ERROR_INVALID_VALUE;
63 break;
64 }
65
66 return ret;
67}
68
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080069static bool base_dbg_copy_create_info(struct intel_base_dbg *dbg,
70 const void *create_info)
71{
72 const union {
73 const void *ptr;
74 const struct {
75 XGL_STRUCTURE_TYPE struct_type;
76 XGL_VOID *next;
77 } *header;
78 } info = { .ptr = create_info };
79 XGL_SIZE shallow_copy = 0;
80
81 if (!create_info)
82 return true;
83
Chia-I Wub1076d72014-08-18 16:10:20 +080084 switch (dbg->type) {
85 case XGL_DBG_OBJECT_DEVICE:
86 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080087 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080088 case XGL_DBG_OBJECT_GPU_MEMORY:
89 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_MEMORY_ALLOC_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080090 shallow_copy = sizeof(XGL_MEMORY_ALLOC_INFO);
91 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080092 case XGL_DBG_OBJECT_EVENT:
93 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_EVENT_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080094 shallow_copy = sizeof(XGL_EVENT_CREATE_INFO);
95 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080096 case XGL_DBG_OBJECT_FENCE:
97 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_FENCE_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080098 shallow_copy = sizeof(XGL_FENCE_CREATE_INFO);
99 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800100 case XGL_DBG_OBJECT_QUERY_POOL:
101 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO);
Courtney Goeltzenleuchter850d12c2014-08-07 18:13:10 -0600102 shallow_copy = sizeof(XGL_QUERY_POOL_CREATE_INFO);
103 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800104 case XGL_DBG_OBJECT_IMAGE:
105 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
Chia-I Wufeb441f2014-08-08 21:27:38 +0800106 shallow_copy = sizeof(XGL_IMAGE_CREATE_INFO);
107 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800108 case XGL_DBG_OBJECT_IMAGE_VIEW:
109 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800110 shallow_copy = sizeof(XGL_IMAGE_VIEW_CREATE_INFO);
111 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800112 case XGL_DBG_OBJECT_COLOR_TARGET_VIEW:
113 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800114 shallow_copy = sizeof(XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO);
115 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800116 case XGL_DBG_OBJECT_DEPTH_STENCIL_VIEW:
117 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800118 shallow_copy = sizeof(XGL_DEPTH_STENCIL_VIEW_CREATE_INFO);
119 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800120 case XGL_DBG_OBJECT_SAMPLER:
121 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
Chia-I Wu28b89962014-08-18 14:40:49 +0800122 shallow_copy = sizeof(XGL_SAMPLER_CREATE_INFO);
123 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800124 case XGL_DBG_OBJECT_DESCRIPTOR_SET:
125 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DESCRIPTOR_SET_CREATE_INFO);
Chia-I Wub8d04c82014-08-18 15:51:10 +0800126 shallow_copy = sizeof(XGL_DESCRIPTOR_SET_CREATE_INFO);
127 break;
Chia-I Wua5714e82014-08-11 15:33:42 +0800128 case XGL_DBG_OBJECT_VIEWPORT_STATE:
129 /* no struct header! */
130 shallow_copy = sizeof(XGL_VIEWPORT_STATE_CREATE_INFO);
131 break;
132 case XGL_DBG_OBJECT_RASTER_STATE:
133 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_RASTER_STATE_CREATE_INFO);
134 shallow_copy = sizeof(XGL_RASTER_STATE_CREATE_INFO);
135 break;
136 case XGL_DBG_OBJECT_MSAA_STATE:
137 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_MSAA_STATE_CREATE_INFO);
138 shallow_copy = sizeof(XGL_MSAA_STATE_CREATE_INFO);
139 break;
140 case XGL_DBG_OBJECT_COLOR_BLEND_STATE:
141 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_COLOR_BLEND_STATE_CREATE_INFO);
142 shallow_copy = sizeof(XGL_COLOR_BLEND_STATE_CREATE_INFO);
143 break;
144 case XGL_DBG_OBJECT_DEPTH_STENCIL_STATE:
145 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEPTH_STENCIL_STATE_CREATE_INFO);
146 shallow_copy = sizeof(XGL_DEPTH_STENCIL_STATE_CREATE_INFO);
147 break;
Chia-I Wu730e5362014-08-19 12:15:09 +0800148 case XGL_DBG_OBJECT_CMD_BUFFER:
149 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_CMD_BUFFER_CREATE_INFO);
150 shallow_copy = sizeof(XGL_CMD_BUFFER_CREATE_INFO);
151 break;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600152 case XGL_DBG_OBJECT_GRAPHICS_PIPELINE:
153 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
154 break;
Courtney Goeltzenleuchter52ec3362014-08-19 11:52:02 -0600155 case XGL_DBG_OBJECT_SHADER:
Courtney Goeltzenleuchteref5b1162014-10-10 16:29:46 -0600156 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_SHADER_CREATE_INFO);
Courtney Goeltzenleuchter52ec3362014-08-19 11:52:02 -0600157 shallow_copy = sizeof(XGL_SHADER_CREATE_INFO);
158 break;
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800159 default:
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600160 // log debug message regarding invalid struct_type?
161 intel_dev_log(dbg->dev, XGL_DBG_MSG_ERROR,
162 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
163 "Invalid Create Info type: 0x%x", info.header->struct_type);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800164 return false;
165 break;
166 }
167
168 if (shallow_copy) {
Chia-I Wu73523682014-10-23 01:38:26 +0800169 /* XGL_VIEWPORT_STATE_CREATE_INFO has no header */
170 if (dbg->type != XGL_DBG_OBJECT_VIEWPORT_STATE)
171 assert(!info.header->next);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800172
173 dbg->create_info = icd_alloc(shallow_copy, 0, XGL_SYSTEM_ALLOC_DEBUG);
174 if (!dbg->create_info)
175 return false;
176
177 memcpy(dbg->create_info, create_info, shallow_copy);
Chia-I Wue2934f92014-08-16 13:17:22 +0800178 dbg->create_info_size = shallow_copy;
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800179 } else if (info.header->struct_type ==
180 XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO) {
181 const XGL_DEVICE_CREATE_INFO *src = info.ptr;
182 XGL_DEVICE_CREATE_INFO *dst;
183 uint8_t *d;
184 XGL_SIZE size;
185 XGL_UINT i;
186
187 size = sizeof(*src);
Chia-I Wue2934f92014-08-16 13:17:22 +0800188 dbg->create_info_size = size;
189
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800190 size += sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
191 size += sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
192 for (i = 0; i < src->extensionCount; i++) {
193 size += 1 +
194 strlen((const char *) src->ppEnabledExtensionNames[i]);
195 }
196
Chia-I Wu98dcfab2014-08-07 12:07:52 +0800197 dst = icd_alloc(size, 0, XGL_SYSTEM_ALLOC_DEBUG);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800198 if (!dst)
199 return false;
200
201 memcpy(dst, src, sizeof(*src));
202
203 d = (uint8_t *) dst;
204 d += sizeof(*src);
205
206 size = sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
207 memcpy(d, src->pRequestedQueues, size);
208 dst->pRequestedQueues = (const XGL_DEVICE_QUEUE_CREATE_INFO *) d;
209 d += size;
210
211 size = sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
212 dst->ppEnabledExtensionNames = (const XGL_CHAR * const *) d;
213
214 for (i = 0; i < src->extensionCount; i++) {
215 const XGL_SIZE len =
216 strlen((const char *) src->ppEnabledExtensionNames[i]);
217
218 memcpy(d + size, src->ppEnabledExtensionNames[i], len + 1);
219 ((const XGL_CHAR **) d)[i] = (const XGL_CHAR *) (d + size);
220
221 size += len + 1;
222 }
Courtney Goeltzenleuchter191b06c2014-10-17 16:21:35 -0600223 dbg->create_info = dst;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600224 } else if (info.header->struct_type == XGL_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO) {
225 // TODO: What do we want to copy here?
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800226 }
227
228 return true;
229}
230
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800231/**
Chia-I Wubbf2c932014-08-07 12:20:08 +0800232 * Create an intel_base_dbg. When dbg_size is non-zero, a buffer of that
Chia-I Wu660caf82014-08-07 10:54:26 +0800233 * size is allocated and zeroed.
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800234 */
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600235struct intel_base_dbg *intel_base_dbg_create(struct intel_dev *dev,
236 XGL_DBG_OBJECT_TYPE type,
Chia-I Wu660caf82014-08-07 10:54:26 +0800237 const void *create_info,
Chia-I Wubbf2c932014-08-07 12:20:08 +0800238 XGL_SIZE dbg_size)
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800239{
Chia-I Wu660caf82014-08-07 10:54:26 +0800240 struct intel_base_dbg *dbg;
241
Chia-I Wubbf2c932014-08-07 12:20:08 +0800242 if (!dbg_size)
243 dbg_size = sizeof(*dbg);
Chia-I Wu660caf82014-08-07 10:54:26 +0800244
Chia-I Wubbf2c932014-08-07 12:20:08 +0800245 assert(dbg_size >= sizeof(*dbg));
Chia-I Wu660caf82014-08-07 10:54:26 +0800246
Chia-I Wubbf2c932014-08-07 12:20:08 +0800247 dbg = icd_alloc(dbg_size, 0, XGL_SYSTEM_ALLOC_DEBUG);
Chia-I Wu660caf82014-08-07 10:54:26 +0800248 if (!dbg)
249 return NULL;
250
Chia-I Wubbf2c932014-08-07 12:20:08 +0800251 memset(dbg, 0, dbg_size);
Chia-I Wu660caf82014-08-07 10:54:26 +0800252
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800253 dbg->alloc_id = icd_get_allocator_id();
254 dbg->type = type;
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600255 dbg->dev = dev;
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800256
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800257 if (!base_dbg_copy_create_info(dbg, create_info)) {
258 icd_free(dbg);
259 return NULL;
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800260 }
261
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800262 return dbg;
263}
264
265void intel_base_dbg_destroy(struct intel_base_dbg *dbg)
266{
Chia-I Wu660caf82014-08-07 10:54:26 +0800267 if (dbg->tag)
268 icd_free(dbg->tag);
269
270 if (dbg->create_info)
271 icd_free(dbg->create_info);
272
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800273 icd_free(dbg);
274}
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800275
Chia-I Wubbf2c932014-08-07 12:20:08 +0800276/**
277 * Create an intel_base. obj_size and dbg_size specify the real sizes of the
278 * object and the debug metadata. Memories are zeroed.
279 */
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600280struct intel_base *intel_base_create(struct intel_dev *dev,
281 XGL_SIZE obj_size, bool debug,
Chia-I Wubbf2c932014-08-07 12:20:08 +0800282 XGL_DBG_OBJECT_TYPE type,
283 const void *create_info,
284 XGL_SIZE dbg_size)
285{
286 struct intel_base *base;
287
288 if (!obj_size)
289 obj_size = sizeof(*base);
290
291 assert(obj_size >= sizeof(*base));
292
293 base = icd_alloc(obj_size, 0, XGL_SYSTEM_ALLOC_API_OBJECT);
294 if (!base)
295 return NULL;
296
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600297 if (dev == NULL) {
298 /*
299 * dev is NULL when we are creating the base device object
300 * Set dev now so that debug setup happens correctly
301 */
302 dev = (struct intel_dev *) base;
303 }
304
Chia-I Wubbf2c932014-08-07 12:20:08 +0800305 memset(base, 0, obj_size);
306
Chia-I Wu6a42c2a2014-08-19 14:36:47 +0800307 base->dispatch = intel_dispatch_get(debug);
Chia-I Wubbf2c932014-08-07 12:20:08 +0800308 if (debug) {
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600309 base->dbg = intel_base_dbg_create(dev, type, create_info, dbg_size);
Chia-I Wubbf2c932014-08-07 12:20:08 +0800310 if (!base->dbg) {
311 icd_free(base);
312 return NULL;
313 }
314 }
Chia-I Wu6a42c2a2014-08-19 14:36:47 +0800315
Chia-I Wubbf2c932014-08-07 12:20:08 +0800316 base->get_info = intel_base_get_info;
317
318 return base;
319}
320
321void intel_base_destroy(struct intel_base *base)
322{
323 if (base->dbg)
324 intel_base_dbg_destroy(base->dbg);
325 icd_free(base);
326}
327
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800328XGL_RESULT XGLAPI intelDestroyObject(
329 XGL_OBJECT object)
330{
331 struct intel_obj *obj = intel_obj(object);
332
333 obj->destroy(obj);
334
335 return XGL_SUCCESS;
336}
337
338XGL_RESULT XGLAPI intelGetObjectInfo(
339 XGL_BASE_OBJECT object,
340 XGL_OBJECT_INFO_TYPE infoType,
341 XGL_SIZE* pDataSize,
342 XGL_VOID* pData)
343{
344 struct intel_base *base = intel_base(object);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800345
Chia-I Wu26f0bd02014-08-07 10:38:40 +0800346 return base->get_info(base, infoType, pDataSize, pData);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800347}
348
349XGL_RESULT XGLAPI intelBindObjectMemory(
350 XGL_OBJECT object,
Chia-I Wu9e61c0d2014-09-15 15:12:06 +0800351 XGL_GPU_MEMORY mem_,
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800352 XGL_GPU_SIZE offset)
353{
354 struct intel_obj *obj = intel_obj(object);
Chia-I Wu9e61c0d2014-09-15 15:12:06 +0800355 struct intel_mem *mem = intel_mem(mem_);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800356
Chia-I Wu9e61c0d2014-09-15 15:12:06 +0800357 intel_obj_bind_mem(obj, mem, offset);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800358
359 return XGL_SUCCESS;
360}
Chia-I Wu7ec9f342014-08-19 10:47:53 +0800361
362XGL_RESULT XGLAPI intelDbgSetObjectTag(
363 XGL_BASE_OBJECT object,
364 XGL_SIZE tagSize,
365 const XGL_VOID* pTag)
366{
367 struct intel_base *base = intel_base(object);
368 struct intel_base_dbg *dbg = base->dbg;
369 void *tag;
370
371 if (!dbg)
372 return XGL_SUCCESS;
373
374 tag = icd_alloc(tagSize, 0, XGL_SYSTEM_ALLOC_DEBUG);
375 if (!tag)
376 return XGL_ERROR_OUT_OF_MEMORY;
377
378 memcpy(tag, pTag, tagSize);
379
380 if (dbg->tag)
381 icd_free(dbg->tag);
382
383 dbg->tag = tag;
384 dbg->tag_size = tagSize;
385
386 return XGL_SUCCESS;
387}