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Chia-I Wue54854a2014-08-05 10:23:50 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wue54854a2014-08-05 10:23:50 +080026 */
27
28#ifndef DEV_H
29#define DEV_H
30
Chia-I Wue09b5362014-08-07 09:25:14 +080031#include "intel.h"
Chia-I Wue54854a2014-08-05 10:23:50 +080032#include "gpu.h"
Chia-I Wua2161db2014-08-15 16:34:34 +080033#include "obj.h"
Chia-I Wue54854a2014-08-05 10:23:50 +080034
Chia-I Wue54854a2014-08-05 10:23:50 +080035struct intel_queue;
36struct intel_winsys;
37
38struct intel_dev_dbg_msg_filter {
39 XGL_INT msg_code;
40 XGL_DBG_MSG_FILTER filter;
41 bool triggered;
42
43 struct intel_dev_dbg_msg_filter *next;
44};
45
46struct intel_dev_dbg {
47 struct intel_base_dbg base;
48
Chia-I Wu069f30f2014-08-21 13:45:20 +080049 XGL_VALIDATION_LEVEL validation_level;
50 bool disable_pipeline_loads;
51 bool force_object_memory_reqs;
52 bool force_large_image_alignment;
53
Chia-I Wue54854a2014-08-05 10:23:50 +080054 struct intel_dev_dbg_msg_filter *filters;
55};
56
57struct intel_dev {
58 struct intel_base base;
59
60 struct intel_gpu *gpu;
61 struct intel_winsys *winsys;
Chia-I Wu0b784442014-08-25 22:54:16 +080062 struct intel_bo *cmd_scratch_bo;
63
Chia-I Wue54854a2014-08-05 10:23:50 +080064 struct intel_queue *queues[INTEL_GPU_ENGINE_COUNT];
65};
66
Chia-I Wue54854a2014-08-05 10:23:50 +080067static inline struct intel_dev *intel_dev(XGL_DEVICE dev)
68{
69 return (struct intel_dev *) dev;
70}
71
72static inline struct intel_dev_dbg *intel_dev_dbg(struct intel_dev *dev)
73{
74 return (struct intel_dev_dbg *) dev->base.dbg;
75}
76
Chia-I Wue54854a2014-08-05 10:23:50 +080077XGL_RESULT intel_dev_create(struct intel_gpu *gpu,
78 const XGL_DEVICE_CREATE_INFO *info,
79 struct intel_dev **dev_ret);
80void intel_dev_destroy(struct intel_dev *dev);
81
82void intel_dev_get_heap_props(const struct intel_dev *dev,
83 XGL_MEMORY_HEAP_PROPERTIES *props);
84
85XGL_RESULT intel_dev_add_msg_filter(struct intel_dev *dev,
86 XGL_INT msg_code,
87 XGL_DBG_MSG_FILTER filter);
88
89void intel_dev_remove_msg_filter(struct intel_dev *dev,
90 XGL_INT msg_code);
91
Chia-I Wu82d3d8b2014-08-09 13:07:44 +080092void intel_dev_log(struct intel_dev *dev,
93 XGL_DBG_MSG_TYPE msg_type,
94 XGL_VALIDATION_LEVEL validation_level,
Chia-I Wuaabb3602014-08-19 14:18:23 +080095 struct intel_base *src_object,
Chia-I Wu82d3d8b2014-08-09 13:07:44 +080096 XGL_SIZE location,
97 XGL_INT msg_code,
98 const char *format, ...);
99
Chia-I Wua207aba2014-08-05 15:13:37 +0800100XGL_RESULT XGLAPI intelCreateDevice(
101 XGL_PHYSICAL_GPU gpu,
102 const XGL_DEVICE_CREATE_INFO* pCreateInfo,
103 XGL_DEVICE* pDevice);
104
105XGL_RESULT XGLAPI intelDestroyDevice(
106 XGL_DEVICE device);
107
108XGL_RESULT XGLAPI intelGetMemoryHeapCount(
109 XGL_DEVICE device,
110 XGL_UINT* pCount);
111
112XGL_RESULT XGLAPI intelGetMemoryHeapInfo(
113 XGL_DEVICE device,
114 XGL_UINT heapId,
115 XGL_MEMORY_HEAP_INFO_TYPE infoType,
116 XGL_SIZE* pDataSize,
117 XGL_VOID* pData);
118
Chia-I Wu49dbee82014-08-06 12:48:47 +0800119XGL_RESULT XGLAPI intelGetDeviceQueue(
120 XGL_DEVICE device,
121 XGL_QUEUE_TYPE queueType,
122 XGL_UINT queueIndex,
123 XGL_QUEUE* pQueue);
124
Chia-I Wu49dbee82014-08-06 12:48:47 +0800125XGL_RESULT XGLAPI intelDeviceWaitIdle(
126 XGL_DEVICE device);
127
Chia-I Wu7ec9f342014-08-19 10:47:53 +0800128XGL_RESULT XGLAPI intelDbgSetValidationLevel(
129 XGL_DEVICE device,
130 XGL_VALIDATION_LEVEL validationLevel);
131
132XGL_RESULT XGLAPI intelDbgSetMessageFilter(
133 XGL_DEVICE device,
134 XGL_INT msgCode,
135 XGL_DBG_MSG_FILTER filter);
136
137XGL_RESULT XGLAPI intelDbgSetDeviceOption(
138 XGL_DEVICE device,
139 XGL_DBG_DEVICE_OPTION dbgOption,
140 XGL_SIZE dataSize,
141 const XGL_VOID* pData);
142
Chia-I Wue54854a2014-08-05 10:23:50 +0800143#endif /* DEV_H */