Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 6274e5222d22e925c579721aed51ad334589210b / . / llvm / lib / Target / AArch64 / AArch64LoadStoreOptimizer.cpp
blob: 517084566f89d788281d15ca4833a0d158d3b25a [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1//=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a pass that performs load / store related peephole
11// optimizations. This pass should be run after register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AArch64InstrInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]16#include "AArch64Subtarget.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]17#include "MCTargetDesc/AArch64AddressingModes.h"
18#include "llvm/ADT/BitVector.h"
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]19#include "llvm/ADT/SmallVector.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]20#include "llvm/ADT/Statistic.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstr.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/raw_ostream.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetMachine.h"
31#include "llvm/Target/TargetRegisterInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-ldst-opt"
35
36/// AArch64AllocLoadStoreOpt - Post-register allocation pass to combine
37/// load / store instructions to form ldp / stp instructions.
38
39STATISTIC(NumPairCreated, "Number of load/store pair instructions generated");
40STATISTIC(NumPostFolded, "Number of post-index updates folded");
41STATISTIC(NumPreFolded, "Number of pre-index updates folded");
42STATISTIC(NumUnscaledPairCreated,
43 "Number of load/store from unscaled generated");
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]44STATISTIC(NumNarrowLoadsPromoted, "Number of narrow loads promoted");
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]45STATISTIC(NumZeroStoresPromoted, "Number of narrow zero stores promoted");
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]46STATISTIC(NumLoadsFromStoresPromoted, "Number of loads from stores promoted");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]48// The LdStLimit limits how far we search for load/store pairs.
49static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]50 cl::init(20), cl::Hidden);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]51
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]52// The UpdateLimit limits how far we search for update instructions when we form
53// pre-/post-index instructions.
54static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
55 cl::Hidden);
56
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]57namespace llvm {
58void initializeAArch64LoadStoreOptPass(PassRegistry &);
59}
60
61#define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
62
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]63namespace {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]64
65typedef struct LdStPairFlags {
66 // If a matching instruction is found, MergeForward is set to true if the
67 // merge is to remove the first instruction and replace the second with
68 // a pair-wise insn, and false if the reverse is true.
69 bool MergeForward;
70
71 // SExtIdx gives the index of the result of the load pair that must be
72 // extended. The value of SExtIdx assumes that the paired load produces the
73 // value in this order: (I, returned iterator), i.e., -1 means no value has
74 // to be extended, 0 means I, and 1 means the returned iterator.
75 int SExtIdx;
76
77 LdStPairFlags() : MergeForward(false), SExtIdx(-1) {}
78
79 void setMergeForward(bool V = true) { MergeForward = V; }
80 bool getMergeForward() const { return MergeForward; }
81
82 void setSExtIdx(int V) { SExtIdx = V; }
83 int getSExtIdx() const { return SExtIdx; }
84
85} LdStPairFlags;
86
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]87struct AArch64LoadStoreOpt : public MachineFunctionPass {
88 static char ID;
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]89 AArch64LoadStoreOpt() : MachineFunctionPass(ID) {
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]90 initializeAArch64LoadStoreOptPass(*PassRegistry::getPassRegistry());
91 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]92
93 const AArch64InstrInfo *TII;
94 const TargetRegisterInfo *TRI;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]95 const AArch64Subtarget *Subtarget;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]96
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]97 // Track which registers have been modified and used.
98 BitVector ModifiedRegs, UsedRegs;
99
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]100 // Scan the instructions looking for a load/store that can be combined
101 // with the current instruction into a load/store pair.
102 // Return the matching instruction if one is found, else MBB->end().
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]103 MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]104 LdStPairFlags &Flags,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]105 unsigned Limit);
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]106
107 // Scan the instructions looking for a store that writes to the address from
108 // which the current load instruction reads. Return true if one is found.
109 bool findMatchingStore(MachineBasicBlock::iterator I, unsigned Limit,
110 MachineBasicBlock::iterator &StoreI);
111
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]112 // Merge the two instructions indicated into a single pair-wise instruction.
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]113 // If MergeForward is true, erase the first instruction and fold its
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]114 // operation into the second. If false, the reverse. Return the instruction
115 // following the first instruction (which may change during processing).
116 MachineBasicBlock::iterator
117 mergePairedInsns(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]118 MachineBasicBlock::iterator Paired,
Chad Rosierfe5399f2015-07-21 17:47:56 +0000[diff] [blame]119 const LdStPairFlags &Flags);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]120
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]121 // Promote the load that reads directly from the address stored to.
122 MachineBasicBlock::iterator
123 promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
124 MachineBasicBlock::iterator StoreI);
125
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]126 // Scan the instruction list to find a base register update that can
127 // be combined with the current instruction (a load or store) using
128 // pre or post indexed addressing with writeback. Scan forwards.
129 MachineBasicBlock::iterator
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]130 findMatchingUpdateInsnForward(MachineBasicBlock::iterator I,
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]131 int UnscaledOffset, unsigned Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]132
133 // Scan the instruction list to find a base register update that can
134 // be combined with the current instruction (a load or store) using
135 // pre or post indexed addressing with writeback. Scan backwards.
136 MachineBasicBlock::iterator
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]137 findMatchingUpdateInsnBackward(MachineBasicBlock::iterator I, unsigned Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]138
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]139 // Find an instruction that updates the base register of the ld/st
140 // instruction.
141 bool isMatchingUpdateInsn(MachineInstr *MemMI, MachineInstr *MI,
142 unsigned BaseReg, int Offset);
143
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]144 // Merge a pre- or post-index base register update into a ld/st instruction.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]145 MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]146 mergeUpdateInsn(MachineBasicBlock::iterator I,
147 MachineBasicBlock::iterator Update, bool IsPreIdx);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]148
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]149 // Find and merge foldable ldr/str instructions.
150 bool tryToMergeLdStInst(MachineBasicBlock::iterator &MBBI);
151
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]152 // Find and promote load instructions which read directly from store.
153 bool tryToPromoteLoadFromStore(MachineBasicBlock::iterator &MBBI);
154
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]155 // Check if converting two narrow loads into a single wider load with
156 // bitfield extracts could be enabled.
157 bool enableNarrowLdMerge(MachineFunction &Fn);
158
159 bool optimizeBlock(MachineBasicBlock &MBB, bool enableNarrowLdOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]160
161 bool runOnMachineFunction(MachineFunction &Fn) override;
162
163 const char *getPassName() const override {
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]164 return AARCH64_LOAD_STORE_OPT_NAME;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]165 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]166};
167char AArch64LoadStoreOpt::ID = 0;
Jim Grosbach1eee3df2014-08-11 22:42:31 +0000[diff] [blame]168} // namespace
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]170INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
171 AARCH64_LOAD_STORE_OPT_NAME, false, false)
172
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]173static bool isUnscaledLdSt(unsigned Opc) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]174 switch (Opc) {
175 default:
176 return false;
177 case AArch64::STURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]178 case AArch64::STURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]179 case AArch64::STURQi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]180 case AArch64::STURBBi:
181 case AArch64::STURHHi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]182 case AArch64::STURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]183 case AArch64::STURXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]184 case AArch64::LDURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]185 case AArch64::LDURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]186 case AArch64::LDURQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]187 case AArch64::LDURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]188 case AArch64::LDURXi:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]189 case AArch64::LDURSWi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]190 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]191 case AArch64::LDURBBi:
192 case AArch64::LDURSBWi:
193 case AArch64::LDURSHWi:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]194 return true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]195 }
196}
197
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]198static bool isUnscaledLdSt(MachineInstr *MI) {
199 return isUnscaledLdSt(MI->getOpcode());
200}
201
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]202static unsigned getBitExtrOpcode(MachineInstr *MI) {
203 switch (MI->getOpcode()) {
204 default:
205 llvm_unreachable("Unexpected opcode.");
206 case AArch64::LDRBBui:
207 case AArch64::LDURBBi:
208 case AArch64::LDRHHui:
209 case AArch64::LDURHHi:
210 return AArch64::UBFMWri;
211 case AArch64::LDRSBWui:
212 case AArch64::LDURSBWi:
213 case AArch64::LDRSHWui:
214 case AArch64::LDURSHWi:
215 return AArch64::SBFMWri;
216 }
217}
218
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]219static bool isNarrowStore(unsigned Opc) {
220 switch (Opc) {
221 default:
222 return false;
223 case AArch64::STRBBui:
224 case AArch64::STURBBi:
225 case AArch64::STRHHui:
226 case AArch64::STURHHi:
227 return true;
228 }
229}
230
231static bool isNarrowStore(MachineInstr *MI) {
232 return isNarrowStore(MI->getOpcode());
233}
234
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]235static bool isNarrowLoad(unsigned Opc) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]236 switch (Opc) {
237 default:
238 return false;
239 case AArch64::LDRHHui:
240 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]241 case AArch64::LDRBBui:
242 case AArch64::LDURBBi:
243 case AArch64::LDRSHWui:
244 case AArch64::LDURSHWi:
245 case AArch64::LDRSBWui:
246 case AArch64::LDURSBWi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]247 return true;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]248 }
249}
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]250
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]251static bool isNarrowLoad(MachineInstr *MI) {
252 return isNarrowLoad(MI->getOpcode());
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]253}
254
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]255// Scaling factor for unscaled load or store.
256static int getMemScale(MachineInstr *MI) {
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]257 switch (MI->getOpcode()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]258 default:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]259 llvm_unreachable("Opcode has unknown scale!");
260 case AArch64::LDRBBui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]261 case AArch64::LDURBBi:
262 case AArch64::LDRSBWui:
263 case AArch64::LDURSBWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]264 case AArch64::STRBBui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]265 case AArch64::STURBBi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]266 return 1;
267 case AArch64::LDRHHui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]268 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]269 case AArch64::LDRSHWui:
270 case AArch64::LDURSHWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]271 case AArch64::STRHHui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]272 case AArch64::STURHHi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]273 return 2;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]274 case AArch64::LDRSui:
275 case AArch64::LDURSi:
276 case AArch64::LDRSWui:
277 case AArch64::LDURSWi:
278 case AArch64::LDRWui:
279 case AArch64::LDURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]280 case AArch64::STRSui:
281 case AArch64::STURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]282 case AArch64::STRWui:
283 case AArch64::STURWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]284 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]285 case AArch64::LDPSWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]286 case AArch64::LDPWi:
287 case AArch64::STPSi:
288 case AArch64::STPWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]289 return 4;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]290 case AArch64::LDRDui:
291 case AArch64::LDURDi:
292 case AArch64::LDRXui:
293 case AArch64::LDURXi:
294 case AArch64::STRDui:
295 case AArch64::STURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]296 case AArch64::STRXui:
297 case AArch64::STURXi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]298 case AArch64::LDPDi:
299 case AArch64::LDPXi:
300 case AArch64::STPDi:
301 case AArch64::STPXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]302 return 8;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]303 case AArch64::LDRQui:
304 case AArch64::LDURQi:
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]305 case AArch64::STRQui:
306 case AArch64::STURQi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]307 case AArch64::LDPQi:
308 case AArch64::STPQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]309 return 16;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]310 }
311}
312
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]313static unsigned getMatchingNonSExtOpcode(unsigned Opc,
314 bool *IsValidLdStrOpc = nullptr) {
315 if (IsValidLdStrOpc)
316 *IsValidLdStrOpc = true;
317 switch (Opc) {
318 default:
319 if (IsValidLdStrOpc)
320 *IsValidLdStrOpc = false;
321 return UINT_MAX;
322 case AArch64::STRDui:
323 case AArch64::STURDi:
324 case AArch64::STRQui:
325 case AArch64::STURQi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]326 case AArch64::STRBBui:
327 case AArch64::STURBBi:
328 case AArch64::STRHHui:
329 case AArch64::STURHHi:
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]330 case AArch64::STRWui:
331 case AArch64::STURWi:
332 case AArch64::STRXui:
333 case AArch64::STURXi:
334 case AArch64::LDRDui:
335 case AArch64::LDURDi:
336 case AArch64::LDRQui:
337 case AArch64::LDURQi:
338 case AArch64::LDRWui:
339 case AArch64::LDURWi:
340 case AArch64::LDRXui:
341 case AArch64::LDURXi:
342 case AArch64::STRSui:
343 case AArch64::STURSi:
344 case AArch64::LDRSui:
345 case AArch64::LDURSi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]346 case AArch64::LDRHHui:
347 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]348 case AArch64::LDRBBui:
349 case AArch64::LDURBBi:
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]350 return Opc;
351 case AArch64::LDRSWui:
352 return AArch64::LDRWui;
353 case AArch64::LDURSWi:
354 return AArch64::LDURWi;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]355 case AArch64::LDRSBWui:
356 return AArch64::LDRBBui;
357 case AArch64::LDRSHWui:
358 return AArch64::LDRHHui;
359 case AArch64::LDURSBWi:
360 return AArch64::LDURBBi;
361 case AArch64::LDURSHWi:
362 return AArch64::LDURHHi;
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]363 }
364}
365
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]366static unsigned getMatchingPairOpcode(unsigned Opc) {
367 switch (Opc) {
368 default:
369 llvm_unreachable("Opcode has no pairwise equivalent!");
370 case AArch64::STRSui:
371 case AArch64::STURSi:
372 return AArch64::STPSi;
373 case AArch64::STRDui:
374 case AArch64::STURDi:
375 return AArch64::STPDi;
376 case AArch64::STRQui:
377 case AArch64::STURQi:
378 return AArch64::STPQi;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]379 case AArch64::STRBBui:
380 return AArch64::STRHHui;
381 case AArch64::STRHHui:
382 return AArch64::STRWui;
383 case AArch64::STURBBi:
384 return AArch64::STURHHi;
385 case AArch64::STURHHi:
386 return AArch64::STURWi;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]387 case AArch64::STRWui:
388 case AArch64::STURWi:
389 return AArch64::STPWi;
390 case AArch64::STRXui:
391 case AArch64::STURXi:
392 return AArch64::STPXi;
393 case AArch64::LDRSui:
394 case AArch64::LDURSi:
395 return AArch64::LDPSi;
396 case AArch64::LDRDui:
397 case AArch64::LDURDi:
398 return AArch64::LDPDi;
399 case AArch64::LDRQui:
400 case AArch64::LDURQi:
401 return AArch64::LDPQi;
402 case AArch64::LDRWui:
403 case AArch64::LDURWi:
404 return AArch64::LDPWi;
405 case AArch64::LDRXui:
406 case AArch64::LDURXi:
407 return AArch64::LDPXi;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]408 case AArch64::LDRSWui:
409 case AArch64::LDURSWi:
410 return AArch64::LDPSWi;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]411 case AArch64::LDRHHui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]412 case AArch64::LDRSHWui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]413 return AArch64::LDRWui;
414 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]415 case AArch64::LDURSHWi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]416 return AArch64::LDURWi;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]417 case AArch64::LDRBBui:
418 case AArch64::LDRSBWui:
419 return AArch64::LDRHHui;
420 case AArch64::LDURBBi:
421 case AArch64::LDURSBWi:
422 return AArch64::LDURHHi;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]423 }
424}
425
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]426static unsigned isMatchingStore(MachineInstr *LoadInst,
427 MachineInstr *StoreInst) {
428 unsigned LdOpc = LoadInst->getOpcode();
429 unsigned StOpc = StoreInst->getOpcode();
430 switch (LdOpc) {
431 default:
432 llvm_unreachable("Unsupported load instruction!");
433 case AArch64::LDRBBui:
434 return StOpc == AArch64::STRBBui || StOpc == AArch64::STRHHui ||
435 StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
436 case AArch64::LDURBBi:
437 return StOpc == AArch64::STURBBi || StOpc == AArch64::STURHHi ||
438 StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
439 case AArch64::LDRHHui:
440 return StOpc == AArch64::STRHHui || StOpc == AArch64::STRWui ||
441 StOpc == AArch64::STRXui;
442 case AArch64::LDURHHi:
443 return StOpc == AArch64::STURHHi || StOpc == AArch64::STURWi ||
444 StOpc == AArch64::STURXi;
445 case AArch64::LDRWui:
446 return StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
447 case AArch64::LDURWi:
448 return StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
449 case AArch64::LDRXui:
450 return StOpc == AArch64::STRXui;
451 case AArch64::LDURXi:
452 return StOpc == AArch64::STURXi;
453 }
454}
455
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]456static unsigned getPreIndexedOpcode(unsigned Opc) {
457 switch (Opc) {
458 default:
459 llvm_unreachable("Opcode has no pre-indexed equivalent!");
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]460 case AArch64::STRSui:
461 return AArch64::STRSpre;
462 case AArch64::STRDui:
463 return AArch64::STRDpre;
464 case AArch64::STRQui:
465 return AArch64::STRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]466 case AArch64::STRBBui:
467 return AArch64::STRBBpre;
468 case AArch64::STRHHui:
469 return AArch64::STRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]470 case AArch64::STRWui:
471 return AArch64::STRWpre;
472 case AArch64::STRXui:
473 return AArch64::STRXpre;
474 case AArch64::LDRSui:
475 return AArch64::LDRSpre;
476 case AArch64::LDRDui:
477 return AArch64::LDRDpre;
478 case AArch64::LDRQui:
479 return AArch64::LDRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]480 case AArch64::LDRBBui:
481 return AArch64::LDRBBpre;
482 case AArch64::LDRHHui:
483 return AArch64::LDRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]484 case AArch64::LDRWui:
485 return AArch64::LDRWpre;
486 case AArch64::LDRXui:
487 return AArch64::LDRXpre;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]488 case AArch64::LDRSWui:
489 return AArch64::LDRSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]490 case AArch64::LDPSi:
491 return AArch64::LDPSpre;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]492 case AArch64::LDPSWi:
493 return AArch64::LDPSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]494 case AArch64::LDPDi:
495 return AArch64::LDPDpre;
496 case AArch64::LDPQi:
497 return AArch64::LDPQpre;
498 case AArch64::LDPWi:
499 return AArch64::LDPWpre;
500 case AArch64::LDPXi:
501 return AArch64::LDPXpre;
502 case AArch64::STPSi:
503 return AArch64::STPSpre;
504 case AArch64::STPDi:
505 return AArch64::STPDpre;
506 case AArch64::STPQi:
507 return AArch64::STPQpre;
508 case AArch64::STPWi:
509 return AArch64::STPWpre;
510 case AArch64::STPXi:
511 return AArch64::STPXpre;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]512 }
513}
514
515static unsigned getPostIndexedOpcode(unsigned Opc) {
516 switch (Opc) {
517 default:
518 llvm_unreachable("Opcode has no post-indexed wise equivalent!");
519 case AArch64::STRSui:
520 return AArch64::STRSpost;
521 case AArch64::STRDui:
522 return AArch64::STRDpost;
523 case AArch64::STRQui:
524 return AArch64::STRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]525 case AArch64::STRBBui:
526 return AArch64::STRBBpost;
527 case AArch64::STRHHui:
528 return AArch64::STRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]529 case AArch64::STRWui:
530 return AArch64::STRWpost;
531 case AArch64::STRXui:
532 return AArch64::STRXpost;
533 case AArch64::LDRSui:
534 return AArch64::LDRSpost;
535 case AArch64::LDRDui:
536 return AArch64::LDRDpost;
537 case AArch64::LDRQui:
538 return AArch64::LDRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]539 case AArch64::LDRBBui:
540 return AArch64::LDRBBpost;
541 case AArch64::LDRHHui:
542 return AArch64::LDRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]543 case AArch64::LDRWui:
544 return AArch64::LDRWpost;
545 case AArch64::LDRXui:
546 return AArch64::LDRXpost;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]547 case AArch64::LDRSWui:
548 return AArch64::LDRSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]549 case AArch64::LDPSi:
550 return AArch64::LDPSpost;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]551 case AArch64::LDPSWi:
552 return AArch64::LDPSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]553 case AArch64::LDPDi:
554 return AArch64::LDPDpost;
555 case AArch64::LDPQi:
556 return AArch64::LDPQpost;
557 case AArch64::LDPWi:
558 return AArch64::LDPWpost;
559 case AArch64::LDPXi:
560 return AArch64::LDPXpost;
561 case AArch64::STPSi:
562 return AArch64::STPSpost;
563 case AArch64::STPDi:
564 return AArch64::STPDpost;
565 case AArch64::STPQi:
566 return AArch64::STPQpost;
567 case AArch64::STPWi:
568 return AArch64::STPWpost;
569 case AArch64::STPXi:
570 return AArch64::STPXpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]571 }
572}
573
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]574static bool isPairedLdSt(const MachineInstr *MI) {
575 switch (MI->getOpcode()) {
576 default:
577 return false;
578 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]579 case AArch64::LDPSWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]580 case AArch64::LDPDi:
581 case AArch64::LDPQi:
582 case AArch64::LDPWi:
583 case AArch64::LDPXi:
584 case AArch64::STPSi:
585 case AArch64::STPDi:
586 case AArch64::STPQi:
587 case AArch64::STPWi:
588 case AArch64::STPXi:
589 return true;
590 }
591}
592
593static const MachineOperand &getLdStRegOp(const MachineInstr *MI,
594 unsigned PairedRegOp = 0) {
595 assert(PairedRegOp < 2 && "Unexpected register operand idx.");
596 unsigned Idx = isPairedLdSt(MI) ? PairedRegOp : 0;
597 return MI->getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]598}
599
600static const MachineOperand &getLdStBaseOp(const MachineInstr *MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]601 unsigned Idx = isPairedLdSt(MI) ? 2 : 1;
602 return MI->getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]603}
604
605static const MachineOperand &getLdStOffsetOp(const MachineInstr *MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]606 unsigned Idx = isPairedLdSt(MI) ? 3 : 2;
607 return MI->getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]608}
609
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]610static bool isLdOffsetInRangeOfSt(MachineInstr *LoadInst,
611 MachineInstr *StoreInst) {
612 assert(isMatchingStore(LoadInst, StoreInst) && "Expect only matched ld/st.");
613 int LoadSize = getMemScale(LoadInst);
614 int StoreSize = getMemScale(StoreInst);
615 int UnscaledStOffset = isUnscaledLdSt(StoreInst)
616 ? getLdStOffsetOp(StoreInst).getImm()
617 : getLdStOffsetOp(StoreInst).getImm() * StoreSize;
618 int UnscaledLdOffset = isUnscaledLdSt(LoadInst)
619 ? getLdStOffsetOp(LoadInst).getImm()
620 : getLdStOffsetOp(LoadInst).getImm() * LoadSize;
621 return (UnscaledStOffset <= UnscaledLdOffset) &&
622 (UnscaledLdOffset + LoadSize <= (UnscaledStOffset + StoreSize));
623}
624
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]625MachineBasicBlock::iterator
626AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
627 MachineBasicBlock::iterator Paired,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]628 const LdStPairFlags &Flags) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]629 MachineBasicBlock::iterator NextI = I;
630 ++NextI;
631 // If NextI is the second of the two instructions to be merged, we need
632 // to skip one further. Either way we merge will invalidate the iterator,
633 // and we don't need to scan the new instruction, as it's a pairwise
634 // instruction, which we're not considering for further action anyway.
635 if (NextI == Paired)
636 ++NextI;
637
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]638 int SExtIdx = Flags.getSExtIdx();
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]639 unsigned Opc =
640 SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]641 bool IsUnscaled = isUnscaledLdSt(Opc);
Chad Rosierf11d0402015-10-01 18:17:12 +0000[diff] [blame]642 int OffsetStride = IsUnscaled ? getMemScale(I) : 1;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]643
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]644 bool MergeForward = Flags.getMergeForward();
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]645 unsigned NewOpc = getMatchingPairOpcode(Opc);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]646 // Insert our new paired instruction after whichever of the paired
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]647 // instructions MergeForward indicates.
648 MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
649 // Also based on MergeForward is from where we copy the base register operand
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]650 // so we get the flags compatible with the input code.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]651 const MachineOperand &BaseRegOp =
652 MergeForward ? getLdStBaseOp(Paired) : getLdStBaseOp(I);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]653
654 // Which register is Rt and which is Rt2 depends on the offset order.
655 MachineInstr *RtMI, *Rt2MI;
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame^]656 if (getLdStOffsetOp(I).getImm() ==
657 getLdStOffsetOp(Paired).getImm() + OffsetStride) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]658 RtMI = Paired;
659 Rt2MI = I;
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]660 // Here we swapped the assumption made for SExtIdx.
661 // I.e., we turn ldp I, Paired into ldp Paired, I.
662 // Update the index accordingly.
663 if (SExtIdx != -1)
664 SExtIdx = (SExtIdx + 1) % 2;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]665 } else {
666 RtMI = I;
667 Rt2MI = Paired;
668 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]669
James Molloy5b18b4c2015-10-23 10:41:38 +0000[diff] [blame]670 int OffsetImm = getLdStOffsetOp(RtMI).getImm();
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]671
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]672 if (isNarrowLoad(Opc)) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]673 // Change the scaled offset from small to large type.
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]674 if (!IsUnscaled) {
675 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]676 OffsetImm /= 2;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]677 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]678 MachineInstr *RtNewDest = MergeForward ? I : Paired;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]679 // When merging small (< 32 bit) loads for big-endian targets, the order of
680 // the component parts gets swapped.
681 if (!Subtarget->isLittleEndian())
682 std::swap(RtMI, Rt2MI);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]683 // Construct the new load instruction.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]684 MachineInstr *NewMemMI, *BitExtMI1, *BitExtMI2;
685 NewMemMI = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
686 TII->get(NewOpc))
687 .addOperand(getLdStRegOp(RtNewDest))
688 .addOperand(BaseRegOp)
Philip Reamesc86ed002016-01-06 04:39:03 +0000[diff] [blame]689 .addImm(OffsetImm)
690 .setMemRefs(I->mergeMemRefsWith(*Paired));
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]691
692 DEBUG(
693 dbgs()
694 << "Creating the new load and extract. Replacing instructions:\n ");
695 DEBUG(I->print(dbgs()));
696 DEBUG(dbgs() << " ");
697 DEBUG(Paired->print(dbgs()));
698 DEBUG(dbgs() << " with instructions:\n ");
699 DEBUG((NewMemMI)->print(dbgs()));
700
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]701 int Width = getMemScale(I) == 1 ? 8 : 16;
702 int LSBLow = 0;
703 int LSBHigh = Width;
704 int ImmsLow = LSBLow + Width - 1;
705 int ImmsHigh = LSBHigh + Width - 1;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]706 MachineInstr *ExtDestMI = MergeForward ? Paired : I;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]707 if ((ExtDestMI == Rt2MI) == Subtarget->isLittleEndian()) {
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]708 // Create the bitfield extract for high bits.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]709 BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]710 TII->get(getBitExtrOpcode(Rt2MI)))
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]711 .addOperand(getLdStRegOp(Rt2MI))
712 .addReg(getLdStRegOp(RtNewDest).getReg())
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]713 .addImm(LSBHigh)
714 .addImm(ImmsHigh);
715 // Create the bitfield extract for low bits.
716 if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
717 // For unsigned, prefer to use AND for low bits.
718 BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
719 TII->get(AArch64::ANDWri))
720 .addOperand(getLdStRegOp(RtMI))
721 .addReg(getLdStRegOp(RtNewDest).getReg())
722 .addImm(ImmsLow);
723 } else {
724 BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
725 TII->get(getBitExtrOpcode(RtMI)))
726 .addOperand(getLdStRegOp(RtMI))
727 .addReg(getLdStRegOp(RtNewDest).getReg())
728 .addImm(LSBLow)
729 .addImm(ImmsLow);
730 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]731 } else {
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]732 // Create the bitfield extract for low bits.
733 if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
734 // For unsigned, prefer to use AND for low bits.
735 BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
736 TII->get(AArch64::ANDWri))
737 .addOperand(getLdStRegOp(RtMI))
738 .addReg(getLdStRegOp(RtNewDest).getReg())
739 .addImm(ImmsLow);
740 } else {
741 BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
742 TII->get(getBitExtrOpcode(RtMI)))
743 .addOperand(getLdStRegOp(RtMI))
744 .addReg(getLdStRegOp(RtNewDest).getReg())
745 .addImm(LSBLow)
746 .addImm(ImmsLow);
747 }
748
749 // Create the bitfield extract for high bits.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]750 BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]751 TII->get(getBitExtrOpcode(Rt2MI)))
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]752 .addOperand(getLdStRegOp(Rt2MI))
753 .addReg(getLdStRegOp(RtNewDest).getReg())
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]754 .addImm(LSBHigh)
755 .addImm(ImmsHigh);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]756 }
757 DEBUG(dbgs() << " ");
758 DEBUG((BitExtMI1)->print(dbgs()));
759 DEBUG(dbgs() << " ");
760 DEBUG((BitExtMI2)->print(dbgs()));
761 DEBUG(dbgs() << "\n");
762
763 // Erase the old instructions.
764 I->eraseFromParent();
765 Paired->eraseFromParent();
766 return NextI;
767 }
768
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]769 // Construct the new instruction.
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]770 MachineInstrBuilder MIB;
771 if (isNarrowStore(Opc)) {
772 // Change the scaled offset from small to large type.
773 if (!IsUnscaled) {
774 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
775 OffsetImm /= 2;
776 }
777 MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
778 TII->get(NewOpc))
779 .addOperand(getLdStRegOp(I))
780 .addOperand(BaseRegOp)
Philip Reamesc86ed002016-01-06 04:39:03 +0000[diff] [blame]781 .addImm(OffsetImm)
782 .setMemRefs(I->mergeMemRefsWith(*Paired));
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]783 } else {
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame^]784 // Handle Unscaled
785 if (IsUnscaled)
786 OffsetImm /= OffsetStride;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]787 MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
788 TII->get(NewOpc))
789 .addOperand(getLdStRegOp(RtMI))
790 .addOperand(getLdStRegOp(Rt2MI))
791 .addOperand(BaseRegOp)
792 .addImm(OffsetImm);
793 }
794
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]795 (void)MIB;
796
797 // FIXME: Do we need/want to copy the mem operands from the source
798 // instructions? Probably. What uses them after this?
799
800 DEBUG(dbgs() << "Creating pair load/store. Replacing instructions:\n ");
801 DEBUG(I->print(dbgs()));
802 DEBUG(dbgs() << " ");
803 DEBUG(Paired->print(dbgs()));
804 DEBUG(dbgs() << " with instruction:\n ");
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]805
806 if (SExtIdx != -1) {
807 // Generate the sign extension for the proper result of the ldp.
808 // I.e., with X1, that would be:
809 // %W1<def> = KILL %W1, %X1<imp-def>
810 // %X1<def> = SBFMXri %X1<kill>, 0, 31
811 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
812 // Right now, DstMO has the extended register, since it comes from an
813 // extended opcode.
814 unsigned DstRegX = DstMO.getReg();
815 // Get the W variant of that register.
816 unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
817 // Update the result of LDP to use the W instead of the X variant.
818 DstMO.setReg(DstRegW);
819 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
820 DEBUG(dbgs() << "\n");
821 // Make the machine verifier happy by providing a definition for
822 // the X register.
823 // Insert this definition right after the generated LDP, i.e., before
824 // InsertionPoint.
825 MachineInstrBuilder MIBKill =
826 BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
827 TII->get(TargetOpcode::KILL), DstRegW)
828 .addReg(DstRegW)
829 .addReg(DstRegX, RegState::Define);
830 MIBKill->getOperand(2).setImplicit();
831 // Create the sign extension.
832 MachineInstrBuilder MIBSXTW =
833 BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
834 TII->get(AArch64::SBFMXri), DstRegX)
835 .addReg(DstRegX)
836 .addImm(0)
837 .addImm(31);
838 (void)MIBSXTW;
839 DEBUG(dbgs() << " Extend operand:\n ");
840 DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
841 DEBUG(dbgs() << "\n");
842 } else {
843 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
844 DEBUG(dbgs() << "\n");
845 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]846
847 // Erase the old instructions.
848 I->eraseFromParent();
849 Paired->eraseFromParent();
850
851 return NextI;
852}
853
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]854MachineBasicBlock::iterator
855AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
856 MachineBasicBlock::iterator StoreI) {
857 MachineBasicBlock::iterator NextI = LoadI;
858 ++NextI;
859
860 int LoadSize = getMemScale(LoadI);
861 int StoreSize = getMemScale(StoreI);
862 unsigned LdRt = getLdStRegOp(LoadI).getReg();
863 unsigned StRt = getLdStRegOp(StoreI).getReg();
864 bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
865
866 assert((IsStoreXReg ||
867 TRI->getRegClass(AArch64::GPR32RegClassID)->contains(StRt)) &&
868 "Unexpected RegClass");
869
870 MachineInstr *BitExtMI;
871 if (LoadSize == StoreSize && (LoadSize == 4 || LoadSize == 8)) {
872 // Remove the load, if the destination register of the loads is the same
873 // register for stored value.
874 if (StRt == LdRt && LoadSize == 8) {
875 DEBUG(dbgs() << "Remove load instruction:\n ");
876 DEBUG(LoadI->print(dbgs()));
877 DEBUG(dbgs() << "\n");
878 LoadI->eraseFromParent();
879 return NextI;
880 }
881 // Replace the load with a mov if the load and store are in the same size.
882 BitExtMI =
883 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
884 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
885 .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
886 .addReg(StRt)
887 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
888 } else {
889 // FIXME: Currently we disable this transformation in big-endian targets as
890 // performance and correctness are verified only in little-endian.
891 if (!Subtarget->isLittleEndian())
892 return NextI;
893 bool IsUnscaled = isUnscaledLdSt(LoadI);
894 assert(IsUnscaled == isUnscaledLdSt(StoreI) && "Unsupported ld/st match");
895 assert(LoadSize <= StoreSize && "Invalid load size");
896 int UnscaledLdOffset = IsUnscaled
897 ? getLdStOffsetOp(LoadI).getImm()
898 : getLdStOffsetOp(LoadI).getImm() * LoadSize;
899 int UnscaledStOffset = IsUnscaled
900 ? getLdStOffsetOp(StoreI).getImm()
901 : getLdStOffsetOp(StoreI).getImm() * StoreSize;
902 int Width = LoadSize * 8;
903 int Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
904 int Imms = Immr + Width - 1;
905 unsigned DestReg = IsStoreXReg
906 ? TRI->getMatchingSuperReg(LdRt, AArch64::sub_32,
907 &AArch64::GPR64RegClass)
908 : LdRt;
909
910 assert((UnscaledLdOffset >= UnscaledStOffset &&
911 (UnscaledLdOffset + LoadSize) <= UnscaledStOffset + StoreSize) &&
912 "Invalid offset");
913
914 Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
915 Imms = Immr + Width - 1;
916 if (UnscaledLdOffset == UnscaledStOffset) {
917 uint32_t AndMaskEncoded = ((IsStoreXReg ? 1 : 0) << 12) // N
918 | ((Immr) << 6) // immr
919 | ((Imms) << 0) // imms
920 ;
921
922 BitExtMI =
923 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
924 TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
925 DestReg)
926 .addReg(StRt)
927 .addImm(AndMaskEncoded);
928 } else {
929 BitExtMI =
930 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
931 TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
932 DestReg)
933 .addReg(StRt)
934 .addImm(Immr)
935 .addImm(Imms);
936 }
937 }
938
939 DEBUG(dbgs() << "Promoting load by replacing :\n ");
940 DEBUG(StoreI->print(dbgs()));
941 DEBUG(dbgs() << " ");
942 DEBUG(LoadI->print(dbgs()));
943 DEBUG(dbgs() << " with instructions:\n ");
944 DEBUG(StoreI->print(dbgs()));
945 DEBUG(dbgs() << " ");
946 DEBUG((BitExtMI)->print(dbgs()));
947 DEBUG(dbgs() << "\n");
948
949 // Erase the old instructions.
950 LoadI->eraseFromParent();
951 return NextI;
952}
953
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]954/// trackRegDefsUses - Remember what registers the specified instruction uses
955/// and modifies.
Pete Cooper7be8f8f2015-08-03 19:04:32 +0000[diff] [blame]956static void trackRegDefsUses(const MachineInstr *MI, BitVector &ModifiedRegs,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]957 BitVector &UsedRegs,
958 const TargetRegisterInfo *TRI) {
Pete Cooper7be8f8f2015-08-03 19:04:32 +0000[diff] [blame]959 for (const MachineOperand &MO : MI->operands()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]960 if (MO.isRegMask())
961 ModifiedRegs.setBitsNotInMask(MO.getRegMask());
962
963 if (!MO.isReg())
964 continue;
965 unsigned Reg = MO.getReg();
966 if (MO.isDef()) {
967 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
968 ModifiedRegs.set(*AI);
969 } else {
970 assert(MO.isUse() && "Reg operand not a def and not a use?!?");
971 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
972 UsedRegs.set(*AI);
973 }
974 }
975}
976
977static bool inBoundsForPair(bool IsUnscaled, int Offset, int OffsetStride) {
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]978 // Convert the byte-offset used by unscaled into an "element" offset used
979 // by the scaled pair load/store instructions.
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame^]980 if (IsUnscaled)
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]981 Offset /= OffsetStride;
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame^]982
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]983 return Offset <= 63 && Offset >= -64;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]984}
985
986// Do alignment, specialized to power of 2 and for signed ints,
987// avoiding having to do a C-style cast from uint_64t to int when
Rui Ueyamada00f2f2016-01-14 21:06:47 +0000[diff] [blame]988// using alignTo from include/llvm/Support/MathExtras.h.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]989// FIXME: Move this function to include/MathExtras.h?
990static int alignTo(int Num, int PowOf2) {
991 return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
992}
993
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]994static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb,
995 const AArch64InstrInfo *TII) {
996 // One of the instructions must modify memory.
997 if (!MIa->mayStore() && !MIb->mayStore())
998 return false;
999
1000 // Both instructions must be memory operations.
1001 if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore())
1002 return false;
1003
1004 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
1005}
1006
1007static bool mayAlias(MachineInstr *MIa,
1008 SmallVectorImpl<MachineInstr *> &MemInsns,
1009 const AArch64InstrInfo *TII) {
1010 for (auto &MIb : MemInsns)
1011 if (mayAlias(MIa, MIb, TII))
1012 return true;
1013
1014 return false;
1015}
1016
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1017bool AArch64LoadStoreOpt::findMatchingStore(
1018 MachineBasicBlock::iterator I, unsigned Limit,
1019 MachineBasicBlock::iterator &StoreI) {
1020 MachineBasicBlock::iterator E = I->getParent()->begin();
1021 MachineBasicBlock::iterator MBBI = I;
1022 MachineInstr *FirstMI = I;
1023 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1024
1025 // Track which registers have been modified and used between the first insn
1026 // and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1027 ModifiedRegs.reset();
1028 UsedRegs.reset();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1029
Chad Rosier1142f3c2016-02-02 15:22:55 +0000[diff] [blame]1030 // FIXME: We miss the case where the matching store is the first instruction
1031 // in the basic block.
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1032 for (unsigned Count = 0; MBBI != E && Count < Limit;) {
1033 --MBBI;
1034 MachineInstr *MI = MBBI;
1035 // Skip DBG_VALUE instructions. Otherwise debug info can affect the
1036 // optimization by changing how far we scan.
1037 if (MI->isDebugValue())
1038 continue;
1039 // Now that we know this is a real instruction, count it.
1040 ++Count;
1041
1042 // If the load instruction reads directly from the address to which the
1043 // store instruction writes and the stored value is not modified, we can
1044 // promote the load. Since we do not handle stores with pre-/post-index,
1045 // it's unnecessary to check if BaseReg is modified by the store itself.
1046 if (MI->mayStore() && isMatchingStore(FirstMI, MI) &&
1047 BaseReg == getLdStBaseOp(MI).getReg() &&
1048 isLdOffsetInRangeOfSt(FirstMI, MI) &&
1049 !ModifiedRegs[getLdStRegOp(MI).getReg()]) {
1050 StoreI = MBBI;
1051 return true;
1052 }
1053
1054 if (MI->isCall())
1055 return false;
1056
1057 // Update modified / uses register lists.
1058 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1059
1060 // Otherwise, if the base register is modified, we have no match, so
1061 // return early.
1062 if (ModifiedRegs[BaseReg])
1063 return false;
1064
1065 // If we encounter a store aliased with the load, return early.
1066 if (MI->mayStore() && mayAlias(FirstMI, MI, TII))
1067 return false;
1068 }
1069 return false;
1070}
1071
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1072/// findMatchingInsn - Scan the instructions looking for a load/store that can
1073/// be combined with the current instruction into a load/store pair.
1074MachineBasicBlock::iterator
1075AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1076 LdStPairFlags &Flags, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1077 MachineBasicBlock::iterator E = I->getParent()->end();
1078 MachineBasicBlock::iterator MBBI = I;
1079 MachineInstr *FirstMI = I;
1080 ++MBBI;
1081
Matthias Braunfa3872e2015-05-18 20:27:55 +0000[diff] [blame]1082 unsigned Opc = FirstMI->getOpcode();
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]1083 bool MayLoad = FirstMI->mayLoad();
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]1084 bool IsUnscaled = isUnscaledLdSt(FirstMI);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1085 unsigned Reg = getLdStRegOp(FirstMI).getReg();
1086 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1087 int Offset = getLdStOffsetOp(FirstMI).getImm();
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1088 bool IsNarrowStore = isNarrowStore(Opc);
1089
1090 // For narrow stores, find only the case where the stored value is WZR.
1091 if (IsNarrowStore && Reg != AArch64::WZR)
1092 return E;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1093
1094 // Early exit if the first instruction modifies the base register.
1095 // e.g., ldr x0, [x0]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1096 if (FirstMI->modifiesRegister(BaseReg, TRI))
1097 return E;
Chad Rosiercaed6db2015-08-10 17:17:19 +0000[diff] [blame]1098
1099 // Early exit if the offset if not possible to match. (6 bits of positive
1100 // range, plus allow an extra one in case we find a later insn that matches
1101 // with Offset-1)
Chad Rosierf11d0402015-10-01 18:17:12 +0000[diff] [blame]1102 int OffsetStride = IsUnscaled ? getMemScale(FirstMI) : 1;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1103 if (!(isNarrowLoad(Opc) || IsNarrowStore) &&
1104 !inBoundsForPair(IsUnscaled, Offset, OffsetStride))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1105 return E;
1106
1107 // Track which registers have been modified and used between the first insn
1108 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1109 ModifiedRegs.reset();
1110 UsedRegs.reset();
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1111
1112 // Remember any instructions that read/write memory between FirstMI and MI.
1113 SmallVector<MachineInstr *, 4> MemInsns;
1114
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1115 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
1116 MachineInstr *MI = MBBI;
1117 // Skip DBG_VALUE instructions. Otherwise debug info can affect the
1118 // optimization by changing how far we scan.
1119 if (MI->isDebugValue())
1120 continue;
1121
1122 // Now that we know this is a real instruction, count it.
1123 ++Count;
1124
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame^]1125 bool CanMergeOpc = Opc == MI->getOpcode();
Chad Rosier18896c02016-02-04 16:01:40 +0000[diff] [blame]1126 Flags.setSExtIdx(-1);
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame^]1127 if (!CanMergeOpc) {
1128 bool IsValidLdStrOpc;
1129 unsigned NonSExtOpc = getMatchingNonSExtOpcode(Opc, &IsValidLdStrOpc);
1130 assert(IsValidLdStrOpc &&
1131 "Given Opc should be a Load or Store with an immediate");
1132 // Opc will be the first instruction in the pair.
1133 Flags.setSExtIdx(NonSExtOpc == (unsigned)Opc ? 1 : 0);
1134 CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode(MI->getOpcode());
1135 }
1136
1137 if (CanMergeOpc && getLdStOffsetOp(MI).isImm()) {
Chad Rosierc56a9132015-08-10 18:42:45 +0000[diff] [blame]1138 assert(MI->mayLoadOrStore() && "Expected memory operation.");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1139 // If we've found another instruction with the same opcode, check to see
1140 // if the base and offset are compatible with our starting instruction.
1141 // These instructions all have scaled immediate operands, so we just
1142 // check for +1/-1. Make sure to check the new instruction offset is
1143 // actually an immediate and not a symbolic reference destined for
1144 // a relocation.
1145 //
1146 // Pairwise instructions have a 7-bit signed offset field. Single insns
1147 // have a 12-bit unsigned offset field. To be a valid combine, the
1148 // final offset must be in range.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1149 unsigned MIBaseReg = getLdStBaseOp(MI).getReg();
1150 int MIOffset = getLdStOffsetOp(MI).getImm();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1151 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
1152 (Offset + OffsetStride == MIOffset))) {
1153 int MinOffset = Offset < MIOffset ? Offset : MIOffset;
1154 // If this is a volatile load/store that otherwise matched, stop looking
1155 // as something is going on that we don't have enough information to
1156 // safely transform. Similarly, stop if we see a hint to avoid pairs.
1157 if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
1158 return E;
1159 // If the resultant immediate offset of merging these instructions
1160 // is out of range for a pairwise instruction, bail and keep looking.
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame^]1161 bool MIIsUnscaled = isUnscaledLdSt(MI);
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1162 bool IsNarrowLoad = isNarrowLoad(MI->getOpcode());
1163 if (!IsNarrowLoad &&
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame^]1164 !inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1165 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Chad Rosierc56a9132015-08-10 18:42:45 +0000[diff] [blame]1166 MemInsns.push_back(MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1167 continue;
1168 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1169
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1170 if (IsNarrowLoad || IsNarrowStore) {
1171 // If the alignment requirements of the scaled wide load/store
1172 // instruction can't express the offset of the scaled narrow
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1173 // input, bail and keep looking.
1174 if (!IsUnscaled && alignTo(MinOffset, 2) != MinOffset) {
1175 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1176 MemInsns.push_back(MI);
1177 continue;
1178 }
1179 } else {
1180 // If the alignment requirements of the paired (scaled) instruction
1181 // can't express the offset of the unscaled input, bail and keep
1182 // looking.
1183 if (IsUnscaled && (alignTo(MinOffset, OffsetStride) != MinOffset)) {
1184 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1185 MemInsns.push_back(MI);
1186 continue;
1187 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1188 }
1189 // If the destination register of the loads is the same register, bail
1190 // and keep looking. A load-pair instruction with both destination
1191 // registers the same is UNPREDICTABLE and will result in an exception.
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1192 // For narrow stores, allow only when the stored value is the same
1193 // (i.e., WZR).
1194 if ((MayLoad && Reg == getLdStRegOp(MI).getReg()) ||
1195 (IsNarrowStore && Reg != getLdStRegOp(MI).getReg())) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1196 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Chad Rosierc56a9132015-08-10 18:42:45 +0000[diff] [blame]1197 MemInsns.push_back(MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1198 continue;
1199 }
1200
1201 // If the Rt of the second instruction was not modified or used between
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1202 // the two instructions and none of the instructions between the second
1203 // and first alias with the second, we can combine the second into the
1204 // first.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1205 if (!ModifiedRegs[getLdStRegOp(MI).getReg()] &&
1206 !(MI->mayLoad() && UsedRegs[getLdStRegOp(MI).getReg()]) &&
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1207 !mayAlias(MI, MemInsns, TII)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1208 Flags.setMergeForward(false);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1209 return MBBI;
1210 }
1211
1212 // Likewise, if the Rt of the first instruction is not modified or used
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1213 // between the two instructions and none of the instructions between the
1214 // first and the second alias with the first, we can combine the first
1215 // into the second.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1216 if (!ModifiedRegs[getLdStRegOp(FirstMI).getReg()] &&
Chad Rosier5f668e12015-09-03 14:19:43 +0000[diff] [blame]1217 !(MayLoad && UsedRegs[getLdStRegOp(FirstMI).getReg()]) &&
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1218 !mayAlias(FirstMI, MemInsns, TII)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1219 Flags.setMergeForward(true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1220 return MBBI;
1221 }
1222 // Unable to combine these instructions due to interference in between.
1223 // Keep looking.
1224 }
1225 }
1226
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1227 // If the instruction wasn't a matching load or store. Stop searching if we
1228 // encounter a call instruction that might modify memory.
1229 if (MI->isCall())
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1230 return E;
1231
1232 // Update modified / uses register lists.
1233 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1234
1235 // Otherwise, if the base register is modified, we have no match, so
1236 // return early.
1237 if (ModifiedRegs[BaseReg])
1238 return E;
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1239
1240 // Update list of instructions that read/write memory.
1241 if (MI->mayLoadOrStore())
1242 MemInsns.push_back(MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1243 }
1244 return E;
1245}
1246
1247MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1248AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
1249 MachineBasicBlock::iterator Update,
1250 bool IsPreIdx) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1251 assert((Update->getOpcode() == AArch64::ADDXri ||
1252 Update->getOpcode() == AArch64::SUBXri) &&
1253 "Unexpected base register update instruction to merge!");
1254 MachineBasicBlock::iterator NextI = I;
1255 // Return the instruction following the merged instruction, which is
1256 // the instruction following our unmerged load. Unless that's the add/sub
1257 // instruction we're merging, in which case it's the one after that.
1258 if (++NextI == Update)
1259 ++NextI;
1260
1261 int Value = Update->getOperand(2).getImm();
1262 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1263 "Can't merge 1 << 12 offset into pre-/post-indexed load / store");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1264 if (Update->getOpcode() == AArch64::SUBXri)
1265 Value = -Value;
1266
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1267 unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode())
1268 : getPostIndexedOpcode(I->getOpcode());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1269 MachineInstrBuilder MIB;
1270 if (!isPairedLdSt(I)) {
1271 // Non-paired instruction.
1272 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1273 .addOperand(getLdStRegOp(Update))
1274 .addOperand(getLdStRegOp(I))
1275 .addOperand(getLdStBaseOp(I))
Chad Rosier3ada75f2016-01-28 15:38:24 +0000[diff] [blame]1276 .addImm(Value)
1277 .setMemRefs(I->memoperands_begin(), I->memoperands_end());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1278 } else {
1279 // Paired instruction.
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]1280 int Scale = getMemScale(I);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1282 .addOperand(getLdStRegOp(Update))
1283 .addOperand(getLdStRegOp(I, 0))
1284 .addOperand(getLdStRegOp(I, 1))
1285 .addOperand(getLdStBaseOp(I))
Chad Rosier3ada75f2016-01-28 15:38:24 +0000[diff] [blame]1286 .addImm(Value / Scale)
1287 .setMemRefs(I->memoperands_begin(), I->memoperands_end());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1288 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1289 (void)MIB;
1290
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1291 if (IsPreIdx)
1292 DEBUG(dbgs() << "Creating pre-indexed load/store.");
1293 else
1294 DEBUG(dbgs() << "Creating post-indexed load/store.");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1295 DEBUG(dbgs() << " Replacing instructions:\n ");
1296 DEBUG(I->print(dbgs()));
1297 DEBUG(dbgs() << " ");
1298 DEBUG(Update->print(dbgs()));
1299 DEBUG(dbgs() << " with instruction:\n ");
1300 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
1301 DEBUG(dbgs() << "\n");
1302
1303 // Erase the old instructions for the block.
1304 I->eraseFromParent();
1305 Update->eraseFromParent();
1306
1307 return NextI;
1308}
1309
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1310bool AArch64LoadStoreOpt::isMatchingUpdateInsn(MachineInstr *MemMI,
1311 MachineInstr *MI,
1312 unsigned BaseReg, int Offset) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1313 switch (MI->getOpcode()) {
1314 default:
1315 break;
1316 case AArch64::SUBXri:
1317 // Negate the offset for a SUB instruction.
1318 Offset *= -1;
1319 // FALLTHROUGH
1320 case AArch64::ADDXri:
1321 // Make sure it's a vanilla immediate operand, not a relocation or
1322 // anything else we can't handle.
1323 if (!MI->getOperand(2).isImm())
1324 break;
1325 // Watch out for 1 << 12 shifted value.
1326 if (AArch64_AM::getShiftValue(MI->getOperand(3).getImm()))
1327 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1328
1329 // The update instruction source and destination register must be the
1330 // same as the load/store base register.
1331 if (MI->getOperand(0).getReg() != BaseReg ||
1332 MI->getOperand(1).getReg() != BaseReg)
1333 break;
1334
1335 bool IsPairedInsn = isPairedLdSt(MemMI);
1336 int UpdateOffset = MI->getOperand(2).getImm();
1337 // For non-paired load/store instructions, the immediate must fit in a
1338 // signed 9-bit integer.
1339 if (!IsPairedInsn && (UpdateOffset > 255 || UpdateOffset < -256))
1340 break;
1341
1342 // For paired load/store instructions, the immediate must be a multiple of
1343 // the scaling factor. The scaled offset must also fit into a signed 7-bit
1344 // integer.
1345 if (IsPairedInsn) {
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]1346 int Scale = getMemScale(MemMI);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1347 if (UpdateOffset % Scale != 0)
1348 break;
1349
1350 int ScaledOffset = UpdateOffset / Scale;
1351 if (ScaledOffset > 64 || ScaledOffset < -64)
1352 break;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1353 }
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1354
1355 // If we have a non-zero Offset, we check that it matches the amount
1356 // we're adding to the register.
1357 if (!Offset || Offset == MI->getOperand(2).getImm())
1358 return true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1359 break;
1360 }
1361 return false;
1362}
1363
1364MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1365 MachineBasicBlock::iterator I, int UnscaledOffset, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1366 MachineBasicBlock::iterator E = I->getParent()->end();
1367 MachineInstr *MemMI = I;
1368 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1369
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1370 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1371 int MIUnscaledOffset = getLdStOffsetOp(MemMI).getImm() * getMemScale(MemMI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1372
Chad Rosierb7c5b912015-10-01 13:43:05 +0000[diff] [blame]1373 // Scan forward looking for post-index opportunities. Updating instructions
1374 // can't be formed if the memory instruction doesn't have the offset we're
1375 // looking for.
1376 if (MIUnscaledOffset != UnscaledOffset)
1377 return E;
1378
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1379 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1380 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1381 bool IsPairedInsn = isPairedLdSt(MemMI);
1382 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1383 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1384 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1385 return E;
1386 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1387
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1388 // Track which registers have been modified and used between the first insn
1389 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1390 ModifiedRegs.reset();
1391 UsedRegs.reset();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1392 ++MBBI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1393 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1394 MachineInstr *MI = MBBI;
Chad Rosierb11c82d2016-01-19 21:27:05 +0000[diff] [blame]1395 // Skip DBG_VALUE instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1396 if (MI->isDebugValue())
1397 continue;
1398
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1399 // Now that we know this is a real instruction, count it.
1400 ++Count;
1401
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1402 // If we found a match, return it.
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1403 if (isMatchingUpdateInsn(I, MI, BaseReg, UnscaledOffset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1404 return MBBI;
1405
1406 // Update the status of what the instruction clobbered and used.
1407 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1408
1409 // Otherwise, if the base register is used or modified, we have no match, so
1410 // return early.
1411 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1412 return E;
1413 }
1414 return E;
1415}
1416
1417MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1418 MachineBasicBlock::iterator I, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1419 MachineBasicBlock::iterator B = I->getParent()->begin();
1420 MachineBasicBlock::iterator E = I->getParent()->end();
1421 MachineInstr *MemMI = I;
1422 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1423
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1424 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
1425 int Offset = getLdStOffsetOp(MemMI).getImm();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1426
1427 // If the load/store is the first instruction in the block, there's obviously
1428 // not any matching update. Ditto if the memory offset isn't zero.
1429 if (MBBI == B || Offset != 0)
1430 return E;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1431 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1432 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1433 bool IsPairedInsn = isPairedLdSt(MemMI);
1434 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1435 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1436 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1437 return E;
1438 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1439
1440 // Track which registers have been modified and used between the first insn
1441 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1442 ModifiedRegs.reset();
1443 UsedRegs.reset();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1444 --MBBI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1445 for (unsigned Count = 0; MBBI != B && Count < Limit; --MBBI) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1446 MachineInstr *MI = MBBI;
Chad Rosierb11c82d2016-01-19 21:27:05 +0000[diff] [blame]1447 // Skip DBG_VALUE instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1448 if (MI->isDebugValue())
1449 continue;
1450
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1451 // Now that we know this is a real instruction, count it.
1452 ++Count;
1453
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1454 // If we found a match, return it.
Chad Rosier11c825f2015-09-30 19:44:40 +0000[diff] [blame]1455 if (isMatchingUpdateInsn(I, MI, BaseReg, Offset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1456 return MBBI;
1457
1458 // Update the status of what the instruction clobbered and used.
1459 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1460
1461 // Otherwise, if the base register is used or modified, we have no match, so
1462 // return early.
1463 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1464 return E;
1465 }
1466 return E;
1467}
1468
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1469bool AArch64LoadStoreOpt::tryToPromoteLoadFromStore(
1470 MachineBasicBlock::iterator &MBBI) {
1471 MachineInstr *MI = MBBI;
1472 // If this is a volatile load, don't mess with it.
1473 if (MI->hasOrderedMemoryRef())
1474 return false;
1475
1476 // Make sure this is a reg+imm.
1477 // FIXME: It is possible to extend it to handle reg+reg cases.
1478 if (!getLdStOffsetOp(MI).isImm())
1479 return false;
1480
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1481 // Look backward up to LdStLimit instructions.
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1482 MachineBasicBlock::iterator StoreI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1483 if (findMatchingStore(MBBI, LdStLimit, StoreI)) {
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1484 ++NumLoadsFromStoresPromoted;
1485 // Promote the load. Keeping the iterator straight is a
1486 // pain, so we let the merge routine tell us what the next instruction
1487 // is after it's done mucking about.
1488 MBBI = promoteLoadFromStore(MBBI, StoreI);
1489 return true;
1490 }
1491 return false;
1492}
1493
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1494bool AArch64LoadStoreOpt::tryToMergeLdStInst(
1495 MachineBasicBlock::iterator &MBBI) {
1496 MachineInstr *MI = MBBI;
1497 MachineBasicBlock::iterator E = MI->getParent()->end();
1498 // If this is a volatile load/store, don't mess with it.
1499 if (MI->hasOrderedMemoryRef())
1500 return false;
1501
1502 // Make sure this is a reg+imm (as opposed to an address reloc).
1503 if (!getLdStOffsetOp(MI).isImm())
1504 return false;
1505
1506 // Check if this load/store has a hint to avoid pair formation.
1507 // MachineMemOperands hints are set by the AArch64StorePairSuppress pass.
1508 if (TII->isLdStPairSuppressed(MI))
1509 return false;
1510
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1511 // Look ahead up to LdStLimit instructions for a pairable instruction.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1512 LdStPairFlags Flags;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1513 MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, Flags, LdStLimit);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1514 if (Paired != E) {
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1515 if (isNarrowLoad(MI)) {
1516 ++NumNarrowLoadsPromoted;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1517 } else if (isNarrowStore(MI)) {
1518 ++NumZeroStoresPromoted;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1519 } else {
1520 ++NumPairCreated;
1521 if (isUnscaledLdSt(MI))
1522 ++NumUnscaledPairCreated;
1523 }
1524
1525 // Merge the loads into a pair. Keeping the iterator straight is a
1526 // pain, so we let the merge routine tell us what the next instruction
1527 // is after it's done mucking about.
1528 MBBI = mergePairedInsns(MBBI, Paired, Flags);
1529 return true;
1530 }
1531 return false;
1532}
1533
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1534bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
1535 bool enableNarrowLdOpt) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1536 bool Modified = false;
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1537 // Four tranformations to do here:
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1538 // 1) Find loads that directly read from stores and promote them by
1539 // replacing with mov instructions. If the store is wider than the load,
1540 // the load will be replaced with a bitfield extract.
1541 // e.g.,
1542 // str w1, [x0, #4]
1543 // ldrh w2, [x0, #6]
1544 // ; becomes
1545 // str w1, [x0, #4]
1546 // lsr w2, w1, #16
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1547 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1548 MBBI != E;) {
1549 MachineInstr *MI = MBBI;
1550 switch (MI->getOpcode()) {
1551 default:
1552 // Just move on to the next instruction.
1553 ++MBBI;
1554 break;
1555 // Scaled instructions.
1556 case AArch64::LDRBBui:
1557 case AArch64::LDRHHui:
1558 case AArch64::LDRWui:
1559 case AArch64::LDRXui:
1560 // Unscaled instructions.
1561 case AArch64::LDURBBi:
1562 case AArch64::LDURHHi:
1563 case AArch64::LDURWi:
1564 case AArch64::LDURXi: {
1565 if (tryToPromoteLoadFromStore(MBBI)) {
1566 Modified = true;
1567 break;
1568 }
1569 ++MBBI;
1570 break;
1571 }
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1572 }
1573 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1574 // 2) Find narrow loads that can be converted into a single wider load
1575 // with bitfield extract instructions.
1576 // e.g.,
1577 // ldrh w0, [x2]
1578 // ldrh w1, [x2, #2]
1579 // ; becomes
1580 // ldr w0, [x2]
1581 // ubfx w1, w0, #16, #16
1582 // and w0, w0, #ffff
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1583 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1584 enableNarrowLdOpt && MBBI != E;) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1585 MachineInstr *MI = MBBI;
1586 switch (MI->getOpcode()) {
1587 default:
1588 // Just move on to the next instruction.
1589 ++MBBI;
1590 break;
1591 // Scaled instructions.
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]1592 case AArch64::LDRBBui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1593 case AArch64::LDRHHui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]1594 case AArch64::LDRSBWui:
1595 case AArch64::LDRSHWui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1596 case AArch64::STRBBui:
1597 case AArch64::STRHHui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1598 // Unscaled instructions.
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]1599 case AArch64::LDURBBi:
1600 case AArch64::LDURHHi:
1601 case AArch64::LDURSBWi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1602 case AArch64::LDURSHWi:
1603 case AArch64::STURBBi:
1604 case AArch64::STURHHi: {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1605 if (tryToMergeLdStInst(MBBI)) {
1606 Modified = true;
1607 break;
1608 }
1609 ++MBBI;
1610 break;
1611 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1612 }
1613 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1614 // 3) Find loads and stores that can be merged into a single load or store
1615 // pair instruction.
1616 // e.g.,
1617 // ldr x0, [x2]
1618 // ldr x1, [x2, #8]
1619 // ; becomes
1620 // ldp x0, x1, [x2]
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1621 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1622 MBBI != E;) {
1623 MachineInstr *MI = MBBI;
1624 switch (MI->getOpcode()) {
1625 default:
1626 // Just move on to the next instruction.
1627 ++MBBI;
1628 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1629 // Scaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1630 case AArch64::STRSui:
1631 case AArch64::STRDui:
1632 case AArch64::STRQui:
1633 case AArch64::STRXui:
1634 case AArch64::STRWui:
1635 case AArch64::LDRSui:
1636 case AArch64::LDRDui:
1637 case AArch64::LDRQui:
1638 case AArch64::LDRXui:
1639 case AArch64::LDRWui:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]1640 case AArch64::LDRSWui:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1641 // Unscaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1642 case AArch64::STURSi:
1643 case AArch64::STURDi:
1644 case AArch64::STURQi:
1645 case AArch64::STURWi:
1646 case AArch64::STURXi:
1647 case AArch64::LDURSi:
1648 case AArch64::LDURDi:
1649 case AArch64::LDURQi:
1650 case AArch64::LDURWi:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]1651 case AArch64::LDURXi:
1652 case AArch64::LDURSWi: {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1653 if (tryToMergeLdStInst(MBBI)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1654 Modified = true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1655 break;
1656 }
1657 ++MBBI;
1658 break;
1659 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1660 }
1661 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1662 // 4) Find base register updates that can be merged into the load or store
1663 // as a base-reg writeback.
1664 // e.g.,
1665 // ldr x0, [x2]
1666 // add x2, x2, #4
1667 // ; becomes
1668 // ldr x0, [x2], #4
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1669 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1670 MBBI != E;) {
1671 MachineInstr *MI = MBBI;
1672 // Do update merging. It's simpler to keep this separate from the above
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1673 // switchs, though not strictly necessary.
Matthias Braunfa3872e2015-05-18 20:27:55 +0000[diff] [blame]1674 unsigned Opc = MI->getOpcode();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1675 switch (Opc) {
1676 default:
1677 // Just move on to the next instruction.
1678 ++MBBI;
1679 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1680 // Scaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1681 case AArch64::STRSui:
1682 case AArch64::STRDui:
1683 case AArch64::STRQui:
1684 case AArch64::STRXui:
1685 case AArch64::STRWui:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]1686 case AArch64::STRHHui:
1687 case AArch64::STRBBui:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1688 case AArch64::LDRSui:
1689 case AArch64::LDRDui:
1690 case AArch64::LDRQui:
1691 case AArch64::LDRXui:
1692 case AArch64::LDRWui:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]1693 case AArch64::LDRHHui:
1694 case AArch64::LDRBBui:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1695 // Unscaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1696 case AArch64::STURSi:
1697 case AArch64::STURDi:
1698 case AArch64::STURQi:
1699 case AArch64::STURWi:
1700 case AArch64::STURXi:
1701 case AArch64::LDURSi:
1702 case AArch64::LDURDi:
1703 case AArch64::LDURQi:
1704 case AArch64::LDURWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1705 case AArch64::LDURXi:
1706 // Paired instructions.
1707 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]1708 case AArch64::LDPSWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1709 case AArch64::LDPDi:
1710 case AArch64::LDPQi:
1711 case AArch64::LDPWi:
1712 case AArch64::LDPXi:
1713 case AArch64::STPSi:
1714 case AArch64::STPDi:
1715 case AArch64::STPQi:
1716 case AArch64::STPWi:
1717 case AArch64::STPXi: {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1718 // Make sure this is a reg+imm (as opposed to an address reloc).
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1719 if (!getLdStOffsetOp(MI).isImm()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1720 ++MBBI;
1721 break;
1722 }
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1723 // Look forward to try to form a post-index instruction. For example,
1724 // ldr x0, [x20]
1725 // add x20, x20, #32
1726 // merged into:
1727 // ldr x0, [x20], #32
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1728 MachineBasicBlock::iterator Update =
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1729 findMatchingUpdateInsnForward(MBBI, 0, UpdateLimit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1730 if (Update != E) {
1731 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1732 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/false);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1733 Modified = true;
1734 ++NumPostFolded;
1735 break;
1736 }
1737 // Don't know how to handle pre/post-index versions, so move to the next
1738 // instruction.
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]1739 if (isUnscaledLdSt(Opc)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1740 ++MBBI;
1741 break;
1742 }
1743
1744 // Look back to try to find a pre-index instruction. For example,
1745 // add x0, x0, #8
1746 // ldr x1, [x0]
1747 // merged into:
1748 // ldr x1, [x0, #8]!
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1749 Update = findMatchingUpdateInsnBackward(MBBI, UpdateLimit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1750 if (Update != E) {
1751 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1752 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1753 Modified = true;
1754 ++NumPreFolded;
1755 break;
1756 }
Chad Rosier7a83d772015-10-01 13:09:44 +0000[diff] [blame]1757 // The immediate in the load/store is scaled by the size of the memory
1758 // operation. The immediate in the add we're looking for,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1759 // however, is not, so adjust here.
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1760 int UnscaledOffset = getLdStOffsetOp(MI).getImm() * getMemScale(MI);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1761
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1762 // Look forward to try to find a post-index instruction. For example,
1763 // ldr x1, [x0, #64]
1764 // add x0, x0, #64
1765 // merged into:
1766 // ldr x1, [x0, #64]!
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1767 Update = findMatchingUpdateInsnForward(MBBI, UnscaledOffset, UpdateLimit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1768 if (Update != E) {
1769 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1770 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1771 Modified = true;
1772 ++NumPreFolded;
1773 break;
1774 }
1775
1776 // Nothing found. Just move to the next instruction.
1777 ++MBBI;
1778 break;
1779 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1780 }
1781 }
1782
1783 return Modified;
1784}
1785
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1786bool AArch64LoadStoreOpt::enableNarrowLdMerge(MachineFunction &Fn) {
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1787 bool ProfitableArch = Subtarget->isCortexA57();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1788 // FIXME: The benefit from converting narrow loads into a wider load could be
1789 // microarchitectural as it assumes that a single load with two bitfield
1790 // extracts is cheaper than two narrow loads. Currently, this conversion is
1791 // enabled only in cortex-a57 on which performance benefits were verified.
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1792 return ProfitableArch && !Subtarget->requiresStrictAlign();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1793}
1794
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1795bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]1796 Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
1797 TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
1798 TRI = Subtarget->getRegisterInfo();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1799
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1800 // Resize the modified and used register bitfield trackers. We do this once
1801 // per function and then clear the bitfield each time we optimize a load or
1802 // store.
1803 ModifiedRegs.resize(TRI->getNumRegs());
1804 UsedRegs.resize(TRI->getNumRegs());
1805
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1806 bool Modified = false;
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1807 bool enableNarrowLdOpt = enableNarrowLdMerge(Fn);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1808 for (auto &MBB : Fn)
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1809 Modified |= optimizeBlock(MBB, enableNarrowLdOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1810
1811 return Modified;
1812}
1813
1814// FIXME: Do we need/want a pre-alloc pass like ARM has to try to keep
1815// loads and stores near one another?
1816
Chad Rosier43f5c842015-08-05 12:40:13 +0000[diff] [blame]1817/// createAArch64LoadStoreOptimizationPass - returns an instance of the
1818/// load / store optimization pass.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1819FunctionPass *llvm::createAArch64LoadStoreOptimizationPass() {
1820 return new AArch64LoadStoreOpt();
1821}