Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 4fbe351817fc05214ff7a360af3601ef40d1941f / . / llvm / lib / Target / X86 / InstPrinter / X86InstComments.cpp
blob: f5f3a4cc83dc9f10333d343539cb2f6aa66204db [file] [log] [blame]
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This defines functionality used to emit comments about X86 instructions to
11// an output stream for -fverbose-asm.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86InstComments.h"
16#include "MCTargetDesc/X86MCTargetDesc.h"
17#include "Utils/X86ShuffleDecode.h"
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]18#include "llvm/CodeGen/MachineValueType.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]20#include "llvm/Support/raw_ostream.h"
21
22using namespace llvm;
23
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]24#define CASE_SSE_INS_COMMON(Inst, src) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]25 case X86::Inst##src:
26
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]27#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]28 case X86::V##Inst##Suffix##src:
29
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]30#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
31 case X86::V##Inst##Suffix##src##k:
32
33#define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \
34 case X86::V##Inst##Suffix##src##kz:
35
36#define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
37 CASE_AVX_INS_COMMON(Inst, Suffix, src) \
38 CASE_MASK_INS_COMMON(Inst, Suffix, src) \
39 CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
40
41#define CASE_MOVDUP(Inst, src) \
42 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
43 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
44 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
45 CASE_AVX_INS_COMMON(Inst, , r##src) \
46 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]47 CASE_SSE_INS_COMMON(Inst, r##src)
48
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]49#define CASE_MASK_MOVDUP(Inst, src) \
50 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
51 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
52 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
53
54#define CASE_MASKZ_MOVDUP(Inst, src) \
55 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
56 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
57 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
58
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]59#define CASE_PMOVZX(Inst, src) \
60 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
61 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
62 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
63 CASE_AVX_INS_COMMON(Inst, , r##src) \
64 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]65 CASE_SSE_INS_COMMON(Inst, r##src)
66
Simon Pilgrim68f438a2016-07-03 13:33:28 +0000[diff] [blame]67#define CASE_MASK_PMOVZX(Inst, src) \
68 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
69 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
70 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
71
72#define CASE_MASKZ_PMOVZX(Inst, src) \
73 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
74 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
75 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
76
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]77#define CASE_UNPCK(Inst, src) \
78 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
79 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
80 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
81 CASE_AVX_INS_COMMON(Inst, , r##src) \
82 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]83 CASE_SSE_INS_COMMON(Inst, r##src)
84
Simon Pilgrim598bdb62016-07-03 14:26:21 +0000[diff] [blame]85#define CASE_MASK_UNPCK(Inst, src) \
86 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
87 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
88 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
89
90#define CASE_MASKZ_UNPCK(Inst, src) \
91 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
92 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
93 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
94
95#define CASE_SHUF(Inst, suf) \
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]96 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
97 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
98 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \
99 CASE_AVX_INS_COMMON(Inst, , suf) \
100 CASE_AVX_INS_COMMON(Inst, Y, suf) \
101 CASE_SSE_INS_COMMON(Inst, suf)
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]102
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]103#define CASE_MASK_SHUF(Inst, src) \
104 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
105 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
106 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
107
108#define CASE_MASKZ_SHUF(Inst, src) \
109 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \
110 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \
111 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
112
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]113#define CASE_VPERMILPI(Inst, src) \
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]114 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
115 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
116 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \
117 CASE_AVX_INS_COMMON(Inst, , src##i) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]118 CASE_AVX_INS_COMMON(Inst, Y, src##i)
119
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]120#define CASE_MASK_VPERMILPI(Inst, src) \
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]121 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
122 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
123 CASE_MASK_INS_COMMON(Inst, Z128, src##i)
124
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]125#define CASE_MASKZ_VPERMILPI(Inst, src) \
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]126 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
127 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \
128 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
129
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]130#define CASE_VPERM(Inst, src) \
131 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
132 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
133 CASE_AVX_INS_COMMON(Inst, Y, src##i)
134
Simon Pilgrim68ea8062016-07-03 18:40:24 +0000[diff] [blame]135#define CASE_MASK_VPERM(Inst, src) \
136 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
137 CASE_MASK_INS_COMMON(Inst, Z256, src##i)
138
139#define CASE_MASKZ_VPERM(Inst, src) \
140 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
141 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
142
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]143#define CASE_VSHUF(Inst, src) \
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]144 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
145 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
146 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
147 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]148
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]149#define CASE_MASK_VSHUF(Inst, src) \
150 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
151 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
152 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
153 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
154
155#define CASE_MASKZ_VSHUF(Inst, src) \
156 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
157 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
158 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
159 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
160
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]161static unsigned getVectorRegSize(unsigned RegNo) {
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]162 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
163 return 512;
164 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
165 return 256;
166 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
167 return 128;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]168 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
169 return 64;
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]170
171 llvm_unreachable("Unknown vector reg!");
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]172}
173
174static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
175 unsigned OperandIndex) {
176 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
177 return MVT::getVectorVT(ScalarVT,
178 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
179}
180
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]181/// \brief Extracts the dst type for a given zero extension instruction.
182static MVT getZeroExtensionResultType(const MCInst *MI) {
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]183 switch (MI->getOpcode()) {
184 default:
185 llvm_unreachable("Unknown zero extension instruction");
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]186 // zero extension to i16
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]187 CASE_PMOVZX(PMOVZXBW, m)
188 CASE_PMOVZX(PMOVZXBW, r)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]189 return getRegOperandVectorVT(MI, MVT::i16, 0);
190 // zero extension to i32
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]191 CASE_PMOVZX(PMOVZXBD, m)
192 CASE_PMOVZX(PMOVZXBD, r)
193 CASE_PMOVZX(PMOVZXWD, m)
194 CASE_PMOVZX(PMOVZXWD, r)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]195 return getRegOperandVectorVT(MI, MVT::i32, 0);
196 // zero extension to i64
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]197 CASE_PMOVZX(PMOVZXBQ, m)
198 CASE_PMOVZX(PMOVZXBQ, r)
199 CASE_PMOVZX(PMOVZXWQ, m)
200 CASE_PMOVZX(PMOVZXWQ, r)
201 CASE_PMOVZX(PMOVZXDQ, m)
202 CASE_PMOVZX(PMOVZXDQ, r)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]203 return getRegOperandVectorVT(MI, MVT::i64, 0);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]204 }
205}
206
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]207/// Wraps the destination register name with AVX512 mask/maskz filtering.
208static std::string getMaskName(const MCInst *MI, const char *DestName,
209 const char *(*getRegName)(unsigned)) {
210 std::string OpMaskName(DestName);
211
212 bool MaskWithZero = false;
213 const char *MaskRegName = nullptr;
214
215 switch (MI->getOpcode()) {
216 default:
217 return OpMaskName;
218 CASE_MASKZ_MOVDUP(MOVDDUP, m)
219 CASE_MASKZ_MOVDUP(MOVDDUP, r)
220 CASE_MASKZ_MOVDUP(MOVSHDUP, m)
221 CASE_MASKZ_MOVDUP(MOVSHDUP, r)
222 CASE_MASKZ_MOVDUP(MOVSLDUP, m)
223 CASE_MASKZ_MOVDUP(MOVSLDUP, r)
Simon Pilgrim68f438a2016-07-03 13:33:28 +0000[diff] [blame]224 CASE_MASKZ_PMOVZX(PMOVZXBD, m)
225 CASE_MASKZ_PMOVZX(PMOVZXBD, r)
226 CASE_MASKZ_PMOVZX(PMOVZXBQ, m)
227 CASE_MASKZ_PMOVZX(PMOVZXBQ, r)
228 CASE_MASKZ_PMOVZX(PMOVZXBW, m)
229 CASE_MASKZ_PMOVZX(PMOVZXBW, r)
230 CASE_MASKZ_PMOVZX(PMOVZXDQ, m)
231 CASE_MASKZ_PMOVZX(PMOVZXDQ, r)
232 CASE_MASKZ_PMOVZX(PMOVZXWD, m)
233 CASE_MASKZ_PMOVZX(PMOVZXWD, r)
234 CASE_MASKZ_PMOVZX(PMOVZXWQ, m)
235 CASE_MASKZ_PMOVZX(PMOVZXWQ, r)
Simon Pilgrim598bdb62016-07-03 14:26:21 +0000[diff] [blame]236 CASE_MASKZ_UNPCK(PUNPCKHBW, m)
237 CASE_MASKZ_UNPCK(PUNPCKHBW, r)
238 CASE_MASKZ_UNPCK(PUNPCKHWD, m)
239 CASE_MASKZ_UNPCK(PUNPCKHWD, r)
240 CASE_MASKZ_UNPCK(PUNPCKHDQ, m)
241 CASE_MASKZ_UNPCK(PUNPCKHDQ, r)
242 CASE_MASKZ_UNPCK(PUNPCKLBW, m)
243 CASE_MASKZ_UNPCK(PUNPCKLBW, r)
244 CASE_MASKZ_UNPCK(PUNPCKLWD, m)
245 CASE_MASKZ_UNPCK(PUNPCKLWD, r)
246 CASE_MASKZ_UNPCK(PUNPCKLDQ, m)
247 CASE_MASKZ_UNPCK(PUNPCKLDQ, r)
248 CASE_MASKZ_UNPCK(UNPCKHPD, m)
249 CASE_MASKZ_UNPCK(UNPCKHPD, r)
250 CASE_MASKZ_UNPCK(UNPCKHPS, m)
251 CASE_MASKZ_UNPCK(UNPCKHPS, r)
252 CASE_MASKZ_UNPCK(UNPCKLPD, m)
253 CASE_MASKZ_UNPCK(UNPCKLPD, r)
254 CASE_MASKZ_UNPCK(UNPCKLPS, m)
255 CASE_MASKZ_UNPCK(UNPCKLPS, r)
Simon Pilgrimdbd6db02016-07-03 15:00:51 +0000[diff] [blame]256 CASE_MASKZ_SHUF(PALIGNR, r)
257 CASE_MASKZ_SHUF(PALIGNR, m)
Craig Topperb084c902016-10-22 06:51:56 +0000[diff] [blame]258 CASE_MASKZ_SHUF(ALIGNQ, r)
259 CASE_MASKZ_SHUF(ALIGNQ, m)
260 CASE_MASKZ_SHUF(ALIGND, r)
261 CASE_MASKZ_SHUF(ALIGND, m)
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]262 CASE_MASKZ_SHUF(SHUFPD, m)
263 CASE_MASKZ_SHUF(SHUFPD, r)
264 CASE_MASKZ_SHUF(SHUFPS, m)
265 CASE_MASKZ_SHUF(SHUFPS, r)
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]266 CASE_MASKZ_VPERMILPI(PERMILPD, m)
267 CASE_MASKZ_VPERMILPI(PERMILPD, r)
268 CASE_MASKZ_VPERMILPI(PERMILPS, m)
269 CASE_MASKZ_VPERMILPI(PERMILPS, r)
270 CASE_MASKZ_VPERMILPI(PSHUFD, m)
271 CASE_MASKZ_VPERMILPI(PSHUFD, r)
272 CASE_MASKZ_VPERMILPI(PSHUFHW, m)
273 CASE_MASKZ_VPERMILPI(PSHUFHW, r)
274 CASE_MASKZ_VPERMILPI(PSHUFLW, m)
275 CASE_MASKZ_VPERMILPI(PSHUFLW, r)
Simon Pilgrim68ea8062016-07-03 18:40:24 +0000[diff] [blame]276 CASE_MASKZ_VPERM(PERMPD, m)
277 CASE_MASKZ_VPERM(PERMPD, r)
278 CASE_MASKZ_VPERM(PERMQ, m)
279 CASE_MASKZ_VPERM(PERMQ, r)
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]280 CASE_MASKZ_VSHUF(64X2, m)
281 CASE_MASKZ_VSHUF(64X2, r)
282 CASE_MASKZ_VSHUF(32X4, m)
283 CASE_MASKZ_VSHUF(32X4, r)
Simon Pilgrim32b06232016-10-21 12:14:24 +0000[diff] [blame]284 CASE_MASKZ_INS_COMMON(BROADCASTF64X2, Z128, rm)
285 CASE_MASKZ_INS_COMMON(BROADCASTI64X2, Z128, rm)
286 CASE_MASKZ_INS_COMMON(BROADCASTF64X2, , rm)
287 CASE_MASKZ_INS_COMMON(BROADCASTI64X2, , rm)
288 CASE_MASKZ_INS_COMMON(BROADCASTF64X4, , rm)
289 CASE_MASKZ_INS_COMMON(BROADCASTI64X4, , rm)
290 CASE_MASKZ_INS_COMMON(BROADCASTF32X4, Z256, rm)
291 CASE_MASKZ_INS_COMMON(BROADCASTI32X4, Z256, rm)
292 CASE_MASKZ_INS_COMMON(BROADCASTF32X4, , rm)
293 CASE_MASKZ_INS_COMMON(BROADCASTI32X4, , rm)
294 CASE_MASKZ_INS_COMMON(BROADCASTF32X8, , rm)
295 CASE_MASKZ_INS_COMMON(BROADCASTI32X8, , rm)
296 CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, r)
297 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, r)
298 CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, m)
299 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, m)
300 CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, r)
301 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, r)
302 CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, m)
303 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, m)
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]304 MaskWithZero = true;
305 MaskRegName = getRegName(MI->getOperand(1).getReg());
306 break;
307 CASE_MASK_MOVDUP(MOVDDUP, m)
308 CASE_MASK_MOVDUP(MOVDDUP, r)
309 CASE_MASK_MOVDUP(MOVSHDUP, m)
310 CASE_MASK_MOVDUP(MOVSHDUP, r)
311 CASE_MASK_MOVDUP(MOVSLDUP, m)
312 CASE_MASK_MOVDUP(MOVSLDUP, r)
Simon Pilgrim68f438a2016-07-03 13:33:28 +0000[diff] [blame]313 CASE_MASK_PMOVZX(PMOVZXBD, m)
314 CASE_MASK_PMOVZX(PMOVZXBD, r)
315 CASE_MASK_PMOVZX(PMOVZXBQ, m)
316 CASE_MASK_PMOVZX(PMOVZXBQ, r)
317 CASE_MASK_PMOVZX(PMOVZXBW, m)
318 CASE_MASK_PMOVZX(PMOVZXBW, r)
319 CASE_MASK_PMOVZX(PMOVZXDQ, m)
320 CASE_MASK_PMOVZX(PMOVZXDQ, r)
321 CASE_MASK_PMOVZX(PMOVZXWD, m)
322 CASE_MASK_PMOVZX(PMOVZXWD, r)
323 CASE_MASK_PMOVZX(PMOVZXWQ, m)
324 CASE_MASK_PMOVZX(PMOVZXWQ, r)
Simon Pilgrim598bdb62016-07-03 14:26:21 +0000[diff] [blame]325 CASE_MASK_UNPCK(PUNPCKHBW, m)
326 CASE_MASK_UNPCK(PUNPCKHBW, r)
327 CASE_MASK_UNPCK(PUNPCKHWD, m)
328 CASE_MASK_UNPCK(PUNPCKHWD, r)
329 CASE_MASK_UNPCK(PUNPCKHDQ, m)
330 CASE_MASK_UNPCK(PUNPCKHDQ, r)
331 CASE_MASK_UNPCK(PUNPCKLBW, m)
332 CASE_MASK_UNPCK(PUNPCKLBW, r)
333 CASE_MASK_UNPCK(PUNPCKLWD, m)
334 CASE_MASK_UNPCK(PUNPCKLWD, r)
335 CASE_MASK_UNPCK(PUNPCKLDQ, m)
336 CASE_MASK_UNPCK(PUNPCKLDQ, r)
337 CASE_MASK_UNPCK(UNPCKHPD, m)
338 CASE_MASK_UNPCK(UNPCKHPD, r)
339 CASE_MASK_UNPCK(UNPCKHPS, m)
340 CASE_MASK_UNPCK(UNPCKHPS, r)
341 CASE_MASK_UNPCK(UNPCKLPD, m)
342 CASE_MASK_UNPCK(UNPCKLPD, r)
343 CASE_MASK_UNPCK(UNPCKLPS, m)
344 CASE_MASK_UNPCK(UNPCKLPS, r)
Simon Pilgrimdbd6db02016-07-03 15:00:51 +0000[diff] [blame]345 CASE_MASK_SHUF(PALIGNR, r)
346 CASE_MASK_SHUF(PALIGNR, m)
Craig Topperb084c902016-10-22 06:51:56 +0000[diff] [blame]347 CASE_MASK_SHUF(ALIGNQ, r)
348 CASE_MASK_SHUF(ALIGNQ, m)
349 CASE_MASK_SHUF(ALIGND, r)
350 CASE_MASK_SHUF(ALIGND, m)
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]351 CASE_MASK_SHUF(SHUFPD, m)
352 CASE_MASK_SHUF(SHUFPD, r)
353 CASE_MASK_SHUF(SHUFPS, m)
354 CASE_MASK_SHUF(SHUFPS, r)
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]355 CASE_MASK_VPERMILPI(PERMILPD, m)
356 CASE_MASK_VPERMILPI(PERMILPD, r)
357 CASE_MASK_VPERMILPI(PERMILPS, m)
358 CASE_MASK_VPERMILPI(PERMILPS, r)
359 CASE_MASK_VPERMILPI(PSHUFD, m)
360 CASE_MASK_VPERMILPI(PSHUFD, r)
361 CASE_MASK_VPERMILPI(PSHUFHW, m)
362 CASE_MASK_VPERMILPI(PSHUFHW, r)
363 CASE_MASK_VPERMILPI(PSHUFLW, m)
364 CASE_MASK_VPERMILPI(PSHUFLW, r)
Simon Pilgrim68ea8062016-07-03 18:40:24 +0000[diff] [blame]365 CASE_MASK_VPERM(PERMPD, m)
366 CASE_MASK_VPERM(PERMPD, r)
367 CASE_MASK_VPERM(PERMQ, m)
368 CASE_MASK_VPERM(PERMQ, r)
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]369 CASE_MASK_VSHUF(64X2, m)
370 CASE_MASK_VSHUF(64X2, r)
371 CASE_MASK_VSHUF(32X4, m)
372 CASE_MASK_VSHUF(32X4, r)
Simon Pilgrim32b06232016-10-21 12:14:24 +0000[diff] [blame]373 CASE_MASK_INS_COMMON(BROADCASTF64X2, Z128, rm)
374 CASE_MASK_INS_COMMON(BROADCASTI64X2, Z128, rm)
375 CASE_MASK_INS_COMMON(BROADCASTF64X2, , rm)
376 CASE_MASK_INS_COMMON(BROADCASTI64X2, , rm)
377 CASE_MASK_INS_COMMON(BROADCASTF64X4, , rm)
378 CASE_MASK_INS_COMMON(BROADCASTI64X4, , rm)
379 CASE_MASK_INS_COMMON(BROADCASTF32X4, Z256, rm)
380 CASE_MASK_INS_COMMON(BROADCASTI32X4, Z256, rm)
381 CASE_MASK_INS_COMMON(BROADCASTF32X4, , rm)
382 CASE_MASK_INS_COMMON(BROADCASTI32X4, , rm)
383 CASE_MASK_INS_COMMON(BROADCASTF32X8, , rm)
384 CASE_MASK_INS_COMMON(BROADCASTI32X8, , rm)
385 CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, r)
386 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, r)
387 CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, m)
388 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, m)
389 CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, r)
390 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, r)
391 CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, m)
392 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, m)
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]393 MaskRegName = getRegName(MI->getOperand(2).getReg());
394 break;
395 }
396
397 // MASK: zmmX {%kY}
398 OpMaskName += " {%";
399 OpMaskName += MaskRegName;
400 OpMaskName += "}";
401
402 // MASKZ: zmmX {%kY} {z}
403 if (MaskWithZero)
404 OpMaskName += " {z}";
405
406 return OpMaskName;
407}
408
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]409//===----------------------------------------------------------------------===//
410// Top Level Entrypoint
411//===----------------------------------------------------------------------===//
412
413/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
414/// newline terminated strings to the specified string if desired. This
415/// information is shown in disassembly dumps when verbose assembly is enabled.
416bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
417 const char *(*getRegName)(unsigned)) {
418 // If this is a shuffle operation, the switch should fill in this state.
419 SmallVector<int, 8> ShuffleMask;
420 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]421 unsigned NumOperands = MI->getNumOperands();
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]422 bool RegForm = false;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]423
424 switch (MI->getOpcode()) {
425 default:
426 // Not an instruction for which we can decode comments.
427 return false;
428
429 case X86::BLENDPDrri:
430 case X86::VBLENDPDrri:
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]431 case X86::VBLENDPDYrri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]432 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]433 LLVM_FALLTHROUGH;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]434 case X86::BLENDPDrmi:
435 case X86::VBLENDPDrmi:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]436 case X86::VBLENDPDYrmi:
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]437 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]438 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]439 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]440 ShuffleMask);
441 Src1Name = getRegName(MI->getOperand(1).getReg());
442 DestName = getRegName(MI->getOperand(0).getReg());
443 break;
444
445 case X86::BLENDPSrri:
446 case X86::VBLENDPSrri:
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]447 case X86::VBLENDPSYrri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]448 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]449 LLVM_FALLTHROUGH;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]450 case X86::BLENDPSrmi:
451 case X86::VBLENDPSrmi:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]452 case X86::VBLENDPSYrmi:
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]453 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]454 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]455 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]456 ShuffleMask);
457 Src1Name = getRegName(MI->getOperand(1).getReg());
458 DestName = getRegName(MI->getOperand(0).getReg());
459 break;
460
461 case X86::PBLENDWrri:
462 case X86::VPBLENDWrri:
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]463 case X86::VPBLENDWYrri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]464 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]465 LLVM_FALLTHROUGH;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]466 case X86::PBLENDWrmi:
467 case X86::VPBLENDWrmi:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]468 case X86::VPBLENDWYrmi:
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]469 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]470 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]471 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]472 ShuffleMask);
473 Src1Name = getRegName(MI->getOperand(1).getReg());
474 DestName = getRegName(MI->getOperand(0).getReg());
475 break;
476
477 case X86::VPBLENDDrri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]478 case X86::VPBLENDDYrri:
479 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]480 LLVM_FALLTHROUGH;
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]481 case X86::VPBLENDDrmi:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]482 case X86::VPBLENDDYrmi:
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]483 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]484 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]485 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]486 ShuffleMask);
487 Src1Name = getRegName(MI->getOperand(1).getReg());
488 DestName = getRegName(MI->getOperand(0).getReg());
489 break;
490
491 case X86::INSERTPSrr:
492 case X86::VINSERTPSrr:
Craig Topper6189d3e2016-07-19 01:26:19 +0000[diff] [blame]493 case X86::VINSERTPSZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]494 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]495 LLVM_FALLTHROUGH;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]496 case X86::INSERTPSrm:
497 case X86::VINSERTPSrm:
Craig Topper6189d3e2016-07-19 01:26:19 +0000[diff] [blame]498 case X86::VINSERTPSZrm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]499 DestName = getRegName(MI->getOperand(0).getReg());
500 Src1Name = getRegName(MI->getOperand(1).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]501 if (MI->getOperand(NumOperands - 1).isImm())
502 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]503 ShuffleMask);
504 break;
505
506 case X86::MOVLHPSrr:
507 case X86::VMOVLHPSrr:
Simon Pilgrimd5a15442015-11-21 13:04:42 +0000[diff] [blame]508 case X86::VMOVLHPSZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]509 Src2Name = getRegName(MI->getOperand(2).getReg());
510 Src1Name = getRegName(MI->getOperand(1).getReg());
511 DestName = getRegName(MI->getOperand(0).getReg());
512 DecodeMOVLHPSMask(2, ShuffleMask);
513 break;
514
515 case X86::MOVHLPSrr:
516 case X86::VMOVHLPSrr:
Simon Pilgrimd5a15442015-11-21 13:04:42 +0000[diff] [blame]517 case X86::VMOVHLPSZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]518 Src2Name = getRegName(MI->getOperand(2).getReg());
519 Src1Name = getRegName(MI->getOperand(1).getReg());
520 DestName = getRegName(MI->getOperand(0).getReg());
521 DecodeMOVHLPSMask(2, ShuffleMask);
522 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]523
Simon Pilgrima3d67442016-02-07 15:39:22 +0000[diff] [blame]524 case X86::MOVHPDrm:
525 case X86::VMOVHPDrm:
526 case X86::VMOVHPDZ128rm:
527 Src1Name = getRegName(MI->getOperand(1).getReg());
528 DestName = getRegName(MI->getOperand(0).getReg());
529 DecodeInsertElementMask(MVT::v2f64, 1, 1, ShuffleMask);
530 break;
531
532 case X86::MOVHPSrm:
533 case X86::VMOVHPSrm:
534 case X86::VMOVHPSZ128rm:
535 Src1Name = getRegName(MI->getOperand(1).getReg());
536 DestName = getRegName(MI->getOperand(0).getReg());
537 DecodeInsertElementMask(MVT::v4f32, 2, 2, ShuffleMask);
538 break;
539
540 case X86::MOVLPDrm:
541 case X86::VMOVLPDrm:
542 case X86::VMOVLPDZ128rm:
543 Src1Name = getRegName(MI->getOperand(1).getReg());
544 DestName = getRegName(MI->getOperand(0).getReg());
545 DecodeInsertElementMask(MVT::v2f64, 0, 1, ShuffleMask);
546 break;
547
548 case X86::MOVLPSrm:
549 case X86::VMOVLPSrm:
550 case X86::VMOVLPSZ128rm:
551 Src1Name = getRegName(MI->getOperand(1).getReg());
552 DestName = getRegName(MI->getOperand(0).getReg());
553 DecodeInsertElementMask(MVT::v4f32, 0, 2, ShuffleMask);
554 break;
555
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]556 CASE_MOVDUP(MOVSLDUP, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]557 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]558 LLVM_FALLTHROUGH;
559
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]560 CASE_MOVDUP(MOVSLDUP, m)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]561 DestName = getRegName(MI->getOperand(0).getReg());
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]562 DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]563 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]564
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]565 CASE_MOVDUP(MOVSHDUP, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]566 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]567 LLVM_FALLTHROUGH;
568
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]569 CASE_MOVDUP(MOVSHDUP, m)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]570 DestName = getRegName(MI->getOperand(0).getReg());
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]571 DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]572 break;
573
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]574 CASE_MOVDUP(MOVDDUP, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]575 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]576 LLVM_FALLTHROUGH;
577
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]578 CASE_MOVDUP(MOVDDUP, m)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]579 DestName = getRegName(MI->getOperand(0).getReg());
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]580 DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]581 break;
582
583 case X86::PSLLDQri:
584 case X86::VPSLLDQri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]585 case X86::VPSLLDQYri:
Simon Pilgrim643734c2016-06-09 22:03:15 +0000[diff] [blame]586 case X86::VPSLLDQZ128rr:
587 case X86::VPSLLDQZ256rr:
588 case X86::VPSLLDQZ512rr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]589 Src1Name = getRegName(MI->getOperand(1).getReg());
Galina Kistanovab2c01162017-05-31 19:41:33 +0000[diff] [blame]590 LLVM_FALLTHROUGH;
Simon Pilgrim643734c2016-06-09 22:03:15 +0000[diff] [blame]591 case X86::VPSLLDQZ128rm:
592 case X86::VPSLLDQZ256rm:
593 case X86::VPSLLDQZ512rm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]594 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]595 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrimb9ada272015-11-16 22:54:41 +0000[diff] [blame]596 DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]597 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]598 ShuffleMask);
599 break;
600
601 case X86::PSRLDQri:
602 case X86::VPSRLDQri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]603 case X86::VPSRLDQYri:
Simon Pilgrim643734c2016-06-09 22:03:15 +0000[diff] [blame]604 case X86::VPSRLDQZ128rr:
605 case X86::VPSRLDQZ256rr:
606 case X86::VPSRLDQZ512rr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]607 Src1Name = getRegName(MI->getOperand(1).getReg());
Galina Kistanovab2c01162017-05-31 19:41:33 +0000[diff] [blame]608 LLVM_FALLTHROUGH;
Simon Pilgrim643734c2016-06-09 22:03:15 +0000[diff] [blame]609 case X86::VPSRLDQZ128rm:
610 case X86::VPSRLDQZ256rm:
611 case X86::VPSRLDQZ512rm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]612 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]613 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrimb9ada272015-11-16 22:54:41 +0000[diff] [blame]614 DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]615 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]616 ShuffleMask);
617 break;
618
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]619 CASE_SHUF(PALIGNR, rri)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]620 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
621 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]622 LLVM_FALLTHROUGH;
623
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]624 CASE_SHUF(PALIGNR, rmi)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]625 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]626 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]627 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrimb9ada272015-11-16 22:54:41 +0000[diff] [blame]628 DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]629 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]630 ShuffleMask);
631 break;
632
Craig Topperb084c902016-10-22 06:51:56 +0000[diff] [blame]633 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
634 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
635 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
636 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
637 RegForm = true;
638 LLVM_FALLTHROUGH;
639
640 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
641 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
642 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
643 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
644 DestName = getRegName(MI->getOperand(0).getReg());
645 if (MI->getOperand(NumOperands - 1).isImm())
646 DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i64, 0),
647 MI->getOperand(NumOperands - 1).getImm(),
648 ShuffleMask);
649 break;
650
651 CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
652 CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
653 CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
654 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
655 RegForm = true;
656 LLVM_FALLTHROUGH;
657
658 CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
659 CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
660 CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
661 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
662 DestName = getRegName(MI->getOperand(0).getReg());
663 if (MI->getOperand(NumOperands - 1).isImm())
664 DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i32, 0),
665 MI->getOperand(NumOperands - 1).getImm(),
666 ShuffleMask);
667 break;
668
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]669 CASE_SHUF(PSHUFD, ri)
Craig Topper6f7288d2016-06-09 07:49:08 +0000[diff] [blame]670 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]671 LLVM_FALLTHROUGH;
672
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]673 CASE_SHUF(PSHUFD, mi)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]674 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]675 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]676 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]677 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]678 ShuffleMask);
679 break;
680
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]681 CASE_SHUF(PSHUFHW, ri)
Craig Topper6f7288d2016-06-09 07:49:08 +0000[diff] [blame]682 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]683 LLVM_FALLTHROUGH;
684
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]685 CASE_SHUF(PSHUFHW, mi)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]686 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]687 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]688 DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]689 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]690 ShuffleMask);
691 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]692
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]693 CASE_SHUF(PSHUFLW, ri)
Craig Topper6f7288d2016-06-09 07:49:08 +0000[diff] [blame]694 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]695 LLVM_FALLTHROUGH;
696
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]697 CASE_SHUF(PSHUFLW, mi)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]698 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]699 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]700 DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]701 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]702 ShuffleMask);
703 break;
704
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]705 case X86::MMX_PSHUFWri:
706 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]707 LLVM_FALLTHROUGH;
708
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]709 case X86::MMX_PSHUFWmi:
710 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]711 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]712 DecodePSHUFMask(MVT::v4i16,
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]713 MI->getOperand(NumOperands - 1).getImm(),
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]714 ShuffleMask);
715 break;
716
717 case X86::PSWAPDrr:
718 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]719 LLVM_FALLTHROUGH;
720
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]721 case X86::PSWAPDrm:
722 DestName = getRegName(MI->getOperand(0).getReg());
723 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
724 break;
725
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]726 CASE_UNPCK(PUNPCKHBW, r)
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]727 case X86::MMX_PUNPCKHBWirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]728 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
729 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]730 LLVM_FALLTHROUGH;
731
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]732 CASE_UNPCK(PUNPCKHBW, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]733 case X86::MMX_PUNPCKHBWirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]734 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]735 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]736 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]737 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]738
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]739 CASE_UNPCK(PUNPCKHWD, r)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]740 case X86::MMX_PUNPCKHWDirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]741 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
742 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]743 LLVM_FALLTHROUGH;
744
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]745 CASE_UNPCK(PUNPCKHWD, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]746 case X86::MMX_PUNPCKHWDirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]747 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]748 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]749 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]750 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]751
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]752 CASE_UNPCK(PUNPCKHDQ, r)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]753 case X86::MMX_PUNPCKHDQirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]754 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
755 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]756 LLVM_FALLTHROUGH;
757
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]758 CASE_UNPCK(PUNPCKHDQ, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]759 case X86::MMX_PUNPCKHDQirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]760 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]761 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]762 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]763 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]764
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]765 CASE_UNPCK(PUNPCKHQDQ, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]766 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
767 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]768 LLVM_FALLTHROUGH;
769
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]770 CASE_UNPCK(PUNPCKHQDQ, m)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]771 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]772 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]773 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]774 break;
775
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]776 CASE_UNPCK(PUNPCKLBW, r)
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]777 case X86::MMX_PUNPCKLBWirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]778 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
779 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]780 LLVM_FALLTHROUGH;
781
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]782 CASE_UNPCK(PUNPCKLBW, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]783 case X86::MMX_PUNPCKLBWirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]784 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]785 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]786 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]787 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]788
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]789 CASE_UNPCK(PUNPCKLWD, r)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]790 case X86::MMX_PUNPCKLWDirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]791 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
792 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]793 LLVM_FALLTHROUGH;
794
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]795 CASE_UNPCK(PUNPCKLWD, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]796 case X86::MMX_PUNPCKLWDirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]797 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]798 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]799 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]800 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]801
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]802 CASE_UNPCK(PUNPCKLDQ, r)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]803 case X86::MMX_PUNPCKLDQirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]804 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
805 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]806 LLVM_FALLTHROUGH;
807
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]808 CASE_UNPCK(PUNPCKLDQ, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]809 case X86::MMX_PUNPCKLDQirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]810 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]811 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]812 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]813 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]814
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]815 CASE_UNPCK(PUNPCKLQDQ, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]816 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
817 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]818 LLVM_FALLTHROUGH;
819
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]820 CASE_UNPCK(PUNPCKLQDQ, m)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]821 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]822 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]823 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]824 break;
825
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]826 CASE_SHUF(SHUFPD, rri)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]827 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
828 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]829 LLVM_FALLTHROUGH;
830
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]831 CASE_SHUF(SHUFPD, rmi)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]832 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]833 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]834 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]835 ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]836 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]837 DestName = getRegName(MI->getOperand(0).getReg());
838 break;
839
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]840 CASE_SHUF(SHUFPS, rri)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]841 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
842 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]843 LLVM_FALLTHROUGH;
844
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]845 CASE_SHUF(SHUFPS, rmi)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]846 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]847 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]848 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]849 ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]850 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]851 DestName = getRegName(MI->getOperand(0).getReg());
852 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]853
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]854 CASE_VSHUF(64X2, r)
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]855 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
856 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]857 LLVM_FALLTHROUGH;
858
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]859 CASE_VSHUF(64X2, m)
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]860 decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0),
861 MI->getOperand(NumOperands - 1).getImm(),
Igor Bregerd7bae452015-10-15 13:29:07 +0000[diff] [blame]862 ShuffleMask);
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]863 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
Igor Bregerd7bae452015-10-15 13:29:07 +0000[diff] [blame]864 DestName = getRegName(MI->getOperand(0).getReg());
Igor Bregerd7bae452015-10-15 13:29:07 +0000[diff] [blame]865 break;
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]866
867 CASE_VSHUF(32X4, r)
868 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
869 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]870 LLVM_FALLTHROUGH;
871
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]872 CASE_VSHUF(32X4, m)
873 decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0),
874 MI->getOperand(NumOperands - 1).getImm(),
875 ShuffleMask);
876 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
877 DestName = getRegName(MI->getOperand(0).getReg());
878 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]879
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]880 CASE_UNPCK(UNPCKLPD, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]881 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
882 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]883 LLVM_FALLTHROUGH;
884
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]885 CASE_UNPCK(UNPCKLPD, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]886 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]887 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]888 DestName = getRegName(MI->getOperand(0).getReg());
889 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]890
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]891 CASE_UNPCK(UNPCKLPS, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]892 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
893 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]894 LLVM_FALLTHROUGH;
895
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]896 CASE_UNPCK(UNPCKLPS, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]897 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]898 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]899 DestName = getRegName(MI->getOperand(0).getReg());
900 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]901
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]902 CASE_UNPCK(UNPCKHPD, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]903 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
904 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]905 LLVM_FALLTHROUGH;
906
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]907 CASE_UNPCK(UNPCKHPD, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]908 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]909 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]910 DestName = getRegName(MI->getOperand(0).getReg());
911 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]912
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]913 CASE_UNPCK(UNPCKHPS, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]914 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
915 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]916 LLVM_FALLTHROUGH;
917
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]918 CASE_UNPCK(UNPCKHPS, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]919 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]920 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]921 DestName = getRegName(MI->getOperand(0).getReg());
922 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]923
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]924 CASE_VPERMILPI(PERMILPS, r)
Simon Pilgrim6ce35dd2016-05-11 18:53:44 +0000[diff] [blame]925 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]926 LLVM_FALLTHROUGH;
927
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]928 CASE_VPERMILPI(PERMILPS, m)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]929 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]930 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]931 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]932 ShuffleMask);
933 DestName = getRegName(MI->getOperand(0).getReg());
934 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]935
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]936 CASE_VPERMILPI(PERMILPD, r)
Simon Pilgrim6ce35dd2016-05-11 18:53:44 +0000[diff] [blame]937 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]938 LLVM_FALLTHROUGH;
939
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]940 CASE_VPERMILPI(PERMILPD, m)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]941 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]942 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]943 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]944 ShuffleMask);
945 DestName = getRegName(MI->getOperand(0).getReg());
946 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]947
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]948 case X86::VPERM2F128rr:
949 case X86::VPERM2I128rr:
950 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]951 LLVM_FALLTHROUGH;
952
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]953 case X86::VPERM2F128rm:
954 case X86::VPERM2I128rm:
955 // For instruction comments purpose, assume the 256-bit vector is v4i64.
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]956 if (MI->getOperand(NumOperands - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]957 DecodeVPERM2X128Mask(MVT::v4i64,
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]958 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]959 ShuffleMask);
960 Src1Name = getRegName(MI->getOperand(1).getReg());
961 DestName = getRegName(MI->getOperand(0).getReg());
962 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]963
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]964 CASE_VPERM(PERMPD, r)
Craig Topper200d2372016-06-10 05:12:40 +0000[diff] [blame]965 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]966 LLVM_FALLTHROUGH;
967
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]968 CASE_VPERM(PERMPD, m)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]969 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]970 DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0),
971 MI->getOperand(NumOperands - 1).getImm(),
972 ShuffleMask);
973 DestName = getRegName(MI->getOperand(0).getReg());
974 break;
975
976 CASE_VPERM(PERMQ, r)
977 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]978 LLVM_FALLTHROUGH;
979
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]980 CASE_VPERM(PERMQ, m)
981 if (MI->getOperand(NumOperands - 1).isImm())
982 DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0),
983 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]984 ShuffleMask);
985 DestName = getRegName(MI->getOperand(0).getReg());
986 break;
987
988 case X86::MOVSDrr:
989 case X86::VMOVSDrr:
Simon Pilgrimf5c23ad2016-02-01 22:26:28 +0000[diff] [blame]990 case X86::VMOVSDZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]991 Src2Name = getRegName(MI->getOperand(2).getReg());
992 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]993 LLVM_FALLTHROUGH;
994
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]995 case X86::MOVSDrm:
996 case X86::VMOVSDrm:
Simon Pilgrimf5c23ad2016-02-01 22:26:28 +0000[diff] [blame]997 case X86::VMOVSDZrm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]998 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
999 DestName = getRegName(MI->getOperand(0).getReg());
1000 break;
Simon Pilgrimd5a15442015-11-21 13:04:42 +0000[diff] [blame]1001
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1002 case X86::MOVSSrr:
1003 case X86::VMOVSSrr:
Simon Pilgrimf5c23ad2016-02-01 22:26:28 +0000[diff] [blame]1004 case X86::VMOVSSZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1005 Src2Name = getRegName(MI->getOperand(2).getReg());
1006 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1007 LLVM_FALLTHROUGH;
1008
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1009 case X86::MOVSSrm:
1010 case X86::VMOVSSrm:
Simon Pilgrimf5c23ad2016-02-01 22:26:28 +0000[diff] [blame]1011 case X86::VMOVSSZrm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1012 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
1013 DestName = getRegName(MI->getOperand(0).getReg());
1014 break;
1015
1016 case X86::MOVPQI2QIrr:
Simon Pilgrim3e0c0222015-12-13 12:49:48 +0000[diff] [blame]1017 case X86::MOVZPQILo2PQIrr:
1018 case X86::VMOVPQI2QIrr:
1019 case X86::VMOVZPQILo2PQIrr:
1020 case X86::VMOVZPQILo2PQIZrr:
1021 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1022 LLVM_FALLTHROUGH;
1023
Simon Pilgrim3e0c0222015-12-13 12:49:48 +0000[diff] [blame]1024 case X86::MOVQI2PQIrm:
Simon Pilgrim3e0c0222015-12-13 12:49:48 +0000[diff] [blame]1025 case X86::VMOVQI2PQIrm:
Simon Pilgrim96fe4ef2016-02-02 13:32:56 +0000[diff] [blame]1026 case X86::VMOVQI2PQIZrm:
Simon Pilgrim3e0c0222015-12-13 12:49:48 +0000[diff] [blame]1027 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
1028 DestName = getRegName(MI->getOperand(0).getReg());
1029 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]1030
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1031 case X86::MOVDI2PDIrm:
1032 case X86::VMOVDI2PDIrm:
Simon Pilgrim5be17b62016-02-01 23:04:05 +0000[diff] [blame]1033 case X86::VMOVDI2PDIZrm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1034 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
1035 DestName = getRegName(MI->getOperand(0).getReg());
1036 break;
1037
Simon Pilgrimd85cae32015-07-06 20:46:41 +0000[diff] [blame]1038 case X86::EXTRQI:
1039 if (MI->getOperand(2).isImm() &&
1040 MI->getOperand(3).isImm())
Simon Pilgrim9f0a0bd2017-07-04 16:53:12 +0000[diff] [blame]1041 DecodeEXTRQIMask(MVT::v16i8, MI->getOperand(2).getImm(),
Simon Pilgrimd85cae32015-07-06 20:46:41 +0000[diff] [blame]1042 MI->getOperand(3).getImm(),
1043 ShuffleMask);
1044
1045 DestName = getRegName(MI->getOperand(0).getReg());
1046 Src1Name = getRegName(MI->getOperand(1).getReg());
1047 break;
1048
1049 case X86::INSERTQI:
1050 if (MI->getOperand(3).isImm() &&
1051 MI->getOperand(4).isImm())
Simon Pilgrim9f0a0bd2017-07-04 16:53:12 +0000[diff] [blame]1052 DecodeINSERTQIMask(MVT::v16i8, MI->getOperand(3).getImm(),
Simon Pilgrimd85cae32015-07-06 20:46:41 +0000[diff] [blame]1053 MI->getOperand(4).getImm(),
1054 ShuffleMask);
1055
1056 DestName = getRegName(MI->getOperand(0).getReg());
1057 Src1Name = getRegName(MI->getOperand(1).getReg());
1058 Src2Name = getRegName(MI->getOperand(2).getReg());
1059 break;
1060
Simon Pilgrima76a8e52016-07-14 12:07:43 +0000[diff] [blame]1061 case X86::VBROADCASTF128:
1062 case X86::VBROADCASTI128:
Craig Topperdde865a2016-10-15 16:26:07 +0000[diff] [blame]1063 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
1064 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
Simon Pilgrima76a8e52016-07-14 12:07:43 +0000[diff] [blame]1065 DecodeSubVectorBroadcast(MVT::v4f64, MVT::v2f64, ShuffleMask);
1066 DestName = getRegName(MI->getOperand(0).getReg());
1067 break;
Craig Topperdde865a2016-10-15 16:26:07 +0000[diff] [blame]1068 CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm)
1069 CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm)
1070 DecodeSubVectorBroadcast(MVT::v8f64, MVT::v2f64, ShuffleMask);
1071 DestName = getRegName(MI->getOperand(0).getReg());
1072 break;
1073 CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm)
1074 CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm)
1075 DecodeSubVectorBroadcast(MVT::v8f64, MVT::v4f64, ShuffleMask);
1076 DestName = getRegName(MI->getOperand(0).getReg());
1077 break;
1078 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1079 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1080 DecodeSubVectorBroadcast(MVT::v8f32, MVT::v4f32, ShuffleMask);
1081 DestName = getRegName(MI->getOperand(0).getReg());
1082 break;
1083 CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm)
1084 CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm)
1085 DecodeSubVectorBroadcast(MVT::v16f32, MVT::v4f32, ShuffleMask);
1086 DestName = getRegName(MI->getOperand(0).getReg());
1087 break;
1088 CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm)
1089 CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm)
1090 DecodeSubVectorBroadcast(MVT::v16f32, MVT::v8f32, ShuffleMask);
1091 DestName = getRegName(MI->getOperand(0).getReg());
1092 break;
1093 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, r)
1094 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, r)
1095 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Galina Kistanovab2c01162017-05-31 19:41:33 +0000[diff] [blame]1096 LLVM_FALLTHROUGH;
Craig Topperdde865a2016-10-15 16:26:07 +0000[diff] [blame]1097 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, m)
1098 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, m)
1099 DecodeSubVectorBroadcast(MVT::v8f32, MVT::v2f32, ShuffleMask);
1100 DestName = getRegName(MI->getOperand(0).getReg());
1101 break;
1102 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, r)
1103 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, r)
1104 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Galina Kistanovab2c01162017-05-31 19:41:33 +0000[diff] [blame]1105 LLVM_FALLTHROUGH;
Craig Topperdde865a2016-10-15 16:26:07 +0000[diff] [blame]1106 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, m)
1107 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, m)
1108 DecodeSubVectorBroadcast(MVT::v16f32, MVT::v2f32, ShuffleMask);
1109 DestName = getRegName(MI->getOperand(0).getReg());
1110 break;
Simon Pilgrima76a8e52016-07-14 12:07:43 +0000[diff] [blame]1111
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1112 CASE_PMOVZX(PMOVZXBW, r)
1113 CASE_PMOVZX(PMOVZXBD, r)
1114 CASE_PMOVZX(PMOVZXBQ, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]1115 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1116 LLVM_FALLTHROUGH;
1117
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1118 CASE_PMOVZX(PMOVZXBW, m)
1119 CASE_PMOVZX(PMOVZXBD, m)
1120 CASE_PMOVZX(PMOVZXBQ, m)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]1121 DecodeZeroExtendMask(MVT::i8, getZeroExtensionResultType(MI), ShuffleMask);
1122 DestName = getRegName(MI->getOperand(0).getReg());
1123 break;
1124
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1125 CASE_PMOVZX(PMOVZXWD, r)
1126 CASE_PMOVZX(PMOVZXWQ, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]1127 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1128 LLVM_FALLTHROUGH;
1129
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1130 CASE_PMOVZX(PMOVZXWD, m)
1131 CASE_PMOVZX(PMOVZXWQ, m)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]1132 DecodeZeroExtendMask(MVT::i16, getZeroExtensionResultType(MI), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1133 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]1134 break;
1135
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1136 CASE_PMOVZX(PMOVZXDQ, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]1137 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1138 LLVM_FALLTHROUGH;
1139
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1140 CASE_PMOVZX(PMOVZXDQ, m)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]1141 DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask);
1142 DestName = getRegName(MI->getOperand(0).getReg());
1143 break;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1144 }
1145
1146 // The only comments we decode are shuffles, so give up if we were unable to
1147 // decode a shuffle mask.
1148 if (ShuffleMask.empty())
1149 return false;
1150
1151 if (!DestName) DestName = Src1Name;
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]1152 OS << (DestName ? getMaskName(MI, DestName, getRegName) : "mem") << " = ";
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1153
1154 // If the two sources are the same, canonicalize the input elements to be
1155 // from the first src so that we get larger element spans.
1156 if (Src1Name == Src2Name) {
1157 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1158 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]1159 ShuffleMask[i] >= (int)e) // From second mask.
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1160 ShuffleMask[i] -= e;
1161 }
1162 }
1163
1164 // The shuffle mask specifies which elements of the src1/src2 fill in the
1165 // destination, with a few sentinel values. Loop through and print them
1166 // out.
1167 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1168 if (i != 0)
1169 OS << ',';
1170 if (ShuffleMask[i] == SM_SentinelZero) {
1171 OS << "zero";
1172 continue;
1173 }
1174
1175 // Otherwise, it must come from src1 or src2. Print the span of elements
1176 // that comes from this src.
1177 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1178 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1179 OS << (SrcName ? SrcName : "mem") << '[';
1180 bool IsFirst = true;
1181 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1182 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1183 if (!IsFirst)
1184 OS << ',';
1185 else
1186 IsFirst = false;
1187 if (ShuffleMask[i] == SM_SentinelUndef)
1188 OS << "u";
1189 else
1190 OS << ShuffleMask[i] % ShuffleMask.size();
1191 ++i;
1192 }
1193 OS << ']';
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]1194 --i; // For loop increments element #.
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1195 }
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1196
1197 // We successfully added a comment to this instruction.
1198 return true;
1199}