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gerrit-public.fairphone.software / toolchain / llvm-project / 747cf606969fb8ee10b96679629ccdf0ccda2112 / . / llvm / lib / Target / Sparc / SparcInstrInfo.td
blob: 1969f7d6b4aeb10de4c6152d78067339c58bede0 [file] [log] [blame]
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Sparc instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Instruction format superclass
16//===----------------------------------------------------------------------===//
17
18include "SparcInstrFormats.td"
19
20//===----------------------------------------------------------------------===//
21// Feature predicates.
22//===----------------------------------------------------------------------===//
23
24// HasV9 - This predicate is true when the target processor supports V9
25// instructions. Note that the machine may be running in 32-bit mode.
26def HasV9 : Predicate<"Subtarget.isV9()">;
27
28// HasNoV9 - This predicate is true when the target doesn't have V9
29// instructions. Use of this is just a hack for the isel not having proper
30// costs for V8 instructions that are more expensive than their V9 ones.
31def HasNoV9 : Predicate<"!Subtarget.isV9()">;
32
33// HasVIS - This is true when the target processor has VIS extensions.
34def HasVIS : Predicate<"Subtarget.isVIS()">;
35
36// UseDeprecatedInsts - This predicate is true when the target processor is a
37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
38// to use when appropriate. In either of these cases, the instruction selector
39// will pick deprecated instructions.
40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
41
42//===----------------------------------------------------------------------===//
43// Instruction Pattern Stuff
44//===----------------------------------------------------------------------===//
45
46def simm11 : PatLeaf<(imm), [{
47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field.
48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
49}]>;
50
51def simm13 : PatLeaf<(imm), [{
52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
54}]>;
55
56def LO10 : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
58}]>;
59
60def HI22 : SDNodeXForm<imm, [{
61 // Transformation function: shift the immediate value down into the low bits.
62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
63}]>;
64
65def SETHIimm : PatLeaf<(imm), [{
66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
67}], HI22>;
68
69// Addressing modes.
70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
Chris Lattnerfcb8a3a2006-02-10 07:35:42 +0000[diff] [blame]71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]72
73// Address operands
74def MEMrr : Operand<i32> {
75 let PrintMethod = "printMemOperand";
76 let NumMIOperands = 2;
77 let MIOperandInfo = (ops IntRegs, IntRegs);
78}
79def MEMri : Operand<i32> {
80 let PrintMethod = "printMemOperand";
81 let NumMIOperands = 2;
82 let MIOperandInfo = (ops IntRegs, i32imm);
83}
84
85// Branch targets have OtherVT type.
86def brtarget : Operand<OtherVT>;
87def calltarget : Operand<i32>;
88
89// Operand for printing out a condition code.
90let PrintMethod = "printCCOperand" in
91 def CCOp : Operand<i32>;
92
93def SDTSPcmpfcc :
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]94SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]95def SDTSPbrcc :
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]96SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]97def SDTSPselectcc :
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]98SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]99def SDTSPFTOI :
100SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
101def SDTSPITOF :
102SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
103
104def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
105def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]106def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
107def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]108
109def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
110def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
111
112def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
113def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
114
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]115def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
116def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]117
118// These are target-independent nodes, but have target-specific formats.
119def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
120def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq, [SDNPHasChain]>;
121def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq, [SDNPHasChain]>;
122
123def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
124def call : SDNode<"SPISD::CALL", SDT_SPCall,
125 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
126
127def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
128def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
129 [SDNPHasChain, SDNPOptInFlag]>;
130
131//===----------------------------------------------------------------------===//
132// SPARC Flag Conditions
133//===----------------------------------------------------------------------===//
134
135// Note that these values must be kept in sync with the CCOp::CondCode enum
136// values.
137class ICC_VAL<int N> : PatLeaf<(i32 N)>;
138def ICC_NE : ICC_VAL< 9>; // Not Equal
139def ICC_E : ICC_VAL< 1>; // Equal
140def ICC_G : ICC_VAL<10>; // Greater
141def ICC_LE : ICC_VAL< 2>; // Less or Equal
142def ICC_GE : ICC_VAL<11>; // Greater or Equal
143def ICC_L : ICC_VAL< 3>; // Less
144def ICC_GU : ICC_VAL<12>; // Greater Unsigned
145def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
146def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
147def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
148def ICC_POS : ICC_VAL<14>; // Positive
149def ICC_NEG : ICC_VAL< 6>; // Negative
150def ICC_VC : ICC_VAL<15>; // Overflow Clear
151def ICC_VS : ICC_VAL< 7>; // Overflow Set
152
153class FCC_VAL<int N> : PatLeaf<(i32 N)>;
154def FCC_U : FCC_VAL<23>; // Unordered
155def FCC_G : FCC_VAL<22>; // Greater
156def FCC_UG : FCC_VAL<21>; // Unordered or Greater
157def FCC_L : FCC_VAL<20>; // Less
158def FCC_UL : FCC_VAL<19>; // Unordered or Less
159def FCC_LG : FCC_VAL<18>; // Less or Greater
160def FCC_NE : FCC_VAL<17>; // Not Equal
161def FCC_E : FCC_VAL<25>; // Equal
162def FCC_UE : FCC_VAL<24>; // Unordered or Equal
163def FCC_GE : FCC_VAL<25>; // Greater or Equal
164def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
165def FCC_LE : FCC_VAL<27>; // Less or Equal
166def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
167def FCC_O : FCC_VAL<29>; // Ordered
168
169
170//===----------------------------------------------------------------------===//
171// Instructions
172//===----------------------------------------------------------------------===//
173
174// Pseudo instructions.
175class Pseudo<dag ops, string asmstr, list<dag> pattern>
176 : InstSP<ops, asmstr, pattern>;
177
178def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
179 "!ADJCALLSTACKDOWN $amt",
180 [(callseq_start imm:$amt)]>;
181def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
182 "!ADJCALLSTACKUP $amt",
183 [(callseq_end imm:$amt)]>;
184def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
185 "!IMPLICIT_DEF $dst",
186 [(set IntRegs:$dst, (undef))]>;
187def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
188 [(set FPRegs:$dst, (undef))]>;
189def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
190 [(set DFPRegs:$dst, (undef))]>;
191
192// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
193// fpmover pass.
Chris Lattner747cf602006-02-21 18:04:32 +0000[diff] [blame^]194let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]195 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
196 "!FpMOVD $src, $dst", []>;
197 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
198 "!FpNEGD $src, $dst",
199 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
200 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
201 "!FpABSD $src, $dst",
202 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
203}
204
205// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
206// scheduler into a branch sequence. This has to handle all permutations of
207// selection between i32/f32/f64 on ICC and FCC.
Chris Lattner747cf602006-02-21 18:04:32 +0000[diff] [blame^]208let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]209 def SELECT_CC_Int_ICC
210 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
211 "; SELECT_CC_Int_ICC PSEUDO!",
212 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]213 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]214 def SELECT_CC_Int_FCC
215 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
216 "; SELECT_CC_Int_FCC PSEUDO!",
217 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]218 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]219 def SELECT_CC_FP_ICC
220 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
221 "; SELECT_CC_FP_ICC PSEUDO!",
222 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]223 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]224 def SELECT_CC_FP_FCC
225 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
226 "; SELECT_CC_FP_FCC PSEUDO!",
227 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]228 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]229 def SELECT_CC_DFP_ICC
230 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
231 "; SELECT_CC_DFP_ICC PSEUDO!",
232 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]233 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]234 def SELECT_CC_DFP_FCC
235 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
236 "; SELECT_CC_DFP_FCC PSEUDO!",
237 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]238 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]239}
240
241
242// Section A.3 - Synthetic Instructions, p. 85
243// special cases of JMPL:
244let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
245 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
246 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
247}
248
249// Section B.1 - Load Integer Instructions, p. 90
250def LDSBrr : F3_1<3, 0b001001,
251 (ops IntRegs:$dst, MEMrr:$addr),
252 "ldsb [$addr], $dst",
253 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
254def LDSBri : F3_2<3, 0b001001,
255 (ops IntRegs:$dst, MEMri:$addr),
256 "ldsb [$addr], $dst",
257 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
258def LDSHrr : F3_1<3, 0b001010,
259 (ops IntRegs:$dst, MEMrr:$addr),
260 "ldsh [$addr], $dst",
261 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
262def LDSHri : F3_2<3, 0b001010,
263 (ops IntRegs:$dst, MEMri:$addr),
264 "ldsh [$addr], $dst",
265 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
266def LDUBrr : F3_1<3, 0b000001,
267 (ops IntRegs:$dst, MEMrr:$addr),
268 "ldub [$addr], $dst",
269 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
270def LDUBri : F3_2<3, 0b000001,
271 (ops IntRegs:$dst, MEMri:$addr),
272 "ldub [$addr], $dst",
273 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
274def LDUHrr : F3_1<3, 0b000010,
275 (ops IntRegs:$dst, MEMrr:$addr),
276 "lduh [$addr], $dst",
277 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
278def LDUHri : F3_2<3, 0b000010,
279 (ops IntRegs:$dst, MEMri:$addr),
280 "lduh [$addr], $dst",
281 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
282def LDrr : F3_1<3, 0b000000,
283 (ops IntRegs:$dst, MEMrr:$addr),
284 "ld [$addr], $dst",
285 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
286def LDri : F3_2<3, 0b000000,
287 (ops IntRegs:$dst, MEMri:$addr),
288 "ld [$addr], $dst",
289 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
290
291// Section B.2 - Load Floating-point Instructions, p. 92
292def LDFrr : F3_1<3, 0b100000,
293 (ops FPRegs:$dst, MEMrr:$addr),
294 "ld [$addr], $dst",
295 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
296def LDFri : F3_2<3, 0b100000,
297 (ops FPRegs:$dst, MEMri:$addr),
298 "ld [$addr], $dst",
299 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
300def LDDFrr : F3_1<3, 0b100011,
301 (ops DFPRegs:$dst, MEMrr:$addr),
302 "ldd [$addr], $dst",
303 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
304def LDDFri : F3_2<3, 0b100011,
305 (ops DFPRegs:$dst, MEMri:$addr),
306 "ldd [$addr], $dst",
307 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
308
309// Section B.4 - Store Integer Instructions, p. 95
310def STBrr : F3_1<3, 0b000101,
311 (ops MEMrr:$addr, IntRegs:$src),
312 "stb $src, [$addr]",
313 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
314def STBri : F3_2<3, 0b000101,
315 (ops MEMri:$addr, IntRegs:$src),
316 "stb $src, [$addr]",
317 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
318def STHrr : F3_1<3, 0b000110,
319 (ops MEMrr:$addr, IntRegs:$src),
320 "sth $src, [$addr]",
321 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
322def STHri : F3_2<3, 0b000110,
323 (ops MEMri:$addr, IntRegs:$src),
324 "sth $src, [$addr]",
325 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
326def STrr : F3_1<3, 0b000100,
327 (ops MEMrr:$addr, IntRegs:$src),
328 "st $src, [$addr]",
329 [(store IntRegs:$src, ADDRrr:$addr)]>;
330def STri : F3_2<3, 0b000100,
331 (ops MEMri:$addr, IntRegs:$src),
332 "st $src, [$addr]",
333 [(store IntRegs:$src, ADDRri:$addr)]>;
334
335// Section B.5 - Store Floating-point Instructions, p. 97
336def STFrr : F3_1<3, 0b100100,
337 (ops MEMrr:$addr, FPRegs:$src),
338 "st $src, [$addr]",
339 [(store FPRegs:$src, ADDRrr:$addr)]>;
340def STFri : F3_2<3, 0b100100,
341 (ops MEMri:$addr, FPRegs:$src),
342 "st $src, [$addr]",
343 [(store FPRegs:$src, ADDRri:$addr)]>;
344def STDFrr : F3_1<3, 0b100111,
345 (ops MEMrr:$addr, DFPRegs:$src),
346 "std $src, [$addr]",
347 [(store DFPRegs:$src, ADDRrr:$addr)]>;
348def STDFri : F3_2<3, 0b100111,
349 (ops MEMri:$addr, DFPRegs:$src),
350 "std $src, [$addr]",
351 [(store DFPRegs:$src, ADDRri:$addr)]>;
352
353// Section B.9 - SETHI Instruction, p. 104
354def SETHIi: F2_1<0b100,
355 (ops IntRegs:$dst, i32imm:$src),
356 "sethi $src, $dst",
357 [(set IntRegs:$dst, SETHIimm:$src)]>;
358
359// Section B.10 - NOP Instruction, p. 105
360// (It's a special case of SETHI)
361let rd = 0, imm22 = 0 in
362 def NOP : F2_1<0b100, (ops), "nop", []>;
363
364// Section B.11 - Logical Instructions, p. 106
365def ANDrr : F3_1<2, 0b000001,
366 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
367 "and $b, $c, $dst",
368 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
369def ANDri : F3_2<2, 0b000001,
370 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
371 "and $b, $c, $dst",
372 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
373def ANDNrr : F3_1<2, 0b000101,
374 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
375 "andn $b, $c, $dst",
376 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
377def ANDNri : F3_2<2, 0b000101,
378 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
379 "andn $b, $c, $dst", []>;
380def ORrr : F3_1<2, 0b000010,
381 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
382 "or $b, $c, $dst",
383 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
384def ORri : F3_2<2, 0b000010,
385 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
386 "or $b, $c, $dst",
387 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
388def ORNrr : F3_1<2, 0b000110,
389 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
390 "orn $b, $c, $dst",
391 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
392def ORNri : F3_2<2, 0b000110,
393 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
394 "orn $b, $c, $dst", []>;
395def XORrr : F3_1<2, 0b000011,
396 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
397 "xor $b, $c, $dst",
398 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
399def XORri : F3_2<2, 0b000011,
400 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
401 "xor $b, $c, $dst",
402 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
403def XNORrr : F3_1<2, 0b000111,
404 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
405 "xnor $b, $c, $dst",
406 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
407def XNORri : F3_2<2, 0b000111,
408 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
409 "xnor $b, $c, $dst", []>;
410
411// Section B.12 - Shift Instructions, p. 107
412def SLLrr : F3_1<2, 0b100101,
413 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
414 "sll $b, $c, $dst",
415 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
416def SLLri : F3_2<2, 0b100101,
417 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
418 "sll $b, $c, $dst",
419 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
420def SRLrr : F3_1<2, 0b100110,
421 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
422 "srl $b, $c, $dst",
423 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
424def SRLri : F3_2<2, 0b100110,
425 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
426 "srl $b, $c, $dst",
427 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
428def SRArr : F3_1<2, 0b100111,
429 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
430 "sra $b, $c, $dst",
431 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
432def SRAri : F3_2<2, 0b100111,
433 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
434 "sra $b, $c, $dst",
435 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
436
437// Section B.13 - Add Instructions, p. 108
438def ADDrr : F3_1<2, 0b000000,
439 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
440 "add $b, $c, $dst",
441 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
442def ADDri : F3_2<2, 0b000000,
443 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
444 "add $b, $c, $dst",
445 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
Chris Lattnerfcb8a3a2006-02-10 07:35:42 +0000[diff] [blame]446
447// "LEA" forms of add (patterns to make tblgen happy)
448def LEA_ADDri : F3_2<2, 0b000000,
449 (ops IntRegs:$dst, MEMri:$addr),
450 "add ${addr:arith}, $dst",
451 [(set IntRegs:$dst, ADDRri:$addr)]>;
452
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]453def ADDCCrr : F3_1<2, 0b010000,
454 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]455 "addcc $b, $c, $dst",
456 [(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]457def ADDCCri : F3_2<2, 0b010000,
458 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]459 "addcc $b, $c, $dst",
460 [(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]461def ADDXrr : F3_1<2, 0b001000,
462 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]463 "addx $b, $c, $dst",
464 [(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]465def ADDXri : F3_2<2, 0b001000,
466 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]467 "addx $b, $c, $dst",
468 [(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]469
470// Section B.15 - Subtract Instructions, p. 110
471def SUBrr : F3_1<2, 0b000100,
472 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
473 "sub $b, $c, $dst",
474 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
475def SUBri : F3_2<2, 0b000100,
476 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
477 "sub $b, $c, $dst",
478 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
479def SUBXrr : F3_1<2, 0b001100,
480 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]481 "subx $b, $c, $dst",
482 [(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]483def SUBXri : F3_2<2, 0b001100,
484 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]485 "subx $b, $c, $dst",
486 [(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]487def SUBCCrr : F3_1<2, 0b010100,
488 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
489 "subcc $b, $c, $dst",
490 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, IntRegs:$c))]>;
491def SUBCCri : F3_2<2, 0b010100,
492 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
493 "subcc $b, $c, $dst",
494 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, simm13:$c))]>;
495def SUBXCCrr: F3_1<2, 0b011100,
496 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
497 "subxcc $b, $c, $dst", []>;
498
499// Section B.18 - Multiply Instructions, p. 113
500def UMULrr : F3_1<2, 0b001010,
501 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
502 "umul $b, $c, $dst", []>;
503def UMULri : F3_2<2, 0b001010,
504 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
505 "umul $b, $c, $dst", []>;
Chris Lattnerc75d5b02006-02-09 05:06:36 +0000[diff] [blame]506
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]507def SMULrr : F3_1<2, 0b001011,
508 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
509 "smul $b, $c, $dst",
510 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
511def SMULri : F3_2<2, 0b001011,
512 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
513 "smul $b, $c, $dst",
514 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
515
Chris Lattnerc75d5b02006-02-09 05:06:36 +0000[diff] [blame]516/*
517//===-------------------------
518// Sparc Example
519defm intinst<id OPC1, id OPC2, bits Opc, string asmstr, SDNode code> {
520 def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
521 [(set IntRegs:$dst, (code IntRegs:$b, IntRegs:$c))]>;
522 def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
523 [(set IntRegs:$dst, (code IntRegs:$b, simm13:$c))]>;
524}
525defm intinst_np<id OPC1, id OPC2, bits Opc, string asmstr> {
526 def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
527 []>;
528 def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
529 []>;
530}
531
532def intinstnp< ADDXrr, ADDXri, 0b001000, "addx $b, $c, $dst">;
533def intinst < SUBrr, SUBri, 0b000100, "sub $b, $c, $dst", sub>;
534def intinstnp< SUBXrr, SUBXri, 0b001100, "subx $b, $c, $dst">;
535def intinst <SUBCCrr, SUBCCri, 0b010100, "subcc $b, $c, $dst", SPcmpicc>;
536def intinst < SMULrr, SMULri, 0b001011, "smul $b, $c, $dst", mul>;
537
538//===-------------------------
539// X86 Example
540defm cmov32<id OPC1, id OPC2, int opc, string asmstr, PatLeaf cond> {
541 def OPC1 : I<opc, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
542 asmstr+" {$src2, $dst|$dst, $src2}",
543 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, cond))]>, TB;
544 def OPC2 : I<opc, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
545 asmstr+" {$src2, $dst|$dst, $src2}",
546 [(set R32:$dst, (X86cmov R32:$src1,
547 (loadi32 addr:$src2), cond))]>, TB;
548}
549
550def cmov<CMOVL32rr, CMOVL32rm, 0x4C, "cmovl", X86_COND_L>;
551def cmov<CMOVB32rr, CMOVB32rm, 0x4C, "cmovb", X86_COND_B>;
552
553//===-------------------------
554// PPC Example
555
556def fpunop<id OPC1, id OPC2, id FORM, int op1, int op2, int op3, string asmstr,
557 SDNode code> {
558 def OPC1 : FORM<op1, op3, (ops F4RC:$frD, F4RC:$frB),
559 asmstr+" $frD, $frB", FPGeneral,
560 [(set F4RC:$frD, (code F4RC:$frB))]>;
561 def OPC2 : FORM<op2, op3, (ops F8RC:$frD, F8RC:$frB),
562 asmstr+" $frD, $frB", FPGeneral,
563 [(set F8RC:$frD, (code F8RC:$frB))]>;
564}
565
566def fpunop< FABSS, FABSD, XForm_26, 63, 63, 264, "fabs", fabs>;
567def fpunop<FNABSS, FNABSD, XForm_26, 63, 63, 136, "fnabs", fnabs>;
568def fpunop< FNEGS, FNEGD, XForm_26, 63, 63, 40, "fneg", fneg>;
569*/
570
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]571// Section B.19 - Divide Instructions, p. 115
572def UDIVrr : F3_1<2, 0b001110,
573 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
574 "udiv $b, $c, $dst", []>;
575def UDIVri : F3_2<2, 0b001110,
576 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
577 "udiv $b, $c, $dst", []>;
578def SDIVrr : F3_1<2, 0b001111,
579 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
580 "sdiv $b, $c, $dst", []>;
581def SDIVri : F3_2<2, 0b001111,
582 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
583 "sdiv $b, $c, $dst", []>;
584
585// Section B.20 - SAVE and RESTORE, p. 117
586def SAVErr : F3_1<2, 0b111100,
587 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
588 "save $b, $c, $dst", []>;
589def SAVEri : F3_2<2, 0b111100,
590 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
591 "save $b, $c, $dst", []>;
592def RESTORErr : F3_1<2, 0b111101,
593 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
594 "restore $b, $c, $dst", []>;
595def RESTOREri : F3_2<2, 0b111101,
596 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
597 "restore $b, $c, $dst", []>;
598
599// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
600
601// conditional branch class:
602class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
603 : F2_2<cc, 0b010, ops, asmstr, pattern> {
604 let isBranch = 1;
605 let isTerminator = 1;
606 let hasDelaySlot = 1;
607 let noResults = 1;
608}
609
610let isBarrier = 1 in
611 def BA : BranchSP<0b1000, (ops brtarget:$dst),
612 "ba $dst",
613 [(br bb:$dst)]>;
614
615// FIXME: the encoding for the JIT should look at the condition field.
616def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc),
617 "b$cc $dst",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]618 [(SPbricc bb:$dst, imm:$cc)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]619
620
621// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
622
623// floating-point conditional branch class:
624class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
625 : F2_2<cc, 0b110, ops, asmstr, pattern> {
626 let isBranch = 1;
627 let isTerminator = 1;
628 let hasDelaySlot = 1;
629 let noResults = 1;
630}
631
632// FIXME: the encoding for the JIT should look at the condition field.
633def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc),
634 "fb$cc $dst",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]635 [(SPbrfcc bb:$dst, imm:$cc)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]636
637
638// Section B.24 - Call and Link Instruction, p. 125
639// This is the only Format 1 instruction
640let Uses = [O0, O1, O2, O3, O4, O5],
641 hasDelaySlot = 1, isCall = 1, noResults = 1,
642 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
643 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
644 def CALL : InstSP<(ops calltarget:$dst),
645 "call $dst", []> {
646 bits<30> disp;
647 let op = 1;
648 let Inst{29-0} = disp;
649 }
650
651 // indirect calls
652 def JMPLrr : F3_1<2, 0b111000,
653 (ops MEMrr:$ptr),
654 "call $ptr",
655 [(call ADDRrr:$ptr)]>;
656 def JMPLri : F3_2<2, 0b111000,
657 (ops MEMri:$ptr),
658 "call $ptr",
659 [(call ADDRri:$ptr)]>;
660}
661
662// Section B.28 - Read State Register Instructions
663def RDY : F3_1<2, 0b101000,
664 (ops IntRegs:$dst),
665 "rd %y, $dst", []>;
666
667// Section B.29 - Write State Register Instructions
668def WRYrr : F3_1<2, 0b110000,
669 (ops IntRegs:$b, IntRegs:$c),
670 "wr $b, $c, %y", []>;
671def WRYri : F3_2<2, 0b110000,
672 (ops IntRegs:$b, i32imm:$c),
673 "wr $b, $c, %y", []>;
674
675// Convert Integer to Floating-point Instructions, p. 141
676def FITOS : F3_3<2, 0b110100, 0b011000100,
677 (ops FPRegs:$dst, FPRegs:$src),
678 "fitos $src, $dst",
679 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
680def FITOD : F3_3<2, 0b110100, 0b011001000,
681 (ops DFPRegs:$dst, FPRegs:$src),
682 "fitod $src, $dst",
683 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
684
685// Convert Floating-point to Integer Instructions, p. 142
686def FSTOI : F3_3<2, 0b110100, 0b011010001,
687 (ops FPRegs:$dst, FPRegs:$src),
688 "fstoi $src, $dst",
689 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
690def FDTOI : F3_3<2, 0b110100, 0b011010010,
691 (ops FPRegs:$dst, DFPRegs:$src),
692 "fdtoi $src, $dst",
693 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
694
695// Convert between Floating-point Formats Instructions, p. 143
696def FSTOD : F3_3<2, 0b110100, 0b011001001,
697 (ops DFPRegs:$dst, FPRegs:$src),
698 "fstod $src, $dst",
699 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
700def FDTOS : F3_3<2, 0b110100, 0b011000110,
701 (ops FPRegs:$dst, DFPRegs:$src),
702 "fdtos $src, $dst",
703 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
704
705// Floating-point Move Instructions, p. 144
706def FMOVS : F3_3<2, 0b110100, 0b000000001,
707 (ops FPRegs:$dst, FPRegs:$src),
708 "fmovs $src, $dst", []>;
709def FNEGS : F3_3<2, 0b110100, 0b000000101,
710 (ops FPRegs:$dst, FPRegs:$src),
711 "fnegs $src, $dst",
712 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
713def FABSS : F3_3<2, 0b110100, 0b000001001,
714 (ops FPRegs:$dst, FPRegs:$src),
715 "fabss $src, $dst",
716 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
717
718
719// Floating-point Square Root Instructions, p.145
720def FSQRTS : F3_3<2, 0b110100, 0b000101001,
721 (ops FPRegs:$dst, FPRegs:$src),
722 "fsqrts $src, $dst",
723 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
724def FSQRTD : F3_3<2, 0b110100, 0b000101010,
725 (ops DFPRegs:$dst, DFPRegs:$src),
726 "fsqrtd $src, $dst",
727 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
728
729
730
731// Floating-point Add and Subtract Instructions, p. 146
732def FADDS : F3_3<2, 0b110100, 0b001000001,
733 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
734 "fadds $src1, $src2, $dst",
735 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
736def FADDD : F3_3<2, 0b110100, 0b001000010,
737 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
738 "faddd $src1, $src2, $dst",
739 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
740def FSUBS : F3_3<2, 0b110100, 0b001000101,
741 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
742 "fsubs $src1, $src2, $dst",
743 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
744def FSUBD : F3_3<2, 0b110100, 0b001000110,
745 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
746 "fsubd $src1, $src2, $dst",
747 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
748
749// Floating-point Multiply and Divide Instructions, p. 147
750def FMULS : F3_3<2, 0b110100, 0b001001001,
751 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
752 "fmuls $src1, $src2, $dst",
753 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
754def FMULD : F3_3<2, 0b110100, 0b001001010,
755 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
756 "fmuld $src1, $src2, $dst",
757 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
758def FSMULD : F3_3<2, 0b110100, 0b001101001,
759 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
760 "fsmuld $src1, $src2, $dst",
761 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
762 (fextend FPRegs:$src2)))]>;
763def FDIVS : F3_3<2, 0b110100, 0b001001101,
764 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
765 "fdivs $src1, $src2, $dst",
766 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
767def FDIVD : F3_3<2, 0b110100, 0b001001110,
768 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
769 "fdivd $src1, $src2, $dst",
770 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
771
772// Floating-point Compare Instructions, p. 148
773// Note: the 2nd template arg is different for these guys.
774// Note 2: the result of a FCMP is not available until the 2nd cycle
775// after the instr is retired, but there is no interlock. This behavior
776// is modelled with a forced noop after the instruction.
777def FCMPS : F3_3<2, 0b110101, 0b001010001,
778 (ops FPRegs:$src1, FPRegs:$src2),
779 "fcmps $src1, $src2\n\tnop",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]780 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]781def FCMPD : F3_3<2, 0b110101, 0b001010010,
782 (ops DFPRegs:$src1, DFPRegs:$src2),
783 "fcmpd $src1, $src2\n\tnop",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]784 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]785
786
787//===----------------------------------------------------------------------===//
788// V9 Instructions
789//===----------------------------------------------------------------------===//
790
791// V9 Conditional Moves.
792let Predicates = [HasV9], isTwoAddress = 1 in {
793 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
794 // FIXME: Add instruction encodings for the JIT some day.
795 def MOVICCrr
796 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
797 "mov$cc %icc, $F, $dst",
798 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]799 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]800 def MOVICCri
801 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
802 "mov$cc %icc, $F, $dst",
803 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]804 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]805
806 def MOVFCCrr
807 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
808 "mov$cc %fcc0, $F, $dst",
809 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]810 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]811 def MOVFCCri
812 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
813 "mov$cc %fcc0, $F, $dst",
814 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]815 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]816
817 def FMOVS_ICC
818 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
819 "fmovs$cc %icc, $F, $dst",
820 [(set FPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]821 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]822 def FMOVD_ICC
823 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
824 "fmovd$cc %icc, $F, $dst",
825 [(set DFPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]826 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]827 def FMOVS_FCC
828 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
829 "fmovs$cc %fcc0, $F, $dst",
830 [(set FPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]831 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]832 def FMOVD_FCC
833 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
834 "fmovd$cc %fcc0, $F, $dst",
835 [(set DFPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]836 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]837
838}
839
840// Floating-Point Move Instructions, p. 164 of the V9 manual.
841let Predicates = [HasV9] in {
842 def FMOVD : F3_3<2, 0b110100, 0b000000010,
843 (ops DFPRegs:$dst, DFPRegs:$src),
844 "fmovd $src, $dst", []>;
845 def FNEGD : F3_3<2, 0b110100, 0b000000110,
846 (ops DFPRegs:$dst, DFPRegs:$src),
847 "fnegd $src, $dst",
848 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
849 def FABSD : F3_3<2, 0b110100, 0b000001010,
850 (ops DFPRegs:$dst, DFPRegs:$src),
851 "fabsd $src, $dst",
852 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
853}
854
855// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
856// the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
857def POPCrr : F3_1<2, 0b101110,
858 (ops IntRegs:$dst, IntRegs:$src),
859 "popc $src, $dst", []>, Requires<[HasV9]>;
860def : Pat<(ctpop IntRegs:$src),
861 (POPCrr (SLLri IntRegs:$src, 0))>;
862
863//===----------------------------------------------------------------------===//
864// Non-Instruction Patterns
865//===----------------------------------------------------------------------===//
866
867// Small immediates.
868def : Pat<(i32 simm13:$val),
869 (ORri G0, imm:$val)>;
870// Arbitrary immediates.
871def : Pat<(i32 imm:$val),
872 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
873
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]874// subc
875def : Pat<(subc IntRegs:$b, IntRegs:$c),
876 (SUBCCrr IntRegs:$b, IntRegs:$c)>;
877def : Pat<(subc IntRegs:$b, simm13:$val),
878 (SUBCCri IntRegs:$b, imm:$val)>;
879
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]880// Global addresses, constant pool entries
881def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
882def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
883def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
884def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
885
886// Add reg, lo. This is used when taking the addr of a global/constpool entry.
887def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
888 (ADDri IntRegs:$r, tglobaladdr:$in)>;
889def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
890 (ADDri IntRegs:$r, tconstpool:$in)>;
891
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]892// Calls:
893def : Pat<(call tglobaladdr:$dst),
894 (CALL tglobaladdr:$dst)>;
Chris Lattnerfcb8a3a2006-02-10 07:35:42 +0000[diff] [blame]895def : Pat<(call texternalsym:$dst),
896 (CALL texternalsym:$dst)>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]897
898def : Pat<(ret), (RETL)>;
899
900// Map integer extload's to zextloads.
901def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
902def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
903def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
904def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
905def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
906def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
907
908// zextload bool -> zextload byte
909def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
910def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
911
912// truncstore bool -> truncstore byte.
913def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
914 (STBrr ADDRrr:$addr, IntRegs:$src)>;
915def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
916 (STBri ADDRri:$addr, IntRegs:$src)>;