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gerrit-public.fairphone.software / toolchain / llvm-project / 756f5978410809530150f5e1cd425e85ad94d1cd / . / llvm / lib / Support / X86TargetParser.cpp
blob: 131bfd5eb6ac8f00ad84e01612cdf003f6654dda [file] [log] [blame]
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/Support/X86TargetParser.h"
14#include "llvm/ADT/StringSwitch.h"
15#include "llvm/ADT/Triple.h"
16
17using namespace llvm;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]18using namespace llvm::X86;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]19
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]20namespace {
21
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]22/// Container class for CPU features.
23/// This is a constexpr reimplementation of a subset of std::bitset. It would be
24/// nice to use std::bitset directly, but it doesn't support constant
25/// initialization.
26class FeatureBitset {
27 static constexpr unsigned NUM_FEATURE_WORDS =
28 (X86::CPU_FEATURE_MAX + 31) / 32;
29
30 // This cannot be a std::array, operator[] is not constexpr until C++17.
31 uint32_t Bits[NUM_FEATURE_WORDS] = {};
32
33public:
34 constexpr FeatureBitset() = default;
35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36 for (auto I : Init)
37 set(I);
38 }
39
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]40 bool any() const {
41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42 }
43
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]44 constexpr FeatureBitset &set(unsigned I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]45 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47 Bits[I / 32] = NewBits;
48 return *this;
49 }
50
51 constexpr bool operator[](unsigned I) const {
52 uint32_t Mask = uint32_t(1) << (I % 32);
53 return (Bits[I / 32] & Mask) != 0;
54 }
55
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
58 // GCC <6.2 crashes if this is written in a single statement.
59 uint32_t NewBits = Bits[I] & RHS.Bits[I];
60 Bits[I] = NewBits;
61 }
62 return *this;
63 }
64
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]67 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]68 uint32_t NewBits = Bits[I] | RHS.Bits[I];
69 Bits[I] = NewBits;
70 }
71 return *this;
72 }
73
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]74 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]76 FeatureBitset Result;
77 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
78 Result.Bits[I] = Bits[I] & RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]79 return Result;
80 }
81
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]82 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]84 FeatureBitset Result;
85 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
86 Result.Bits[I] = Bits[I] | RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]87 return Result;
88 }
89
90 constexpr FeatureBitset operator~() const {
91 FeatureBitset Result;
92 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
93 Result.Bits[I] = ~Bits[I];
94 return Result;
95 }
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]96
97 constexpr bool operator!=(const FeatureBitset &RHS) const {
98 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
99 if (Bits[I] != RHS.Bits[I])
100 return true;
101 return false;
102 }
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]103};
104
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]105struct ProcInfo {
106 StringLiteral Name;
107 X86::CPUKind Kind;
108 unsigned KeyFeature;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]109 FeatureBitset Features;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]110};
111
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]112struct FeatureInfo {
113 StringLiteral Name;
114 FeatureBitset ImpliedFeatures;
115};
116
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]117} // end anonymous namespace
118
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]119#define X86_FEATURE(ENUM, STRING) \
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]120 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]121#include "llvm/Support/X86TargetParser.def"
122
123// Pentium with MMX.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]124constexpr FeatureBitset FeaturesPentiumMMX =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126
127// Pentium 2 and 3.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]128constexpr FeatureBitset FeaturesPentium2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]130constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]131
132// Pentium 4 CPUs
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]133constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
134constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
135constexpr FeatureBitset FeaturesNocona =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]136 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]137
138// Basic 64-bit capable CPU.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]139constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]140constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
141 FeaturePOPCNT | FeatureSSE4_2 |
142 FeatureCMPXCHG16B;
143constexpr FeatureBitset FeaturesX86_64_V3 =
144 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
145 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
146constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 |
147 FeatureAVX512BW | FeatureAVX512CD |
148 FeatureAVX512DQ | FeatureAVX512VL;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]149
150// Intel Core CPUs
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]151constexpr FeatureBitset FeaturesCore2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]152 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]153constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
154constexpr FeatureBitset FeaturesNehalem =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]155 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]156constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
157constexpr FeatureBitset FeaturesSandyBridge =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]158 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]159constexpr FeatureBitset FeaturesIvyBridge =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]160 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]161constexpr FeatureBitset FeaturesHaswell =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]162 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
163 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]164constexpr FeatureBitset FeaturesBroadwell =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]165 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
166
167// Intel Knights Landing and Knights Mill
168// Knights Landing has feature parity with Broadwell.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]169constexpr FeatureBitset FeaturesKNL =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]170 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
171 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]172constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]173
174// Intel Skylake processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]175constexpr FeatureBitset FeaturesSkylakeClient =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]176 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
177 FeatureXSAVES | FeatureSGX;
178// SkylakeServer inherits all SkylakeClient features except SGX.
179// FIXME: That doesn't match gcc.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]180constexpr FeatureBitset FeaturesSkylakeServer =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]181 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
182 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
183 FeaturePKU;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]184constexpr FeatureBitset FeaturesCascadeLake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]185 FeaturesSkylakeServer | FeatureAVX512VNNI;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]186constexpr FeatureBitset FeaturesCooperLake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]187 FeaturesCascadeLake | FeatureAVX512BF16;
188
189// Intel 10nm processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]190constexpr FeatureBitset FeaturesCannonlake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]191 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
192 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
193 FeaturePKU | FeatureSHA;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]194constexpr FeatureBitset FeaturesICLClient =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]195 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
196 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
197 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]198constexpr FeatureBitset FeaturesICLServer =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]199 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]200constexpr FeatureBitset FeaturesTigerlake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]201 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]202 FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]203constexpr FeatureBitset FeaturesSapphireRapids =
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]204 FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]205 FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
206 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
Tianqing Wangbe39a6f2020-10-22 16:46:07 +0800[diff] [blame]207 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
Liu, Chen3756f5972020-10-30 12:58:05 +0800[diff] [blame^]208 FeatureWAITPKG | FeatureAVXVNNI;
Benjamin Kramer39a0d682020-10-24 18:00:33 +0200[diff] [blame]209constexpr FeatureBitset FeaturesAlderlake =
210 FeaturesSkylakeClient | FeatureCLDEMOTE | FeatureHRESET | FeaturePTWRITE |
Liu, Chen3756f5972020-10-30 12:58:05 +0800[diff] [blame^]211 FeatureSERIALIZE | FeatureWAITPKG | FeatureAVXVNNI;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]212
213// Intel Atom processors.
214// Bonnell has feature parity with Core2 and adds MOVBE.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]215constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]216// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]217constexpr FeatureBitset FeaturesSilvermont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]218 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]219constexpr FeatureBitset FeaturesGoldmont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]220 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
221 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
222 FeatureXSAVEOPT | FeatureXSAVES;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]223constexpr FeatureBitset FeaturesGoldmontPlus =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]224 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]225constexpr FeatureBitset FeaturesTremont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]226 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
227
228// Geode Processor.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]229constexpr FeatureBitset FeaturesGeode =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]230 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
231
232// K6 processor.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]233constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]234
235// K7 and K8 architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]236constexpr FeatureBitset FeaturesAthlon =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]237 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]238constexpr FeatureBitset FeaturesAthlonXP =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]239 FeaturesAthlon | FeatureFXSR | FeatureSSE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]240constexpr FeatureBitset FeaturesK8 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]241 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]242constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
243constexpr FeatureBitset FeaturesAMDFAM10 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]244 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]245 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]246
247// Bobcat architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]248constexpr FeatureBitset FeaturesBTVER1 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]249 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]250 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]251 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]252 FeatureSAHF;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]253constexpr FeatureBitset FeaturesBTVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]254 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
255 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
256
257// AMD Bulldozer architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]258constexpr FeatureBitset FeaturesBDVER1 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]259 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]260 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]261 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
262 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]263 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]264constexpr FeatureBitset FeaturesBDVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]265 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]266constexpr FeatureBitset FeaturesBDVER3 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]267 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]268constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
269 FeatureBMI2 | FeatureMOVBE |
270 FeatureMWAITX | FeatureRDRND;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]271
272// AMD Zen architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]273constexpr FeatureBitset FeaturesZNVER1 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]274 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
275 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]276 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]277 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
278 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
279 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
280 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]281 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]282 FeatureXSAVEOPT | FeatureXSAVES;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]283constexpr FeatureBitset FeaturesZNVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]284 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
Benjamin Kramerbd2cf962020-10-24 18:00:20 +0200[diff] [blame]285static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
286 FeatureINVPCID | FeaturePKU |
287 FeatureVAES | FeatureVPCLMULQDQ;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]288
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]289constexpr ProcInfo Processors[] = {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]290 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
291 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]292 // i386-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]293 { {"i386"}, CK_i386, ~0U, FeatureX87 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]294 // i486-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]295 { {"i486"}, CK_i486, ~0U, FeatureX87 },
296 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
297 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
298 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]299 // i586-generation processors, P5 microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]300 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
301 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
302 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]303 // i686-generation processors, P6 / Pentium M microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]304 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
305 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
306 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
307 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
308 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
309 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
310 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
311 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]312 // Netburst microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]313 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
314 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
315 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
316 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]317 // Core microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]318 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
319 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]320 // Atom processors
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]321 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
322 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
323 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
324 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
325 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
326 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
327 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]328 // Nehalem microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]329 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
330 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]331 // Westmere microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]332 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]333 // Sandy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]334 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
335 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]336 // Ivy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]337 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
338 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]339 // Haswell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]340 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
341 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]342 // Broadwell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]343 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]344 // Skylake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]345 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]346 // Skylake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]347 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
348 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]349 // Cascadelake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]350 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]351 // Cooperlake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]352 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]353 // Cannonlake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]354 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]355 // Icelake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]356 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]357 // Icelake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]358 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]359 // Tigerlake microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]360 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]361 // Sapphire Rapids microarchitecture based processors.
362 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
Benjamin Kramer39a0d682020-10-24 18:00:33 +0200[diff] [blame]363 // Alderlake microarchitecture based processors.
364 { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]365 // Knights Landing processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]366 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]367 // Knights Mill processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]368 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]369 // Lakemont microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]370 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]371 // K6 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]372 { {"k6"}, CK_K6, ~0U, FeaturesK6 },
373 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
374 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]375 // K7 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]376 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
377 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
378 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
379 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
380 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]381 // K8 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]382 { {"k8"}, CK_K8, ~0U, FeaturesK8 },
383 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
384 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
385 { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
386 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
387 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
388 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
389 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
390 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]391 // Bobcat architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]392 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
393 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]394 // Bulldozer architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]395 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
396 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
397 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
398 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]399 // Zen architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]400 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
401 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
Benjamin Kramerbd2cf962020-10-24 18:00:20 +0200[diff] [blame]402 { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]403 // Generic 64-bit processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]404 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]405 { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
406 { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
407 { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]408 // Geode processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]409 { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]410};
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]411
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]412constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
413
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]414X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]415 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]416 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]417 return P.Kind;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]418
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]419 return CK_None;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]420}
421
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]422X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
423 if (llvm::is_contained(NoTuneList, CPU))
424 return CK_None;
425 return parseArchX86(CPU, Only64Bit);
426}
427
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]428void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
429 bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]430 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]431 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]432 Values.emplace_back(P.Name);
433}
434
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]435void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
436 bool Only64Bit) {
437 for (const ProcInfo &P : Processors)
438 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
439 !llvm::is_contained(NoTuneList, P.Name))
440 Values.emplace_back(P.Name);
441}
442
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]443ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
444 // FIXME: Can we avoid a linear search here? The table might be sorted by
445 // CPUKind so we could binary search?
446 for (const auto &P : Processors) {
447 if (P.Kind == Kind) {
448 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
449 return static_cast<ProcessorFeatures>(P.KeyFeature);
450 }
451 }
452
453 llvm_unreachable("Unable to find CPU kind!");
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]454}
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]455
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]456// Features with no dependencies.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]457constexpr FeatureBitset ImpliedFeatures64BIT = {};
458constexpr FeatureBitset ImpliedFeaturesADX = {};
459constexpr FeatureBitset ImpliedFeaturesBMI = {};
460constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
461constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
462constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
463constexpr FeatureBitset ImpliedFeaturesCLWB = {};
464constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
465constexpr FeatureBitset ImpliedFeaturesCMOV = {};
466constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
467constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
468constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
469constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
470constexpr FeatureBitset ImpliedFeaturesFXSR = {};
471constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
472constexpr FeatureBitset ImpliedFeaturesLWP = {};
473constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
474constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
475constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
476constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
477constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
478constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
479constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
480constexpr FeatureBitset ImpliedFeaturesPKU = {};
481constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
482constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
483constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
484constexpr FeatureBitset ImpliedFeaturesRDPID = {};
485constexpr FeatureBitset ImpliedFeaturesRDRND = {};
486constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
487constexpr FeatureBitset ImpliedFeaturesRTM = {};
488constexpr FeatureBitset ImpliedFeaturesSAHF = {};
489constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
490constexpr FeatureBitset ImpliedFeaturesSGX = {};
491constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
492constexpr FeatureBitset ImpliedFeaturesTBM = {};
493constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
Tianqing Wangbe39a6f2020-10-22 16:46:07 +0800[diff] [blame]494constexpr FeatureBitset ImpliedFeaturesUINTR = {};
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]495constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
496constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
497constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
498constexpr FeatureBitset ImpliedFeaturesX87 = {};
499constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]500
501// Not really CPU features, but need to be in the table because clang uses
502// target features to communicate them to the backend.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]503constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
504constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
505constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
506constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
507constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]508
509// XSAVE features are dependent on basic XSAVE.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]510constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
511constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
512constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]513
514// MMX->3DNOW->3DNOWA chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]515constexpr FeatureBitset ImpliedFeaturesMMX = {};
516constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
517constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]518
519// SSE/AVX/AVX512F chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]520constexpr FeatureBitset ImpliedFeaturesSSE = {};
521constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
522constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
523constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
524constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
525constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
526constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
527constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
528constexpr FeatureBitset ImpliedFeaturesAVX512F =
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]529 FeatureAVX2 | FeatureF16C | FeatureFMA;
530
531// Vector extensions that build on SSE or AVX.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]532constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
533constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
534constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
535constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
536constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
537constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
538constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
539constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]540
541// AVX512 features.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]542constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
543constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
544constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
545constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
546constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
547constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]548
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]549constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
550constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
551constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
552constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
553constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
554constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
555constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
556constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]557
558// FIXME: These two aren't really implemented and just exist in the feature
559// list for __builtin_cpu_supports. So omit their dependencies.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]560constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
561constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]562
563// SSE4_A->FMA4->XOP chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]564constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
565constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
566constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]567
568// AMX Features
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]569constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
570constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
571constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
Wang, Pengfei412cdcf2020-10-13 08:42:46 +0800[diff] [blame]572constexpr FeatureBitset ImpliedFeaturesHRESET = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]573
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]574// Key Locker Features
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]575constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
576constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]577
Liu, Chen3756f5972020-10-30 12:58:05 +0800[diff] [blame^]578// AVXVNNI Features
579constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
580
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]581constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]582#define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]583#include "llvm/Support/X86TargetParser.def"
584};
585
586void llvm::X86::getFeaturesForCPU(StringRef CPU,
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]587 SmallVectorImpl<StringRef> &EnabledFeatures) {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]588 auto I = llvm::find_if(Processors,
589 [&](const ProcInfo &P) { return P.Name == CPU; });
590 assert(I != std::end(Processors) && "Processor not found!");
591
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]592 FeatureBitset Bits = I->Features;
593
594 // Remove the 64-bit feature which we only use to validate if a CPU can
595 // be used with 64-bit mode.
596 Bits &= ~Feature64BIT;
597
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]598 // Add the string version of all set bits.
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]599 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
600 if (Bits[i] && !FeatureInfos[i].Name.empty())
601 EnabledFeatures.push_back(FeatureInfos[i].Name);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]602}
603
604// For each feature that is (transitively) implied by this feature, set it.
605static void getImpliedEnabledFeatures(FeatureBitset &Bits,
606 const FeatureBitset &Implies) {
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]607 // Fast path: Implies is often empty.
608 if (!Implies.any())
609 return;
610 FeatureBitset Prev;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]611 Bits |= Implies;
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]612 do {
613 Prev = Bits;
614 for (unsigned i = CPU_FEATURE_MAX; i;)
615 if (Bits[--i])
616 Bits |= FeatureInfos[i].ImpliedFeatures;
617 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]618}
619
620/// Create bit vector of features that are implied disabled if the feature
621/// passed in Value is disabled.
622static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
623 // Check all features looking for any dependent on this feature. If we find
624 // one, mark it and recursively find any feature that depend on it.
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]625 FeatureBitset Prev;
626 Bits.set(Value);
627 do {
628 Prev = Bits;
629 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
630 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
631 Bits.set(i);
632 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]633}
634
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]635void llvm::X86::updateImpliedFeatures(
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]636 StringRef Feature, bool Enabled,
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]637 StringMap<bool> &Features) {
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]638 auto I = llvm::find_if(
639 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
640 if (I == std::end(FeatureInfos)) {
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]641 // FIXME: This shouldn't happen, but may not have all features in the table
642 // yet.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]643 return;
644 }
645
646 FeatureBitset ImpliedBits;
647 if (Enabled)
648 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
649 else
650 getImpliedDisabledFeatures(ImpliedBits,
651 std::distance(std::begin(FeatureInfos), I));
652
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]653 // Update the map entry for all implied features.
654 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
655 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
656 Features[FeatureInfos[i].Name] = Enabled;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]657}