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gerrit-public.fairphone.software / toolchain / llvm-project / 7684e055b34935b29e4fb355fde9630c55a88bb2 / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: ca16bc35ba2cfc06a882d329cec5bfc65297b9fc [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
25 // This flag is set to allow the scheduler to assign a default model to
26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
70def BWDivider : ProcResource<1>; // Integer division issued on port 0.
71
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]72// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
73// cycles after the memory operand.
74def : ReadAdvance<ReadAfterLd, 5>;
75
76// Many SchedWrites are defined in pairs with and without a folded load.
77// Instructions with folded loads are usually micro-fused, so they only appear
78// as two micro-ops when queued in the reservation station.
79// This multiclass defines the resource usage for variants with and without
80// folded loads.
81multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]82 list<ProcResourceKind> ExePorts,
83 int Lat, list<int> Res = [1], int UOps = 1> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]84 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]85 def : WriteRes<SchedRW, ExePorts> {
86 let Latency = Lat;
87 let ResourceCycles = Res;
88 let NumMicroOps = UOps;
89 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]90
91 // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
92 // latency.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]93 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
94 let Latency = !add(Lat, 5);
95 let ResourceCycles = !listconcat([1], Res);
96 let NumMicroOps = UOps;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]97 }
98}
99
100// A folded store needs a cycle on port 4 for the store data, but it does not
101// need an extra port 2/3 cycle to recompute the address.
102def : WriteRes<WriteRMW, [BWPort4]>;
103
104// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]105defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
106defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
107defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]108def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]109
110def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
111
112// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]113defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]114
115// Loads, stores, and moves, not folded with other operations.
116def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
117def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
118def : WriteRes<WriteMove, [BWPort0156]>;
119
120// Idioms that clear a register, like xorps %xmm0, %xmm0.
121// These can often bypass execution ports completely.
122def : WriteRes<WriteZero, []>;
123
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]124// Treat misc copies as a move.
125def : InstRW<[WriteMove], (instrs COPY)>;
126
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]127// Branches don't produce values, so they have no latency, but they still
128// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]129defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]130
131// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]132def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
133def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
134def : WriteRes<WriteFMove, [BWPort5]>;
135
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]136defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
137defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
138defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
139defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
140defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
141defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
142defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
143defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
144defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
145defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]146
147// FMA Scheduling helper class.
148// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
149
150// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]151def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
152def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
153def : WriteRes<WriteVecMove, [BWPort015]>;
154
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]155defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
156defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
157defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
158defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
159defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
160defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
161defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]162
163// Vector bitwise operations.
164// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]165defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]166
167// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]168defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
169defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
170defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]171
172// Strings instructions.
173// Packed Compare Implicit Length Strings, Return Mask
174// String instructions.
175def : WriteRes<WritePCmpIStrM, [BWPort0]> {
176 let Latency = 10;
177 let ResourceCycles = [3];
178}
179def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
180 let Latency = 10;
181 let ResourceCycles = [3, 1];
182}
183// Packed Compare Explicit Length Strings, Return Mask
184def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort16, BWPort5]> {
185 let Latency = 10;
186 let ResourceCycles = [3, 2, 4];
187}
188def : WriteRes<WritePCmpEStrMLd, [BWPort05, BWPort16, BWPort23]> {
189 let Latency = 10;
190 let ResourceCycles = [6, 2, 1];
191}
192 // Packed Compare Implicit Length Strings, Return Index
193def : WriteRes<WritePCmpIStrI, [BWPort0]> {
194 let Latency = 11;
195 let ResourceCycles = [3];
196}
197def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
198 let Latency = 11;
199 let ResourceCycles = [3, 1];
200}
201// Packed Compare Explicit Length Strings, Return Index
202def : WriteRes<WritePCmpEStrI, [BWPort05, BWPort16]> {
203 let Latency = 11;
204 let ResourceCycles = [6, 2];
205}
206def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort16, BWPort5, BWPort23]> {
207 let Latency = 11;
208 let ResourceCycles = [3, 2, 2, 1];
209}
210
211// AES instructions.
212def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
213 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]214 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]215 let ResourceCycles = [1];
216}
217def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]218 let Latency = 12;
219 let NumMicroOps = 2;
220 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]221}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]222
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]223def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
224 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]225 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]226 let ResourceCycles = [2];
227}
228def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]229 let Latency = 19;
230 let NumMicroOps = 3;
231 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]232}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]233
234def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
235 let Latency = 29;
236 let NumMicroOps = 11;
237 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]238}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]239def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
240 let Latency = 33;
241 let NumMicroOps = 11;
242 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]243}
244
245// Carry-less multiplication instructions.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]246defm : BWWriteResPair<WriteCLMul, [BWPort0, BWPort5], 7, [2, 1]>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]247
248// Catch-all for expensive system instructions.
249def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
250
251// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]252defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
253defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
254defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]255
256// Old microcoded instructions that nobody use.
257def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
258
259// Fence instructions.
260def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
261
262// Nop, not very useful expect it provides a model for nops!
263def : WriteRes<WriteNop, []>;
264
265////////////////////////////////////////////////////////////////////////////////
266// Horizontal add/sub instructions.
267////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]268
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]269defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
270defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]271
272// Remaining instrs.
273
274def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
275 let Latency = 1;
276 let NumMicroOps = 1;
277 let ResourceCycles = [1];
278}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]279def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
280 "MMX_MOVD64grr",
281 "MMX_PMOVMSKBrr",
282 "MMX_PSLLDri",
283 "MMX_PSLLDrr",
284 "MMX_PSLLQri",
285 "MMX_PSLLQrr",
286 "MMX_PSLLWri",
287 "MMX_PSLLWrr",
288 "MMX_PSRADri",
289 "MMX_PSRADrr",
290 "MMX_PSRAWri",
291 "MMX_PSRAWrr",
292 "MMX_PSRLDri",
293 "MMX_PSRLDrr",
294 "MMX_PSRLQri",
295 "MMX_PSRLQrr",
296 "MMX_PSRLWri",
297 "MMX_PSRLWrr",
298 "MOVPDI2DIrr",
299 "MOVPQIto64rr",
300 "PSLLDri",
301 "PSLLQri",
302 "PSLLWri",
303 "PSRADri",
304 "PSRAWri",
305 "PSRLDri",
306 "PSRLQri",
307 "PSRLWri",
308 "VMOVPDI2DIrr",
309 "VMOVPQIto64rr",
310 "VPSLLDYri",
311 "VPSLLDri",
312 "VPSLLQYri",
313 "VPSLLQri",
314 "VPSLLVQYrr",
315 "VPSLLVQrr",
316 "VPSLLWYri",
317 "VPSLLWri",
318 "VPSRADYri",
319 "VPSRADri",
320 "VPSRAWYri",
321 "VPSRAWri",
322 "VPSRLDYri",
323 "VPSRLDri",
324 "VPSRLQYri",
325 "VPSRLQri",
326 "VPSRLVQYrr",
327 "VPSRLVQrr",
328 "VPSRLWYri",
329 "VPSRLWri",
330 "VTESTPDYrr",
331 "VTESTPDrr",
332 "VTESTPSYrr",
333 "VTESTPSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]334
335def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
336 let Latency = 1;
337 let NumMicroOps = 1;
338 let ResourceCycles = [1];
339}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]340def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
341 "COM_FST0r",
342 "UCOM_FPr",
343 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]344
345def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
346 let Latency = 1;
347 let NumMicroOps = 1;
348 let ResourceCycles = [1];
349}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]350def: InstRW<[BWWriteResGroup3], (instregex "ANDNPDrr",
351 "ANDNPSrr",
352 "ANDPDrr",
353 "ANDPSrr",
354 "INSERTPSrr",
355 "MMX_MOVD64rr",
356 "MMX_MOVD64to64rr",
357 "MMX_MOVQ2DQrr",
358 "MMX_PALIGNRrri",
359 "MMX_PSHUFBrr",
360 "MMX_PSHUFWri",
361 "MMX_PUNPCKHBWirr",
362 "MMX_PUNPCKHDQirr",
363 "MMX_PUNPCKHWDirr",
364 "MMX_PUNPCKLBWirr",
365 "MMX_PUNPCKLDQirr",
366 "MMX_PUNPCKLWDirr",
367 "MOV64toPQIrr",
368 "MOVAPDrr",
369 "MOVAPSrr",
370 "MOVDDUPrr",
371 "MOVDI2PDIrr",
372 "MOVHLPSrr",
373 "MOVLHPSrr",
374 "MOVSDrr",
375 "MOVSHDUPrr",
376 "MOVSLDUPrr",
377 "MOVSSrr",
378 "MOVUPDrr",
379 "MOVUPSrr",
380 "ORPDrr",
381 "ORPSrr",
382 "PACKSSDWrr",
383 "PACKSSWBrr",
384 "PACKUSDWrr",
385 "PACKUSWBrr",
386 "PALIGNRrri",
387 "PBLENDWrri",
388 "PMOVSXBDrr",
389 "PMOVSXBQrr",
390 "PMOVSXBWrr",
391 "PMOVSXDQrr",
392 "PMOVSXWDrr",
393 "PMOVSXWQrr",
394 "PMOVZXBDrr",
395 "PMOVZXBQrr",
396 "PMOVZXBWrr",
397 "PMOVZXDQrr",
398 "PMOVZXWDrr",
399 "PMOVZXWQrr",
400 "PSHUFBrr",
401 "PSHUFDri",
402 "PSHUFHWri",
403 "PSHUFLWri",
404 "PSLLDQri",
405 "PSRLDQri",
406 "PUNPCKHBWrr",
407 "PUNPCKHDQrr",
408 "PUNPCKHQDQrr",
409 "PUNPCKHWDrr",
410 "PUNPCKLBWrr",
411 "PUNPCKLDQrr",
412 "PUNPCKLQDQrr",
413 "PUNPCKLWDrr",
414 "SHUFPDrri",
415 "SHUFPSrri",
416 "UNPCKHPDrr",
417 "UNPCKHPSrr",
418 "UNPCKLPDrr",
419 "UNPCKLPSrr",
420 "VANDNPDYrr",
421 "VANDNPDrr",
422 "VANDNPSYrr",
423 "VANDNPSrr",
424 "VANDPDYrr",
425 "VANDPDrr",
426 "VANDPSYrr",
427 "VANDPSrr",
428 "VBROADCASTSSrr",
429 "VINSERTPSrr",
430 "VMOV64toPQIrr",
431 "VMOVAPDYrr",
432 "VMOVAPDrr",
433 "VMOVAPSYrr",
434 "VMOVAPSrr",
435 "VMOVDDUPYrr",
436 "VMOVDDUPrr",
437 "VMOVDI2PDIrr",
438 "VMOVHLPSrr",
439 "VMOVLHPSrr",
440 "VMOVSDrr",
441 "VMOVSHDUPYrr",
442 "VMOVSHDUPrr",
443 "VMOVSLDUPYrr",
444 "VMOVSLDUPrr",
445 "VMOVSSrr",
446 "VMOVUPDYrr",
447 "VMOVUPDrr",
448 "VMOVUPSYrr",
449 "VMOVUPSrr",
450 "VORPDYrr",
451 "VORPDrr",
452 "VORPSYrr",
453 "VORPSrr",
454 "VPACKSSDWYrr",
455 "VPACKSSDWrr",
456 "VPACKSSWBYrr",
457 "VPACKSSWBrr",
458 "VPACKUSDWYrr",
459 "VPACKUSDWrr",
460 "VPACKUSWBYrr",
461 "VPACKUSWBrr",
462 "VPALIGNRYrri",
463 "VPALIGNRrri",
464 "VPBLENDWYrri",
465 "VPBLENDWrri",
466 "VPBROADCASTDrr",
467 "VPBROADCASTQrr",
468 "VPERMILPDYri",
469 "VPERMILPDYrr",
470 "VPERMILPDri",
471 "VPERMILPDrr",
472 "VPERMILPSYri",
473 "VPERMILPSYrr",
474 "VPERMILPSri",
475 "VPERMILPSrr",
476 "VPMOVSXBDrr",
477 "VPMOVSXBQrr",
478 "VPMOVSXBWrr",
479 "VPMOVSXDQrr",
480 "VPMOVSXWDrr",
481 "VPMOVSXWQrr",
482 "VPMOVZXBDrr",
483 "VPMOVZXBQrr",
484 "VPMOVZXBWrr",
485 "VPMOVZXDQrr",
486 "VPMOVZXWDrr",
487 "VPMOVZXWQrr",
488 "VPSHUFBYrr",
489 "VPSHUFBrr",
490 "VPSHUFDYri",
491 "VPSHUFDri",
492 "VPSHUFHWYri",
493 "VPSHUFHWri",
494 "VPSHUFLWYri",
495 "VPSHUFLWri",
496 "VPSLLDQYri",
497 "VPSLLDQri",
498 "VPSRLDQYri",
499 "VPSRLDQri",
500 "VPUNPCKHBWYrr",
501 "VPUNPCKHBWrr",
502 "VPUNPCKHDQYrr",
503 "VPUNPCKHDQrr",
504 "VPUNPCKHQDQYrr",
505 "VPUNPCKHQDQrr",
506 "VPUNPCKHWDYrr",
507 "VPUNPCKHWDrr",
508 "VPUNPCKLBWYrr",
509 "VPUNPCKLBWrr",
510 "VPUNPCKLDQYrr",
511 "VPUNPCKLDQrr",
512 "VPUNPCKLQDQYrr",
513 "VPUNPCKLQDQrr",
514 "VPUNPCKLWDYrr",
515 "VPUNPCKLWDrr",
516 "VSHUFPDYrri",
517 "VSHUFPDrri",
518 "VSHUFPSYrri",
519 "VSHUFPSrri",
520 "VUNPCKHPDYrr",
521 "VUNPCKHPDrr",
522 "VUNPCKHPSYrr",
523 "VUNPCKHPSrr",
524 "VUNPCKLPDYrr",
525 "VUNPCKLPDrr",
526 "VUNPCKLPSYrr",
527 "VUNPCKLPSrr",
528 "VXORPDYrr",
529 "VXORPDrr",
530 "VXORPSYrr",
531 "VXORPSrr",
532 "XORPDrr",
533 "XORPSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]534
535def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
536 let Latency = 1;
537 let NumMicroOps = 1;
538 let ResourceCycles = [1];
539}
540def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
541
542def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
543 let Latency = 1;
544 let NumMicroOps = 1;
545 let ResourceCycles = [1];
546}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]547def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
548 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]549
550def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
551 let Latency = 1;
552 let NumMicroOps = 1;
553 let ResourceCycles = [1];
554}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]555def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
556 "ADC(16|32|64)i",
557 "ADC(8|16|32|64)rr",
558 "ADCX(32|64)rr",
559 "ADOX(32|64)rr",
560 "BT(16|32|64)ri8",
561 "BT(16|32|64)rr",
562 "BTC(16|32|64)ri8",
563 "BTC(16|32|64)rr",
564 "BTR(16|32|64)ri8",
565 "BTR(16|32|64)rr",
566 "BTS(16|32|64)ri8",
567 "BTS(16|32|64)rr",
568 "CDQ",
569 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
570 "CQO",
571 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
572 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
573 "JMP_1",
574 "JMP_4",
575 "RORX(32|64)ri",
576 "SAR(8|16|32|64)r1",
577 "SAR(8|16|32|64)ri",
578 "SARX(32|64)rr",
579 "SBB(16|32|64)ri",
580 "SBB(16|32|64)i",
581 "SBB(8|16|32|64)rr",
582 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
583 "SHL(8|16|32|64)r1",
584 "SHL(8|16|32|64)ri",
585 "SHLX(32|64)rr",
586 "SHR(8|16|32|64)r1",
587 "SHR(8|16|32|64)ri",
588 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]589
590def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
591 let Latency = 1;
592 let NumMicroOps = 1;
593 let ResourceCycles = [1];
594}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]595def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
596 "BLSI(32|64)rr",
597 "BLSMSK(32|64)rr",
598 "BLSR(32|64)rr",
599 "BZHI(32|64)rr",
600 "LEA(16|32|64)(_32)?r",
601 "MMX_PABSBrr",
602 "MMX_PABSDrr",
603 "MMX_PABSWrr",
604 "MMX_PADDBirr",
605 "MMX_PADDDirr",
606 "MMX_PADDQirr",
607 "MMX_PADDSBirr",
608 "MMX_PADDSWirr",
609 "MMX_PADDUSBirr",
610 "MMX_PADDUSWirr",
611 "MMX_PADDWirr",
612 "MMX_PAVGBirr",
613 "MMX_PAVGWirr",
614 "MMX_PCMPEQBirr",
615 "MMX_PCMPEQDirr",
616 "MMX_PCMPEQWirr",
617 "MMX_PCMPGTBirr",
618 "MMX_PCMPGTDirr",
619 "MMX_PCMPGTWirr",
620 "MMX_PMAXSWirr",
621 "MMX_PMAXUBirr",
622 "MMX_PMINSWirr",
623 "MMX_PMINUBirr",
624 "MMX_PSIGNBrr",
625 "MMX_PSIGNDrr",
626 "MMX_PSIGNWrr",
627 "MMX_PSUBBirr",
628 "MMX_PSUBDirr",
629 "MMX_PSUBQirr",
630 "MMX_PSUBSBirr",
631 "MMX_PSUBSWirr",
632 "MMX_PSUBUSBirr",
633 "MMX_PSUBUSWirr",
634 "MMX_PSUBWirr",
635 "PABSBrr",
636 "PABSDrr",
637 "PABSWrr",
638 "PADDBrr",
639 "PADDDrr",
640 "PADDQrr",
641 "PADDSBrr",
642 "PADDSWrr",
643 "PADDUSBrr",
644 "PADDUSWrr",
645 "PADDWrr",
646 "PAVGBrr",
647 "PAVGWrr",
648 "PCMPEQBrr",
649 "PCMPEQDrr",
650 "PCMPEQQrr",
651 "PCMPEQWrr",
652 "PCMPGTBrr",
653 "PCMPGTDrr",
654 "PCMPGTWrr",
655 "PMAXSBrr",
656 "PMAXSDrr",
657 "PMAXSWrr",
658 "PMAXUBrr",
659 "PMAXUDrr",
660 "PMAXUWrr",
661 "PMINSBrr",
662 "PMINSDrr",
663 "PMINSWrr",
664 "PMINUBrr",
665 "PMINUDrr",
666 "PMINUWrr",
667 "PSIGNBrr",
668 "PSIGNDrr",
669 "PSIGNWrr",
670 "PSUBBrr",
671 "PSUBDrr",
672 "PSUBQrr",
673 "PSUBSBrr",
674 "PSUBSWrr",
675 "PSUBUSBrr",
676 "PSUBUSWrr",
677 "PSUBWrr",
678 "VPABSBYrr",
679 "VPABSBrr",
680 "VPABSDYrr",
681 "VPABSDrr",
682 "VPABSWYrr",
683 "VPABSWrr",
684 "VPADDBYrr",
685 "VPADDBrr",
686 "VPADDDYrr",
687 "VPADDDrr",
688 "VPADDQYrr",
689 "VPADDQrr",
690 "VPADDSBYrr",
691 "VPADDSBrr",
692 "VPADDSWYrr",
693 "VPADDSWrr",
694 "VPADDUSBYrr",
695 "VPADDUSBrr",
696 "VPADDUSWYrr",
697 "VPADDUSWrr",
698 "VPADDWYrr",
699 "VPADDWrr",
700 "VPAVGBYrr",
701 "VPAVGBrr",
702 "VPAVGWYrr",
703 "VPAVGWrr",
704 "VPCMPEQBYrr",
705 "VPCMPEQBrr",
706 "VPCMPEQDYrr",
707 "VPCMPEQDrr",
708 "VPCMPEQQYrr",
709 "VPCMPEQQrr",
710 "VPCMPEQWYrr",
711 "VPCMPEQWrr",
712 "VPCMPGTBYrr",
713 "VPCMPGTBrr",
714 "VPCMPGTDYrr",
715 "VPCMPGTDrr",
716 "VPCMPGTWYrr",
717 "VPCMPGTWrr",
718 "VPMAXSBYrr",
719 "VPMAXSBrr",
720 "VPMAXSDYrr",
721 "VPMAXSDrr",
722 "VPMAXSWYrr",
723 "VPMAXSWrr",
724 "VPMAXUBYrr",
725 "VPMAXUBrr",
726 "VPMAXUDYrr",
727 "VPMAXUDrr",
728 "VPMAXUWYrr",
729 "VPMAXUWrr",
730 "VPMINSBYrr",
731 "VPMINSBrr",
732 "VPMINSDYrr",
733 "VPMINSDrr",
734 "VPMINSWYrr",
735 "VPMINSWrr",
736 "VPMINUBYrr",
737 "VPMINUBrr",
738 "VPMINUDYrr",
739 "VPMINUDrr",
740 "VPMINUWYrr",
741 "VPMINUWrr",
742 "VPSIGNBYrr",
743 "VPSIGNBrr",
744 "VPSIGNDYrr",
745 "VPSIGNDrr",
746 "VPSIGNWYrr",
747 "VPSIGNWrr",
748 "VPSUBBYrr",
749 "VPSUBBrr",
750 "VPSUBDYrr",
751 "VPSUBDrr",
752 "VPSUBQYrr",
753 "VPSUBQrr",
754 "VPSUBSBYrr",
755 "VPSUBSBrr",
756 "VPSUBSWYrr",
757 "VPSUBSWrr",
758 "VPSUBUSBYrr",
759 "VPSUBUSBrr",
760 "VPSUBUSWYrr",
761 "VPSUBUSWrr",
762 "VPSUBWYrr",
763 "VPSUBWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]764
765def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
766 let Latency = 1;
767 let NumMicroOps = 1;
768 let ResourceCycles = [1];
769}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]770def: InstRW<[BWWriteResGroup8], (instregex "BLENDPDrri",
771 "BLENDPSrri",
772 "MMX_MOVQ64rr",
773 "MMX_PANDNirr",
774 "MMX_PANDirr",
775 "MMX_PORirr",
776 "MMX_PXORirr",
777 "MOVDQArr",
778 "MOVDQUrr",
779 "MOVPQI2QIrr",
780 "PANDNrr",
781 "PANDrr",
782 "PORrr",
783 "PXORrr",
784 "VBLENDPDYrri",
785 "VBLENDPDrri",
786 "VBLENDPSYrri",
787 "VBLENDPSrri",
788 "VMOVDQAYrr",
789 "VMOVDQArr",
790 "VMOVDQUYrr",
791 "VMOVDQUrr",
792 "VMOVPQI2QIrr",
793 "VMOVZPQILo2PQIrr",
794 "VPANDNYrr",
795 "VPANDNrr",
796 "VPANDYrr",
797 "VPANDrr",
798 "VPBLENDDYrri",
799 "VPBLENDDrri",
800 "VPORYrr",
801 "VPORrr",
802 "VPXORYrr",
803 "VPXORrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]804
805def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
806 let Latency = 1;
807 let NumMicroOps = 1;
808 let ResourceCycles = [1];
809}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]810def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]811def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
812 "ADD(8|16|32|64)rr",
813 "ADD(8|16|32|64)i",
814 "AND(8|16|32|64)ri",
815 "AND(8|16|32|64)rr",
816 "AND(8|16|32|64)i",
817 "CBW",
818 "CLC",
819 "CMC",
820 "CMP(8|16|32|64)ri",
821 "CMP(8|16|32|64)rr",
822 "CMP(8|16|32|64)i",
823 "DEC(8|16|32|64)r",
824 "INC(8|16|32|64)r",
825 "LAHF",
826 "MOV(8|16|32|64)rr",
827 "MOV(8|16|32|64)ri",
828 "MOVSX(16|32|64)rr16",
829 "MOVSX(16|32|64)rr32",
830 "MOVSX(16|32|64)rr8",
831 "MOVZX(16|32|64)rr16",
832 "MOVZX(16|32|64)rr8",
833 "NEG(8|16|32|64)r",
834 "NOOP",
835 "NOT(8|16|32|64)r",
836 "OR(8|16|32|64)ri",
837 "OR(8|16|32|64)rr",
838 "OR(8|16|32|64)i",
839 "SAHF",
840 "SGDT64m",
841 "SIDT64m",
842 "SLDT64m",
843 "SMSW16m",
844 "STC",
845 "STRm",
846 "SUB(8|16|32|64)ri",
847 "SUB(8|16|32|64)rr",
848 "SUB(8|16|32|64)i",
849 "SYSCALL",
850 "TEST(8|16|32|64)rr",
851 "TEST(8|16|32|64)i",
852 "TEST(8|16|32|64)ri",
853 "XCHG(16|32|64)rr",
854 "XOR(8|16|32|64)ri",
855 "XOR(8|16|32|64)rr",
856 "XOR(8|16|32|64)i")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]857
858def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
859 let Latency = 1;
860 let NumMicroOps = 2;
861 let ResourceCycles = [1,1];
862}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]863def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
864 "MMX_MOVD64from64rm",
865 "MMX_MOVD64mr",
866 "MMX_MOVNTQmr",
867 "MMX_MOVQ64mr",
868 "MOV(16|32|64)mr",
869 "MOV8mi",
870 "MOV8mr",
871 "MOVAPDmr",
872 "MOVAPSmr",
873 "MOVDQAmr",
874 "MOVDQUmr",
875 "MOVHPDmr",
876 "MOVHPSmr",
877 "MOVLPDmr",
878 "MOVLPSmr",
879 "MOVNTDQmr",
880 "MOVNTI_64mr",
881 "MOVNTImr",
882 "MOVNTPDmr",
883 "MOVNTPSmr",
884 "MOVPDI2DImr",
885 "MOVPQI2QImr",
886 "MOVPQIto64mr",
887 "MOVSDmr",
888 "MOVSSmr",
889 "MOVUPDmr",
890 "MOVUPSmr",
891 "ST_FP32m",
892 "ST_FP64m",
893 "ST_FP80m",
894 "VEXTRACTF128mr",
895 "VEXTRACTI128mr",
896 "VMOVAPDYmr",
897 "VMOVAPDmr",
898 "VMOVAPSYmr",
899 "VMOVAPSmr",
900 "VMOVDQAYmr",
901 "VMOVDQAmr",
902 "VMOVDQUYmr",
903 "VMOVDQUmr",
904 "VMOVHPDmr",
905 "VMOVHPSmr",
906 "VMOVLPDmr",
907 "VMOVLPSmr",
908 "VMOVNTDQYmr",
909 "VMOVNTDQmr",
910 "VMOVNTPDYmr",
911 "VMOVNTPDmr",
912 "VMOVNTPSYmr",
913 "VMOVNTPSmr",
914 "VMOVPDI2DImr",
915 "VMOVPQI2QImr",
916 "VMOVPQIto64mr",
917 "VMOVSDmr",
918 "VMOVSSmr",
919 "VMOVUPDYmr",
920 "VMOVUPDmr",
921 "VMOVUPSYmr",
922 "VMOVUPSmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]923
924def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
925 let Latency = 2;
926 let NumMicroOps = 2;
927 let ResourceCycles = [2];
928}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]929def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
930 "BLENDVPSrr0",
931 "MMX_PINSRWrr",
932 "PBLENDVBrr0",
933 "PINSRBrr",
934 "PINSRDrr",
935 "PINSRQrr",
936 "PINSRWrr",
937 "VBLENDVPDYrr",
938 "VBLENDVPDrr",
939 "VBLENDVPSYrr",
940 "VBLENDVPSrr",
941 "VPBLENDVBYrr",
942 "VPBLENDVBrr",
943 "VPINSRBrr",
944 "VPINSRDrr",
945 "VPINSRQrr",
946 "VPINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]947
948def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
949 let Latency = 2;
950 let NumMicroOps = 2;
951 let ResourceCycles = [2];
952}
953def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
954
955def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
956 let Latency = 2;
957 let NumMicroOps = 2;
958 let ResourceCycles = [2];
959}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]960def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
961 "ROL(8|16|32|64)ri",
962 "ROR(8|16|32|64)r1",
963 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]964
965def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
966 let Latency = 2;
967 let NumMicroOps = 2;
968 let ResourceCycles = [2];
969}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]970def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
971 "MFENCE",
972 "WAIT",
973 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]974
975def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
976 let Latency = 2;
977 let NumMicroOps = 2;
978 let ResourceCycles = [1,1];
979}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]980def: InstRW<[BWWriteResGroup15], (instregex "CVTPS2PDrr",
981 "CVTSS2SDrr",
982 "EXTRACTPSrr",
983 "MMX_PEXTRWrr",
984 "PEXTRBrr",
985 "PEXTRDrr",
986 "PEXTRQrr",
987 "PEXTRWrr",
988 "PSLLDrr",
989 "PSLLQrr",
990 "PSLLWrr",
991 "PSRADrr",
992 "PSRAWrr",
993 "PSRLDrr",
994 "PSRLQrr",
995 "PSRLWrr",
996 "PTESTrr",
997 "VCVTPH2PSYrr",
998 "VCVTPH2PSrr",
999 "VCVTPS2PDrr",
1000 "VCVTSS2SDrr",
1001 "VEXTRACTPSrr",
1002 "VPEXTRBrr",
1003 "VPEXTRDrr",
1004 "VPEXTRQrr",
1005 "VPEXTRWrr",
1006 "VPSLLDrr",
1007 "VPSLLQrr",
1008 "VPSLLWrr",
1009 "VPSRADrr",
1010 "VPSRAWrr",
1011 "VPSRLDrr",
1012 "VPSRLQrr",
1013 "VPSRLWrr",
1014 "VPTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1015
1016def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
1017 let Latency = 2;
1018 let NumMicroOps = 2;
1019 let ResourceCycles = [1,1];
1020}
1021def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
1022
1023def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
1024 let Latency = 2;
1025 let NumMicroOps = 2;
1026 let ResourceCycles = [1,1];
1027}
1028def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
1029
1030def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
1031 let Latency = 2;
1032 let NumMicroOps = 2;
1033 let ResourceCycles = [1,1];
1034}
1035def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
1036
1037def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
1038 let Latency = 2;
1039 let NumMicroOps = 2;
1040 let ResourceCycles = [1,1];
1041}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1042def: InstRW<[BWWriteResGroup19], (instregex "BEXTR(32|64)rr",
1043 "BSWAP(16|32|64)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1044
1045def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
1046 let Latency = 2;
1047 let NumMicroOps = 2;
1048 let ResourceCycles = [1,1];
1049}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1050def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]1051def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1052def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
1053 "ADC8ri",
1054 "CMOV(A|BE)(16|32|64)rr",
1055 "SBB8i8",
1056 "SBB8ri",
1057 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1058
1059def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
1060 let Latency = 2;
1061 let NumMicroOps = 3;
1062 let ResourceCycles = [1,1,1];
1063}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1064def: InstRW<[BWWriteResGroup21], (instregex "EXTRACTPSmr",
1065 "PEXTRBmr",
1066 "PEXTRDmr",
1067 "PEXTRQmr",
1068 "PEXTRWmr",
1069 "STMXCSR",
1070 "VEXTRACTPSmr",
1071 "VPEXTRBmr",
1072 "VPEXTRDmr",
1073 "VPEXTRQmr",
1074 "VPEXTRWmr",
1075 "VSTMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1076
1077def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
1078 let Latency = 2;
1079 let NumMicroOps = 3;
1080 let ResourceCycles = [1,1,1];
1081}
1082def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
1083
1084def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
1085 let Latency = 2;
1086 let NumMicroOps = 3;
1087 let ResourceCycles = [1,1,1];
1088}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1089def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1090
1091def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
1092 let Latency = 2;
1093 let NumMicroOps = 3;
1094 let ResourceCycles = [1,1,1];
1095}
1096def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
1097
1098def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1099 let Latency = 2;
1100 let NumMicroOps = 3;
1101 let ResourceCycles = [1,1,1];
1102}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1103def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1104def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
1105 "PUSH64i8",
1106 "STOSB",
1107 "STOSL",
1108 "STOSQ",
1109 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1110
1111def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> {
1112 let Latency = 3;
1113 let NumMicroOps = 1;
1114 let ResourceCycles = [1];
1115}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1116def: InstRW<[BWWriteResGroup26], (instregex "MOVMSKPDrr",
1117 "MOVMSKPSrr",
1118 "PMOVMSKBrr",
1119 "VMOVMSKPDYrr",
1120 "VMOVMSKPDrr",
1121 "VMOVMSKPSYrr",
1122 "VMOVMSKPSrr",
1123 "VPMOVMSKBYrr",
1124 "VPMOVMSKBrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1125
1126def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
1127 let Latency = 3;
1128 let NumMicroOps = 1;
1129 let ResourceCycles = [1];
1130}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1131def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1132def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
1133def: InstRW<[BWWriteResGroup27], (instregex "ADDPDrr",
1134 "ADDPSrr",
1135 "ADDSDrr",
1136 "ADDSSrr",
1137 "ADDSUBPDrr",
1138 "ADDSUBPSrr",
1139 "ADD_FPrST0",
1140 "ADD_FST0r",
1141 "ADD_FrST0",
1142 "BSF(16|32|64)rr",
1143 "BSR(16|32|64)rr",
1144 "CMPPDrri",
1145 "CMPPSrri",
1146 "CMPSDrr",
1147 "CMPSSrr",
1148 "COMISDrr",
1149 "COMISSrr",
1150 "CVTDQ2PSrr",
1151 "CVTPS2DQrr",
1152 "CVTTPS2DQrr",
1153 "LZCNT(16|32|64)rr",
1154 "MAX(C?)PDrr",
1155 "MAX(C?)PSrr",
1156 "MAX(C?)SDrr",
1157 "MAX(C?)SSrr",
1158 "MIN(C?)PDrr",
1159 "MIN(C?)PSrr",
1160 "MIN(C?)SDrr",
1161 "MIN(C?)SSrr",
1162 "MMX_CVTPI2PSirr",
1163 "PDEP(32|64)rr",
1164 "PEXT(32|64)rr",
1165 "POPCNT(16|32|64)rr",
1166 "SHLD(16|32|64)rri8",
1167 "SHRD(16|32|64)rri8",
1168 "SUBPDrr",
1169 "SUBPSrr",
1170 "SUBR_FPrST0",
1171 "SUBR_FST0r",
1172 "SUBR_FrST0",
1173 "SUBSDrr",
1174 "SUBSSrr",
1175 "SUB_FPrST0",
1176 "SUB_FST0r",
1177 "SUB_FrST0",
1178 "TZCNT(16|32|64)rr",
1179 "UCOMISDrr",
1180 "UCOMISSrr",
1181 "VADDPDYrr",
1182 "VADDPDrr",
1183 "VADDPSYrr",
1184 "VADDPSrr",
1185 "VADDSDrr",
1186 "VADDSSrr",
1187 "VADDSUBPDYrr",
1188 "VADDSUBPDrr",
1189 "VADDSUBPSYrr",
1190 "VADDSUBPSrr",
1191 "VCMPPDYrri",
1192 "VCMPPDrri",
1193 "VCMPPSYrri",
1194 "VCMPPSrri",
1195 "VCMPSDrr",
1196 "VCMPSSrr",
1197 "VCOMISDrr",
1198 "VCOMISSrr",
1199 "VCVTDQ2PSYrr",
1200 "VCVTDQ2PSrr",
1201 "VCVTPS2DQYrr",
1202 "VCVTPS2DQrr",
1203 "VCVTTPS2DQYrr",
1204 "VCVTTPS2DQrr",
1205 "VMAX(C?)PDYrr",
1206 "VMAX(C?)PDrr",
1207 "VMAX(C?)PSYrr",
1208 "VMAX(C?)PSrr",
1209 "VMAX(C?)SDrr",
1210 "VMAX(C?)SSrr",
1211 "VMIN(C?)PDYrr",
1212 "VMIN(C?)PDrr",
1213 "VMIN(C?)PSYrr",
1214 "VMIN(C?)PSrr",
1215 "VMIN(C?)SDrr",
1216 "VMIN(C?)SSrr",
1217 "VSUBPDYrr",
1218 "VSUBPDrr",
1219 "VSUBPSYrr",
1220 "VSUBPSrr",
1221 "VSUBSDrr",
1222 "VSUBSSrr",
1223 "VUCOMISDrr",
1224 "VUCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1225
1226def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
1227 let Latency = 3;
1228 let NumMicroOps = 2;
1229 let ResourceCycles = [1,1];
1230}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1231def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1232
1233def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
1234 let Latency = 3;
1235 let NumMicroOps = 1;
1236 let ResourceCycles = [1];
1237}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1238def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
1239 "VBROADCASTSSYrr",
1240 "VEXTRACTF128rr",
1241 "VEXTRACTI128rr",
1242 "VINSERTF128rr",
1243 "VINSERTI128rr",
1244 "VPBROADCASTBYrr",
1245 "VPBROADCASTBrr",
1246 "VPBROADCASTDYrr",
1247 "VPBROADCASTQYrr",
1248 "VPBROADCASTWYrr",
1249 "VPBROADCASTWrr",
1250 "VPERM2F128rr",
1251 "VPERM2I128rr",
1252 "VPERMDYrr",
1253 "VPERMPDYri",
1254 "VPERMPSYrr",
1255 "VPERMQYri",
1256 "VPMOVSXBDYrr",
1257 "VPMOVSXBQYrr",
1258 "VPMOVSXBWYrr",
1259 "VPMOVSXDQYrr",
1260 "VPMOVSXWDYrr",
1261 "VPMOVSXWQYrr",
1262 "VPMOVZXBDYrr",
1263 "VPMOVZXBQYrr",
1264 "VPMOVZXBWYrr",
1265 "VPMOVZXDQYrr",
1266 "VPMOVZXWDYrr",
1267 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1268
1269def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
1270 let Latency = 3;
1271 let NumMicroOps = 1;
1272 let ResourceCycles = [1];
1273}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1274def: InstRW<[BWWriteResGroup29], (instregex "MULPDrr",
1275 "MULPSrr",
1276 "MULSDrr",
1277 "MULSSrr",
1278 "VMULPDYrr",
1279 "VMULPDrr",
1280 "VMULPSYrr",
1281 "VMULPSrr",
1282 "VMULSDrr",
1283 "VMULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1284
1285def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
1286 let Latency = 3;
1287 let NumMicroOps = 3;
1288 let ResourceCycles = [3];
1289}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1290def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
1291 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1292
1293def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
1294 let Latency = 3;
1295 let NumMicroOps = 3;
1296 let ResourceCycles = [2,1];
1297}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1298def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVDYrr",
1299 "VPSLLVDrr",
1300 "VPSRAVDYrr",
1301 "VPSRAVDrr",
1302 "VPSRLVDYrr",
1303 "VPSRLVDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1304
1305def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
1306 let Latency = 3;
1307 let NumMicroOps = 3;
1308 let ResourceCycles = [2,1];
1309}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1310def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
1311 "MMX_PHADDSWrr",
1312 "MMX_PHADDWrr",
1313 "MMX_PHSUBDrr",
1314 "MMX_PHSUBSWrr",
1315 "MMX_PHSUBWrr",
1316 "PHADDDrr",
1317 "PHADDSWrr",
1318 "PHADDWrr",
1319 "PHSUBDrr",
1320 "PHSUBSWrr",
1321 "PHSUBWrr",
1322 "VPHADDDYrr",
1323 "VPHADDDrr",
1324 "VPHADDSWYrr",
1325 "VPHADDSWrr",
1326 "VPHADDWYrr",
1327 "VPHADDWrr",
1328 "VPHSUBDYrr",
1329 "VPHSUBDrr",
1330 "VPHSUBSWYrr",
1331 "VPHSUBSWrr",
1332 "VPHSUBWYrr",
1333 "VPHSUBWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1334
1335def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
1336 let Latency = 3;
1337 let NumMicroOps = 3;
1338 let ResourceCycles = [2,1];
1339}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1340def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
1341 "MMX_PACKSSWBirr",
1342 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1343
1344def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
1345 let Latency = 3;
1346 let NumMicroOps = 3;
1347 let ResourceCycles = [1,2];
1348}
1349def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
1350
1351def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
1352 let Latency = 3;
1353 let NumMicroOps = 3;
1354 let ResourceCycles = [1,2];
1355}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1356def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
1357 "RCL(8|16|32|64)ri",
1358 "RCR(8|16|32|64)r1",
1359 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1360
1361def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
1362 let Latency = 3;
1363 let NumMicroOps = 3;
1364 let ResourceCycles = [2,1];
1365}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1366def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
1367 "ROR(8|16|32|64)rCL",
1368 "SAR(8|16|32|64)rCL",
1369 "SHL(8|16|32|64)rCL",
1370 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1371
1372def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
1373 let Latency = 3;
1374 let NumMicroOps = 4;
1375 let ResourceCycles = [1,1,1,1];
1376}
1377def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1378
1379def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1380 let Latency = 3;
1381 let NumMicroOps = 4;
1382 let ResourceCycles = [1,1,1,1];
1383}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1384def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1385 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1386
1387def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1388 let Latency = 4;
1389 let NumMicroOps = 2;
1390 let ResourceCycles = [1,1];
1391}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1392def: InstRW<[BWWriteResGroup39], (instregex "CVTSD2SI64rr",
1393 "CVTSD2SIrr",
1394 "CVTSS2SI64rr",
1395 "CVTSS2SIrr",
1396 "CVTTSD2SI64rr",
1397 "CVTTSD2SIrr",
1398 "CVTTSS2SI64rr",
1399 "CVTTSS2SIrr",
1400 "VCVTSD2SI64rr",
1401 "VCVTSD2SIrr",
1402 "VCVTSS2SI64rr",
1403 "VCVTSS2SIrr",
1404 "VCVTTSD2SI64rr",
1405 "VCVTTSD2SIrr",
1406 "VCVTTSS2SI64rr",
1407 "VCVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1408
1409def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1410 let Latency = 4;
1411 let NumMicroOps = 2;
1412 let ResourceCycles = [1,1];
1413}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1414def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1415 "VPSLLDYrr",
1416 "VPSLLQYrr",
1417 "VPSLLWYrr",
1418 "VPSRADYrr",
1419 "VPSRAWYrr",
1420 "VPSRLDYrr",
1421 "VPSRLQYrr",
1422 "VPSRLWYrr",
1423 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1424
1425def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1426 let Latency = 4;
1427 let NumMicroOps = 2;
1428 let ResourceCycles = [1,1];
1429}
1430def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1431
1432def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1433 let Latency = 4;
1434 let NumMicroOps = 2;
1435 let ResourceCycles = [1,1];
1436}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1437def: InstRW<[BWWriteResGroup42], (instrs IMUL32r, IMUL64r, MUL32r, MUL64r)>;
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1438def: InstRW<[BWWriteResGroup42], (instrs MULX64rr)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1439def: InstRW<[BWWriteResGroup42], (instregex "CVTDQ2PDrr",
1440 "CVTPD2DQrr",
1441 "CVTPD2PSrr",
1442 "CVTSD2SSrr",
1443 "CVTSI642SDrr",
1444 "CVTSI2SDrr",
1445 "CVTSI2SSrr",
1446 "CVTTPD2DQrr",
1447 "MMX_CVTPD2PIirr",
1448 "MMX_CVTPI2PDirr",
1449 "MMX_CVTPS2PIirr",
1450 "MMX_CVTTPD2PIirr",
1451 "MMX_CVTTPS2PIirr",
1452 "VCVTDQ2PDrr",
1453 "VCVTPD2DQrr",
1454 "VCVTPD2PSrr",
1455 "VCVTPS2PHrr",
1456 "VCVTSD2SSrr",
1457 "VCVTSI642SDrr",
1458 "VCVTSI2SDrr",
1459 "VCVTSI2SSrr",
1460 "VCVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1461
1462def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1463 let Latency = 4;
1464 let NumMicroOps = 4;
1465}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1466def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1467
1468def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1469 let Latency = 4;
1470 let NumMicroOps = 3;
1471 let ResourceCycles = [1,1,1];
1472}
1473def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1474
1475def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1476 let Latency = 4;
1477 let NumMicroOps = 3;
1478 let ResourceCycles = [1,1,1];
1479}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1480def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1481 "ISTT_FP32m",
1482 "ISTT_FP64m",
1483 "IST_F16m",
1484 "IST_F32m",
1485 "IST_FP16m",
1486 "IST_FP32m",
1487 "IST_FP64m",
1488 "VCVTPS2PHYmr",
1489 "VCVTPS2PHmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1490
1491def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1492 let Latency = 4;
1493 let NumMicroOps = 4;
1494 let ResourceCycles = [4];
1495}
1496def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1497
1498def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1499 let Latency = 4;
1500 let NumMicroOps = 4;
1501 let ResourceCycles = [1,3];
1502}
1503def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1504
1505def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1506 let Latency = 5;
1507 let NumMicroOps = 1;
1508 let ResourceCycles = [1];
1509}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1510def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1511 "MMX_PMADDWDirr",
1512 "MMX_PMULHRSWrr",
1513 "MMX_PMULHUWirr",
1514 "MMX_PMULHWirr",
1515 "MMX_PMULLWirr",
1516 "MMX_PMULUDQirr",
1517 "MMX_PSADBWirr",
1518 "MUL_FPrST0",
1519 "MUL_FST0r",
1520 "MUL_FrST0",
1521 "PCLMULQDQrr",
1522 "PCMPGTQrr",
1523 "PHMINPOSUWrr",
1524 "PMADDUBSWrr",
1525 "PMADDWDrr",
1526 "PMULDQrr",
1527 "PMULHRSWrr",
1528 "PMULHUWrr",
1529 "PMULHWrr",
1530 "PMULLWrr",
1531 "PMULUDQrr",
1532 "PSADBWrr",
1533 "RCPPSr",
1534 "RCPSSr",
1535 "RSQRTPSr",
1536 "RSQRTSSr",
1537 "VPCLMULQDQrr",
1538 "VPCMPGTQYrr",
1539 "VPCMPGTQrr",
1540 "VPHMINPOSUWrr",
1541 "VPMADDUBSWYrr",
1542 "VPMADDUBSWrr",
1543 "VPMADDWDYrr",
1544 "VPMADDWDrr",
1545 "VPMULDQYrr",
1546 "VPMULDQrr",
1547 "VPMULHRSWYrr",
1548 "VPMULHRSWrr",
1549 "VPMULHUWYrr",
1550 "VPMULHUWrr",
1551 "VPMULHWYrr",
1552 "VPMULHWrr",
1553 "VPMULLWYrr",
1554 "VPMULLWrr",
1555 "VPMULUDQYrr",
1556 "VPMULUDQrr",
1557 "VPSADBWYrr",
1558 "VPSADBWrr",
1559 "VRCPPSr",
1560 "VRCPSSr",
1561 "VRSQRTPSr",
1562 "VRSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1563
1564def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1565 let Latency = 5;
1566 let NumMicroOps = 1;
1567 let ResourceCycles = [1];
1568}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1569def: InstRW<[BWWriteResGroup48],
1570 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1571 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1572
1573def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1574 let Latency = 5;
1575 let NumMicroOps = 1;
1576 let ResourceCycles = [1];
1577}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1578def: InstRW<[BWWriteResGroup49], (instregex "LDDQUrm",
1579 "MMX_MOVD64rm",
1580 "MMX_MOVD64to64rm",
1581 "MMX_MOVQ64rm",
1582 "MOV(16|32|64)rm",
1583 "MOV64toPQIrm",
1584 "MOV8rm",
1585 "MOVAPDrm",
1586 "MOVAPSrm",
1587 "MOVDDUPrm",
1588 "MOVDI2PDIrm",
1589 "MOVDQArm",
1590 "MOVDQUrm",
1591 "MOVNTDQArm",
1592 "MOVQI2PQIrm",
1593 "MOVSDrm",
1594 "MOVSHDUPrm",
1595 "MOVSLDUPrm",
1596 "MOVSSrm",
1597 "MOVSX(16|32|64)rm16",
1598 "MOVSX(16|32|64)rm32",
1599 "MOVSX(16|32|64)rm8",
1600 "MOVUPDrm",
1601 "MOVUPSrm",
1602 "MOVZX(16|32|64)rm16",
1603 "MOVZX(16|32|64)rm8",
1604 "PREFETCHNTA",
1605 "PREFETCHT0",
1606 "PREFETCHT1",
1607 "PREFETCHT2",
1608 "VBROADCASTSSrm",
1609 "VLDDQUrm",
1610 "VMOV64toPQIrm",
1611 "VMOVAPDrm",
1612 "VMOVAPSrm",
1613 "VMOVDDUPrm",
1614 "VMOVDI2PDIrm",
1615 "VMOVDQArm",
1616 "VMOVDQUrm",
1617 "VMOVNTDQArm",
1618 "VMOVQI2PQIrm",
1619 "VMOVSDrm",
1620 "VMOVSHDUPrm",
1621 "VMOVSLDUPrm",
1622 "VMOVSSrm",
1623 "VMOVUPDrm",
1624 "VMOVUPSrm",
1625 "VPBROADCASTDrm",
1626 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1627
1628def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1629 let Latency = 5;
1630 let NumMicroOps = 3;
1631 let ResourceCycles = [1,2];
1632}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1633def: InstRW<[BWWriteResGroup50], (instregex "CVTSI642SSrr",
1634 "HADDPDrr",
1635 "HADDPSrr",
1636 "HSUBPDrr",
1637 "HSUBPSrr",
1638 "VCVTSI642SSrr",
1639 "VHADDPDYrr",
1640 "VHADDPDrr",
1641 "VHADDPSYrr",
1642 "VHADDPSrr",
1643 "VHSUBPDYrr",
1644 "VHSUBPDrr",
1645 "VHSUBPSYrr",
1646 "VHSUBPSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1647
1648def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1649 let Latency = 5;
1650 let NumMicroOps = 3;
1651 let ResourceCycles = [1,1,1];
1652}
1653def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1654
1655def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1656 let Latency = 5;
1657 let NumMicroOps = 3;
1658 let ResourceCycles = [1,1,1];
1659}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1660def: InstRW<[BWWriteResGroup52], (instrs MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1661
1662def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1663 let Latency = 5;
1664 let NumMicroOps = 4;
1665 let ResourceCycles = [1,1,1,1];
1666}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1667def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPDYmr",
1668 "VMASKMOVPDmr",
1669 "VMASKMOVPSYmr",
1670 "VMASKMOVPSmr",
1671 "VPMASKMOVDYmr",
1672 "VPMASKMOVDmr",
1673 "VPMASKMOVQYmr",
1674 "VPMASKMOVQmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1675
1676def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1677 let Latency = 5;
1678 let NumMicroOps = 5;
1679 let ResourceCycles = [1,4];
1680}
1681def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1682
1683def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1684 let Latency = 5;
1685 let NumMicroOps = 5;
1686 let ResourceCycles = [1,4];
1687}
1688def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1689
1690def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1691 let Latency = 5;
1692 let NumMicroOps = 5;
1693 let ResourceCycles = [2,3];
1694}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1695def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1696
1697def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1698 let Latency = 5;
1699 let NumMicroOps = 6;
1700 let ResourceCycles = [1,1,4];
1701}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1702def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1703
1704def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1705 let Latency = 6;
1706 let NumMicroOps = 1;
1707 let ResourceCycles = [1];
1708}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1709def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1710 "LD_F64m",
1711 "LD_F80m",
1712 "VBROADCASTF128",
1713 "VBROADCASTI128",
1714 "VBROADCASTSDYrm",
1715 "VBROADCASTSSYrm",
1716 "VLDDQUYrm",
1717 "VMOVAPDYrm",
1718 "VMOVAPSYrm",
1719 "VMOVDDUPYrm",
1720 "VMOVDQAYrm",
1721 "VMOVDQUYrm",
1722 "VMOVNTDQAYrm",
1723 "VMOVSHDUPYrm",
1724 "VMOVSLDUPYrm",
1725 "VMOVUPDYrm",
1726 "VMOVUPSYrm",
1727 "VPBROADCASTDYrm",
1728 "VPBROADCASTQYrm",
1729 "ROUNDPDr",
1730 "ROUNDPSr",
1731 "ROUNDSDr",
1732 "ROUNDSSr",
1733 "VROUNDPDr",
1734 "VROUNDPSr",
1735 "VROUNDSDr",
1736 "VROUNDSSr",
1737 "VROUNDYPDr",
1738 "VROUNDYPSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1739
1740def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1741 let Latency = 6;
1742 let NumMicroOps = 2;
1743 let ResourceCycles = [1,1];
1744}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1745def: InstRW<[BWWriteResGroup59], (instregex "CVTPS2PDrm",
1746 "CVTSS2SDrm",
1747 "MMX_PSLLDrm",
1748 "MMX_PSLLQrm",
1749 "MMX_PSLLWrm",
1750 "MMX_PSRADrm",
1751 "MMX_PSRAWrm",
1752 "MMX_PSRLDrm",
1753 "MMX_PSRLQrm",
1754 "MMX_PSRLWrm",
1755 "VCVTPH2PSYrm",
1756 "VCVTPH2PSrm",
1757 "VCVTPS2PDrm",
1758 "VCVTSS2SDrm",
1759 "VPSLLVQrm",
1760 "VPSRLVQrm",
1761 "VTESTPDrm",
1762 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1763
1764def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1765 let Latency = 6;
1766 let NumMicroOps = 2;
1767 let ResourceCycles = [1,1];
1768}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1769def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1770 "VCVTPD2DQYrr",
1771 "VCVTPD2PSYrr",
1772 "VCVTPS2PHYrr",
1773 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1774
1775def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1776 let Latency = 6;
1777 let NumMicroOps = 2;
1778 let ResourceCycles = [1,1];
1779}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1780def: InstRW<[BWWriteResGroup61], (instregex "ANDNPDrm",
1781 "ANDNPSrm",
1782 "ANDPDrm",
1783 "ANDPSrm",
1784 "INSERTPSrm",
1785 "MMX_PALIGNRrmi",
1786 "MMX_PINSRWrm",
1787 "MMX_PSHUFBrm",
1788 "MMX_PSHUFWmi",
1789 "MMX_PUNPCKHBWirm",
1790 "MMX_PUNPCKHDQirm",
1791 "MMX_PUNPCKHWDirm",
1792 "MMX_PUNPCKLBWirm",
1793 "MMX_PUNPCKLDQirm",
1794 "MMX_PUNPCKLWDirm",
1795 "MOVHPDrm",
1796 "MOVHPSrm",
1797 "MOVLPDrm",
1798 "MOVLPSrm",
1799 "ORPDrm",
1800 "ORPSrm",
1801 "PACKSSDWrm",
1802 "PACKSSWBrm",
1803 "PACKUSDWrm",
1804 "PACKUSWBrm",
1805 "PALIGNRrmi",
1806 "PBLENDWrmi",
1807 "PINSRBrm",
1808 "PINSRDrm",
1809 "PINSRQrm",
1810 "PINSRWrm",
1811 "PMOVSXBDrm",
1812 "PMOVSXBQrm",
1813 "PMOVSXBWrm",
1814 "PMOVSXDQrm",
1815 "PMOVSXWDrm",
1816 "PMOVSXWQrm",
1817 "PMOVZXBDrm",
1818 "PMOVZXBQrm",
1819 "PMOVZXBWrm",
1820 "PMOVZXDQrm",
1821 "PMOVZXWDrm",
1822 "PMOVZXWQrm",
1823 "PSHUFBrm",
1824 "PSHUFDmi",
1825 "PSHUFHWmi",
1826 "PSHUFLWmi",
1827 "PUNPCKHBWrm",
1828 "PUNPCKHDQrm",
1829 "PUNPCKHQDQrm",
1830 "PUNPCKHWDrm",
1831 "PUNPCKLBWrm",
1832 "PUNPCKLDQrm",
1833 "PUNPCKLQDQrm",
1834 "PUNPCKLWDrm",
1835 "SHUFPDrmi",
1836 "SHUFPSrmi",
1837 "UNPCKHPDrm",
1838 "UNPCKHPSrm",
1839 "UNPCKLPDrm",
1840 "UNPCKLPSrm",
1841 "VANDNPDrm",
1842 "VANDNPSrm",
1843 "VANDPDrm",
1844 "VANDPSrm",
1845 "VINSERTPSrm",
1846 "VMOVHPDrm",
1847 "VMOVHPSrm",
1848 "VMOVLPDrm",
1849 "VMOVLPSrm",
1850 "VORPDrm",
1851 "VORPSrm",
1852 "VPACKSSDWrm",
1853 "VPACKSSWBrm",
1854 "VPACKUSDWrm",
1855 "VPACKUSWBrm",
1856 "VPALIGNRrmi",
1857 "VPBLENDWrmi",
1858 "VPERMILPDmi",
1859 "VPERMILPDrm",
1860 "VPERMILPSmi",
1861 "VPERMILPSrm",
1862 "VPINSRBrm",
1863 "VPINSRDrm",
1864 "VPINSRQrm",
1865 "VPINSRWrm",
1866 "VPMOVSXBDrm",
1867 "VPMOVSXBQrm",
1868 "VPMOVSXBWrm",
1869 "VPMOVSXDQrm",
1870 "VPMOVSXWDrm",
1871 "VPMOVSXWQrm",
1872 "VPMOVZXBDrm",
1873 "VPMOVZXBQrm",
1874 "VPMOVZXBWrm",
1875 "VPMOVZXDQrm",
1876 "VPMOVZXWDrm",
1877 "VPMOVZXWQrm",
1878 "VPSHUFBrm",
1879 "VPSHUFDmi",
1880 "VPSHUFHWmi",
1881 "VPSHUFLWmi",
1882 "VPUNPCKHBWrm",
1883 "VPUNPCKHDQrm",
1884 "VPUNPCKHQDQrm",
1885 "VPUNPCKHWDrm",
1886 "VPUNPCKLBWrm",
1887 "VPUNPCKLDQrm",
1888 "VPUNPCKLQDQrm",
1889 "VPUNPCKLWDrm",
1890 "VSHUFPDrmi",
1891 "VSHUFPSrmi",
1892 "VUNPCKHPDrm",
1893 "VUNPCKHPSrm",
1894 "VUNPCKLPDrm",
1895 "VUNPCKLPSrm",
1896 "VXORPDrm",
1897 "VXORPSrm",
1898 "XORPDrm",
1899 "XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1900
1901def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1902 let Latency = 6;
1903 let NumMicroOps = 2;
1904 let ResourceCycles = [1,1];
1905}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1906def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1907 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1908
1909def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1910 let Latency = 6;
1911 let NumMicroOps = 2;
1912 let ResourceCycles = [1,1];
1913}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1914def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1915 "ADCX(32|64)rm",
1916 "ADOX(32|64)rm",
1917 "BT(16|32|64)mi8",
1918 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1919 "RORX(32|64)mi",
1920 "SARX(32|64)rm",
1921 "SBB(8|16|32|64)rm",
1922 "SHLX(32|64)rm",
1923 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1924
1925def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1926 let Latency = 6;
1927 let NumMicroOps = 2;
1928 let ResourceCycles = [1,1];
1929}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1930def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1931 "BLSI(32|64)rm",
1932 "BLSMSK(32|64)rm",
1933 "BLSR(32|64)rm",
1934 "BZHI(32|64)rm",
1935 "MMX_PABSBrm",
1936 "MMX_PABSDrm",
1937 "MMX_PABSWrm",
1938 "MMX_PADDBirm",
1939 "MMX_PADDDirm",
1940 "MMX_PADDQirm",
1941 "MMX_PADDSBirm",
1942 "MMX_PADDSWirm",
1943 "MMX_PADDUSBirm",
1944 "MMX_PADDUSWirm",
1945 "MMX_PADDWirm",
1946 "MMX_PAVGBirm",
1947 "MMX_PAVGWirm",
1948 "MMX_PCMPEQBirm",
1949 "MMX_PCMPEQDirm",
1950 "MMX_PCMPEQWirm",
1951 "MMX_PCMPGTBirm",
1952 "MMX_PCMPGTDirm",
1953 "MMX_PCMPGTWirm",
1954 "MMX_PMAXSWirm",
1955 "MMX_PMAXUBirm",
1956 "MMX_PMINSWirm",
1957 "MMX_PMINUBirm",
1958 "MMX_PSIGNBrm",
1959 "MMX_PSIGNDrm",
1960 "MMX_PSIGNWrm",
1961 "MMX_PSUBBirm",
1962 "MMX_PSUBDirm",
1963 "MMX_PSUBQirm",
1964 "MMX_PSUBSBirm",
1965 "MMX_PSUBSWirm",
1966 "MMX_PSUBUSBirm",
1967 "MMX_PSUBUSWirm",
1968 "MMX_PSUBWirm",
1969 "MOVBE(16|32|64)rm",
1970 "PABSBrm",
1971 "PABSDrm",
1972 "PABSWrm",
1973 "PADDBrm",
1974 "PADDDrm",
1975 "PADDQrm",
1976 "PADDSBrm",
1977 "PADDSWrm",
1978 "PADDUSBrm",
1979 "PADDUSWrm",
1980 "PADDWrm",
1981 "PAVGBrm",
1982 "PAVGWrm",
1983 "PCMPEQBrm",
1984 "PCMPEQDrm",
1985 "PCMPEQQrm",
1986 "PCMPEQWrm",
1987 "PCMPGTBrm",
1988 "PCMPGTDrm",
1989 "PCMPGTWrm",
1990 "PMAXSBrm",
1991 "PMAXSDrm",
1992 "PMAXSWrm",
1993 "PMAXUBrm",
1994 "PMAXUDrm",
1995 "PMAXUWrm",
1996 "PMINSBrm",
1997 "PMINSDrm",
1998 "PMINSWrm",
1999 "PMINUBrm",
2000 "PMINUDrm",
2001 "PMINUWrm",
2002 "PSIGNBrm",
2003 "PSIGNDrm",
2004 "PSIGNWrm",
2005 "PSUBBrm",
2006 "PSUBDrm",
2007 "PSUBQrm",
2008 "PSUBSBrm",
2009 "PSUBSWrm",
2010 "PSUBUSBrm",
2011 "PSUBUSWrm",
2012 "PSUBWrm",
2013 "VPABSBrm",
2014 "VPABSDrm",
2015 "VPABSWrm",
2016 "VPADDBrm",
2017 "VPADDDrm",
2018 "VPADDQrm",
2019 "VPADDSBrm",
2020 "VPADDSWrm",
2021 "VPADDUSBrm",
2022 "VPADDUSWrm",
2023 "VPADDWrm",
2024 "VPAVGBrm",
2025 "VPAVGWrm",
2026 "VPCMPEQBrm",
2027 "VPCMPEQDrm",
2028 "VPCMPEQQrm",
2029 "VPCMPEQWrm",
2030 "VPCMPGTBrm",
2031 "VPCMPGTDrm",
2032 "VPCMPGTWrm",
2033 "VPMAXSBrm",
2034 "VPMAXSDrm",
2035 "VPMAXSWrm",
2036 "VPMAXUBrm",
2037 "VPMAXUDrm",
2038 "VPMAXUWrm",
2039 "VPMINSBrm",
2040 "VPMINSDrm",
2041 "VPMINSWrm",
2042 "VPMINUBrm",
2043 "VPMINUDrm",
2044 "VPMINUWrm",
2045 "VPSIGNBrm",
2046 "VPSIGNDrm",
2047 "VPSIGNWrm",
2048 "VPSUBBrm",
2049 "VPSUBDrm",
2050 "VPSUBQrm",
2051 "VPSUBSBrm",
2052 "VPSUBSWrm",
2053 "VPSUBUSBrm",
2054 "VPSUBUSWrm",
2055 "VPSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2056
2057def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
2058 let Latency = 6;
2059 let NumMicroOps = 2;
2060 let ResourceCycles = [1,1];
2061}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2062def: InstRW<[BWWriteResGroup65], (instregex "BLENDPDrmi",
2063 "BLENDPSrmi",
2064 "MMX_PANDNirm",
2065 "MMX_PANDirm",
2066 "MMX_PORirm",
2067 "MMX_PXORirm",
2068 "PANDNrm",
2069 "PANDrm",
2070 "PORrm",
2071 "PXORrm",
2072 "VBLENDPDrmi",
2073 "VBLENDPSrmi",
2074 "VINSERTF128rm",
2075 "VINSERTI128rm",
2076 "VPANDNrm",
2077 "VPANDrm",
2078 "VPBLENDDrmi",
2079 "VPORrm",
2080 "VPXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2081
2082def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
2083 let Latency = 6;
2084 let NumMicroOps = 2;
2085 let ResourceCycles = [1,1];
2086}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2087def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2088def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
2089 "AND(8|16|32|64)rm",
2090 "CMP(8|16|32|64)mi",
2091 "CMP(8|16|32|64)mr",
2092 "CMP(8|16|32|64)rm",
2093 "OR(8|16|32|64)rm",
2094 "POP(16|32|64)rmr",
2095 "SUB(8|16|32|64)rm",
2096 "TEST(8|16|32|64)mr",
2097 "TEST(8|16|32|64)mi",
2098 "XOR(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2099
2100def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2101 let Latency = 6;
2102 let NumMicroOps = 4;
2103 let ResourceCycles = [1,1,2];
2104}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2105def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
2106 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2107
2108def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
2109 let Latency = 6;
2110 let NumMicroOps = 4;
2111 let ResourceCycles = [1,1,1,1];
2112}
2113def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
2114
2115def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
2116 let Latency = 6;
2117 let NumMicroOps = 4;
2118 let ResourceCycles = [1,1,1,1];
2119}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2120def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
2121 "BTR(16|32|64)mi8",
2122 "BTS(16|32|64)mi8",
2123 "SAR(8|16|32|64)m1",
2124 "SAR(8|16|32|64)mi",
2125 "SHL(8|16|32|64)m1",
2126 "SHL(8|16|32|64)mi",
2127 "SHR(8|16|32|64)m1",
2128 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2129
2130def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2131 let Latency = 6;
2132 let NumMicroOps = 4;
2133 let ResourceCycles = [1,1,1,1];
2134}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2135def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
2136 "ADD(8|16|32|64)mr",
2137 "AND(8|16|32|64)mi",
2138 "AND(8|16|32|64)mr",
2139 "DEC(8|16|32|64)m",
2140 "INC(8|16|32|64)m",
2141 "NEG(8|16|32|64)m",
2142 "NOT(8|16|32|64)m",
2143 "OR(8|16|32|64)mi",
2144 "OR(8|16|32|64)mr",
2145 "POP(16|32|64)rmm",
2146 "PUSH(16|32|64)rmm",
2147 "SUB(8|16|32|64)mi",
2148 "SUB(8|16|32|64)mr",
2149 "XOR(8|16|32|64)mi",
2150 "XOR(8|16|32|64)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2151
2152def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
2153 let Latency = 6;
2154 let NumMicroOps = 6;
2155 let ResourceCycles = [1,5];
2156}
2157def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
2158
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2159def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
2160 let Latency = 7;
2161 let NumMicroOps = 2;
2162 let ResourceCycles = [1,1];
2163}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2164def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
2165 "VPSLLQYrm",
2166 "VPSLLVQYrm",
2167 "VPSLLWYrm",
2168 "VPSRADYrm",
2169 "VPSRAWYrm",
2170 "VPSRLDYrm",
2171 "VPSRLQYrm",
2172 "VPSRLVQYrm",
2173 "VPSRLWYrm",
2174 "VTESTPDYrm",
2175 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2176
2177def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
2178 let Latency = 7;
2179 let NumMicroOps = 2;
2180 let ResourceCycles = [1,1];
2181}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2182def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
2183 "FCOM64m",
2184 "FCOMP32m",
2185 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2186
2187def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
2188 let Latency = 7;
2189 let NumMicroOps = 2;
2190 let ResourceCycles = [1,1];
2191}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2192def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
2193 "VANDNPSYrm",
2194 "VANDPDYrm",
2195 "VANDPSYrm",
2196 "VORPDYrm",
2197 "VORPSYrm",
2198 "VPACKSSDWYrm",
2199 "VPACKSSWBYrm",
2200 "VPACKUSDWYrm",
2201 "VPACKUSWBYrm",
2202 "VPALIGNRYrmi",
2203 "VPBLENDWYrmi",
2204 "VPERMILPDYmi",
2205 "VPERMILPDYrm",
2206 "VPERMILPSYmi",
2207 "VPERMILPSYrm",
2208 "VPSHUFBYrm",
2209 "VPSHUFDYmi",
2210 "VPSHUFHWYmi",
2211 "VPSHUFLWYmi",
2212 "VPUNPCKHBWYrm",
2213 "VPUNPCKHDQYrm",
2214 "VPUNPCKHQDQYrm",
2215 "VPUNPCKHWDYrm",
2216 "VPUNPCKLBWYrm",
2217 "VPUNPCKLDQYrm",
2218 "VPUNPCKLQDQYrm",
2219 "VPUNPCKLWDYrm",
2220 "VSHUFPDYrmi",
2221 "VSHUFPSYrmi",
2222 "VUNPCKHPDYrm",
2223 "VUNPCKHPSYrm",
2224 "VUNPCKLPDYrm",
2225 "VUNPCKLPSYrm",
2226 "VXORPDYrm",
2227 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2228
2229def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
2230 let Latency = 7;
2231 let NumMicroOps = 2;
2232 let ResourceCycles = [1,1];
2233}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2234def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
2235 "VPABSDYrm",
2236 "VPABSWYrm",
2237 "VPADDBYrm",
2238 "VPADDDYrm",
2239 "VPADDQYrm",
2240 "VPADDSBYrm",
2241 "VPADDSWYrm",
2242 "VPADDUSBYrm",
2243 "VPADDUSWYrm",
2244 "VPADDWYrm",
2245 "VPAVGBYrm",
2246 "VPAVGWYrm",
2247 "VPCMPEQBYrm",
2248 "VPCMPEQDYrm",
2249 "VPCMPEQQYrm",
2250 "VPCMPEQWYrm",
2251 "VPCMPGTBYrm",
2252 "VPCMPGTDYrm",
2253 "VPCMPGTWYrm",
2254 "VPMAXSBYrm",
2255 "VPMAXSDYrm",
2256 "VPMAXSWYrm",
2257 "VPMAXUBYrm",
2258 "VPMAXUDYrm",
2259 "VPMAXUWYrm",
2260 "VPMINSBYrm",
2261 "VPMINSDYrm",
2262 "VPMINSWYrm",
2263 "VPMINUBYrm",
2264 "VPMINUDYrm",
2265 "VPMINUWYrm",
2266 "VPSIGNBYrm",
2267 "VPSIGNDYrm",
2268 "VPSIGNWYrm",
2269 "VPSUBBYrm",
2270 "VPSUBDYrm",
2271 "VPSUBQYrm",
2272 "VPSUBSBYrm",
2273 "VPSUBSWYrm",
2274 "VPSUBUSBYrm",
2275 "VPSUBUSWYrm",
2276 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2277
2278def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
2279 let Latency = 7;
2280 let NumMicroOps = 2;
2281 let ResourceCycles = [1,1];
2282}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2283def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
2284 "VBLENDPSYrmi",
2285 "VPANDNYrm",
2286 "VPANDYrm",
2287 "VPBLENDDYrmi",
2288 "VPORYrm",
2289 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2290
2291def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
2292 let Latency = 7;
2293 let NumMicroOps = 3;
2294 let ResourceCycles = [1,2];
2295}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2296def: InstRW<[BWWriteResGroup78], (instregex "MPSADBWrri",
2297 "VMPSADBWYrri",
2298 "VMPSADBWrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2299
2300def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
2301 let Latency = 7;
2302 let NumMicroOps = 3;
2303 let ResourceCycles = [2,1];
2304}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2305def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
2306 "BLENDVPSrm0",
2307 "MMX_PACKSSDWirm",
2308 "MMX_PACKSSWBirm",
2309 "MMX_PACKUSWBirm",
2310 "PBLENDVBrm0",
2311 "VBLENDVPDrm",
2312 "VBLENDVPSrm",
2313 "VMASKMOVPDrm",
2314 "VMASKMOVPSrm",
2315 "VPBLENDVBrm",
2316 "VPMASKMOVDrm",
2317 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2318
2319def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
2320 let Latency = 7;
2321 let NumMicroOps = 3;
2322 let ResourceCycles = [1,2];
2323}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2324def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64",
2325 "SCASB",
2326 "SCASL",
2327 "SCASQ",
2328 "SCASW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2329
2330def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2331 let Latency = 7;
2332 let NumMicroOps = 3;
2333 let ResourceCycles = [1,1,1];
2334}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2335def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
2336 "PSLLQrm",
2337 "PSLLWrm",
2338 "PSRADrm",
2339 "PSRAWrm",
2340 "PSRLDrm",
2341 "PSRLQrm",
2342 "PSRLWrm",
2343 "PTESTrm",
2344 "VPSLLDrm",
2345 "VPSLLQrm",
2346 "VPSLLWrm",
2347 "VPSRADrm",
2348 "VPSRAWrm",
2349 "VPSRLDrm",
2350 "VPSRLQrm",
2351 "VPSRLWrm",
2352 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2353
2354def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
2355 let Latency = 7;
2356 let NumMicroOps = 3;
2357 let ResourceCycles = [1,1,1];
2358}
2359def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
2360
2361def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
2362 let Latency = 7;
2363 let NumMicroOps = 3;
2364 let ResourceCycles = [1,1,1];
2365}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2366def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2367
2368def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2369 let Latency = 7;
2370 let NumMicroOps = 3;
2371 let ResourceCycles = [1,1,1];
2372}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2373def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
2374 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2375
2376def BWWriteResGroup85 : SchedWriteRes<[BWPort23,BWPort06,BWPort15]> {
2377 let Latency = 7;
2378 let NumMicroOps = 3;
2379 let ResourceCycles = [1,1,1];
2380}
Craig Toppera42a2ba2017-12-16 18:35:31 +0000[diff] [blame]2381def: InstRW<[BWWriteResGroup85], (instregex "BEXTR(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2382
2383def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2384 let Latency = 7;
2385 let NumMicroOps = 3;
2386 let ResourceCycles = [1,1,1];
2387}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]2388def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2389
2390def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
2391 let Latency = 7;
2392 let NumMicroOps = 5;
2393 let ResourceCycles = [1,1,1,2];
2394}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2395def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
2396 "ROL(8|16|32|64)mi",
2397 "ROR(8|16|32|64)m1",
2398 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2399
2400def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2401 let Latency = 7;
2402 let NumMicroOps = 5;
2403 let ResourceCycles = [1,1,1,2];
2404}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2405def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2406
2407def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2408 let Latency = 7;
2409 let NumMicroOps = 5;
2410 let ResourceCycles = [1,1,1,1,1];
2411}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2412def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
2413 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2414
2415def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
2416 let Latency = 7;
2417 let NumMicroOps = 7;
2418 let ResourceCycles = [2,2,1,2];
2419}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2420def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2421
2422def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
2423 let Latency = 8;
2424 let NumMicroOps = 2;
2425 let ResourceCycles = [1,1];
2426}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2427def: InstRW<[BWWriteResGroup91], (instrs IMUL64m, MUL64m)>;
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2428def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2429def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
2430def: InstRW<[BWWriteResGroup91], (instregex "ADDPDrm",
2431 "ADDPSrm",
2432 "ADDSDrm",
2433 "ADDSSrm",
2434 "ADDSUBPDrm",
2435 "ADDSUBPSrm",
2436 "BSF(16|32|64)rm",
2437 "BSR(16|32|64)rm",
2438 "CMPPDrmi",
2439 "CMPPSrmi",
2440 "CMPSDrm",
2441 "CMPSSrm",
2442 "COMISDrm",
2443 "COMISSrm",
2444 "CVTDQ2PSrm",
2445 "CVTPS2DQrm",
2446 "CVTTPS2DQrm",
2447 "LZCNT(16|32|64)rm",
2448 "MAX(C?)PDrm",
2449 "MAX(C?)PSrm",
2450 "MAX(C?)SDrm",
2451 "MAX(C?)SSrm",
2452 "MIN(C?)PDrm",
2453 "MIN(C?)PSrm",
2454 "MIN(C?)SDrm",
2455 "MIN(C?)SSrm",
2456 "MMX_CVTPI2PSirm",
2457 "MMX_CVTPS2PIirm",
2458 "MMX_CVTTPS2PIirm",
2459 "PDEP(32|64)rm",
2460 "PEXT(32|64)rm",
2461 "POPCNT(16|32|64)rm",
2462 "SUBPDrm",
2463 "SUBPSrm",
2464 "SUBSDrm",
2465 "SUBSSrm",
2466 "TZCNT(16|32|64)rm",
2467 "UCOMISDrm",
2468 "UCOMISSrm",
2469 "VADDPDrm",
2470 "VADDPSrm",
2471 "VADDSDrm",
2472 "VADDSSrm",
2473 "VADDSUBPDrm",
2474 "VADDSUBPSrm",
2475 "VCMPPDrmi",
2476 "VCMPPSrmi",
2477 "VCMPSDrm",
2478 "VCMPSSrm",
2479 "VCOMISDrm",
2480 "VCOMISSrm",
2481 "VCVTDQ2PSrm",
2482 "VCVTPS2DQrm",
2483 "VCVTTPS2DQrm",
2484 "VMAX(C?)PDrm",
2485 "VMAX(C?)PSrm",
2486 "VMAX(C?)SDrm",
2487 "VMAX(C?)SSrm",
2488 "VMIN(C?)PDrm",
2489 "VMIN(C?)PSrm",
2490 "VMIN(C?)SDrm",
2491 "VMIN(C?)SSrm",
2492 "VSUBPDrm",
2493 "VSUBPSrm",
2494 "VSUBSDrm",
2495 "VSUBSSrm",
2496 "VUCOMISDrm",
2497 "VUCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2498
2499def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
2500 let Latency = 8;
2501 let NumMicroOps = 3;
2502 let ResourceCycles = [1,1,1];
2503}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2504def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2505
2506def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
2507 let Latency = 8;
2508 let NumMicroOps = 5;
2509}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2510def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2511
2512def BWWriteResGroup91_32 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
2513 let Latency = 8;
2514 let NumMicroOps = 3;
2515 let ResourceCycles = [1,1,1];
2516}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2517def: InstRW<[BWWriteResGroup91_32], (instrs IMUL32m, MUL32m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2518
2519def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
2520 let Latency = 8;
2521 let NumMicroOps = 2;
2522 let ResourceCycles = [1,1];
2523}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2524def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
2525 "VPMOVSXBQYrm",
2526 "VPMOVSXBWYrm",
2527 "VPMOVSXDQYrm",
2528 "VPMOVSXWDYrm",
2529 "VPMOVSXWQYrm",
2530 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2531
2532def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
2533 let Latency = 8;
2534 let NumMicroOps = 2;
2535 let ResourceCycles = [1,1];
2536}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2537def: InstRW<[BWWriteResGroup93], (instregex "MULPDrm",
2538 "MULPSrm",
2539 "MULSDrm",
2540 "MULSSrm",
2541 "VMULPDrm",
2542 "VMULPSrm",
2543 "VMULSDrm",
2544 "VMULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2545
2546def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
2547 let Latency = 8;
2548 let NumMicroOps = 3;
2549 let ResourceCycles = [2,1];
2550}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2551def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
2552 "VBLENDVPSYrm",
2553 "VMASKMOVPDYrm",
2554 "VMASKMOVPSYrm",
2555 "VPBLENDVBYrm",
2556 "VPMASKMOVDYrm",
2557 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2558
2559def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2560 let Latency = 8;
2561 let NumMicroOps = 4;
2562 let ResourceCycles = [2,1,1];
2563}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2564def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
2565 "VPSRAVDrm",
2566 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2567
2568def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2569 let Latency = 8;
2570 let NumMicroOps = 4;
2571 let ResourceCycles = [2,1,1];
2572}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2573def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
2574 "MMX_PHADDSWrm",
2575 "MMX_PHADDWrm",
2576 "MMX_PHSUBDrm",
2577 "MMX_PHSUBSWrm",
2578 "MMX_PHSUBWrm",
2579 "PHADDDrm",
2580 "PHADDSWrm",
2581 "PHADDWrm",
2582 "PHSUBDrm",
2583 "PHSUBSWrm",
2584 "PHSUBWrm",
2585 "VPHADDDrm",
2586 "VPHADDSWrm",
2587 "VPHADDWrm",
2588 "VPHSUBDrm",
2589 "VPHSUBSWrm",
2590 "VPHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2591
2592def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2593 let Latency = 8;
2594 let NumMicroOps = 5;
2595 let ResourceCycles = [1,1,1,2];
2596}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2597def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
2598 "RCL(8|16|32|64)mi",
2599 "RCR(8|16|32|64)m1",
2600 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2601
2602def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2603 let Latency = 8;
2604 let NumMicroOps = 5;
2605 let ResourceCycles = [1,1,2,1];
2606}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2607def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2608
2609def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2610 let Latency = 8;
2611 let NumMicroOps = 6;
2612 let ResourceCycles = [1,1,1,3];
2613}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2614def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
2615 "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2616
2617def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2618 let Latency = 8;
2619 let NumMicroOps = 6;
2620 let ResourceCycles = [1,1,1,2,1];
2621}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2622def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
2623 "CMPXCHG(8|16|32|64)rm",
2624 "ROL(8|16|32|64)mCL",
2625 "SAR(8|16|32|64)mCL",
2626 "SBB(8|16|32|64)mi",
2627 "SBB(8|16|32|64)mr",
2628 "SHL(8|16|32|64)mCL",
2629 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2630
2631def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
2632 let Latency = 9;
2633 let NumMicroOps = 2;
2634 let ResourceCycles = [1,1];
2635}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2636def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
2637 "ADD_F64m",
2638 "ILD_F16m",
2639 "ILD_F32m",
2640 "ILD_F64m",
2641 "SUBR_F32m",
2642 "SUBR_F64m",
2643 "SUB_F32m",
2644 "SUB_F64m",
2645 "VADDPDYrm",
2646 "VADDPSYrm",
2647 "VADDSUBPDYrm",
2648 "VADDSUBPSYrm",
2649 "VCMPPDYrmi",
2650 "VCMPPSYrmi",
2651 "VCVTDQ2PSYrm",
2652 "VCVTPS2DQYrm",
2653 "VCVTTPS2DQYrm",
2654 "VMAX(C?)PDYrm",
2655 "VMAX(C?)PSYrm",
2656 "VMIN(C?)PDYrm",
2657 "VMIN(C?)PSYrm",
2658 "VSUBPDYrm",
2659 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2660
2661def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2662 let Latency = 9;
2663 let NumMicroOps = 2;
2664 let ResourceCycles = [1,1];
2665}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2666def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2667 "VPERM2I128rm",
2668 "VPERMDYrm",
2669 "VPERMPDYmi",
2670 "VPERMPSYrm",
2671 "VPERMQYmi",
2672 "VPMOVZXBDYrm",
2673 "VPMOVZXBQYrm",
2674 "VPMOVZXBWYrm",
2675 "VPMOVZXDQYrm",
2676 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2677
2678def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2679 let Latency = 9;
2680 let NumMicroOps = 2;
2681 let ResourceCycles = [1,1];
2682}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2683def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2684 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2685
2686def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2687 let Latency = 9;
2688 let NumMicroOps = 3;
2689 let ResourceCycles = [1,1,1];
2690}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2691def: InstRW<[BWWriteResGroup104], (instregex "DPPDrri",
2692 "VDPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2693
2694def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2695 let Latency = 9;
2696 let NumMicroOps = 3;
2697 let ResourceCycles = [1,1,1];
2698}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2699def: InstRW<[BWWriteResGroup105], (instregex "CVTSD2SI64rm",
2700 "CVTSD2SIrm",
2701 "CVTSS2SI64rm",
2702 "CVTSS2SIrm",
2703 "CVTTSD2SI64rm",
2704 "CVTTSD2SIrm",
2705 "CVTTSS2SIrm",
2706 "VCVTSD2SI64rm",
2707 "VCVTSD2SIrm",
2708 "VCVTSS2SI64rm",
2709 "VCVTSS2SIrm",
2710 "VCVTTSD2SI64rm",
2711 "VCVTTSD2SIrm",
2712 "VCVTTSS2SI64rm",
2713 "VCVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2714
2715def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2716 let Latency = 9;
2717 let NumMicroOps = 3;
2718 let ResourceCycles = [1,1,1];
2719}
2720def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2721
2722def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2723 let Latency = 9;
2724 let NumMicroOps = 3;
2725 let ResourceCycles = [1,1,1];
2726}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2727def: InstRW<[BWWriteResGroup107], (instrs MULX64rm)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2728def: InstRW<[BWWriteResGroup107], (instregex "CVTDQ2PDrm",
2729 "CVTPD2DQrm",
2730 "CVTPD2PSrm",
2731 "CVTSD2SSrm",
2732 "CVTTPD2DQrm",
2733 "MMX_CVTPD2PIirm",
2734 "MMX_CVTPI2PDirm",
2735 "MMX_CVTTPD2PIirm",
2736 "VCVTDQ2PDrm",
2737 "VCVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2738
2739def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2740 let Latency = 9;
2741 let NumMicroOps = 3;
2742 let ResourceCycles = [1,1,1];
2743}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2744def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTBYrm",
2745 "VPBROADCASTBrm",
2746 "VPBROADCASTWYrm",
2747 "VPBROADCASTWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2748
2749def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2750 let Latency = 9;
2751 let NumMicroOps = 4;
2752 let ResourceCycles = [2,1,1];
2753}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2754def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2755 "VPSRAVDYrm",
2756 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2757
2758def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2759 let Latency = 9;
2760 let NumMicroOps = 4;
2761 let ResourceCycles = [2,1,1];
2762}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2763def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2764 "VPHADDSWYrm",
2765 "VPHADDWYrm",
2766 "VPHSUBDYrm",
2767 "VPHSUBSWYrm",
2768 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2769
2770def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2771 let Latency = 9;
2772 let NumMicroOps = 4;
2773 let ResourceCycles = [1,1,1,1];
2774}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2775def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2776 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2777
2778def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2779 let Latency = 9;
2780 let NumMicroOps = 5;
2781 let ResourceCycles = [1,1,3];
2782}
2783def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2784
2785def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2786 let Latency = 9;
2787 let NumMicroOps = 5;
2788 let ResourceCycles = [1,2,1,1];
2789}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2790def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2791 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2792
2793def BWWriteResGroup114 : SchedWriteRes<[BWPort0]> {
2794 let Latency = 10;
2795 let NumMicroOps = 2;
2796 let ResourceCycles = [2];
2797}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2798def: InstRW<[BWWriteResGroup114], (instregex "PMULLDrr",
2799 "VPMULLDYrr",
2800 "VPMULLDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2801
2802def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2803 let Latency = 10;
2804 let NumMicroOps = 2;
2805 let ResourceCycles = [1,1];
2806}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2807def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2808 "MMX_PMADDWDirm",
2809 "MMX_PMULHRSWrm",
2810 "MMX_PMULHUWirm",
2811 "MMX_PMULHWirm",
2812 "MMX_PMULLWirm",
2813 "MMX_PMULUDQirm",
2814 "MMX_PSADBWirm",
2815 "PCLMULQDQrm",
2816 "PCMPGTQrm",
2817 "PHMINPOSUWrm",
2818 "PMADDUBSWrm",
2819 "PMADDWDrm",
2820 "PMULDQrm",
2821 "PMULHRSWrm",
2822 "PMULHUWrm",
2823 "PMULHWrm",
2824 "PMULLWrm",
2825 "PMULUDQrm",
2826 "PSADBWrm",
2827 "RCPPSm",
2828 "RCPSSm",
2829 "RSQRTPSm",
2830 "RSQRTSSm",
2831 "VPCLMULQDQrm",
2832 "VPCMPGTQrm",
2833 "VPHMINPOSUWrm",
2834 "VPMADDUBSWrm",
2835 "VPMADDWDrm",
2836 "VPMULDQrm",
2837 "VPMULHRSWrm",
2838 "VPMULHUWrm",
2839 "VPMULHWrm",
2840 "VPMULLWrm",
2841 "VPMULUDQrm",
2842 "VPSADBWrm",
2843 "VRCPPSm",
2844 "VRCPSSm",
2845 "VRSQRTPSm",
2846 "VRSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2847
2848def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2849 let Latency = 10;
2850 let NumMicroOps = 2;
2851 let ResourceCycles = [1,1];
2852}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2853def: InstRW<[BWWriteResGroup116],
2854 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2855 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2856
2857def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2858 let Latency = 10;
2859 let NumMicroOps = 3;
2860 let ResourceCycles = [2,1];
2861}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2862def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2863 "FICOM32m",
2864 "FICOMP16m",
2865 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2866
2867def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2868 let Latency = 10;
2869 let NumMicroOps = 3;
2870 let ResourceCycles = [1,1,1];
2871}
2872def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2873
2874def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2875 let Latency = 10;
2876 let NumMicroOps = 4;
2877 let ResourceCycles = [1,2,1];
2878}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2879def: InstRW<[BWWriteResGroup119], (instregex "HADDPDrm",
2880 "HADDPSrm",
2881 "HSUBPDrm",
2882 "HSUBPSrm",
2883 "VHADDPDrm",
2884 "VHADDPSrm",
2885 "VHSUBPDrm",
2886 "VHSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2887
2888def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2889 let Latency = 10;
2890 let NumMicroOps = 4;
2891 let ResourceCycles = [1,1,1,1];
2892}
2893def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2894
2895def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
2896 let Latency = 10;
2897 let NumMicroOps = 4;
2898 let ResourceCycles = [1,1,1,1];
2899}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2900def: InstRW<[BWWriteResGroup121], (instrs MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2901
2902def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {
2903 let Latency = 11;
2904 let NumMicroOps = 1;
2905 let ResourceCycles = [1];
2906}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2907def: InstRW<[BWWriteResGroup122], (instregex "DIVPSrr",
2908 "DIVSSrr",
2909 "VDIVPSrr",
2910 "VDIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2911
2912def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2913 let Latency = 11;
2914 let NumMicroOps = 2;
2915 let ResourceCycles = [1,1];
2916}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2917def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2918 "MUL_F64m",
2919 "VPCMPGTQYrm",
2920 "VPMADDUBSWYrm",
2921 "VPMADDWDYrm",
2922 "VPMULDQYrm",
2923 "VPMULHRSWYrm",
2924 "VPMULHUWYrm",
2925 "VPMULHWYrm",
2926 "VPMULLWYrm",
2927 "VPMULUDQYrm",
2928 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2929
2930def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2931 let Latency = 11;
2932 let NumMicroOps = 2;
2933 let ResourceCycles = [1,1];
2934}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2935def: InstRW<[BWWriteResGroup124],
2936 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2937
2938def BWWriteResGroup125 : SchedWriteRes<[BWPort0]> {
2939 let Latency = 11;
2940 let NumMicroOps = 3;
2941 let ResourceCycles = [3];
2942}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2943def: InstRW<[BWWriteResGroup125], (instregex "PCMPISTRIrr",
2944 "PCMPISTRM128rr",
2945 "VPCMPISTRIrr",
2946 "VPCMPISTRM128rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2947
2948def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2949 let Latency = 11;
2950 let NumMicroOps = 3;
2951 let ResourceCycles = [2,1];
2952}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2953def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2954 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2955
2956def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2957 let Latency = 11;
2958 let NumMicroOps = 3;
2959 let ResourceCycles = [2,1];
2960}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2961def: InstRW<[BWWriteResGroup127], (instregex "ROUNDPDm",
2962 "ROUNDPSm",
2963 "ROUNDSDm",
2964 "ROUNDSSm",
2965 "VROUNDPDm",
2966 "VROUNDPSm",
2967 "VROUNDSDm",
2968 "VROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2969
2970def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2971 let Latency = 11;
2972 let NumMicroOps = 3;
2973 let ResourceCycles = [1,1,1];
2974}
2975def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2976
2977def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2978 let Latency = 11;
2979 let NumMicroOps = 4;
2980 let ResourceCycles = [1,2,1];
2981}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2982def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2983 "VHADDPSYrm",
2984 "VHSUBPDYrm",
2985 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2986
2987def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2988 let Latency = 11;
2989 let NumMicroOps = 6;
2990 let ResourceCycles = [1,1,1,1,2];
2991}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2992def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2993 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2994
2995def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2996 let Latency = 11;
2997 let NumMicroOps = 7;
2998 let ResourceCycles = [2,2,3];
2999}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3000def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
3001 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3002
3003def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
3004 let Latency = 11;
3005 let NumMicroOps = 9;
3006 let ResourceCycles = [1,4,1,3];
3007}
3008def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
3009
3010def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
3011 let Latency = 11;
3012 let NumMicroOps = 11;
3013 let ResourceCycles = [2,9];
3014}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3015def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
3016def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3017
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3018def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
3019 let Latency = 12;
3020 let NumMicroOps = 3;
3021 let ResourceCycles = [2,1];
3022}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3023def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
3024 "ADD_FI32m",
3025 "SUBR_FI16m",
3026 "SUBR_FI32m",
3027 "SUB_FI16m",
3028 "SUB_FI32m",
3029 "VROUNDYPDm",
3030 "VROUNDYPSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3031
3032def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
3033 let Latency = 12;
3034 let NumMicroOps = 4;
3035 let ResourceCycles = [1,2,1];
3036}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3037def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3038
3039def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {
3040 let Latency = 13;
3041 let NumMicroOps = 1;
3042 let ResourceCycles = [1];
3043}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3044def: InstRW<[BWWriteResGroup137], (instregex "SQRTPSr",
3045 "SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3046
3047def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
3048 let Latency = 13;
3049 let NumMicroOps = 4;
3050 let ResourceCycles = [1,2,1];
3051}
3052def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
3053
3054def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {
3055 let Latency = 14;
3056 let NumMicroOps = 1;
3057 let ResourceCycles = [1];
3058}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3059def: InstRW<[BWWriteResGroup139], (instregex "DIVPDrr",
3060 "DIVSDrr",
3061 "VDIVPDrr",
3062 "VDIVSDrr",
3063 "VSQRTPSr",
3064 "VSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3065
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3066def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
3067 let Latency = 14;
3068 let NumMicroOps = 3;
3069 let ResourceCycles = [1,1,1];
3070}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3071def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
3072 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3073
3074def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
3075 let Latency = 14;
3076 let NumMicroOps = 4;
3077 let ResourceCycles = [2,1,1];
3078}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3079def: InstRW<[BWWriteResGroup142], (instregex "DPPSrri",
3080 "VDPPSYrri",
3081 "VDPPSrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3082
3083def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
3084 let Latency = 14;
3085 let NumMicroOps = 4;
3086 let ResourceCycles = [1,1,1,1];
3087}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3088def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3089
3090def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
3091 let Latency = 14;
3092 let NumMicroOps = 8;
3093 let ResourceCycles = [2,2,1,3];
3094}
3095def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
3096
3097def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
3098 let Latency = 14;
3099 let NumMicroOps = 10;
3100 let ResourceCycles = [2,3,1,4];
3101}
3102def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
3103
3104def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
3105 let Latency = 14;
3106 let NumMicroOps = 12;
3107 let ResourceCycles = [2,1,4,5];
3108}
3109def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
3110
3111def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
3112 let Latency = 15;
3113 let NumMicroOps = 1;
3114 let ResourceCycles = [1];
3115}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3116def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
3117 "DIVR_FST0r",
3118 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3119
3120def BWWriteResGroup148 : SchedWriteRes<[BWPort0,BWPort23]> {
3121 let Latency = 15;
3122 let NumMicroOps = 3;
3123 let ResourceCycles = [2,1];
3124}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3125def: InstRW<[BWWriteResGroup148], (instregex "(V?)PMULLDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3126
3127def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
3128 let Latency = 15;
3129 let NumMicroOps = 10;
3130 let ResourceCycles = [1,1,1,4,1,2];
3131}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3132def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3133
3134def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
3135 let Latency = 16;
3136 let NumMicroOps = 2;
3137 let ResourceCycles = [1,1];
3138}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3139def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
3140 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3141
3142def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
3143 let Latency = 16;
3144 let NumMicroOps = 3;
3145 let ResourceCycles = [2,1];
3146}
3147def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
3148
3149def BWWriteResGroup152 : SchedWriteRes<[BWPort0,BWPort23]> {
3150 let Latency = 16;
3151 let NumMicroOps = 4;
3152 let ResourceCycles = [3,1];
3153}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3154def: InstRW<[BWWriteResGroup152], (instregex "(V?)PCMPISTRIrm",
3155 "(V?)PCMPISTRM128rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3156
3157def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
3158 let Latency = 16;
3159 let NumMicroOps = 14;
3160 let ResourceCycles = [1,1,1,4,2,5];
3161}
3162def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
3163
3164def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
3165 let Latency = 16;
3166 let NumMicroOps = 16;
3167 let ResourceCycles = [16];
3168}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3169def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3170
3171def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {
3172 let Latency = 17;
3173 let NumMicroOps = 3;
3174 let ResourceCycles = [2,1];
3175}
3176def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
3177
3178def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3179 let Latency = 17;
3180 let NumMicroOps = 4;
3181 let ResourceCycles = [2,1,1];
3182}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3183def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
3184 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3185
3186def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {
3187 let Latency = 18;
3188 let NumMicroOps = 2;
3189 let ResourceCycles = [1,1];
3190}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3191def: InstRW<[BWWriteResGroup157], (instregex "SQRTPSm",
3192 "SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3193
3194def BWWriteResGroup158 : SchedWriteRes<[BWPort0,BWPort5,BWPort0156]> {
3195 let Latency = 18;
3196 let NumMicroOps = 8;
3197 let ResourceCycles = [4,3,1];
3198}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3199def: InstRW<[BWWriteResGroup158], (instregex "(V?)PCMPESTRIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3200
3201def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
3202 let Latency = 18;
3203 let NumMicroOps = 8;
3204 let ResourceCycles = [1,1,1,5];
3205}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3206def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3207def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3208
3209def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
3210 let Latency = 18;
3211 let NumMicroOps = 11;
3212 let ResourceCycles = [2,1,1,3,1,3];
3213}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3214def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3215
3216def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
3217 let Latency = 19;
3218 let NumMicroOps = 2;
3219 let ResourceCycles = [1,1];
3220}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3221def: InstRW<[BWWriteResGroup161], (instregex "DIVPDrm",
3222 "DIVSDrm",
3223 "VDIVPDrm",
3224 "VDIVSDrm",
3225 "VSQRTPSm",
3226 "VSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3227
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3228def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
3229 let Latency = 19;
3230 let NumMicroOps = 5;
3231 let ResourceCycles = [2,1,1,1];
3232}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3233def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3234
3235def BWWriteResGroup164 : SchedWriteRes<[BWPort0,BWPort5,BWPort015,BWPort0156]> {
3236 let Latency = 19;
3237 let NumMicroOps = 9;
3238 let ResourceCycles = [4,3,1,1];
3239}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3240def: InstRW<[BWWriteResGroup164], (instregex "(V?)PCMPESTRM128rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3241
3242def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
3243 let Latency = 20;
3244 let NumMicroOps = 1;
3245 let ResourceCycles = [1];
3246}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3247def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
3248 "DIV_FST0r",
3249 "DIV_FrST0",
3250 "SQRTPDr",
3251 "SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3252
3253def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
3254 let Latency = 20;
3255 let NumMicroOps = 5;
3256 let ResourceCycles = [2,1,1,1];
3257}
3258def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
3259
3260def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
3261 let Latency = 20;
3262 let NumMicroOps = 8;
3263 let ResourceCycles = [1,1,1,1,1,1,2];
3264}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3265def: InstRW<[BWWriteResGroup167], (instregex "INSB",
3266 "INSL",
3267 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3268
3269def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {
3270 let Latency = 21;
3271 let NumMicroOps = 1;
3272 let ResourceCycles = [1];
3273}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3274def: InstRW<[BWWriteResGroup168], (instregex "VSQRTPDr",
3275 "VSQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3276
3277def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
3278 let Latency = 21;
3279 let NumMicroOps = 2;
3280 let ResourceCycles = [1,1];
3281}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3282def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
3283 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3284
3285def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {
3286 let Latency = 21;
3287 let NumMicroOps = 3;
3288 let ResourceCycles = [2,1];
3289}
3290def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
3291
3292def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
3293 let Latency = 21;
3294 let NumMicroOps = 19;
3295 let ResourceCycles = [2,1,4,1,1,4,6];
3296}
3297def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
3298
3299def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
3300 let Latency = 22;
3301 let NumMicroOps = 18;
3302 let ResourceCycles = [1,1,16];
3303}
3304def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
3305
3306def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {
3307 let Latency = 23;
3308 let NumMicroOps = 3;
3309 let ResourceCycles = [2,1];
3310}
3311def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
3312
3313def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3314 let Latency = 23;
3315 let NumMicroOps = 4;
3316 let ResourceCycles = [2,1,1];
3317}
3318def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
3319
3320def BWWriteResGroup175 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort0156]> {
3321 let Latency = 23;
3322 let NumMicroOps = 9;
3323 let ResourceCycles = [4,3,1,1];
3324}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3325def: InstRW<[BWWriteResGroup175], (instregex "(V?)PCMPESTRIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3326
3327def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
3328 let Latency = 23;
3329 let NumMicroOps = 19;
3330 let ResourceCycles = [3,1,15];
3331}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]3332def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3333
3334def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
3335 let Latency = 24;
3336 let NumMicroOps = 3;
3337 let ResourceCycles = [1,1,1];
3338}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3339def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
3340 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3341
3342def BWWriteResGroup178 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort015,BWPort0156]> {
3343 let Latency = 24;
3344 let NumMicroOps = 10;
3345 let ResourceCycles = [4,3,1,1,1];
3346}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3347def: InstRW<[BWWriteResGroup178], (instregex "(V?)PCMPESTRM128rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3348
3349def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
3350 let Latency = 25;
3351 let NumMicroOps = 2;
3352 let ResourceCycles = [1,1];
3353}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3354def: InstRW<[BWWriteResGroup179], (instregex "SQRTPDm",
3355 "SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3356
3357def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
3358 let Latency = 26;
3359 let NumMicroOps = 2;
3360 let ResourceCycles = [1,1];
3361}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3362def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
3363 "DIVR_F64m",
3364 "VSQRTPDm",
3365 "VSQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3366
3367def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3368 let Latency = 27;
3369 let NumMicroOps = 4;
3370 let ResourceCycles = [2,1,1];
3371}
3372def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
3373
3374def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
3375 let Latency = 29;
3376 let NumMicroOps = 3;
3377 let ResourceCycles = [1,1,1];
3378}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3379def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
3380 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3381
3382def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3383 let Latency = 29;
3384 let NumMicroOps = 4;
3385 let ResourceCycles = [2,1,1];
3386}
3387def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
3388
3389def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3390 let Latency = 22;
3391 let NumMicroOps = 7;
3392 let ResourceCycles = [1,3,2,1];
3393}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3394def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3395
3396def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3397 let Latency = 23;
3398 let NumMicroOps = 9;
3399 let ResourceCycles = [1,3,4,1];
3400}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3401def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3402
3403def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3404 let Latency = 24;
3405 let NumMicroOps = 9;
3406 let ResourceCycles = [1,5,2,1];
3407}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3408def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3409
3410def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3411 let Latency = 25;
3412 let NumMicroOps = 7;
3413 let ResourceCycles = [1,3,2,1];
3414}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3415def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
3416 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3417
3418def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3419 let Latency = 26;
3420 let NumMicroOps = 9;
3421 let ResourceCycles = [1,5,2,1];
3422}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3423def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3424
3425def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3426 let Latency = 26;
3427 let NumMicroOps = 14;
3428 let ResourceCycles = [1,4,8,1];
3429}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3430def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3431
3432def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3433 let Latency = 27;
3434 let NumMicroOps = 9;
3435 let ResourceCycles = [1,5,2,1];
3436}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3437def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3438
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3439def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
3440 let Latency = 29;
3441 let NumMicroOps = 27;
3442 let ResourceCycles = [1,5,1,1,19];
3443}
3444def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
3445
3446def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
3447 let Latency = 30;
3448 let NumMicroOps = 28;
3449 let ResourceCycles = [1,6,1,1,19];
3450}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3451def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3452
3453def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
3454 let Latency = 31;
3455 let NumMicroOps = 31;
3456 let ResourceCycles = [8,1,21,1];
3457}
3458def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
3459
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3460def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
3461 let Latency = 34;
3462 let NumMicroOps = 3;
3463 let ResourceCycles = [2,1];
3464}
3465def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
3466
3467def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
3468 let Latency = 34;
3469 let NumMicroOps = 8;
3470 let ResourceCycles = [2,2,2,1,1];
3471}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3472def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3473
3474def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
3475 let Latency = 34;
3476 let NumMicroOps = 23;
3477 let ResourceCycles = [1,5,3,4,10];
3478}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3479def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
3480 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3481
3482def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
3483 let Latency = 35;
3484 let NumMicroOps = 8;
3485 let ResourceCycles = [2,2,2,1,1];
3486}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3487def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3488
3489def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
3490 let Latency = 35;
3491 let NumMicroOps = 23;
3492 let ResourceCycles = [1,5,2,1,4,10];
3493}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3494def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
3495 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3496
3497def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3498 let Latency = 40;
3499 let NumMicroOps = 4;
3500 let ResourceCycles = [2,1,1];
3501}
3502def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
3503
3504def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
3505 let Latency = 42;
3506 let NumMicroOps = 22;
3507 let ResourceCycles = [2,20];
3508}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3509def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3510
3511def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
3512 let Latency = 60;
3513 let NumMicroOps = 64;
3514 let ResourceCycles = [2,2,8,1,10,2,39];
3515}
3516def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3517
3518def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
3519 let Latency = 63;
3520 let NumMicroOps = 88;
3521 let ResourceCycles = [4,4,31,1,2,1,45];
3522}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3523def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3524
3525def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
3526 let Latency = 63;
3527 let NumMicroOps = 90;
3528 let ResourceCycles = [4,2,33,1,2,1,47];
3529}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3530def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3531
3532def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
3533 let Latency = 75;
3534 let NumMicroOps = 15;
3535 let ResourceCycles = [6,3,6];
3536}
3537def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
3538
3539def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
3540 let Latency = 80;
3541 let NumMicroOps = 32;
3542 let ResourceCycles = [7,7,3,3,1,11];
3543}
3544def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
3545
3546def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
3547 let Latency = 115;
3548 let NumMicroOps = 100;
3549 let ResourceCycles = [9,9,11,8,1,11,21,30];
3550}
3551def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3552
3553} // SchedModel
3554