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gerrit-public.fairphone.software / toolchain / llvm-project / abdf44e7f38d392fed85692b2a31bf1578f3ee3b / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: 6a2854790d8551fa19922dfc42fbc2b2a31bf100 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]21#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]22#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]23#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]25#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]26#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]27#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]28#include "llvm/IR/DerivedTypes.h"
29#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]30#include "llvm/MC/MCAsmInfo.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]31#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]32#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]33#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]36#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]37#include <limits>
38
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]39using namespace llvm;
40
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]41#define DEBUG_TYPE "x86-instr-info"
42
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]43#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]44#include "X86GenInstrInfo.inc"
45
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]46static cl::opt<bool>
47NoFusing("disable-spill-fusing",
48 cl::desc("Disable fusing of spill code into instructions"));
49static cl::opt<bool>
50PrintFailedFusing("print-failed-fuse-candidates",
51 cl::desc("Print instructions that the allocator wants to"
52 " fuse, but the X86 backend currently can't"),
53 cl::Hidden);
54static cl::opt<bool>
55ReMatPICStubLoad("remat-pic-stub-load",
56 cl::desc("Re-materialize load from stub in PIC mode"),
57 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]58
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]59enum {
60 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]61 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]62 TB_INDEX_0 = 0,
63 TB_INDEX_1 = 1,
64 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]65 TB_INDEX_3 = 3,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]66 TB_INDEX_MASK = 0xf,
67
68 // Do not insert the reverse map (MemOp -> RegOp) into the table.
69 // This may be needed because there is a many -> one mapping.
70 TB_NO_REVERSE = 1 << 4,
71
72 // Do not insert the forward map (RegOp -> MemOp) into the table.
73 // This is needed for Native Client, which prohibits branch
74 // instructions from using a memory operand.
75 TB_NO_FORWARD = 1 << 5,
76
77 TB_FOLDED_LOAD = 1 << 6,
78 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]79
80 // Minimum alignment required for load/store.
81 // Used for RegOp->MemOp conversion.
82 // (stored in bits 8 - 15)
83 TB_ALIGN_SHIFT = 8,
84 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
85 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
86 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]87 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]88 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]89};
90
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]91struct X86OpTblEntry {
92 uint16_t RegOp;
93 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]94 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]95};
96
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]97// Pin the vtable to this file.
98void X86InstrInfo::anchor() {}
99
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]100X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
Evan Cheng703a0fb2011-07-01 17:57:27 +0000[diff] [blame]101 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
102 ? X86::ADJCALLSTACKDOWN64
103 : X86::ADJCALLSTACKDOWN32),
104 (tm.getSubtarget<X86Subtarget>().is64Bit()
105 ? X86::ADJCALLSTACKUP64
106 : X86::ADJCALLSTACKUP32)),
Bill Wendling8f268402013-06-07 21:00:34 +0000[diff] [blame]107 TM(tm), RI(tm) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]108
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]109 static const X86OpTblEntry OpTbl2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]110 { X86::ADC32ri, X86::ADC32mi, 0 },
111 { X86::ADC32ri8, X86::ADC32mi8, 0 },
112 { X86::ADC32rr, X86::ADC32mr, 0 },
113 { X86::ADC64ri32, X86::ADC64mi32, 0 },
114 { X86::ADC64ri8, X86::ADC64mi8, 0 },
115 { X86::ADC64rr, X86::ADC64mr, 0 },
116 { X86::ADD16ri, X86::ADD16mi, 0 },
117 { X86::ADD16ri8, X86::ADD16mi8, 0 },
118 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
119 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
120 { X86::ADD16rr, X86::ADD16mr, 0 },
121 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
122 { X86::ADD32ri, X86::ADD32mi, 0 },
123 { X86::ADD32ri8, X86::ADD32mi8, 0 },
124 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
125 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
126 { X86::ADD32rr, X86::ADD32mr, 0 },
127 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
128 { X86::ADD64ri32, X86::ADD64mi32, 0 },
129 { X86::ADD64ri8, X86::ADD64mi8, 0 },
130 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
131 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
132 { X86::ADD64rr, X86::ADD64mr, 0 },
133 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
134 { X86::ADD8ri, X86::ADD8mi, 0 },
135 { X86::ADD8rr, X86::ADD8mr, 0 },
136 { X86::AND16ri, X86::AND16mi, 0 },
137 { X86::AND16ri8, X86::AND16mi8, 0 },
138 { X86::AND16rr, X86::AND16mr, 0 },
139 { X86::AND32ri, X86::AND32mi, 0 },
140 { X86::AND32ri8, X86::AND32mi8, 0 },
141 { X86::AND32rr, X86::AND32mr, 0 },
142 { X86::AND64ri32, X86::AND64mi32, 0 },
143 { X86::AND64ri8, X86::AND64mi8, 0 },
144 { X86::AND64rr, X86::AND64mr, 0 },
145 { X86::AND8ri, X86::AND8mi, 0 },
146 { X86::AND8rr, X86::AND8mr, 0 },
147 { X86::DEC16r, X86::DEC16m, 0 },
148 { X86::DEC32r, X86::DEC32m, 0 },
149 { X86::DEC64_16r, X86::DEC64_16m, 0 },
150 { X86::DEC64_32r, X86::DEC64_32m, 0 },
151 { X86::DEC64r, X86::DEC64m, 0 },
152 { X86::DEC8r, X86::DEC8m, 0 },
153 { X86::INC16r, X86::INC16m, 0 },
154 { X86::INC32r, X86::INC32m, 0 },
155 { X86::INC64_16r, X86::INC64_16m, 0 },
156 { X86::INC64_32r, X86::INC64_32m, 0 },
157 { X86::INC64r, X86::INC64m, 0 },
158 { X86::INC8r, X86::INC8m, 0 },
159 { X86::NEG16r, X86::NEG16m, 0 },
160 { X86::NEG32r, X86::NEG32m, 0 },
161 { X86::NEG64r, X86::NEG64m, 0 },
162 { X86::NEG8r, X86::NEG8m, 0 },
163 { X86::NOT16r, X86::NOT16m, 0 },
164 { X86::NOT32r, X86::NOT32m, 0 },
165 { X86::NOT64r, X86::NOT64m, 0 },
166 { X86::NOT8r, X86::NOT8m, 0 },
167 { X86::OR16ri, X86::OR16mi, 0 },
168 { X86::OR16ri8, X86::OR16mi8, 0 },
169 { X86::OR16rr, X86::OR16mr, 0 },
170 { X86::OR32ri, X86::OR32mi, 0 },
171 { X86::OR32ri8, X86::OR32mi8, 0 },
172 { X86::OR32rr, X86::OR32mr, 0 },
173 { X86::OR64ri32, X86::OR64mi32, 0 },
174 { X86::OR64ri8, X86::OR64mi8, 0 },
175 { X86::OR64rr, X86::OR64mr, 0 },
176 { X86::OR8ri, X86::OR8mi, 0 },
177 { X86::OR8rr, X86::OR8mr, 0 },
178 { X86::ROL16r1, X86::ROL16m1, 0 },
179 { X86::ROL16rCL, X86::ROL16mCL, 0 },
180 { X86::ROL16ri, X86::ROL16mi, 0 },
181 { X86::ROL32r1, X86::ROL32m1, 0 },
182 { X86::ROL32rCL, X86::ROL32mCL, 0 },
183 { X86::ROL32ri, X86::ROL32mi, 0 },
184 { X86::ROL64r1, X86::ROL64m1, 0 },
185 { X86::ROL64rCL, X86::ROL64mCL, 0 },
186 { X86::ROL64ri, X86::ROL64mi, 0 },
187 { X86::ROL8r1, X86::ROL8m1, 0 },
188 { X86::ROL8rCL, X86::ROL8mCL, 0 },
189 { X86::ROL8ri, X86::ROL8mi, 0 },
190 { X86::ROR16r1, X86::ROR16m1, 0 },
191 { X86::ROR16rCL, X86::ROR16mCL, 0 },
192 { X86::ROR16ri, X86::ROR16mi, 0 },
193 { X86::ROR32r1, X86::ROR32m1, 0 },
194 { X86::ROR32rCL, X86::ROR32mCL, 0 },
195 { X86::ROR32ri, X86::ROR32mi, 0 },
196 { X86::ROR64r1, X86::ROR64m1, 0 },
197 { X86::ROR64rCL, X86::ROR64mCL, 0 },
198 { X86::ROR64ri, X86::ROR64mi, 0 },
199 { X86::ROR8r1, X86::ROR8m1, 0 },
200 { X86::ROR8rCL, X86::ROR8mCL, 0 },
201 { X86::ROR8ri, X86::ROR8mi, 0 },
202 { X86::SAR16r1, X86::SAR16m1, 0 },
203 { X86::SAR16rCL, X86::SAR16mCL, 0 },
204 { X86::SAR16ri, X86::SAR16mi, 0 },
205 { X86::SAR32r1, X86::SAR32m1, 0 },
206 { X86::SAR32rCL, X86::SAR32mCL, 0 },
207 { X86::SAR32ri, X86::SAR32mi, 0 },
208 { X86::SAR64r1, X86::SAR64m1, 0 },
209 { X86::SAR64rCL, X86::SAR64mCL, 0 },
210 { X86::SAR64ri, X86::SAR64mi, 0 },
211 { X86::SAR8r1, X86::SAR8m1, 0 },
212 { X86::SAR8rCL, X86::SAR8mCL, 0 },
213 { X86::SAR8ri, X86::SAR8mi, 0 },
214 { X86::SBB32ri, X86::SBB32mi, 0 },
215 { X86::SBB32ri8, X86::SBB32mi8, 0 },
216 { X86::SBB32rr, X86::SBB32mr, 0 },
217 { X86::SBB64ri32, X86::SBB64mi32, 0 },
218 { X86::SBB64ri8, X86::SBB64mi8, 0 },
219 { X86::SBB64rr, X86::SBB64mr, 0 },
220 { X86::SHL16rCL, X86::SHL16mCL, 0 },
221 { X86::SHL16ri, X86::SHL16mi, 0 },
222 { X86::SHL32rCL, X86::SHL32mCL, 0 },
223 { X86::SHL32ri, X86::SHL32mi, 0 },
224 { X86::SHL64rCL, X86::SHL64mCL, 0 },
225 { X86::SHL64ri, X86::SHL64mi, 0 },
226 { X86::SHL8rCL, X86::SHL8mCL, 0 },
227 { X86::SHL8ri, X86::SHL8mi, 0 },
228 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
229 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
230 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
231 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
232 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
233 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
234 { X86::SHR16r1, X86::SHR16m1, 0 },
235 { X86::SHR16rCL, X86::SHR16mCL, 0 },
236 { X86::SHR16ri, X86::SHR16mi, 0 },
237 { X86::SHR32r1, X86::SHR32m1, 0 },
238 { X86::SHR32rCL, X86::SHR32mCL, 0 },
239 { X86::SHR32ri, X86::SHR32mi, 0 },
240 { X86::SHR64r1, X86::SHR64m1, 0 },
241 { X86::SHR64rCL, X86::SHR64mCL, 0 },
242 { X86::SHR64ri, X86::SHR64mi, 0 },
243 { X86::SHR8r1, X86::SHR8m1, 0 },
244 { X86::SHR8rCL, X86::SHR8mCL, 0 },
245 { X86::SHR8ri, X86::SHR8mi, 0 },
246 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
247 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
248 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
249 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
250 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
251 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
252 { X86::SUB16ri, X86::SUB16mi, 0 },
253 { X86::SUB16ri8, X86::SUB16mi8, 0 },
254 { X86::SUB16rr, X86::SUB16mr, 0 },
255 { X86::SUB32ri, X86::SUB32mi, 0 },
256 { X86::SUB32ri8, X86::SUB32mi8, 0 },
257 { X86::SUB32rr, X86::SUB32mr, 0 },
258 { X86::SUB64ri32, X86::SUB64mi32, 0 },
259 { X86::SUB64ri8, X86::SUB64mi8, 0 },
260 { X86::SUB64rr, X86::SUB64mr, 0 },
261 { X86::SUB8ri, X86::SUB8mi, 0 },
262 { X86::SUB8rr, X86::SUB8mr, 0 },
263 { X86::XOR16ri, X86::XOR16mi, 0 },
264 { X86::XOR16ri8, X86::XOR16mi8, 0 },
265 { X86::XOR16rr, X86::XOR16mr, 0 },
266 { X86::XOR32ri, X86::XOR32mi, 0 },
267 { X86::XOR32ri8, X86::XOR32mi8, 0 },
268 { X86::XOR32rr, X86::XOR32mr, 0 },
269 { X86::XOR64ri32, X86::XOR64mi32, 0 },
270 { X86::XOR64ri8, X86::XOR64mi8, 0 },
271 { X86::XOR64rr, X86::XOR64mr, 0 },
272 { X86::XOR8ri, X86::XOR8mi, 0 },
273 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]274 };
275
276 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]277 unsigned RegOp = OpTbl2Addr[i].RegOp;
278 unsigned MemOp = OpTbl2Addr[i].MemOp;
279 unsigned Flags = OpTbl2Addr[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]280 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
281 RegOp, MemOp,
282 // Index 0, folded load and store, no alignment requirement.
283 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]284 }
285
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]286 static const X86OpTblEntry OpTbl0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]287 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
288 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
289 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
290 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
291 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]292 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
293 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
294 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
295 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
296 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
297 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
298 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
299 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
300 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
301 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
302 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
303 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
304 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
305 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
306 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]307 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]308 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
309 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
310 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
311 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
312 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
313 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
314 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
315 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
316 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
317 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
318 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
319 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
320 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
321 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
322 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
323 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
324 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
325 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
326 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
327 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
328 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
329 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]330 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
331 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
332 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
333 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
334 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
335 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]336 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
337 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
338 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
339 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
340 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
341 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
342 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
343 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
344 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
345 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
346 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
347 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
348 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
349 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
350 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
351 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
352 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
353 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
354 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
355 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
356 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
357 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
358 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
359 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
360 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]361 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
362 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]363 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]364 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]365 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
367 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
368 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
369 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
370 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
371 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
372 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
373 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
374 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]375 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]376 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
377 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
378 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
379 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]380 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
381 // AVX-512 foldable instructions
382 { X86::VMOVPDI2DIZrr,X86::VMOVPDI2DIZmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]383 };
384
385 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]386 unsigned RegOp = OpTbl0[i].RegOp;
387 unsigned MemOp = OpTbl0[i].MemOp;
388 unsigned Flags = OpTbl0[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]389 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
390 RegOp, MemOp, TB_INDEX_0 | Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]391 }
392
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]393 static const X86OpTblEntry OpTbl1[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]394 { X86::CMP16rr, X86::CMP16rm, 0 },
395 { X86::CMP32rr, X86::CMP32rm, 0 },
396 { X86::CMP64rr, X86::CMP64rm, 0 },
397 { X86::CMP8rr, X86::CMP8rm, 0 },
398 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
399 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
400 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
401 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
402 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
403 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
404 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
405 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
406 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
407 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]408 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
409 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
410 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
411 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
412 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
413 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
414 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
415 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]416 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
417 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]418 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
419 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]420 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
421 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
422 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
423 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
424 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
425 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
426 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
427 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]428 { X86::MOV16rr, X86::MOV16rm, 0 },
429 { X86::MOV32rr, X86::MOV32rm, 0 },
430 { X86::MOV64rr, X86::MOV64rm, 0 },
431 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
432 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
433 { X86::MOV8rr, X86::MOV8rm, 0 },
434 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
435 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]436 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
437 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
438 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
439 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]440 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
441 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
442 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
443 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
444 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
445 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
446 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
447 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
448 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
449 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]450 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
451 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
452 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
453 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
454 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
455 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]456 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
457 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
458 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]459 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
460 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
461 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
462 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
463 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
464 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
465 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
466 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
467 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
468 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]469 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]470 { X86::SQRTSDr, X86::SQRTSDm, 0 },
471 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
472 { X86::SQRTSSr, X86::SQRTSSm, 0 },
473 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
474 { X86::TEST16rr, X86::TEST16rm, 0 },
475 { X86::TEST32rr, X86::TEST32rm, 0 },
476 { X86::TEST64rr, X86::TEST64rm, 0 },
477 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]478 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]479 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
480 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]481 // AVX 128-bit versions of foldable instructions
482 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
483 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]484 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
485 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]486 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
487 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]488 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]489 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
490 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
491 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
492 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
493 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
494 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
495 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
496 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
497 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]498 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
499 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
500 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
501 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
502 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
503 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
504 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
505 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
506 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
507 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]508 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]509 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]510 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
511 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]512 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
513 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
514 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
515 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
516 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
517 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
518 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
519 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
520 { X86::VRCPPSr, X86::VRCPPSm, 0 },
521 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 },
522 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
523 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 },
524 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]525 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]526 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]527 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]528 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
529
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]530 // AVX 256-bit foldable instructions
531 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
532 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]533 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]534 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]535 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]536 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
537 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]538
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]539 // AVX2 foldable instructions
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]540 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
541 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
542 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
543 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
544 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
545 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
546 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
547 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 },
548 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]549 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]550 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]551 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
552 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]553
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]554 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]555 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
556 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]557 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
558 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
559 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
560 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
561 { X86::BLCI32rr, X86::BLCI32rm, 0 },
562 { X86::BLCI64rr, X86::BLCI64rm, 0 },
563 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
564 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
565 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
566 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
567 { X86::BLCS32rr, X86::BLCS32rm, 0 },
568 { X86::BLCS64rr, X86::BLCS64rm, 0 },
569 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
570 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]571 { X86::BLSI32rr, X86::BLSI32rm, 0 },
572 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]573 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
574 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]575 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
576 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
577 { X86::BLSR32rr, X86::BLSR32rm, 0 },
578 { X86::BLSR64rr, X86::BLSR64rm, 0 },
579 { X86::BZHI32rr, X86::BZHI32rm, 0 },
580 { X86::BZHI64rr, X86::BZHI64rm, 0 },
581 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
582 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
583 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
584 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
585 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
586 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]587 { X86::RORX32ri, X86::RORX32mi, 0 },
588 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]589 { X86::SARX32rr, X86::SARX32rm, 0 },
590 { X86::SARX64rr, X86::SARX64rm, 0 },
591 { X86::SHRX32rr, X86::SHRX32rm, 0 },
592 { X86::SHRX64rr, X86::SHRX64rm, 0 },
593 { X86::SHLX32rr, X86::SHLX32rm, 0 },
594 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]595 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
596 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]597 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
598 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
599 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]600 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
601 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]602
603 // AVX-512 foldable instructions
604 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
605 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
Craig Topper684abc82013-09-17 06:05:17 +0000[diff] [blame]606 { X86::VMOVDQA32rr, X86::VMOVDQA32rm, TB_ALIGN_64 },
607 { X86::VMOVDQA64rr, X86::VMOVDQA64rm, TB_ALIGN_64 },
608 { X86::VMOVDQU32rr, X86::VMOVDQU32rm, 0 },
609 { X86::VMOVDQU64rr, X86::VMOVDQU64rm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]610 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
611 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]612
613 // AES foldable instructions
614 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
615 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
616 { X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 },
617 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]618 };
619
620 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]621 unsigned RegOp = OpTbl1[i].RegOp;
622 unsigned MemOp = OpTbl1[i].MemOp;
623 unsigned Flags = OpTbl1[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]624 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
625 RegOp, MemOp,
626 // Index 1, folded load
627 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]628 }
629
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]630 static const X86OpTblEntry OpTbl2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]631 { X86::ADC32rr, X86::ADC32rm, 0 },
632 { X86::ADC64rr, X86::ADC64rm, 0 },
633 { X86::ADD16rr, X86::ADD16rm, 0 },
634 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
635 { X86::ADD32rr, X86::ADD32rm, 0 },
636 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
637 { X86::ADD64rr, X86::ADD64rm, 0 },
638 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
639 { X86::ADD8rr, X86::ADD8rm, 0 },
640 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
641 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
642 { X86::ADDSDrr, X86::ADDSDrm, 0 },
643 { X86::ADDSSrr, X86::ADDSSrm, 0 },
644 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
645 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
646 { X86::AND16rr, X86::AND16rm, 0 },
647 { X86::AND32rr, X86::AND32rm, 0 },
648 { X86::AND64rr, X86::AND64rm, 0 },
649 { X86::AND8rr, X86::AND8rm, 0 },
650 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
651 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
652 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
653 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]654 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
655 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
656 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
657 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]658 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
659 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
660 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
661 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
662 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
663 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
664 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
665 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
666 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
667 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
668 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
669 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
670 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
671 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
672 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
673 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
674 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
675 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
676 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
677 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
678 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
679 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
680 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
681 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
682 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
683 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
684 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
685 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
686 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
687 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
688 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
689 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
690 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
691 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
692 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
693 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
694 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
695 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
696 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
697 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
698 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
699 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
700 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
701 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
702 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
703 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
704 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
705 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
706 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
707 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
708 { X86::CMPSDrr, X86::CMPSDrm, 0 },
709 { X86::CMPSSrr, X86::CMPSSrm, 0 },
710 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
711 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
712 { X86::DIVSDrr, X86::DIVSDrm, 0 },
713 { X86::DIVSSrr, X86::DIVSSrm, 0 },
714 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
715 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
716 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
717 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
718 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
719 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
720 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
721 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
722 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
723 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
724 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
725 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
726 { X86::IMUL16rr, X86::IMUL16rm, 0 },
727 { X86::IMUL32rr, X86::IMUL32rm, 0 },
728 { X86::IMUL64rr, X86::IMUL64rm, 0 },
729 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
730 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]731 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
732 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
733 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
734 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
735 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
736 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]737 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]738 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]739 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]740 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]741 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]742 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]743 { X86::MINSDrr, X86::MINSDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]744 { X86::MINSSrr, X86::MINSSrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]745 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]746 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
747 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
748 { X86::MULSDrr, X86::MULSDrm, 0 },
749 { X86::MULSSrr, X86::MULSSrm, 0 },
750 { X86::OR16rr, X86::OR16rm, 0 },
751 { X86::OR32rr, X86::OR32rm, 0 },
752 { X86::OR64rr, X86::OR64rm, 0 },
753 { X86::OR8rr, X86::OR8rm, 0 },
754 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
755 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
756 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
757 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]758 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]759 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
760 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
761 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
762 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
763 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
764 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]765 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
766 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]767 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]768 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]769 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
770 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
771 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
772 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]773 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]774 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
775 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]776 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]777 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
778 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
779 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]780 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]781 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]782 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
783 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]784 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]785 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]786 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]787 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]788 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]789 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]790 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
791 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
792 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
793 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
794 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]795 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
796 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
797 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
798 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
799 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
800 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
801 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
802 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]803 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]804 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]805 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
806 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
807 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
808 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
809 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
810 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
811 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]812 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
813 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
814 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
815 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]816 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
817 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
818 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
819 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
820 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
821 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
822 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
823 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
824 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
825 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
826 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
827 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
828 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
829 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
830 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
831 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
832 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
833 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
834 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
835 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
836 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
837 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
838 { X86::SBB32rr, X86::SBB32rm, 0 },
839 { X86::SBB64rr, X86::SBB64rm, 0 },
840 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
841 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
842 { X86::SUB16rr, X86::SUB16rm, 0 },
843 { X86::SUB32rr, X86::SUB32rm, 0 },
844 { X86::SUB64rr, X86::SUB64rm, 0 },
845 { X86::SUB8rr, X86::SUB8rm, 0 },
846 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
847 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
848 { X86::SUBSDrr, X86::SUBSDrm, 0 },
849 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]850 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]851 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
852 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
853 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
854 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
855 { X86::XOR16rr, X86::XOR16rm, 0 },
856 { X86::XOR32rr, X86::XOR32rm, 0 },
857 { X86::XOR64rr, X86::XOR64rm, 0 },
858 { X86::XOR8rr, X86::XOR8rm, 0 },
859 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]860 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
861 // AVX 128-bit versions of foldable instructions
862 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
863 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
864 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
865 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
866 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
867 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
868 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
869 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
870 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
871 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]872 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
873 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]874 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
875 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]876 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
877 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
878 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]879 { X86::VADDPDrr, X86::VADDPDrm, 0 },
880 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]881 { X86::VADDSDrr, X86::VADDSDrm, 0 },
882 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]883 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
884 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
885 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
886 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
887 { X86::VANDPDrr, X86::VANDPDrm, 0 },
888 { X86::VANDPSrr, X86::VANDPSrm, 0 },
889 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
890 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
891 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
892 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
893 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
894 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]895 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
896 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]897 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
898 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]899 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
900 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
901 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
902 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
903 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
904 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
905 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
906 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
907 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
908 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]909 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
910 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
911 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
912 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]913 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
914 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]915 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]916 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]917 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]918 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]919 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]920 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]921 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]922 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]923 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
924 { X86::VMULPDrr, X86::VMULPDrm, 0 },
925 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]926 { X86::VMULSDrr, X86::VMULSDrm, 0 },
927 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]928 { X86::VORPDrr, X86::VORPDrm, 0 },
929 { X86::VORPSrr, X86::VORPSrm, 0 },
930 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
931 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
932 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
933 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
934 { X86::VPADDBrr, X86::VPADDBrm, 0 },
935 { X86::VPADDDrr, X86::VPADDDrm, 0 },
936 { X86::VPADDQrr, X86::VPADDQrm, 0 },
937 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
938 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
939 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
940 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
941 { X86::VPADDWrr, X86::VPADDWrm, 0 },
942 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
943 { X86::VPANDNrr, X86::VPANDNrm, 0 },
944 { X86::VPANDrr, X86::VPANDrm, 0 },
945 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
946 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
947 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
948 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
949 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
950 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
951 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
952 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
953 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
954 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
955 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
956 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
957 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
958 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
959 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
960 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
961 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
962 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
963 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
964 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
965 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
966 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
967 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
968 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
969 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
970 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
971 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
972 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
973 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
974 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
975 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
976 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
977 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
978 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
979 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
980 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
981 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
982 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
983 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
984 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
985 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
986 { X86::VPORrr, X86::VPORrm, 0 },
987 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
988 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
989 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
990 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
991 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
992 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
993 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
994 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
995 { X86::VPSRADrr, X86::VPSRADrm, 0 },
996 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
997 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
998 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
999 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1000 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1001 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1002 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1003 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1004 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1005 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1006 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1007 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1008 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1009 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1010 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1011 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1012 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1013 { X86::VPXORrr, X86::VPXORrm, 0 },
1014 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1015 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1016 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1017 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1018 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1019 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1020 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1021 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1022 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1023 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1024 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1025 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1026 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1027 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1028 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1029 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1030 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1031 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1032 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1033 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1034 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1035 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1036 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1037 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1038 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1039 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1040 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1041 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1042 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1043 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1044 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1045 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1046 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1047 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1048 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1049 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1050 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1051 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1052 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1053 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1054 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1055 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1056 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1057 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1058 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1059 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1060 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1061 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1062 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1063 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1064 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1065 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1066 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1067 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1068 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1069 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1070 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1071 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1072 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1073 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1074 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1075 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1076 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1077 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1078 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1079 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1080 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1081 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1082 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1083 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1084 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1085 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1086 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1087 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1088 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1089 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1090 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1091 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1092 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1093 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1094 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1095 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1096 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1097 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1098 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1099 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1100 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1101 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
1102 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1103 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
1104 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1105 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1106 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1107 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1108 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1109 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1110 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1111 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1112 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1113 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1114 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1115 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1116 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1117 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1118 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1119 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1120 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1121 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1122 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1123 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1124 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1125 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1126 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1127 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1128 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1129 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1130 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1131 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1132 { X86::VPORYrr, X86::VPORYrm, 0 },
1133 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1134 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1135 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1136 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1137 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1138 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1139 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1140 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1141 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1142 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1143 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1144 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1145 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1146 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1147 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1148 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1149 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1150 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1151 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1152 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1153 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1154 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1155 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1156 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1157 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1158 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1159 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1160 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1161 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1162 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1163 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1164 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1165 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1166 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1167 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1168 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1169 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1170 // FIXME: add AVX 256-bit foldable instructions
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1171
1172 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1173 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1174 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1175 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 },
1176 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 },
1177 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 },
1178 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1179 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1180 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1181 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 },
1182 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 },
1183 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 },
1184 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1185 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1186 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1187 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 },
1188 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 },
1189 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 },
1190 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1191 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1192 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1193 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 },
1194 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 },
1195 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 },
1196 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 },
1197 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 },
1198 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 },
1199 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 },
1200 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 },
1201 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 },
1202 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 },
1203 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 },
1204 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1205
1206 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1207 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1208 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1209 { X86::MULX32rr, X86::MULX32rm, 0 },
1210 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1211 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1212 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1213 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1214 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1215
1216 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1217 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1218 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1219 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1220 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1221 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1222 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1223 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1224 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1225 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1226 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1227 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1228 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1229 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1230 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1231 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1232 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1233 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1234 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1235 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1236 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1237 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1238 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1239 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1240 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1241 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1242 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1243 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1244 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1245 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1246 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1247 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1248 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1249 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1250 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1251 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
1252 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1253 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1254
1255 // AES foldable instructions
1256 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1257 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1258 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1259 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
1260 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, TB_ALIGN_16 },
1261 { X86::VAESDECrr, X86::VAESDECrm, TB_ALIGN_16 },
1262 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, TB_ALIGN_16 },
1263 { X86::VAESENCrr, X86::VAESENCrm, TB_ALIGN_16 },
1264
1265 // SHA foldable instructions
1266 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1267 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1268 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1269 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1270 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1271 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
1272 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1273 };
1274
1275 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]1276 unsigned RegOp = OpTbl2[i].RegOp;
1277 unsigned MemOp = OpTbl2[i].MemOp;
1278 unsigned Flags = OpTbl2[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1279 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1280 RegOp, MemOp,
1281 // Index 2, folded load
1282 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1283 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1284
1285 static const X86OpTblEntry OpTbl3[] = {
1286 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1287 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1288 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1289 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1290 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1291 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1292 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1293
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1294 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1295 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1296 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1297 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1298 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1299 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1300 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1301 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1302 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1303 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1304 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1305 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1306
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1307 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1308 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1309 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1310 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1311 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1312 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1313
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1314 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1315 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1316 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1317 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1318 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1319 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1320 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1321 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1322 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1323 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1324 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1325 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1326
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1327 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1328 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1329 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1330 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1331 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1332 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1333
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1334 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1335 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1336 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1337 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1338 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1339 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1340 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1341 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1342 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1343 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1344 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1345 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1346
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1347 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1348 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1349 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1350 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1351 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1352 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1353
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1354 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1355 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1356 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1357 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1358 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1359 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1360 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1361 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1362 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1363 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1364 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1365 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1366
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1367 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1368 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1369 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1370 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1371 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1372 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1373 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1374 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1375 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1376 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1377 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1378 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1379
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1380 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1381 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1382 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1383 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1384 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1385 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1386 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1387 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1388 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1389 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1390 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1391 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1392
1393 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1394 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1395 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1396 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1397 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1398 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1399 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1400 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1401 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1402 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1403 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1404 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1405 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1406 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1407 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1408 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1409 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1410 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1411 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1412 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1413 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1414 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1415 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1416 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1417 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1418 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1419 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1420 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1421 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1422 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1423 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1424 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1425 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1426 // AVX-512 VPERMI instructions with 3 source operands.
1427 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1428 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1429 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1430 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1431 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1432 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1433 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
1434 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1435 };
1436
1437 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1438 unsigned RegOp = OpTbl3[i].RegOp;
1439 unsigned MemOp = OpTbl3[i].MemOp;
1440 unsigned Flags = OpTbl3[i].Flags;
1441 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1442 RegOp, MemOp,
1443 // Index 3, folded load
1444 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1445 }
1446
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]1447}
1448
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1449void
1450X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1451 MemOp2RegOpTableType &M2RTable,
1452 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1453 if ((Flags & TB_NO_FORWARD) == 0) {
1454 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1455 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1456 }
1457 if ((Flags & TB_NO_REVERSE) == 0) {
1458 assert(!M2RTable.count(MemOp) &&
1459 "Duplicated entries in unfolding maps?");
1460 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1461 }
1462}
1463
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1464bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1465X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1466 unsigned &SrcReg, unsigned &DstReg,
1467 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1468 switch (MI.getOpcode()) {
1469 default: break;
1470 case X86::MOVSX16rr8:
1471 case X86::MOVZX16rr8:
1472 case X86::MOVSX32rr8:
1473 case X86::MOVZX32rr8:
1474 case X86::MOVSX64rr8:
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]1475 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1476 // It's not always legal to reference the low 8-bit of the larger
1477 // register in 32-bit mode.
1478 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1479 case X86::MOVSX32rr16:
1480 case X86::MOVZX32rr16:
1481 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]1482 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1483 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1484 // Be conservative.
1485 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1486 SrcReg = MI.getOperand(1).getReg();
1487 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1488 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]1489 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1490 case X86::MOVSX16rr8:
1491 case X86::MOVZX16rr8:
1492 case X86::MOVSX32rr8:
1493 case X86::MOVZX32rr8:
1494 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1495 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1496 break;
1497 case X86::MOVSX32rr16:
1498 case X86::MOVZX32rr16:
1499 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1500 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1501 break;
1502 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1503 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1504 break;
1505 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1506 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1507 }
1508 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1509 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1510}
1511
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1512/// isFrameOperand - Return true and the FrameIndex if the specified
1513/// operand and follow operands form a reference to the stack frame.
1514bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1515 int &FrameIndex) const {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1516 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1517 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1518 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1519 MI->getOperand(Op+X86::AddrDisp).isImm() &&
1520 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1521 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1522 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1523 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1524 return true;
1525 }
1526 return false;
1527}
1528
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1529static bool isFrameLoadOpcode(int Opcode) {
1530 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]1531 default:
1532 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1533 case X86::MOV8rm:
1534 case X86::MOV16rm:
1535 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]1536 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]1537 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1538 case X86::MOVSSrm:
1539 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]1540 case X86::MOVAPSrm:
1541 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]1542 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1543 case X86::VMOVSSrm:
1544 case X86::VMOVSDrm:
1545 case X86::VMOVAPSrm:
1546 case X86::VMOVAPDrm:
1547 case X86::VMOVDQArm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1548 case X86::VMOVAPSYrm:
1549 case X86::VMOVAPDYrm:
1550 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]1551 case X86::MMX_MOVD64rm:
1552 case X86::MMX_MOVQ64rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1553 case X86::VMOVAPSZrm:
1554 case X86::VMOVUPSZrm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1555 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1556 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1557}
1558
1559static bool isFrameStoreOpcode(int Opcode) {
1560 switch (Opcode) {
1561 default: break;
1562 case X86::MOV8mr:
1563 case X86::MOV16mr:
1564 case X86::MOV32mr:
1565 case X86::MOV64mr:
1566 case X86::ST_FpP64m:
1567 case X86::MOVSSmr:
1568 case X86::MOVSDmr:
1569 case X86::MOVAPSmr:
1570 case X86::MOVAPDmr:
1571 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1572 case X86::VMOVSSmr:
1573 case X86::VMOVSDmr:
1574 case X86::VMOVAPSmr:
1575 case X86::VMOVAPDmr:
1576 case X86::VMOVDQAmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1577 case X86::VMOVAPSYmr:
1578 case X86::VMOVAPDYmr:
1579 case X86::VMOVDQAYmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1580 case X86::VMOVUPSZmr:
1581 case X86::VMOVAPSZmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1582 case X86::MMX_MOVD64mr:
1583 case X86::MMX_MOVQ64mr:
1584 case X86::MMX_MOVNTQmr:
1585 return true;
1586 }
1587 return false;
1588}
1589
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1590unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1591 int &FrameIndex) const {
1592 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1593 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1594 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1595 return 0;
1596}
1597
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1598unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1599 int &FrameIndex) const {
1600 if (isFrameLoadOpcode(MI->getOpcode())) {
1601 unsigned Reg;
1602 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1603 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1604 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1605 const MachineMemOperand *Dummy;
1606 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1607 }
1608 return 0;
1609}
1610
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]1611unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1612 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1613 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1614 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1615 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]1616 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1617 return 0;
1618}
1619
1620unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1621 int &FrameIndex) const {
1622 if (isFrameStoreOpcode(MI->getOpcode())) {
1623 unsigned Reg;
1624 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1625 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1626 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1627 const MachineMemOperand *Dummy;
1628 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1629 }
1630 return 0;
1631}
1632
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1633/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1634/// X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1635static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]1636 // Don't waste compile time scanning use-def chains of physregs.
1637 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1638 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1639 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]1640 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1641 E = MRI.def_instr_end(); I != E; ++I) {
1642 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1643 if (DefMI->getOpcode() != X86::MOVPC32r)
1644 return false;
1645 assert(!isPICBase && "More than one PIC base?");
1646 isPICBase = true;
1647 }
1648 return isPICBase;
1649}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]1650
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]1651bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]1652X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1653 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1654 switch (MI->getOpcode()) {
1655 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1656 case X86::MOV8rm:
1657 case X86::MOV16rm:
1658 case X86::MOV32rm:
1659 case X86::MOV64rm:
1660 case X86::LD_Fp64m:
1661 case X86::MOVSSrm:
1662 case X86::MOVSDrm:
1663 case X86::MOVAPSrm:
1664 case X86::MOVUPSrm:
1665 case X86::MOVAPDrm:
1666 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]1667 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1668 case X86::VMOVSSrm:
1669 case X86::VMOVSDrm:
1670 case X86::VMOVAPSrm:
1671 case X86::VMOVUPSrm:
1672 case X86::VMOVAPDrm:
1673 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]1674 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1675 case X86::VMOVAPSYrm:
1676 case X86::VMOVUPSYrm:
1677 case X86::VMOVAPDYrm:
1678 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]1679 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1680 case X86::MMX_MOVD64rm:
1681 case X86::MMX_MOVQ64rm:
1682 case X86::FsVMOVAPSrm:
1683 case X86::FsVMOVAPDrm:
1684 case X86::FsMOVAPSrm:
1685 case X86::FsMOVAPDrm: {
1686 // Loads from constant pools are trivially rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1687 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1688 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1689 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1690 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1691 MI->isInvariantLoad(AA)) {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1692 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1693 if (BaseReg == 0 || BaseReg == X86::RIP)
1694 return true;
1695 // Allow re-materialization of PIC load.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1696 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1697 return false;
1698 const MachineFunction &MF = *MI->getParent()->getParent();
1699 const MachineRegisterInfo &MRI = MF.getRegInfo();
1700 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]1701 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1702 return false;
1703 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1704
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1705 case X86::LEA32r:
1706 case X86::LEA64r: {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1707 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1708 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1709 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1710 !MI->getOperand(1+X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1711 // lea fi#, lea GV, etc. are all rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1712 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1713 return true;
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1714 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1715 if (BaseReg == 0)
1716 return true;
1717 // Allow re-materialization of lea PICBase + x.
1718 const MachineFunction &MF = *MI->getParent()->getParent();
1719 const MachineRegisterInfo &MRI = MF.getRegInfo();
1720 return regIsPICBase(BaseReg, MRI);
1721 }
1722 return false;
1723 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1724 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1725
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]1726 // All other instructions marked M_REMATERIALIZABLE are always trivially
1727 // rematerializable.
1728 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1729}
1730
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1731/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1732/// would clobber the EFLAGS condition register. Note the result may be
1733/// conservative. If it cannot definitely determine the safety after visiting
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1734/// a few instructions in each direction it assumes it's not safe.
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1735static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1736 MachineBasicBlock::iterator I) {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1737 MachineBasicBlock::iterator E = MBB.end();
1738
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1739 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1740 // safety after visiting 4 instructions in each direction, we will assume
1741 // it's not safe.
1742 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1743 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1744 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1745 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1746 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]1747 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1748 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1749 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1750 continue;
1751 if (MO.getReg() == X86::EFLAGS) {
1752 if (MO.isUse())
1753 return false;
1754 SeenDef = true;
1755 }
1756 }
1757
1758 if (SeenDef)
1759 // This instruction defines EFLAGS, no need to look any further.
1760 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1761 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1762 // Skip over DBG_VALUE.
1763 while (Iter != E && Iter->isDebugValue())
1764 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1765 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]1766
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1767 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1768 // live in.
1769 if (Iter == E) {
1770 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1771 SE = MBB.succ_end(); SI != SE; ++SI)
1772 if ((*SI)->isLiveIn(X86::EFLAGS))
1773 return false;
1774 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1775 }
1776
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1777 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1778 Iter = I;
1779 for (unsigned i = 0; i < 4; ++i) {
1780 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]1781 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1782 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1783 return !MBB.isLiveIn(X86::EFLAGS);
1784
1785 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1786 // Skip over DBG_VALUE.
1787 while (Iter != B && Iter->isDebugValue())
1788 --Iter;
1789
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1790 bool SawKill = false;
1791 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1792 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]1793 // A register mask may clobber EFLAGS, but we should still look for a
1794 // live EFLAGS def.
1795 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1796 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1797 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1798 if (MO.isDef()) return MO.isDead();
1799 if (MO.isKill()) SawKill = true;
1800 }
1801 }
1802
1803 if (SawKill)
1804 // This instruction kills EFLAGS and doesn't redefine it, so
1805 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]1806 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1807 }
1808
1809 // Conservative answer.
1810 return false;
1811}
1812
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1813void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1814 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1815 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]1816 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1817 const TargetRegisterInfo &TRI) const {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]1818 // MOV32r0 is implemented with a xor which clobbers condition code.
1819 // Re-materialize it as movri instructions to avoid side effects.
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1820 unsigned Opc = Orig->getOpcode();
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]1821 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1822 DebugLoc DL = Orig->getDebugLoc();
1823 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1824 .addImm(0);
1825 } else {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1826 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1827 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1828 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]1829
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]1830 MachineInstr *NewMI = std::prev(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1831 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1832}
1833
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1834/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1835/// is not marked dead.
1836static bool hasLiveCondCodeDef(MachineInstr *MI) {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1837 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1838 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1839 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1840 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1841 return true;
1842 }
1843 }
1844 return false;
1845}
1846
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]1847/// getTruncatedShiftCount - check whether the shift count for a machine operand
1848/// is non-zero.
1849inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1850 unsigned ShiftAmtOperandIdx) {
1851 // The shift count is six bits with the REX.W prefix and five bits without.
1852 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1853 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1854 return Imm & ShiftCountMask;
1855}
1856
1857/// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1858/// can be represented by a LEA instruction.
1859inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1860 // Left shift instructions can be transformed into load-effective-address
1861 // instructions if we can encode them appropriately.
1862 // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1863 // The SIB.scale field is two bits wide which means that we can encode any
1864 // shift amount less than 4.
1865 return ShAmt < 4 && ShAmt > 0;
1866}
1867
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]1868bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1869 unsigned Opc, bool AllowSP,
1870 unsigned &NewSrc, bool &isKill, bool &isUndef,
1871 MachineOperand &ImplicitOp) const {
1872 MachineFunction &MF = *MI->getParent()->getParent();
1873 const TargetRegisterClass *RC;
1874 if (AllowSP) {
1875 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1876 } else {
1877 RC = Opc != X86::LEA32r ?
1878 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1879 }
1880 unsigned SrcReg = Src.getReg();
1881
1882 // For both LEA64 and LEA32 the register already has essentially the right
1883 // type (32-bit or 64-bit) we may just need to forbid SP.
1884 if (Opc != X86::LEA64_32r) {
1885 NewSrc = SrcReg;
1886 isKill = Src.isKill();
1887 isUndef = Src.isUndef();
1888
1889 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1890 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1891 return false;
1892
1893 return true;
1894 }
1895
1896 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1897 // another we need to add 64-bit registers to the final MI.
1898 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1899 ImplicitOp = Src;
1900 ImplicitOp.setImplicit();
1901
1902 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1903 MachineBasicBlock::LivenessQueryResult LQR =
1904 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1905
1906 switch (LQR) {
1907 case MachineBasicBlock::LQR_Unknown:
1908 // We can't give sane liveness flags to the instruction, abandon LEA
1909 // formation.
1910 return false;
1911 case MachineBasicBlock::LQR_Live:
1912 isKill = MI->killsRegister(SrcReg);
1913 isUndef = false;
1914 break;
1915 default:
1916 // The physreg itself is dead, so we have to use it as an <undef>.
1917 isKill = false;
1918 isUndef = true;
1919 break;
1920 }
1921 } else {
1922 // Virtual register of the wrong class, we have to create a temporary 64-bit
1923 // vreg to feed into the LEA.
1924 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1925 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1926 get(TargetOpcode::COPY))
1927 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1928 .addOperand(Src);
1929
1930 // Which is obviously going to be dead after we're done with it.
1931 isKill = true;
1932 isUndef = false;
1933 }
1934
1935 // We've set all the parameters without issue.
1936 return true;
1937}
1938
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1939/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1940/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1941/// to a 32-bit superregister and then truncating back down to a 16-bit
1942/// subregister.
1943MachineInstr *
1944X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1945 MachineFunction::iterator &MFI,
1946 MachineBasicBlock::iterator &MBBI,
1947 LiveVariables *LV) const {
1948 MachineInstr *MI = MBBI;
1949 unsigned Dest = MI->getOperand(0).getReg();
1950 unsigned Src = MI->getOperand(1).getReg();
1951 bool isDead = MI->getOperand(0).isDead();
1952 bool isKill = MI->getOperand(1).isKill();
1953
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1954 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1955 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]1956 unsigned Opc, leaInReg;
1957 if (TM.getSubtarget<X86Subtarget>().is64Bit()) {
1958 Opc = X86::LEA64_32r;
1959 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1960 } else {
1961 Opc = X86::LEA32r;
1962 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1963 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1964
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1965 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1966 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1967 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]1968 // movw (%rbp,%rcx,2), %dx
1969 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1970 // But testing has shown this *does* help performance in 64-bit mode (at
1971 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1972 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1973 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]1974 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1975 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1976 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1977
1978 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1979 get(Opc), leaOutReg);
1980 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]1981 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1982 case X86::SHL16ri: {
1983 unsigned ShAmt = MI->getOperand(2).getImm();
1984 MIB.addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1985 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1986 break;
1987 }
1988 case X86::INC16r:
1989 case X86::INC64_16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1990 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1991 break;
1992 case X86::DEC16r:
1993 case X86::DEC64_16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1994 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1995 break;
1996 case X86::ADD16ri:
1997 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]1998 case X86::ADD16ri_DB:
1999 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2000 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2001 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2002 case X86::ADD16rr:
2003 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2004 unsigned Src2 = MI->getOperand(2).getReg();
2005 bool isKill2 = MI->getOperand(2).isKill();
2006 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2007 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2008 if (Src == Src2) {
2009 // ADD16rr %reg1028<kill>, %reg1028
2010 // just a single insert_subreg.
2011 addRegReg(MIB, leaInReg, true, leaInReg, false);
2012 } else {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2013 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2014 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2015 else
2016 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2017 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2018 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2019 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2020 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2021 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2022 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2023 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2024 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2025 }
2026 if (LV && isKill2 && InsMI2)
2027 LV->replaceKillInstruction(Src2, MI, InsMI2);
2028 break;
2029 }
2030 }
2031
2032 MachineInstr *NewMI = MIB;
2033 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2034 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2035 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2036 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2037
2038 if (LV) {
2039 // Update live variables
2040 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2041 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2042 if (isKill)
2043 LV->replaceKillInstruction(Src, MI, InsMI);
2044 if (isDead)
2045 LV->replaceKillInstruction(Dest, MI, ExtMI);
2046 }
2047
2048 return ExtMI;
2049}
2050
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2051/// convertToThreeAddress - This method must be implemented by targets that
2052/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2053/// may be able to convert a two-address instruction into a true
2054/// three-address instruction on demand. This allows the X86 target (for
2055/// example) to convert ADD and SHL instructions into LEA instructions if they
2056/// would require register copies due to two-addressness.
2057///
2058/// This method returns a null pointer if the transformation cannot be
2059/// performed, otherwise it returns the new instruction.
2060///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2061MachineInstr *
2062X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2063 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]2064 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2065 MachineInstr *MI = MBBI;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2066
2067 // The following opcodes also sets the condition code register(s). Only
2068 // convert them to equivalent lea if the condition code register def's
2069 // are dead!
2070 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2071 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2072
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2073 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2074 // All instructions input are two-addr instructions. Get the known operands.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2075 const MachineOperand &Dest = MI->getOperand(0);
2076 const MachineOperand &Src = MI->getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2077
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2078 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2079 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2080 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2081 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2082 bool DisableLEA16 = true;
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2083 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2084
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2085 unsigned MIOpc = MI->getOpcode();
2086 switch (MIOpc) {
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2087 case X86::SHUFPSrri: {
2088 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2089 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return nullptr;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2090
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]2091 unsigned B = MI->getOperand(1).getReg();
2092 unsigned C = MI->getOperand(2).getReg();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2093 if (B != C) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2094 unsigned M = MI->getOperand(3).getImm();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2095 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2096 .addOperand(Dest).addOperand(Src).addImm(M);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2097 break;
2098 }
Craig Toppere52d86a2012-01-13 09:21:41 +0000[diff] [blame]2099 case X86::SHUFPDrri: {
2100 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2101 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return nullptr;
Craig Toppere52d86a2012-01-13 09:21:41 +0000[diff] [blame]2102
2103 unsigned B = MI->getOperand(1).getReg();
2104 unsigned C = MI->getOperand(2).getReg();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2105 if (B != C) return nullptr;
Craig Toppere52d86a2012-01-13 09:21:41 +0000[diff] [blame]2106 unsigned M = MI->getOperand(3).getImm();
2107
2108 // Convert to PSHUFD mask.
2109 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
2110
2111 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2112 .addOperand(Dest).addOperand(Src).addImm(M);
Craig Toppere52d86a2012-01-13 09:21:41 +0000[diff] [blame]2113 break;
2114 }
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2115 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2116 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2117 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2118 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2119
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2120 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2121 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2122 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2123 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2124 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2125
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2126 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2127 .addOperand(Dest)
2128 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2129 break;
2130 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2131 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2132 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2133 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2134 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2135
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2136 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2137
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2138 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2139 bool isKill, isUndef;
2140 unsigned SrcReg;
2141 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2142 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2143 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2144 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2145
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2146 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2147 .addOperand(Dest)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2148 .addReg(0).addImm(1 << ShAmt)
2149 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2150 .addImm(0).addReg(0);
2151 if (ImplicitOp.getReg() != 0)
2152 MIB.addOperand(ImplicitOp);
2153 NewMI = MIB;
2154
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2155 break;
2156 }
2157 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2158 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2159 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2160 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2161
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2162 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2163 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2164 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2165 .addOperand(Dest)
2166 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2167 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2168 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2169 default: {
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2170
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2171 switch (MIOpc) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2172 default: return nullptr;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2173 case X86::INC64r:
Dan Gohmanbeac19e2009-01-06 23:34:46 +0000[diff] [blame]2174 case X86::INC32r:
2175 case X86::INC64_32r: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2176 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Evan Cheng82bc90a2007-10-09 07:14:53 +0000[diff] [blame]2177 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2178 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2179 bool isKill, isUndef;
2180 unsigned SrcReg;
2181 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2182 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2183 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2184 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2185
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2186 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2187 .addOperand(Dest)
2188 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2189 if (ImplicitOp.getReg() != 0)
2190 MIB.addOperand(ImplicitOp);
2191
2192 NewMI = addOffset(MIB, 1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2193 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2194 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2195 case X86::INC16r:
2196 case X86::INC64_16r:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2197 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2198 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2199 : nullptr;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2200 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2201 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2202 .addOperand(Dest).addOperand(Src), 1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2203 break;
2204 case X86::DEC64r:
Dan Gohmanbeac19e2009-01-06 23:34:46 +0000[diff] [blame]2205 case X86::DEC32r:
2206 case X86::DEC64_32r: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2207 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Evan Cheng82bc90a2007-10-09 07:14:53 +0000[diff] [blame]2208 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2209 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2210
2211 bool isKill, isUndef;
2212 unsigned SrcReg;
2213 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2214 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2215 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2216 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2217
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2218 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2219 .addOperand(Dest)
2220 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2221 if (ImplicitOp.getReg() != 0)
2222 MIB.addOperand(ImplicitOp);
2223
2224 NewMI = addOffset(MIB, -1);
2225
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2226 break;
2227 }
2228 case X86::DEC16r:
2229 case X86::DEC64_16r:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2230 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2231 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2232 : nullptr;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2233 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2234 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2235 .addOperand(Dest).addOperand(Src), -1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2236 break;
2237 case X86::ADD64rr:
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2238 case X86::ADD64rr_DB:
2239 case X86::ADD32rr:
2240 case X86::ADD32rr_DB: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2241 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2242 unsigned Opc;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2243 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2244 Opc = X86::LEA64r;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2245 else
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2246 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2247
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2248 bool isKill, isUndef;
2249 unsigned SrcReg;
2250 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2251 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2252 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2253 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2254
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2255 const MachineOperand &Src2 = MI->getOperand(2);
2256 bool isKill2, isUndef2;
2257 unsigned SrcReg2;
2258 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2259 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2260 SrcReg2, isKill2, isUndef2, ImplicitOp2))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2261 return nullptr;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2262
2263 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2264 .addOperand(Dest);
2265 if (ImplicitOp.getReg() != 0)
2266 MIB.addOperand(ImplicitOp);
2267 if (ImplicitOp2.getReg() != 0)
2268 MIB.addOperand(ImplicitOp2);
2269
2270 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
Nadav Rotem4968e452012-07-16 10:52:25 +0000[diff] [blame]2271
2272 // Preserve undefness of the operands.
Tim Northover339bf152013-06-01 10:23:46 +0000[diff] [blame]2273 NewMI->getOperand(1).setIsUndef(isUndef);
2274 NewMI->getOperand(3).setIsUndef(isUndef2);
Nadav Rotem4968e452012-07-16 10:52:25 +0000[diff] [blame]2275
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2276 if (LV && Src2.isKill())
2277 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2278 break;
2279 }
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2280 case X86::ADD16rr:
2281 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2282 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2283 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2284 : nullptr;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2285 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2286 unsigned Src2 = MI->getOperand(2).getReg();
2287 bool isKill2 = MI->getOperand(2).isKill();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2288 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2289 .addOperand(Dest),
2290 Src.getReg(), Src.isKill(), Src2, isKill2);
2291
2292 // Preserve undefness of the operands.
2293 bool isUndef = MI->getOperand(1).isUndef();
2294 bool isUndef2 = MI->getOperand(2).isUndef();
2295 NewMI->getOperand(1).setIsUndef(isUndef);
2296 NewMI->getOperand(3).setIsUndef(isUndef2);
2297
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2298 if (LV && isKill2)
2299 LV->replaceKillInstruction(Src2, MI, NewMI);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2300 break;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2301 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2302 case X86::ADD64ri32:
2303 case X86::ADD64ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2304 case X86::ADD64ri32_DB:
2305 case X86::ADD64ri8_DB:
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2306 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2307 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2308 .addOperand(Dest).addOperand(Src),
2309 MI->getOperand(2).getImm());
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2310 break;
2311 case X86::ADD32ri:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2312 case X86::ADD32ri8:
2313 case X86::ADD32ri_DB:
2314 case X86::ADD32ri8_DB: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2315 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Tim Northover339bf152013-06-01 10:23:46 +0000[diff] [blame]2316 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2317
2318 bool isKill, isUndef;
2319 unsigned SrcReg;
2320 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2321 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2322 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2323 return nullptr;
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2324
2325 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2326 .addOperand(Dest)
2327 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2328 if (ImplicitOp.getReg() != 0)
2329 MIB.addOperand(ImplicitOp);
2330
2331 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2332 break;
2333 }
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2334 case X86::ADD16ri:
2335 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2336 case X86::ADD16ri_DB:
2337 case X86::ADD16ri8_DB:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2338 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2339 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2340 : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2341 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2342 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2343 .addOperand(Dest).addOperand(Src),
2344 MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2345 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2346 }
2347 }
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2348 }
2349
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2350 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2351
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2352 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2353 if (Src.isKill())
2354 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2355 if (Dest.isDead())
2356 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2357 }
2358
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2359 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]2360 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2361}
2362
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2363/// commuteInstruction - We have a few instructions that must be hacked on to
2364/// commute them.
2365///
Evan Cheng03553bb2008-06-16 07:33:11 +0000[diff] [blame]2366MachineInstr *
2367X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2368 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2369 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2370 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2371 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2372 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2373 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2374 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2375 unsigned Opc;
2376 unsigned Size;
2377 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2378 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2379 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2380 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2381 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2382 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2383 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2384 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2385 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]2386 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2387 if (NewMI) {
2388 MachineFunction &MF = *MI->getParent()->getParent();
2389 MI = MF.CloneMachineInstr(MI);
2390 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]2391 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2392 MI->setDesc(get(Opc));
2393 MI->getOperand(3).setImm(Size-Amt);
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2394 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2395 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2396 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2397 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2398 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2399 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2400 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2401 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2402 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2403 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2404 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2405 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2406 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2407 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2408 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2409 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2410 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2411 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2412 unsigned Opc;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2413 switch (MI->getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2414 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2415 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2416 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2417 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2418 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2419 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2420 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2421 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2422 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2423 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2424 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2425 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2426 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]2427 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2428 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2429 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2430 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2431 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2432 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2433 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2434 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2435 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2436 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2437 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2438 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2439 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2440 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2441 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2442 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2443 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2444 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2445 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2446 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2447 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2448 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2449 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2450 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2451 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2452 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2453 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2454 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2455 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2456 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2457 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2458 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2459 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2460 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2461 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2462 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2463 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2464 if (NewMI) {
2465 MachineFunction &MF = *MI->getParent()->getParent();
2466 MI = MF.CloneMachineInstr(MI);
2467 NewMI = false;
2468 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]2469 MI->setDesc(get(Opc));
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2470 // Fallthrough intended.
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2471 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2472 default:
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2473 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2474 }
2475}
2476
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2477bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2478 unsigned &SrcOpIdx2) const {
2479 switch (MI->getOpcode()) {
2480 case X86::VFMADDPDr231r:
2481 case X86::VFMADDPSr231r:
2482 case X86::VFMADDSDr231r:
2483 case X86::VFMADDSSr231r:
2484 case X86::VFMSUBPDr231r:
2485 case X86::VFMSUBPSr231r:
2486 case X86::VFMSUBSDr231r:
2487 case X86::VFMSUBSSr231r:
2488 case X86::VFNMADDPDr231r:
2489 case X86::VFNMADDPSr231r:
2490 case X86::VFNMADDSDr231r:
2491 case X86::VFNMADDSSr231r:
2492 case X86::VFNMSUBPDr231r:
2493 case X86::VFNMSUBPSr231r:
2494 case X86::VFNMSUBSDr231r:
2495 case X86::VFNMSUBSSr231r:
2496 case X86::VFMADDPDr231rY:
2497 case X86::VFMADDPSr231rY:
2498 case X86::VFMSUBPDr231rY:
2499 case X86::VFMSUBPSr231rY:
2500 case X86::VFNMADDPDr231rY:
2501 case X86::VFNMADDPSr231rY:
2502 case X86::VFNMSUBPDr231rY:
2503 case X86::VFNMSUBPSr231rY:
2504 SrcOpIdx1 = 2;
2505 SrcOpIdx2 = 3;
2506 return true;
2507 default:
2508 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2509 }
2510}
2511
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2512static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2513 switch (BrOpc) {
2514 default: return X86::COND_INVALID;
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2515 case X86::JE_4: return X86::COND_E;
2516 case X86::JNE_4: return X86::COND_NE;
2517 case X86::JL_4: return X86::COND_L;
2518 case X86::JLE_4: return X86::COND_LE;
2519 case X86::JG_4: return X86::COND_G;
2520 case X86::JGE_4: return X86::COND_GE;
2521 case X86::JB_4: return X86::COND_B;
2522 case X86::JBE_4: return X86::COND_BE;
2523 case X86::JA_4: return X86::COND_A;
2524 case X86::JAE_4: return X86::COND_AE;
2525 case X86::JS_4: return X86::COND_S;
2526 case X86::JNS_4: return X86::COND_NS;
2527 case X86::JP_4: return X86::COND_P;
2528 case X86::JNP_4: return X86::COND_NP;
2529 case X86::JO_4: return X86::COND_O;
2530 case X86::JNO_4: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2531 }
2532}
2533
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2534/// getCondFromSETOpc - return condition code of a SET opcode.
2535static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2536 switch (Opc) {
2537 default: return X86::COND_INVALID;
2538 case X86::SETAr: case X86::SETAm: return X86::COND_A;
2539 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2540 case X86::SETBr: case X86::SETBm: return X86::COND_B;
2541 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2542 case X86::SETEr: case X86::SETEm: return X86::COND_E;
2543 case X86::SETGr: case X86::SETGm: return X86::COND_G;
2544 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2545 case X86::SETLr: case X86::SETLm: return X86::COND_L;
2546 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2547 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2548 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2549 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2550 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2551 case X86::SETOr: case X86::SETOm: return X86::COND_O;
2552 case X86::SETPr: case X86::SETPm: return X86::COND_P;
2553 case X86::SETSr: case X86::SETSm: return X86::COND_S;
2554 }
2555}
2556
2557/// getCondFromCmovOpc - return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]2558X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2559 switch (Opc) {
2560 default: return X86::COND_INVALID;
2561 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2562 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2563 return X86::COND_A;
2564 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2565 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2566 return X86::COND_AE;
2567 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2568 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2569 return X86::COND_B;
2570 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2571 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2572 return X86::COND_BE;
2573 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2574 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2575 return X86::COND_E;
2576 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2577 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2578 return X86::COND_G;
2579 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2580 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2581 return X86::COND_GE;
2582 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2583 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2584 return X86::COND_L;
2585 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2586 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2587 return X86::COND_LE;
2588 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2589 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2590 return X86::COND_NE;
2591 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2592 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2593 return X86::COND_NO;
2594 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2595 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2596 return X86::COND_NP;
2597 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2598 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2599 return X86::COND_NS;
2600 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2601 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2602 return X86::COND_O;
2603 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2604 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2605 return X86::COND_P;
2606 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2607 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2608 return X86::COND_S;
2609 }
2610}
2611
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2612unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2613 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2614 default: llvm_unreachable("Illegal condition code!");
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2615 case X86::COND_E: return X86::JE_4;
2616 case X86::COND_NE: return X86::JNE_4;
2617 case X86::COND_L: return X86::JL_4;
2618 case X86::COND_LE: return X86::JLE_4;
2619 case X86::COND_G: return X86::JG_4;
2620 case X86::COND_GE: return X86::JGE_4;
2621 case X86::COND_B: return X86::JB_4;
2622 case X86::COND_BE: return X86::JBE_4;
2623 case X86::COND_A: return X86::JA_4;
2624 case X86::COND_AE: return X86::JAE_4;
2625 case X86::COND_S: return X86::JS_4;
2626 case X86::COND_NS: return X86::JNS_4;
2627 case X86::COND_P: return X86::JP_4;
2628 case X86::COND_NP: return X86::JNP_4;
2629 case X86::COND_O: return X86::JO_4;
2630 case X86::COND_NO: return X86::JNO_4;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2631 }
2632}
2633
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2634/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2635/// e.g. turning COND_E to COND_NE.
2636X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2637 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2638 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2639 case X86::COND_E: return X86::COND_NE;
2640 case X86::COND_NE: return X86::COND_E;
2641 case X86::COND_L: return X86::COND_GE;
2642 case X86::COND_LE: return X86::COND_G;
2643 case X86::COND_G: return X86::COND_LE;
2644 case X86::COND_GE: return X86::COND_L;
2645 case X86::COND_B: return X86::COND_AE;
2646 case X86::COND_BE: return X86::COND_A;
2647 case X86::COND_A: return X86::COND_BE;
2648 case X86::COND_AE: return X86::COND_B;
2649 case X86::COND_S: return X86::COND_NS;
2650 case X86::COND_NS: return X86::COND_S;
2651 case X86::COND_P: return X86::COND_NP;
2652 case X86::COND_NP: return X86::COND_P;
2653 case X86::COND_O: return X86::COND_NO;
2654 case X86::COND_NO: return X86::COND_O;
2655 }
2656}
2657
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2658/// getSwappedCondition - assume the flags are set by MI(a,b), return
2659/// the condition code if we modify the instructions such that flags are
2660/// set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]2661static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2662 switch (CC) {
2663 default: return X86::COND_INVALID;
2664 case X86::COND_E: return X86::COND_E;
2665 case X86::COND_NE: return X86::COND_NE;
2666 case X86::COND_L: return X86::COND_G;
2667 case X86::COND_LE: return X86::COND_GE;
2668 case X86::COND_G: return X86::COND_L;
2669 case X86::COND_GE: return X86::COND_LE;
2670 case X86::COND_B: return X86::COND_A;
2671 case X86::COND_BE: return X86::COND_AE;
2672 case X86::COND_A: return X86::COND_B;
2673 case X86::COND_AE: return X86::COND_BE;
2674 }
2675}
2676
2677/// getSETFromCond - Return a set opcode for the given condition and
2678/// whether it has memory operand.
2679static unsigned getSETFromCond(X86::CondCode CC,
2680 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]2681 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2682 { X86::SETAr, X86::SETAm },
2683 { X86::SETAEr, X86::SETAEm },
2684 { X86::SETBr, X86::SETBm },
2685 { X86::SETBEr, X86::SETBEm },
2686 { X86::SETEr, X86::SETEm },
2687 { X86::SETGr, X86::SETGm },
2688 { X86::SETGEr, X86::SETGEm },
2689 { X86::SETLr, X86::SETLm },
2690 { X86::SETLEr, X86::SETLEm },
2691 { X86::SETNEr, X86::SETNEm },
2692 { X86::SETNOr, X86::SETNOm },
2693 { X86::SETNPr, X86::SETNPm },
2694 { X86::SETNSr, X86::SETNSm },
2695 { X86::SETOr, X86::SETOm },
2696 { X86::SETPr, X86::SETPm },
2697 { X86::SETSr, X86::SETSm }
2698 };
2699
2700 assert(CC < 16 && "Can only handle standard cond codes");
2701 return Opc[CC][HasMemoryOperand ? 1 : 0];
2702}
2703
2704/// getCMovFromCond - Return a cmov opcode for the given condition,
2705/// register size in bytes, and operand type.
2706static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
2707 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]2708 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2709 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2710 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2711 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2712 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2713 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2714 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2715 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2716 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2717 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2718 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2719 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2720 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2721 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2722 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2723 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2724 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2725 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2726 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2727 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2728 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2729 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2730 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2731 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2732 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2733 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2734 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2735 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2736 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2737 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2738 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2739 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2740 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2741 };
2742
2743 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2744 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2745 switch(RegBytes) {
2746 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2747 case 2: return Opc[Idx][0];
2748 case 4: return Opc[Idx][1];
2749 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2750 }
2751}
2752
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]2753bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2754 if (!MI->isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2755
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2756 // Conditional branch is a special case.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2757 if (MI->isBranch() && !MI->isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2758 return true;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2759 if (!MI->isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2760 return true;
2761 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]2762}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2763
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2764bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2765 MachineBasicBlock *&TBB,
2766 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2767 SmallVectorImpl<MachineOperand> &Cond,
2768 bool AllowModify) const {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2769 // Start from the bottom of the block and work up, examining the
2770 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2771 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2772 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2773 while (I != MBB.begin()) {
2774 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]2775 if (I->isDebugValue())
2776 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2777
2778 // Working from the bottom, when we see a non-terminator instruction, we're
2779 // done.
Jakob Stoklund Olesenc30b4dd2010-07-16 17:41:44 +0000[diff] [blame]2780 if (!isUnpredicatedTerminator(I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2781 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2782
2783 // A terminator that isn't a branch can't easily be handled by this
2784 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2785 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2786 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2787
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2788 // Handle unconditional branches.
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2789 if (I->getOpcode() == X86::JMP_4) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2790 UnCondBrIter = I;
2791
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2792 if (!AllowModify) {
2793 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]2794 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2795 }
2796
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2797 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2798 while (std::next(I) != MBB.end())
2799 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2800
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2801 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2802 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2803
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2804 // Delete the JMP if it's equivalent to a fall-through.
2805 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2806 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2807 I->eraseFromParent();
2808 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2809 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2810 continue;
2811 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2812
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2813 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2814 TBB = I->getOperand(0).getMBB();
2815 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2816 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2817
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2818 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2819 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2820 if (BranchCode == X86::COND_INVALID)
2821 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2822
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2823 // Working from the bottom, handle the first conditional branch.
2824 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2825 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2826 if (AllowModify && UnCondBrIter != MBB.end() &&
2827 MBB.isLayoutSuccessor(TargetBB)) {
2828 // If we can modify the code and it ends in something like:
2829 //
2830 // jCC L1
2831 // jmp L2
2832 // L1:
2833 // ...
2834 // L2:
2835 //
2836 // Then we can change this to:
2837 //
2838 // jnCC L2
2839 // L1:
2840 // ...
2841 // L2:
2842 //
2843 // Which is a bit more efficient.
2844 // We conditionally jump to the fall-through block.
2845 BranchCode = GetOppositeBranchCondition(BranchCode);
2846 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2847 MachineBasicBlock::iterator OldInst = I;
2848
2849 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2850 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2851 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2852 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2853
2854 OldInst->eraseFromParent();
2855 UnCondBrIter->eraseFromParent();
2856
2857 // Restart the analysis.
2858 UnCondBrIter = MBB.end();
2859 I = MBB.end();
2860 continue;
2861 }
2862
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2863 FBB = TBB;
2864 TBB = I->getOperand(0).getMBB();
2865 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2866 continue;
2867 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2868
2869 // Handle subsequent conditional branches. Only handle the case where all
2870 // conditional branches branch to the same destination and their condition
2871 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2872 assert(Cond.size() == 1);
2873 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2874
2875 // Only handle the case where all conditional branches branch to the same
2876 // destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2877 if (TBB != I->getOperand(0).getMBB())
2878 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2879
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2880 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2881 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2882 if (OldBranchCode == BranchCode)
2883 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2884
2885 // If they differ, see if they fit one of the known patterns. Theoretically,
2886 // we could handle more patterns here, but we shouldn't expect to see them
2887 // if instruction selection has done a reasonable job.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2888 if ((OldBranchCode == X86::COND_NP &&
2889 BranchCode == X86::COND_E) ||
2890 (OldBranchCode == X86::COND_E &&
2891 BranchCode == X86::COND_NP))
2892 BranchCode = X86::COND_NP_OR_E;
2893 else if ((OldBranchCode == X86::COND_P &&
2894 BranchCode == X86::COND_NE) ||
2895 (OldBranchCode == X86::COND_NE &&
2896 BranchCode == X86::COND_P))
2897 BranchCode = X86::COND_NE_OR_P;
2898 else
2899 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2900
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2901 // Update the MachineOperand.
2902 Cond[0].setImm(BranchCode);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]2903 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2904
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2905 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2906}
2907
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2908unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2909 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2910 unsigned Count = 0;
2911
2912 while (I != MBB.begin()) {
2913 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]2914 if (I->isDebugValue())
2915 continue;
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2916 if (I->getOpcode() != X86::JMP_4 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2917 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2918 break;
2919 // Remove the branch.
2920 I->eraseFromParent();
2921 I = MBB.end();
2922 ++Count;
2923 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2924
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2925 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2926}
2927
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2928unsigned
2929X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2930 MachineBasicBlock *FBB,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2931 const SmallVectorImpl<MachineOperand> &Cond,
2932 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2933 // Shouldn't be a fall through.
2934 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]2935 assert((Cond.size() == 1 || Cond.size() == 0) &&
2936 "X86 branch conditions have one component!");
2937
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2938 if (Cond.empty()) {
2939 // Unconditional branch?
2940 assert(!FBB && "Unconditional branch with multiple successors!");
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2941 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2942 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2943 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2944
2945 // Conditional branch.
2946 unsigned Count = 0;
2947 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2948 switch (CC) {
2949 case X86::COND_NP_OR_E:
2950 // Synthesize NP_OR_E with two branches.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2951 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2952 ++Count;
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2953 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2954 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2955 break;
2956 case X86::COND_NE_OR_P:
2957 // Synthesize NE_OR_P with two branches.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2958 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2959 ++Count;
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2960 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2961 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2962 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2963 default: {
2964 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2965 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2966 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2967 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2968 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2969 if (FBB) {
2970 // Two-way Conditional branch. Insert the second branch.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2971 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2972 ++Count;
2973 }
2974 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2975}
2976
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2977bool X86InstrInfo::
2978canInsertSelect(const MachineBasicBlock &MBB,
2979 const SmallVectorImpl<MachineOperand> &Cond,
2980 unsigned TrueReg, unsigned FalseReg,
2981 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2982 // Not all subtargets have cmov instructions.
2983 if (!TM.getSubtarget<X86Subtarget>().hasCMov())
2984 return false;
2985 if (Cond.size() != 1)
2986 return false;
2987 // We cannot do the composite conditions, at least not in SSA form.
2988 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2989 return false;
2990
2991 // Check register classes.
2992 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2993 const TargetRegisterClass *RC =
2994 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2995 if (!RC)
2996 return false;
2997
2998 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2999 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3000 X86::GR32RegClass.hasSubClassEq(RC) ||
3001 X86::GR64RegClass.hasSubClassEq(RC)) {
3002 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3003 // Bridge. Probably Ivy Bridge as well.
3004 CondCycles = 2;
3005 TrueCycles = 2;
3006 FalseCycles = 2;
3007 return true;
3008 }
3009
3010 // Can't do vectors.
3011 return false;
3012}
3013
3014void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3015 MachineBasicBlock::iterator I, DebugLoc DL,
3016 unsigned DstReg,
3017 const SmallVectorImpl<MachineOperand> &Cond,
3018 unsigned TrueReg, unsigned FalseReg) const {
3019 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3020 assert(Cond.size() == 1 && "Invalid Cond array");
3021 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3022 MRI.getRegClass(DstReg)->getSize(),
3023 false/*HasMemoryOperand*/);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3024 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3025}
3026
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3027/// isHReg - Test if the given register is a physical h register.
3028static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3029 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3030}
3031
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3032// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3033static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3034 const X86Subtarget& Subtarget) {
3035
3036
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3037 // SrcReg(VR128) -> DestReg(GR64)
3038 // SrcReg(VR64) -> DestReg(GR64)
3039 // SrcReg(GR64) -> DestReg(VR128)
3040 // SrcReg(GR64) -> DestReg(VR64)
3041
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3042 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3043 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3044 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3045 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3046 // Copy from a VR128 register to a GR64 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3047 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3048 X86::MOVPQIto64rr);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3049 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3050 // Copy from a VR64 register to a GR64 register.
3051 return X86::MOVSDto64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3052 } else if (X86::GR64RegClass.contains(SrcReg)) {
3053 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3054 if (X86::VR128XRegClass.contains(DestReg))
3055 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3056 X86::MOV64toPQIrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3057 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3058 if (X86::VR64RegClass.contains(DestReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3059 return X86::MOV64toSDrr;
3060 }
3061
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3062 // SrcReg(FR32) -> DestReg(GR32)
3063 // SrcReg(GR32) -> DestReg(FR32)
3064
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3065 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3066 // Copy from a FR32 register to a GR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3067 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3068
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3069 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3070 // Copy from a GR32 register to a FR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3071 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3072 return 0;
3073}
3074
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3075inline static bool MaskRegClassContains(unsigned Reg) {
3076 return X86::VK8RegClass.contains(Reg) ||
3077 X86::VK16RegClass.contains(Reg) ||
3078 X86::VK1RegClass.contains(Reg);
3079}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3080static
3081unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3082 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3083 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3084 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3085 DestReg = get512BitSuperRegister(DestReg);
3086 SrcReg = get512BitSuperRegister(SrcReg);
3087 return X86::VMOVAPSZrr;
3088 }
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3089 if (MaskRegClassContains(DestReg) &&
3090 MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3091 return X86::KMOVWkk;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3092 if (MaskRegClassContains(DestReg) &&
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3093 (X86::GR32RegClass.contains(SrcReg) ||
3094 X86::GR16RegClass.contains(SrcReg) ||
3095 X86::GR8RegClass.contains(SrcReg))) {
3096 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3097 return X86::KMOVWkr;
3098 }
3099 if ((X86::GR32RegClass.contains(DestReg) ||
3100 X86::GR16RegClass.contains(DestReg) ||
3101 X86::GR8RegClass.contains(DestReg)) &&
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3102 MaskRegClassContains(SrcReg)) {
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3103 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3104 return X86::KMOVWrk;
3105 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3106 return 0;
3107}
3108
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3109void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3110 MachineBasicBlock::iterator MI, DebugLoc DL,
3111 unsigned DestReg, unsigned SrcReg,
3112 bool KillSrc) const {
3113 // First deal with the normal symmetric copies.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3114 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3115 bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
3116 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3117 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3118 Opc = X86::MOV64rr;
3119 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3120 Opc = X86::MOV32rr;
3121 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3122 Opc = X86::MOV16rr;
3123 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3124 // Copying to or from a physical H register on x86-64 requires a NOREX
3125 // move. Otherwise use a normal move.
3126 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]3127 TM.getSubtarget<X86Subtarget>().is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3128 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]3129 // Both operands must be encodable without an REX prefix.
3130 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3131 "8-bit H register can not be copied outside GR8_NOREX");
3132 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3133 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3134 }
3135 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3136 Opc = X86::MMX_MOVQ64rr;
3137 else if (HasAVX512)
3138 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3139 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3140 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3141 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3142 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3143 if (!Opc)
3144 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, TM.getSubtarget<X86Subtarget>());
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3145
3146 if (Opc) {
3147 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3148 .addReg(SrcReg, getKillRegState(KillSrc));
3149 return;
3150 }
3151
3152 // Moving EFLAGS to / from another register requires a push and a pop.
Nadav Rotemd5aae982012-12-21 23:48:49 +0000[diff] [blame]3153 // Notice that we have to adjust the stack if we don't want to clobber the
3154 // first frame index. See X86FrameLowering.cpp - colobbersTheStack.
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3155 if (SrcReg == X86::EFLAGS) {
3156 if (X86::GR64RegClass.contains(DestReg)) {
3157 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3158 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3159 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3160 }
3161 if (X86::GR32RegClass.contains(DestReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3162 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3163 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3164 return;
3165 }
3166 }
3167 if (DestReg == X86::EFLAGS) {
3168 if (X86::GR64RegClass.contains(SrcReg)) {
3169 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3170 .addReg(SrcReg, getKillRegState(KillSrc));
3171 BuildMI(MBB, MI, DL, get(X86::POPF64));
3172 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3173 }
3174 if (X86::GR32RegClass.contains(SrcReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3175 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3176 .addReg(SrcReg, getKillRegState(KillSrc));
3177 BuildMI(MBB, MI, DL, get(X86::POPF32));
3178 return;
3179 }
3180 }
3181
3182 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3183 << " to " << RI.getName(DestReg) << '\n');
3184 llvm_unreachable("Cannot emit physreg copy instruction");
3185}
3186
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3187static unsigned getLoadStoreRegOpcode(unsigned Reg,
3188 const TargetRegisterClass *RC,
3189 bool isStackAligned,
3190 const TargetMachine &TM,
3191 bool load) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3192 if (TM.getSubtarget<X86Subtarget>().hasAVX512()) {
Andrew Trick8460a3b2013-10-14 22:18:56 +0000[diff] [blame]3193 if (X86::VK8RegClass.hasSubClassEq(RC) ||
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3194 X86::VK16RegClass.hasSubClassEq(RC))
3195 return load ? X86::KMOVWkm : X86::KMOVWmk;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3196 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3197 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3198 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3199 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3200 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3201 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3202 }
3203
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3204 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3205 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]3206 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3207 llvm_unreachable("Unknown spill size");
3208 case 1:
3209 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3210 if (TM.getSubtarget<X86Subtarget>().is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3211 // Copying to or from a physical H register on x86-64 requires a NOREX
3212 // move. Otherwise use a normal move.
3213 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3214 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3215 return load ? X86::MOV8rm : X86::MOV8mr;
3216 case 2:
3217 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3218 return load ? X86::MOV16rm : X86::MOV16mr;
3219 case 4:
3220 if (X86::GR32RegClass.hasSubClassEq(RC))
3221 return load ? X86::MOV32rm : X86::MOV32mr;
3222 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3223 return load ?
3224 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3225 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3226 if (X86::RFP32RegClass.hasSubClassEq(RC))
3227 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3228 llvm_unreachable("Unknown 4-byte regclass");
3229 case 8:
3230 if (X86::GR64RegClass.hasSubClassEq(RC))
3231 return load ? X86::MOV64rm : X86::MOV64mr;
3232 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3233 return load ?
3234 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3235 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3236 if (X86::VR64RegClass.hasSubClassEq(RC))
3237 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3238 if (X86::RFP64RegClass.hasSubClassEq(RC))
3239 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3240 llvm_unreachable("Unknown 8-byte regclass");
3241 case 10:
3242 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3243 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3244 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3245 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3246 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3247 // If stack is realigned we can use aligned stores.
3248 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3249 return load ?
3250 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3251 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3252 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3253 return load ?
3254 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3255 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3256 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3257 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3258 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3259 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3260 // If stack is realigned we can use aligned stores.
3261 if (isStackAligned)
3262 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3263 else
3264 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3265 case 64:
3266 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3267 if (isStackAligned)
3268 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3269 else
3270 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3271 }
3272}
3273
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3274static unsigned getStoreRegOpcode(unsigned SrcReg,
3275 const TargetRegisterClass *RC,
3276 bool isStackAligned,
3277 TargetMachine &TM) {
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3278 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
3279}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3280
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3281
3282static unsigned getLoadRegOpcode(unsigned DestReg,
3283 const TargetRegisterClass *RC,
3284 bool isStackAligned,
3285 const TargetMachine &TM) {
3286 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3287}
3288
3289void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3290 MachineBasicBlock::iterator MI,
3291 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3292 const TargetRegisterClass *RC,
3293 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3294 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]3295 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3296 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3297 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3298 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
Evan Chengee9b90a2011-06-23 01:53:43 +0000[diff] [blame]3299 RI.canRealignStack(MF);
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3300 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3301 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3302 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3303 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3304}
3305
3306void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3307 bool isKill,
3308 SmallVectorImpl<MachineOperand> &Addr,
3309 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3310 MachineInstr::mmo_iterator MMOBegin,
3311 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3312 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3313 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3314 bool isAligned = MMOBegin != MMOEnd &&
3315 (*MMOBegin)->getAlignment() >= Alignment;
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3316 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3317 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3318 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3319 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3320 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3321 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3322 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3323 NewMIs.push_back(MIB);
3324}
3325
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3326
3327void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3328 MachineBasicBlock::iterator MI,
3329 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3330 const TargetRegisterClass *RC,
3331 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3332 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3333 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3334 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
Evan Chengee9b90a2011-06-23 01:53:43 +0000[diff] [blame]3335 RI.canRealignStack(MF);
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3336 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3337 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3338 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3339}
3340
3341void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3342 SmallVectorImpl<MachineOperand> &Addr,
3343 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3344 MachineInstr::mmo_iterator MMOBegin,
3345 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3346 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3347 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3348 bool isAligned = MMOBegin != MMOEnd &&
3349 (*MMOBegin)->getAlignment() >= Alignment;
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3350 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3351 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3352 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3353 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3354 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3355 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3356 NewMIs.push_back(MIB);
3357}
3358
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3359bool X86InstrInfo::
3360analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3361 int &CmpMask, int &CmpValue) const {
3362 switch (MI->getOpcode()) {
3363 default: break;
3364 case X86::CMP64ri32:
3365 case X86::CMP64ri8:
3366 case X86::CMP32ri:
3367 case X86::CMP32ri8:
3368 case X86::CMP16ri:
3369 case X86::CMP16ri8:
3370 case X86::CMP8ri:
3371 SrcReg = MI->getOperand(0).getReg();
3372 SrcReg2 = 0;
3373 CmpMask = ~0;
3374 CmpValue = MI->getOperand(1).getImm();
3375 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3376 // A SUB can be used to perform comparison.
3377 case X86::SUB64rm:
3378 case X86::SUB32rm:
3379 case X86::SUB16rm:
3380 case X86::SUB8rm:
3381 SrcReg = MI->getOperand(1).getReg();
3382 SrcReg2 = 0;
3383 CmpMask = ~0;
3384 CmpValue = 0;
3385 return true;
3386 case X86::SUB64rr:
3387 case X86::SUB32rr:
3388 case X86::SUB16rr:
3389 case X86::SUB8rr:
3390 SrcReg = MI->getOperand(1).getReg();
3391 SrcReg2 = MI->getOperand(2).getReg();
3392 CmpMask = ~0;
3393 CmpValue = 0;
3394 return true;
3395 case X86::SUB64ri32:
3396 case X86::SUB64ri8:
3397 case X86::SUB32ri:
3398 case X86::SUB32ri8:
3399 case X86::SUB16ri:
3400 case X86::SUB16ri8:
3401 case X86::SUB8ri:
3402 SrcReg = MI->getOperand(1).getReg();
3403 SrcReg2 = 0;
3404 CmpMask = ~0;
3405 CmpValue = MI->getOperand(2).getImm();
3406 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3407 case X86::CMP64rr:
3408 case X86::CMP32rr:
3409 case X86::CMP16rr:
3410 case X86::CMP8rr:
3411 SrcReg = MI->getOperand(0).getReg();
3412 SrcReg2 = MI->getOperand(1).getReg();
3413 CmpMask = ~0;
3414 CmpValue = 0;
3415 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3416 case X86::TEST8rr:
3417 case X86::TEST16rr:
3418 case X86::TEST32rr:
3419 case X86::TEST64rr:
3420 SrcReg = MI->getOperand(0).getReg();
3421 if (MI->getOperand(1).getReg() != SrcReg) return false;
3422 // Compare against zero.
3423 SrcReg2 = 0;
3424 CmpMask = ~0;
3425 CmpValue = 0;
3426 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3427 }
3428 return false;
3429}
3430
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3431/// isRedundantFlagInstr - check whether the first instruction, whose only
3432/// purpose is to update flags, can be made redundant.
3433/// CMPrr can be made redundant by SUBrr if the operands are the same.
3434/// This function can be extended later on.
3435/// SrcReg, SrcRegs: register operands for FlagI.
3436/// ImmValue: immediate for FlagI if it takes an immediate.
3437inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3438 unsigned SrcReg2, int ImmValue,
3439 MachineInstr *OI) {
3440 if (((FlagI->getOpcode() == X86::CMP64rr &&
3441 OI->getOpcode() == X86::SUB64rr) ||
3442 (FlagI->getOpcode() == X86::CMP32rr &&
3443 OI->getOpcode() == X86::SUB32rr)||
3444 (FlagI->getOpcode() == X86::CMP16rr &&
3445 OI->getOpcode() == X86::SUB16rr)||
3446 (FlagI->getOpcode() == X86::CMP8rr &&
3447 OI->getOpcode() == X86::SUB8rr)) &&
3448 ((OI->getOperand(1).getReg() == SrcReg &&
3449 OI->getOperand(2).getReg() == SrcReg2) ||
3450 (OI->getOperand(1).getReg() == SrcReg2 &&
3451 OI->getOperand(2).getReg() == SrcReg)))
3452 return true;
3453
3454 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3455 OI->getOpcode() == X86::SUB64ri32) ||
3456 (FlagI->getOpcode() == X86::CMP64ri8 &&
3457 OI->getOpcode() == X86::SUB64ri8) ||
3458 (FlagI->getOpcode() == X86::CMP32ri &&
3459 OI->getOpcode() == X86::SUB32ri) ||
3460 (FlagI->getOpcode() == X86::CMP32ri8 &&
3461 OI->getOpcode() == X86::SUB32ri8) ||
3462 (FlagI->getOpcode() == X86::CMP16ri &&
3463 OI->getOpcode() == X86::SUB16ri) ||
3464 (FlagI->getOpcode() == X86::CMP16ri8 &&
3465 OI->getOpcode() == X86::SUB16ri8) ||
3466 (FlagI->getOpcode() == X86::CMP8ri &&
3467 OI->getOpcode() == X86::SUB8ri)) &&
3468 OI->getOperand(1).getReg() == SrcReg &&
3469 OI->getOperand(2).getImm() == ImmValue)
3470 return true;
3471 return false;
3472}
3473
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3474/// isDefConvertible - check whether the definition can be converted
3475/// to remove a comparison against zero.
3476inline static bool isDefConvertible(MachineInstr *MI) {
3477 switch (MI->getOpcode()) {
3478 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3479
3480 // The shift instructions only modify ZF if their shift count is non-zero.
3481 // N.B.: The processor truncates the shift count depending on the encoding.
3482 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3483 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3484 return getTruncatedShiftCount(MI, 2) != 0;
3485
3486 // Some left shift instructions can be turned into LEA instructions but only
3487 // if their flags aren't used. Avoid transforming such instructions.
3488 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3489 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3490 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3491 return ShAmt != 0;
3492 }
3493
3494 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3495 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3496 return getTruncatedShiftCount(MI, 3) != 0;
3497
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3498 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3499 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3500 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3501 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3502 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]3503 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3504 case X86::DEC64_32r: case X86::DEC64_16r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3505 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3506 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3507 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3508 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3509 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]3510 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3511 case X86::INC64_32r: case X86::INC64_16r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3512 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3513 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3514 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3515 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3516 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3517 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3518 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3519 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3520 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3521 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3522 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3523 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3524 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3525 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3526 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]3527 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3528 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3529 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3530 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3531 case X86::ADC32ri: case X86::ADC32ri8:
3532 case X86::ADC32rr: case X86::ADC64ri32:
3533 case X86::ADC64ri8: case X86::ADC64rr:
3534 case X86::SBB32ri: case X86::SBB32ri8:
3535 case X86::SBB32rr: case X86::SBB64ri32:
3536 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]3537 case X86::ANDN32rr: case X86::ANDN32rm:
3538 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]3539 case X86::BEXTR32rr: case X86::BEXTR64rr:
3540 case X86::BEXTR32rm: case X86::BEXTR64rm:
3541 case X86::BLSI32rr: case X86::BLSI32rm:
3542 case X86::BLSI64rr: case X86::BLSI64rm:
3543 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3544 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3545 case X86::BLSR32rr: case X86::BLSR32rm:
3546 case X86::BLSR64rr: case X86::BLSR64rm:
3547 case X86::BZHI32rr: case X86::BZHI32rm:
3548 case X86::BZHI64rr: case X86::BZHI64rm:
3549 case X86::LZCNT16rr: case X86::LZCNT16rm:
3550 case X86::LZCNT32rr: case X86::LZCNT32rm:
3551 case X86::LZCNT64rr: case X86::LZCNT64rm:
3552 case X86::POPCNT16rr:case X86::POPCNT16rm:
3553 case X86::POPCNT32rr:case X86::POPCNT32rm:
3554 case X86::POPCNT64rr:case X86::POPCNT64rm:
3555 case X86::TZCNT16rr: case X86::TZCNT16rm:
3556 case X86::TZCNT32rr: case X86::TZCNT32rm:
3557 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3558 return true;
3559 }
3560}
3561
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3562/// isUseDefConvertible - check whether the use can be converted
3563/// to remove a comparison against zero.
3564static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
3565 switch (MI->getOpcode()) {
3566 default: return X86::COND_INVALID;
3567 case X86::LZCNT16rr: case X86::LZCNT16rm:
3568 case X86::LZCNT32rr: case X86::LZCNT32rm:
3569 case X86::LZCNT64rr: case X86::LZCNT64rm:
3570 return X86::COND_B;
3571 case X86::POPCNT16rr:case X86::POPCNT16rm:
3572 case X86::POPCNT32rr:case X86::POPCNT32rm:
3573 case X86::POPCNT64rr:case X86::POPCNT64rm:
3574 return X86::COND_E;
3575 case X86::TZCNT16rr: case X86::TZCNT16rm:
3576 case X86::TZCNT32rr: case X86::TZCNT32rm:
3577 case X86::TZCNT64rr: case X86::TZCNT64rm:
3578 return X86::COND_B;
3579 }
3580}
3581
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3582/// optimizeCompareInstr - Check if there exists an earlier instruction that
3583/// operates on the same source operands and sets flags in the same way as
3584/// Compare; remove Compare if possible.
3585bool X86InstrInfo::
3586optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3587 int CmpMask, int CmpValue,
3588 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3589 // Check whether we can replace SUB with CMP.
3590 unsigned NewOpcode = 0;
3591 switch (CmpInstr->getOpcode()) {
3592 default: break;
3593 case X86::SUB64ri32:
3594 case X86::SUB64ri8:
3595 case X86::SUB32ri:
3596 case X86::SUB32ri8:
3597 case X86::SUB16ri:
3598 case X86::SUB16ri8:
3599 case X86::SUB8ri:
3600 case X86::SUB64rm:
3601 case X86::SUB32rm:
3602 case X86::SUB16rm:
3603 case X86::SUB8rm:
3604 case X86::SUB64rr:
3605 case X86::SUB32rr:
3606 case X86::SUB16rr:
3607 case X86::SUB8rr: {
3608 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3609 return false;
3610 // There is no use of the destination register, we can replace SUB with CMP.
3611 switch (CmpInstr->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]3612 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3613 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3614 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3615 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3616 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3617 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3618 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3619 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3620 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3621 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3622 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3623 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3624 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3625 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3626 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3627 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3628 }
3629 CmpInstr->setDesc(get(NewOpcode));
3630 CmpInstr->RemoveOperand(0);
3631 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3632 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3633 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3634 return false;
3635 }
3636 }
3637
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3638 // Get the unique definition of SrcReg.
3639 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3640 if (!MI) return false;
3641
3642 // CmpInstr is the first instruction of the BB.
3643 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3644
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3645 // If we are comparing against zero, check whether we can use MI to update
3646 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3647 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3648 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3649 return false;
3650
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3651 // If we have a use of the source register between the def and our compare
3652 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3653 // right way.
3654 bool ShouldUpdateCC = false;
3655 X86::CondCode NewCC = X86::COND_INVALID;
3656 if (IsCmpZero && !isDefConvertible(MI)) {
3657 // Scan forward from the use until we hit the use we're looking for or the
3658 // compare instruction.
3659 for (MachineBasicBlock::iterator J = MI;; ++J) {
3660 // Do we have a convertible instruction?
3661 NewCC = isUseDefConvertible(J);
3662 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3663 J->getOperand(1).getReg() == SrcReg) {
3664 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3665 ShouldUpdateCC = true; // Update CC later on.
3666 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3667 // with the new def.
3668 MI = Def = J;
3669 break;
3670 }
3671
3672 if (J == I)
3673 return false;
3674 }
3675 }
3676
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3677 // We are searching for an earlier instruction that can make CmpInstr
3678 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3679 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3680 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3681
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3682 // We iterate backward, starting from the instruction before CmpInstr and
3683 // stop when reaching the definition of a source register or done with the BB.
3684 // RI points to the instruction before CmpInstr.
3685 // If the definition is in this basic block, RE points to the definition;
3686 // otherwise, RE is the rend of the basic block.
3687 MachineBasicBlock::reverse_iterator
3688 RI = MachineBasicBlock::reverse_iterator(I),
3689 RE = CmpInstr->getParent() == MI->getParent() ?
3690 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3691 CmpInstr->getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3692 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3693 for (; RI != RE; ++RI) {
3694 MachineInstr *Instr = &*RI;
3695 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3696 if (!IsCmpZero &&
3697 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3698 Sub = Instr;
3699 break;
3700 }
3701
3702 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3703 Instr->readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3704 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3705
3706 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3707 // They are safe to move up, if the definition to EFLAGS is dead and
3708 // earlier instructions do not read or write EFLAGS.
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]3709 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3710 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3711 Movr0Inst = Instr;
3712 continue;
3713 }
3714
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3715 // We can't remove CmpInstr.
3716 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3717 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3718 }
3719
3720 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3721 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3722 return false;
3723
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3724 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3725 Sub->getOperand(2).getReg() == SrcReg);
3726
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3727 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3728 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3729 // If we are done with the basic block, we need to check whether EFLAGS is
3730 // live-out.
3731 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3732 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3733 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3734 for (++I; I != E; ++I) {
3735 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]3736 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3737 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3738 // We should check the usage if this instruction uses and updates EFLAGS.
3739 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3740 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3741 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3742 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3743 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]3744 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3745 continue;
3746
3747 // EFLAGS is used by this instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3748 X86::CondCode OldCC;
3749 bool OpcIsSET = false;
3750 if (IsCmpZero || IsSwapped) {
3751 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3752 if (Instr.isBranch())
3753 OldCC = getCondFromBranchOpc(Instr.getOpcode());
3754 else {
3755 OldCC = getCondFromSETOpc(Instr.getOpcode());
3756 if (OldCC != X86::COND_INVALID)
3757 OpcIsSET = true;
3758 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3759 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3760 }
3761 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3762 }
3763 if (IsCmpZero) {
3764 switch (OldCC) {
3765 default: break;
3766 case X86::COND_A: case X86::COND_AE:
3767 case X86::COND_B: case X86::COND_BE:
3768 case X86::COND_G: case X86::COND_GE:
3769 case X86::COND_L: case X86::COND_LE:
3770 case X86::COND_O: case X86::COND_NO:
3771 // CF and OF are used, we can't perform this optimization.
3772 return false;
3773 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3774
3775 // If we're updating the condition code check if we have to reverse the
3776 // condition.
3777 if (ShouldUpdateCC)
3778 switch (OldCC) {
3779 default:
3780 return false;
3781 case X86::COND_E:
3782 break;
3783 case X86::COND_NE:
3784 NewCC = GetOppositeBranchCondition(NewCC);
3785 break;
3786 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3787 } else if (IsSwapped) {
3788 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3789 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3790 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3791 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3792 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3793 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3794
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3795 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3796 // Synthesize the new opcode.
3797 bool HasMemoryOperand = Instr.hasOneMemOperand();
3798 unsigned NewOpc;
3799 if (Instr.isBranch())
3800 NewOpc = GetCondBranchFromCond(NewCC);
3801 else if(OpcIsSET)
3802 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3803 else {
3804 unsigned DstReg = Instr.getOperand(0).getReg();
3805 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3806 HasMemoryOperand);
3807 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3808
3809 // Push the MachineInstr to OpsToUpdate.
3810 // If it is safe to remove CmpInstr, the condition code of these
3811 // instructions will be modified.
3812 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3813 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]3814 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3815 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3816 IsSafe = true;
3817 break;
3818 }
3819 }
3820
3821 // If EFLAGS is not killed nor re-defined, we should check whether it is
3822 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3823 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3824 MachineBasicBlock *MBB = CmpInstr->getParent();
3825 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3826 SE = MBB->succ_end(); SI != SE; ++SI)
3827 if ((*SI)->isLiveIn(X86::EFLAGS))
3828 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3829 }
3830
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3831 // The instruction to be updated is either Sub or MI.
3832 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]3833 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3834 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]3835 // Look backwards until we find a def that doesn't use the current EFLAGS.
3836 Def = Sub;
3837 MachineBasicBlock::reverse_iterator
3838 InsertI = MachineBasicBlock::reverse_iterator(++Def),
3839 InsertE = Sub->getParent()->rend();
3840 for (; InsertI != InsertE; ++InsertI) {
3841 MachineInstr *Instr = &*InsertI;
3842 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3843 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3844 Sub->getParent()->remove(Movr0Inst);
3845 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3846 Movr0Inst);
3847 break;
3848 }
3849 }
3850 if (InsertI == InsertE)
3851 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3852 }
3853
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3854 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]3855 unsigned i = 0, e = Sub->getNumOperands();
3856 for (; i != e; ++i) {
3857 MachineOperand &MO = Sub->getOperand(i);
3858 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3859 MO.setIsDead(false);
3860 break;
3861 }
3862 }
3863 assert(i != e && "Unable to locate a def EFLAGS operand");
3864
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3865 CmpInstr->eraseFromParent();
3866
3867 // Modify the condition code of instructions in OpsToUpdate.
3868 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3869 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3870 return true;
3871}
3872
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3873/// optimizeLoadInstr - Try to remove the load by folding it to a register
3874/// operand at the use. We fold the load instructions if load defines a virtual
3875/// register, the virtual register is used once in the same BB, and the
3876/// instructions in-between do not load or store, and have no side effects.
3877MachineInstr* X86InstrInfo::
3878optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3879 unsigned &FoldAsLoadDefReg,
3880 MachineInstr *&DefMI) const {
3881 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3882 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3883 // To be conservative, if there exists another load, clear the load candidate.
3884 if (MI->mayLoad()) {
3885 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3886 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3887 }
3888
3889 // Check whether we can move DefMI here.
3890 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3891 assert(DefMI);
3892 bool SawStore = false;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3893 if (!DefMI->isSafeToMove(this, nullptr, SawStore))
3894 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3895
3896 // We try to commute MI if possible.
3897 unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
3898 for (unsigned Idx = 0; Idx < IdxEnd; Idx++) {
3899 // Collect information about virtual register operands of MI.
3900 unsigned SrcOperandId = 0;
3901 bool FoundSrcOperand = false;
3902 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3903 MachineOperand &MO = MI->getOperand(i);
3904 if (!MO.isReg())
3905 continue;
3906 unsigned Reg = MO.getReg();
3907 if (Reg != FoldAsLoadDefReg)
3908 continue;
3909 // Do not fold if we have a subreg use or a def or multiple uses.
3910 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3911 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3912
3913 SrcOperandId = i;
3914 FoundSrcOperand = true;
3915 }
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3916 if (!FoundSrcOperand) return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3917
3918 // Check whether we can fold the def into SrcOperandId.
3919 SmallVector<unsigned, 8> Ops;
3920 Ops.push_back(SrcOperandId);
3921 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3922 if (FoldMI) {
3923 FoldAsLoadDefReg = 0;
3924 return FoldMI;
3925 }
3926
3927 if (Idx == 1) {
3928 // MI was changed but it didn't help, commute it back!
3929 commuteInstruction(MI, false);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3930 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3931 }
3932
3933 // Check whether we can commute MI and enable folding.
3934 if (MI->isCommutable()) {
3935 MachineInstr *NewMI = commuteInstruction(MI, false);
3936 // Unable to commute.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3937 if (!NewMI) return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3938 if (NewMI != MI) {
3939 // New instruction. It doesn't need to be kept.
3940 NewMI->eraseFromParent();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3941 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3942 }
3943 }
3944 }
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3945 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3946}
3947
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3948/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3949/// instruction with two undef reads of the register being defined. This is
3950/// used for mapping:
3951/// %xmm4 = V_SET0
3952/// to:
3953/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3954///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3955static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3956 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3957 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3958 unsigned Reg = MIB->getOperand(0).getReg();
3959 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3960
3961 // MachineInstr::addOperand() will insert explicit operands before any
3962 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3963 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3964 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3965 assert(MIB->getOperand(1).getReg() == Reg &&
3966 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3967 return true;
3968}
3969
3970bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
3971 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3972 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3973 switch (MI->getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]3974 case X86::MOV32r0:
3975 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]3976 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3977 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]3978 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3979 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]3980 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3981 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]3982 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3983 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3984 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]3985 case X86::FsFLD0SS:
3986 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3987 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]3988 case X86::AVX_SET0:
3989 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3990 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]3991 case X86::AVX512_512_SET0:
3992 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]3993 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3994 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]3995 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]3996 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]3997 case X86::TEST8ri_NOREX:
3998 MI->setDesc(get(X86::TEST8ri));
3999 return true;
Elena Demikhovsky8fae5652014-03-06 08:15:35 +0000[diff] [blame]4000 case X86::KSET0B:
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4001 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4002 case X86::KSET1B:
4003 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4004 }
4005 return false;
4006}
4007
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4008static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4009 const SmallVectorImpl<MachineOperand> &MOs,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4010 MachineInstr *MI,
4011 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4012 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4013 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4014 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4015 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4016 MachineInstrBuilder MIB(MF, NewMI);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4017 unsigned NumAddrOps = MOs.size();
4018 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4019 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4020 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4021 addOffset(MIB, 0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4022
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4023 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4024 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4025 for (unsigned i = 0; i != NumOps; ++i) {
4026 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4027 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4028 }
4029 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4030 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4031 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4032 }
4033 return MIB;
4034}
4035
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4036static MachineInstr *FuseInst(MachineFunction &MF,
4037 unsigned Opcode, unsigned OpNo,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4038 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4039 MachineInstr *MI, const TargetInstrInfo &TII) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4040 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4041 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4042 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4043 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4044
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4045 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4046 MachineOperand &MO = MI->getOperand(i);
4047 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4048 assert(MO.isReg() && "Expected to fold into reg operand!");
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4049 unsigned NumAddrOps = MOs.size();
4050 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4051 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4052 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4053 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4054 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4055 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4056 }
4057 }
4058 return MIB;
4059}
4060
4061static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4062 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4063 MachineInstr *MI) {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4064 MachineFunction &MF = *MI->getParent()->getParent();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4065 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4066
4067 unsigned NumAddrOps = MOs.size();
4068 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4069 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4070 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4071 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4072 return MIB.addImm(0);
4073}
4074
4075MachineInstr*
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4076X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4077 MachineInstr *MI, unsigned i,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4078 const SmallVectorImpl<MachineOperand> &MOs,
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4079 unsigned Size, unsigned Align) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4080 const DenseMap<unsigned,
4081 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4082 bool isCallRegIndirect = TM.getSubtarget<X86Subtarget>().callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4083 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4084
4085 // Atom favors register form of call. So, we do not fold loads into calls
4086 // when X86Subtarget is Atom.
4087 if (isCallRegIndirect &&
4088 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4089 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4090 }
4091
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4092 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4093 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4094 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4095
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4096 // FIXME: AsmPrinter doesn't know how to handle
4097 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4098 if (MI->getOpcode() == X86::ADD32ri &&
4099 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4100 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4101
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4102 MachineInstr *NewMI = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4103 // Folding a memory location into the two-address part of a two-address
4104 // instruction is different than folding it other places. It requires
4105 // replacing the *two* registers with the memory location.
4106 if (isTwoAddr && NumOps >= 2 && i < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4107 MI->getOperand(0).isReg() &&
4108 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4109 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4110 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4111 isTwoAddrFold = true;
4112 } else if (i == 0) { // If operand 0
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4113 if (MI->getOpcode() == X86::MOV32r0) {
4114 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4115 if (NewMI)
4116 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]4117 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4118
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4119 OpcodeTablePtr = &RegOp2MemOpTable0;
4120 } else if (i == 1) {
4121 OpcodeTablePtr = &RegOp2MemOpTable1;
4122 } else if (i == 2) {
4123 OpcodeTablePtr = &RegOp2MemOpTable2;
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]4124 } else if (i == 3) {
4125 OpcodeTablePtr = &RegOp2MemOpTable3;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4126 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4127
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4128 // If table selected...
4129 if (OpcodeTablePtr) {
4130 // Find the Opcode to fuse
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4131 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4132 OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4133 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4134 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4135 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4136 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4137 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4138 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4139 if (Size) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4140 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4141 if (Size < RCSize) {
4142 // Check if it's safe to fold the load. If the size of the object is
4143 // narrower than the load width, then it's not.
4144 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4145 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4146 // If this is a 64-bit load, but the spill slot is 32, then we can do
4147 // a 32-bit load which is implicitly zero-extended. This likely is due
4148 // to liveintervalanalysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4149 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4150 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4151 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4152 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4153 }
4154 }
4155
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4156 if (isTwoAddrFold)
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4157 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4158 else
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4159 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4160
4161 if (NarrowToMOV32rm) {
4162 // If this is the special case where we use a MOV32rm to load a 32-bit
4163 // value and zero-extend the top bits. Change the destination register
4164 // to a 32-bit one.
4165 unsigned DstReg = NewMI->getOperand(0).getReg();
4166 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4167 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]4168 X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4169 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]4170 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4171 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4172 return NewMI;
4173 }
4174 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4175
4176 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]4177 if (PrintFailedFusing && !MI->isCopy())
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]4178 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4179 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4180}
4181
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4182/// hasPartialRegUpdate - Return true for all instructions that only update
4183/// the first 32 or 64-bits of the destination register and leave the rest
4184/// unmodified. This can be used to avoid folding loads if the instructions
4185/// only update part of the destination register, and the non-updated part is
4186/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4187/// instructions breaks the partial register dependency and it can improve
4188/// performance. e.g.:
4189///
4190/// movss (%rdi), %xmm0
4191/// cvtss2sd %xmm0, %xmm0
4192///
4193/// Instead of
4194/// cvtss2sd (%rdi), %xmm0
4195///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]4196/// FIXME: This should be turned into a TSFlags.
4197///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4198static bool hasPartialRegUpdate(unsigned Opcode) {
4199 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4200 case X86::CVTSI2SSrr:
4201 case X86::CVTSI2SS64rr:
4202 case X86::CVTSI2SDrr:
4203 case X86::CVTSI2SD64rr:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4204 case X86::CVTSD2SSrr:
4205 case X86::Int_CVTSD2SSrr:
4206 case X86::CVTSS2SDrr:
4207 case X86::Int_CVTSS2SDrr:
4208 case X86::RCPSSr:
4209 case X86::RCPSSr_Int:
4210 case X86::ROUNDSDr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4211 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4212 case X86::ROUNDSSr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4213 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4214 case X86::RSQRTSSr:
4215 case X86::RSQRTSSr_Int:
4216 case X86::SQRTSSr:
4217 case X86::SQRTSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4218 return true;
4219 }
4220
4221 return false;
4222}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4223
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4224/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4225/// instructions we would like before a partial register update.
4226unsigned X86InstrInfo::
4227getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4228 const TargetRegisterInfo *TRI) const {
4229 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4230 return 0;
4231
4232 // If MI is marked as reading Reg, the partial register update is wanted.
4233 const MachineOperand &MO = MI->getOperand(0);
4234 unsigned Reg = MO.getReg();
4235 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4236 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4237 return 0;
4238 } else {
4239 if (MI->readsRegister(Reg, TRI))
4240 return 0;
4241 }
4242
4243 // If any of the preceding 16 instructions are reading Reg, insert a
4244 // dependency breaking instruction. The magic number is based on a few
4245 // Nehalem experiments.
4246 return 16;
4247}
4248
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4249// Return true for any instruction the copies the high bits of the first source
4250// operand into the unused high bits of the destination operand.
4251static bool hasUndefRegUpdate(unsigned Opcode) {
4252 switch (Opcode) {
4253 case X86::VCVTSI2SSrr:
4254 case X86::Int_VCVTSI2SSrr:
4255 case X86::VCVTSI2SS64rr:
4256 case X86::Int_VCVTSI2SS64rr:
4257 case X86::VCVTSI2SDrr:
4258 case X86::Int_VCVTSI2SDrr:
4259 case X86::VCVTSI2SD64rr:
4260 case X86::Int_VCVTSI2SD64rr:
4261 case X86::VCVTSD2SSrr:
4262 case X86::Int_VCVTSD2SSrr:
4263 case X86::VCVTSS2SDrr:
4264 case X86::Int_VCVTSS2SDrr:
4265 case X86::VRCPSSr:
4266 case X86::VROUNDSDr:
4267 case X86::VROUNDSDr_Int:
4268 case X86::VROUNDSSr:
4269 case X86::VROUNDSSr_Int:
4270 case X86::VRSQRTSSr:
4271 case X86::VSQRTSSr:
4272
4273 // AVX-512
4274 case X86::VCVTSD2SSZrr:
4275 case X86::VCVTSS2SDZrr:
4276 return true;
4277 }
4278
4279 return false;
4280}
4281
4282/// Inform the ExeDepsFix pass how many idle instructions we would like before
4283/// certain undef register reads.
4284///
4285/// This catches the VCVTSI2SD family of instructions:
4286///
4287/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4288///
4289/// We should to be careful *not* to catch VXOR idioms which are presumably
4290/// handled specially in the pipeline:
4291///
4292/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4293///
4294/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4295/// high bits that are passed-through are not live.
4296unsigned X86InstrInfo::
4297getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4298 const TargetRegisterInfo *TRI) const {
4299 if (!hasUndefRegUpdate(MI->getOpcode()))
4300 return 0;
4301
4302 // Set the OpNum parameter to the first source operand.
4303 OpNum = 1;
4304
4305 const MachineOperand &MO = MI->getOperand(OpNum);
4306 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4307 // Use the same magic number as getPartialRegUpdateClearance.
4308 return 16;
4309 }
4310 return 0;
4311}
4312
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4313void X86InstrInfo::
4314breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4315 const TargetRegisterInfo *TRI) const {
4316 unsigned Reg = MI->getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4317 // If MI kills this register, the false dependence is already broken.
4318 if (MI->killsRegister(Reg, TRI))
4319 return;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4320 if (X86::VR128RegClass.contains(Reg)) {
4321 // These instructions are all floating point domain, so xorps is the best
4322 // choice.
4323 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
4324 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4325 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4326 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4327 } else if (X86::VR256RegClass.contains(Reg)) {
4328 // Use vxorps to clear the full ymm register.
4329 // It wants to read and write the xmm sub-register.
4330 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4331 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4332 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4333 .addReg(Reg, RegState::ImplicitDefine);
4334 } else
4335 return;
4336 MI->addRegisterKilled(Reg, TRI, true);
4337}
4338
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]4339MachineInstr*
4340X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4341 const SmallVectorImpl<unsigned> &Ops,
4342 int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4343 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4344 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4345
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4346 // Unless optimizing for size, don't fold to avoid partial
4347 // register update stalls
Bill Wendling698e84f2012-12-30 10:32:01 +0000[diff] [blame]4348 if (!MF.getFunction()->getAttributes().
4349 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4350 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4351 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]4352
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4353 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4354 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4355 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]4356 // If the function stack isn't realigned we don't want to fold instructions
4357 // that need increased alignment.
4358 if (!RI.needsStackRealignment(MF))
4359 Alignment = std::min(Alignment, TM.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4360 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4361 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4362 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4363 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4364 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4365 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]4366 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4367 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4368 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4369 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4370 // Check if it's safe to fold the load. If the size of the object is
4371 // narrower than the load width, then it's not.
4372 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4373 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4374 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]4375 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4376 MI->getOperand(1).ChangeToImmediate(0);
4377 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4378 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4379
4380 SmallVector<MachineOperand,4> MOs;
4381 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4382 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4383}
4384
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4385MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4386 MachineInstr *MI,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4387 const SmallVectorImpl<unsigned> &Ops,
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4388 MachineInstr *LoadMI) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]4389 // If loading from a FrameIndex, fold directly from the FrameIndex.
4390 unsigned NumOps = LoadMI->getDesc().getNumOperands();
4391 int FrameIndex;
4392 if (isLoadFromStackSlot(LoadMI, FrameIndex))
4393 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4394
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4395 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4396 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4397
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4398 // Unless optimizing for size, don't fold to avoid partial
4399 // register update stalls
Bill Wendling698e84f2012-12-30 10:32:01 +0000[diff] [blame]4400 if (!MF.getFunction()->getAttributes().
4401 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4402 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4403 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]4404
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]4405 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4406 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]4407 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]4408 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4409 else
4410 switch (LoadMI->getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]4411 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4412 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]4413 Alignment = 32;
4414 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4415 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4416 case X86::V_SETALLONES:
4417 Alignment = 16;
4418 break;
4419 case X86::FsFLD0SD:
4420 Alignment = 8;
4421 break;
4422 case X86::FsFLD0SS:
4423 Alignment = 4;
4424 break;
4425 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4426 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4427 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4428 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4429 unsigned NewOpc = 0;
4430 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4431 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4432 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4433 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4434 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4435 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4436 }
4437 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]4438 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4439 MI->getOperand(1).ChangeToImmediate(0);
4440 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4441 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4442
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]4443 // Make sure the subregisters match.
4444 // Otherwise we risk changing the size of the load.
4445 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4446 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]4447
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4448 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4449 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4450 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4451 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]4452 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4453 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4454 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4455 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4456 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4457 // Create a constant-pool entry and operands to load from it.
4458
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]4459 // Medium and large mode can't fold loads this way.
4460 if (TM.getCodeModel() != CodeModel::Small &&
4461 TM.getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4462 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]4463
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4464 // x86-32 PIC requires a PIC base register for constant pools.
4465 unsigned PICBase = 0;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]4466 if (TM.getRelocationModel() == Reloc::PIC_) {
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]4467 if (TM.getSubtarget<X86Subtarget>().is64Bit())
4468 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]4469 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4470 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]4471 // This doesn't work for several reasons.
4472 // 1. GlobalBaseReg may have been spilled.
4473 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4474 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]4475 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4476
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4477 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4478 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]4479 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]4480 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4481 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4482 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4483 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4484 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4485 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]4486 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4487 else
4488 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]4489
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4490 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]4491 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4492 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4493 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4494
4495 // Create operands to load from the constant pool entry.
4496 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4497 MOs.push_back(MachineOperand::CreateImm(1));
4498 MOs.push_back(MachineOperand::CreateReg(0, false));
4499 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4500 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4501 break;
4502 }
4503 default: {
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]4504 if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4505 LoadMI->getOpcode() == X86::VMOVSSrm) &&
4506 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4507 > 4)
4508 // These instructions only load 32 bits, we can't fold them if the
4509 // destination register is wider than 32 bits (4 bytes).
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4510 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]4511 if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4512 LoadMI->getOpcode() == X86::VMOVSDrm) &&
4513 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4514 > 8)
4515 // These instructions only load 64 bits, we can't fold them if the
4516 // destination register is wider than 64 bits (8 bytes).
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4517 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]4518
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4519 // Folding a normal load. Just copy the load's address operands.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4520 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4521 MOs.push_back(LoadMI->getOperand(i));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4522 break;
4523 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4524 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4525 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4526}
4527
4528
Dan Gohman33332bc2008-10-16 01:49:15 +0000[diff] [blame]4529bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4530 const SmallVectorImpl<unsigned> &Ops) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4531 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4532 if (NoFusing) return 0;
4533
4534 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4535 switch (MI->getOpcode()) {
4536 default: return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4537 case X86::TEST8rr:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4538 case X86::TEST16rr:
4539 case X86::TEST32rr:
4540 case X86::TEST64rr:
4541 return true;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4542 case X86::ADD32ri:
4543 // FIXME: AsmPrinter doesn't know how to handle
4544 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4545 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4546 return false;
4547 break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4548 }
4549 }
4550
4551 if (Ops.size() != 1)
4552 return false;
4553
4554 unsigned OpNum = Ops[0];
4555 unsigned Opc = MI->getOpcode();
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4556 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4557 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4558 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4559
4560 // Folding a memory location into the two-address part of a two-address
4561 // instruction is different than folding it other places. It requires
4562 // replacing the *two* registers with the memory location.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4563 const DenseMap<unsigned,
4564 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4565 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4566 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4567 } else if (OpNum == 0) { // If operand 0
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4568 if (Opc == X86::MOV32r0)
4569 return true;
4570
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4571 OpcodeTablePtr = &RegOp2MemOpTable0;
4572 } else if (OpNum == 1) {
4573 OpcodeTablePtr = &RegOp2MemOpTable1;
4574 } else if (OpNum == 2) {
4575 OpcodeTablePtr = &RegOp2MemOpTable2;
Craig Topper7573c8f2012-08-31 22:12:16 +0000[diff] [blame]4576 } else if (OpNum == 3) {
4577 OpcodeTablePtr = &RegOp2MemOpTable3;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4578 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4579
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]4580 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4581 return true;
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]4582 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4583}
4584
4585bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4586 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4587 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4588 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4589 MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4590 if (I == MemOp2RegOpTable.end())
4591 return false;
4592 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4593 unsigned Index = I->second.second & TB_INDEX_MASK;
4594 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4595 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4596 if (UnfoldLoad && !FoldedLoad)
4597 return false;
4598 UnfoldLoad &= FoldedLoad;
4599 if (UnfoldStore && !FoldedStore)
4600 return false;
4601 UnfoldStore &= FoldedStore;
4602
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4603 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4604 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4605 if (!MI->hasOneMemOperand() &&
4606 RC == &X86::VR128RegClass &&
4607 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4608 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4609 // conservatively assume the address is unaligned. That's bad for
4610 // performance.
4611 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4612 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4613 SmallVector<MachineOperand,2> BeforeOps;
4614 SmallVector<MachineOperand,2> AfterOps;
4615 SmallVector<MachineOperand,4> ImpOps;
4616 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4617 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4618 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4619 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4620 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4621 ImpOps.push_back(Op);
4622 else if (i < Index)
4623 BeforeOps.push_back(Op);
4624 else if (i > Index)
4625 AfterOps.push_back(Op);
4626 }
4627
4628 // Emit the load instruction.
4629 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4630 std::pair<MachineInstr::mmo_iterator,
4631 MachineInstr::mmo_iterator> MMOs =
4632 MF.extractLoadMemRefs(MI->memoperands_begin(),
4633 MI->memoperands_end());
4634 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4635 if (UnfoldStore) {
4636 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4637 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4638 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4639 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4640 MO.setIsKill(false);
4641 }
4642 }
4643 }
4644
4645 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4646 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4647 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4648
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4649 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4650 MIB.addReg(Reg, RegState::Define);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4651 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4652 MIB.addOperand(BeforeOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4653 if (FoldedLoad)
4654 MIB.addReg(Reg);
4655 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4656 MIB.addOperand(AfterOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4657 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4658 MachineOperand &MO = ImpOps[i];
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4659 MIB.addReg(MO.getReg(),
4660 getDefRegState(MO.isDef()) |
4661 RegState::Implicit |
4662 getKillRegState(MO.isKill()) |
Evan Cheng0dc101b2009-06-30 08:49:04 +0000[diff] [blame]4663 getDeadRegState(MO.isDead()) |
4664 getUndefRegState(MO.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4665 }
4666 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4667 switch (DataMI->getOpcode()) {
4668 default: break;
4669 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4670 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4671 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4672 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4673 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4674 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4675 case X86::CMP8ri: {
4676 MachineOperand &MO0 = DataMI->getOperand(0);
4677 MachineOperand &MO1 = DataMI->getOperand(1);
4678 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4679 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4680 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4681 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4682 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4683 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4684 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4685 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4686 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4687 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
4688 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
4689 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]4690 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4691 MO1.ChangeToRegister(MO0.getReg(), false);
4692 }
4693 }
4694 }
4695 NewMIs.push_back(DataMI);
4696
4697 // Emit the store instruction.
4698 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4699 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4700 std::pair<MachineInstr::mmo_iterator,
4701 MachineInstr::mmo_iterator> MMOs =
4702 MF.extractStoreMemRefs(MI->memoperands_begin(),
4703 MI->memoperands_end());
4704 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4705 }
4706
4707 return true;
4708}
4709
4710bool
4711X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4712 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]4713 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4714 return false;
4715
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4716 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4717 MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4718 if (I == MemOp2RegOpTable.end())
4719 return false;
4720 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4721 unsigned Index = I->second.second & TB_INDEX_MASK;
4722 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4723 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4724 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4725 MachineFunction &MF = DAG.getMachineFunction();
4726 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4727 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4728 std::vector<SDValue> AddrOps;
4729 std::vector<SDValue> BeforeOps;
4730 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]4731 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4732 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]4733 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4734 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4735 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4736 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]4737 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4738 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]4739 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4740 AfterOps.push_back(Op);
4741 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4742 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4743 AddrOps.push_back(Chain);
4744
4745 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4746 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4747 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]4748 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]4749 std::pair<MachineInstr::mmo_iterator,
4750 MachineInstr::mmo_iterator> MMOs =
4751 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4752 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4753 if (!(*MMOs.first) &&
4754 RC == &X86::VR128RegClass &&
4755 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4756 // Do not introduce a slow unaligned load.
4757 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4758 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4759 bool isAligned = (*MMOs.first) &&
4760 (*MMOs.first)->getAlignment() >= Alignment;
Dan Gohman32f71d72009-09-25 18:54:59 +0000[diff] [blame]4761 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]4762 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4763 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4764
4765 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4766 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4767 }
4768
4769 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]4770 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4771 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4772 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4773 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4774 VTs.push_back(*DstRC->vt_begin());
4775 }
4776 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]4777 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4778 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4779 VTs.push_back(VT);
4780 }
4781 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4782 BeforeOps.push_back(SDValue(Load, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4783 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]4784 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4785 NewNodes.push_back(NewNode);
4786
4787 // Emit the store instruction.
4788 if (FoldedStore) {
4789 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4790 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4791 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]4792 std::pair<MachineInstr::mmo_iterator,
4793 MachineInstr::mmo_iterator> MMOs =
4794 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4795 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4796 if (!(*MMOs.first) &&
4797 RC == &X86::VR128RegClass &&
4798 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4799 // Do not introduce a slow unaligned store.
4800 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4801 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4802 bool isAligned = (*MMOs.first) &&
4803 (*MMOs.first)->getAlignment() >= Alignment;
Dan Gohman32f71d72009-09-25 18:54:59 +0000[diff] [blame]4804 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
4805 isAligned, TM),
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]4806 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4807 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4808
4809 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4810 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4811 }
4812
4813 return true;
4814}
4815
4816unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]4817 bool UnfoldLoad, bool UnfoldStore,
4818 unsigned *LoadRegIndex) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4819 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4820 MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4821 if (I == MemOp2RegOpTable.end())
4822 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4823 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4824 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4825 if (UnfoldLoad && !FoldedLoad)
4826 return 0;
4827 if (UnfoldStore && !FoldedStore)
4828 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]4829 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4830 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4831 return I->second.first;
4832}
4833
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4834bool
4835X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4836 int64_t &Offset1, int64_t &Offset2) const {
4837 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4838 return false;
4839 unsigned Opc1 = Load1->getMachineOpcode();
4840 unsigned Opc2 = Load2->getMachineOpcode();
4841 switch (Opc1) {
4842 default: return false;
4843 case X86::MOV8rm:
4844 case X86::MOV16rm:
4845 case X86::MOV32rm:
4846 case X86::MOV64rm:
4847 case X86::LD_Fp32m:
4848 case X86::LD_Fp64m:
4849 case X86::LD_Fp80m:
4850 case X86::MOVSSrm:
4851 case X86::MOVSDrm:
4852 case X86::MMX_MOVD64rm:
4853 case X86::MMX_MOVQ64rm:
4854 case X86::FsMOVAPSrm:
4855 case X86::FsMOVAPDrm:
4856 case X86::MOVAPSrm:
4857 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4858 case X86::MOVAPDrm:
4859 case X86::MOVDQArm:
4860 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]4861 // AVX load instructions
4862 case X86::VMOVSSrm:
4863 case X86::VMOVSDrm:
4864 case X86::FsVMOVAPSrm:
4865 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4866 case X86::VMOVAPSrm:
4867 case X86::VMOVUPSrm:
4868 case X86::VMOVAPDrm:
4869 case X86::VMOVDQArm:
4870 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4871 case X86::VMOVAPSYrm:
4872 case X86::VMOVUPSYrm:
4873 case X86::VMOVAPDYrm:
4874 case X86::VMOVDQAYrm:
4875 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4876 break;
4877 }
4878 switch (Opc2) {
4879 default: return false;
4880 case X86::MOV8rm:
4881 case X86::MOV16rm:
4882 case X86::MOV32rm:
4883 case X86::MOV64rm:
4884 case X86::LD_Fp32m:
4885 case X86::LD_Fp64m:
4886 case X86::LD_Fp80m:
4887 case X86::MOVSSrm:
4888 case X86::MOVSDrm:
4889 case X86::MMX_MOVD64rm:
4890 case X86::MMX_MOVQ64rm:
4891 case X86::FsMOVAPSrm:
4892 case X86::FsMOVAPDrm:
4893 case X86::MOVAPSrm:
4894 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4895 case X86::MOVAPDrm:
4896 case X86::MOVDQArm:
4897 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]4898 // AVX load instructions
4899 case X86::VMOVSSrm:
4900 case X86::VMOVSDrm:
4901 case X86::FsVMOVAPSrm:
4902 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4903 case X86::VMOVAPSrm:
4904 case X86::VMOVUPSrm:
4905 case X86::VMOVAPDrm:
4906 case X86::VMOVDQArm:
4907 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4908 case X86::VMOVAPSYrm:
4909 case X86::VMOVUPSYrm:
4910 case X86::VMOVAPDYrm:
4911 case X86::VMOVDQAYrm:
4912 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4913 break;
4914 }
4915
4916 // Check if chain operands and base addresses match.
4917 if (Load1->getOperand(0) != Load2->getOperand(0) ||
4918 Load1->getOperand(5) != Load2->getOperand(5))
4919 return false;
4920 // Segment operands should match as well.
4921 if (Load1->getOperand(4) != Load2->getOperand(4))
4922 return false;
4923 // Scale should be 1, Index should be Reg0.
4924 if (Load1->getOperand(1) == Load2->getOperand(1) &&
4925 Load1->getOperand(2) == Load2->getOperand(2)) {
4926 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
4927 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4928
4929 // Now let's examine the displacements.
4930 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
4931 isa<ConstantSDNode>(Load2->getOperand(3))) {
4932 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
4933 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
4934 return true;
4935 }
4936 }
4937 return false;
4938}
4939
4940bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
4941 int64_t Offset1, int64_t Offset2,
4942 unsigned NumLoads) const {
4943 assert(Offset2 > Offset1);
4944 if ((Offset2 - Offset1) / 8 > 64)
4945 return false;
4946
4947 unsigned Opc1 = Load1->getMachineOpcode();
4948 unsigned Opc2 = Load2->getMachineOpcode();
4949 if (Opc1 != Opc2)
4950 return false; // FIXME: overly conservative?
4951
4952 switch (Opc1) {
4953 default: break;
4954 case X86::LD_Fp32m:
4955 case X86::LD_Fp64m:
4956 case X86::LD_Fp80m:
4957 case X86::MMX_MOVD64rm:
4958 case X86::MMX_MOVQ64rm:
4959 return false;
4960 }
4961
4962 EVT VT = Load1->getValueType(0);
4963 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]4964 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4965 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
4966 // have 16 of them to play with.
4967 if (TM.getSubtargetImpl()->is64Bit()) {
4968 if (NumLoads >= 3)
4969 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]4970 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4971 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]4972 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4973 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4974 case MVT::i8:
4975 case MVT::i16:
4976 case MVT::i32:
4977 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]4978 case MVT::f32:
4979 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4980 if (NumLoads)
4981 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]4982 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4983 }
4984
4985 return true;
4986}
4987
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]4988bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
4989 MachineInstr *Second) const {
4990 // Check if this processor supports macro-fusion. Since this is a minor
4991 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
4992 // proxy for SandyBridge+.
4993 if (!TM.getSubtarget<X86Subtarget>().hasAVX())
4994 return false;
4995
4996 enum {
4997 FuseTest,
4998 FuseCmp,
4999 FuseInc
5000 } FuseKind;
5001
5002 switch(Second->getOpcode()) {
5003 default:
5004 return false;
5005 case X86::JE_4:
5006 case X86::JNE_4:
5007 case X86::JL_4:
5008 case X86::JLE_4:
5009 case X86::JG_4:
5010 case X86::JGE_4:
5011 FuseKind = FuseInc;
5012 break;
5013 case X86::JB_4:
5014 case X86::JBE_4:
5015 case X86::JA_4:
5016 case X86::JAE_4:
5017 FuseKind = FuseCmp;
5018 break;
5019 case X86::JS_4:
5020 case X86::JNS_4:
5021 case X86::JP_4:
5022 case X86::JNP_4:
5023 case X86::JO_4:
5024 case X86::JNO_4:
5025 FuseKind = FuseTest;
5026 break;
5027 }
5028 switch (First->getOpcode()) {
5029 default:
5030 return false;
5031 case X86::TEST8rr:
5032 case X86::TEST16rr:
5033 case X86::TEST32rr:
5034 case X86::TEST64rr:
5035 case X86::TEST8ri:
5036 case X86::TEST16ri:
5037 case X86::TEST32ri:
5038 case X86::TEST32i32:
5039 case X86::TEST64i32:
5040 case X86::TEST64ri32:
5041 case X86::TEST8rm:
5042 case X86::TEST16rm:
5043 case X86::TEST32rm:
5044 case X86::TEST64rm:
5045 case X86::AND16i16:
5046 case X86::AND16ri:
5047 case X86::AND16ri8:
5048 case X86::AND16rm:
5049 case X86::AND16rr:
5050 case X86::AND32i32:
5051 case X86::AND32ri:
5052 case X86::AND32ri8:
5053 case X86::AND32rm:
5054 case X86::AND32rr:
5055 case X86::AND64i32:
5056 case X86::AND64ri32:
5057 case X86::AND64ri8:
5058 case X86::AND64rm:
5059 case X86::AND64rr:
5060 case X86::AND8i8:
5061 case X86::AND8ri:
5062 case X86::AND8rm:
5063 case X86::AND8rr:
5064 return true;
5065 case X86::CMP16i16:
5066 case X86::CMP16ri:
5067 case X86::CMP16ri8:
5068 case X86::CMP16rm:
5069 case X86::CMP16rr:
5070 case X86::CMP32i32:
5071 case X86::CMP32ri:
5072 case X86::CMP32ri8:
5073 case X86::CMP32rm:
5074 case X86::CMP32rr:
5075 case X86::CMP64i32:
5076 case X86::CMP64ri32:
5077 case X86::CMP64ri8:
5078 case X86::CMP64rm:
5079 case X86::CMP64rr:
5080 case X86::CMP8i8:
5081 case X86::CMP8ri:
5082 case X86::CMP8rm:
5083 case X86::CMP8rr:
5084 case X86::ADD16i16:
5085 case X86::ADD16ri:
5086 case X86::ADD16ri8:
5087 case X86::ADD16ri8_DB:
5088 case X86::ADD16ri_DB:
5089 case X86::ADD16rm:
5090 case X86::ADD16rr:
5091 case X86::ADD16rr_DB:
5092 case X86::ADD32i32:
5093 case X86::ADD32ri:
5094 case X86::ADD32ri8:
5095 case X86::ADD32ri8_DB:
5096 case X86::ADD32ri_DB:
5097 case X86::ADD32rm:
5098 case X86::ADD32rr:
5099 case X86::ADD32rr_DB:
5100 case X86::ADD64i32:
5101 case X86::ADD64ri32:
5102 case X86::ADD64ri32_DB:
5103 case X86::ADD64ri8:
5104 case X86::ADD64ri8_DB:
5105 case X86::ADD64rm:
5106 case X86::ADD64rr:
5107 case X86::ADD64rr_DB:
5108 case X86::ADD8i8:
5109 case X86::ADD8mi:
5110 case X86::ADD8mr:
5111 case X86::ADD8ri:
5112 case X86::ADD8rm:
5113 case X86::ADD8rr:
5114 case X86::SUB16i16:
5115 case X86::SUB16ri:
5116 case X86::SUB16ri8:
5117 case X86::SUB16rm:
5118 case X86::SUB16rr:
5119 case X86::SUB32i32:
5120 case X86::SUB32ri:
5121 case X86::SUB32ri8:
5122 case X86::SUB32rm:
5123 case X86::SUB32rr:
5124 case X86::SUB64i32:
5125 case X86::SUB64ri32:
5126 case X86::SUB64ri8:
5127 case X86::SUB64rm:
5128 case X86::SUB64rr:
5129 case X86::SUB8i8:
5130 case X86::SUB8ri:
5131 case X86::SUB8rm:
5132 case X86::SUB8rr:
5133 return FuseKind == FuseCmp || FuseKind == FuseInc;
5134 case X86::INC16r:
5135 case X86::INC32r:
5136 case X86::INC64_16r:
5137 case X86::INC64_32r:
5138 case X86::INC64r:
5139 case X86::INC8r:
5140 case X86::DEC16r:
5141 case X86::DEC32r:
5142 case X86::DEC64_16r:
5143 case X86::DEC64_32r:
5144 case X86::DEC64r:
5145 case X86::DEC8r:
5146 return FuseKind == FuseInc;
5147 }
5148}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5149
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5150bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]5151ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5152 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5153 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]5154 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5155 return true;
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5156 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5157 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5158}
5159
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5160bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5161isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5162 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5163 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5164 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5165 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5166}
5167
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5168/// getGlobalBaseReg - Return a virtual register initialized with the
5169/// the global base register value. Output instructions required to
5170/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5171///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5172/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5173///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5174unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5175 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
5176 "X86-64 PIC uses RIP relative addressing");
5177
5178 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5179 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5180 if (GlobalBaseReg != 0)
5181 return GlobalBaseReg;
5182
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5183 // Create the register. The code to initialize it is inserted
5184 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5185 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]5186 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5187 X86FI->setGlobalBaseReg(GlobalBaseReg);
5188 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5189}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5190
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5191// These are the replaceable SSE instructions. Some of these have Int variants
5192// that we don't include here. We don't want to replace instructions selected
5193// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5194static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]5195 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]5196 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5197 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5198 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5199 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5200 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5201 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5202 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5203 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5204 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5205 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5206 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5207 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5208 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5209 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5210 // AVX 128-bit support
5211 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5212 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5213 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5214 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5215 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5216 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5217 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5218 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5219 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5220 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5221 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5222 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5223 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5224 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5225 // AVX 256-bit support
5226 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5227 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5228 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5229 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5230 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5231 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
5232};
5233
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5234static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5235 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]5236 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5237 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5238 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5239 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5240 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5241 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5242 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]5243 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5244 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5245 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5246 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
5247 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
5248 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]5249 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5250 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5251 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5252 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5253 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5254 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5255 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5256};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5257
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5258// FIXME: Some shuffle and unpack instructions have equivalents in different
5259// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5260
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5261static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5262 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5263 if (ReplaceableInstrs[i][domain-1] == opcode)
5264 return ReplaceableInstrs[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5265 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5266}
5267
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5268static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5269 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5270 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5271 return ReplaceableInstrsAVX2[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5272 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5273}
5274
5275std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5276X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5277 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5278 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5279 uint16_t validDomains = 0;
5280 if (domain && lookup(MI->getOpcode(), domain))
5281 validDomains = 0xe;
5282 else if (domain && lookupAVX2(MI->getOpcode(), domain))
5283 validDomains = hasAVX2 ? 0xe : 0x6;
5284 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5285}
5286
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5287void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5288 assert(Domain>0 && Domain<4 && "Invalid execution domain");
5289 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5290 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5291 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5292 if (!table) { // try the other table
5293 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
5294 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5295 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5296 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5297 assert(table && "Cannot change domain");
5298 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5299}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]5300
5301/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5302void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5303 NopInst.setOpcode(X86::NOOP);
5304}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5305
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]5306bool X86InstrInfo::isHighLatencyDef(int opc) const {
5307 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5308 default: return false;
5309 case X86::DIVSDrm:
5310 case X86::DIVSDrm_Int:
5311 case X86::DIVSDrr:
5312 case X86::DIVSDrr_Int:
5313 case X86::DIVSSrm:
5314 case X86::DIVSSrm_Int:
5315 case X86::DIVSSrr:
5316 case X86::DIVSSrr_Int:
5317 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5318 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5319 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5320 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5321 case X86::SQRTSDm:
5322 case X86::SQRTSDm_Int:
5323 case X86::SQRTSDr:
5324 case X86::SQRTSDr_Int:
5325 case X86::SQRTSSm:
5326 case X86::SQRTSSm_Int:
5327 case X86::SQRTSSr:
5328 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5329 // AVX instructions with high latency
5330 case X86::VDIVSDrm:
5331 case X86::VDIVSDrm_Int:
5332 case X86::VDIVSDrr:
5333 case X86::VDIVSDrr_Int:
5334 case X86::VDIVSSrm:
5335 case X86::VDIVSSrm_Int:
5336 case X86::VDIVSSrr:
5337 case X86::VDIVSSrr_Int:
5338 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5339 case X86::VSQRTPDr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5340 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5341 case X86::VSQRTPSr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5342 case X86::VSQRTSDm:
5343 case X86::VSQRTSDm_Int:
5344 case X86::VSQRTSDr:
5345 case X86::VSQRTSSm:
5346 case X86::VSQRTSSm_Int:
5347 case X86::VSQRTSSr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]5348 case X86::VSQRTPDZrm:
5349 case X86::VSQRTPDZrr:
5350 case X86::VSQRTPSZrm:
5351 case X86::VSQRTPSZrr:
5352 case X86::VSQRTSDZm:
5353 case X86::VSQRTSDZm_Int:
5354 case X86::VSQRTSDZr:
5355 case X86::VSQRTSSZm_Int:
5356 case X86::VSQRTSSZr:
5357 case X86::VSQRTSSZm:
5358 case X86::VDIVSDZrm:
5359 case X86::VDIVSDZrr:
5360 case X86::VDIVSSZrm:
5361 case X86::VDIVSSZrr:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]5362
5363 case X86::VGATHERQPSZrm:
5364 case X86::VGATHERQPDZrm:
5365 case X86::VGATHERDPDZrm:
5366 case X86::VGATHERDPSZrm:
5367 case X86::VPGATHERQDZrm:
5368 case X86::VPGATHERQQZrm:
5369 case X86::VPGATHERDDZrm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]5370 case X86::VPGATHERDQZrm:
5371 case X86::VSCATTERQPDZmr:
5372 case X86::VSCATTERQPSZmr:
5373 case X86::VSCATTERDPDZmr:
5374 case X86::VSCATTERDPSZmr:
5375 case X86::VPSCATTERQDZmr:
5376 case X86::VPSCATTERQQZmr:
5377 case X86::VPSCATTERDDZmr:
5378 case X86::VPSCATTERDQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5379 return true;
5380 }
5381}
5382
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]5383bool X86InstrInfo::
5384hasHighOperandLatency(const InstrItineraryData *ItinData,
5385 const MachineRegisterInfo *MRI,
5386 const MachineInstr *DefMI, unsigned DefIdx,
5387 const MachineInstr *UseMI, unsigned UseIdx) const {
5388 return isHighLatencyDef(DefMI->getOpcode());
5389}
5390
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5391namespace {
5392 /// CGBR - Create Global Base Reg pass. This initializes the PIC
5393 /// global base register for x86-32.
5394 struct CGBR : public MachineFunctionPass {
5395 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]5396 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5397
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5398 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5399 const X86TargetMachine *TM =
5400 static_cast<const X86TargetMachine *>(&MF.getTarget());
5401
5402 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
5403 "X86-64 PIC uses RIP relative addressing");
5404
5405 // Only emit a global base reg in PIC mode.
5406 if (TM->getRelocationModel() != Reloc::PIC_)
5407 return false;
5408
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]5409 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5410 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5411
5412 // If we didn't need a GlobalBaseReg, don't insert code.
5413 if (GlobalBaseReg == 0)
5414 return false;
5415
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5416 // Insert the set of GlobalBaseReg into the first MBB of the function
5417 MachineBasicBlock &FirstMBB = MF.front();
5418 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5419 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5420 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5421 const X86InstrInfo *TII = TM->getInstrInfo();
5422
5423 unsigned PC;
5424 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]5425 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5426 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]5427 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5428
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5429 // Operand of MovePCtoStack is completely ignored by asm printer. It's
5430 // only used in JIT code emission as displacement to pc.
5431 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5432
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5433 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5434 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5435 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5436 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5437 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5438 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5439 X86II::MO_GOT_ABSOLUTE_ADDRESS);
5440 }
5441
5442 return true;
5443 }
5444
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5445 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5446 return "X86 PIC Global Base Reg Initialization";
5447 }
5448
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5449 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5450 AU.setPreservesCFG();
5451 MachineFunctionPass::getAnalysisUsage(AU);
5452 }
5453 };
5454}
5455
5456char CGBR::ID = 0;
5457FunctionPass*
5458llvm::createGlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5459
5460namespace {
5461 struct LDTLSCleanup : public MachineFunctionPass {
5462 static char ID;
5463 LDTLSCleanup() : MachineFunctionPass(ID) {}
5464
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5465 bool runOnMachineFunction(MachineFunction &MF) override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5466 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5467 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5468 // No point folding accesses if there isn't at least two.
5469 return false;
5470 }
5471
5472 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5473 return VisitNode(DT->getRootNode(), 0);
5474 }
5475
5476 // Visit the dominator subtree rooted at Node in pre-order.
5477 // If TLSBaseAddrReg is non-null, then use that to replace any
5478 // TLS_base_addr instructions. Otherwise, create the register
5479 // when the first such instruction is seen, and then use it
5480 // as we encounter more instructions.
5481 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5482 MachineBasicBlock *BB = Node->getBlock();
5483 bool Changed = false;
5484
5485 // Traverse the current block.
5486 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5487 ++I) {
5488 switch (I->getOpcode()) {
5489 case X86::TLS_base_addr32:
5490 case X86::TLS_base_addr64:
5491 if (TLSBaseAddrReg)
5492 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5493 else
5494 I = SetRegister(I, &TLSBaseAddrReg);
5495 Changed = true;
5496 break;
5497 default:
5498 break;
5499 }
5500 }
5501
5502 // Visit the children of this block in the dominator tree.
5503 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5504 I != E; ++I) {
5505 Changed |= VisitNode(*I, TLSBaseAddrReg);
5506 }
5507
5508 return Changed;
5509 }
5510
5511 // Replace the TLS_base_addr instruction I with a copy from
5512 // TLSBaseAddrReg, returning the new instruction.
5513 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5514 unsigned TLSBaseAddrReg) {
5515 MachineFunction *MF = I->getParent()->getParent();
5516 const X86TargetMachine *TM =
5517 static_cast<const X86TargetMachine *>(&MF->getTarget());
5518 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5519 const X86InstrInfo *TII = TM->getInstrInfo();
5520
5521 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5522 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5523 TII->get(TargetOpcode::COPY),
5524 is64Bit ? X86::RAX : X86::EAX)
5525 .addReg(TLSBaseAddrReg);
5526
5527 // Erase the TLS_base_addr instruction.
5528 I->eraseFromParent();
5529
5530 return Copy;
5531 }
5532
5533 // Create a virtal register in *TLSBaseAddrReg, and populate it by
5534 // inserting a copy instruction after I. Returns the new instruction.
5535 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5536 MachineFunction *MF = I->getParent()->getParent();
5537 const X86TargetMachine *TM =
5538 static_cast<const X86TargetMachine *>(&MF->getTarget());
5539 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5540 const X86InstrInfo *TII = TM->getInstrInfo();
5541
5542 // Create a virtual register for the TLS base address.
5543 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5544 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5545 ? &X86::GR64RegClass
5546 : &X86::GR32RegClass);
5547
5548 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5549 MachineInstr *Next = I->getNextNode();
5550 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5551 TII->get(TargetOpcode::COPY),
5552 *TLSBaseAddrReg)
5553 .addReg(is64Bit ? X86::RAX : X86::EAX);
5554
5555 return Copy;
5556 }
5557
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5558 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5559 return "Local Dynamic TLS Access Clean-up";
5560 }
5561
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5562 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5563 AU.setPreservesCFG();
5564 AU.addRequired<MachineDominatorTree>();
5565 MachineFunctionPass::getAnalysisUsage(AU);
5566 }
5567 };
5568}
5569
5570char LDTLSCleanup::ID = 0;
5571FunctionPass*
5572llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }