blob: 4f330e3a884be4f1432669d3573e43edf45b7a73 [file] [log] [blame]
Eugene Zelenko076468c2017-09-20 21:35:51 +00001//===- Thumb1FrameLowering.cpp - Thumb1 Frame Information -----------------===//
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Anton Korobeynikov2f931282011-01-10 12:39:04 +000010// This file contains the Thumb1 implementation of TargetFrameLowering class.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000011//
12//===----------------------------------------------------------------------===//
13
Chandler Carruth6bda14b2017-06-06 11:49:48 +000014#include "Thumb1FrameLowering.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000015#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000017#include "ARMMachineFunctionInfo.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000018#include "ARMSubtarget.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000019#include "Thumb1InstrInfo.h"
20#include "ThumbRegisterInfo.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000021#include "Utils/ARMBaseInfo.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000022#include "llvm/ADT/BitVector.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000023#include "llvm/ADT/STLExtras.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000024#include "llvm/ADT/SmallVector.h"
Quentin Colombet71a71482015-07-20 21:42:14 +000025#include "llvm/CodeGen/LivePhysRegs.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000026#include "llvm/CodeGen/MachineBasicBlock.h"
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000027#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000029#include "llvm/CodeGen/MachineInstr.h"
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000030#include "llvm/CodeGen/MachineInstrBuilder.h"
Artyom Skrobovf6830f42014-02-14 17:19:07 +000031#include "llvm/CodeGen/MachineModuleInfo.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000032#include "llvm/CodeGen/MachineOperand.h"
Evan Chengeb56dca2010-11-22 18:12:04 +000033#include "llvm/CodeGen/MachineRegisterInfo.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000034#include "llvm/IR/DebugLoc.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000035#include "llvm/MC/MCContext.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000036#include "llvm/MC/MCDwarf.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000037#include "llvm/MC/MCRegisterInfo.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000038#include "llvm/Support/Compiler.h"
39#include "llvm/Support/ErrorHandling.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000040#include "llvm/Support/MathExtras.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000041#include "llvm/Target/TargetInstrInfo.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000042#include "llvm/Target/TargetOpcodes.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000043#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer79d53fe2017-08-30 22:28:30 +000044#include <bitset>
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000045#include <cassert>
46#include <iterator>
47#include <vector>
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000048
49using namespace llvm;
50
Eric Christopher45fb7b62014-06-26 19:29:59 +000051Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
52 : ARMFrameLowering(sti) {}
53
Jim Grosbache7e2aca2011-09-13 20:30:37 +000054bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
Matthias Braun941a7052016-07-28 18:40:00 +000055 const MachineFrameInfo &MFI = MF.getFrameInfo();
56 unsigned CFSize = MFI.getMaxCallFrameSize();
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +000057 // It's not always a good idea to include the call frame as part of the
58 // stack frame. ARM (especially Thumb) has small immediate offset to
59 // address the stack frame. So a large call frame can cause poor codegen
60 // and may even makes it impossible to scavenge a register.
61 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
62 return false;
63
Matthias Braun941a7052016-07-28 18:40:00 +000064 return !MFI.hasVarSizedObjects();
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +000065}
66
Benjamin Kramerbdc49562016-06-12 15:39:02 +000067static void emitSPUpdate(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator &MBBI,
69 const TargetInstrInfo &TII, const DebugLoc &dl,
70 const ThumbRegisterInfo &MRI, int NumBytes,
71 unsigned MIFlags = MachineInstr::NoFlags) {
Anton Korobeynikove7410dd2011-03-05 18:43:32 +000072 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
Anton Korobeynikova8d177b2011-03-05 18:43:50 +000073 MRI, MIFlags);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000074}
75
Hans Wennborge1a2e902016-03-31 18:33:38 +000076MachineBasicBlock::iterator Thumb1FrameLowering::
Eli Bendersky8da87162013-02-21 20:05:00 +000077eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator I) const {
79 const Thumb1InstrInfo &TII =
Eric Christopher1b21f002015-01-29 00:19:33 +000080 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
Eric Christopherae326492015-03-12 22:48:50 +000081 const ThumbRegisterInfo *RegInfo =
82 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
Eli Bendersky8da87162013-02-21 20:05:00 +000083 if (!hasReservedCallFrame(MF)) {
84 // If we have alloca, convert as follows:
85 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
86 // ADJCALLSTACKUP -> add, sp, sp, amount
Duncan P. N. Exon Smith29c52492016-07-08 20:21:17 +000087 MachineInstr &Old = *I;
88 DebugLoc dl = Old.getDebugLoc();
Serge Pavlov5943a962017-04-19 03:12:05 +000089 unsigned Amount = TII.getFrameSize(Old);
Eli Bendersky8da87162013-02-21 20:05:00 +000090 if (Amount != 0) {
91 // We need to keep the stack aligned properly. To do this, we round the
92 // amount of space needed for the outgoing arguments up to the next
93 // alignment boundary.
Serge Pavlov5943a962017-04-19 03:12:05 +000094 Amount = alignTo(Amount, getStackAlignment());
Eli Bendersky8da87162013-02-21 20:05:00 +000095
96 // Replace the pseudo instruction with a new instruction...
Duncan P. N. Exon Smith29c52492016-07-08 20:21:17 +000097 unsigned Opc = Old.getOpcode();
Eli Bendersky8da87162013-02-21 20:05:00 +000098 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
99 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
100 } else {
101 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
102 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
103 }
104 }
105 }
Hans Wennborge1a2e902016-03-31 18:33:38 +0000106 return MBB.erase(I);
Eli Bendersky8da87162013-02-21 20:05:00 +0000107}
108
Quentin Colombet61b305e2015-05-05 17:38:16 +0000109void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
110 MachineBasicBlock &MBB) const {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000111 MachineBasicBlock::iterator MBBI = MBB.begin();
Matthias Braun941a7052016-07-28 18:40:00 +0000112 MachineFrameInfo &MFI = MF.getFrameInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000113 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000114 MachineModuleInfo &MMI = MF.getMMI();
115 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
Eric Christopherae326492015-03-12 22:48:50 +0000116 const ThumbRegisterInfo *RegInfo =
117 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000118 const Thumb1InstrInfo &TII =
Eric Christopher1b21f002015-01-29 00:19:33 +0000119 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000120
Tim Northover8cda34f2015-03-11 18:54:22 +0000121 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
Matthias Braun941a7052016-07-28 18:40:00 +0000122 unsigned NumBytes = MFI.getStackSize();
Tim Northover775aaeb2015-11-05 21:54:58 +0000123 assert(NumBytes >= ArgRegsSaveSize &&
124 "ArgRegsSaveSize is included in NumBytes");
Matthias Braun941a7052016-07-28 18:40:00 +0000125 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
Tim Northover775aaeb2015-11-05 21:54:58 +0000126
127 // Debug location must be unknown since the first debug location is used
128 // to determine the end of the prologue.
129 DebugLoc dl;
130
131 unsigned FramePtr = RegInfo->getFrameRegister(MF);
132 unsigned BasePtr = RegInfo->getBaseRegister();
133 int CFAOffset = 0;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000134
135 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
136 NumBytes = (NumBytes + 3) & ~3;
Matthias Braun941a7052016-07-28 18:40:00 +0000137 MFI.setStackSize(NumBytes);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000138
139 // Determine the sizes of each callee-save spill areas and record which frame
140 // belongs to which callee-save spill areas.
141 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
142 int FramePtrSpillFI = 0;
143
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000144 if (ArgRegsSaveSize) {
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000145 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
Anton Korobeynikova8d177b2011-03-05 18:43:50 +0000146 MachineInstr::FrameSetup);
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000147 CFAOffset -= ArgRegsSaveSize;
Matthias Braunf23ef432016-11-30 23:48:42 +0000148 unsigned CFIIndex = MF.addFrameInst(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000149 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
150 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Adrian Prantld9e64b62014-12-22 23:09:14 +0000151 .addCFIIndex(CFIIndex)
152 .setMIFlags(MachineInstr::FrameSetup);
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000153 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000154
155 if (!AFI->hasStackFrame()) {
Oliver Stannardd55e1152014-03-05 15:25:27 +0000156 if (NumBytes - ArgRegsSaveSize != 0) {
157 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
Anton Korobeynikova8d177b2011-03-05 18:43:50 +0000158 MachineInstr::FrameSetup);
Oliver Stannardd55e1152014-03-05 15:25:27 +0000159 CFAOffset -= NumBytes - ArgRegsSaveSize;
Matthias Braunf23ef432016-11-30 23:48:42 +0000160 unsigned CFIIndex = MF.addFrameInst(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000161 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
162 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Adrian Prantld9e64b62014-12-22 23:09:14 +0000163 .addCFIIndex(CFIIndex)
164 .setMIFlags(MachineInstr::FrameSetup);
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000165 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000166 return;
167 }
168
169 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
170 unsigned Reg = CSI[i].getReg();
171 int FI = CSI[i].getFrameIdx();
172 switch (Reg) {
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000173 case ARM::R8:
174 case ARM::R9:
175 case ARM::R10:
176 case ARM::R11:
Oliver Stannard9aa6f012016-08-23 09:19:22 +0000177 if (STI.splitFramePushPop(MF)) {
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000178 GPRCS2Size += 4;
179 break;
180 }
Justin Bognerb03fd122016-08-17 05:10:15 +0000181 LLVM_FALLTHROUGH;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000182 case ARM::R4:
183 case ARM::R5:
184 case ARM::R6:
185 case ARM::R7:
186 case ARM::LR:
187 if (Reg == FramePtr)
188 FramePtrSpillFI = FI;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000189 GPRCS1Size += 4;
190 break;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000191 default:
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000192 DPRCSSize += 8;
193 }
194 }
Tim Northover775aaeb2015-11-05 21:54:58 +0000195
196 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
197 ++MBBI;
198 }
199
200 // Determine starting offsets of spill areas.
Oliver Stannardd55e1152014-03-05 15:25:27 +0000201 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000202 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
203 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
Logan Chien53c18d82013-02-20 12:21:33 +0000204 bool HasFP = hasFP(MF);
205 if (HasFP)
Matthias Braun941a7052016-07-28 18:40:00 +0000206 AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
Logan Chien53c18d82013-02-20 12:21:33 +0000207 NumBytes);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000208 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
209 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
210 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000211 NumBytes = DPRCSOffset;
Evan Chengeb56dca2010-11-22 18:12:04 +0000212
Tim Northover93bcc662013-11-08 17:18:07 +0000213 int FramePtrOffsetInBlock = 0;
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000214 unsigned adjustedGPRCS1Size = GPRCS1Size;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000215 if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
216 tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
Tim Northover93bcc662013-11-08 17:18:07 +0000217 FramePtrOffsetInBlock = NumBytes;
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000218 adjustedGPRCS1Size += NumBytes;
Tim Northover93bcc662013-11-08 17:18:07 +0000219 NumBytes = 0;
220 }
221
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000222 if (adjustedGPRCS1Size) {
223 CFAOffset -= adjustedGPRCS1Size;
Matthias Braunf23ef432016-11-30 23:48:42 +0000224 unsigned CFIIndex = MF.addFrameInst(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000225 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
226 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Adrian Prantld9e64b62014-12-22 23:09:14 +0000227 .addCFIIndex(CFIIndex)
228 .setMIFlags(MachineInstr::FrameSetup);
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000229 }
230 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
231 E = CSI.end(); I != E; ++I) {
232 unsigned Reg = I->getReg();
233 int FI = I->getFrameIdx();
234 switch (Reg) {
235 case ARM::R8:
236 case ARM::R9:
237 case ARM::R10:
238 case ARM::R11:
239 case ARM::R12:
Oliver Stannard9aa6f012016-08-23 09:19:22 +0000240 if (STI.splitFramePushPop(MF))
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000241 break;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000242 LLVM_FALLTHROUGH;
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000243 case ARM::R0:
244 case ARM::R1:
245 case ARM::R2:
246 case ARM::R3:
247 case ARM::R4:
248 case ARM::R5:
249 case ARM::R6:
250 case ARM::R7:
251 case ARM::LR:
Matthias Braunf23ef432016-11-30 23:48:42 +0000252 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
Matthias Braun941a7052016-07-28 18:40:00 +0000253 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000254 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Adrian Prantld9e64b62014-12-22 23:09:14 +0000255 .addCFIIndex(CFIIndex)
256 .setMIFlags(MachineInstr::FrameSetup);
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000257 break;
258 }
259 }
260
Evan Chengeb56dca2010-11-22 18:12:04 +0000261 // Adjust FP so it point to the stack slot that contains the previous FP.
Logan Chien53c18d82013-02-20 12:21:33 +0000262 if (HasFP) {
NAKAMURA Takumi0a7d0ad2015-09-22 11:15:07 +0000263 FramePtrOffsetInBlock +=
Matthias Braun941a7052016-07-28 18:40:00 +0000264 MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
Diana Picus4f8c3e12017-01-13 09:37:56 +0000265 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
266 .addReg(ARM::SP)
267 .addImm(FramePtrOffsetInBlock / 4)
268 .setMIFlags(MachineInstr::FrameSetup)
269 .add(predOps(ARMCC::AL));
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000270 if(FramePtrOffsetInBlock) {
271 CFAOffset += FramePtrOffsetInBlock;
Matthias Braunf23ef432016-11-30 23:48:42 +0000272 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000273 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
274 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Adrian Prantld9e64b62014-12-22 23:09:14 +0000275 .addCFIIndex(CFIIndex)
276 .setMIFlags(MachineInstr::FrameSetup);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000277 } else {
278 unsigned CFIIndex =
Matthias Braunf23ef432016-11-30 23:48:42 +0000279 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000280 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
281 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Adrian Prantld9e64b62014-12-22 23:09:14 +0000282 .addCFIIndex(CFIIndex)
283 .setMIFlags(MachineInstr::FrameSetup);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000284 }
Jim Grosbachdca85312011-06-13 21:18:25 +0000285 if (NumBytes > 508)
286 // If offset is > 508 then sp cannot be adjusted in a single instruction,
Evan Chengeb56dca2010-11-22 18:12:04 +0000287 // try restoring from fp instead.
288 AFI->setShouldRestoreSPFromFP(true);
289 }
290
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000291 // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
292 // and tMOVr instructions. We don't need to add any call frame information
293 // in-between these instructions, because they do not modify the high
294 // registers.
295 while (true) {
296 MachineBasicBlock::iterator OldMBBI = MBBI;
297 // Skip a run of tMOVr instructions
298 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
299 MBBI++;
300 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
301 MBBI++;
302 } else {
303 // We have reached an instruction which is not a push, so the previous
304 // run of tMOVr instructions (which may have been empty) was not part of
305 // the prologue. Reset MBBI back to the last PUSH of the prologue.
306 MBBI = OldMBBI;
307 break;
308 }
309 }
310
311 // Emit call frame information for the callee-saved high registers.
312 for (auto &I : CSI) {
313 unsigned Reg = I.getReg();
314 int FI = I.getFrameIdx();
315 switch (Reg) {
316 case ARM::R8:
317 case ARM::R9:
318 case ARM::R10:
319 case ARM::R11:
320 case ARM::R12: {
Matthias Braunf23ef432016-11-30 23:48:42 +0000321 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000322 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
323 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
324 .addCFIIndex(CFIIndex)
325 .setMIFlags(MachineInstr::FrameSetup);
326 break;
327 }
328 default:
329 break;
330 }
331 }
332
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000333 if (NumBytes) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000334 // Insert it after all the callee-save spills.
Anton Korobeynikova8d177b2011-03-05 18:43:50 +0000335 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
336 MachineInstr::FrameSetup);
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000337 if (!HasFP) {
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000338 CFAOffset -= NumBytes;
Matthias Braunf23ef432016-11-30 23:48:42 +0000339 unsigned CFIIndex = MF.addFrameInst(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000340 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
341 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Adrian Prantld9e64b62014-12-22 23:09:14 +0000342 .addCFIIndex(CFIIndex)
343 .setMIFlags(MachineInstr::FrameSetup);
Artyom Skrobovf6830f42014-02-14 17:19:07 +0000344 }
345 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000346
Logan Chien53c18d82013-02-20 12:21:33 +0000347 if (STI.isTargetELF() && HasFP)
Matthias Braun941a7052016-07-28 18:40:00 +0000348 MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
349 AFI->getFramePtrSpillOffset());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000350
351 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
352 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
353 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
354
Momchil Velikovd6a4ab32017-10-22 11:56:35 +0000355 if (RegInfo->needsStackRealignment(MF)) {
356 const unsigned NrBitsToZero = countTrailingZeros(MFI.getMaxAlignment());
357 // Emit the following sequence, using R4 as a temporary, since we cannot use
358 // SP as a source or destination register for the shifts:
359 // mov r4, sp
360 // lsrs r4, r4, #NrBitsToZero
361 // lsls r4, r4, #NrBitsToZero
362 // mov sp, r4
363 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
364 .addReg(ARM::SP, RegState::Kill)
365 .add(predOps(ARMCC::AL));
366
367 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
368 .addDef(ARM::CPSR)
369 .addReg(ARM::R4, RegState::Kill)
370 .addImm(NrBitsToZero)
371 .add(predOps(ARMCC::AL));
372
373 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
374 .addDef(ARM::CPSR)
375 .addReg(ARM::R4, RegState::Kill)
376 .addImm(NrBitsToZero)
377 .add(predOps(ARMCC::AL));
378
379 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
380 .addReg(ARM::R4, RegState::Kill)
381 .add(predOps(ARMCC::AL));
382
383 AFI->setShouldRestoreSPFromFP(true);
384 }
Chad Rosier1809d6c2011-10-15 00:28:24 +0000385
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000386 // If we need a base pointer, set it up here. It's whatever the value
387 // of the stack pointer is at this point. Any variable size objects
388 // will be allocated after this, so we can still use the base pointer
389 // to reference locals.
390 if (RegInfo->hasBasePointer(MF))
Diana Picus4f8c3e12017-01-13 09:37:56 +0000391 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
392 .addReg(ARM::SP)
393 .add(predOps(ARMCC::AL));
Anton Korobeynikova8d177b2011-03-05 18:43:50 +0000394
Eric Christopher39043432011-01-11 00:16:04 +0000395 // If the frame has variable sized objects then the epilogue must restore
396 // the sp from fp. We can assume there's an FP here since hasFP already
397 // checks for hasVarSizedObjects.
Matthias Braun941a7052016-07-28 18:40:00 +0000398 if (MFI.hasVarSizedObjects())
Eric Christopher39043432011-01-11 00:16:04 +0000399 AFI->setShouldRestoreSPFromFP(true);
Florian Hahn8485cec2017-01-18 15:01:22 +0000400
401 // In some cases, virtual registers have been introduced, e.g. by uses of
402 // emitThumbRegPlusImmInReg.
403 MF.getProperties().reset(MachineFunctionProperties::Property::NoVRegs);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000404}
405
Duncan P. N. Exon Smith29c52492016-07-08 20:21:17 +0000406static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
407 if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
408 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000409 return true;
Duncan P. N. Exon Smith29c52492016-07-08 20:21:17 +0000410 else if (MI.getOpcode() == ARM::tPOP) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000411 return true;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000412 } else if (MI.getOpcode() == ARM::tMOVr) {
413 unsigned Dst = MI.getOperand(0).getReg();
414 unsigned Src = MI.getOperand(1).getReg();
415 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
416 ARM::hGPRRegClass.contains(Dst));
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000417 }
418 return false;
419}
420
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000421void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000422 MachineBasicBlock &MBB) const {
Quentin Colombet71a71482015-07-20 21:42:14 +0000423 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
424 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
Matthias Braun941a7052016-07-28 18:40:00 +0000425 MachineFrameInfo &MFI = MF.getFrameInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000426 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Eric Christopherae326492015-03-12 22:48:50 +0000427 const ThumbRegisterInfo *RegInfo =
428 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000429 const Thumb1InstrInfo &TII =
Eric Christopher1b21f002015-01-29 00:19:33 +0000430 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000431
Tim Northover8cda34f2015-03-11 18:54:22 +0000432 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
Matthias Braun941a7052016-07-28 18:40:00 +0000433 int NumBytes = (int)MFI.getStackSize();
David Blaikie7f4a52e2014-03-05 18:53:36 +0000434 assert((unsigned)NumBytes >= ArgRegsSaveSize &&
Oliver Stannardd55e1152014-03-05 15:25:27 +0000435 "ArgRegsSaveSize is included in NumBytes");
Eric Christopher7af952872015-03-11 21:41:28 +0000436 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000437 unsigned FramePtr = RegInfo->getFrameRegister(MF);
438
439 if (!AFI->hasStackFrame()) {
Oliver Stannardd55e1152014-03-05 15:25:27 +0000440 if (NumBytes - ArgRegsSaveSize != 0)
441 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000442 } else {
443 // Unwind MBBI to point to first LDR / VLDRD.
444 if (MBBI != MBB.begin()) {
445 do
446 --MBBI;
Duncan P. N. Exon Smith29c52492016-07-08 20:21:17 +0000447 while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
448 if (!isCSRestore(*MBBI, CSRegs))
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000449 ++MBBI;
450 }
451
452 // Move SP to start of FP callee save spill area.
453 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
454 AFI->getGPRCalleeSavedArea2Size() +
Oliver Stannardd55e1152014-03-05 15:25:27 +0000455 AFI->getDPRCalleeSavedAreaSize() +
456 ArgRegsSaveSize);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000457
458 if (AFI->shouldRestoreSPFromFP()) {
459 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
460 // Reset SP based on frame pointer only if the stack frame extends beyond
Eric Christopher39043432011-01-11 00:16:04 +0000461 // frame pointer stack slot, the target is ELF and the function has FP, or
462 // the target uses var sized objects.
Evan Chengeb56dca2010-11-22 18:12:04 +0000463 if (NumBytes) {
Matthias Braun941a7052016-07-28 18:40:00 +0000464 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
Evan Chengeb56dca2010-11-22 18:12:04 +0000465 "No scratch register to restore SP from FP!");
Anton Korobeynikove7410dd2011-03-05 18:43:32 +0000466 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
467 TII, *RegInfo);
Diana Picus4f8c3e12017-01-13 09:37:56 +0000468 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
469 .addReg(ARM::R4)
470 .add(predOps(ARMCC::AL));
Evan Chengeb56dca2010-11-22 18:12:04 +0000471 } else
Diana Picus4f8c3e12017-01-13 09:37:56 +0000472 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
473 .addReg(FramePtr)
474 .add(predOps(ARMCC::AL));
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000475 } else {
Quentin Colombet71a71482015-07-20 21:42:14 +0000476 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
Duncan P. N. Exon Smith29c52492016-07-08 20:21:17 +0000477 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000478 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
Duncan P. N. Exon Smith29c52492016-07-08 20:21:17 +0000479 if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
Tim Northover93bcc662013-11-08 17:18:07 +0000480 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
Duncan P. N. Exon Smith29c52492016-07-08 20:21:17 +0000481 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000482 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
483 }
484 }
485
Quentin Colombet48b77202015-07-22 16:34:37 +0000486 if (needPopSpecialFixUp(MF)) {
487 bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
488 (void)Done;
489 assert(Done && "Emission of the special fixup failed!?");
490 }
491}
492
493bool Thumb1FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
494 if (!needPopSpecialFixUp(*MBB.getParent()))
495 return true;
496
497 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
498 return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
499}
500
501bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
502 ARMFunctionInfo *AFI =
503 const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
504 if (AFI->getArgRegsSaveSize())
505 return true;
506
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000507 // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
Matthias Braun941a7052016-07-28 18:40:00 +0000508 for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
Jonathan Roelofsef84bda2014-08-05 21:32:21 +0000509 if (CSI.getReg() == ARM::LR)
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000510 return true;
511
512 return false;
Quentin Colombet48b77202015-07-22 16:34:37 +0000513}
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000514
Quentin Colombet48b77202015-07-22 16:34:37 +0000515bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
516 bool DoIt) const {
517 MachineFunction &MF = *MBB.getParent();
518 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
519 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
520 const TargetInstrInfo &TII = *STI.getInstrInfo();
521 const ThumbRegisterInfo *RegInfo =
522 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
Quentin Colombet71a71482015-07-20 21:42:14 +0000523
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000524 // If MBBI is a return instruction, or is a tPOP followed by a return
525 // instruction in the successor BB, we may be able to directly restore
526 // LR in the PC.
527 // This is only possible with v5T ops (v4T can't change the Thumb bit via
528 // a POP PC instruction), and only if we do not need to emit any SP update.
529 // Otherwise, we need a temporary register to pop the value
530 // and copy that value into LR.
Quentin Colombet48b77202015-07-22 16:34:37 +0000531 auto MBBI = MBB.getFirstTerminator();
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000532 bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
533 if (CanRestoreDirectly) {
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000534 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000535 CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
536 MBBI->getOpcode() == ARM::tPOP_RET);
537 else {
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000538 auto MBBI_prev = MBBI;
539 MBBI_prev--;
540 assert(MBBI_prev->getOpcode() == ARM::tPOP);
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000541 assert(MBB.succ_size() == 1);
542 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000543 MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000544 else
545 CanRestoreDirectly = false;
546 }
547 }
548
549 if (CanRestoreDirectly) {
550 if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
551 return true;
552 MachineInstrBuilder MIB =
Diana Picus4f8c3e12017-01-13 09:37:56 +0000553 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
554 .add(predOps(ARMCC::AL));
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000555 // Copy implicit ops and popped registers, if any.
556 for (auto MO: MBBI->operands())
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000557 if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
Diana Picus116bbab2017-01-13 09:58:52 +0000558 MIB.add(MO);
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000559 MIB.addReg(ARM::PC, RegState::Define);
560 // Erase the old instruction (tBX_RET or tPOP).
561 MBB.erase(MBBI);
562 return true;
563 }
Quentin Colombet71a71482015-07-20 21:42:14 +0000564
Quentin Colombet48b77202015-07-22 16:34:37 +0000565 // Look for a temporary register to use.
566 // First, compute the liveness information.
Matthias Braunac4307c2017-05-26 21:51:00 +0000567 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
568 LivePhysRegs UsedRegs(TRI);
Matthias Braund1aabb22016-05-03 00:24:32 +0000569 UsedRegs.addLiveOuts(MBB);
Quentin Colombet48b77202015-07-22 16:34:37 +0000570 // The semantic of pristines changed recently and now,
571 // the callee-saved registers that are touched in the function
572 // are not part of the pristines set anymore.
573 // Add those callee-saved now.
Matthias Braunac4307c2017-05-26 21:51:00 +0000574 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
Quentin Colombet48b77202015-07-22 16:34:37 +0000575 for (unsigned i = 0; CSRegs[i]; ++i)
576 UsedRegs.addReg(CSRegs[i]);
Quentin Colombet71a71482015-07-20 21:42:14 +0000577
Quentin Colombet48b77202015-07-22 16:34:37 +0000578 DebugLoc dl = DebugLoc();
579 if (MBBI != MBB.end()) {
580 dl = MBBI->getDebugLoc();
581 auto InstUpToMBBI = MBB.end();
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000582 while (InstUpToMBBI != MBBI)
583 // The pre-decrement is on purpose here.
584 // We want to have the liveness right before MBBI.
585 UsedRegs.stepBackward(*--InstUpToMBBI);
Quentin Colombet48b77202015-07-22 16:34:37 +0000586 }
587
588 // Look for a register that can be directly use in the POP.
589 unsigned PopReg = 0;
590 // And some temporary register, just in case.
591 unsigned TemporaryReg = 0;
592 BitVector PopFriendly =
Matthias Braunac4307c2017-05-26 21:51:00 +0000593 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
Quentin Colombet48b77202015-07-22 16:34:37 +0000594 assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
595 // Rebuild the GPRs from the high registers because they are removed
596 // form the GPR reg class for thumb1.
597 BitVector GPRsNoLRSP =
Matthias Braunac4307c2017-05-26 21:51:00 +0000598 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
Quentin Colombet48b77202015-07-22 16:34:37 +0000599 GPRsNoLRSP |= PopFriendly;
600 GPRsNoLRSP.reset(ARM::LR);
601 GPRsNoLRSP.reset(ARM::SP);
602 GPRsNoLRSP.reset(ARM::PC);
Francis Visoiu Mistrihb52e0362017-05-17 01:07:53 +0000603 for (unsigned Register : GPRsNoLRSP.set_bits()) {
Quentin Colombet48b77202015-07-22 16:34:37 +0000604 if (!UsedRegs.contains(Register)) {
605 // Remember the first pop-friendly register and exit.
606 if (PopFriendly.test(Register)) {
607 PopReg = Register;
608 TemporaryReg = 0;
609 break;
Quentin Colombet71a71482015-07-20 21:42:14 +0000610 }
Quentin Colombet48b77202015-07-22 16:34:37 +0000611 // Otherwise, remember that the register will be available to
612 // save a pop-friendly register.
613 TemporaryReg = Register;
Jonathan Roelofsef84bda2014-08-05 21:32:21 +0000614 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000615 }
Quentin Colombet48b77202015-07-22 16:34:37 +0000616
617 if (!DoIt && !PopReg && !TemporaryReg)
618 return false;
619
620 assert((PopReg || TemporaryReg) && "Cannot get LR");
621
622 if (TemporaryReg) {
623 assert(!PopReg && "Unnecessary MOV is about to be inserted");
624 PopReg = PopFriendly.find_first();
Diana Picus4f8c3e12017-01-13 09:37:56 +0000625 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
626 .addReg(TemporaryReg, RegState::Define)
627 .addReg(PopReg, RegState::Kill)
628 .add(predOps(ARMCC::AL));
Quentin Colombet48b77202015-07-22 16:34:37 +0000629 }
630
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000631 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
Artyom Skrobov0a37b802015-12-08 19:59:01 +0000632 // We couldn't use the direct restoration above, so
633 // perform the opposite conversion: tPOP_RET to tPOP.
634 MachineInstrBuilder MIB =
Diana Picus4f8c3e12017-01-13 09:37:56 +0000635 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
636 .add(predOps(ARMCC::AL));
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000637 bool Popped = false;
Artyom Skrobov0a37b802015-12-08 19:59:01 +0000638 for (auto MO: MBBI->operands())
639 if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
640 MO.getReg() != ARM::PC) {
Diana Picus116bbab2017-01-13 09:58:52 +0000641 MIB.add(MO);
Artyom Skrobov0a37b802015-12-08 19:59:01 +0000642 if (!MO.isImplicit())
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000643 Popped = true;
Artyom Skrobov0a37b802015-12-08 19:59:01 +0000644 }
645 // Is there anything left to pop?
646 if (!Popped)
647 MBB.erase(MIB.getInstr());
648 // Erase the old instruction.
649 MBB.erase(MBBI);
Diana Picus4f8c3e12017-01-13 09:37:56 +0000650 MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
651 .add(predOps(ARMCC::AL));
Artyom Skrobov5d1f2522015-12-01 19:25:11 +0000652 }
653
Quentin Colombet48b77202015-07-22 16:34:37 +0000654 assert(PopReg && "Do not know how to get LR");
Diana Picus4f8c3e12017-01-13 09:37:56 +0000655 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
656 .add(predOps(ARMCC::AL))
Quentin Colombet48b77202015-07-22 16:34:37 +0000657 .addReg(PopReg, RegState::Define);
658
659 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
660
Diana Picus4f8c3e12017-01-13 09:37:56 +0000661 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
662 .addReg(ARM::LR, RegState::Define)
663 .addReg(PopReg, RegState::Kill)
664 .add(predOps(ARMCC::AL));
Quentin Colombet48b77202015-07-22 16:34:37 +0000665
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000666 if (TemporaryReg)
Diana Picus4f8c3e12017-01-13 09:37:56 +0000667 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
668 .addReg(PopReg, RegState::Define)
669 .addReg(TemporaryReg, RegState::Kill)
670 .add(predOps(ARMCC::AL));
Quentin Colombet48b77202015-07-22 16:34:37 +0000671
672 return true;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000673}
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000674
Eugene Zelenko076468c2017-09-20 21:35:51 +0000675using ARMRegSet = std::bitset<ARM::NUM_TARGET_REGS>;
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000676
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000677// Return the first iteraror after CurrentReg which is present in EnabledRegs,
678// or OrderEnd if no further registers are in that set. This does not advance
679// the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000680static const unsigned *findNextOrderedReg(const unsigned *CurrentReg,
681 const ARMRegSet &EnabledRegs,
682 const unsigned *OrderEnd) {
683 while (CurrentReg != OrderEnd && !EnabledRegs[*CurrentReg])
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000684 ++CurrentReg;
685 return CurrentReg;
686}
687
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000688bool Thumb1FrameLowering::
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000689spillCalleeSavedRegisters(MachineBasicBlock &MBB,
690 MachineBasicBlock::iterator MI,
691 const std::vector<CalleeSavedInfo> &CSI,
692 const TargetRegisterInfo *TRI) const {
693 if (CSI.empty())
694 return false;
695
Tim Northover775aaeb2015-11-05 21:54:58 +0000696 DebugLoc DL;
697 const TargetInstrInfo &TII = *STI.getInstrInfo();
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000698 MachineFunction &MF = *MBB.getParent();
699 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
700 MF.getSubtarget().getRegisterInfo());
Tim Northover775aaeb2015-11-05 21:54:58 +0000701
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000702 ARMRegSet LoRegsToSave; // r0-r7, lr
703 ARMRegSet HiRegsToSave; // r8-r11
704 ARMRegSet CopyRegs; // Registers which can be used after pushing
705 // LoRegs for saving HiRegs.
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000706
Tim Northover775aaeb2015-11-05 21:54:58 +0000707 for (unsigned i = CSI.size(); i != 0; --i) {
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000708 unsigned Reg = CSI[i-1].getReg();
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000709
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000710 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000711 LoRegsToSave[Reg] = true;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000712 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000713 HiRegsToSave[Reg] = true;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000714 } else {
715 llvm_unreachable("callee-saved register of unexpected class");
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000716 }
717
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000718 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
719 !MF.getRegInfo().isLiveIn(Reg) &&
720 !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000721 CopyRegs[Reg] = true;
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000722 }
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000723
724 // Unused argument registers can be used for the high register saving.
725 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
726 if (!MF.getRegInfo().isLiveIn(ArgReg))
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000727 CopyRegs[ArgReg] = true;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000728
729 // Push the low registers and lr
Matthias Braun0dba4e32017-05-31 01:21:30 +0000730 const MachineRegisterInfo &MRI = MF.getRegInfo();
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000731 if (!LoRegsToSave.none()) {
Diana Picus4f8c3e12017-01-13 09:37:56 +0000732 MachineInstrBuilder MIB =
733 BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000734 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000735 if (LoRegsToSave[Reg]) {
Matthias Braun0dba4e32017-05-31 01:21:30 +0000736 bool isKill = !MRI.isLiveIn(Reg);
737 if (isKill && !MRI.isReserved(Reg))
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000738 MBB.addLiveIn(Reg);
739
740 MIB.addReg(Reg, getKillRegState(isKill));
741 }
742 }
743 MIB.setMIFlags(MachineInstr::FrameSetup);
744 }
745
746 // Push the high registers. There are no store instructions that can access
747 // these registers directly, so we have to move them to low registers, and
748 // push them. This might take multiple pushes, as it is possible for there to
749 // be fewer low registers available than high registers which need saving.
750
751 // These are in reverse order so that in the case where we need to use
752 // multiple PUSH instructions, the order of the registers on the stack still
753 // matches the unwind info. They need to be swicthed back to ascending order
754 // before adding to the PUSH instruction.
755 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
756 ARM::R5, ARM::R4, ARM::R3,
757 ARM::R2, ARM::R1, ARM::R0};
758 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
759
760 const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
761 const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
762
763 // Find the first register to save.
764 const unsigned *HiRegToSave = findNextOrderedReg(
765 std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
766
767 while (HiRegToSave != AllHighRegsEnd) {
768 // Find the first low register to use.
769 const unsigned *CopyReg =
770 findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
771
772 // Create the PUSH, but don't insert it yet (the MOVs need to come first).
Diana Picus4f8c3e12017-01-13 09:37:56 +0000773 MachineInstrBuilder PushMIB =
774 BuildMI(MF, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000775
776 SmallVector<unsigned, 4> RegsToPush;
777 while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000778 if (HiRegsToSave[*HiRegToSave]) {
Matthias Braun0dba4e32017-05-31 01:21:30 +0000779 bool isKill = !MRI.isLiveIn(*HiRegToSave);
780 if (isKill && !MRI.isReserved(*HiRegToSave))
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000781 MBB.addLiveIn(*HiRegToSave);
782
783 // Emit a MOV from the high reg to the low reg.
Diana Picus4f8c3e12017-01-13 09:37:56 +0000784 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
785 .addReg(*CopyReg, RegState::Define)
786 .addReg(*HiRegToSave, getKillRegState(isKill))
787 .add(predOps(ARMCC::AL));
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000788
789 // Record the register that must be added to the PUSH.
790 RegsToPush.push_back(*CopyReg);
791
792 CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
793 HiRegToSave =
794 findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
795 }
796 }
797
798 // Add the low registers to the PUSH, in ascending order.
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +0000799 for (unsigned Reg : llvm::reverse(RegsToPush))
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000800 PushMIB.addReg(Reg, RegState::Kill);
801
802 // Insert the PUSH instruction after the MOVs.
803 MBB.insert(MI, PushMIB);
804 }
805
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000806 return true;
807}
808
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000809bool Thumb1FrameLowering::
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000810restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
811 MachineBasicBlock::iterator MI,
Krzysztof Parzyszekbea30c62017-08-10 16:17:32 +0000812 std::vector<CalleeSavedInfo> &CSI,
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000813 const TargetRegisterInfo *TRI) const {
814 if (CSI.empty())
815 return false;
816
817 MachineFunction &MF = *MBB.getParent();
818 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Eric Christopher1b21f002015-01-29 00:19:33 +0000819 const TargetInstrInfo &TII = *STI.getInstrInfo();
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000820 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
821 MF.getSubtarget().getRegisterInfo());
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000822
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000823 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
Quentin Colombet48b77202015-07-22 16:34:37 +0000824 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000825
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000826 ARMRegSet LoRegsToRestore;
827 ARMRegSet HiRegsToRestore;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000828 // Low registers (r0-r7) which can be used to restore the high registers.
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000829 ARMRegSet CopyRegs;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000830
831 for (CalleeSavedInfo I : CSI) {
832 unsigned Reg = I.getReg();
833
834 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000835 LoRegsToRestore[Reg] = true;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000836 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000837 HiRegsToRestore[Reg] = true;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000838 } else {
839 llvm_unreachable("callee-saved register of unexpected class");
840 }
841
842 // If this is a low register not used as the frame pointer, we may want to
843 // use it for restoring the high registers.
844 if ((ARM::tGPRRegClass.contains(Reg)) &&
845 !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000846 CopyRegs[Reg] = true;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000847 }
848
849 // If this is a return block, we may be able to use some unused return value
850 // registers for restoring the high regs.
851 auto Terminator = MBB.getFirstTerminator();
852 if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000853 CopyRegs[ARM::R0] = true;
854 CopyRegs[ARM::R1] = true;
855 CopyRegs[ARM::R2] = true;
856 CopyRegs[ARM::R3] = true;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000857 for (auto Op : Terminator->implicit_operands()) {
858 if (Op.isReg())
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000859 CopyRegs[Op.getReg()] = false;
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000860 }
861 }
862
863 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
864 ARM::R4, ARM::R5, ARM::R6, ARM::R7};
865 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
866
867 const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
868 const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
869
870 // Find the first register to restore.
871 auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
872 HiRegsToRestore, AllHighRegsEnd);
873
874 while (HiRegToRestore != AllHighRegsEnd) {
Benjamin Kramer79d53fe2017-08-30 22:28:30 +0000875 assert(!CopyRegs.none());
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000876 // Find the first low register to use.
877 auto CopyReg =
878 findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
879
880 // Create the POP instruction.
Diana Picus4f8c3e12017-01-13 09:37:56 +0000881 MachineInstrBuilder PopMIB =
882 BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000883
884 while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
885 // Add the low register to the POP.
886 PopMIB.addReg(*CopyReg, RegState::Define);
887
888 // Create the MOV from low to high register.
Diana Picus4f8c3e12017-01-13 09:37:56 +0000889 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
890 .addReg(*HiRegToRestore, RegState::Define)
891 .addReg(*CopyReg, RegState::Kill)
892 .add(predOps(ARMCC::AL));
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000893
894 CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
895 HiRegToRestore =
896 findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
897 }
898 }
899
Diana Picus4f8c3e12017-01-13 09:37:56 +0000900 MachineInstrBuilder MIB =
901 BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000902
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000903 bool NeedsPop = false;
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000904 for (unsigned i = CSI.size(); i != 0; --i) {
Matthias Braun51687912017-09-28 23:12:06 +0000905 CalleeSavedInfo &Info = CSI[i-1];
906 unsigned Reg = Info.getReg();
Reid Klecknerbdfc05f2016-10-11 21:14:03 +0000907
908 // High registers (excluding lr) have already been dealt with
909 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
910 continue;
911
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000912 if (Reg == ARM::LR) {
Matthias Braun51687912017-09-28 23:12:06 +0000913 Info.setRestored(false);
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000914 if (MBB.succ_empty()) {
915 // Special epilogue for vararg functions. See emitEpilogue
916 if (isVarArg)
917 continue;
918 // ARMv4T requires BX, see emitEpilogue
919 if (!STI.hasV5TOps())
920 continue;
Sanne Woudaa9941852017-02-03 11:15:53 +0000921 // Tailcall optimization failed; change TCRETURN to a tBL
922 if (MI->getOpcode() == ARM::TCRETURNdi ||
923 MI->getOpcode() == ARM::TCRETURNri) {
924 unsigned Opcode = MI->getOpcode() == ARM::TCRETURNdi
925 ? ARM::tBL : ARM::tBLXr;
926 MachineInstrBuilder BL = BuildMI(MF, DL, TII.get(Opcode));
927 BL.add(predOps(ARMCC::AL));
928 BL.add(MI->getOperand(0));
929 MBB.insert(MI, &*BL);
930 }
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000931 Reg = ARM::PC;
932 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
933 if (MI != MBB.end())
Duncan P. N. Exon Smithfd8cc232016-02-27 20:01:33 +0000934 MIB.copyImplicitOps(*MI);
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000935 MI = MBB.erase(MI);
936 } else
937 // LR may only be popped into PC, as part of return sequence.
938 // If this isn't the return sequence, we'll need emitPopSpecialFixUp
939 // to restore LR the hard way.
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000940 continue;
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000941 }
942 MIB.addReg(Reg, getDefRegState(true));
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000943 NeedsPop = true;
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000944 }
945
946 // It's illegal to emit pop instruction without operands.
Artyom Skrobov2aca0c62015-12-28 21:40:45 +0000947 if (NeedsPop)
Anton Korobeynikovd08fbd12010-11-27 23:05:03 +0000948 MBB.insert(MI, &*MIB);
949 else
950 MF.DeleteMachineInstr(MIB);
951
952 return true;
953}