Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / d80f7d34dec2c02c949bd3e4761d7b7a77e2be8b / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 8935f90ac27f832cd0e8642dfe874a373c1c406c [file] [log] [blame]
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1// Bitcasts between 512-bit vector types. Return the original type since
2// no instruction is needed for the conversion
3let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
17
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
48
49// Bitcasts between 256-bit vector types. Return the original type since
50// no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
81}
82
83//
84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
85//
86
87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
91}
92
93def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
97
98//===----------------------------------------------------------------------===//
99// AVX-512 - VECTOR INSERT
100//
101// -- 32x8 form --
102let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
107let mayLoad = 1 in
108def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
112}
113
114// -- 64x4 fp form --
115let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
120let mayLoad = 1 in
121def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
125}
126// -- 32x4 integer form --
127let neverHasSideEffects = 1 in {
128def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
132let mayLoad = 1 in
133def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
137
138}
139
140let neverHasSideEffects = 1 in {
141// -- 64x4 form --
142def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
146let mayLoad = 1 in
147def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
151}
152
153def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
165
166def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179
180def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
192
193def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206
207// vinsertps - insert f32 to XMM
208def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212 EVEX_4V;
213def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
219
220//===----------------------------------------------------------------------===//
221// AVX-512 VECTOR EXTRACT
222//---
223let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
224// -- 32x4 form --
225def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
233
234// -- 64x4 form --
235def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
239let mayStore = 1 in
240def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
244}
245
246let neverHasSideEffects = 1 in {
247// -- 32x4 form --
248def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
256
257// -- 64x4 form --
258def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
262let mayStore = 1 in
263def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
267}
268
269def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
272
273def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
276
277def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
280
281def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
284
285
286def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
289
290def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
293
294def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
297
298def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
301
302// A 256-bit subvector extract from the first 512-bit vector position
303// is a subregister copy that needs no instruction.
304def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
312
313// zmm -> xmm
314def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
322
323
324// A 128-bit subvector insert to the first 512-bit vector position
325// is a subregister copy that needs no instruction.
326def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
329 sub_ymm)>;
330def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
333 sub_ymm)>;
334def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
337 sub_ymm)>;
338def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
341 sub_ymm)>;
342
343def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
351
352// vextractps - extract 32 bits from XMM
353def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
357 EVEX;
358
359def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
363 addr:$dst)]>, EVEX;
364
365//===---------------------------------------------------------------------===//
366// AVX-512 BROADCAST
367//---
368multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
373 []>, EVEX;
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
376}
377let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
379 VR128X, f32mem>,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
381}
382
383let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
385 VR128X, f64mem>,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
387}
388
389def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
393
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]394def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
398
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]399multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
409}
410
411defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
413 VEX_W;
414
415def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
417
418def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
420
421def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
424 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]425def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
426 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]427
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]428def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
429 (VPBROADCASTDrZrr GR32:$src)>;
430def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
431 (VPBROADCASTQrZrr GR64:$src)>;
432
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]433multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
434 X86MemOperand x86memop, PatFrag ld_frag,
435 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
436 RegisterClass KRC> {
437 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
438 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
439 [(set DstRC:$dst,
440 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
441 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
442 VR128X:$src),
443 !strconcat(OpcodeStr,
444 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
445 [(set DstRC:$dst,
446 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
447 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]448 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]449 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
450 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
451 [(set DstRC:$dst,
452 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
453 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
454 x86memop:$src),
455 !strconcat(OpcodeStr,
456 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
457 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
458 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]459 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]460}
461
462defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
463 loadi32, VR512, v16i32, v4i32, VK16WM>,
464 EVEX_V512, EVEX_CD8<32, CD8VT1>;
465defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
466 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
467 EVEX_CD8<64, CD8VT1>;
468
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]469def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
470 (VPBROADCASTDZrr VR128X:$src)>;
471def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
472 (VPBROADCASTQZrr VR128X:$src)>;
473
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]474def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
475 (VBROADCASTSSZrr VR128X:$src)>;
476def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
477 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]478
479def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
480 (VBROADCASTSSZrr VR128X:$src)>;
481def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
482 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]483
484// Provide fallback in case the load node that is used in the patterns above
485// is used by additional users, which prevents the pattern selection.
486def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
487 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
488def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
489 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
490
491
492let Predicates = [HasAVX512] in {
493def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
494 (EXTRACT_SUBREG
495 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
496 addr:$src)), sub_ymm)>;
497}
498//===----------------------------------------------------------------------===//
499// AVX-512 BROADCAST MASK TO VECTOR REGISTER
500//---
501
502multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
503 RegisterClass DstRC, RegisterClass KRC,
504 ValueType OpVT, ValueType SrcVT> {
505def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
506 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
507 []>, EVEX;
508}
509
510defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
511 VK16, v16i32, v16i1>, EVEX_V512;
512defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
513 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
514
515//===----------------------------------------------------------------------===//
516// AVX-512 - VPERM
517//
518// -- immediate form --
519multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
520 SDNode OpNode, PatFrag mem_frag,
521 X86MemOperand x86memop, ValueType OpVT> {
522 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
523 (ins RC:$src1, i8imm:$src2),
524 !strconcat(OpcodeStr,
525 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
526 [(set RC:$dst,
527 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
528 EVEX;
529 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
530 (ins x86memop:$src1, i8imm:$src2),
531 !strconcat(OpcodeStr,
532 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
533 [(set RC:$dst,
534 (OpVT (OpNode (mem_frag addr:$src1),
535 (i8 imm:$src2))))]>, EVEX;
536}
537
538defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
539 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
540let ExeDomain = SSEPackedDouble in
541defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
542 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
543
544// -- VPERM - register form --
545multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
546 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
547
548 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
549 (ins RC:$src1, RC:$src2),
550 !strconcat(OpcodeStr,
551 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
552 [(set RC:$dst,
553 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
554
555 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
556 (ins RC:$src1, x86memop:$src2),
557 !strconcat(OpcodeStr,
558 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
559 [(set RC:$dst,
560 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
561 EVEX_4V;
562}
563
564defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
565 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
566defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
567 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
568let ExeDomain = SSEPackedSingle in
569defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
570 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
571let ExeDomain = SSEPackedDouble in
572defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
573 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
574
575// -- VPERM2I - 3 source operands form --
576multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
577 PatFrag mem_frag, X86MemOperand x86memop,
578 ValueType OpVT> {
579let Constraints = "$src1 = $dst" in {
580 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
581 (ins RC:$src1, RC:$src2, RC:$src3),
582 !strconcat(OpcodeStr,
583 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
584 [(set RC:$dst,
585 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
586 EVEX_4V;
587
588 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
589 (ins RC:$src1, RC:$src2, x86memop:$src3),
590 !strconcat(OpcodeStr,
591 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
592 [(set RC:$dst,
593 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
594 (mem_frag addr:$src3))))]>, EVEX_4V;
595 }
596}
597defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
598 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
599defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
600 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
601defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
602 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
603defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
604 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
605
606//===----------------------------------------------------------------------===//
607// AVX-512 - BLEND using mask
608//
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame^]609multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]610 RegisterClass KRC, RegisterClass RC,
611 X86MemOperand x86memop, PatFrag mem_frag,
612 SDNode OpNode, ValueType vt> {
613 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
614 (ins KRC:$mask, RC:$src1, RC:$src2),
615 !strconcat(OpcodeStr,
616 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
617 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
618 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame^]619 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
620 (ins KRC:$mask, RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]621 !strconcat(OpcodeStr,
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame^]622 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
623 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
624 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
625
626 let mayLoad = 1 in {
627 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
628 (ins KRC:$mask, RC:$src1, x86memop:$src2),
629 !strconcat(OpcodeStr,
630 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
631 []>,
632 EVEX_4V, EVEX_K;
633
634 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
635 (ins KRC:$mask, RC:$src1, x86memop:$src2),
636 !strconcat(OpcodeStr,
637 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
638 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
639 (mem_frag addr:$src2)))]>,
640 EVEX_4V, EVEX_K;
641 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]642}
643
644let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame^]645defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
646 int_x86_avx512_mskblend_ps_512,
647 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame^]651defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 int_x86_avx512_mskblend_pd_512,
653 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]654 memopv8f64, vselect, v8f64>,
655 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame^]657defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
658 int_x86_avx512_mskblend_d_512,
659 VK16WM, VR512, f512mem,
660 memopv16i32, vselect, v16i32>,
661 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]662
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame^]663defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
664 int_x86_avx512_mskblend_q_512,
665 VK8WM, VR512, f512mem,
666 memopv8i64, vselect, v8i64>,
667 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]668
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]669let Predicates = [HasAVX512] in {
670def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
671 (v8f32 VR256X:$src2))),
672 (EXTRACT_SUBREG
673 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
674 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
675 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
676
677def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
678 (v8i32 VR256X:$src2))),
679 (EXTRACT_SUBREG
680 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
681 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
682 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
683}
684
685multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
686 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
687 SDNode OpNode, ValueType vt> {
688 def rr : AVX512BI<opc, MRMSrcReg,
689 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
690 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
691 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
692 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
693 def rm : AVX512BI<opc, MRMSrcMem,
694 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
695 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
696 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
697 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
698}
699
700defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
701 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
702defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
703 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
704
705defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
706 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
707defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
708 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
709
710def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
711 (COPY_TO_REGCLASS (VPCMPGTDZrr
712 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
713 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
714
715def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
716 (COPY_TO_REGCLASS (VPCMPEQDZrr
717 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
718 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
719
720multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
721 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
722 SDNode OpNode, ValueType vt, Operand CC, string asm,
723 string asm_alt> {
724 def rri : AVX512AIi8<opc, MRMSrcReg,
725 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
726 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
727 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
728 def rmi : AVX512AIi8<opc, MRMSrcMem,
729 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
730 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
731 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
732 // Accept explicit immediate argument form instead of comparison code.
733 let neverHasSideEffects = 1 in {
734 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
735 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
736 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
737 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
738 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
739 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
740 }
741}
742
743defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
744 X86cmpm, v16i32, AVXCC,
745 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
746 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
747 EVEX_V512, EVEX_CD8<32, CD8VF>;
748defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
749 X86cmpmu, v16i32, AVXCC,
750 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
751 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
752 EVEX_V512, EVEX_CD8<32, CD8VF>;
753
754defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
755 X86cmpm, v8i64, AVXCC,
756 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
757 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
758 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
759defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
760 X86cmpmu, v8i64, AVXCC,
761 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
762 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
763 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
764
765// avx512_cmp_packed - sse 1 & 2 compare packed instructions
766multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
767 X86MemOperand x86memop, Operand CC,
768 SDNode OpNode, ValueType vt, string asm,
769 string asm_alt, Domain d> {
770 def rri : AVX512PIi8<0xC2, MRMSrcReg,
771 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
772 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
773 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
774 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
775 [(set KRC:$dst,
776 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
777
778 // Accept explicit immediate argument form instead of comparison code.
779 let neverHasSideEffects = 1 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]780 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]781 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]782 asm_alt, [], d>;
783 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]784 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]785 asm_alt, [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]786 }
787}
788
789defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
790 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
791 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]792 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]793defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
794 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
795 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]796 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]797 EVEX_CD8<64, CD8VF>;
798
799def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
800 (COPY_TO_REGCLASS (VCMPPSZrri
801 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
802 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
803 imm:$cc), VK8)>;
804def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
805 (COPY_TO_REGCLASS (VPCMPDZrri
806 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
807 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
808 imm:$cc), VK8)>;
809def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
810 (COPY_TO_REGCLASS (VPCMPUDZrri
811 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
812 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
813 imm:$cc), VK8)>;
814
815// Mask register copy, including
816// - copy between mask registers
817// - load/store mask registers
818// - copy from GPR to mask register and vice versa
819//
820multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
821 string OpcodeStr, RegisterClass KRC,
822 ValueType vt, X86MemOperand x86memop> {
823 let neverHasSideEffects = 1 in {
824 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
825 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
826 let mayLoad = 1 in
827 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
828 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
829 [(set KRC:$dst, (vt (load addr:$src)))]>;
830 let mayStore = 1 in
831 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
832 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
833 }
834}
835
836multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
837 string OpcodeStr,
838 RegisterClass KRC, RegisterClass GRC> {
839 let neverHasSideEffects = 1 in {
840 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
841 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
842 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
844 }
845}
846
847let Predicates = [HasAVX512] in {
848 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
849 VEX, TB;
850 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
851 VEX, TB;
852}
853
854let Predicates = [HasAVX512] in {
855 // GR16 from/to 16-bit mask
856 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
857 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
858 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
859 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
860
861 // Store kreg in memory
862 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
863 (KMOVWmk addr:$dst, VK16:$src)>;
864
865 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
866 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
867}
868// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
869let Predicates = [HasAVX512] in {
870 // GR from/to 8-bit mask without native support
871 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
872 (COPY_TO_REGCLASS
873 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
874 VK8)>;
875 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
876 (EXTRACT_SUBREG
877 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
878 sub_8bit)>;
879}
880
881// Mask unary operation
882// - KNOT
883multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
884 RegisterClass KRC, SDPatternOperator OpNode> {
885 let Predicates = [HasAVX512] in
886 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
887 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
888 [(set KRC:$dst, (OpNode KRC:$src))]>;
889}
890
891multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
892 SDPatternOperator OpNode> {
893 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
894 VEX, TB;
895}
896
897defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
898
899def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
900def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
901 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
902
903// With AVX-512, 8-bit mask is promoted to 16-bit mask.
904def : Pat<(not VK8:$src),
905 (COPY_TO_REGCLASS
906 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
907
908// Mask binary operation
909// - KADD, KAND, KANDN, KOR, KXNOR, KXOR
910multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
911 RegisterClass KRC, SDPatternOperator OpNode> {
912 let Predicates = [HasAVX512] in
913 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
914 !strconcat(OpcodeStr,
915 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
916 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
917}
918
919multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
920 SDPatternOperator OpNode> {
921 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
922 VEX_4V, VEX_L, TB;
923}
924
925def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
926def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
927
928let isCommutable = 1 in {
929 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
930 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
931 let isCommutable = 0 in
932 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
933 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
934 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
935 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
936}
937
938multiclass avx512_mask_binop_int<string IntName, string InstName> {
939 let Predicates = [HasAVX512] in
940 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
941 VK16:$src1, VK16:$src2),
942 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
943}
944
945defm : avx512_mask_binop_int<"kadd", "KADD">;
946defm : avx512_mask_binop_int<"kand", "KAND">;
947defm : avx512_mask_binop_int<"kandn", "KANDN">;
948defm : avx512_mask_binop_int<"kor", "KOR">;
949defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
950defm : avx512_mask_binop_int<"kxor", "KXOR">;
951// With AVX-512, 8-bit mask is promoted to 16-bit mask.
952multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
953 let Predicates = [HasAVX512] in
954 def : Pat<(OpNode VK8:$src1, VK8:$src2),
955 (COPY_TO_REGCLASS
956 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
957 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
958}
959
960defm : avx512_binop_pat<and, KANDWrr>;
961defm : avx512_binop_pat<andn, KANDNWrr>;
962defm : avx512_binop_pat<or, KORWrr>;
963defm : avx512_binop_pat<xnor, KXNORWrr>;
964defm : avx512_binop_pat<xor, KXORWrr>;
965
966// Mask unpacking
967multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
968 RegisterClass KRC1, RegisterClass KRC2> {
969 let Predicates = [HasAVX512] in
970 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
971 !strconcat(OpcodeStr,
972 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
973}
974
975multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
976 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
977 VEX_4V, VEX_L, OpSize, TB;
978}
979
980defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
981
982multiclass avx512_mask_unpck_int<string IntName, string InstName> {
983 let Predicates = [HasAVX512] in
984 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
985 VK8:$src1, VK8:$src2),
986 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
987}
988
989defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
990// Mask bit testing
991multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
992 SDNode OpNode> {
993 let Predicates = [HasAVX512], Defs = [EFLAGS] in
994 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
995 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
996 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
997}
998
999multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1000 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1001 VEX, TB;
1002}
1003
1004defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1005defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
1006
1007// Mask shift
1008multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1009 SDNode OpNode> {
1010 let Predicates = [HasAVX512] in
1011 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1012 !strconcat(OpcodeStr,
1013 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1014 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1015}
1016
1017multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1018 SDNode OpNode> {
1019 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1020 VEX, OpSize, TA, VEX_W;
1021}
1022
1023defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
1024defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
1025
1026// Mask setting all 0s or 1s
1027multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1028 let Predicates = [HasAVX512] in
1029 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1030 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1031 [(set KRC:$dst, (VT Val))]>;
1032}
1033
1034multiclass avx512_mask_setop_w<PatFrag Val> {
1035 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1036 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1037}
1038
1039defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1040defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1041
1042// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1043let Predicates = [HasAVX512] in {
1044 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1045 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1046}
1047def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1048 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1049
1050def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1051 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1052
1053def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1054 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1055
1056//===----------------------------------------------------------------------===//
1057// AVX-512 - Aligned and unaligned load and store
1058//
1059
1060multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1061 X86MemOperand x86memop, PatFrag ld_frag,
1062 string asm, Domain d> {
1063let neverHasSideEffects = 1 in
1064 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1065 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1066 EVEX;
1067let canFoldAsLoad = 1 in
1068 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1069 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1070 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1071let Constraints = "$src1 = $dst" in {
1072 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1073 (ins RC:$src1, KRC:$mask, RC:$src2),
1074 !strconcat(asm,
1075 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1076 EVEX, EVEX_K;
1077 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1078 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1079 !strconcat(asm,
1080 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1081 [], d>, EVEX, EVEX_K;
1082}
1083}
1084
1085defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1086 "vmovaps", SSEPackedSingle>,
1087 EVEX_V512, EVEX_CD8<32, CD8VF>;
1088defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1089 "vmovapd", SSEPackedDouble>,
1090 OpSize, EVEX_V512, VEX_W,
1091 EVEX_CD8<64, CD8VF>;
1092defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1093 "vmovups", SSEPackedSingle>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1094 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1095defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1096 "vmovupd", SSEPackedDouble>,
1097 OpSize, EVEX_V512, VEX_W,
1098 EVEX_CD8<64, CD8VF>;
1099def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1100 "vmovaps\t{$src, $dst|$dst, $src}",
1101 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1102 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1103def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1104 "vmovapd\t{$src, $dst|$dst, $src}",
1105 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1106 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1107 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1108def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1109 "vmovups\t{$src, $dst|$dst, $src}",
1110 [(store (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1111 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1112def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1113 "vmovupd\t{$src, $dst|$dst, $src}",
1114 [(store (v8f64 VR512:$src), addr:$dst)],
1115 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1116 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1117
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1118let neverHasSideEffects = 1 in {
1119 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1120 (ins VR512:$src),
1121 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1122 EVEX, EVEX_V512;
1123 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1124 (ins VR512:$src),
1125 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1126 EVEX, EVEX_V512, VEX_W;
1127let mayStore = 1 in {
1128 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1129 (ins i512mem:$dst, VR512:$src),
1130 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1131 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1132 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1133 (ins i512mem:$dst, VR512:$src),
1134 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1135 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1136}
1137let mayLoad = 1 in {
1138def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1139 (ins i512mem:$src),
1140 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1141 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1142def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1143 (ins i512mem:$src),
1144 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1145 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1146}
1147}
1148
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1149// 512-bit aligned load/store
1150def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1151def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1152
1153def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1154 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1155def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1156 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1157
1158multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1159 RegisterClass RC, RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1160 PatFrag ld_frag, X86MemOperand x86memop> {
1161let neverHasSideEffects = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1162 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1163 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1164let canFoldAsLoad = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1165 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1166 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1167 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1168let mayStore = 1 in
1169 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1170 (ins x86memop:$dst, VR512:$src),
1171 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1172let Constraints = "$src1 = $dst" in {
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1173 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1174 (ins RC:$src1, KRC:$mask, RC:$src2),
1175 !strconcat(asm,
1176 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1177 EVEX, EVEX_K;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1178 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1179 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1180 !strconcat(asm,
1181 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1182 []>, EVEX, EVEX_K;
1183}
1184}
1185
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1186defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1187 memopv16i32, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1188 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1189defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1190 memopv8i64, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1191 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1192
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1193// 512-bit unaligned load/store
1194def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1195def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1196
1197def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1198 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1199def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1200 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1201
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1202let AddedComplexity = 20 in {
1203def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1204 (v16f32 VR512:$src2))),
1205 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1206def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1207 (v8f64 VR512:$src2))),
1208 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1209def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1210 (v16i32 VR512:$src2))),
1211 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1212def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1213 (v8i64 VR512:$src2))),
1214 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1215}
1216// Move Int Doubleword to Packed Double Int
1217//
1218def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1219 "vmovd{z}\t{$src, $dst|$dst, $src}",
1220 [(set VR128X:$dst,
1221 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1222 EVEX, VEX_LIG;
1223def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1224 "vmovd{z}\t{$src, $dst|$dst, $src}",
1225 [(set VR128X:$dst,
1226 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1227 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1228def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1229 "vmovq{z}\t{$src, $dst|$dst, $src}",
1230 [(set VR128X:$dst,
1231 (v2i64 (scalar_to_vector GR64:$src)))],
1232 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1233let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1234def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1235 "vmovq{z}\t{$src, $dst|$dst, $src}",
1236 [(set FR64:$dst, (bitconvert GR64:$src))],
1237 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1238def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1239 "vmovq{z}\t{$src, $dst|$dst, $src}",
1240 [(set GR64:$dst, (bitconvert FR64:$src))],
1241 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1242}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1243def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1244 "vmovq{z}\t{$src, $dst|$dst, $src}",
1245 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1246 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1247 EVEX_CD8<64, CD8VT1>;
1248
1249// Move Int Doubleword to Single Scalar
1250//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1251let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1252def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1253 "vmovd{z}\t{$src, $dst|$dst, $src}",
1254 [(set FR32X:$dst, (bitconvert GR32:$src))],
1255 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1256
1257def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1258 "vmovd{z}\t{$src, $dst|$dst, $src}",
1259 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1260 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1261}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1262
1263// Move Packed Doubleword Int to Packed Double Int
1264//
1265def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1266 "vmovd{z}\t{$src, $dst|$dst, $src}",
1267 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1268 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1269 EVEX, VEX_LIG;
1270def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1271 (ins i32mem:$dst, VR128X:$src),
1272 "vmovd{z}\t{$src, $dst|$dst, $src}",
1273 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1274 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1275 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1276
1277// Move Packed Doubleword Int first element to Doubleword Int
1278//
1279def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1280 "vmovq{z}\t{$src, $dst|$dst, $src}",
1281 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1282 (iPTR 0)))],
1283 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1284 Requires<[HasAVX512, In64BitMode]>;
1285
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1286def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1287 (ins i64mem:$dst, VR128X:$src),
1288 "vmovq{z}\t{$src, $dst|$dst, $src}",
1289 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1290 addr:$dst)], IIC_SSE_MOVDQ>,
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1291 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1292 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1293
1294// Move Scalar Single to Double Int
1295//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1296let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1297def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1298 (ins FR32X:$src),
1299 "vmovd{z}\t{$src, $dst|$dst, $src}",
1300 [(set GR32:$dst, (bitconvert FR32X:$src))],
1301 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1302def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1303 (ins i32mem:$dst, FR32X:$src),
1304 "vmovd{z}\t{$src, $dst|$dst, $src}",
1305 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1306 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1307}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1308
1309// Move Quadword Int to Packed Quadword Int
1310//
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1311def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1312 (ins i64mem:$src),
1313 "vmovq{z}\t{$src, $dst|$dst, $src}",
1314 [(set VR128X:$dst,
1315 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1316 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1317
1318//===----------------------------------------------------------------------===//
1319// AVX-512 MOVSS, MOVSD
1320//===----------------------------------------------------------------------===//
1321
1322multiclass avx512_move_scalar <string asm, RegisterClass RC,
1323 SDNode OpNode, ValueType vt,
1324 X86MemOperand x86memop, PatFrag mem_pat> {
1325 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1326 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1327 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1328 (scalar_to_vector RC:$src2))))],
1329 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1330 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1331 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1332 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1333 EVEX, VEX_LIG;
1334 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1335 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1336 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1337 EVEX, VEX_LIG;
1338}
1339
1340let ExeDomain = SSEPackedSingle in
1341defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1342 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1343
1344let ExeDomain = SSEPackedDouble in
1345defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1346 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1347
1348
1349// For the disassembler
1350let isCodeGenOnly = 1 in {
1351 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1352 (ins VR128X:$src1, FR32X:$src2),
1353 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1354 IIC_SSE_MOV_S_RR>,
1355 XS, EVEX_4V, VEX_LIG;
1356 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1357 (ins VR128X:$src1, FR64X:$src2),
1358 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1359 IIC_SSE_MOV_S_RR>,
1360 XD, EVEX_4V, VEX_LIG, VEX_W;
1361}
1362
1363let Predicates = [HasAVX512] in {
1364 let AddedComplexity = 15 in {
1365 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1366 // MOVS{S,D} to the lower bits.
1367 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1368 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1369 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1370 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1371 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1372 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1373 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1374 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1375
1376 // Move low f32 and clear high bits.
1377 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1378 (SUBREG_TO_REG (i32 0),
1379 (VMOVSSZrr (v4f32 (V_SET0)),
1380 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1381 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1382 (SUBREG_TO_REG (i32 0),
1383 (VMOVSSZrr (v4i32 (V_SET0)),
1384 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1385 }
1386
1387 let AddedComplexity = 20 in {
1388 // MOVSSrm zeros the high parts of the register; represent this
1389 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1390 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1391 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1392 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1393 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1394 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1395 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1396
1397 // MOVSDrm zeros the high parts of the register; represent this
1398 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1399 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1400 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1401 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1402 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1403 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1404 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1405 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1406 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1407 def : Pat<(v2f64 (X86vzload addr:$src)),
1408 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1409
1410 // Represent the same patterns above but in the form they appear for
1411 // 256-bit types
1412 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1413 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1414 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1415 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1416 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1417 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1418 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1419 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1420 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1421 }
1422 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1423 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1424 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1425 FR32X:$src)), sub_xmm)>;
1426 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1427 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1428 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1429 FR64X:$src)), sub_xmm)>;
1430 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1431 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1432 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1433
1434 // Move low f64 and clear high bits.
1435 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1436 (SUBREG_TO_REG (i32 0),
1437 (VMOVSDZrr (v2f64 (V_SET0)),
1438 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1439
1440 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1441 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1442 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1443
1444 // Extract and store.
1445 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1446 addr:$dst),
1447 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1448 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1449 addr:$dst),
1450 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1451
1452 // Shuffle with VMOVSS
1453 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1454 (VMOVSSZrr (v4i32 VR128X:$src1),
1455 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1456 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1457 (VMOVSSZrr (v4f32 VR128X:$src1),
1458 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1459
1460 // 256-bit variants
1461 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1462 (SUBREG_TO_REG (i32 0),
1463 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1464 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1465 sub_xmm)>;
1466 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1467 (SUBREG_TO_REG (i32 0),
1468 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1469 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1470 sub_xmm)>;
1471
1472 // Shuffle with VMOVSD
1473 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1474 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1475 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1476 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1477 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1478 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1479 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1480 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1481
1482 // 256-bit variants
1483 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1484 (SUBREG_TO_REG (i32 0),
1485 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1486 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1487 sub_xmm)>;
1488 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1489 (SUBREG_TO_REG (i32 0),
1490 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1491 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1492 sub_xmm)>;
1493
1494 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1495 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1496 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1497 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1498 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1499 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1500 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1501 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1502}
1503
1504let AddedComplexity = 15 in
1505def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1506 (ins VR128X:$src),
1507 "vmovq{z}\t{$src, $dst|$dst, $src}",
1508 [(set VR128X:$dst, (v2i64 (X86vzmovl
1509 (v2i64 VR128X:$src))))],
1510 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1511
1512let AddedComplexity = 20 in
1513def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1514 (ins i128mem:$src),
1515 "vmovq{z}\t{$src, $dst|$dst, $src}",
1516 [(set VR128X:$dst, (v2i64 (X86vzmovl
1517 (loadv2i64 addr:$src))))],
1518 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1519 EVEX_CD8<8, CD8VT8>;
1520
1521let Predicates = [HasAVX512] in {
1522 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1523 let AddedComplexity = 20 in {
1524 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1525 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1526 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1527 (VMOV64toPQIZrr GR64:$src)>;
1528 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1529 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1530
1531 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1532 (VMOVDI2PDIZrm addr:$src)>;
1533 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1534 (VMOVDI2PDIZrm addr:$src)>;
1535 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1536 (VMOVZPQILo2PQIZrm addr:$src)>;
1537 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1538 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1539 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1540
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1541 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1542 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1543 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1544 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1545 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1546 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1547 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1548}
1549
1550def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1551 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1552
1553def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1554 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1555
1556def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1557 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1558
1559def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1560 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1561
1562//===----------------------------------------------------------------------===//
1563// AVX-512 - Integer arithmetic
1564//
1565multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1566 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1567 X86MemOperand x86memop, PatFrag scalar_mfrag,
1568 X86MemOperand x86scalar_mop, string BrdcstStr,
1569 OpndItins itins, bit IsCommutable = 0> {
1570 let isCommutable = IsCommutable in
1571 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1572 (ins RC:$src1, RC:$src2),
1573 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1574 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1575 itins.rr>, EVEX_4V;
1576 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1577 (ins RC:$src1, x86memop:$src2),
1578 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1579 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1580 itins.rm>, EVEX_4V;
1581 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1582 (ins RC:$src1, x86scalar_mop:$src2),
1583 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1584 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1585 [(set RC:$dst, (OpNode RC:$src1,
1586 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1587 itins.rm>, EVEX_4V, EVEX_B;
1588}
1589multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1590 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1591 PatFrag memop_frag, X86MemOperand x86memop,
1592 OpndItins itins,
1593 bit IsCommutable = 0> {
1594 let isCommutable = IsCommutable in
1595 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1596 (ins RC:$src1, RC:$src2),
1597 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1598 []>, EVEX_4V, VEX_W;
1599 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1600 (ins RC:$src1, x86memop:$src2),
1601 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1602 []>, EVEX_4V, VEX_W;
1603}
1604
1605defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1606 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1607 EVEX_V512, EVEX_CD8<32, CD8VF>;
1608
1609defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1610 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1611 EVEX_V512, EVEX_CD8<32, CD8VF>;
1612
1613defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1614 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1615 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1616
1617defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1618 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1619 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1620
1621defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1622 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1623 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1624
1625defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1626 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1627 EVEX_V512, EVEX_CD8<64, CD8VF>;
1628
1629defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1630 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1631 EVEX_CD8<64, CD8VF>;
1632
1633def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1634 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1635
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]1636defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1637 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1638 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1639defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1640 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1641 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1642
1643defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1644 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1645 EVEX_V512, EVEX_CD8<32, CD8VF>;
1646defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1647 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1648 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1649
1650defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1651 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1652 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1653defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1654 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1655 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1656
1657defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1658 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1659 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1660defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1661 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1662 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1663
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1664//===----------------------------------------------------------------------===//
1665// AVX-512 - Unpack Instructions
1666//===----------------------------------------------------------------------===//
1667
1668multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1669 PatFrag mem_frag, RegisterClass RC,
1670 X86MemOperand x86memop, string asm,
1671 Domain d> {
1672 def rr : AVX512PI<opc, MRMSrcReg,
1673 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1674 asm, [(set RC:$dst,
1675 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1676 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1677 def rm : AVX512PI<opc, MRMSrcMem,
1678 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1679 asm, [(set RC:$dst,
1680 (vt (OpNode RC:$src1,
1681 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1682 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1683}
1684
1685defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1686 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1687 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1688defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1689 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1690 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1691defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1692 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1693 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1694defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1695 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1696 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1697
1698multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1699 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1700 X86MemOperand x86memop> {
1701 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1702 (ins RC:$src1, RC:$src2),
1703 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1704 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1705 IIC_SSE_UNPCK>, EVEX_4V;
1706 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1707 (ins RC:$src1, x86memop:$src2),
1708 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1709 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1710 (bitconvert (memop_frag addr:$src2)))))],
1711 IIC_SSE_UNPCK>, EVEX_4V;
1712}
1713defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1714 VR512, memopv16i32, i512mem>, EVEX_V512,
1715 EVEX_CD8<32, CD8VF>;
1716defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1717 VR512, memopv8i64, i512mem>, EVEX_V512,
1718 VEX_W, EVEX_CD8<64, CD8VF>;
1719defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1720 VR512, memopv16i32, i512mem>, EVEX_V512,
1721 EVEX_CD8<32, CD8VF>;
1722defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1723 VR512, memopv8i64, i512mem>, EVEX_V512,
1724 VEX_W, EVEX_CD8<64, CD8VF>;
1725//===----------------------------------------------------------------------===//
1726// AVX-512 - PSHUFD
1727//
1728
1729multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1730 SDNode OpNode, PatFrag mem_frag,
1731 X86MemOperand x86memop, ValueType OpVT> {
1732 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1733 (ins RC:$src1, i8imm:$src2),
1734 !strconcat(OpcodeStr,
1735 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1736 [(set RC:$dst,
1737 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1738 EVEX;
1739 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1740 (ins x86memop:$src1, i8imm:$src2),
1741 !strconcat(OpcodeStr,
1742 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1743 [(set RC:$dst,
1744 (OpVT (OpNode (mem_frag addr:$src1),
1745 (i8 imm:$src2))))]>, EVEX;
1746}
1747
1748defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1749 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1750
1751let ExeDomain = SSEPackedSingle in
1752defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1753 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1754 EVEX_CD8<32, CD8VF>;
1755let ExeDomain = SSEPackedDouble in
1756defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1757 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1758 VEX_W, EVEX_CD8<32, CD8VF>;
1759
1760def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1761 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1762def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1763 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1764
1765//===----------------------------------------------------------------------===//
1766// AVX-512 Logical Instructions
1767//===----------------------------------------------------------------------===//
1768
1769defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1770 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1771 EVEX_V512, EVEX_CD8<32, CD8VF>;
1772defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1773 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1774 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1775defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1776 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1777 EVEX_V512, EVEX_CD8<32, CD8VF>;
1778defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1779 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1780 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1781defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1782 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1783 EVEX_V512, EVEX_CD8<32, CD8VF>;
1784defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1785 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1786 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1787defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1788 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1789 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1790defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1791 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1792 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1793
1794//===----------------------------------------------------------------------===//
1795// AVX-512 FP arithmetic
1796//===----------------------------------------------------------------------===//
1797
1798multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1799 SizeItins itins> {
1800 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1801 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1802 EVEX_CD8<32, CD8VT1>;
1803 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1804 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1805 EVEX_CD8<64, CD8VT1>;
1806}
1807
1808let isCommutable = 1 in {
1809defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1810defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1811defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1812defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1813}
1814let isCommutable = 0 in {
1815defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1816defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1817}
1818
1819multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1820 RegisterClass RC, ValueType vt,
1821 X86MemOperand x86memop, PatFrag mem_frag,
1822 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1823 string BrdcstStr,
1824 Domain d, OpndItins itins, bit commutable> {
1825 let isCommutable = commutable in
1826 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1827 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1828 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1829 EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1830 let mayLoad = 1 in {
1831 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1832 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1833 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1834 itins.rm, d>, EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1835 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1836 (ins RC:$src1, x86scalar_mop:$src2),
1837 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1838 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1839 [(set RC:$dst, (OpNode RC:$src1,
1840 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1841 itins.rm, d>, EVEX_4V, EVEX_B, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1842 }
1843}
1844
1845defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1846 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1847 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1848
1849defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1850 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1851 SSE_ALU_ITINS_P.d, 1>,
1852 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1853
1854defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1855 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1856 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1857defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1858 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1859 SSE_ALU_ITINS_P.d, 1>,
1860 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1861
1862defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1863 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1864 SSE_ALU_ITINS_P.s, 1>,
1865 EVEX_V512, EVEX_CD8<32, CD8VF>;
1866defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1867 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1868 SSE_ALU_ITINS_P.s, 1>,
1869 EVEX_V512, EVEX_CD8<32, CD8VF>;
1870
1871defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1872 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1873 SSE_ALU_ITINS_P.d, 1>,
1874 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1875defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1876 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1877 SSE_ALU_ITINS_P.d, 1>,
1878 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1879
1880defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1881 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1882 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1883defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1884 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1885 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1886
1887defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1888 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1889 SSE_ALU_ITINS_P.d, 0>,
1890 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1891defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1892 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1893 SSE_ALU_ITINS_P.d, 0>,
1894 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1895
1896//===----------------------------------------------------------------------===//
1897// AVX-512 VPTESTM instructions
1898//===----------------------------------------------------------------------===//
1899
1900multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1901 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1902 SDNode OpNode, ValueType vt> {
1903 def rr : AVX5128I<opc, MRMSrcReg,
1904 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1905 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1906 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1907 def rm : AVX5128I<opc, MRMSrcMem,
1908 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1909 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1910 [(set KRC:$dst, (OpNode (vt RC:$src1),
1911 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1912}
1913
1914defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1915 memopv16i32, X86testm, v16i32>, EVEX_V512,
1916 EVEX_CD8<32, CD8VF>;
1917defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1918 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1919 EVEX_CD8<64, CD8VF>;
1920
1921//===----------------------------------------------------------------------===//
1922// AVX-512 Shift instructions
1923//===----------------------------------------------------------------------===//
1924multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1925 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1926 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1927 RegisterClass KRC> {
1928 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1929 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1930 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1931 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1932 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1933 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1934 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1935 !strconcat(OpcodeStr,
1936 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1937 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1938 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1939 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1940 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1941 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1942 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1943 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1944 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1945 !strconcat(OpcodeStr,
1946 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1947 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1948}
1949
1950multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1951 RegisterClass RC, ValueType vt, ValueType SrcVT,
1952 PatFrag bc_frag, RegisterClass KRC> {
1953 // src2 is always 128-bit
1954 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1955 (ins RC:$src1, VR128X:$src2),
1956 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1957 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1958 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1959 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1960 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1961 !strconcat(OpcodeStr,
1962 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1963 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1964 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1965 (ins RC:$src1, i128mem:$src2),
1966 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1967 [(set RC:$dst, (vt (OpNode RC:$src1,
1968 (bc_frag (memopv2i64 addr:$src2)))))],
1969 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1970 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1971 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1972 !strconcat(OpcodeStr,
1973 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1974 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1975}
1976
1977defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1978 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1979 EVEX_V512, EVEX_CD8<32, CD8VF>;
1980defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1981 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1982 EVEX_CD8<32, CD8VQ>;
1983
1984defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1985 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1986 EVEX_CD8<64, CD8VF>, VEX_W;
1987defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1988 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1989 EVEX_CD8<64, CD8VQ>, VEX_W;
1990
1991defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1992 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1993 EVEX_CD8<32, CD8VF>;
1994defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1995 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1996 EVEX_CD8<32, CD8VQ>;
1997
1998defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1999 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2000 EVEX_CD8<64, CD8VF>, VEX_W;
2001defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2002 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2003 EVEX_CD8<64, CD8VQ>, VEX_W;
2004
2005defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2006 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2007 EVEX_V512, EVEX_CD8<32, CD8VF>;
2008defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2009 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2010 EVEX_CD8<32, CD8VQ>;
2011
2012defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2013 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2014 EVEX_CD8<64, CD8VF>, VEX_W;
2015defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2016 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2017 EVEX_CD8<64, CD8VQ>, VEX_W;
2018
2019//===-------------------------------------------------------------------===//
2020// Variable Bit Shifts
2021//===-------------------------------------------------------------------===//
2022multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2023 RegisterClass RC, ValueType vt,
2024 X86MemOperand x86memop, PatFrag mem_frag> {
2025 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2026 (ins RC:$src1, RC:$src2),
2027 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2028 [(set RC:$dst,
2029 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2030 EVEX_4V;
2031 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2032 (ins RC:$src1, x86memop:$src2),
2033 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2034 [(set RC:$dst,
2035 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2036 EVEX_4V;
2037}
2038
2039defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2040 i512mem, memopv16i32>, EVEX_V512,
2041 EVEX_CD8<32, CD8VF>;
2042defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2043 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2044 EVEX_CD8<64, CD8VF>;
2045defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2046 i512mem, memopv16i32>, EVEX_V512,
2047 EVEX_CD8<32, CD8VF>;
2048defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2049 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2050 EVEX_CD8<64, CD8VF>;
2051defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2052 i512mem, memopv16i32>, EVEX_V512,
2053 EVEX_CD8<32, CD8VF>;
2054defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2055 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2056 EVEX_CD8<64, CD8VF>;
2057
2058//===----------------------------------------------------------------------===//
2059// AVX-512 - MOVDDUP
2060//===----------------------------------------------------------------------===//
2061
2062multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2063 X86MemOperand x86memop, PatFrag memop_frag> {
2064def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2065 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2066 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2067def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2068 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2069 [(set RC:$dst,
2070 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2071}
2072
2073defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2074 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2075def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2076 (VMOVDDUPZrm addr:$src)>;
2077
2078def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2079 (ins VR128X:$src1, VR128X:$src2),
2080 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2081 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2082 IIC_SSE_MOV_LH>, EVEX_4V;
2083def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2084 (ins VR128X:$src1, VR128X:$src2),
2085 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2086 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2087 IIC_SSE_MOV_LH>, EVEX_4V;
2088
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2089let Predicates = [HasAVX512] in {
2090 // MOVLHPS patterns
2091 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2092 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2093 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2094 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2095
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2096 // MOVHLPS patterns
2097 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2098 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2099}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2100
2101//===----------------------------------------------------------------------===//
2102// FMA - Fused Multiply Operations
2103//
2104let Constraints = "$src1 = $dst" in {
2105multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2106 RegisterClass RC, X86MemOperand x86memop,
2107 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2108 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2109 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2110 (ins RC:$src1, RC:$src2, RC:$src3),
2111 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2112 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2113
2114 let mayLoad = 1 in
2115 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2116 (ins RC:$src1, RC:$src2, x86memop:$src3),
2117 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2118 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2119 (mem_frag addr:$src3))))]>;
2120 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2121 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2122 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2123 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2124 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2125 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2126}
2127} // Constraints = "$src1 = $dst"
2128
2129let ExeDomain = SSEPackedSingle in {
2130 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2131 memopv16f32, f32mem, loadf32, "{1to16}",
2132 X86Fmadd, v16f32>, EVEX_V512,
2133 EVEX_CD8<32, CD8VF>;
2134 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2135 memopv16f32, f32mem, loadf32, "{1to16}",
2136 X86Fmsub, v16f32>, EVEX_V512,
2137 EVEX_CD8<32, CD8VF>;
2138 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2139 memopv16f32, f32mem, loadf32, "{1to16}",
2140 X86Fmaddsub, v16f32>,
2141 EVEX_V512, EVEX_CD8<32, CD8VF>;
2142 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2143 memopv16f32, f32mem, loadf32, "{1to16}",
2144 X86Fmsubadd, v16f32>,
2145 EVEX_V512, EVEX_CD8<32, CD8VF>;
2146 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2147 memopv16f32, f32mem, loadf32, "{1to16}",
2148 X86Fnmadd, v16f32>, EVEX_V512,
2149 EVEX_CD8<32, CD8VF>;
2150 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2151 memopv16f32, f32mem, loadf32, "{1to16}",
2152 X86Fnmsub, v16f32>, EVEX_V512,
2153 EVEX_CD8<32, CD8VF>;
2154}
2155let ExeDomain = SSEPackedDouble in {
2156 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2157 memopv8f64, f64mem, loadf64, "{1to8}",
2158 X86Fmadd, v8f64>, EVEX_V512,
2159 VEX_W, EVEX_CD8<64, CD8VF>;
2160 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2161 memopv8f64, f64mem, loadf64, "{1to8}",
2162 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2163 EVEX_CD8<64, CD8VF>;
2164 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2165 memopv8f64, f64mem, loadf64, "{1to8}",
2166 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2167 EVEX_CD8<64, CD8VF>;
2168 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2169 memopv8f64, f64mem, loadf64, "{1to8}",
2170 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2171 EVEX_CD8<64, CD8VF>;
2172 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2173 memopv8f64, f64mem, loadf64, "{1to8}",
2174 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2175 EVEX_CD8<64, CD8VF>;
2176 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2177 memopv8f64, f64mem, loadf64, "{1to8}",
2178 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2179 EVEX_CD8<64, CD8VF>;
2180}
2181
2182let Constraints = "$src1 = $dst" in {
2183multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2184 RegisterClass RC, X86MemOperand x86memop,
2185 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2186 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2187 let mayLoad = 1 in
2188 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2189 (ins RC:$src1, RC:$src3, x86memop:$src2),
2190 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2191 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2192 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2193 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2194 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2195 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2196 [(set RC:$dst, (OpNode RC:$src1,
2197 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2198}
2199} // Constraints = "$src1 = $dst"
2200
2201
2202let ExeDomain = SSEPackedSingle in {
2203 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2204 memopv16f32, f32mem, loadf32, "{1to16}",
2205 X86Fmadd, v16f32>, EVEX_V512,
2206 EVEX_CD8<32, CD8VF>;
2207 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2208 memopv16f32, f32mem, loadf32, "{1to16}",
2209 X86Fmsub, v16f32>, EVEX_V512,
2210 EVEX_CD8<32, CD8VF>;
2211 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2212 memopv16f32, f32mem, loadf32, "{1to16}",
2213 X86Fmaddsub, v16f32>,
2214 EVEX_V512, EVEX_CD8<32, CD8VF>;
2215 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2216 memopv16f32, f32mem, loadf32, "{1to16}",
2217 X86Fmsubadd, v16f32>,
2218 EVEX_V512, EVEX_CD8<32, CD8VF>;
2219 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2220 memopv16f32, f32mem, loadf32, "{1to16}",
2221 X86Fnmadd, v16f32>, EVEX_V512,
2222 EVEX_CD8<32, CD8VF>;
2223 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2224 memopv16f32, f32mem, loadf32, "{1to16}",
2225 X86Fnmsub, v16f32>, EVEX_V512,
2226 EVEX_CD8<32, CD8VF>;
2227}
2228let ExeDomain = SSEPackedDouble in {
2229 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2230 memopv8f64, f64mem, loadf64, "{1to8}",
2231 X86Fmadd, v8f64>, EVEX_V512,
2232 VEX_W, EVEX_CD8<64, CD8VF>;
2233 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2234 memopv8f64, f64mem, loadf64, "{1to8}",
2235 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2236 EVEX_CD8<64, CD8VF>;
2237 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2238 memopv8f64, f64mem, loadf64, "{1to8}",
2239 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2240 EVEX_CD8<64, CD8VF>;
2241 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2242 memopv8f64, f64mem, loadf64, "{1to8}",
2243 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2244 EVEX_CD8<64, CD8VF>;
2245 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2246 memopv8f64, f64mem, loadf64, "{1to8}",
2247 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2248 EVEX_CD8<64, CD8VF>;
2249 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2250 memopv8f64, f64mem, loadf64, "{1to8}",
2251 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2252 EVEX_CD8<64, CD8VF>;
2253}
2254
2255// Scalar FMA
2256let Constraints = "$src1 = $dst" in {
2257multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2258 RegisterClass RC, ValueType OpVT,
2259 X86MemOperand x86memop, Operand memop,
2260 PatFrag mem_frag> {
2261 let isCommutable = 1 in
2262 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2263 (ins RC:$src1, RC:$src2, RC:$src3),
2264 !strconcat(OpcodeStr,
2265 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2266 [(set RC:$dst,
2267 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2268 let mayLoad = 1 in
2269 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2270 (ins RC:$src1, RC:$src2, f128mem:$src3),
2271 !strconcat(OpcodeStr,
2272 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2273 [(set RC:$dst,
2274 (OpVT (OpNode RC:$src2, RC:$src1,
2275 (mem_frag addr:$src3))))]>;
2276}
2277
2278} // Constraints = "$src1 = $dst"
2279
2280defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2281 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2282defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2283 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2284defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2285 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2286defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2287 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2288defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2289 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2290defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2291 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2292defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2293 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2294defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2295 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2296
2297//===----------------------------------------------------------------------===//
2298// AVX-512 Scalar convert from sign integer to float/double
2299//===----------------------------------------------------------------------===//
2300
2301multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2302 X86MemOperand x86memop, string asm> {
2303let neverHasSideEffects = 1 in {
2304 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2305 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2306 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2307 let mayLoad = 1 in
2308 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2309 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2310 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2311 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2312} // neverHasSideEffects = 1
2313}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2314let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2315defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2316 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2317defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2318 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2319defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2320 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2321defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2322 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2323
2324def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2325 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2326def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2327 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2328def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2329 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2330def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2331 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2332
2333def : Pat<(f32 (sint_to_fp GR32:$src)),
2334 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2335def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2336 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2337def : Pat<(f64 (sint_to_fp GR32:$src)),
2338 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2339def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2340 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2341
2342defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2343 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2344defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2345 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2346defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2347 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2348defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2349 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2350
2351def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2352 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2353def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2354 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2355def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2356 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2357def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2358 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2359
2360def : Pat<(f32 (uint_to_fp GR32:$src)),
2361 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2362def : Pat<(f32 (uint_to_fp GR64:$src)),
2363 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2364def : Pat<(f64 (uint_to_fp GR32:$src)),
2365 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2366def : Pat<(f64 (uint_to_fp GR64:$src)),
2367 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2368}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2369
2370//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2371// AVX-512 Scalar convert from float/double to integer
2372//===----------------------------------------------------------------------===//
2373multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2374 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2375 string asm> {
2376let neverHasSideEffects = 1 in {
2377 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2378 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2379 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2380 let mayLoad = 1 in
2381 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2382 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2383} // neverHasSideEffects = 1
2384}
2385let Predicates = [HasAVX512] in {
2386// Convert float/double to signed/unsigned int 32/64
2387defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2388 ssmem, sse_load_f32, "cvtss2si{z}">,
2389 XS, EVEX_CD8<32, CD8VT1>;
2390defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2391 ssmem, sse_load_f32, "cvtss2si{z}">,
2392 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2393defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2394 ssmem, sse_load_f32, "cvtss2usi{z}">,
2395 XS, EVEX_CD8<32, CD8VT1>;
2396defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2397 int_x86_avx512_cvtss2usi64, ssmem,
2398 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2399 EVEX_CD8<32, CD8VT1>;
2400defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2401 sdmem, sse_load_f64, "cvtsd2si{z}">,
2402 XD, EVEX_CD8<64, CD8VT1>;
2403defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2404 sdmem, sse_load_f64, "cvtsd2si{z}">,
2405 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2406defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2407 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2408 XD, EVEX_CD8<64, CD8VT1>;
2409defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2410 int_x86_avx512_cvtsd2usi64, sdmem,
2411 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2412 EVEX_CD8<64, CD8VT1>;
2413
2414defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2415 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2416 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2417defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2418 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2419 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2420defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2421 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2422 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2423defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2424 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2425 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2426
2427defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2428 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2429 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2430defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2431 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2432 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2433defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2434 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2435 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2436defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2437 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2438 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2439
2440// Convert float/double to signed/unsigned int 32/64 with truncation
2441defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2442 ssmem, sse_load_f32, "cvttss2si{z}">,
2443 XS, EVEX_CD8<32, CD8VT1>;
2444defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2445 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2446 "cvttss2si{z}">, XS, VEX_W,
2447 EVEX_CD8<32, CD8VT1>;
2448defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2449 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2450 EVEX_CD8<64, CD8VT1>;
2451defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2452 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2453 "cvttsd2si{z}">, XD, VEX_W,
2454 EVEX_CD8<64, CD8VT1>;
2455defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2456 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2457 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2458defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2459 int_x86_avx512_cvttss2usi64, ssmem,
2460 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2461 EVEX_CD8<32, CD8VT1>;
2462defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2463 int_x86_avx512_cvttsd2usi,
2464 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2465 EVEX_CD8<64, CD8VT1>;
2466defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2467 int_x86_avx512_cvttsd2usi64, sdmem,
2468 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2469 EVEX_CD8<64, CD8VT1>;
2470}
2471
2472multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2473 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2474 string asm> {
2475 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2476 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2477 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2478 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2479 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2480 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2481}
2482
2483defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2484 loadf32, "cvttss2si{z}">, XS,
2485 EVEX_CD8<32, CD8VT1>;
2486defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2487 loadf32, "cvttss2usi{z}">, XS,
2488 EVEX_CD8<32, CD8VT1>;
2489defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2490 loadf32, "cvttss2si{z}">, XS, VEX_W,
2491 EVEX_CD8<32, CD8VT1>;
2492defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2493 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2494 EVEX_CD8<32, CD8VT1>;
2495defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2496 loadf64, "cvttsd2si{z}">, XD,
2497 EVEX_CD8<64, CD8VT1>;
2498defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2499 loadf64, "cvttsd2usi{z}">, XD,
2500 EVEX_CD8<64, CD8VT1>;
2501defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2502 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2503 EVEX_CD8<64, CD8VT1>;
2504defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2505 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2506 EVEX_CD8<64, CD8VT1>;
2507//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2508// AVX-512 Convert form float to double and back
2509//===----------------------------------------------------------------------===//
2510let neverHasSideEffects = 1 in {
2511def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2512 (ins FR32X:$src1, FR32X:$src2),
2513 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2514 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2515let mayLoad = 1 in
2516def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2517 (ins FR32X:$src1, f32mem:$src2),
2518 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2519 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2520 EVEX_CD8<32, CD8VT1>;
2521
2522// Convert scalar double to scalar single
2523def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2524 (ins FR64X:$src1, FR64X:$src2),
2525 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2526 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2527let mayLoad = 1 in
2528def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2529 (ins FR64X:$src1, f64mem:$src2),
2530 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2531 []>, EVEX_4V, VEX_LIG, VEX_W,
2532 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2533}
2534
2535def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2536 Requires<[HasAVX512]>;
2537def : Pat<(fextend (loadf32 addr:$src)),
2538 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2539
2540def : Pat<(extloadf32 addr:$src),
2541 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2542 Requires<[HasAVX512, OptForSize]>;
2543
2544def : Pat<(extloadf32 addr:$src),
2545 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2546 Requires<[HasAVX512, OptForSpeed]>;
2547
2548def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2549 Requires<[HasAVX512]>;
2550
2551multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2552 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2553 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2554 Domain d> {
2555let neverHasSideEffects = 1 in {
2556 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2557 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2558 [(set DstRC:$dst,
2559 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2560 let mayLoad = 1 in
2561 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2562 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2563 [(set DstRC:$dst,
2564 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2565} // neverHasSideEffects = 1
2566}
2567
2568defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2569 memopv8f64, f512mem, v8f32, v8f64,
2570 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2571 EVEX_CD8<64, CD8VF>;
2572
2573defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2574 memopv4f64, f256mem, v8f64, v8f32,
2575 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2576def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2577 (VCVTPS2PDZrm addr:$src)>;
2578
2579//===----------------------------------------------------------------------===//
2580// AVX-512 Vector convert from sign integer to float/double
2581//===----------------------------------------------------------------------===//
2582
2583defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2584 memopv8i64, i512mem, v16f32, v16i32,
2585 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2586
2587defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2588 memopv4i64, i256mem, v8f64, v8i32,
2589 SSEPackedDouble>, EVEX_V512, XS,
2590 EVEX_CD8<32, CD8VH>;
2591
2592defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2593 memopv16f32, f512mem, v16i32, v16f32,
2594 SSEPackedSingle>, EVEX_V512, XS,
2595 EVEX_CD8<32, CD8VF>;
2596
2597defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2598 memopv8f64, f512mem, v8i32, v8f64,
2599 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2600 EVEX_CD8<64, CD8VF>;
2601
2602defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2603 memopv16f32, f512mem, v16i32, v16f32,
2604 SSEPackedSingle>, EVEX_V512,
2605 EVEX_CD8<32, CD8VF>;
2606
2607defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2608 memopv8f64, f512mem, v8i32, v8f64,
2609 SSEPackedDouble>, EVEX_V512, VEX_W,
2610 EVEX_CD8<64, CD8VF>;
2611
2612defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2613 memopv4i64, f256mem, v8f64, v8i32,
2614 SSEPackedDouble>, EVEX_V512, XS,
2615 EVEX_CD8<32, CD8VH>;
2616
2617defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2618 memopv16i32, f512mem, v16f32, v16i32,
2619 SSEPackedSingle>, EVEX_V512, XD,
2620 EVEX_CD8<32, CD8VF>;
2621
2622def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2623 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2624 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2625
2626
2627def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2628 (VCVTDQ2PSZrr VR512:$src)>;
2629def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2630 (VCVTDQ2PSZrm addr:$src)>;
2631
2632def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2633 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2634 [(set VR512:$dst,
2635 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2636 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2637def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2638 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2639 [(set VR512:$dst,
2640 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2641 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2642
2643
2644let Predicates = [HasAVX512] in {
2645 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2646 (VCVTPD2PSZrm addr:$src)>;
2647 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2648 (VCVTPS2PDZrm addr:$src)>;
2649}
2650
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]2651//===----------------------------------------------------------------------===//
2652// Half precision conversion instructions
2653//===----------------------------------------------------------------------===//
2654multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2655 X86MemOperand x86memop, Intrinsic Int> {
2656 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2657 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2658 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2659 let neverHasSideEffects = 1, mayLoad = 1 in
2660 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2661 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2662}
2663
2664multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2665 X86MemOperand x86memop, Intrinsic Int> {
2666 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2667 (ins srcRC:$src1, i32i8imm:$src2),
2668 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2669 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2670 let neverHasSideEffects = 1, mayStore = 1 in
2671 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2672 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2673 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2674}
2675
2676defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2677 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2678 EVEX_CD8<32, CD8VH>;
2679defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2680 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2681 EVEX_CD8<32, CD8VH>;
2682
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2683let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2684 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2685 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2686 EVEX_CD8<32, CD8VT1>;
2687 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2688 "ucomisd{z}">, TB, OpSize, EVEX,
2689 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2690 let Pattern = []<dag> in {
2691 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2692 "comiss{z}">, TB, EVEX, VEX_LIG,
2693 EVEX_CD8<32, CD8VT1>;
2694 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2695 "comisd{z}">, TB, OpSize, EVEX,
2696 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2697 }
2698 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2699 load, "ucomiss">, TB, EVEX, VEX_LIG,
2700 EVEX_CD8<32, CD8VT1>;
2701 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2702 load, "ucomisd">, TB, OpSize, EVEX,
2703 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2704
2705 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2706 load, "comiss">, TB, EVEX, VEX_LIG,
2707 EVEX_CD8<32, CD8VT1>;
2708 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2709 load, "comisd">, TB, OpSize, EVEX,
2710 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2711}
2712
2713/// avx512_unop_p - AVX-512 unops in packed form.
2714multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2715 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2716 !strconcat(OpcodeStr,
2717 "ps\t{$src, $dst|$dst, $src}"),
2718 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2719 EVEX, EVEX_V512;
2720 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2721 !strconcat(OpcodeStr,
2722 "ps\t{$src, $dst|$dst, $src}"),
2723 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2724 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2725 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2726 !strconcat(OpcodeStr,
2727 "pd\t{$src, $dst|$dst, $src}"),
2728 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2729 EVEX, EVEX_V512, VEX_W;
2730 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2731 !strconcat(OpcodeStr,
2732 "pd\t{$src, $dst|$dst, $src}"),
2733 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2734 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2735}
2736
2737/// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2738multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2739 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2740 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2741 !strconcat(OpcodeStr,
2742 "ps\t{$src, $dst|$dst, $src}"),
2743 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2744 EVEX, EVEX_V512;
2745 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2746 !strconcat(OpcodeStr,
2747 "ps\t{$src, $dst|$dst, $src}"),
2748 [(set VR512:$dst,
2749 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2750 EVEX_V512, EVEX_CD8<32, CD8VF>;
2751 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2752 !strconcat(OpcodeStr,
2753 "pd\t{$src, $dst|$dst, $src}"),
2754 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2755 EVEX, EVEX_V512, VEX_W;
2756 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2757 !strconcat(OpcodeStr,
2758 "pd\t{$src, $dst|$dst, $src}"),
2759 [(set VR512:$dst,
2760 (V8F64Int (memopv8f64 addr:$src)))]>,
2761 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2762}
2763
2764/// avx512_fp_unop_s - AVX-512 unops in scalar form.
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2765multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2766 let hasSideEffects = 0 in {
2767 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2768 (ins FR32X:$src1, FR32X:$src2),
2769 !strconcat(OpcodeStr,
2770 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2771 []>, EVEX_4V;
2772 let mayLoad = 1 in {
2773 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2774 (ins FR32X:$src1, f32mem:$src2),
2775 !strconcat(OpcodeStr,
2776 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2777 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2778 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2779 (ins VR128X:$src1, ssmem:$src2),
2780 !strconcat(OpcodeStr,
2781 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2782 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2783 }
2784 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2785 (ins FR64X:$src1, FR64X:$src2),
2786 !strconcat(OpcodeStr,
2787 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2788 EVEX_4V, VEX_W;
2789 let mayLoad = 1 in {
2790 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2791 (ins FR64X:$src1, f64mem:$src2),
2792 !strconcat(OpcodeStr,
2793 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2794 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2795 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2796 (ins VR128X:$src1, sdmem:$src2),
2797 !strconcat(OpcodeStr,
2798 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2799 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2800 }
2801}
2802}
2803
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2804defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2805 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2806 avx512_fp_unop_p_int<0x4C, "vrcp14",
2807 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2808
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2809defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2810 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2811 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2812 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2813
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2814def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2815 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2816 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2817 VR128X)>;
2818def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2819 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2820
2821def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2822 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2823 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2824 VR128X)>;
2825def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2826 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2827
2828let AddedComplexity = 20, Predicates = [HasERI] in {
2829defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2830 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2831 avx512_fp_unop_p_int<0xCA, "vrcp28",
2832 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2833
2834defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2835 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2836 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2837 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2838}
2839
2840let Predicates = [HasERI] in {
2841 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2842 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2843 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2844 VR128X)>;
2845 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2846 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2847
2848 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2849 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2850 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2851 VR128X)>;
2852 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2853 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2854}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2855multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2856 Intrinsic V16F32Int, Intrinsic V8F64Int,
2857 OpndItins itins_s, OpndItins itins_d> {
2858 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2859 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2860 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2861 EVEX, EVEX_V512;
2862
2863 let mayLoad = 1 in
2864 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2866 [(set VR512:$dst,
2867 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2868 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2869
2870 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2871 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2872 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2873 EVEX, EVEX_V512;
2874
2875 let mayLoad = 1 in
2876 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2877 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2878 [(set VR512:$dst, (OpNode
2879 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2880 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2881
2882 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2883 !strconcat(OpcodeStr,
2884 "ps\t{$src, $dst|$dst, $src}"),
2885 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2886 EVEX, EVEX_V512;
2887 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2888 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2889 [(set VR512:$dst,
2890 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2891 EVEX_V512, EVEX_CD8<32, CD8VF>;
2892 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2893 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2894 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2895 EVEX, EVEX_V512, VEX_W;
2896 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2897 !strconcat(OpcodeStr,
2898 "pd\t{$src, $dst|$dst, $src}"),
2899 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2900 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2901}
2902
2903multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2904 Intrinsic F32Int, Intrinsic F64Int,
2905 OpndItins itins_s, OpndItins itins_d> {
2906 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2907 (ins FR32X:$src1, FR32X:$src2),
2908 !strconcat(OpcodeStr,
2909 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2910 [], itins_s.rr>, XS, EVEX_4V;
2911 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2912 (ins VR128X:$src1, VR128X:$src2),
2913 !strconcat(OpcodeStr,
2914 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2915 [(set VR128X:$dst,
2916 (F32Int VR128X:$src1, VR128X:$src2))],
2917 itins_s.rr>, XS, EVEX_4V;
2918 let mayLoad = 1 in {
2919 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2920 (ins FR32X:$src1, f32mem:$src2),
2921 !strconcat(OpcodeStr,
2922 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2923 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2924 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2925 (ins VR128X:$src1, ssmem:$src2),
2926 !strconcat(OpcodeStr,
2927 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2928 [(set VR128X:$dst,
2929 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2930 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2931 }
2932 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2933 (ins FR64X:$src1, FR64X:$src2),
2934 !strconcat(OpcodeStr,
2935 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2936 XD, EVEX_4V, VEX_W;
2937 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2938 (ins VR128X:$src1, VR128X:$src2),
2939 !strconcat(OpcodeStr,
2940 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2941 [(set VR128X:$dst,
2942 (F64Int VR128X:$src1, VR128X:$src2))],
2943 itins_s.rr>, XD, EVEX_4V, VEX_W;
2944 let mayLoad = 1 in {
2945 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2946 (ins FR64X:$src1, f64mem:$src2),
2947 !strconcat(OpcodeStr,
2948 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2949 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2950 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2951 (ins VR128X:$src1, sdmem:$src2),
2952 !strconcat(OpcodeStr,
2953 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2954 [(set VR128X:$dst,
2955 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2956 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2957 }
2958}
2959
2960
2961defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2962 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2963 SSE_SQRTSS, SSE_SQRTSD>,
2964 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2965 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2966 SSE_SQRTPS, SSE_SQRTPD>;
2967
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2968let Predicates = [HasAVX512] in {
2969 def : Pat<(f32 (fsqrt FR32X:$src)),
2970 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2971 def : Pat<(f32 (fsqrt (load addr:$src))),
2972 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2973 Requires<[OptForSize]>;
2974 def : Pat<(f64 (fsqrt FR64X:$src)),
2975 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2976 def : Pat<(f64 (fsqrt (load addr:$src))),
2977 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2978 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2979
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2980 def : Pat<(f32 (X86frsqrt FR32X:$src)),
2981 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2982 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2983 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2984 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2985
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2986 def : Pat<(f32 (X86frcp FR32X:$src)),
2987 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2988 def : Pat<(f32 (X86frcp (load addr:$src))),
2989 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2990 Requires<[OptForSize]>;
2991
2992 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
2993 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
2994 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2995 VR128X)>;
2996 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2997 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2998
2999 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3000 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3001 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3002 VR128X)>;
3003 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3004 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3005}
3006
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3007
3008multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3009 X86MemOperand x86memop, RegisterClass RC,
3010 PatFrag mem_frag32, PatFrag mem_frag64,
3011 Intrinsic V4F32Int, Intrinsic V2F64Int,
3012 CD8VForm VForm> {
3013let ExeDomain = SSEPackedSingle in {
3014 // Intrinsic operation, reg.
3015 // Vector intrinsic operation, reg
3016 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3017 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3018 !strconcat(OpcodeStr,
3019 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3020 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3021
3022 // Vector intrinsic operation, mem
3023 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3024 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3025 !strconcat(OpcodeStr,
3026 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3027 [(set RC:$dst,
3028 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3029 EVEX_CD8<32, VForm>;
3030} // ExeDomain = SSEPackedSingle
3031
3032let ExeDomain = SSEPackedDouble in {
3033 // Vector intrinsic operation, reg
3034 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3035 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3036 !strconcat(OpcodeStr,
3037 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3038 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3039
3040 // Vector intrinsic operation, mem
3041 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3042 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3043 !strconcat(OpcodeStr,
3044 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3045 [(set RC:$dst,
3046 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3047 EVEX_CD8<64, VForm>;
3048} // ExeDomain = SSEPackedDouble
3049}
3050
3051multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3052 string OpcodeStr,
3053 Intrinsic F32Int,
3054 Intrinsic F64Int> {
3055let ExeDomain = GenericDomain in {
3056 // Operation, reg.
3057 let hasSideEffects = 0 in
3058 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3059 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3060 !strconcat(OpcodeStr,
3061 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3062 []>;
3063
3064 // Intrinsic operation, reg.
3065 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3066 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3067 !strconcat(OpcodeStr,
3068 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3069 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3070
3071 // Intrinsic operation, mem.
3072 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3073 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3074 !strconcat(OpcodeStr,
3075 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3076 [(set VR128X:$dst, (F32Int VR128X:$src1,
3077 sse_load_f32:$src2, imm:$src3))]>,
3078 EVEX_CD8<32, CD8VT1>;
3079
3080 // Operation, reg.
3081 let hasSideEffects = 0 in
3082 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3083 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3084 !strconcat(OpcodeStr,
3085 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3086 []>, VEX_W;
3087
3088 // Intrinsic operation, reg.
3089 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3090 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3091 !strconcat(OpcodeStr,
3092 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3093 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3094 VEX_W;
3095
3096 // Intrinsic operation, mem.
3097 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3098 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3099 !strconcat(OpcodeStr,
3100 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3101 [(set VR128X:$dst,
3102 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3103 VEX_W, EVEX_CD8<64, CD8VT1>;
3104} // ExeDomain = GenericDomain
3105}
3106
3107let Predicates = [HasAVX512] in {
3108 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3109 int_x86_avx512_rndscale_ss,
3110 int_x86_avx512_rndscale_sd>, EVEX_4V;
3111
3112 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3113 memopv16f32, memopv8f64,
3114 int_x86_avx512_rndscale_ps_512,
3115 int_x86_avx512_rndscale_pd_512, CD8VF>,
3116 EVEX, EVEX_V512;
3117}
3118
3119def : Pat<(ffloor FR32X:$src),
3120 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3121def : Pat<(f64 (ffloor FR64X:$src)),
3122 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3123def : Pat<(f32 (fnearbyint FR32X:$src)),
3124 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3125def : Pat<(f64 (fnearbyint FR64X:$src)),
3126 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3127def : Pat<(f32 (fceil FR32X:$src)),
3128 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3129def : Pat<(f64 (fceil FR64X:$src)),
3130 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3131def : Pat<(f32 (frint FR32X:$src)),
3132 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3133def : Pat<(f64 (frint FR64X:$src)),
3134 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3135def : Pat<(f32 (ftrunc FR32X:$src)),
3136 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3137def : Pat<(f64 (ftrunc FR64X:$src)),
3138 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3139
3140def : Pat<(v16f32 (ffloor VR512:$src)),
3141 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3142def : Pat<(v16f32 (fnearbyint VR512:$src)),
3143 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3144def : Pat<(v16f32 (fceil VR512:$src)),
3145 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3146def : Pat<(v16f32 (frint VR512:$src)),
3147 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3148def : Pat<(v16f32 (ftrunc VR512:$src)),
3149 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3150
3151def : Pat<(v8f64 (ffloor VR512:$src)),
3152 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3153def : Pat<(v8f64 (fnearbyint VR512:$src)),
3154 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3155def : Pat<(v8f64 (fceil VR512:$src)),
3156 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3157def : Pat<(v8f64 (frint VR512:$src)),
3158 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3159def : Pat<(v8f64 (ftrunc VR512:$src)),
3160 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3161
3162//-------------------------------------------------
3163// Integer truncate and extend operations
3164//-------------------------------------------------
3165
3166multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3167 RegisterClass dstRC, RegisterClass srcRC,
3168 RegisterClass KRC, X86MemOperand x86memop> {
3169 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3170 (ins srcRC:$src),
3171 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3172 []>, EVEX;
3173
3174 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3175 (ins KRC:$mask, srcRC:$src),
3176 !strconcat(OpcodeStr,
3177 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3178 []>, EVEX, EVEX_KZ;
3179
3180 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3181 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3182 []>, EVEX;
3183}
3184defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3185 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3186defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3187 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3188defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3189 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3190defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3191 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3192defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3193 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3194defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3195 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3196defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3197 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3198defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3199 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3200defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3201 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3202defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3203 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3204defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3205 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3206defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3207 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3208defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3209 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3210defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3211 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3212defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3213 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3214
3215def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3216def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3217def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3218def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3219def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3220
3221def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3222 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3223def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3224 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3225def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3226 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3227def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3228 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3229
3230
3231multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3232 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3233 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3234
3235 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3236 (ins SrcRC:$src),
3237 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3238 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3239 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3240 (ins x86memop:$src),
3241 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3242 [(set DstRC:$dst,
3243 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3244 EVEX;
3245}
3246
3247defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3248 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3249 EVEX_CD8<8, CD8VQ>;
3250defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3251 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3252 EVEX_CD8<8, CD8VO>;
3253defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3254 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3255 EVEX_CD8<16, CD8VH>;
3256defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3257 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3258 EVEX_CD8<16, CD8VQ>;
3259defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3260 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3261 EVEX_CD8<32, CD8VH>;
3262
3263defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3264 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3265 EVEX_CD8<8, CD8VQ>;
3266defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3267 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3268 EVEX_CD8<8, CD8VO>;
3269defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3270 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3271 EVEX_CD8<16, CD8VH>;
3272defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3273 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3274 EVEX_CD8<16, CD8VQ>;
3275defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3276 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3277 EVEX_CD8<32, CD8VH>;
3278
3279//===----------------------------------------------------------------------===//
3280// GATHER - SCATTER Operations
3281
3282multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3283 RegisterClass RC, X86MemOperand memop> {
3284let mayLoad = 1,
3285 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3286 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3287 (ins RC:$src1, KRC:$mask, memop:$src2),
3288 !strconcat(OpcodeStr,
3289 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3290 []>, EVEX, EVEX_K;
3291}
3292defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3293 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3294defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3295 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3296
3297defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3298 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3299defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3300 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3301
3302defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3303 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3304defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3305 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3306
3307defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3308 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3309defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3310 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3311
3312multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3313 RegisterClass RC, X86MemOperand memop> {
3314let mayStore = 1, Constraints = "$mask = $mask_wb" in
3315 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3316 (ins memop:$dst, KRC:$mask, RC:$src2),
3317 !strconcat(OpcodeStr,
3318 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3319 []>, EVEX, EVEX_K;
3320}
3321
3322defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3323 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3324defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3325 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3326
3327defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3328 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3329defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3330 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3331
3332defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3333 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3334defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3335 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3336
3337defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3338 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3339defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3340 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3341
3342//===----------------------------------------------------------------------===//
3343// VSHUFPS - VSHUFPD Operations
3344
3345multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3346 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3347 Domain d> {
3348 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3349 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3350 !strconcat(OpcodeStr,
3351 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3352 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3353 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3354 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3355 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3356 (ins RC:$src1, RC:$src2, i8imm:$src3),
3357 !strconcat(OpcodeStr,
3358 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3359 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3360 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3361 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3362}
3363
3364defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3365 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3366defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3367 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3368
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]3369def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3370 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3371def : Pat<(v16i32 (X86Shufp VR512:$src1,
3372 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3373 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3374
3375def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3376 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3377def : Pat<(v8i64 (X86Shufp VR512:$src1,
3378 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3379 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3380
3381multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3382 X86MemOperand x86memop> {
3383 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3384 (ins RC:$src1, RC:$src2, i8imm:$src3),
3385 !strconcat(OpcodeStr,
3386 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3387 []>, EVEX_4V;
3388 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3389 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3390 !strconcat(OpcodeStr,
3391 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3392 []>, EVEX_4V;
3393}
3394defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3395 EVEX_V512, EVEX_CD8<32, CD8VF>;
3396defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3397 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3398
3399def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3400 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3401def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3402 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3403def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3404 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3405def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3406 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3407
3408multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3409 X86MemOperand x86memop> {
3410 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3411 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3412 EVEX;
3413 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3414 (ins x86memop:$src),
3415 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3416 EVEX;
3417}
3418
3419defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3420 EVEX_CD8<32, CD8VF>;
3421defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3422 EVEX_CD8<64, CD8VF>;
3423
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]3424multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3425 RegisterClass RC, RegisterClass KRC, PatFrag memop_frag,
3426 X86MemOperand x86memop, PatFrag scalar_mfrag,
3427 X86MemOperand x86scalar_mop, string BrdcstStr,
3428 Intrinsic Int, Intrinsic maskInt, Intrinsic maskzInt> {
3429 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3430 (ins RC:$src),
3431 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3432 [(set RC:$dst, (Int RC:$src))]>, EVEX;
3433 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3434 (ins x86memop:$src),
3435 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3436 [(set RC:$dst, (Int (memop_frag addr:$src)))]>, EVEX;
3437 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3438 (ins x86scalar_mop:$src),
3439 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3440 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3441 []>, EVEX, EVEX_B;
3442 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3443 (ins KRC:$mask, RC:$src),
3444 !strconcat(OpcodeStr,
3445 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3446 [(set RC:$dst, (maskzInt KRC:$mask, RC:$src))]>, EVEX, EVEX_KZ;
3447 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3448 (ins KRC:$mask, x86memop:$src),
3449 !strconcat(OpcodeStr,
3450 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3451 [(set RC:$dst, (maskzInt KRC:$mask, (memop_frag addr:$src)))]>,
3452 EVEX, EVEX_KZ;
3453 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3454 (ins KRC:$mask, x86scalar_mop:$src),
3455 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3456 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3457 BrdcstStr, "}"),
3458 []>, EVEX, EVEX_KZ, EVEX_B;
3459
3460 let Constraints = "$src1 = $dst" in {
3461 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3462 (ins RC:$src1, KRC:$mask, RC:$src2),
3463 !strconcat(OpcodeStr,
3464 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3465 [(set RC:$dst, (maskInt RC:$src1, KRC:$mask, RC:$src2))]>, EVEX, EVEX_K;
3466 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3467 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3468 !strconcat(OpcodeStr,
3469 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3470 [(set RC:$dst, (maskInt RC:$src1, KRC:$mask, (memop_frag addr:$src2)))]>, EVEX, EVEX_K;
3471 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3472 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3473 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3474 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3475 []>, EVEX, EVEX_K, EVEX_B;
3476 }
3477}
3478
3479let Predicates = [HasCDI] in {
3480defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3481 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
3482 int_x86_avx512_conflict_d_512,
3483 int_x86_avx512_conflict_d_mask_512,
3484 int_x86_avx512_conflict_d_maskz_512>,
3485 EVEX_V512, EVEX_CD8<32, CD8VF>;
3486
3487defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3488 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3489 int_x86_avx512_conflict_q_512,
3490 int_x86_avx512_conflict_q_mask_512,
3491 int_x86_avx512_conflict_q_maskz_512>,
3492 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3493}