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Eugene Zelenko076468c2017-09-20 21:35:51 +00001//===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
Evan Cheng10043e22007-01-19 07:51:42 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Cheng10043e22007-01-19 07:51:42 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000015#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
Evan Cheng10043e22007-01-19 07:51:42 +000017
Craig Toppera9253262014-03-22 23:51:00 +000018#include "MCTargetDesc/ARMBaseInfo.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000019#include "llvm/ADT/SmallVector.h"
20#include "llvm/ADT/StringRef.h"
Chandler Carruth802d7552012-12-04 07:12:27 +000021#include "llvm/CodeGen/CallingConvLower.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000022#include "llvm/CodeGen/ISDOpcodes.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineValueType.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000025#include "llvm/CodeGen/SelectionDAGNodes.h"
David Blaikieb3bde2e2017-11-17 01:07:10 +000026#include "llvm/CodeGen/TargetLowering.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000027#include "llvm/CodeGen/ValueTypes.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000028#include "llvm/IR/Attributes.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000029#include "llvm/IR/CallingConv.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000030#include "llvm/IR/Function.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000031#include "llvm/IR/IRBuilder.h"
32#include "llvm/IR/InlineAsm.h"
33#include "llvm/Support/CodeGen.h"
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000034#include <utility>
Evan Cheng10043e22007-01-19 07:51:42 +000035
36namespace llvm {
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000037
38class ARMSubtarget;
Eugene Zelenko076468c2017-09-20 21:35:51 +000039class DataLayout;
40class FastISel;
41class FunctionLoweringInfo;
42class GlobalValue;
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000043class InstrItineraryData;
Eugene Zelenko076468c2017-09-20 21:35:51 +000044class Instruction;
45class MachineBasicBlock;
46class MachineInstr;
47class SelectionDAG;
48class TargetLibraryInfo;
49class TargetMachine;
50class TargetRegisterInfo;
51class VectorType;
Evan Cheng10043e22007-01-19 07:51:42 +000052
53 namespace ARMISD {
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +000054
Evan Cheng10043e22007-01-19 07:51:42 +000055 // ARM Specific DAG Nodes
Matthias Braund04893f2015-05-07 21:33:59 +000056 enum NodeType : unsigned {
Jim Grosbach91fa7812009-05-13 22:32:43 +000057 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohmaned1cf1a2008-09-23 18:42:32 +000058 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Cheng10043e22007-01-19 07:51:42 +000059
60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
61 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Chengdfce83c2011-01-17 08:03:18 +000062 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
63 // PIC mode.
Evan Cheng10043e22007-01-19 07:51:42 +000064 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach91fa7812009-05-13 22:32:43 +000065
Manman Ren9f911162012-06-01 02:44:42 +000066 // Add pseudo op to model memcpy for struct byval.
67 COPY_STRUCT_BYVAL,
68
Evan Cheng10043e22007-01-19 07:51:42 +000069 CALL, // Function call.
Evan Chengc3c949b42007-06-19 21:05:09 +000070 CALL_PRED, // Function call that's predicable.
Evan Cheng10043e22007-01-19 07:51:42 +000071 CALL_NOLINK, // Function call with branch not branch-and-link.
Evan Cheng10043e22007-01-19 07:51:42 +000072 BRCOND, // Conditional branch.
73 BR_JT, // Jumptable branch.
Evan Chengc6d70ae2009-07-29 02:18:14 +000074 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Cheng10043e22007-01-19 07:51:42 +000075 RET_FLAG, // Return with a flag operand.
Tim Northoverd8407452013-10-01 14:33:28 +000076 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
Evan Cheng10043e22007-01-19 07:51:42 +000077
78 PIC_ADD, // Add with a PC operand and a PIC label.
79
80 CMP, // ARM compare instructions.
Bill Wendling4b796472012-06-11 08:07:26 +000081 CMN, // ARM CMN instructions.
David Goodwindbf11ba2009-06-29 15:33:01 +000082 CMPZ, // ARM compare that sets only Z flag.
Evan Cheng10043e22007-01-19 07:51:42 +000083 CMPFP, // ARM VFP compare instruction, sets FPSCR.
84 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
85 FMSTAT, // ARM fmstat instruction.
Evan Chenge87681c2012-02-23 01:19:06 +000086
Evan Cheng10043e22007-01-19 07:51:42 +000087 CMOV, // ARM conditional move instructions.
Jim Grosbach91fa7812009-05-13 22:32:43 +000088
Pablo Barrio7a643462016-06-23 16:53:49 +000089 SSAT, // Signed saturation
90
Evan Cheng0cc4ad92010-07-13 19:27:42 +000091 BCC_i64,
92
Evan Cheng10043e22007-01-19 07:51:42 +000093 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
94 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
95 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach91fa7812009-05-13 22:32:43 +000096
Evan Chenge8916542011-08-30 01:34:54 +000097 ADDC, // Add with carry
98 ADDE, // Add using carry
99 SUBC, // Sub with carry
100 SUBE, // Sub using carry
101
Jim Grosbachd7cf55c2009-11-09 00:11:35 +0000102 VMOVRRD, // double to two gprs.
103 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +0000104
Jim Grosbachbbdc5d22010-10-19 23:27:08 +0000105 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
106 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Matthias Braun3cd00c12015-07-16 22:34:16 +0000107 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
Jim Grosbachaeca45d2009-05-12 23:59:14 +0000108
Dale Johannesend679ff72010-06-03 21:09:53 +0000109 TC_RETURN, // Tail call return pseudo.
110
Bob Wilson2e076c42009-06-22 23:27:02 +0000111 THREAD_POINTER,
112
Evan Chengb972e562009-08-07 00:34:42 +0000113 DYN_ALLOC, // Dynamic allocation on the stack.
114
Bob Wilson7ed59712010-10-30 00:54:37 +0000115 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Cheng8740ee32010-11-03 06:34:55 +0000116
117 PRELOAD, // Preload
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000118
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000119 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000120 WIN__DBZCHK, // Windows' divide by zero check
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000121
Bob Wilson2e076c42009-06-22 23:27:02 +0000122 VCEQ, // Vector compare equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000123 VCEQZ, // Vector compare equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000124 VCGE, // Vector compare greater than or equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000125 VCGEZ, // Vector compare greater than or equal to zero.
126 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000127 VCGEU, // Vector compare unsigned greater than or equal.
128 VCGT, // Vector compare greater than.
Owen Andersonc7baee32010-11-08 23:21:22 +0000129 VCGTZ, // Vector compare greater than zero.
130 VCLTZ, // Vector compare less than zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000131 VCGTU, // Vector compare unsigned greater than.
132 VTST, // Vector test bits.
133
134 // Vector shift by immediate:
135 VSHL, // ...left
136 VSHRs, // ...right (signed)
137 VSHRu, // ...right (unsigned)
Bob Wilson2e076c42009-06-22 23:27:02 +0000138
139 // Vector rounding shift by immediate:
140 VRSHRs, // ...right (signed)
141 VRSHRu, // ...right (unsigned)
142 VRSHRN, // ...right narrow
143
144 // Vector saturating shift by immediate:
145 VQSHLs, // ...left (signed)
146 VQSHLu, // ...left (unsigned)
147 VQSHLsu, // ...left (signed to unsigned)
148 VQSHRNs, // ...right narrow (signed)
149 VQSHRNu, // ...right narrow (unsigned)
150 VQSHRNsu, // ...right narrow (signed to unsigned)
151
152 // Vector saturating rounding shift by immediate:
153 VQRSHRNs, // ...right narrow (signed)
154 VQRSHRNu, // ...right narrow (unsigned)
155 VQRSHRNsu, // ...right narrow (signed to unsigned)
156
157 // Vector shift and insert:
158 VSLI, // ...left
159 VSRI, // ...right
160
161 // Vector get lane (VMOV scalar to ARM core register)
162 // (These are used for 8- and 16-bit element types only.)
163 VGETLANEu, // zero-extend vector extract element
164 VGETLANEs, // sign-extend vector extract element
165
Bob Wilsonbad47f62010-07-14 06:31:50 +0000166 // Vector move immediate and move negated immediate:
Bob Wilsona3f19012010-07-13 21:16:48 +0000167 VMOVIMM,
Bob Wilsonbad47f62010-07-14 06:31:50 +0000168 VMVNIMM,
169
Evan Cheng7ca4b6e2011-11-15 02:12:34 +0000170 // Vector move f32 immediate:
171 VMOVFPIMM,
172
Bob Wilsonbad47f62010-07-14 06:31:50 +0000173 // Vector duplicate:
Bob Wilsoneb54d512009-08-14 05:13:08 +0000174 VDUP,
Bob Wilsoncce31f62009-08-14 05:08:32 +0000175 VDUPLANE,
Bob Wilsonf45dee32009-08-04 00:36:16 +0000176
Bob Wilsonea3a4022009-08-12 22:31:50 +0000177 // Vector shuffles:
Bob Wilson32cd8552009-08-19 17:03:43 +0000178 VEXT, // extract
Bob Wilsonea3a4022009-08-12 22:31:50 +0000179 VREV64, // reverse elements within 64-bit doublewords
180 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov9a232f42009-08-21 12:41:24 +0000181 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsona7062312009-08-21 20:54:19 +0000182 VZIP, // zip (interleave)
183 VUZP, // unzip (deinterleave)
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000184 VTRN, // transpose
Bill Wendlinge1fd78f2011-03-14 23:02:38 +0000185 VTBL1, // 1-register shuffle with mask
186 VTBL2, // 2-register shuffle with mask
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000187
Bob Wilson38ab35a2010-09-01 23:50:19 +0000188 // Vector multiply long:
189 VMULLs, // ...signed
190 VMULLu, // ...unsigned
191
Sam Parker916b1ba2017-03-14 09:13:22 +0000192 SMULWB, // Signed multiply word by half word, bottom
193 SMULWT, // Signed multiply word by half word, top
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +0000194 UMLAL, // 64bit Unsigned Accumulate Multiply
195 SMLAL, // 64bit Signed Accumulate Multiply
Sam Parkerd616cf02016-06-20 16:47:09 +0000196 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
Sam Parker654cb822017-03-15 08:27:11 +0000197 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
198 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
199 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
200 SMLALTT, // 64-bit signed accumulate multiply top, top 16
Sam Parkerdf337702017-05-04 07:31:28 +0000201 SMLALD, // Signed multiply accumulate long dual
202 SMLALDX, // Signed multiply accumulate long dual exchange
203 SMLSLD, // Signed multiply subtract long dual
204 SMLSLDX, // Signed multiply subtract long dual exchange
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +0000205
Bob Wilsond8a9a042010-06-04 00:04:02 +0000206 // Operands of the standard BUILD_VECTOR node are not legalized, which
207 // is fine if BUILD_VECTORs are always lowered to shuffles or other
208 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
209 // operands need to be legalized. Define an ARM-specific version of
210 // BUILD_VECTOR for this purpose.
211 BUILD_VECTOR,
212
Jim Grosbach11013ed2010-07-16 23:05:05 +0000213 // Bit-field insert
Owen Anderson07473072010-11-03 22:44:51 +0000214 BFI,
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000215
Owen Anderson07473072010-11-03 22:44:51 +0000216 // Vector OR with immediate
Owen Anderson30c48922010-11-05 19:27:46 +0000217 VORRIMM,
218 // Vector AND with NOT of immediate
Bob Wilson2d790df2010-11-28 06:51:26 +0000219 VBICIMM,
220
Cameron Zwarich53dd03d2011-03-30 23:01:21 +0000221 // Vector bitwise select
222 VBSL,
223
Scott Douglass953f9082015-10-05 14:49:54 +0000224 // Pseudo-instruction representing a memory copy using ldm/stm
225 // instructions.
226 MEMCPY,
227
Bob Wilson2d790df2010-11-28 06:51:26 +0000228 // Vector load N-element structure to all lanes:
Eli Friedmanf624ec22016-12-16 18:44:08 +0000229 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
230 VLD2DUP,
Bob Wilson2d790df2010-11-28 06:51:26 +0000231 VLD3DUP,
Bob Wilson06fce872011-02-07 17:43:21 +0000232 VLD4DUP,
233
234 // NEON loads with post-increment base updates:
235 VLD1_UPD,
236 VLD2_UPD,
237 VLD3_UPD,
238 VLD4_UPD,
239 VLD2LN_UPD,
240 VLD3LN_UPD,
241 VLD4LN_UPD,
Eli Friedmanf624ec22016-12-16 18:44:08 +0000242 VLD1DUP_UPD,
Bob Wilson06fce872011-02-07 17:43:21 +0000243 VLD2DUP_UPD,
244 VLD3DUP_UPD,
245 VLD4DUP_UPD,
246
247 // NEON stores with post-increment base updates:
248 VST1_UPD,
249 VST2_UPD,
250 VST3_UPD,
251 VST4_UPD,
252 VST2LN_UPD,
253 VST3LN_UPD,
Amara Emersonb4ad2f32013-09-26 12:22:36 +0000254 VST4LN_UPD
Evan Cheng10043e22007-01-19 07:51:42 +0000255 };
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000256
257 } // end namespace ARMISD
Evan Cheng10043e22007-01-19 07:51:42 +0000258
Bob Wilson2e076c42009-06-22 23:27:02 +0000259 /// Define some predicates that are used for node matching.
260 namespace ARM {
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000261
Jim Grosbach11013ed2010-07-16 23:05:05 +0000262 bool isBitFieldInvertedMask(unsigned v);
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000263
264 } // end namespace ARM
Bob Wilson2e076c42009-06-22 23:27:02 +0000265
Bob Wilsondd0e2362009-05-20 16:30:25 +0000266 //===--------------------------------------------------------------------===//
Dale Johannesen8447d342007-03-20 00:30:56 +0000267 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach91fa7812009-05-13 22:32:43 +0000268
Evan Cheng10043e22007-01-19 07:51:42 +0000269 class ARMTargetLowering : public TargetLowering {
Evan Cheng10043e22007-01-19 07:51:42 +0000270 public:
Eric Christopher1889fdc2015-01-29 00:19:39 +0000271 explicit ARMTargetLowering(const TargetMachine &TM,
272 const ARMSubtarget &STI);
Evan Cheng10043e22007-01-19 07:51:42 +0000273
Craig Topper6bc27bf2014-03-10 02:09:33 +0000274 unsigned getJumpTableEncoding() const override;
Eric Christopher824f42f2015-05-12 01:26:05 +0000275 bool useSoftFloat() const override;
Jim Grosbach8d3ba732010-07-19 17:20:38 +0000276
Craig Topper6bc27bf2014-03-10 02:09:33 +0000277 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
Duncan Sands6ed40142008-12-01 11:39:25 +0000278
279 /// ReplaceNodeResults - Replace the results of node with an illegal result
280 /// type with new values built out of custom code.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000281 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
282 SelectionDAG &DAG) const override;
Duncan Sands6ed40142008-12-01 11:39:25 +0000283
Craig Topper6bc27bf2014-03-10 02:09:33 +0000284 const char *getTargetNodeName(unsigned Opcode) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000285
Craig Topper6bc27bf2014-03-10 02:09:33 +0000286 bool isSelectSupported(SelectSupportKind Kind) const override {
Nadav Rotem9d832022012-09-02 12:10:19 +0000287 // ARM does not support scalar condition selects on vectors.
288 return (Kind != ScalarCondVectorVal);
289 }
290
Diana Picus1d101d72017-09-01 10:44:48 +0000291 bool isReadOnly(const GlobalValue *GV) const;
292
Duncan Sandsf2641e12011-09-06 19:07:46 +0000293 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
Mehdi Amini44ede332015-07-09 02:09:04 +0000294 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
295 EVT VT) const override;
Duncan Sandsf2641e12011-09-06 19:07:46 +0000296
Craig Topper6bc27bf2014-03-10 02:09:33 +0000297 MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000298 EmitInstrWithCustomInserter(MachineInstr &MI,
299 MachineBasicBlock *MBB) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000300
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000301 void AdjustInstrPostInstrSelection(MachineInstr &MI,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000302 SDNode *Node) const override;
Evan Chenge6fba772011-08-30 19:09:48 +0000303
Evan Chengf863e3f2011-07-13 00:42:17 +0000304 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Peter Collingbourne86b9fbe2016-03-21 18:00:02 +0000305 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
James Molloy9d55f192015-11-10 14:22:05 +0000306 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000307 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
Evan Chengd42641c2011-02-02 01:06:55 +0000308
Craig Topper6bc27bf2014-03-10 02:09:33 +0000309 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
Evan Chengd42641c2011-02-02 01:06:55 +0000310
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000311 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
Evan Cheng79e2ca92012-12-10 23:21:26 +0000312 /// unaligned memory accesses of the specified type. Returns whether it
313 /// is "fast" by reference in the second argument.
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000314 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
315 unsigned Align,
316 bool *Fast) const override;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000317
Craig Topper6bc27bf2014-03-10 02:09:33 +0000318 EVT getOptimalMemOpType(uint64_t Size,
319 unsigned DstAlign, unsigned SrcAlign,
320 bool IsMemset, bool ZeroMemset,
321 bool MemcpyStrSrc,
322 MachineFunction &MF) const override;
Lang Hames9929c422011-11-02 22:52:45 +0000323
Sam Parker71efbe42017-09-18 14:28:51 +0000324 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
325 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000326 bool isZExtFree(SDValue Val, EVT VT2) const override;
Evan Cheng9ec512d2012-12-06 19:13:27 +0000327
Ahmed Bougacha4200cc92015-03-05 19:37:53 +0000328 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
329
Craig Topper6bc27bf2014-03-10 02:09:33 +0000330 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
Tim Northovercc2e9032013-08-06 13:58:03 +0000331
332
Chris Lattner1eb94d92007-03-30 23:15:24 +0000333 /// isLegalAddressingMode - Return true if the addressing mode represented
334 /// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000335 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
Jonas Paulsson024e3192017-07-21 11:59:37 +0000336 Type *Ty, unsigned AS,
337 Instruction *I = nullptr) const override;
Javed Absar85874a92016-10-13 14:57:43 +0000338
339 /// getScalingFactorCost - Return the cost of the scaling used in
340 /// addressing mode represented by AM.
341 /// If the AM is supported, the return value must be >= 0.
342 /// If the AM is not supported, the return value must be negative.
343 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
344 unsigned AS) const override;
345
Evan Chengdc49a8d2009-08-14 20:09:37 +0000346 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000347
Evgeny Astigeevich540a39a2017-08-24 10:00:25 +0000348 /// \brief Returns true if the addresing mode representing by AM is legal
349 /// for the Thumb1 target, for a load/store of the specified type.
350 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
351
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000352 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach84511e12010-06-02 21:53:11 +0000353 /// icmp immediate, that is the target has icmp instructions which can
354 /// compare a register against the immediate without having to materialize
355 /// the immediate into a register.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000356 bool isLegalICmpImmediate(int64_t Imm) const override;
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000357
Dan Gohman6136e942011-05-03 00:46:49 +0000358 /// isLegalAddImmediate - Return true if the specified immediate is legal
359 /// add immediate, that is the target has add instructions which can
360 /// add a register and the immediate without having to materialize
361 /// the immediate into a register.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000362 bool isLegalAddImmediate(int64_t Imm) const override;
Dan Gohman6136e942011-05-03 00:46:49 +0000363
Evan Cheng10043e22007-01-19 07:51:42 +0000364 /// getPreIndexedAddressParts - returns true by value, base pointer and
365 /// offset pointer and addressing mode by reference if the node's address
366 /// can be legally represented as pre-indexed load / store address.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000367 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
368 ISD::MemIndexedMode &AM,
369 SelectionDAG &DAG) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000370
371 /// getPostIndexedAddressParts - returns true by value, base pointer and
372 /// offset pointer and addressing mode by reference if this node can be
373 /// combined with a load / store to form a post-indexed load / store.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000374 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
375 SDValue &Offset, ISD::MemIndexedMode &AM,
376 SelectionDAG &DAG) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000377
Craig Topperd0af7e82017-04-28 05:31:46 +0000378 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
Simon Pilgrim37b536e2017-03-31 11:24:16 +0000379 const APInt &DemandedElts,
Jay Foada0653a32014-05-14 21:14:37 +0000380 const SelectionDAG &DAG,
381 unsigned Depth) const override;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000382
383
Craig Topper6bc27bf2014-03-10 02:09:33 +0000384 bool ExpandInlineAsm(CallInst *CI) const override;
Evan Cheng078b0b02011-01-08 01:24:27 +0000385
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000386 ConstraintType getConstraintType(StringRef Constraint) const override;
John Thompsone8360b72010-10-29 17:29:13 +0000387
388 /// Examine constraint string and operand type and determine a weight value.
389 /// The operand object must already have been set up with the operand type.
390 ConstraintWeight getSingleConstraintMatchWeight(
Craig Topper6bc27bf2014-03-10 02:09:33 +0000391 AsmOperandInfo &info, const char *constraint) const override;
John Thompsone8360b72010-10-29 17:29:13 +0000392
Eric Christopher11e4df72015-02-26 22:38:43 +0000393 std::pair<unsigned, const TargetRegisterClass *>
394 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000395 StringRef Constraint, MVT VT) const override;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000396
Silviu Baranga82d04262016-04-25 14:29:18 +0000397 const char *LowerXConstraint(EVT ConstraintVT) const override;
398
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +0000399 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
400 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
401 /// true it means one of the asm constraint of the inline asm instruction
402 /// being processed is 'm'.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000403 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
404 std::vector<SDValue> &Ops,
405 SelectionDAG &DAG) const override;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000406
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000407 unsigned
408 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
Daniel Sanders1f58ef72015-06-03 12:33:56 +0000409 if (ConstraintCode == "Q")
410 return InlineAsm::Constraint_Q;
James Molloy72222f52015-10-26 10:04:52 +0000411 else if (ConstraintCode == "o")
412 return InlineAsm::Constraint_o;
Daniel Sanders1f58ef72015-06-03 12:33:56 +0000413 else if (ConstraintCode.size() == 2) {
414 if (ConstraintCode[0] == 'U') {
415 switch(ConstraintCode[1]) {
416 default:
417 break;
418 case 'm':
419 return InlineAsm::Constraint_Um;
420 case 'n':
421 return InlineAsm::Constraint_Un;
422 case 'q':
423 return InlineAsm::Constraint_Uq;
424 case 's':
425 return InlineAsm::Constraint_Us;
426 case 't':
427 return InlineAsm::Constraint_Ut;
428 case 'v':
429 return InlineAsm::Constraint_Uv;
430 case 'y':
431 return InlineAsm::Constraint_Uy;
432 }
433 }
434 }
435 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
Daniel Sandersbf5b80f2015-03-16 13:13:41 +0000436 }
437
Dan Gohman4df9d9c2010-05-11 16:21:03 +0000438 const ARMSubtarget* getSubtarget() const {
Dan Gohman544ab2c2008-04-12 04:36:06 +0000439 return Subtarget;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000440 }
441
Evan Cheng4cad68e2010-05-15 02:18:07 +0000442 /// getRegClassFor - Return the register class that should be used for the
443 /// specified value type.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000444 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
Evan Cheng4cad68e2010-05-15 02:18:07 +0000445
James Molloy8a259922013-12-03 11:23:11 +0000446 /// Returns true if a cast between SrcAS and DestAS is a noop.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000447 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
James Molloy8a259922013-12-03 11:23:11 +0000448 // Addrspacecasts are always noops.
449 return true;
450 }
451
John Brawn0dbcd652015-03-18 12:01:59 +0000452 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
453 unsigned &PrefAlign) const override;
454
Eric Christopher84bdfd82010-07-21 22:26:11 +0000455 /// createFastISel - This method returns a target specific FastISel object,
456 /// or null if the target does not support "fast" ISel.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000457 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
458 const TargetLibraryInfo *libInfo) const override;
Eric Christopher84bdfd82010-07-21 22:26:11 +0000459
Craig Topper6bc27bf2014-03-10 02:09:33 +0000460 Sched::Preference getSchedulingPreference(SDNode *N) const override;
Evan Cheng4401f882010-05-20 23:26:43 +0000461
Craig Topper6bc27bf2014-03-10 02:09:33 +0000462 bool
Zvi Rackover1b736822017-07-26 08:06:58 +0000463 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000464 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000465
466 /// isFPImmLegal - Returns true if the target can instruction select the
467 /// specified FP immediate natively. If false, the legalizer will
468 /// materialize the FP immediate as a load from a constant pool.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000469 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000470
Craig Topper6bc27bf2014-03-10 02:09:33 +0000471 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
472 const CallInst &I,
Matt Arsenault7d7adf42017-12-14 22:34:10 +0000473 MachineFunction &MF,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000474 unsigned Intrinsic) const override;
Juergen Ributzka659ce002014-01-28 01:20:14 +0000475
476 /// \brief Returns true if it is beneficial to convert a load of a constant
477 /// to just the constant itself.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000478 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
479 Type *Ty) const override;
Juergen Ributzka659ce002014-01-28 01:20:14 +0000480
Eli Friedmand03df812016-12-20 20:05:07 +0000481 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
482 /// with this index.
Craig Topper2251ef92017-08-13 17:29:07 +0000483 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
484 unsigned Index) const override;
Eli Friedmand03df812016-12-20 20:05:07 +0000485
Oliver Stannardc24f2172014-05-09 14:01:47 +0000486 /// \brief Returns true if an argument of type Ty needs to be passed in a
487 /// contiguous block of registers in calling convention CallConv.
488 bool functionArgumentNeedsConsecutiveRegisters(
489 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
490
Joseph Tremouletf748c892015-11-07 01:11:31 +0000491 /// If a physical register, this returns the register that receives the
492 /// exception address on entry to an EH pad.
493 unsigned
494 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
495
496 /// If a physical register, this returns the register that receives the
497 /// exception typeid on entry to a landing pad.
498 unsigned
499 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
500
Robin Morisset5349e8e2014-09-18 18:56:04 +0000501 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
Tim Northover037f26f22014-04-17 18:22:47 +0000502 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
503 AtomicOrdering Ord) const override;
504 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
505 Value *Addr, AtomicOrdering Ord) const override;
506
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000507 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
508
Tim Shen04de70d2017-05-09 15:27:17 +0000509 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
510 AtomicOrdering Ord) const override;
511 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
512 AtomicOrdering Ord) const override;
Robin Morisseta47cb412014-09-03 21:01:03 +0000513
Hao Liu2cd34bb2015-06-26 02:45:36 +0000514 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
515
516 bool lowerInterleavedLoad(LoadInst *LI,
517 ArrayRef<ShuffleVectorInst *> Shuffles,
518 ArrayRef<unsigned> Indices,
519 unsigned Factor) const override;
520 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
521 unsigned Factor) const override;
522
James Y Knightf44fc522016-03-16 22:12:04 +0000523 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
Ahmed Bougacha52468672015-09-11 17:08:28 +0000524 TargetLoweringBase::AtomicExpansionKind
525 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
Robin Morisseted3d48f2014-09-03 21:29:59 +0000526 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
Ahmed Bougacha9d677132015-09-11 17:08:17 +0000527 TargetLoweringBase::AtomicExpansionKind
JF Bastienf14889e2015-03-04 15:47:57 +0000528 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
Ahmed Bougacha52468672015-09-11 17:08:28 +0000529 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
Tim Northover037f26f22014-04-17 18:22:47 +0000530
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000531 bool useLoadStackGuardNode() const override;
532
Quentin Colombetc32615d2014-10-31 17:52:53 +0000533 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
534 unsigned &Cost) const override;
535
Nirav Dave4dcad5d2017-07-10 20:25:54 +0000536 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
537 const SelectionDAG &DAG) const override {
Nirav Dave54e22f32017-03-14 00:34:14 +0000538 // Do not merge to larger than i32.
539 return (MemVT.getSizeInBits() <= 32);
540 }
541
Sanjay Patelaf1b48b2015-11-10 19:24:31 +0000542 bool isCheapToSpeculateCttz() const override;
543 bool isCheapToSpeculateCtlz() const override;
544
Sanjay Patelb2f16212017-04-05 14:09:39 +0000545 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
546 return VT.isScalarInteger();
547 }
548
Manman Ren57518142016-04-11 21:08:06 +0000549 bool supportSwiftError() const override {
550 return true;
551 }
552
Diana Picus774d1572016-07-18 06:48:25 +0000553 bool hasStandaloneRem(EVT VT) const override {
554 return HasStandaloneRem;
555 }
556
Diana Picus2af9c382016-12-16 10:35:20 +0000557 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
558 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
559
Matthew Simpson1468d3e2017-04-10 18:34:37 +0000560 /// Returns true if \p VecTy is a legal interleaved access type. This
561 /// function checks the vector element type and the overall width of the
562 /// vector.
563 bool isLegalInterleavedAccessType(VectorType *VecTy,
564 const DataLayout &DL) const;
565
566 /// Returns the number of interleaved accesses that will be generated when
567 /// lowering accesses of the given type.
568 unsigned getNumInterleavedAccesses(VectorType *VecTy,
569 const DataLayout &DL) const;
570
Matthias Braun4682ac62017-05-05 22:04:05 +0000571 void finalizeLowering(MachineFunction &MF) const override;
572
Evan Cheng10f99a32010-07-19 22:15:08 +0000573 protected:
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000574 std::pair<const TargetRegisterClass *, uint8_t>
575 findRepresentativeClass(const TargetRegisterInfo *TRI,
576 MVT VT) const override;
Evan Cheng10f99a32010-07-19 22:15:08 +0000577
Evan Cheng10043e22007-01-19 07:51:42 +0000578 private:
579 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
580 /// make the right decision when generating code for different targets.
581 const ARMSubtarget *Subtarget;
582
Evan Chengdf907f42010-07-23 22:39:59 +0000583 const TargetRegisterInfo *RegInfo;
584
Evan Chengbf407072010-09-10 01:29:16 +0000585 const InstrItineraryData *Itins;
586
Bob Wilson844d6c82009-07-13 18:11:36 +0000587 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Cheng10043e22007-01-19 07:51:42 +0000588 unsigned ARMPCLabelIndex;
589
James Y Knightf44fc522016-03-16 22:12:04 +0000590 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
591 // check.
592 bool InsertFencesForAtomic;
593
Diana Picus774d1572016-07-18 06:48:25 +0000594 bool HasStandaloneRem = true;
595
Craig Topper4fa625f2012-08-12 03:16:37 +0000596 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
597 void addDRTypeForNEON(MVT VT);
598 void addQRTypeForNEON(MVT VT);
Louis Gerbarg3342bf12014-05-09 17:02:49 +0000599 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000600
Eugene Zelenko076468c2017-09-20 21:35:51 +0000601 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000602
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000603 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
604 SDValue &Arg, RegsToPassVector &RegsToPass,
Bob Wilson2e076c42009-06-22 23:27:02 +0000605 CCValAssign &VA, CCValAssign &NextVA,
606 SDValue &StackPtr,
Craig Topperb94011f2013-07-14 04:42:23 +0000607 SmallVectorImpl<SDValue> &MemOpChains,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000608 ISD::ArgFlagsTy Flags) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000609 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000610 SDValue &Root, SelectionDAG &DAG,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000611 const SDLoc &dl) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000612
Oliver Stannardc24f2172014-05-09 14:01:47 +0000613 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
614 bool isVarArg) const;
Jim Grosbach84511e12010-06-02 21:53:11 +0000615 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
616 bool isVarArg) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000617 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000618 const SDLoc &dl, SelectionDAG &DAG,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000619 const CCValAssign &VA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000620 ISD::ArgFlagsTy Flags) const;
Jim Grosbachc98892f2010-05-26 20:22:18 +0000621 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbachbd9485d2010-05-22 01:06:18 +0000622 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Matthias Braun3cd00c12015-07-16 22:34:16 +0000623 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha570d052010-02-08 23:22:00 +0000624 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000625 const ARMSubtarget *Subtarget) const;
626 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
Alexandros Lamprineas2b2b4202017-06-20 07:20:52 +0000627 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
628 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000629 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
630 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +0000631 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000632 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000633 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000634 SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000635 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Hans Wennborgaea41202012-05-04 09:40:39 +0000636 SelectionDAG &DAG,
637 TLSModel::Model model) const;
Tim Northoverbd41cf82016-01-07 09:03:03 +0000638 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
Saleem Abdulrasoolf36005a2016-02-03 18:21:59 +0000639 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
Tim Northoverbd41cf82016-01-07 09:03:03 +0000640 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000641 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Roger Ferrer Ibanez5ea0f252017-12-11 12:13:45 +0000642 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
643 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
Bill Wendling6a981312010-08-11 08:43:16 +0000644 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000645 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
646 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng25f93642010-07-08 02:08:50 +0000647 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng168ced92010-05-22 01:47:14 +0000648 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000649 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000650 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
651 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemanb69b1822010-08-03 21:31:55 +0000652 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hamesc35ee8b2012-03-15 18:49:02 +0000653 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
654 const ARMSubtarget *ST) const;
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000655 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson6f2b8962011-01-07 21:37:30 +0000656 const ARMSubtarget *ST) const;
Bob Wilsone7dde0c2013-11-03 06:14:38 +0000657 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
Renato Golin87610692013-07-16 09:32:17 +0000658 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
Martell Maloned1229242015-11-26 15:34:03 +0000659 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
660 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000661 SmallVectorImpl<SDValue> &Results) const;
Martell Maloned1229242015-11-26 15:34:03 +0000662 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000663 SDValue &Chain) const;
Scott Douglassbdef6042015-08-24 09:17:18 +0000664 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000665 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
Oliver Stannard51b1d462014-08-21 12:50:31 +0000666 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
667 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
668 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
669 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
Bob Wilson6f2b8962011-01-07 21:37:30 +0000670
Pat Gavlina717f252015-07-09 17:40:29 +0000671 unsigned getRegisterByName(const char* RegName, EVT VT,
672 SelectionDAG &DAG) const override;
Renato Golinc7aea402014-05-06 16:51:25 +0000673
Stephen Lindd502022013-07-10 01:54:24 +0000674 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
675 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
676 /// expanded to FMAs when this method returns true, otherwise fmuladd is
677 /// expanded to fmul + fadd.
678 ///
679 /// ARM supports both fused and unfused multiply-add operations; we already
Stephen Lin2a644732013-07-10 01:57:39 +0000680 /// lower a pair of fmul and fadd to the latter so it's not clear that there
Stephen Lindd502022013-07-10 01:54:24 +0000681 /// would be a gain or that the gain would be worthwhile enough to risk
682 /// correctness bugs.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000683 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
Stephen Lindd502022013-07-10 01:54:24 +0000684
Bob Wilson6f2b8962011-01-07 21:37:30 +0000685 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola18a831d2007-10-19 14:35:17 +0000686
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000687 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000688 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000689 const SmallVectorImpl<ISD::InputArg> &Ins,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000690 const SDLoc &dl, SelectionDAG &DAG,
691 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
692 SDValue ThisVal) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000693
Manman Ren5e9e65e2016-01-12 00:47:18 +0000694 bool supportSplitCSR(MachineFunction *MF) const override {
Matthias Braunf1caa282017-12-15 22:22:58 +0000695 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
696 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
Manman Ren5e9e65e2016-01-12 00:47:18 +0000697 }
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000698
Manman Ren5e9e65e2016-01-12 00:47:18 +0000699 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
700 void insertCopiesSplitCSR(
701 MachineBasicBlock *Entry,
702 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
703
Craig Topper6bc27bf2014-03-10 02:09:33 +0000704 SDValue
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000705 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
706 const SmallVectorImpl<ISD::InputArg> &Ins,
707 const SDLoc &dl, SelectionDAG &DAG,
708 SmallVectorImpl<SDValue> &InVals) const override;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000709
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000710 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
711 SDValue &Chain, const Value *OrigArg,
712 unsigned InRegsParamRecordIdx, int ArgOffset,
Tim Northover8cda34f2015-03-11 18:54:22 +0000713 unsigned ArgSize) const;
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000714
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000715 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000716 const SDLoc &dl, SDValue &Chain,
717 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000718 bool ForceMutable = false) const;
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000719
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000720 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
721 SmallVectorImpl<SDValue> &InVals) const override;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000722
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000723 /// HandleByVal - Target-specific cleanup for ByVal support.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000724 void HandleByVal(CCState *, unsigned &, unsigned) const override;
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000725
Dale Johannesend679ff72010-06-03 21:09:53 +0000726 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
727 /// for tail call optimization. Targets which want to do tail call
728 /// optimization should implement this function.
729 bool IsEligibleForTailCallOptimization(SDValue Callee,
730 CallingConv::ID CalleeCC,
731 bool isVarArg,
732 bool isCalleeStructRet,
733 bool isCallerStructRet,
734 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000735 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesend679ff72010-06-03 21:09:53 +0000736 const SmallVectorImpl<ISD::InputArg> &Ins,
737 SelectionDAG& DAG) const;
Benjamin Kramerb1996da2012-11-28 20:55:10 +0000738
Craig Topper6bc27bf2014-03-10 02:09:33 +0000739 bool CanLowerReturn(CallingConv::ID CallConv,
740 MachineFunction &MF, bool isVarArg,
741 const SmallVectorImpl<ISD::OutputArg> &Outs,
742 LLVMContext &Context) const override;
Benjamin Kramerb1996da2012-11-28 20:55:10 +0000743
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000744 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
745 const SmallVectorImpl<ISD::OutputArg> &Outs,
746 const SmallVectorImpl<SDValue> &OutVals,
747 const SDLoc &dl, SelectionDAG &DAG) const override;
Evan Cheng15b80e42009-11-12 07:13:11 +0000748
Craig Topper6bc27bf2014-03-10 02:09:33 +0000749 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
Evan Chengd4b08732010-11-30 23:55:39 +0000750
Matt Arsenault31380752017-04-18 21:16:46 +0000751 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
Evan Cheng0663f232011-03-21 01:19:09 +0000752
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000753 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
Oliver Stannard51b1d462014-08-21 12:50:31 +0000754 SDValue ARMcc, SDValue CCR, SDValue Cmp,
755 SelectionDAG &DAG) const;
Evan Cheng15b80e42009-11-12 07:13:11 +0000756 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000757 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
758 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
James Molloyd5087892017-02-13 12:32:47 +0000759 const SDLoc &dl, bool InvalidOnQNaN) const;
Bob Wilson45acbd02011-03-08 01:17:20 +0000760 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000761
762 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000763
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000764 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
Bill Wendling030b58e2011-10-06 22:18:16 +0000765 MachineBasicBlock *DispatchBB, int FI) const;
766
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000767 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
Bill Wendling374ee192011-10-03 21:25:38 +0000768
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000769 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
Manman Rene8735522012-06-01 19:33:18 +0000770
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000771 MachineBasicBlock *EmitStructByval(MachineInstr &MI,
Manman Rene8735522012-06-01 19:33:18 +0000772 MachineBasicBlock *MBB) const;
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000773
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000774 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000775 MachineBasicBlock *MBB) const;
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000776 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000777 MachineBasicBlock *MBB) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000778 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000779
Owen Andersona4076922010-11-05 21:57:54 +0000780 enum NEONModImmType {
781 VMOVModImm,
782 VMVNModImm,
783 OtherModImm
784 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000785
Eric Christopher84bdfd82010-07-21 22:26:11 +0000786 namespace ARM {
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000787
Bob Wilson3e6fa462012-08-03 04:06:28 +0000788 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
789 const TargetLibraryInfo *libInfo);
Evan Cheng10043e22007-01-19 07:51:42 +0000790
Eugene Zelenkoc4ad1ce2017-01-11 01:45:03 +0000791 } // end namespace ARM
792
793} // end namespace llvm
794
795#endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H