Jia Liu | f54f60f | 2012-02-28 07:46:26 +0000 | [diff] [blame] | 1 | //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 9 | // |
Eric Christopher | 5dc19f9 | 2011-05-09 18:16:46 +0000 | [diff] [blame] | 10 | // This file describes the Mips FPU instruction set. |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 11 | // |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 12 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 13 | |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 14 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 7ceec57 | 2008-07-09 04:45:36 +0000 | [diff] [blame] | 15 | // Floating Point Instructions |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 16 | // ------------------------ |
| 17 | // * 64bit fp: |
| 18 | // - 32 64-bit registers (default mode) |
| 19 | // - 16 even 32-bit registers (32-bit compatible mode) for |
| 20 | // single and double access. |
| 21 | // * 32bit fp: |
| 22 | // - 16 even 32-bit registers - single and double (aliased) |
| 23 | // - 32 32-bit registers (within single-only mode) |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 24 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 25 | |
Bruno Cardoso Lopes | 7ceec57 | 2008-07-09 04:45:36 +0000 | [diff] [blame] | 26 | // Floating Point Compare and Branch |
Akira Hatanaka | 1fb1b8b | 2013-07-26 20:13:47 +0000 | [diff] [blame] | 27 | def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, |
| 28 | SDTCisVT<1, i32>, |
| 29 | SDTCisVT<2, OtherVT>]>; |
Akira Hatanaka | a535270 | 2011-03-31 18:26:17 +0000 | [diff] [blame] | 30 | def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, |
Akira Hatanaka | f25c37e | 2011-09-22 23:31:54 +0000 | [diff] [blame] | 31 | SDTCisVT<2, i32>]>; |
Akira Hatanaka | 8bce21c | 2013-07-26 20:51:20 +0000 | [diff] [blame] | 32 | def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, |
| 33 | SDTCisSameAs<1, 3>]>; |
Akira Hatanaka | 252f54f | 2013-05-16 21:17:15 +0000 | [diff] [blame] | 34 | def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; |
Akira Hatanaka | 2791697 | 2011-04-15 19:52:08 +0000 | [diff] [blame] | 35 | def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, |
| 36 | SDTCisVT<1, i32>, |
| 37 | SDTCisSameAs<1, 2>]>; |
| 38 | def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, |
| 39 | SDTCisVT<1, f64>, |
Akira Hatanaka | f25c37e | 2011-09-22 23:31:54 +0000 | [diff] [blame] | 40 | SDTCisVT<2, i32>]>; |
Bruno Cardoso Lopes | a72a505 | 2009-05-27 17:23:44 +0000 | [diff] [blame] | 41 | |
Akira Hatanaka | a535270 | 2011-03-31 18:26:17 +0000 | [diff] [blame] | 42 | def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; |
| 43 | def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; |
| 44 | def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 45 | def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, |
Akira Hatanaka | a535270 | 2011-03-31 18:26:17 +0000 | [diff] [blame] | 46 | [SDNPHasChain, SDNPOptInGlue]>; |
Akira Hatanaka | 252f54f | 2013-05-16 21:17:15 +0000 | [diff] [blame] | 47 | def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; |
Akira Hatanaka | 2791697 | 2011-04-15 19:52:08 +0000 | [diff] [blame] | 48 | def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; |
| 49 | def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", |
| 50 | SDT_MipsExtractElementF64>; |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 51 | |
| 52 | // Operand for printing out a condition code. |
Akira Hatanaka | 71928e6 | 2012-04-17 18:03:21 +0000 | [diff] [blame] | 53 | let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 54 | def condcode : Operand<i32>; |
| 55 | |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 56 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 57 | // Feature predicates. |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 58 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 59 | |
Eric Christopher | 22405e4 | 2014-07-10 17:26:51 +0000 | [diff] [blame] | 60 | def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, |
Akira Hatanaka | d8ab16b | 2012-06-14 21:03:23 +0000 | [diff] [blame] | 61 | AssemblerPredicate<"FeatureFP64Bit">; |
Eric Christopher | 22405e4 | 2014-07-10 17:26:51 +0000 | [diff] [blame] | 62 | def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, |
Akira Hatanaka | d8ab16b | 2012-06-14 21:03:23 +0000 | [diff] [blame] | 63 | AssemblerPredicate<"!FeatureFP64Bit">; |
Eric Christopher | 22405e4 | 2014-07-10 17:26:51 +0000 | [diff] [blame] | 64 | def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, |
Akira Hatanaka | d8ab16b | 2012-06-14 21:03:23 +0000 | [diff] [blame] | 65 | AssemblerPredicate<"FeatureSingleFloat">; |
Eric Christopher | 22405e4 | 2014-07-10 17:26:51 +0000 | [diff] [blame] | 66 | def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, |
Akira Hatanaka | d8ab16b | 2012-06-14 21:03:23 +0000 | [diff] [blame] | 67 | AssemblerPredicate<"!FeatureSingleFloat">; |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 68 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 69 | //===----------------------------------------------------------------------===// |
| 70 | // Mips FGR size adjectives. |
| 71 | // They are mutually exclusive. |
| 72 | //===----------------------------------------------------------------------===// |
| 73 | |
| 74 | class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; } |
| 75 | class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; } |
| 76 | |
| 77 | //===----------------------------------------------------------------------===// |
| 78 | |
Akira Hatanaka | 60f7a8e | 2012-02-25 00:21:52 +0000 | [diff] [blame] | 79 | // FP immediate patterns. |
| 80 | def fpimm0 : PatLeaf<(fpimm), [{ |
| 81 | return N->isExactlyValue(+0.0); |
| 82 | }]>; |
| 83 | |
| 84 | def fpimm0neg : PatLeaf<(fpimm), [{ |
| 85 | return N->isExactlyValue(-0.0); |
| 86 | }]>; |
| 87 | |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 88 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 89 | // Instruction Class Templates |
| 90 | // |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 91 | // A set of multiclasses is used to address the register usage. |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 92 | // |
Jakob Stoklund Olesen | 6728958 | 2011-09-28 23:59:28 +0000 | [diff] [blame] | 93 | // S32 - single precision in 16 32bit even fp registers |
Bruno Cardoso Lopes | 9b9586a | 2009-03-21 00:05:07 +0000 | [diff] [blame] | 94 | // single precision in 32 32bit fp registers in SingleOnly mode |
Jakob Stoklund Olesen | 6728958 | 2011-09-28 23:59:28 +0000 | [diff] [blame] | 95 | // S64 - single precision in 32 64bit fp registers (In64BitMode) |
Bruno Cardoso Lopes | 9b9586a | 2009-03-21 00:05:07 +0000 | [diff] [blame] | 96 | // D32 - double precision in 16 32bit even fp registers |
| 97 | // D64 - double precision in 32 64bit fp registers (In64BitMode) |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 98 | // |
Jakob Stoklund Olesen | 6728958 | 2011-09-28 23:59:28 +0000 | [diff] [blame] | 99 | // Only S32 and D32 are supported right now. |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 100 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 101 | |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 102 | class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, |
Akira Hatanaka | 29b5138 | 2012-12-13 01:07:37 +0000 | [diff] [blame] | 103 | SDPatternOperator OpNode= null_frag> : |
| 104 | InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), |
| 105 | !strconcat(opstr, "\t$fd, $fs, $ft"), |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 106 | [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> { |
Akira Hatanaka | 29b5138 | 2012-12-13 01:07:37 +0000 | [diff] [blame] | 107 | let isCommutable = IsComm; |
| 108 | } |
| 109 | |
| 110 | multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, |
| 111 | SDPatternOperator OpNode = null_frag> { |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 112 | def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 113 | AdditionalRequires<[NotFP64bit]>; |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 114 | def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, |
| 115 | IsComm, OpNode>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 116 | AdditionalRequires<[IsFP64bit]> { |
Akira Hatanaka | 29b5138 | 2012-12-13 01:07:37 +0000 | [diff] [blame] | 117 | string DecoderNamespace = "Mips64"; |
| 118 | } |
| 119 | } |
| 120 | |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 121 | class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, |
Akira Hatanaka | dea8f61 | 2012-12-13 01:14:07 +0000 | [diff] [blame] | 122 | InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : |
| 123 | InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 124 | [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, |
Akira Hatanaka | 28aed9c | 2013-01-25 00:20:39 +0000 | [diff] [blame] | 125 | NeverHasSideEffects; |
Akira Hatanaka | dea8f61 | 2012-12-13 01:14:07 +0000 | [diff] [blame] | 126 | |
| 127 | multiclass ABSS_M<string opstr, InstrItinClass Itin, |
| 128 | SDPatternOperator OpNode= null_frag> { |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 129 | def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 130 | AdditionalRequires<[NotFP64bit]>; |
Akira Hatanaka | 00fcf2e | 2013-08-08 21:54:26 +0000 | [diff] [blame] | 131 | def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 132 | AdditionalRequires<[IsFP64bit]> { |
Akira Hatanaka | dea8f61 | 2012-12-13 01:14:07 +0000 | [diff] [blame] | 133 | string DecoderNamespace = "Mips64"; |
| 134 | } |
| 135 | } |
| 136 | |
| 137 | multiclass ROUND_M<string opstr, InstrItinClass Itin> { |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 138 | def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 139 | AdditionalRequires<[NotFP64bit]>; |
Akira Hatanaka | 00fcf2e | 2013-08-08 21:54:26 +0000 | [diff] [blame] | 140 | def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 141 | AdditionalRequires<[IsFP64bit]> { |
Akira Hatanaka | dea8f61 | 2012-12-13 01:14:07 +0000 | [diff] [blame] | 142 | let DecoderNamespace = "Mips64"; |
| 143 | } |
| 144 | } |
| 145 | |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 146 | class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, |
Akira Hatanaka | 2b75dde | 2012-12-13 01:16:49 +0000 | [diff] [blame] | 147 | InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : |
| 148 | InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), |
Zoran Jovanovic | 8876be3 | 2013-12-25 10:09:27 +0000 | [diff] [blame] | 149 | [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>; |
Akira Hatanaka | 2b75dde | 2012-12-13 01:16:49 +0000 | [diff] [blame] | 150 | |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 151 | class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, |
Akira Hatanaka | 2b75dde | 2012-12-13 01:16:49 +0000 | [diff] [blame] | 152 | InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : |
| 153 | InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), |
Zoran Jovanovic | 8876be3 | 2013-12-25 10:09:27 +0000 | [diff] [blame] | 154 | [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>; |
Akira Hatanaka | 2b75dde | 2012-12-13 01:16:49 +0000 | [diff] [blame] | 155 | |
Daniel Sanders | 1f6f0f4 | 2014-06-12 11:55:58 +0000 | [diff] [blame] | 156 | class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, |
| 157 | InstrItinClass Itin> : |
| 158 | InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), |
| 159 | !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr> { |
| 160 | // $fs_in is part of a white lie to work around a widespread bug in the FPU |
| 161 | // implementation. See expandBuildPairF64 for details. |
| 162 | let Constraints = "$fs = $fs_in"; |
| 163 | } |
| 164 | |
Vladimir Medic | 233dd51 | 2013-06-24 10:05:34 +0000 | [diff] [blame] | 165 | class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, |
Akira Hatanaka | 6781fc1 | 2013-08-20 21:08:22 +0000 | [diff] [blame] | 166 | SDPatternOperator OpNode= null_frag> : |
| 167 | InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 168 | [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { |
Akira Hatanaka | 92994f4 | 2012-12-13 01:24:00 +0000 | [diff] [blame] | 169 | let DecoderMethod = "DecodeFMem"; |
Akira Hatanaka | 9edae02 | 2013-05-13 18:23:35 +0000 | [diff] [blame] | 170 | let mayLoad = 1; |
Akira Hatanaka | 92994f4 | 2012-12-13 01:24:00 +0000 | [diff] [blame] | 171 | } |
| 172 | |
Vladimir Medic | 233dd51 | 2013-06-24 10:05:34 +0000 | [diff] [blame] | 173 | class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, |
Akira Hatanaka | 6781fc1 | 2013-08-20 21:08:22 +0000 | [diff] [blame] | 174 | SDPatternOperator OpNode= null_frag> : |
| 175 | InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 176 | [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { |
Akira Hatanaka | 92994f4 | 2012-12-13 01:24:00 +0000 | [diff] [blame] | 177 | let DecoderMethod = "DecodeFMem"; |
Akira Hatanaka | 9edae02 | 2013-05-13 18:23:35 +0000 | [diff] [blame] | 178 | let mayStore = 1; |
Akira Hatanaka | 92994f4 | 2012-12-13 01:24:00 +0000 | [diff] [blame] | 179 | } |
Akira Hatanaka | 2b75dde | 2012-12-13 01:16:49 +0000 | [diff] [blame] | 180 | |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 181 | class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, |
Akira Hatanaka | b0d4acb | 2012-12-13 01:27:48 +0000 | [diff] [blame] | 182 | SDPatternOperator OpNode = null_frag> : |
| 183 | InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), |
| 184 | !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), |
Zoran Jovanovic | 8876be3 | 2013-12-25 10:09:27 +0000 | [diff] [blame] | 185 | [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, |
| 186 | FrmFR, opstr>; |
Akira Hatanaka | b0d4acb | 2012-12-13 01:27:48 +0000 | [diff] [blame] | 187 | |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 188 | class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, |
Akira Hatanaka | b0d4acb | 2012-12-13 01:27:48 +0000 | [diff] [blame] | 189 | SDPatternOperator OpNode = null_frag> : |
| 190 | InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), |
| 191 | !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), |
| 192 | [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], |
Zoran Jovanovic | 8876be3 | 2013-12-25 10:09:27 +0000 | [diff] [blame] | 193 | Itin, FrmFR, opstr>; |
Akira Hatanaka | b0d4acb | 2012-12-13 01:27:48 +0000 | [diff] [blame] | 194 | |
Akira Hatanaka | 9bfa2e2 | 2013-08-28 00:55:15 +0000 | [diff] [blame] | 195 | class LWXC1_FT<string opstr, RegisterOperand DRC, |
Akira Hatanaka | cd3dfd2 | 2012-12-13 01:30:49 +0000 | [diff] [blame] | 196 | InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : |
Akira Hatanaka | 9bfa2e2 | 2013-08-28 00:55:15 +0000 | [diff] [blame] | 197 | InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), |
Akira Hatanaka | cd3dfd2 | 2012-12-13 01:30:49 +0000 | [diff] [blame] | 198 | !strconcat(opstr, "\t$fd, ${index}(${base})"), |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 199 | [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, |
| 200 | FrmFI, opstr> { |
Akira Hatanaka | 69fb3d1 | 2013-02-15 21:20:45 +0000 | [diff] [blame] | 201 | let AddedComplexity = 20; |
| 202 | } |
Akira Hatanaka | cd3dfd2 | 2012-12-13 01:30:49 +0000 | [diff] [blame] | 203 | |
Akira Hatanaka | 9bfa2e2 | 2013-08-28 00:55:15 +0000 | [diff] [blame] | 204 | class SWXC1_FT<string opstr, RegisterOperand DRC, |
Akira Hatanaka | cd3dfd2 | 2012-12-13 01:30:49 +0000 | [diff] [blame] | 205 | InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : |
Akira Hatanaka | 9bfa2e2 | 2013-08-28 00:55:15 +0000 | [diff] [blame] | 206 | InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), |
Akira Hatanaka | cd3dfd2 | 2012-12-13 01:30:49 +0000 | [diff] [blame] | 207 | !strconcat(opstr, "\t$fs, ${index}(${base})"), |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 208 | [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, |
| 209 | FrmFI, opstr> { |
Akira Hatanaka | 69fb3d1 | 2013-02-15 21:20:45 +0000 | [diff] [blame] | 210 | let AddedComplexity = 20; |
| 211 | } |
Akira Hatanaka | cd3dfd2 | 2012-12-13 01:30:49 +0000 | [diff] [blame] | 212 | |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 213 | class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, |
Akira Hatanaka | fd9163b | 2012-12-13 01:32:36 +0000 | [diff] [blame] | 214 | SDPatternOperator Op = null_frag> : |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 215 | InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), |
Akira Hatanaka | 1fb1b8b | 2013-07-26 20:13:47 +0000 | [diff] [blame] | 216 | !strconcat(opstr, "\t$fcc, $offset"), |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 217 | [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, |
| 218 | FrmFI, opstr> { |
Akira Hatanaka | fd9163b | 2012-12-13 01:32:36 +0000 | [diff] [blame] | 219 | let isBranch = 1; |
| 220 | let isTerminator = 1; |
| 221 | let hasDelaySlot = 1; |
| 222 | let Defs = [AT]; |
Akira Hatanaka | fd9163b | 2012-12-13 01:32:36 +0000 | [diff] [blame] | 223 | } |
| 224 | |
Akira Hatanaka | 79e1cdb | 2012-12-13 01:34:09 +0000 | [diff] [blame] | 225 | class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, |
| 226 | SDPatternOperator OpNode = null_frag> : |
| 227 | InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), |
| 228 | !strconcat("c.$cond.", typestr, "\t$fs, $ft"), |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 229 | [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, |
| 230 | !strconcat("c.$cond.", typestr)> { |
Akira Hatanaka | 55f69b3 | 2013-07-26 19:01:56 +0000 | [diff] [blame] | 231 | let Defs = [FCC0]; |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 232 | let isCodeGenOnly = 1; |
Akira Hatanaka | 79e1cdb | 2012-12-13 01:34:09 +0000 | [diff] [blame] | 233 | } |
| 234 | |
Daniel Sanders | f28bf76 | 2014-08-17 19:47:47 +0000 | [diff] [blame^] | 235 | class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, |
| 236 | InstrItinClass itin> : |
| 237 | InstSE<(outs), (ins RC:$fs, RC:$ft), |
| 238 | !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, |
| 239 | FrmFR>; |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 240 | |
Daniel Sanders | f28bf76 | 2014-08-17 19:47:47 +0000 | [diff] [blame^] | 241 | multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, |
| 242 | InstrItinClass itin> { |
Daniel Sanders | b8013ba | 2014-01-21 11:42:48 +0000 | [diff] [blame] | 243 | def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>; |
| 244 | def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>; |
| 245 | def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>; |
| 246 | def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>; |
| 247 | def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>; |
| 248 | def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>; |
| 249 | def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>; |
| 250 | def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>; |
| 251 | def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>; |
| 252 | def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>; |
| 253 | def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>; |
| 254 | def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>; |
| 255 | def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>; |
| 256 | def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>; |
| 257 | def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>; |
| 258 | def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>; |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 259 | } |
| 260 | |
Daniel Sanders | f28bf76 | 2014-08-17 19:47:47 +0000 | [diff] [blame^] | 261 | defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; |
| 262 | defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, |
| 263 | AdditionalRequires<[NotFP64bit]>; |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 264 | let DecoderNamespace = "Mips64" in |
Daniel Sanders | f28bf76 | 2014-08-17 19:47:47 +0000 | [diff] [blame^] | 265 | defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, |
| 266 | AdditionalRequires<[IsFP64bit]>; |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 267 | |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 268 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 7ceec57 | 2008-07-09 04:45:36 +0000 | [diff] [blame] | 269 | // Floating Point Instructions |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 270 | //===----------------------------------------------------------------------===// |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 271 | def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, |
Daniel Sanders | d39320c | 2014-05-08 12:40:48 +0000 | [diff] [blame] | 272 | ABSS_FM<0xc, 16>, ISA_MIPS2; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 273 | def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, |
Daniel Sanders | d39320c | 2014-05-08 12:40:48 +0000 | [diff] [blame] | 274 | ABSS_FM<0xd, 16>, ISA_MIPS2; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 275 | def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, |
Daniel Sanders | d39320c | 2014-05-08 12:40:48 +0000 | [diff] [blame] | 276 | ABSS_FM<0xe, 16>, ISA_MIPS2; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 277 | def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, |
Daniel Sanders | d39320c | 2014-05-08 12:40:48 +0000 | [diff] [blame] | 278 | ABSS_FM<0xf, 16>, ISA_MIPS2; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 279 | def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 280 | ABSS_FM<0x24, 16>; |
Akira Hatanaka | 13ae13b | 2011-10-08 03:19:38 +0000 | [diff] [blame] | 281 | |
Daniel Sanders | d39320c | 2014-05-08 12:40:48 +0000 | [diff] [blame] | 282 | defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; |
| 283 | defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; |
| 284 | defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; |
| 285 | defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 286 | defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; |
Akira Hatanaka | e986a59 | 2012-12-13 00:29:29 +0000 | [diff] [blame] | 287 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 288 | let DecoderNamespace = "Mips64" in { |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 289 | def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 290 | ABSS_FM<0x8, 16>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 291 | def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 292 | ABSS_FM<0x8, 17>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 293 | def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 294 | ABSS_FM<0x9, 16>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 295 | def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 296 | ABSS_FM<0x9, 17>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 297 | def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 298 | ABSS_FM<0xa, 16>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 299 | def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 300 | ABSS_FM<0xa, 17>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 301 | def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 302 | ABSS_FM<0xb, 16>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 303 | def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 304 | ABSS_FM<0xb, 17>, FGR_64; |
Akira Hatanaka | e986a59 | 2012-12-13 00:29:29 +0000 | [diff] [blame] | 305 | } |
| 306 | |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 307 | def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 308 | ABSS_FM<0x20, 20>; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 309 | def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, |
Daniel Sanders | 387fc15 | 2014-05-13 11:45:36 +0000 | [diff] [blame] | 310 | ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 311 | def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, |
Daniel Sanders | 387fc15 | 2014-05-13 11:45:36 +0000 | [diff] [blame] | 312 | ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; |
Akira Hatanaka | 13ae13b | 2011-10-08 03:19:38 +0000 | [diff] [blame] | 313 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 314 | def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, |
| 315 | ABSS_FM<0x20, 17>, FGR_32; |
| 316 | def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, |
| 317 | ABSS_FM<0x21, 20>, FGR_32; |
| 318 | def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, |
| 319 | ABSS_FM<0x21, 16>, FGR_32; |
Akira Hatanaka | 13ae13b | 2011-10-08 03:19:38 +0000 | [diff] [blame] | 320 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 321 | let DecoderNamespace = "Mips64" in { |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 322 | def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 323 | ABSS_FM<0x20, 17>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 324 | def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 325 | ABSS_FM<0x20, 21>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 326 | def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 327 | ABSS_FM<0x21, 20>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 328 | def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 329 | ABSS_FM<0x21, 16>, FGR_64; |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 330 | def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 331 | ABSS_FM<0x21, 21>, FGR_64; |
Akira Hatanaka | 13ae13b | 2011-10-08 03:19:38 +0000 | [diff] [blame] | 332 | } |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 333 | |
Akira Hatanaka | 39d40f7 | 2013-05-16 19:48:37 +0000 | [diff] [blame] | 334 | let isPseudo = 1, isCodeGenOnly = 1 in { |
Daniel Sanders | 555f4c5 | 2014-01-21 10:56:23 +0000 | [diff] [blame] | 335 | def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; |
| 336 | def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; |
| 337 | def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; |
| 338 | def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; |
| 339 | def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; |
Akira Hatanaka | 39d40f7 | 2013-05-16 19:48:37 +0000 | [diff] [blame] | 340 | } |
| 341 | |
Daniel Sanders | b282f1f | 2014-04-09 09:56:43 +0000 | [diff] [blame] | 342 | def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, |
| 343 | ABSS_FM<0x5, 16>; |
| 344 | def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, |
| 345 | ABSS_FM<0x7, 16>; |
| 346 | defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; |
| 347 | defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; |
Akira Hatanaka | e986a59 | 2012-12-13 00:29:29 +0000 | [diff] [blame] | 348 | |
Daniel Sanders | 3424067 | 2014-01-21 13:36:45 +0000 | [diff] [blame] | 349 | def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, |
Daniel Sanders | d39320c | 2014-05-08 12:40:48 +0000 | [diff] [blame] | 350 | ABSS_FM<0x4, 16>, ISA_MIPS2; |
| 351 | defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 352 | |
| 353 | // The odd-numbered registers are only referenced when doing loads, |
| 354 | // stores, and moves between floating-point and integer registers. |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 355 | // When defining instructions, we reference all 32-bit registers, |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 356 | // regardless of register aliasing. |
Bruno Cardoso Lopes | 2312a3a | 2011-10-18 17:50:36 +0000 | [diff] [blame] | 357 | |
Bruno Cardoso Lopes | 2312a3a | 2011-10-18 17:50:36 +0000 | [diff] [blame] | 358 | /// Move Control Registers From/To CPU Registers |
Daniel Sanders | f5fb341 | 2014-01-21 11:28:03 +0000 | [diff] [blame] | 359 | def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; |
| 360 | def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; |
Daniel Sanders | 3d345b1 | 2014-01-21 15:03:52 +0000 | [diff] [blame] | 361 | def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, |
Zoran Jovanovic | 8876be3 | 2013-12-25 10:09:27 +0000 | [diff] [blame] | 362 | bitconvert>, MFC1_FM<0>; |
Daniel Sanders | 3d345b1 | 2014-01-21 15:03:52 +0000 | [diff] [blame] | 363 | def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, |
Zoran Jovanovic | 8876be3 | 2013-12-25 10:09:27 +0000 | [diff] [blame] | 364 | bitconvert>, MFC1_FM<4>; |
Daniel Sanders | 24e08fd | 2014-07-14 12:41:31 +0000 | [diff] [blame] | 365 | def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, |
| 366 | MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; |
| 367 | def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, |
| 368 | MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { |
| 369 | let DecoderNamespace = "Mips64"; |
| 370 | } |
| 371 | def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, |
Daniel Sanders | 1f6f0f4 | 2014-06-12 11:55:58 +0000 | [diff] [blame] | 372 | MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; |
Daniel Sanders | 24e08fd | 2014-07-14 12:41:31 +0000 | [diff] [blame] | 373 | def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, |
Daniel Sanders | 1f6f0f4 | 2014-06-12 11:55:58 +0000 | [diff] [blame] | 374 | MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { |
| 375 | let DecoderNamespace = "Mips64"; |
| 376 | } |
Daniel Sanders | 3d345b1 | 2014-01-21 15:03:52 +0000 | [diff] [blame] | 377 | def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, |
Daniel Sanders | f2056be | 2014-05-09 13:02:27 +0000 | [diff] [blame] | 378 | bitconvert>, MFC1_FM<1>, ISA_MIPS3; |
Daniel Sanders | 3d345b1 | 2014-01-21 15:03:52 +0000 | [diff] [blame] | 379 | def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, |
Daniel Sanders | f2056be | 2014-05-09 13:02:27 +0000 | [diff] [blame] | 380 | bitconvert>, MFC1_FM<5>, ISA_MIPS3; |
Akira Hatanaka | 1537e29 | 2011-11-07 21:32:58 +0000 | [diff] [blame] | 381 | |
Daniel Sanders | f5fb341 | 2014-01-21 11:28:03 +0000 | [diff] [blame] | 382 | def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 383 | ABSS_FM<0x6, 16>; |
Daniel Sanders | f5fb341 | 2014-01-21 11:28:03 +0000 | [diff] [blame] | 384 | def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 385 | ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>; |
Daniel Sanders | f5fb341 | 2014-01-21 11:28:03 +0000 | [diff] [blame] | 386 | def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 387 | ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> { |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 388 | let DecoderNamespace = "Mips64"; |
Akira Hatanaka | 71928e6 | 2012-04-17 18:03:21 +0000 | [diff] [blame] | 389 | } |
Bruno Cardoso Lopes | 7ee7191 | 2010-01-30 18:29:19 +0000 | [diff] [blame] | 390 | |
Bruno Cardoso Lopes | 7ceec57 | 2008-07-09 04:45:36 +0000 | [diff] [blame] | 391 | /// Floating Point Memory Instructions |
Daniel Sanders | 5682f63 | 2014-04-29 16:37:01 +0000 | [diff] [blame] | 392 | def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; |
| 393 | def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 394 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 395 | let DecoderNamespace = "Mips64" in { |
Daniel Sanders | d39320c | 2014-05-08 12:40:48 +0000 | [diff] [blame] | 396 | def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2, |
| 397 | FGR_64; |
| 398 | def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2, |
| 399 | FGR_64; |
Akira Hatanaka | 3c5cab4 | 2012-02-27 19:09:08 +0000 | [diff] [blame] | 400 | } |
| 401 | |
Daniel Sanders | d39320c | 2014-05-08 12:40:48 +0000 | [diff] [blame] | 402 | def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, |
| 403 | ISA_MIPS2, FGR_32; |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 404 | def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, |
Daniel Sanders | d39320c | 2014-05-08 12:40:48 +0000 | [diff] [blame] | 405 | ISA_MIPS2, FGR_32; |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 406 | |
Daniel Sanders | cdbbe08 | 2014-05-08 13:02:11 +0000 | [diff] [blame] | 407 | // Cop2 Memory Instructions |
| 408 | // FIXME: These aren't really FPU instructions and as such don't belong in this |
| 409 | // file |
Daniel Sanders | 5e6f54e | 2014-06-16 10:00:45 +0000 | [diff] [blame] | 410 | def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>, |
| 411 | ISA_MIPS1_NOT_32R6_64R6; |
| 412 | def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>, |
| 413 | ISA_MIPS1_NOT_32R6_64R6; |
| 414 | def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, |
| 415 | ISA_MIPS2_NOT_32R6_64R6; |
| 416 | def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, |
| 417 | ISA_MIPS2_NOT_32R6_64R6; |
Vladimir Medic | 05bcde6 | 2013-09-16 10:29:42 +0000 | [diff] [blame] | 418 | |
Daniel Sanders | cdbbe08 | 2014-05-08 13:02:11 +0000 | [diff] [blame] | 419 | // Cop3 Memory Instructions |
| 420 | // FIXME: These aren't really FPU instructions and as such don't belong in this |
| 421 | // file |
Daniel Sanders | c171f65 | 2014-06-13 13:15:59 +0000 | [diff] [blame] | 422 | let DecoderNamespace = "COP3_" in { |
| 423 | def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>; |
| 424 | def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>; |
| 425 | def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>, |
| 426 | ISA_MIPS2; |
| 427 | def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, |
| 428 | ISA_MIPS2; |
| 429 | } |
Daniel Sanders | cdbbe08 | 2014-05-08 13:02:11 +0000 | [diff] [blame] | 430 | |
Akira Hatanaka | 330d901 | 2012-02-28 02:55:02 +0000 | [diff] [blame] | 431 | // Indexed loads and stores. |
Petar Jovanovic | 9725016 | 2014-02-05 17:19:30 +0000 | [diff] [blame] | 432 | // Base register + offset register addressing mode (indicated by "x" in the |
| 433 | // instruction mnemonic) is disallowed under NaCl. |
Daniel Sanders | 94eda2e | 2014-05-12 11:56:16 +0000 | [diff] [blame] | 434 | let AdditionalPredicates = [IsNotNaCl] in { |
| 435 | def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 436 | INSN_MIPS4_32R2_NOT_32R6_64R6; |
Daniel Sanders | 94eda2e | 2014-05-12 11:56:16 +0000 | [diff] [blame] | 437 | def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 438 | INSN_MIPS4_32R2_NOT_32R6_64R6; |
Akira Hatanaka | 330d901 | 2012-02-28 02:55:02 +0000 | [diff] [blame] | 439 | } |
| 440 | |
Daniel Sanders | 94eda2e | 2014-05-12 11:56:16 +0000 | [diff] [blame] | 441 | let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 442 | def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 443 | INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 444 | def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 445 | INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; |
Akira Hatanaka | 330d901 | 2012-02-28 02:55:02 +0000 | [diff] [blame] | 446 | } |
| 447 | |
Daniel Sanders | 94eda2e | 2014-05-12 11:56:16 +0000 | [diff] [blame] | 448 | let DecoderNamespace="Mips64" in { |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 449 | def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 450 | INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 451 | def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 452 | INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; |
Akira Hatanaka | 330d901 | 2012-02-28 02:55:02 +0000 | [diff] [blame] | 453 | } |
| 454 | |
Akira Hatanaka | 4ce7c40 | 2012-07-31 18:16:49 +0000 | [diff] [blame] | 455 | // Load/store doubleword indexed unaligned. |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 456 | let AdditionalPredicates = [IsNotNaCl] in { |
| 457 | def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 458 | INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 459 | def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 460 | INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; |
Akira Hatanaka | 4ce7c40 | 2012-07-31 18:16:49 +0000 | [diff] [blame] | 461 | } |
| 462 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 463 | let DecoderNamespace="Mips64" in { |
Daniel Sanders | 07cdea2 | 2014-05-12 12:52:44 +0000 | [diff] [blame] | 464 | def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 465 | INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; |
Daniel Sanders | 07cdea2 | 2014-05-12 12:52:44 +0000 | [diff] [blame] | 466 | def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, |
Daniel Sanders | fd61fd3 | 2014-06-12 14:19:28 +0000 | [diff] [blame] | 467 | INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; |
Akira Hatanaka | 4ce7c40 | 2012-07-31 18:16:49 +0000 | [diff] [blame] | 468 | } |
| 469 | |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 470 | /// Floating-point Aritmetic |
Daniel Sanders | 4bf6078 | 2014-01-21 12:38:07 +0000 | [diff] [blame] | 471 | def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 472 | ADDS_FM<0x00, 16>; |
Daniel Sanders | 4bf6078 | 2014-01-21 12:38:07 +0000 | [diff] [blame] | 473 | defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; |
Daniel Sanders | 072f60f | 2014-01-21 13:22:08 +0000 | [diff] [blame] | 474 | def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 475 | ADDS_FM<0x03, 16>; |
Daniel Sanders | 072f60f | 2014-01-21 13:22:08 +0000 | [diff] [blame] | 476 | defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; |
Daniel Sanders | 47b4b6d | 2014-01-21 12:51:44 +0000 | [diff] [blame] | 477 | def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 478 | ADDS_FM<0x02, 16>; |
Daniel Sanders | 2ce72b0 | 2014-01-21 13:07:31 +0000 | [diff] [blame] | 479 | defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; |
Daniel Sanders | 4bf6078 | 2014-01-21 12:38:07 +0000 | [diff] [blame] | 480 | def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, |
Vladimir Medic | 64828a1 | 2013-07-16 10:07:14 +0000 | [diff] [blame] | 481 | ADDS_FM<0x01, 16>; |
Daniel Sanders | 4bf6078 | 2014-01-21 12:38:07 +0000 | [diff] [blame] | 482 | defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 483 | |
Daniel Sanders | 9c1b1be | 2014-05-07 13:57:22 +0000 | [diff] [blame] | 484 | def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 485 | MADDS_FM<4, 0>, ISA_MIPS32R2_NOT_32R6_64R6; |
Daniel Sanders | 9c1b1be | 2014-05-07 13:57:22 +0000 | [diff] [blame] | 486 | def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 487 | MADDS_FM<5, 0>, ISA_MIPS32R2_NOT_32R6_64R6; |
Akira Hatanaka | 60f7a8e | 2012-02-25 00:21:52 +0000 | [diff] [blame] | 488 | |
Daniel Sanders | 9c1b1be | 2014-05-07 13:57:22 +0000 | [diff] [blame] | 489 | let AdditionalPredicates = [NoNaNsFPMath] in { |
Daniel Sanders | 47b4b6d | 2014-01-21 12:51:44 +0000 | [diff] [blame] | 490 | def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 491 | MADDS_FM<6, 0>, ISA_MIPS32R2_NOT_32R6_64R6; |
Daniel Sanders | 47b4b6d | 2014-01-21 12:51:44 +0000 | [diff] [blame] | 492 | def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 493 | MADDS_FM<7, 0>, ISA_MIPS32R2_NOT_32R6_64R6; |
Akira Hatanaka | 60f7a8e | 2012-02-25 00:21:52 +0000 | [diff] [blame] | 494 | } |
| 495 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 496 | def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 497 | MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 498 | def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 499 | MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; |
Akira Hatanaka | 60f7a8e | 2012-02-25 00:21:52 +0000 | [diff] [blame] | 500 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 501 | let AdditionalPredicates = [NoNaNsFPMath] in { |
Daniel Sanders | 2ce72b0 | 2014-01-21 13:07:31 +0000 | [diff] [blame] | 502 | def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 503 | MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; |
Daniel Sanders | 2ce72b0 | 2014-01-21 13:07:31 +0000 | [diff] [blame] | 504 | def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 505 | MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; |
Akira Hatanaka | 60f7a8e | 2012-02-25 00:21:52 +0000 | [diff] [blame] | 506 | } |
| 507 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 508 | let isCodeGenOnly=1 in { |
Daniel Sanders | 2ce72b0 | 2014-01-21 13:07:31 +0000 | [diff] [blame] | 509 | def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 510 | MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; |
Daniel Sanders | 2ce72b0 | 2014-01-21 13:07:31 +0000 | [diff] [blame] | 511 | def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 512 | MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; |
Akira Hatanaka | 60f7a8e | 2012-02-25 00:21:52 +0000 | [diff] [blame] | 513 | } |
| 514 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 515 | let AdditionalPredicates = [NoNaNsFPMath], |
Akira Hatanaka | cdf4fd8 | 2012-05-22 03:10:09 +0000 | [diff] [blame] | 516 | isCodeGenOnly=1 in { |
Daniel Sanders | 2ce72b0 | 2014-01-21 13:07:31 +0000 | [diff] [blame] | 517 | def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 518 | MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; |
Daniel Sanders | 2ce72b0 | 2014-01-21 13:07:31 +0000 | [diff] [blame] | 519 | def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, |
Daniel Sanders | ded02af | 2014-06-12 11:04:18 +0000 | [diff] [blame] | 520 | MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; |
Akira Hatanaka | 60f7a8e | 2012-02-25 00:21:52 +0000 | [diff] [blame] | 521 | } |
| 522 | |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 523 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 7ceec57 | 2008-07-09 04:45:36 +0000 | [diff] [blame] | 524 | // Floating Point Branch Codes |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 525 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 526 | // Mips branch codes. These correspond to condcode in MipsInstrInfo.h. |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 527 | // They must be kept in synch. |
| 528 | def MIPS_BRANCH_F : PatLeaf<(i32 0)>; |
| 529 | def MIPS_BRANCH_T : PatLeaf<(i32 1)>; |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 530 | |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 531 | def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>, |
Daniel Sanders | 3d3ea53 | 2014-06-12 15:00:17 +0000 | [diff] [blame] | 532 | BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; |
Zoran Jovanovic | ce02486 | 2013-12-20 15:44:08 +0000 | [diff] [blame] | 533 | def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>, |
Daniel Sanders | 3d3ea53 | 2014-06-12 15:00:17 +0000 | [diff] [blame] | 534 | BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; |
Akira Hatanaka | 1fb1b8b | 2013-07-26 20:13:47 +0000 | [diff] [blame] | 535 | |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 536 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 7ceec57 | 2008-07-09 04:45:36 +0000 | [diff] [blame] | 537 | // Floating Point Flag Conditions |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 538 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 539 | // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 540 | // They must be kept in synch. |
| 541 | def MIPS_FCOND_F : PatLeaf<(i32 0)>; |
| 542 | def MIPS_FCOND_UN : PatLeaf<(i32 1)>; |
Akira Hatanaka | a535270 | 2011-03-31 18:26:17 +0000 | [diff] [blame] | 543 | def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; |
Bruno Cardoso Lopes | c9c3f49 | 2008-07-05 19:05:21 +0000 | [diff] [blame] | 544 | def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; |
| 545 | def MIPS_FCOND_OLT : PatLeaf<(i32 4)>; |
| 546 | def MIPS_FCOND_ULT : PatLeaf<(i32 5)>; |
| 547 | def MIPS_FCOND_OLE : PatLeaf<(i32 6)>; |
| 548 | def MIPS_FCOND_ULE : PatLeaf<(i32 7)>; |
| 549 | def MIPS_FCOND_SF : PatLeaf<(i32 8)>; |
| 550 | def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; |
| 551 | def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; |
| 552 | def MIPS_FCOND_NGL : PatLeaf<(i32 11)>; |
| 553 | def MIPS_FCOND_LT : PatLeaf<(i32 12)>; |
| 554 | def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; |
| 555 | def MIPS_FCOND_LE : PatLeaf<(i32 14)>; |
| 556 | def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; |
| 557 | |
| 558 | /// Floating Point Compare |
Daniel Sanders | 0fa6041 | 2014-06-12 13:39:06 +0000 | [diff] [blame] | 559 | def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, |
| 560 | ISA_MIPS1_NOT_32R6_64R6; |
Daniel Sanders | b8013ba | 2014-01-21 11:42:48 +0000 | [diff] [blame] | 561 | def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, |
Daniel Sanders | 0fa6041 | 2014-06-12 13:39:06 +0000 | [diff] [blame] | 562 | ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[NotFP64bit]>; |
Akira Hatanaka | 79e1cdb | 2012-12-13 01:34:09 +0000 | [diff] [blame] | 563 | let DecoderNamespace = "Mips64" in |
Daniel Sanders | b8013ba | 2014-01-21 11:42:48 +0000 | [diff] [blame] | 564 | def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, |
Daniel Sanders | 0fa6041 | 2014-06-12 13:39:06 +0000 | [diff] [blame] | 565 | ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[IsFP64bit]>; |
Akira Hatanaka | a535270 | 2011-03-31 18:26:17 +0000 | [diff] [blame] | 566 | |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 567 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | e683bba | 2008-07-29 19:05:28 +0000 | [diff] [blame] | 568 | // Floating Point Pseudo-Instructions |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 569 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | a72a505 | 2009-05-27 17:23:44 +0000 | [diff] [blame] | 570 | |
Akira Hatanaka | 2791697 | 2011-04-15 19:52:08 +0000 | [diff] [blame] | 571 | // This pseudo instr gets expanded into 2 mtc1 instrs after register |
| 572 | // allocation. |
Akira Hatanaka | 9a1fb6b | 2013-08-20 23:47:25 +0000 | [diff] [blame] | 573 | class BuildPairF64Base<RegisterOperand RO> : |
| 574 | PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), |
| 575 | [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>; |
| 576 | |
| 577 | def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 578 | AdditionalRequires<[NotFP64bit]>; |
Akira Hatanaka | 9a1fb6b | 2013-08-20 23:47:25 +0000 | [diff] [blame] | 579 | def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 580 | AdditionalRequires<[IsFP64bit]>; |
Akira Hatanaka | 2791697 | 2011-04-15 19:52:08 +0000 | [diff] [blame] | 581 | |
| 582 | // This pseudo instr gets expanded into 2 mfc1 instrs after register |
| 583 | // allocation. |
| 584 | // if n is 0, lower part of src is extracted. |
| 585 | // if n is 1, higher part of src is extracted. |
Akira Hatanaka | 9a1fb6b | 2013-08-20 23:47:25 +0000 | [diff] [blame] | 586 | class ExtractElementF64Base<RegisterOperand RO> : |
| 587 | PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), |
| 588 | [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>; |
| 589 | |
| 590 | def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 591 | AdditionalRequires<[NotFP64bit]>; |
Akira Hatanaka | 9a1fb6b | 2013-08-20 23:47:25 +0000 | [diff] [blame] | 592 | def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, |
Daniel Sanders | 3dc2c01 | 2014-05-07 10:27:09 +0000 | [diff] [blame] | 593 | AdditionalRequires<[IsFP64bit]>; |
Akira Hatanaka | 2791697 | 2011-04-15 19:52:08 +0000 | [diff] [blame] | 594 | |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 595 | //===----------------------------------------------------------------------===// |
Akira Hatanaka | 1fb1b8b | 2013-07-26 20:13:47 +0000 | [diff] [blame] | 596 | // InstAliases. |
| 597 | //===----------------------------------------------------------------------===// |
Daniel Sanders | 3d3ea53 | 2014-06-12 15:00:17 +0000 | [diff] [blame] | 598 | def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, |
| 599 | ISA_MIPS1_NOT_32R6_64R6; |
| 600 | def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, |
| 601 | ISA_MIPS1_NOT_32R6_64R6; |
Akira Hatanaka | 1fb1b8b | 2013-07-26 20:13:47 +0000 | [diff] [blame] | 602 | |
| 603 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 7ceec57 | 2008-07-09 04:45:36 +0000 | [diff] [blame] | 604 | // Floating Point Patterns |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 605 | //===----------------------------------------------------------------------===// |
Akira Hatanaka | d8ab16b | 2012-06-14 21:03:23 +0000 | [diff] [blame] | 606 | def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; |
| 607 | def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; |
Bruno Cardoso Lopes | 2d7ddea | 2008-07-30 19:00:31 +0000 | [diff] [blame] | 608 | |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 609 | def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), |
| 610 | (PseudoCVT_S_W GPR32Opnd:$src)>; |
Akira Hatanaka | 00fcf2e | 2013-08-08 21:54:26 +0000 | [diff] [blame] | 611 | def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), |
| 612 | (TRUNC_W_S FGR32Opnd:$src)>; |
Bruno Cardoso Lopes | 2d7ddea | 2008-07-30 19:00:31 +0000 | [diff] [blame] | 613 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 614 | def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), |
| 615 | (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; |
| 616 | def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), |
| 617 | (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32; |
| 618 | def : MipsPat<(f32 (fround AFGR64Opnd:$src)), |
| 619 | (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; |
| 620 | def : MipsPat<(f64 (fextend FGR32Opnd:$src)), |
| 621 | (CVT_D32_S FGR32Opnd:$src)>, FGR_32; |
Bruno Cardoso Lopes | a72a505 | 2009-05-27 17:23:44 +0000 | [diff] [blame] | 622 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 623 | def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; |
| 624 | def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64; |
Akira Hatanaka | 2216f73 | 2011-11-07 21:38:58 +0000 | [diff] [blame] | 625 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 626 | def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), |
| 627 | (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; |
| 628 | def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), |
| 629 | (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64; |
| 630 | def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), |
| 631 | (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; |
Akira Hatanaka | 2216f73 | 2011-11-07 21:38:58 +0000 | [diff] [blame] | 632 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 633 | def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), |
| 634 | (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64; |
| 635 | def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), |
| 636 | (TRUNC_L_S FGR32Opnd:$src)>, FGR_64; |
| 637 | def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), |
| 638 | (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64; |
Akira Hatanaka | 2216f73 | 2011-11-07 21:38:58 +0000 | [diff] [blame] | 639 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 640 | def : MipsPat<(f32 (fround FGR64Opnd:$src)), |
| 641 | (CVT_S_D64 FGR64Opnd:$src)>, FGR_64; |
| 642 | def : MipsPat<(f64 (fextend FGR32Opnd:$src)), |
| 643 | (CVT_D64_S FGR32Opnd:$src)>, FGR_64; |
Akira Hatanaka | 69fb3d1 | 2013-02-15 21:20:45 +0000 | [diff] [blame] | 644 | |
Akira Hatanaka | b145730 | 2013-03-30 02:01:48 +0000 | [diff] [blame] | 645 | // Patterns for loads/stores with a reg+imm operand. |
Akira Hatanaka | 69fb3d1 | 2013-02-15 21:20:45 +0000 | [diff] [blame] | 646 | let AddedComplexity = 40 in { |
Daniel Sanders | f562582 | 2014-04-29 16:24:10 +0000 | [diff] [blame] | 647 | def : LoadRegImmPat<LWC1, f32, load>; |
| 648 | def : StoreRegImmPat<SWC1, f32>; |
Akira Hatanaka | 69fb3d1 | 2013-02-15 21:20:45 +0000 | [diff] [blame] | 649 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 650 | def : LoadRegImmPat<LDC164, f64, load>, FGR_64; |
| 651 | def : StoreRegImmPat<SDC164, f64>, FGR_64; |
Akira Hatanaka | 69fb3d1 | 2013-02-15 21:20:45 +0000 | [diff] [blame] | 652 | |
Daniel Sanders | 5b864d0 | 2014-05-07 14:25:43 +0000 | [diff] [blame] | 653 | def : LoadRegImmPat<LDC1, f64, load>, FGR_32; |
| 654 | def : StoreRegImmPat<SDC1, f64>, FGR_32; |
Akira Hatanaka | 69fb3d1 | 2013-02-15 21:20:45 +0000 | [diff] [blame] | 655 | } |