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gerrit-public.fairphone.software / toolchain / llvm-project / fcc213fab7b49ef0df671dea4db9605639365119 / . / llvm / lib / Target / AMDGPU / DSInstructions.td
blob: 2e81c59728d286e09aa6effafccab25ab65a1958 [file] [log] [blame]
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]1//===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11 InstSI <outs, ins, "", pattern>,
12 SIMCInstr <opName, SIEncodingFamily.NONE> {
13
14 let SubtargetPredicate = isGCN;
15
16 let LGKM_CNT = 1;
17 let DS = 1;
Matt Arsenault10c17ca2016-10-06 10:13:23 +0000[diff] [blame]18 let Size = 8;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]19 let UseNamedOperandTable = 1;
20 let Uses = [M0, EXEC];
21
22 // Most instruction load and store data, so set this as the default.
23 let mayLoad = 1;
24 let mayStore = 1;
25
26 let hasSideEffects = 0;
27 let SchedRW = [WriteLDS];
28
29 let isPseudo = 1;
30 let isCodeGenOnly = 1;
31
32 let AsmMatchConverter = "cvtDS";
33
34 string Mnemonic = opName;
35 string AsmOperands = asmOps;
36
37 // Well these bits a kind of hack because it would be more natural
38 // to test "outs" and "ins" dags for the presence of particular operands
39 bits<1> has_vdst = 1;
40 bits<1> has_addr = 1;
41 bits<1> has_data0 = 1;
42 bits<1> has_data1 = 1;
43
44 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
45 bits<1> has_offset0 = 1;
46 bits<1> has_offset1 = 1;
47
48 bits<1> has_gds = 1;
49 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
50}
51
52class DS_Real <DS_Pseudo ds> :
53 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
54 Enc64 {
55
56 let isPseudo = 0;
57 let isCodeGenOnly = 0;
58
59 // copy relevant pseudo op flags
60 let SubtargetPredicate = ds.SubtargetPredicate;
61 let AsmMatchConverter = ds.AsmMatchConverter;
62
63 // encoding fields
64 bits<8> vdst;
65 bits<1> gds;
66 bits<8> addr;
67 bits<8> data0;
68 bits<8> data1;
69 bits<8> offset0;
70 bits<8> offset1;
71
72 bits<16> offset;
73 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
74 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
75}
76
77
78// DS Pseudo instructions
79
80class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
81: DS_Pseudo<opName,
82 (outs),
83 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
84 "$addr, $data0$offset$gds">,
85 AtomicNoRet<opName, 0> {
86
87 let has_data1 = 0;
88 let has_vdst = 0;
89}
90
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]91class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]92: DS_Pseudo<opName,
93 (outs),
94 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
95 "$addr, $data0, $data1"#"$offset"#"$gds">,
96 AtomicNoRet<opName, 0> {
97
98 let has_vdst = 0;
99}
100
101class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
102: DS_Pseudo<opName,
103 (outs),
104 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
105 offset0:$offset0, offset1:$offset1, gds:$gds),
106 "$addr, $data0, $data1$offset0$offset1$gds"> {
107
108 let has_vdst = 0;
109 let has_offset = 0;
110 let AsmMatchConverter = "cvtDSOffset01";
111}
112
113class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
114: DS_Pseudo<opName,
115 (outs rc:$vdst),
116 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
117 "$vdst, $addr, $data0$offset$gds"> {
118
119 let hasPostISelHook = 1;
120 let has_data1 = 0;
121}
122
123class DS_1A2D_RET<string opName,
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]124 RegisterClass rc = VGPR_32,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]125 RegisterClass src = rc>
126: DS_Pseudo<opName,
127 (outs rc:$vdst),
128 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
129 "$vdst, $addr, $data0, $data1$offset$gds"> {
130
131 let hasPostISelHook = 1;
132}
133
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]134class DS_1A2D_Off8_RET<string opName,
135 RegisterClass rc = VGPR_32,
136 RegisterClass src = rc>
137: DS_Pseudo<opName,
138 (outs rc:$vdst),
139 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
140 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
141
142 let has_offset = 0;
143 let AsmMatchConverter = "cvtDSOffset01";
144
145 let hasPostISelHook = 1;
146}
147
Dmitry Preobrazhensky793c5922017-05-31 16:26:47 +0000[diff] [blame]148class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, Operand ofs = offset>
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]149: DS_Pseudo<opName,
150 (outs rc:$vdst),
Dmitry Preobrazhensky793c5922017-05-31 16:26:47 +0000[diff] [blame]151 (ins VGPR_32:$addr, ofs:$offset, gds:$gds),
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]152 "$vdst, $addr$offset$gds"> {
153
154 let has_data0 = 0;
155 let has_data1 = 0;
156}
157
158class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
159: DS_Pseudo<opName,
160 (outs rc:$vdst),
161 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
162 "$vdst, $addr$offset0$offset1$gds"> {
163
164 let has_offset = 0;
165 let has_data0 = 0;
166 let has_data1 = 0;
167 let AsmMatchConverter = "cvtDSOffset01";
168}
169
170class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
171 (outs VGPR_32:$vdst),
172 (ins VGPR_32:$addr, offset:$offset),
173 "$vdst, $addr$offset gds"> {
174
175 let has_data0 = 0;
176 let has_data1 = 0;
177 let has_gds = 0;
178 let gdsValue = 1;
Artem Tamazov43b61562017-02-03 12:47:30 +0000[diff] [blame]179 let AsmMatchConverter = "cvtDSGds";
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]180}
181
182class DS_0A_RET <string opName> : DS_Pseudo<opName,
183 (outs VGPR_32:$vdst),
184 (ins offset:$offset, gds:$gds),
185 "$vdst$offset$gds"> {
186
187 let mayLoad = 1;
188 let mayStore = 1;
189
190 let has_addr = 0;
191 let has_data0 = 0;
192 let has_data1 = 0;
193}
194
195class DS_1A <string opName> : DS_Pseudo<opName,
196 (outs),
197 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
198 "$addr$offset$gds"> {
199
200 let mayLoad = 1;
201 let mayStore = 1;
202
203 let has_vdst = 0;
204 let has_data0 = 0;
205 let has_data1 = 0;
206}
207
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]208class DS_GWS <string opName, dag ins, string asmOps>
209: DS_Pseudo<opName, (outs), ins, asmOps> {
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]210
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]211 let has_vdst = 0;
212 let has_addr = 0;
213 let has_data0 = 0;
214 let has_data1 = 0;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]215
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]216 let has_gds = 0;
217 let gdsValue = 1;
218 let AsmMatchConverter = "cvtDSGds";
219}
220
221class DS_GWS_0D <string opName>
222: DS_GWS<opName,
223 (ins offset:$offset, gds:$gds), "$offset gds">;
224
225class DS_GWS_1D <string opName>
226: DS_GWS<opName,
227 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
228
229 let has_data0 = 1;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]230}
231
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]232class DS_VOID <string opName> : DS_Pseudo<opName,
233 (outs), (ins), ""> {
234 let mayLoad = 0;
235 let mayStore = 0;
236 let hasSideEffects = 1;
237 let UseNamedOperandTable = 0;
238 let AsmMatchConverter = "";
239
240 let has_vdst = 0;
241 let has_addr = 0;
242 let has_data0 = 0;
243 let has_data1 = 0;
244 let has_offset = 0;
245 let has_offset0 = 0;
246 let has_offset1 = 0;
247 let has_gds = 0;
248}
249
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]250class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
251: DS_Pseudo<opName,
252 (outs VGPR_32:$vdst),
253 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
254 "$vdst, $addr, $data0$offset",
255 [(set i32:$vdst,
256 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
257
258 let mayLoad = 0;
259 let mayStore = 0;
260 let isConvergent = 1;
261
262 let has_data1 = 0;
263 let has_gds = 0;
264}
265
266def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">;
267def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">;
268def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">;
269def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">;
270def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">;
271def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
272def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
273def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
274def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
275def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
276def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
277def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]278def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]279def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">;
280def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]281
282let mayLoad = 0 in {
283def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
284def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
285def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
286def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
287def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000[diff] [blame]288
289let SubtargetPredicate = HasD16LoadStore in {
290def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
291def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
292}
293
Matt Arsenaultefa1d652017-09-01 18:38:02 +0000[diff] [blame]294let SubtargetPredicate = HasDSAddTid in {
295def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">;
296}
297
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]298}
299
300def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
301def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
302def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]303
304def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
305def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
306def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
307def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
308def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
309def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
310def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
311def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>;
312def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>;
313def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>;
314def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>;
315def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>;
316def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>;
317let mayLoad = 0 in {
318def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>;
319def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>;
320def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>;
321}
322def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
323def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
324def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
325def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
326
327def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
328 AtomicNoRet<"ds_add_u32", 1>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]329def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
330 AtomicNoRet<"ds_add_f32", 1>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]331def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
332 AtomicNoRet<"ds_sub_u32", 1>;
333def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
334 AtomicNoRet<"ds_rsub_u32", 1>;
335def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">,
336 AtomicNoRet<"ds_inc_u32", 1>;
337def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">,
338 AtomicNoRet<"ds_dec_u32", 1>;
339def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">,
340 AtomicNoRet<"ds_min_i32", 1>;
341def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">,
342 AtomicNoRet<"ds_max_i32", 1>;
343def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">,
344 AtomicNoRet<"ds_min_u32", 1>;
345def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">,
346 AtomicNoRet<"ds_max_u32", 1>;
347def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">,
348 AtomicNoRet<"ds_and_b32", 1>;
349def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">,
350 AtomicNoRet<"ds_or_b32", 1>;
351def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">,
352 AtomicNoRet<"ds_xor_b32", 1>;
353def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">,
354 AtomicNoRet<"ds_mskor_b32", 1>;
355def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
356 AtomicNoRet<"ds_cmpst_b32", 1>;
357def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
358 AtomicNoRet<"ds_cmpst_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]359def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]360 AtomicNoRet<"ds_min_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]361def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]362 AtomicNoRet<"ds_max_f32", 1>;
363
364def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
365 AtomicNoRet<"", 1>;
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]366def DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]367 AtomicNoRet<"", 1>;
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]368def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]369 AtomicNoRet<"", 1>;
370
371def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
372 AtomicNoRet<"ds_add_u64", 1>;
373def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
374 AtomicNoRet<"ds_sub_u64", 1>;
375def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
376 AtomicNoRet<"ds_rsub_u64", 1>;
377def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
378 AtomicNoRet<"ds_inc_u64", 1>;
379def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
380 AtomicNoRet<"ds_dec_u64", 1>;
381def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
382 AtomicNoRet<"ds_min_i64", 1>;
383def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
384 AtomicNoRet<"ds_max_i64", 1>;
385def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
386 AtomicNoRet<"ds_min_u64", 1>;
387def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
388 AtomicNoRet<"ds_max_u64", 1>;
389def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
390 AtomicNoRet<"ds_and_b64", 1>;
391def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
392 AtomicNoRet<"ds_or_b64", 1>;
393def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
394 AtomicNoRet<"ds_xor_b64", 1>;
395def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
396 AtomicNoRet<"ds_mskor_b64", 1>;
397def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
398 AtomicNoRet<"ds_cmpst_b64", 1>;
399def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
400 AtomicNoRet<"ds_cmpst_f64", 1>;
401def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
402 AtomicNoRet<"ds_min_f64", 1>;
403def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
404 AtomicNoRet<"ds_max_f64", 1>;
405
406def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]407 AtomicNoRet<"", 1>;
408def DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
409 AtomicNoRet<"", 1>;
410def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
411 AtomicNoRet<"", 1>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]412
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]413def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
414def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
415def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
416def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
417def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]418
419def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
420def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
421def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
422def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
423def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
424def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
425def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
426def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
427def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]428def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]429def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
430def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
431def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
432def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
433
434def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
435def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
436def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
437def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
438def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
439def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
440def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
441def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
442def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
443def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
444def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
445def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
446def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
447def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
448
Dmitry Preobrazhenskye6ef0992017-04-14 12:28:07 +0000[diff] [blame]449def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
450def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]451
452let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
Dmitry Preobrazhensky793c5922017-05-31 16:26:47 +0000[diff] [blame]453def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, SwizzleImm>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]454}
455
456let mayStore = 0 in {
457def DS_READ_I8 : DS_1A_RET<"ds_read_i8">;
458def DS_READ_U8 : DS_1A_RET<"ds_read_u8">;
459def DS_READ_I16 : DS_1A_RET<"ds_read_i16">;
460def DS_READ_U16 : DS_1A_RET<"ds_read_u16">;
461def DS_READ_B32 : DS_1A_RET<"ds_read_b32">;
462def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>;
463
464def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>;
465def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>;
466
467def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
468def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000[diff] [blame]469
470let SubtargetPredicate = HasD16LoadStore in {
471def DS_READ_U8_D16 : DS_1A_RET<"ds_read_u8_d16">;
472def DS_READ_U8_D16_HI : DS_1A_RET<"ds_read_u8_d16_hi">;
473def DS_READ_I8_D16 : DS_1A_RET<"ds_read_i8_d16">;
474def DS_READ_I8_D16_HI : DS_1A_RET<"ds_read_i8_d16_hi">;
475def DS_READ_U16_D16 : DS_1A_RET<"ds_read_u16_d16">;
476def DS_READ_U16_D16_HI : DS_1A_RET<"ds_read_u16_d16_hi">;
477}
Matt Arsenaultefa1d652017-09-01 18:38:02 +0000[diff] [blame]478
479let SubtargetPredicate = HasDSAddTid in {
480def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">;
481}
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]482}
483
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]484def DS_CONSUME : DS_0A_RET<"ds_consume">;
485def DS_APPEND : DS_0A_RET<"ds_append">;
486def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]487
488//===----------------------------------------------------------------------===//
489// Instruction definitions for CI and newer.
490//===----------------------------------------------------------------------===//
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]491
492let SubtargetPredicate = isCIVI in {
493
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]494def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>;
495
496def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>,
497 AtomicNoRet<"", 1>;
498
499def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]500
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]501let mayStore = 0 in {
502def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>;
503def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>;
504} // End mayStore = 0
505
506let mayLoad = 0 in {
507def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>;
508def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>;
509} // End mayLoad = 0
510
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]511def DS_NOP : DS_VOID<"ds_nop">;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]512
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]513} // let SubtargetPredicate = isCIVI
514
515//===----------------------------------------------------------------------===//
516// Instruction definitions for VI and newer.
517//===----------------------------------------------------------------------===//
518
519let SubtargetPredicate = isVI in {
520
521let Uses = [EXEC] in {
522def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
523 int_amdgcn_ds_permute>;
524def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
525 int_amdgcn_ds_bpermute>;
526}
527
528} // let SubtargetPredicate = isVI
529
530//===----------------------------------------------------------------------===//
531// DS Patterns
532//===----------------------------------------------------------------------===//
533
534let Predicates = [isGCN] in {
535
536def : Pat <
537 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
538 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
539>;
540
541class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
542 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
543 (inst $ptr, (as_i16imm $offset), (i1 0))
544>;
545
546def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>;
547def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]548def : DSReadPat <DS_READ_I8, i16, si_sextload_local_i8>;
549def : DSReadPat <DS_READ_U8, i16, si_az_extload_local_i8>;
550def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]551def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
552def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]553def : DSReadPat <DS_READ_U16, i16, si_load_local>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]554def : DSReadPat <DS_READ_B32, i32, si_load_local>;
555
556let AddedComplexity = 100 in {
557
558def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>;
559
560} // End AddedComplexity = 100
561
562def : Pat <
563 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
564 i8:$offset1))),
565 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
566>;
567
568class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
569 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
570 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
571>;
572
573def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>;
574def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]575def : DSWritePat <DS_WRITE_B8, i16, si_truncstore_local_i8>;
576def : DSWritePat <DS_WRITE_B16, i16, si_store_local>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]577def : DSWritePat <DS_WRITE_B32, i32, si_store_local>;
578
Matt Arsenaultfcc213f2017-09-20 03:20:09 +0000[diff] [blame^]579let Predicates = [HasD16LoadStore] in {
580def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_local_hi16>;
581def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_local_hi16>;
582}
583
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]584let AddedComplexity = 100 in {
585
586def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>;
587} // End AddedComplexity = 100
588
589def : Pat <
590 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
591 i8:$offset1)),
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]592 (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
593 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]594 (i1 0))
595>;
596
597class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
598 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
599 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
600>;
601
602class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
603 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
604 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
605>;
606
607
608// 32-bit atomics.
609def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>;
610def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>;
611def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>;
612def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>;
613def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>;
614def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>;
615def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>;
616def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>;
617def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>;
618def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>;
619def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>;
620def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>;
621def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>;
622
623// 64-bit atomics.
624def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>;
625def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>;
626def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>;
627def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>;
628def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>;
629def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>;
630def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>;
631def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>;
632def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>;
633def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>;
634def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>;
635def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>;
636
637def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
638
639} // let Predicates = [isGCN]
640
641//===----------------------------------------------------------------------===//
642// Real instructions
643//===----------------------------------------------------------------------===//
644
645//===----------------------------------------------------------------------===//
646// SIInstructions.td
647//===----------------------------------------------------------------------===//
648
649class DS_Real_si <bits<8> op, DS_Pseudo ds> :
650 DS_Real <ds>,
651 SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
652 let AssemblerPredicates=[isSICI];
653 let DecoderNamespace="SICI";
654
655 // encoding
656 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
657 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
658 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
659 let Inst{25-18} = op;
660 let Inst{31-26} = 0x36; // ds prefix
661 let Inst{39-32} = !if(ds.has_addr, addr, 0);
662 let Inst{47-40} = !if(ds.has_data0, data0, 0);
663 let Inst{55-48} = !if(ds.has_data1, data1, 0);
664 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
665}
666
667def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>;
668def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>;
669def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>;
670def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
671def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>;
672def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>;
673def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>;
674def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>;
675def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>;
676def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>;
677def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
678def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>;
679def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>;
680def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>;
681def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>;
682def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>;
683def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>;
684def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>;
685def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>;
686def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]687def DS_NOP_si : DS_Real_si<0x14, DS_NOP>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]688def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>;
689def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
690def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
691def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
692def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>;
693def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
694def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>;
695def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>;
696def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>;
697def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
698def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>;
699def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>;
700def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>;
701def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>;
702def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>;
703def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>;
704def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
705def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>;
706def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
707def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
708def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
709def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
710def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
711def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
712def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
713def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
714def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
715
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]716// These instruction are CI/VI only
717def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>;
718def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>;
719def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]720
721def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
722def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
723def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>;
724def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>;
725def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>;
726def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>;
727def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
728def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>;
729def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>;
730def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
731def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
732def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>;
733def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>;
734def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>;
735def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>;
736def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>;
737def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>;
738def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>;
739def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>;
740def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>;
741def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>;
742def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>;
743def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>;
744def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>;
745def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>;
746def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>;
747def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
748def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>;
749def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>;
750def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>;
751def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>;
752
753def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>;
754def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>;
755def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
756def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>;
757def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>;
758def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>;
759def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>;
760def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>;
761def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>;
762def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>;
763def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>;
764def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
765def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
766def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
767def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
768def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
769def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
770def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
771def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>;
772def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>;
773
774def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>;
775def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>;
776def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>;
777
778def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
779def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
780def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
781def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>;
782def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
783def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
784def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
785def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
786def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
787def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>;
788def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
789def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
790def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
791
792def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
793def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
794
795def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
796def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
797def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
798def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
799def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
800def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
801def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
802def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
803def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
804def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
805def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>;
806def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
807def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
808
809def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
810def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]811def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>;
812def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>;
813def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>;
814def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]815
816//===----------------------------------------------------------------------===//
817// VIInstructions.td
818//===----------------------------------------------------------------------===//
819
820class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
821 DS_Real <ds>,
822 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
823 let AssemblerPredicates = [isVI];
824 let DecoderNamespace="VI";
825
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]826 // encoding
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]827 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
828 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
829 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
830 let Inst{24-17} = op;
831 let Inst{31-26} = 0x36; // ds prefix
832 let Inst{39-32} = !if(ds.has_addr, addr, 0);
833 let Inst{47-40} = !if(ds.has_data0, data0, 0);
834 let Inst{55-48} = !if(ds.has_data1, data1, 0);
835 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
836}
837
838def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
839def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
840def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
841def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
842def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
843def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
844def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
845def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
846def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
847def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
848def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
849def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
850def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
851def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
852def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
853def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
854def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
855def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
856def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
857def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]858def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]859def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]860def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
861def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
862def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
863def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
864def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
Matt Arsenaultefa1d652017-09-01 18:38:02 +0000[diff] [blame]865def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]866def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
867def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
868def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
869def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
870def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
871def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
872def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
873def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
874def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
875def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
876def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
877def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
878def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
879def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
880def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
881def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
882def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
883def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
884def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
885def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
886def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
887def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]888def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]889def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]890def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
891def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
892def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
893def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
894def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
895def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
896def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
Matt Arsenaultefa1d652017-09-01 18:38:02 +0000[diff] [blame]897def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]898def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
899def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
900def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]901def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
902def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
903def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
904
905def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
906def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
907def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
908def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
909def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
910def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
911def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
912def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
913def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
914def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
915def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
916def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
917def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
918def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
919def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
920def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
921def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
922def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
923def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
924def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
925
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000[diff] [blame]926def DS_WRITE_B8_D16_HI_vi : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
927def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
928
929def DS_READ_U8_D16_vi : DS_Real_vi<0x56, DS_READ_U8_D16>;
930def DS_READ_U8_D16_HI_vi : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
931def DS_READ_I8_D16_vi : DS_Real_vi<0x58, DS_READ_I8_D16>;
932def DS_READ_I8_D16_HI_vi : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
933def DS_READ_U16_D16_vi : DS_Real_vi<0x5a, DS_READ_U16_D16>;
934def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
935
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]936def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
937def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
938def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
939def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
940def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
941def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
942def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
943def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
944def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
945def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
946def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
947def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
948def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
949def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
950def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
951def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]952def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
953def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]954def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
955def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
956def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
957def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
958
959def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
960def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
961def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
962
963def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
964def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
965def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
966def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
967def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
968def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
969def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
970def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
971def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
972def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
973def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
974def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
975def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
976def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
977def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
978def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
979def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
980def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
981def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
982def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
983def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
984def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
985def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
986def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
987def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
988def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
989def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
990def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
991def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
992def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]993def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>;
994def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>;
995def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>;
996def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>;