blob: ac26acfdb65d61e190fdefe1180e52428625b533 [file] [log] [blame]
Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/platform_device.h>
17#include <linux/msm_rotator.h>
Joel Nidere5de00e2012-07-03 10:58:10 +030018#include <linux/gpio.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/clkdev.h>
Hemant Kumard86c4882012-01-24 19:39:37 -080020#include <linux/dma-mapping.h>
Pratik Patel1746b8f2012-06-02 21:11:41 -070021#include <linux/coresight.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070022#include <mach/irqs-8064.h>
23#include <mach/board.h>
24#include <mach/msm_iomap.h>
Yan He06913ce2011-08-26 16:33:46 -070025#include <mach/usbdiag.h>
26#include <mach/msm_sps.h>
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -070027#include <mach/dma.h>
Jin Hongd3024e62012-02-09 16:13:32 -080028#include <mach/msm_dsps.h>
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -080029#include <sound/msm-dai-q6.h>
30#include <sound/apr_audio.h>
Joel Nidere5de00e2012-07-03 10:58:10 +030031#include <mach/msm_tsif.h>
Gagan Mac8a7a5d32011-11-11 16:43:06 -070032#include <mach/msm_bus_board.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060033#include <mach/rpm.h>
Joel Kingdacbc822012-01-25 13:30:57 -080034#include <mach/mdm2.h>
Eric Holmberg023d25c2012-03-01 12:27:55 -070035#include <mach/msm_smd.h>
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -070036#include <mach/msm_dcvs.h>
Laura Abbott532b2df2012-04-12 10:53:48 -070037#include <mach/msm_rtb.h>
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -080038#include <linux/ion.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070039#include "clock.h"
40#include "devices.h"
Matt Wagantall1875d322012-02-22 16:11:33 -080041#include "footswitch.h"
Jeff Ohlstein7e668552011-10-06 16:17:25 -070042#include "msm_watchdog.h"
Praveen Chidambaram78499012011-11-01 17:15:17 -060043#include "rpm_stats.h"
44#include "rpm_log.h"
Subhash Jadavani909e04f2012-04-12 10:52:50 +053045#include <mach/mpm.h>
Laura Abbott0577d7b2012-04-17 11:14:30 -070046#include <mach/iommu_domains.h>
Laura Abbott93a4a352012-05-25 09:26:35 -070047#include <mach/msm_cache_dump.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070048
49/* Address of GSBI blocks */
Stepan Moskovchenko2701a442011-08-19 13:47:22 -070050#define MSM_GSBI1_PHYS 0x12440000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070051#define MSM_GSBI3_PHYS 0x16200000
Harini Jayaramanc4c58692011-07-19 14:50:10 -060052#define MSM_GSBI4_PHYS 0x16300000
53#define MSM_GSBI5_PHYS 0x1A200000
54#define MSM_GSBI6_PHYS 0x16500000
55#define MSM_GSBI7_PHYS 0x16600000
56
Kenneth Heitke748593a2011-07-15 15:45:11 -060057/* GSBI UART devices */
Stepan Moskovchenko2701a442011-08-19 13:47:22 -070058#define MSM_UART1DM_PHYS (MSM_GSBI1_PHYS + 0x10000)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070059#define MSM_UART3DM_PHYS (MSM_GSBI3_PHYS + 0x40000)
Jin Hong4bbbfba2012-02-02 21:48:07 -080060#define MSM_UART7DM_PHYS (MSM_GSBI7_PHYS + 0x40000)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070061
Harini Jayaramanc4c58692011-07-19 14:50:10 -060062/* GSBI QUP devices */
David Keitel3c40fc52012-02-09 17:53:52 -080063#define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x20000)
Harini Jayaramanc4c58692011-07-19 14:50:10 -060064#define MSM_GSBI3_QUP_PHYS (MSM_GSBI3_PHYS + 0x80000)
65#define MSM_GSBI4_QUP_PHYS (MSM_GSBI4_PHYS + 0x80000)
66#define MSM_GSBI5_QUP_PHYS (MSM_GSBI5_PHYS + 0x80000)
67#define MSM_GSBI6_QUP_PHYS (MSM_GSBI6_PHYS + 0x80000)
68#define MSM_GSBI7_QUP_PHYS (MSM_GSBI7_PHYS + 0x80000)
69#define MSM_QUP_SIZE SZ_4K
70
Kenneth Heitke36920d32011-07-20 16:44:30 -060071/* Address of SSBI CMD */
72#define MSM_PMIC1_SSBI_CMD_PHYS 0x00500000
73#define MSM_PMIC2_SSBI_CMD_PHYS 0x00C00000
74#define MSM_PMIC_SSBI_SIZE SZ_4K
Harini Jayaramanc4c58692011-07-19 14:50:10 -060075
Hemant Kumarcaa09092011-07-30 00:26:33 -070076/* Address of HS USBOTG1 */
Hemant Kumard86c4882012-01-24 19:39:37 -080077#define MSM_HSUSB1_PHYS 0x12500000
78#define MSM_HSUSB1_SIZE SZ_4K
Hemant Kumarcaa09092011-07-30 00:26:33 -070079
Manu Gautam91223e02011-11-08 15:27:22 +053080/* Address of HS USB3 */
81#define MSM_HSUSB3_PHYS 0x12520000
82#define MSM_HSUSB3_SIZE SZ_4K
83
Hemant Kumar1d66e1c2012-02-13 15:24:59 -080084/* Address of HS USB4 */
85#define MSM_HSUSB4_PHYS 0x12530000
86#define MSM_HSUSB4_SIZE SZ_4K
87
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -060088/* Address of PCIE20 PARF */
89#define PCIE20_PARF_PHYS 0x1b600000
90#define PCIE20_PARF_SIZE SZ_128
91
92/* Address of PCIE20 ELBI */
93#define PCIE20_ELBI_PHYS 0x1b502000
94#define PCIE20_ELBI_SIZE SZ_256
95
96/* Address of PCIE20 */
97#define PCIE20_PHYS 0x1b500000
98#define PCIE20_SIZE SZ_4K
99
Jeff Ohlstein7e668552011-10-06 16:17:25 -0700100static struct msm_watchdog_pdata msm_watchdog_pdata = {
101 .pet_time = 10000,
102 .bark_time = 11000,
103 .has_secure = true,
Joel Kinge7ca6f72012-02-09 20:51:25 -0800104 .needs_expired_enable = true,
Jeff Ohlstein7e668552011-10-06 16:17:25 -0700105};
106
107struct platform_device msm8064_device_watchdog = {
108 .name = "msm_watchdog",
109 .id = -1,
110 .dev = {
111 .platform_data = &msm_watchdog_pdata,
112 },
113};
114
Joel King0581896d2011-07-19 16:43:28 -0700115static struct resource msm_dmov_resource[] = {
116 {
Jeff Ohlstein4af72692011-11-07 15:59:17 -0800117 .start = ADM_0_SCSS_1_IRQ,
Joel King0581896d2011-07-19 16:43:28 -0700118 .flags = IORESOURCE_IRQ,
119 },
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -0700120 {
Jeff Ohlstein4af72692011-11-07 15:59:17 -0800121 .start = 0x18320000,
122 .end = 0x18320000 + SZ_1M - 1,
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -0700123 .flags = IORESOURCE_MEM,
124 },
125};
126
127static struct msm_dmov_pdata msm_dmov_pdata = {
Jeff Ohlstein4af72692011-11-07 15:59:17 -0800128 .sd = 1,
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -0700129 .sd_size = 0x800,
Joel King0581896d2011-07-19 16:43:28 -0700130};
131
Stepan Moskovchenkodf13d342011-08-03 19:01:25 -0700132struct platform_device apq8064_device_dmov = {
Joel King0581896d2011-07-19 16:43:28 -0700133 .name = "msm_dmov",
134 .id = -1,
135 .resource = msm_dmov_resource,
136 .num_resources = ARRAY_SIZE(msm_dmov_resource),
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -0700137 .dev = {
138 .platform_data = &msm_dmov_pdata,
139 },
Joel King0581896d2011-07-19 16:43:28 -0700140};
141
Stepan Moskovchenko2701a442011-08-19 13:47:22 -0700142static struct resource resources_uart_gsbi1[] = {
143 {
144 .start = APQ8064_GSBI1_UARTDM_IRQ,
145 .end = APQ8064_GSBI1_UARTDM_IRQ,
146 .flags = IORESOURCE_IRQ,
147 },
148 {
149 .start = MSM_UART1DM_PHYS,
150 .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1,
151 .name = "uartdm_resource",
152 .flags = IORESOURCE_MEM,
153 },
154 {
155 .start = MSM_GSBI1_PHYS,
156 .end = MSM_GSBI1_PHYS + PAGE_SIZE - 1,
157 .name = "gsbi_resource",
158 .flags = IORESOURCE_MEM,
159 },
160};
161
162struct platform_device apq8064_device_uart_gsbi1 = {
163 .name = "msm_serial_hsl",
Jin Hong4bbbfba2012-02-02 21:48:07 -0800164 .id = 1,
Stepan Moskovchenko2701a442011-08-19 13:47:22 -0700165 .num_resources = ARRAY_SIZE(resources_uart_gsbi1),
166 .resource = resources_uart_gsbi1,
167};
168
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700169static struct resource resources_uart_gsbi3[] = {
170 {
171 .start = GSBI3_UARTDM_IRQ,
172 .end = GSBI3_UARTDM_IRQ,
173 .flags = IORESOURCE_IRQ,
174 },
175 {
176 .start = MSM_UART3DM_PHYS,
177 .end = MSM_UART3DM_PHYS + PAGE_SIZE - 1,
178 .name = "uartdm_resource",
179 .flags = IORESOURCE_MEM,
180 },
181 {
182 .start = MSM_GSBI3_PHYS,
183 .end = MSM_GSBI3_PHYS + PAGE_SIZE - 1,
184 .name = "gsbi_resource",
185 .flags = IORESOURCE_MEM,
186 },
187};
188
189struct platform_device apq8064_device_uart_gsbi3 = {
190 .name = "msm_serial_hsl",
191 .id = 0,
192 .num_resources = ARRAY_SIZE(resources_uart_gsbi3),
193 .resource = resources_uart_gsbi3,
194};
195
Jing Lin04601f92012-02-05 15:36:07 -0800196static struct resource resources_qup_i2c_gsbi3[] = {
197 {
198 .name = "gsbi_qup_i2c_addr",
199 .start = MSM_GSBI3_PHYS,
200 .end = MSM_GSBI3_PHYS + 4 - 1,
201 .flags = IORESOURCE_MEM,
202 },
203 {
204 .name = "qup_phys_addr",
205 .start = MSM_GSBI3_QUP_PHYS,
206 .end = MSM_GSBI3_QUP_PHYS + MSM_QUP_SIZE - 1,
207 .flags = IORESOURCE_MEM,
208 },
209 {
210 .name = "qup_err_intr",
211 .start = GSBI3_QUP_IRQ,
212 .end = GSBI3_QUP_IRQ,
213 .flags = IORESOURCE_IRQ,
214 },
215 {
216 .name = "i2c_clk",
217 .start = 9,
218 .end = 9,
219 .flags = IORESOURCE_IO,
220 },
221 {
222 .name = "i2c_sda",
223 .start = 8,
224 .end = 8,
225 .flags = IORESOURCE_IO,
226 },
227};
228
David Keitel3c40fc52012-02-09 17:53:52 -0800229static struct resource resources_qup_i2c_gsbi1[] = {
230 {
231 .name = "gsbi_qup_i2c_addr",
232 .start = MSM_GSBI1_PHYS,
233 .end = MSM_GSBI1_PHYS + 4 - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 {
237 .name = "qup_phys_addr",
238 .start = MSM_GSBI1_QUP_PHYS,
239 .end = MSM_GSBI1_QUP_PHYS + MSM_QUP_SIZE - 1,
240 .flags = IORESOURCE_MEM,
241 },
242 {
243 .name = "qup_err_intr",
244 .start = APQ8064_GSBI1_QUP_IRQ,
245 .end = APQ8064_GSBI1_QUP_IRQ,
246 .flags = IORESOURCE_IRQ,
247 },
248 {
249 .name = "i2c_clk",
250 .start = 21,
251 .end = 21,
252 .flags = IORESOURCE_IO,
253 },
254 {
255 .name = "i2c_sda",
256 .start = 20,
257 .end = 20,
258 .flags = IORESOURCE_IO,
259 },
260};
261
262struct platform_device apq8064_device_qup_i2c_gsbi1 = {
263 .name = "qup_i2c",
264 .id = 0,
265 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi1),
266 .resource = resources_qup_i2c_gsbi1,
267};
268
Jing Lin04601f92012-02-05 15:36:07 -0800269struct platform_device apq8064_device_qup_i2c_gsbi3 = {
270 .name = "qup_i2c",
271 .id = 3,
272 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi3),
273 .resource = resources_qup_i2c_gsbi3,
274};
275
Kenneth Heitke748593a2011-07-15 15:45:11 -0600276static struct resource resources_qup_i2c_gsbi4[] = {
277 {
278 .name = "gsbi_qup_i2c_addr",
279 .start = MSM_GSBI4_PHYS,
Harini Jayaramane1554a92011-09-15 14:43:02 -0600280 .end = MSM_GSBI4_PHYS + 4 - 1,
Kenneth Heitke748593a2011-07-15 15:45:11 -0600281 .flags = IORESOURCE_MEM,
282 },
283 {
284 .name = "qup_phys_addr",
285 .start = MSM_GSBI4_QUP_PHYS,
Harini Jayaramane1554a92011-09-15 14:43:02 -0600286 .end = MSM_GSBI4_QUP_PHYS + MSM_QUP_SIZE - 1,
Kenneth Heitke748593a2011-07-15 15:45:11 -0600287 .flags = IORESOURCE_MEM,
288 },
289 {
290 .name = "qup_err_intr",
291 .start = GSBI4_QUP_IRQ,
292 .end = GSBI4_QUP_IRQ,
293 .flags = IORESOURCE_IRQ,
294 },
Kevin Chand07220e2012-02-13 15:52:22 -0800295 {
296 .name = "i2c_clk",
297 .start = 11,
298 .end = 11,
299 .flags = IORESOURCE_IO,
300 },
301 {
302 .name = "i2c_sda",
303 .start = 10,
304 .end = 10,
305 .flags = IORESOURCE_IO,
306 },
Kenneth Heitke748593a2011-07-15 15:45:11 -0600307};
308
309struct platform_device apq8064_device_qup_i2c_gsbi4 = {
310 .name = "qup_i2c",
311 .id = 4,
312 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi4),
313 .resource = resources_qup_i2c_gsbi4,
314};
315
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700316static struct resource resources_qup_spi_gsbi5[] = {
317 {
318 .name = "spi_base",
319 .start = MSM_GSBI5_QUP_PHYS,
320 .end = MSM_GSBI5_QUP_PHYS + SZ_4K - 1,
321 .flags = IORESOURCE_MEM,
322 },
323 {
324 .name = "gsbi_base",
325 .start = MSM_GSBI5_PHYS,
326 .end = MSM_GSBI5_PHYS + 4 - 1,
327 .flags = IORESOURCE_MEM,
328 },
329 {
330 .name = "spi_irq_in",
331 .start = GSBI5_QUP_IRQ,
332 .end = GSBI5_QUP_IRQ,
333 .flags = IORESOURCE_IRQ,
334 },
335};
336
337struct platform_device apq8064_device_qup_spi_gsbi5 = {
338 .name = "spi_qsd",
339 .id = 0,
340 .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi5),
341 .resource = resources_qup_spi_gsbi5,
342};
343
Joel King8f839b92012-04-01 14:37:46 -0700344static struct resource resources_qup_i2c_gsbi5[] = {
345 {
346 .name = "gsbi_qup_i2c_addr",
347 .start = MSM_GSBI5_PHYS,
348 .end = MSM_GSBI5_PHYS + 4 - 1,
349 .flags = IORESOURCE_MEM,
350 },
351 {
352 .name = "qup_phys_addr",
353 .start = MSM_GSBI5_QUP_PHYS,
354 .end = MSM_GSBI5_QUP_PHYS + MSM_QUP_SIZE - 1,
355 .flags = IORESOURCE_MEM,
356 },
357 {
358 .name = "qup_err_intr",
359 .start = GSBI5_QUP_IRQ,
360 .end = GSBI5_QUP_IRQ,
361 .flags = IORESOURCE_IRQ,
362 },
363 {
364 .name = "i2c_clk",
365 .start = 54,
366 .end = 54,
367 .flags = IORESOURCE_IO,
368 },
369 {
370 .name = "i2c_sda",
371 .start = 53,
372 .end = 53,
373 .flags = IORESOURCE_IO,
374 },
375};
376
377struct platform_device mpq8064_device_qup_i2c_gsbi5 = {
378 .name = "qup_i2c",
379 .id = 5,
380 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi5),
381 .resource = resources_qup_i2c_gsbi5,
382};
383
Jin Hong4bbbfba2012-02-02 21:48:07 -0800384static struct resource resources_uart_gsbi7[] = {
385 {
386 .start = GSBI7_UARTDM_IRQ,
387 .end = GSBI7_UARTDM_IRQ,
388 .flags = IORESOURCE_IRQ,
389 },
390 {
391 .start = MSM_UART7DM_PHYS,
392 .end = MSM_UART7DM_PHYS + PAGE_SIZE - 1,
393 .name = "uartdm_resource",
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 .start = MSM_GSBI7_PHYS,
398 .end = MSM_GSBI7_PHYS + PAGE_SIZE - 1,
399 .name = "gsbi_resource",
400 .flags = IORESOURCE_MEM,
401 },
402};
403
404struct platform_device apq8064_device_uart_gsbi7 = {
405 .name = "msm_serial_hsl",
406 .id = 0,
407 .num_resources = ARRAY_SIZE(resources_uart_gsbi7),
408 .resource = resources_uart_gsbi7,
409};
410
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800411struct platform_device apq_pcm = {
412 .name = "msm-pcm-dsp",
413 .id = -1,
414};
415
416struct platform_device apq_pcm_routing = {
417 .name = "msm-pcm-routing",
418 .id = -1,
419};
420
421struct platform_device apq_cpudai0 = {
422 .name = "msm-dai-q6",
423 .id = 0x4000,
424};
425
426struct platform_device apq_cpudai1 = {
427 .name = "msm-dai-q6",
428 .id = 0x4001,
429};
Santosh Mardieff9a742012-04-09 23:23:39 +0530430struct platform_device mpq_cpudai_sec_i2s_rx = {
431 .name = "msm-dai-q6",
432 .id = 4,
433};
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800434struct platform_device apq_cpudai_hdmi_rx = {
Swaminathan Sathappanfd9dbad2012-02-15 16:56:44 -0800435 .name = "msm-dai-q6-hdmi",
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800436 .id = 8,
437};
438
439struct platform_device apq_cpudai_bt_rx = {
440 .name = "msm-dai-q6",
441 .id = 0x3000,
442};
443
444struct platform_device apq_cpudai_bt_tx = {
445 .name = "msm-dai-q6",
446 .id = 0x3001,
447};
448
449struct platform_device apq_cpudai_fm_rx = {
450 .name = "msm-dai-q6",
451 .id = 0x3004,
452};
453
454struct platform_device apq_cpudai_fm_tx = {
455 .name = "msm-dai-q6",
456 .id = 0x3005,
457};
458
Helen Zeng8f925502012-03-05 16:50:17 -0800459struct platform_device apq_cpudai_slim_4_rx = {
460 .name = "msm-dai-q6",
461 .id = 0x4008,
462};
463
464struct platform_device apq_cpudai_slim_4_tx = {
465 .name = "msm-dai-q6",
466 .id = 0x4009,
467};
468
Joel Nidere5de00e2012-07-03 10:58:10 +0300469#define MSM_TSIF0_PHYS (0x18200000)
470#define MSM_TSIF1_PHYS (0x18201000)
471#define MSM_TSIF_SIZE (0x200)
472
473#define TSIF_0_CLK GPIO_CFG(55, 1, GPIO_CFG_INPUT, \
474 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
475#define TSIF_0_EN GPIO_CFG(56, 1, GPIO_CFG_INPUT, \
476 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
477#define TSIF_0_DATA GPIO_CFG(57, 1, GPIO_CFG_INPUT, \
478 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
479#define TSIF_0_SYNC GPIO_CFG(62, 1, GPIO_CFG_INPUT, \
480 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
481#define TSIF_1_CLK GPIO_CFG(59, 1, GPIO_CFG_INPUT, \
482 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
483#define TSIF_1_EN GPIO_CFG(60, 1, GPIO_CFG_INPUT, \
484 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
485#define TSIF_1_DATA GPIO_CFG(61, 1, GPIO_CFG_INPUT, \
486 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
487#define TSIF_1_SYNC GPIO_CFG(58, 1, GPIO_CFG_INPUT, \
488 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
489
490static const struct msm_gpio tsif0_gpios[] = {
491 { .gpio_cfg = TSIF_0_CLK, .label = "tsif_clk", },
492 { .gpio_cfg = TSIF_0_EN, .label = "tsif_en", },
493 { .gpio_cfg = TSIF_0_DATA, .label = "tsif_data", },
494 { .gpio_cfg = TSIF_0_SYNC, .label = "tsif_sync", },
495};
496
497static const struct msm_gpio tsif1_gpios[] = {
498 { .gpio_cfg = TSIF_1_CLK, .label = "tsif_clk", },
499 { .gpio_cfg = TSIF_1_EN, .label = "tsif_en", },
500 { .gpio_cfg = TSIF_1_DATA, .label = "tsif_data", },
501 { .gpio_cfg = TSIF_1_SYNC, .label = "tsif_sync", },
502};
503
504struct msm_tsif_platform_data tsif1_8064_platform_data = {
505 .num_gpios = ARRAY_SIZE(tsif1_gpios),
506 .gpios = tsif1_gpios,
507 .tsif_pclk = "iface_clk",
508 .tsif_ref_clk = "ref_clk",
509};
510
511struct resource tsif1_8064_resources[] = {
512 [0] = {
513 .flags = IORESOURCE_IRQ,
514 .start = TSIF2_IRQ,
515 .end = TSIF2_IRQ,
516 },
517 [1] = {
518 .flags = IORESOURCE_MEM,
519 .start = MSM_TSIF1_PHYS,
520 .end = MSM_TSIF1_PHYS + MSM_TSIF_SIZE - 1,
521 },
522 [2] = {
523 .flags = IORESOURCE_DMA,
524 .start = DMOV8064_TSIF_CHAN,
525 .end = DMOV8064_TSIF_CRCI,
526 },
527};
528
529struct msm_tsif_platform_data tsif0_8064_platform_data = {
530 .num_gpios = ARRAY_SIZE(tsif0_gpios),
531 .gpios = tsif0_gpios,
532 .tsif_pclk = "iface_clk",
533 .tsif_ref_clk = "ref_clk",
534};
535
536struct resource tsif0_8064_resources[] = {
537 [0] = {
538 .flags = IORESOURCE_IRQ,
539 .start = TSIF1_IRQ,
540 .end = TSIF1_IRQ,
541 },
542 [1] = {
543 .flags = IORESOURCE_MEM,
544 .start = MSM_TSIF0_PHYS,
545 .end = MSM_TSIF0_PHYS + MSM_TSIF_SIZE - 1,
546 },
547 [2] = {
548 .flags = IORESOURCE_DMA,
549 .start = DMOV_TSIF_CHAN,
550 .end = DMOV_TSIF_CRCI,
551 },
552};
553
554struct platform_device msm_8064_device_tsif[2] = {
555 {
556 .name = "msm_tsif",
557 .id = 0,
558 .num_resources = ARRAY_SIZE(tsif0_8064_resources),
559 .resource = tsif0_8064_resources,
560 .dev = {
561 .platform_data = &tsif0_8064_platform_data
562 },
563 },
564 {
565 .name = "msm_tsif",
566 .id = 1,
567 .num_resources = ARRAY_SIZE(tsif1_8064_resources),
568 .resource = tsif1_8064_resources,
569 .dev = {
570 .platform_data = &tsif1_8064_platform_data
571 },
572 }
573};
574
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800575/*
576 * Machine specific data for AUX PCM Interface
577 * which the driver will be unware of.
578 */
Kiran Kandi5f4ab692012-02-23 11:23:56 -0800579struct msm_dai_auxpcm_pdata apq_auxpcm_pdata = {
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800580 .clk = "pcm_clk",
Kuirong Wang547a9982012-05-04 18:29:11 -0700581 .mode_8k = {
582 .mode = AFE_PCM_CFG_MODE_PCM,
583 .sync = AFE_PCM_CFG_SYNC_INT,
584 .frame = AFE_PCM_CFG_FRM_256BPF,
585 .quant = AFE_PCM_CFG_QUANT_LINEAR_NOPAD,
586 .slot = 0,
587 .data = AFE_PCM_CFG_CDATAOE_MASTER,
588 .pcm_clk_rate = 2048000,
589 },
590 .mode_16k = {
591 .mode = AFE_PCM_CFG_MODE_PCM,
592 .sync = AFE_PCM_CFG_SYNC_INT,
593 .frame = AFE_PCM_CFG_FRM_256BPF,
594 .quant = AFE_PCM_CFG_QUANT_LINEAR_NOPAD,
595 .slot = 0,
596 .data = AFE_PCM_CFG_CDATAOE_MASTER,
597 .pcm_clk_rate = 4096000,
598 }
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800599};
600
601struct platform_device apq_cpudai_auxpcm_rx = {
602 .name = "msm-dai-q6",
603 .id = 2,
604 .dev = {
Kiran Kandi5f4ab692012-02-23 11:23:56 -0800605 .platform_data = &apq_auxpcm_pdata,
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800606 },
607};
608
609struct platform_device apq_cpudai_auxpcm_tx = {
610 .name = "msm-dai-q6",
611 .id = 3,
Kiran Kandi5f4ab692012-02-23 11:23:56 -0800612 .dev = {
613 .platform_data = &apq_auxpcm_pdata,
614 },
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800615};
616
Patrick Lai04baee942012-05-01 14:38:47 -0700617struct msm_mi2s_pdata mpq_mi2s_tx_data = {
618 .rx_sd_lines = 0,
619 .tx_sd_lines = MSM_MI2S_SD0 | MSM_MI2S_SD1 | MSM_MI2S_SD2 |
620 MSM_MI2S_SD3,
Kuirong Wangf23f8c52012-03-31 12:34:51 -0700621};
622
623struct platform_device mpq_cpudai_mi2s_tx = {
Patrick Lai04baee942012-05-01 14:38:47 -0700624 .name = "msm-dai-q6-mi2s",
625 .id = -1, /*MI2S_TX */
Kuirong Wangf23f8c52012-03-31 12:34:51 -0700626 .dev = {
627 .platform_data = &mpq_mi2s_tx_data,
628 },
629};
630
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800631struct platform_device apq_cpu_fe = {
632 .name = "msm-dai-fe",
633 .id = -1,
634};
635
636struct platform_device apq_stub_codec = {
637 .name = "msm-stub-codec",
638 .id = 1,
639};
640
641struct platform_device apq_voice = {
642 .name = "msm-pcm-voice",
643 .id = -1,
644};
645
646struct platform_device apq_voip = {
647 .name = "msm-voip-dsp",
648 .id = -1,
649};
650
651struct platform_device apq_lpa_pcm = {
652 .name = "msm-pcm-lpa",
653 .id = -1,
654};
655
Krishnankutty Kolathappilly4374e332012-03-18 22:27:30 -0700656struct platform_device apq_compr_dsp = {
657 .name = "msm-compr-dsp",
658 .id = -1,
659};
660
661struct platform_device apq_multi_ch_pcm = {
662 .name = "msm-multi-ch-pcm-dsp",
663 .id = -1,
664};
665
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800666struct platform_device apq_pcm_hostless = {
667 .name = "msm-pcm-hostless",
668 .id = -1,
669};
670
671struct platform_device apq_cpudai_afe_01_rx = {
672 .name = "msm-dai-q6",
673 .id = 0xE0,
674};
675
676struct platform_device apq_cpudai_afe_01_tx = {
677 .name = "msm-dai-q6",
678 .id = 0xF0,
679};
680
681struct platform_device apq_cpudai_afe_02_rx = {
682 .name = "msm-dai-q6",
683 .id = 0xF1,
684};
685
686struct platform_device apq_cpudai_afe_02_tx = {
687 .name = "msm-dai-q6",
688 .id = 0xE1,
689};
690
691struct platform_device apq_pcm_afe = {
692 .name = "msm-pcm-afe",
693 .id = -1,
694};
695
Neema Shetty8427c262012-02-16 11:23:43 -0800696struct platform_device apq_cpudai_stub = {
697 .name = "msm-dai-stub",
698 .id = -1,
699};
700
Neema Shetty3c9d2862012-03-11 01:25:32 -0800701struct platform_device apq_cpudai_slimbus_1_rx = {
702 .name = "msm-dai-q6",
703 .id = 0x4002,
704};
705
706struct platform_device apq_cpudai_slimbus_1_tx = {
707 .name = "msm-dai-q6",
708 .id = 0x4003,
709};
710
Kiran Kandi97fe19d2012-05-20 22:34:04 -0700711struct platform_device apq_cpudai_slimbus_2_rx = {
712 .name = "msm-dai-q6",
713 .id = 0x4004,
714};
715
Kiran Kandi1e6371d2012-03-29 11:48:57 -0700716struct platform_device apq_cpudai_slimbus_2_tx = {
717 .name = "msm-dai-q6",
718 .id = 0x4005,
719};
720
Neema Shettyc9d86c32012-05-09 12:01:39 -0700721struct platform_device apq_cpudai_slimbus_3_rx = {
722 .name = "msm-dai-q6",
723 .id = 0x4006,
724};
725
Helen Zeng38c3c962012-05-17 14:56:20 -0700726struct platform_device apq_cpudai_slimbus_3_tx = {
727 .name = "msm-dai-q6",
728 .id = 0x4007,
729};
730
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700731static struct resource resources_ssbi_pmic1[] = {
732 {
733 .start = MSM_PMIC1_SSBI_CMD_PHYS,
734 .end = MSM_PMIC1_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
735 .flags = IORESOURCE_MEM,
736 },
737};
738
Sagar Dharia8bdcdaf2011-09-16 16:01:15 -0600739#define LPASS_SLIMBUS_PHYS 0x28080000
740#define LPASS_SLIMBUS_BAM_PHYS 0x28084000
Swaminathan Sathappan2316e082012-02-03 14:07:17 -0800741#define LPASS_SLIMBUS_SLEW (MSM8960_TLMM_PHYS + 0x207C)
Sagar Dharia8bdcdaf2011-09-16 16:01:15 -0600742/* Board info for the slimbus slave device */
743static struct resource slimbus_res[] = {
744 {
745 .start = LPASS_SLIMBUS_PHYS,
746 .end = LPASS_SLIMBUS_PHYS + 8191,
747 .flags = IORESOURCE_MEM,
748 .name = "slimbus_physical",
749 },
750 {
751 .start = LPASS_SLIMBUS_BAM_PHYS,
752 .end = LPASS_SLIMBUS_BAM_PHYS + 8191,
753 .flags = IORESOURCE_MEM,
754 .name = "slimbus_bam_physical",
755 },
756 {
Swaminathan Sathappan2316e082012-02-03 14:07:17 -0800757 .start = LPASS_SLIMBUS_SLEW,
758 .end = LPASS_SLIMBUS_SLEW + 4 - 1,
759 .flags = IORESOURCE_MEM,
760 .name = "slimbus_slew_reg",
761 },
762 {
Sagar Dharia8bdcdaf2011-09-16 16:01:15 -0600763 .start = SLIMBUS0_CORE_EE1_IRQ,
764 .end = SLIMBUS0_CORE_EE1_IRQ,
765 .flags = IORESOURCE_IRQ,
766 .name = "slimbus_irq",
767 },
768 {
769 .start = SLIMBUS0_BAM_EE1_IRQ,
770 .end = SLIMBUS0_BAM_EE1_IRQ,
771 .flags = IORESOURCE_IRQ,
772 .name = "slimbus_bam_irq",
773 },
774};
775
776struct platform_device apq8064_slim_ctrl = {
777 .name = "msm_slim_ctrl",
778 .id = 1,
779 .num_resources = ARRAY_SIZE(slimbus_res),
780 .resource = slimbus_res,
781 .dev = {
782 .coherent_dma_mask = 0xffffffffULL,
783 },
784};
785
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700786struct platform_device apq8064_device_ssbi_pmic1 = {
787 .name = "msm_ssbi",
788 .id = 0,
789 .resource = resources_ssbi_pmic1,
790 .num_resources = ARRAY_SIZE(resources_ssbi_pmic1),
791};
792
793static struct resource resources_ssbi_pmic2[] = {
794 {
795 .start = MSM_PMIC2_SSBI_CMD_PHYS,
796 .end = MSM_PMIC2_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
797 .flags = IORESOURCE_MEM,
798 },
799};
800
801struct platform_device apq8064_device_ssbi_pmic2 = {
802 .name = "msm_ssbi",
803 .id = 1,
804 .resource = resources_ssbi_pmic2,
805 .num_resources = ARRAY_SIZE(resources_ssbi_pmic2),
806};
807
808static struct resource resources_otg[] = {
809 {
Hemant Kumard86c4882012-01-24 19:39:37 -0800810 .start = MSM_HSUSB1_PHYS,
811 .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700812 .flags = IORESOURCE_MEM,
813 },
814 {
815 .start = USB1_HS_IRQ,
816 .end = USB1_HS_IRQ,
817 .flags = IORESOURCE_IRQ,
818 },
819};
820
Stepan Moskovchenko14aa6492011-08-08 15:15:01 -0700821struct platform_device apq8064_device_otg = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700822 .name = "msm_otg",
823 .id = -1,
824 .num_resources = ARRAY_SIZE(resources_otg),
825 .resource = resources_otg,
826 .dev = {
827 .coherent_dma_mask = 0xffffffff,
828 },
829};
830
831static struct resource resources_hsusb[] = {
832 {
Hemant Kumard86c4882012-01-24 19:39:37 -0800833 .start = MSM_HSUSB1_PHYS,
834 .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700835 .flags = IORESOURCE_MEM,
836 },
837 {
838 .start = USB1_HS_IRQ,
839 .end = USB1_HS_IRQ,
840 .flags = IORESOURCE_IRQ,
841 },
842};
843
Stepan Moskovchenko14aa6492011-08-08 15:15:01 -0700844struct platform_device apq8064_device_gadget_peripheral = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700845 .name = "msm_hsusb",
846 .id = -1,
847 .num_resources = ARRAY_SIZE(resources_hsusb),
848 .resource = resources_hsusb,
849 .dev = {
850 .coherent_dma_mask = 0xffffffff,
851 },
852};
853
Hemant Kumard86c4882012-01-24 19:39:37 -0800854static struct resource resources_hsusb_host[] = {
855 {
856 .start = MSM_HSUSB1_PHYS,
857 .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1,
858 .flags = IORESOURCE_MEM,
859 },
860 {
861 .start = USB1_HS_IRQ,
862 .end = USB1_HS_IRQ,
863 .flags = IORESOURCE_IRQ,
864 },
865};
866
Hemant Kumara945b472012-01-25 15:08:06 -0800867static struct resource resources_hsic_host[] = {
868 {
869 .start = 0x12510000,
870 .end = 0x12510000 + SZ_4K - 1,
871 .flags = IORESOURCE_MEM,
872 },
873 {
874 .start = USB2_HSIC_IRQ,
875 .end = USB2_HSIC_IRQ,
876 .flags = IORESOURCE_IRQ,
877 },
878 {
879 .start = MSM_GPIO_TO_INT(49),
880 .end = MSM_GPIO_TO_INT(49),
881 .name = "peripheral_status_irq",
882 .flags = IORESOURCE_IRQ,
883 },
Vamsi Krishna6921cbe2012-02-21 18:34:43 -0800884 {
Hemant Kumar6fd65032012-05-23 13:02:24 -0700885 .start = 47,
886 .end = 47,
887 .name = "wakeup",
888 .flags = IORESOURCE_IO,
Vamsi Krishna6921cbe2012-02-21 18:34:43 -0800889 },
Hemant Kumara945b472012-01-25 15:08:06 -0800890};
891
Hemant Kumard86c4882012-01-24 19:39:37 -0800892static u64 dma_mask = DMA_BIT_MASK(32);
893struct platform_device apq8064_device_hsusb_host = {
894 .name = "msm_hsusb_host",
895 .id = -1,
896 .num_resources = ARRAY_SIZE(resources_hsusb_host),
897 .resource = resources_hsusb_host,
898 .dev = {
899 .dma_mask = &dma_mask,
900 .coherent_dma_mask = 0xffffffff,
901 },
902};
903
Hemant Kumara945b472012-01-25 15:08:06 -0800904struct platform_device apq8064_device_hsic_host = {
905 .name = "msm_hsic_host",
906 .id = -1,
907 .num_resources = ARRAY_SIZE(resources_hsic_host),
908 .resource = resources_hsic_host,
909 .dev = {
910 .dma_mask = &dma_mask,
911 .coherent_dma_mask = DMA_BIT_MASK(32),
912 },
913};
914
Manu Gautam91223e02011-11-08 15:27:22 +0530915static struct resource resources_ehci_host3[] = {
916{
917 .start = MSM_HSUSB3_PHYS,
918 .end = MSM_HSUSB3_PHYS + MSM_HSUSB3_SIZE - 1,
919 .flags = IORESOURCE_MEM,
920 },
921 {
922 .start = USB3_HS_IRQ,
923 .end = USB3_HS_IRQ,
924 .flags = IORESOURCE_IRQ,
925 },
926};
927
928struct platform_device apq8064_device_ehci_host3 = {
929 .name = "msm_ehci_host",
930 .id = 0,
931 .num_resources = ARRAY_SIZE(resources_ehci_host3),
932 .resource = resources_ehci_host3,
933 .dev = {
934 .dma_mask = &dma_mask,
935 .coherent_dma_mask = 0xffffffff,
936 },
937};
938
Hemant Kumar1d66e1c2012-02-13 15:24:59 -0800939static struct resource resources_ehci_host4[] = {
940{
941 .start = MSM_HSUSB4_PHYS,
942 .end = MSM_HSUSB4_PHYS + MSM_HSUSB4_SIZE - 1,
943 .flags = IORESOURCE_MEM,
944 },
945 {
946 .start = USB4_HS_IRQ,
947 .end = USB4_HS_IRQ,
948 .flags = IORESOURCE_IRQ,
949 },
950};
951
952struct platform_device apq8064_device_ehci_host4 = {
953 .name = "msm_ehci_host",
954 .id = 1,
955 .num_resources = ARRAY_SIZE(resources_ehci_host4),
956 .resource = resources_ehci_host4,
957 .dev = {
958 .dma_mask = &dma_mask,
959 .coherent_dma_mask = 0xffffffff,
960 },
961};
962
Matt Wagantallf5cc3892012-06-07 19:47:02 -0700963struct platform_device apq8064_device_acpuclk = {
964 .name = "acpuclk-8064",
965 .id = -1,
966};
967
Ramesh Masavarapuf31ff242012-05-10 18:55:21 -0700968#define SHARED_IMEM_TZ_BASE 0x2a03f720
969static struct resource tzlog_resources[] = {
970 {
971 .start = SHARED_IMEM_TZ_BASE,
972 .end = SHARED_IMEM_TZ_BASE + SZ_4K - 1,
973 .flags = IORESOURCE_MEM,
974 },
975};
976
977struct platform_device apq_device_tz_log = {
978 .name = "tz_log",
979 .id = 0,
980 .num_resources = ARRAY_SIZE(tzlog_resources),
981 .resource = tzlog_resources,
982};
983
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -0800984/* MSM Video core device */
985#ifdef CONFIG_MSM_BUS_SCALING
986static struct msm_bus_vectors vidc_init_vectors[] = {
987 {
988 .src = MSM_BUS_MASTER_VIDEO_ENC,
989 .dst = MSM_BUS_SLAVE_EBI_CH0,
990 .ab = 0,
991 .ib = 0,
992 },
993 {
994 .src = MSM_BUS_MASTER_VIDEO_DEC,
995 .dst = MSM_BUS_SLAVE_EBI_CH0,
996 .ab = 0,
997 .ib = 0,
998 },
999 {
1000 .src = MSM_BUS_MASTER_AMPSS_M0,
1001 .dst = MSM_BUS_SLAVE_EBI_CH0,
1002 .ab = 0,
1003 .ib = 0,
1004 },
1005 {
1006 .src = MSM_BUS_MASTER_AMPSS_M0,
1007 .dst = MSM_BUS_SLAVE_EBI_CH0,
1008 .ab = 0,
1009 .ib = 0,
1010 },
1011};
1012static struct msm_bus_vectors vidc_venc_vga_vectors[] = {
1013 {
1014 .src = MSM_BUS_MASTER_VIDEO_ENC,
1015 .dst = MSM_BUS_SLAVE_EBI_CH0,
1016 .ab = 54525952,
1017 .ib = 436207616,
1018 },
1019 {
1020 .src = MSM_BUS_MASTER_VIDEO_DEC,
1021 .dst = MSM_BUS_SLAVE_EBI_CH0,
1022 .ab = 72351744,
1023 .ib = 289406976,
1024 },
1025 {
1026 .src = MSM_BUS_MASTER_AMPSS_M0,
1027 .dst = MSM_BUS_SLAVE_EBI_CH0,
1028 .ab = 500000,
1029 .ib = 1000000,
1030 },
1031 {
1032 .src = MSM_BUS_MASTER_AMPSS_M0,
1033 .dst = MSM_BUS_SLAVE_EBI_CH0,
1034 .ab = 500000,
1035 .ib = 1000000,
1036 },
1037};
1038static struct msm_bus_vectors vidc_vdec_vga_vectors[] = {
1039 {
1040 .src = MSM_BUS_MASTER_VIDEO_ENC,
1041 .dst = MSM_BUS_SLAVE_EBI_CH0,
1042 .ab = 40894464,
1043 .ib = 327155712,
1044 },
1045 {
1046 .src = MSM_BUS_MASTER_VIDEO_DEC,
1047 .dst = MSM_BUS_SLAVE_EBI_CH0,
1048 .ab = 48234496,
1049 .ib = 192937984,
1050 },
1051 {
1052 .src = MSM_BUS_MASTER_AMPSS_M0,
1053 .dst = MSM_BUS_SLAVE_EBI_CH0,
1054 .ab = 500000,
1055 .ib = 2000000,
1056 },
1057 {
1058 .src = MSM_BUS_MASTER_AMPSS_M0,
1059 .dst = MSM_BUS_SLAVE_EBI_CH0,
1060 .ab = 500000,
1061 .ib = 2000000,
1062 },
1063};
1064static struct msm_bus_vectors vidc_venc_720p_vectors[] = {
1065 {
1066 .src = MSM_BUS_MASTER_VIDEO_ENC,
1067 .dst = MSM_BUS_SLAVE_EBI_CH0,
1068 .ab = 163577856,
1069 .ib = 1308622848,
1070 },
1071 {
1072 .src = MSM_BUS_MASTER_VIDEO_DEC,
1073 .dst = MSM_BUS_SLAVE_EBI_CH0,
1074 .ab = 219152384,
1075 .ib = 876609536,
1076 },
1077 {
1078 .src = MSM_BUS_MASTER_AMPSS_M0,
1079 .dst = MSM_BUS_SLAVE_EBI_CH0,
1080 .ab = 1750000,
1081 .ib = 3500000,
1082 },
1083 {
1084 .src = MSM_BUS_MASTER_AMPSS_M0,
1085 .dst = MSM_BUS_SLAVE_EBI_CH0,
1086 .ab = 1750000,
1087 .ib = 3500000,
1088 },
1089};
1090static struct msm_bus_vectors vidc_vdec_720p_vectors[] = {
1091 {
1092 .src = MSM_BUS_MASTER_VIDEO_ENC,
1093 .dst = MSM_BUS_SLAVE_EBI_CH0,
1094 .ab = 121634816,
1095 .ib = 973078528,
1096 },
1097 {
1098 .src = MSM_BUS_MASTER_VIDEO_DEC,
1099 .dst = MSM_BUS_SLAVE_EBI_CH0,
1100 .ab = 155189248,
1101 .ib = 620756992,
1102 },
1103 {
1104 .src = MSM_BUS_MASTER_AMPSS_M0,
1105 .dst = MSM_BUS_SLAVE_EBI_CH0,
1106 .ab = 1750000,
1107 .ib = 7000000,
1108 },
1109 {
1110 .src = MSM_BUS_MASTER_AMPSS_M0,
1111 .dst = MSM_BUS_SLAVE_EBI_CH0,
1112 .ab = 1750000,
1113 .ib = 7000000,
1114 },
1115};
1116static struct msm_bus_vectors vidc_venc_1080p_vectors[] = {
1117 {
1118 .src = MSM_BUS_MASTER_VIDEO_ENC,
1119 .dst = MSM_BUS_SLAVE_EBI_CH0,
1120 .ab = 372244480,
1121 .ib = 2560000000U,
1122 },
1123 {
1124 .src = MSM_BUS_MASTER_VIDEO_DEC,
1125 .dst = MSM_BUS_SLAVE_EBI_CH0,
1126 .ab = 501219328,
1127 .ib = 2560000000U,
1128 },
1129 {
1130 .src = MSM_BUS_MASTER_AMPSS_M0,
1131 .dst = MSM_BUS_SLAVE_EBI_CH0,
1132 .ab = 2500000,
1133 .ib = 5000000,
1134 },
1135 {
1136 .src = MSM_BUS_MASTER_AMPSS_M0,
1137 .dst = MSM_BUS_SLAVE_EBI_CH0,
1138 .ab = 2500000,
1139 .ib = 5000000,
1140 },
1141};
1142static struct msm_bus_vectors vidc_vdec_1080p_vectors[] = {
1143 {
1144 .src = MSM_BUS_MASTER_VIDEO_ENC,
1145 .dst = MSM_BUS_SLAVE_EBI_CH0,
1146 .ab = 222298112,
1147 .ib = 2560000000U,
1148 },
1149 {
1150 .src = MSM_BUS_MASTER_VIDEO_DEC,
1151 .dst = MSM_BUS_SLAVE_EBI_CH0,
1152 .ab = 330301440,
1153 .ib = 2560000000U,
1154 },
1155 {
1156 .src = MSM_BUS_MASTER_AMPSS_M0,
1157 .dst = MSM_BUS_SLAVE_EBI_CH0,
1158 .ab = 2500000,
1159 .ib = 700000000,
1160 },
1161 {
1162 .src = MSM_BUS_MASTER_AMPSS_M0,
1163 .dst = MSM_BUS_SLAVE_EBI_CH0,
1164 .ab = 2500000,
1165 .ib = 10000000,
1166 },
1167};
1168
Arun Menon152c3c72012-06-20 11:50:08 -07001169static struct msm_bus_vectors vidc_venc_1080p_turbo_vectors[] = {
1170 {
1171 .src = MSM_BUS_MASTER_VIDEO_ENC,
1172 .dst = MSM_BUS_SLAVE_EBI_CH0,
1173 .ab = 222298112,
1174 .ib = 3522000000U,
1175 },
1176 {
1177 .src = MSM_BUS_MASTER_VIDEO_DEC,
1178 .dst = MSM_BUS_SLAVE_EBI_CH0,
1179 .ab = 330301440,
1180 .ib = 3522000000U,
1181 },
1182 {
1183 .src = MSM_BUS_MASTER_AMPSS_M0,
1184 .dst = MSM_BUS_SLAVE_EBI_CH0,
1185 .ab = 2500000,
1186 .ib = 700000000,
1187 },
1188 {
1189 .src = MSM_BUS_MASTER_AMPSS_M0,
1190 .dst = MSM_BUS_SLAVE_EBI_CH0,
1191 .ab = 2500000,
1192 .ib = 10000000,
1193 },
1194};
1195static struct msm_bus_vectors vidc_vdec_1080p_turbo_vectors[] = {
1196 {
1197 .src = MSM_BUS_MASTER_VIDEO_ENC,
1198 .dst = MSM_BUS_SLAVE_EBI_CH0,
1199 .ab = 222298112,
1200 .ib = 3522000000U,
1201 },
1202 {
1203 .src = MSM_BUS_MASTER_VIDEO_DEC,
1204 .dst = MSM_BUS_SLAVE_EBI_CH0,
1205 .ab = 330301440,
1206 .ib = 3522000000U,
1207 },
1208 {
1209 .src = MSM_BUS_MASTER_AMPSS_M0,
1210 .dst = MSM_BUS_SLAVE_EBI_CH0,
1211 .ab = 2500000,
1212 .ib = 700000000,
1213 },
1214 {
1215 .src = MSM_BUS_MASTER_AMPSS_M0,
1216 .dst = MSM_BUS_SLAVE_EBI_CH0,
1217 .ab = 2500000,
1218 .ib = 10000000,
1219 },
1220};
1221
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -08001222static struct msm_bus_paths vidc_bus_client_config[] = {
1223 {
1224 ARRAY_SIZE(vidc_init_vectors),
1225 vidc_init_vectors,
1226 },
1227 {
1228 ARRAY_SIZE(vidc_venc_vga_vectors),
1229 vidc_venc_vga_vectors,
1230 },
1231 {
1232 ARRAY_SIZE(vidc_vdec_vga_vectors),
1233 vidc_vdec_vga_vectors,
1234 },
1235 {
1236 ARRAY_SIZE(vidc_venc_720p_vectors),
1237 vidc_venc_720p_vectors,
1238 },
1239 {
1240 ARRAY_SIZE(vidc_vdec_720p_vectors),
1241 vidc_vdec_720p_vectors,
1242 },
1243 {
1244 ARRAY_SIZE(vidc_venc_1080p_vectors),
1245 vidc_venc_1080p_vectors,
1246 },
1247 {
1248 ARRAY_SIZE(vidc_vdec_1080p_vectors),
1249 vidc_vdec_1080p_vectors,
1250 },
Arun Menon152c3c72012-06-20 11:50:08 -07001251 {
1252 ARRAY_SIZE(vidc_venc_1080p_turbo_vectors),
1253 vidc_venc_1080p_turbo_vectors,
1254 },
1255 {
1256 ARRAY_SIZE(vidc_vdec_1080p_turbo_vectors),
1257 vidc_vdec_1080p_turbo_vectors,
1258 },
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -08001259};
1260
1261static struct msm_bus_scale_pdata vidc_bus_client_data = {
1262 vidc_bus_client_config,
1263 ARRAY_SIZE(vidc_bus_client_config),
1264 .name = "vidc",
1265};
1266#endif
1267
1268
1269#define APQ8064_VIDC_BASE_PHYS 0x04400000
1270#define APQ8064_VIDC_BASE_SIZE 0x00100000
1271
1272static struct resource apq8064_device_vidc_resources[] = {
1273 {
1274 .start = APQ8064_VIDC_BASE_PHYS,
1275 .end = APQ8064_VIDC_BASE_PHYS + APQ8064_VIDC_BASE_SIZE - 1,
1276 .flags = IORESOURCE_MEM,
1277 },
1278 {
1279 .start = VCODEC_IRQ,
1280 .end = VCODEC_IRQ,
1281 .flags = IORESOURCE_IRQ,
1282 },
1283};
1284
1285struct msm_vidc_platform_data apq8064_vidc_platform_data = {
1286#ifdef CONFIG_MSM_BUS_SCALING
1287 .vidc_bus_client_pdata = &vidc_bus_client_data,
1288#endif
1289#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
1290 .memtype = ION_CP_MM_HEAP_ID,
1291 .enable_ion = 1,
Deepak kotureda295a2012-05-10 19:49:46 -07001292 .cp_enabled = 1,
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -08001293#else
1294 .memtype = MEMTYPE_EBI1,
1295 .enable_ion = 0,
1296#endif
1297 .disable_dmx = 0,
1298 .disable_fullhd = 0,
Mohan Kumar Gubbihalli Lachma Naiked9dc912012-03-01 19:11:14 -08001299 .cont_mode_dpb_count = 18,
Riaz Rahaman84f8c682012-05-30 13:32:10 +05301300 .fw_addr = 0x9fe00000,
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -08001301};
1302
1303struct platform_device apq8064_msm_device_vidc = {
1304 .name = "msm_vidc",
1305 .id = 0,
1306 .num_resources = ARRAY_SIZE(apq8064_device_vidc_resources),
1307 .resource = apq8064_device_vidc_resources,
1308 .dev = {
1309 .platform_data = &apq8064_vidc_platform_data,
1310 },
1311};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001312#define MSM_SDC1_BASE 0x12400000
1313#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
1314#define MSM_SDC1_BAM_BASE (MSM_SDC1_BASE + 0x2000)
1315#define MSM_SDC2_BASE 0x12140000
1316#define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800)
1317#define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000)
1318#define MSM_SDC3_BASE 0x12180000
1319#define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800)
1320#define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000)
1321#define MSM_SDC4_BASE 0x121C0000
1322#define MSM_SDC4_DML_BASE (MSM_SDC4_BASE + 0x800)
1323#define MSM_SDC4_BAM_BASE (MSM_SDC4_BASE + 0x2000)
1324
1325static struct resource resources_sdc1[] = {
1326 {
1327 .name = "core_mem",
1328 .flags = IORESOURCE_MEM,
1329 .start = MSM_SDC1_BASE,
1330 .end = MSM_SDC1_DML_BASE - 1,
1331 },
1332 {
1333 .name = "core_irq",
1334 .flags = IORESOURCE_IRQ,
1335 .start = SDC1_IRQ_0,
1336 .end = SDC1_IRQ_0
1337 },
1338#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
1339 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301340 .name = "dml_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001341 .start = MSM_SDC1_DML_BASE,
1342 .end = MSM_SDC1_BAM_BASE - 1,
1343 .flags = IORESOURCE_MEM,
1344 },
1345 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301346 .name = "bam_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001347 .start = MSM_SDC1_BAM_BASE,
1348 .end = MSM_SDC1_BAM_BASE + (2 * SZ_4K) - 1,
1349 .flags = IORESOURCE_MEM,
1350 },
1351 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301352 .name = "bam_irq",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001353 .start = SDC1_BAM_IRQ,
1354 .end = SDC1_BAM_IRQ,
1355 .flags = IORESOURCE_IRQ,
1356 },
1357#endif
1358};
1359
1360static struct resource resources_sdc2[] = {
1361 {
1362 .name = "core_mem",
1363 .flags = IORESOURCE_MEM,
1364 .start = MSM_SDC2_BASE,
1365 .end = MSM_SDC2_DML_BASE - 1,
1366 },
1367 {
1368 .name = "core_irq",
1369 .flags = IORESOURCE_IRQ,
1370 .start = SDC2_IRQ_0,
1371 .end = SDC2_IRQ_0
1372 },
1373#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
1374 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301375 .name = "dml_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001376 .start = MSM_SDC2_DML_BASE,
1377 .end = MSM_SDC2_BAM_BASE - 1,
1378 .flags = IORESOURCE_MEM,
1379 },
1380 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301381 .name = "bam_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001382 .start = MSM_SDC2_BAM_BASE,
1383 .end = MSM_SDC2_BAM_BASE + (2 * SZ_4K) - 1,
1384 .flags = IORESOURCE_MEM,
1385 },
1386 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301387 .name = "bam_irq",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001388 .start = SDC2_BAM_IRQ,
1389 .end = SDC2_BAM_IRQ,
1390 .flags = IORESOURCE_IRQ,
1391 },
1392#endif
1393};
1394
1395static struct resource resources_sdc3[] = {
1396 {
1397 .name = "core_mem",
1398 .flags = IORESOURCE_MEM,
1399 .start = MSM_SDC3_BASE,
1400 .end = MSM_SDC3_DML_BASE - 1,
1401 },
1402 {
1403 .name = "core_irq",
1404 .flags = IORESOURCE_IRQ,
1405 .start = SDC3_IRQ_0,
1406 .end = SDC3_IRQ_0
1407 },
1408#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
1409 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301410 .name = "dml_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001411 .start = MSM_SDC3_DML_BASE,
1412 .end = MSM_SDC3_BAM_BASE - 1,
1413 .flags = IORESOURCE_MEM,
1414 },
1415 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301416 .name = "bam_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001417 .start = MSM_SDC3_BAM_BASE,
1418 .end = MSM_SDC3_BAM_BASE + (2 * SZ_4K) - 1,
1419 .flags = IORESOURCE_MEM,
1420 },
1421 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301422 .name = "bam_irq",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001423 .start = SDC3_BAM_IRQ,
1424 .end = SDC3_BAM_IRQ,
1425 .flags = IORESOURCE_IRQ,
1426 },
1427#endif
1428};
1429
1430static struct resource resources_sdc4[] = {
1431 {
1432 .name = "core_mem",
1433 .flags = IORESOURCE_MEM,
1434 .start = MSM_SDC4_BASE,
1435 .end = MSM_SDC4_DML_BASE - 1,
1436 },
1437 {
1438 .name = "core_irq",
1439 .flags = IORESOURCE_IRQ,
1440 .start = SDC4_IRQ_0,
1441 .end = SDC4_IRQ_0
1442 },
1443#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
1444 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301445 .name = "dml_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001446 .start = MSM_SDC4_DML_BASE,
1447 .end = MSM_SDC4_BAM_BASE - 1,
1448 .flags = IORESOURCE_MEM,
1449 },
1450 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301451 .name = "bam_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001452 .start = MSM_SDC4_BAM_BASE,
1453 .end = MSM_SDC4_BAM_BASE + (2 * SZ_4K) - 1,
1454 .flags = IORESOURCE_MEM,
1455 },
1456 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301457 .name = "bam_irq",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001458 .start = SDC4_BAM_IRQ,
1459 .end = SDC4_BAM_IRQ,
1460 .flags = IORESOURCE_IRQ,
1461 },
1462#endif
1463};
1464
1465struct platform_device apq8064_device_sdc1 = {
1466 .name = "msm_sdcc",
1467 .id = 1,
1468 .num_resources = ARRAY_SIZE(resources_sdc1),
1469 .resource = resources_sdc1,
1470 .dev = {
1471 .coherent_dma_mask = 0xffffffff,
1472 },
1473};
1474
1475struct platform_device apq8064_device_sdc2 = {
1476 .name = "msm_sdcc",
1477 .id = 2,
1478 .num_resources = ARRAY_SIZE(resources_sdc2),
1479 .resource = resources_sdc2,
1480 .dev = {
1481 .coherent_dma_mask = 0xffffffff,
1482 },
1483};
1484
1485struct platform_device apq8064_device_sdc3 = {
1486 .name = "msm_sdcc",
1487 .id = 3,
1488 .num_resources = ARRAY_SIZE(resources_sdc3),
1489 .resource = resources_sdc3,
1490 .dev = {
1491 .coherent_dma_mask = 0xffffffff,
1492 },
1493};
1494
1495struct platform_device apq8064_device_sdc4 = {
1496 .name = "msm_sdcc",
1497 .id = 4,
1498 .num_resources = ARRAY_SIZE(resources_sdc4),
1499 .resource = resources_sdc4,
1500 .dev = {
1501 .coherent_dma_mask = 0xffffffff,
1502 },
1503};
1504
1505static struct platform_device *apq8064_sdcc_devices[] __initdata = {
1506 &apq8064_device_sdc1,
1507 &apq8064_device_sdc2,
1508 &apq8064_device_sdc3,
1509 &apq8064_device_sdc4,
1510};
1511
1512int __init apq8064_add_sdcc(unsigned int controller,
1513 struct mmc_platform_data *plat)
1514{
1515 struct platform_device *pdev;
1516
1517 if (!plat)
1518 return 0;
1519 if (controller < 1 || controller > 4)
1520 return -EINVAL;
1521
1522 pdev = apq8064_sdcc_devices[controller-1];
1523 pdev->dev.platform_data = plat;
1524 return platform_device_register(pdev);
1525}
1526
Yan He06913ce2011-08-26 16:33:46 -07001527static struct resource resources_sps[] = {
1528 {
1529 .name = "pipe_mem",
1530 .start = 0x12800000,
1531 .end = 0x12800000 + 0x4000 - 1,
1532 .flags = IORESOURCE_MEM,
1533 },
1534 {
1535 .name = "bamdma_dma",
1536 .start = 0x12240000,
1537 .end = 0x12240000 + 0x1000 - 1,
1538 .flags = IORESOURCE_MEM,
1539 },
1540 {
1541 .name = "bamdma_bam",
1542 .start = 0x12244000,
1543 .end = 0x12244000 + 0x4000 - 1,
1544 .flags = IORESOURCE_MEM,
1545 },
1546 {
1547 .name = "bamdma_irq",
1548 .start = SPS_BAM_DMA_IRQ,
1549 .end = SPS_BAM_DMA_IRQ,
1550 .flags = IORESOURCE_IRQ,
1551 },
1552};
1553
Gagan Mac8a7a5d32011-11-11 16:43:06 -07001554struct platform_device msm_bus_8064_sys_fabric = {
1555 .name = "msm_bus_fabric",
1556 .id = MSM_BUS_FAB_SYSTEM,
1557};
1558struct platform_device msm_bus_8064_apps_fabric = {
1559 .name = "msm_bus_fabric",
1560 .id = MSM_BUS_FAB_APPSS,
1561};
1562struct platform_device msm_bus_8064_mm_fabric = {
1563 .name = "msm_bus_fabric",
1564 .id = MSM_BUS_FAB_MMSS,
1565};
1566struct platform_device msm_bus_8064_sys_fpb = {
1567 .name = "msm_bus_fabric",
1568 .id = MSM_BUS_FAB_SYSTEM_FPB,
1569};
1570struct platform_device msm_bus_8064_cpss_fpb = {
1571 .name = "msm_bus_fabric",
1572 .id = MSM_BUS_FAB_CPSS_FPB,
1573};
1574
Yan He06913ce2011-08-26 16:33:46 -07001575static struct msm_sps_platform_data msm_sps_pdata = {
1576 .bamdma_restricted_pipes = 0x06,
1577};
1578
1579struct platform_device msm_device_sps_apq8064 = {
1580 .name = "msm_sps",
1581 .id = -1,
1582 .num_resources = ARRAY_SIZE(resources_sps),
1583 .resource = resources_sps,
1584 .dev.platform_data = &msm_sps_pdata,
1585};
1586
Eric Holmberg023d25c2012-03-01 12:27:55 -07001587static struct resource smd_resource[] = {
1588 {
1589 .name = "a9_m2a_0",
1590 .start = INT_A9_M2A_0,
1591 .flags = IORESOURCE_IRQ,
1592 },
1593 {
1594 .name = "a9_m2a_5",
1595 .start = INT_A9_M2A_5,
1596 .flags = IORESOURCE_IRQ,
1597 },
1598 {
1599 .name = "adsp_a11",
1600 .start = INT_ADSP_A11,
1601 .flags = IORESOURCE_IRQ,
1602 },
1603 {
1604 .name = "adsp_a11_smsm",
1605 .start = INT_ADSP_A11_SMSM,
1606 .flags = IORESOURCE_IRQ,
1607 },
1608 {
1609 .name = "dsps_a11",
1610 .start = INT_DSPS_A11,
1611 .flags = IORESOURCE_IRQ,
1612 },
1613 {
1614 .name = "dsps_a11_smsm",
1615 .start = INT_DSPS_A11_SMSM,
1616 .flags = IORESOURCE_IRQ,
1617 },
1618 {
1619 .name = "wcnss_a11",
1620 .start = INT_WCNSS_A11,
1621 .flags = IORESOURCE_IRQ,
1622 },
1623 {
1624 .name = "wcnss_a11_smsm",
1625 .start = INT_WCNSS_A11_SMSM,
1626 .flags = IORESOURCE_IRQ,
1627 },
1628};
1629
1630static struct smd_subsystem_config smd_config_list[] = {
1631 {
1632 .irq_config_id = SMD_MODEM,
1633 .subsys_name = "gss",
1634 .edge = SMD_APPS_MODEM,
1635
1636 .smd_int.irq_name = "a9_m2a_0",
1637 .smd_int.flags = IRQF_TRIGGER_RISING,
1638 .smd_int.irq_id = -1,
1639 .smd_int.device_name = "smd_dev",
1640 .smd_int.dev_id = 0,
1641 .smd_int.out_bit_pos = 1 << 3,
1642 .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1643 .smd_int.out_offset = 0x8,
1644
1645 .smsm_int.irq_name = "a9_m2a_5",
1646 .smsm_int.flags = IRQF_TRIGGER_RISING,
1647 .smsm_int.irq_id = -1,
1648 .smsm_int.device_name = "smd_smsm",
1649 .smsm_int.dev_id = 0,
1650 .smsm_int.out_bit_pos = 1 << 4,
1651 .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1652 .smsm_int.out_offset = 0x8,
1653 },
1654 {
1655 .irq_config_id = SMD_Q6,
1656 .subsys_name = "q6",
1657 .edge = SMD_APPS_QDSP,
1658
1659 .smd_int.irq_name = "adsp_a11",
1660 .smd_int.flags = IRQF_TRIGGER_RISING,
1661 .smd_int.irq_id = -1,
1662 .smd_int.device_name = "smd_dev",
1663 .smd_int.dev_id = 0,
1664 .smd_int.out_bit_pos = 1 << 15,
1665 .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1666 .smd_int.out_offset = 0x8,
1667
1668 .smsm_int.irq_name = "adsp_a11_smsm",
1669 .smsm_int.flags = IRQF_TRIGGER_RISING,
1670 .smsm_int.irq_id = -1,
1671 .smsm_int.device_name = "smd_smsm",
1672 .smsm_int.dev_id = 0,
1673 .smsm_int.out_bit_pos = 1 << 14,
1674 .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1675 .smsm_int.out_offset = 0x8,
1676 },
1677 {
1678 .irq_config_id = SMD_DSPS,
1679 .subsys_name = "dsps",
1680 .edge = SMD_APPS_DSPS,
1681
1682 .smd_int.irq_name = "dsps_a11",
1683 .smd_int.flags = IRQF_TRIGGER_RISING,
1684 .smd_int.irq_id = -1,
1685 .smd_int.device_name = "smd_dev",
1686 .smd_int.dev_id = 0,
1687 .smd_int.out_bit_pos = 1,
1688 .smd_int.out_base = (void __iomem *)MSM_SIC_NON_SECURE_BASE,
1689 .smd_int.out_offset = 0x4080,
1690
1691 .smsm_int.irq_name = "dsps_a11_smsm",
1692 .smsm_int.flags = IRQF_TRIGGER_RISING,
1693 .smsm_int.irq_id = -1,
1694 .smsm_int.device_name = "smd_smsm",
1695 .smsm_int.dev_id = 0,
1696 .smsm_int.out_bit_pos = 1,
1697 .smsm_int.out_base = (void __iomem *)MSM_SIC_NON_SECURE_BASE,
1698 .smsm_int.out_offset = 0x4094,
1699 },
1700 {
1701 .irq_config_id = SMD_WCNSS,
1702 .subsys_name = "wcnss",
1703 .edge = SMD_APPS_WCNSS,
1704
1705 .smd_int.irq_name = "wcnss_a11",
1706 .smd_int.flags = IRQF_TRIGGER_RISING,
1707 .smd_int.irq_id = -1,
1708 .smd_int.device_name = "smd_dev",
1709 .smd_int.dev_id = 0,
1710 .smd_int.out_bit_pos = 1 << 25,
1711 .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1712 .smd_int.out_offset = 0x8,
1713
1714 .smsm_int.irq_name = "wcnss_a11_smsm",
1715 .smsm_int.flags = IRQF_TRIGGER_RISING,
1716 .smsm_int.irq_id = -1,
1717 .smsm_int.device_name = "smd_smsm",
1718 .smsm_int.dev_id = 0,
1719 .smsm_int.out_bit_pos = 1 << 23,
1720 .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1721 .smsm_int.out_offset = 0x8,
1722 },
1723};
1724
Eric Holmberg2bb6ccd2012-03-13 13:05:14 -06001725static struct smd_subsystem_restart_config smd_ssr_config = {
1726 .disable_smsm_reset_handshake = 1,
1727};
1728
Eric Holmberg023d25c2012-03-01 12:27:55 -07001729static struct smd_platform smd_platform_data = {
1730 .num_ss_configs = ARRAY_SIZE(smd_config_list),
1731 .smd_ss_configs = smd_config_list,
Eric Holmberg2bb6ccd2012-03-13 13:05:14 -06001732 .smd_ssr_config = &smd_ssr_config,
Eric Holmberg023d25c2012-03-01 12:27:55 -07001733};
1734
Jeff Hugo0c0f5e92011-09-28 13:55:45 -06001735struct platform_device msm_device_smd_apq8064 = {
1736 .name = "msm_smd",
1737 .id = -1,
Eric Holmberg023d25c2012-03-01 12:27:55 -07001738 .resource = smd_resource,
1739 .num_resources = ARRAY_SIZE(smd_resource),
1740 .dev = {
1741 .platform_data = &smd_platform_data,
1742 },
Jeff Hugo0c0f5e92011-09-28 13:55:45 -06001743};
1744
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06001745static struct resource resources_msm_pcie[] = {
1746 {
Niranjana Vishwanathapura68210ff2012-06-24 18:03:49 -06001747 .name = "pcie_parf",
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06001748 .start = PCIE20_PARF_PHYS,
1749 .end = PCIE20_PARF_PHYS + PCIE20_PARF_SIZE - 1,
1750 .flags = IORESOURCE_MEM,
1751 },
1752 {
Niranjana Vishwanathapura68210ff2012-06-24 18:03:49 -06001753 .name = "pcie_elbi",
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06001754 .start = PCIE20_ELBI_PHYS,
1755 .end = PCIE20_ELBI_PHYS + PCIE20_ELBI_SIZE - 1,
1756 .flags = IORESOURCE_MEM,
1757 },
1758 {
1759 .name = "pcie20",
1760 .start = PCIE20_PHYS,
1761 .end = PCIE20_PHYS + PCIE20_SIZE - 1,
1762 .flags = IORESOURCE_MEM,
1763 },
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06001764};
1765
1766struct platform_device msm_device_pcie = {
1767 .name = "msm_pcie",
1768 .id = -1,
1769 .num_resources = ARRAY_SIZE(resources_msm_pcie),
1770 .resource = resources_msm_pcie,
1771};
1772
Ramesh Masavarapuf46be1b2011-11-03 11:13:41 -07001773#ifdef CONFIG_HW_RANDOM_MSM
1774/* PRNG device */
1775#define MSM_PRNG_PHYS 0x1A500000
1776static struct resource rng_resources = {
1777 .flags = IORESOURCE_MEM,
1778 .start = MSM_PRNG_PHYS,
1779 .end = MSM_PRNG_PHYS + SZ_512 - 1,
1780};
1781
1782struct platform_device apq8064_device_rng = {
1783 .name = "msm_rng",
1784 .id = 0,
1785 .num_resources = 1,
1786 .resource = &rng_resources,
1787};
1788#endif
1789
Matt Wagantall292aace2012-01-26 19:12:34 -08001790static struct resource msm_gss_resources[] = {
1791 {
1792 .start = 0x10000000,
1793 .end = 0x10000000 + SZ_256 - 1,
1794 .flags = IORESOURCE_MEM,
1795 },
Matt Wagantall19ac4fd2012-02-03 20:18:23 -08001796 {
1797 .start = 0x10008000,
1798 .end = 0x10008000 + SZ_256 - 1,
1799 .flags = IORESOURCE_MEM,
1800 },
Matt Wagantall292aace2012-01-26 19:12:34 -08001801};
1802
1803struct platform_device msm_gss = {
1804 .name = "pil_gss",
1805 .id = -1,
1806 .num_resources = ARRAY_SIZE(msm_gss_resources),
1807 .resource = msm_gss_resources,
1808};
1809
Matt Wagantall1f65d9d2012-04-25 14:24:20 -07001810static struct fs_driver_data gfx3d_fs_data = {
1811 .clks = (struct fs_clk_data[]){
1812 { .name = "core_clk", .reset_rate = 27000000 },
1813 { .name = "iface_clk" },
1814 { .name = "bus_clk" },
1815 { 0 }
1816 },
1817 .bus_port0 = MSM_BUS_MASTER_GRAPHICS_3D,
1818 .bus_port1 = MSM_BUS_MASTER_GRAPHICS_3D_PORT1,
Matt Wagantall1875d322012-02-22 16:11:33 -08001819};
Matt Wagantall1f65d9d2012-04-25 14:24:20 -07001820
1821static struct fs_driver_data ijpeg_fs_data = {
1822 .clks = (struct fs_clk_data[]){
1823 { .name = "core_clk" },
1824 { .name = "iface_clk" },
1825 { .name = "bus_clk" },
1826 { 0 }
1827 },
1828 .bus_port0 = MSM_BUS_MASTER_JPEG_ENC,
1829};
1830
Nagamalleswararao Ganji6db8c512012-05-24 20:26:23 -07001831static struct fs_driver_data mdp_fs_data = {
1832 .clks = (struct fs_clk_data[]){
1833 { .name = "core_clk" },
1834 { .name = "iface_clk" },
1835 { .name = "bus_clk" },
1836 { .name = "vsync_clk" },
1837 { .name = "lut_clk" },
1838 { .name = "tv_src_clk" },
1839 { .name = "tv_clk" },
1840 { 0 }
1841 },
1842 .bus_port0 = MSM_BUS_MASTER_MDP_PORT0,
1843 .bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
1844};
1845
Matt Wagantall1f65d9d2012-04-25 14:24:20 -07001846static struct fs_driver_data rot_fs_data = {
1847 .clks = (struct fs_clk_data[]){
1848 { .name = "core_clk" },
1849 { .name = "iface_clk" },
1850 { .name = "bus_clk" },
1851 { 0 }
1852 },
1853 .bus_port0 = MSM_BUS_MASTER_ROTATOR,
1854};
1855
1856static struct fs_driver_data ved_fs_data = {
1857 .clks = (struct fs_clk_data[]){
1858 { .name = "core_clk" },
1859 { .name = "iface_clk" },
1860 { .name = "bus_clk" },
1861 { 0 }
1862 },
1863 .bus_port0 = MSM_BUS_MASTER_VIDEO_ENC,
1864 .bus_port1 = MSM_BUS_MASTER_VIDEO_DEC,
1865};
1866
1867static struct fs_driver_data vfe_fs_data = {
1868 .clks = (struct fs_clk_data[]){
1869 { .name = "core_clk" },
1870 { .name = "iface_clk" },
1871 { .name = "bus_clk" },
1872 { 0 }
1873 },
1874 .bus_port0 = MSM_BUS_MASTER_VFE,
1875};
1876
1877static struct fs_driver_data vpe_fs_data = {
1878 .clks = (struct fs_clk_data[]){
1879 { .name = "core_clk" },
1880 { .name = "iface_clk" },
1881 { .name = "bus_clk" },
1882 { 0 }
1883 },
1884 .bus_port0 = MSM_BUS_MASTER_VPE,
1885};
1886
1887static struct fs_driver_data vcap_fs_data = {
1888 .clks = (struct fs_clk_data[]){
1889 { .name = "core_clk" },
1890 { .name = "iface_clk" },
1891 { .name = "bus_clk" },
1892 { 0 },
1893 },
1894 .bus_port0 = MSM_BUS_MASTER_VIDEO_CAP,
1895};
1896
1897struct platform_device *apq8064_footswitch[] __initdata = {
Nagamalleswararao Ganji6db8c512012-05-24 20:26:23 -07001898 FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data),
Matt Wagantall316f2fc2012-05-03 20:41:42 -07001899 FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
Matt Wagantalle4454b82012-05-03 20:48:01 -07001900 FS_8X60(FS_IJPEG, "vdd", "msm_gemini.0", &ijpeg_fs_data),
Kiran Kumar H Nfa18a032012-06-25 14:34:18 -07001901 FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
1902 FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
Matt Wagantalld6fbf232012-05-03 20:09:28 -07001903 FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
Matt Wagantall5e46aac2012-05-03 20:20:18 -07001904 FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
Matt Wagantall3cd5b3d2012-05-03 20:35:20 -07001905 FS_8X60(FS_VCAP, "vdd", "msm_vcap.0", &vcap_fs_data),
Matt Wagantall1f65d9d2012-04-25 14:24:20 -07001906};
1907unsigned apq8064_num_footswitch __initdata = ARRAY_SIZE(apq8064_footswitch);
Matt Wagantall1875d322012-02-22 16:11:33 -08001908
Praveen Chidambaram78499012011-11-01 17:15:17 -06001909struct msm_rpm_platform_data apq8064_rpm_data __initdata = {
1910 .reg_base_addrs = {
1911 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
1912 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
1913 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
1914 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
1915 },
1916 .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
Stephen Boydf61255e2012-02-24 14:31:09 -08001917 .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
Praveen Chidambarame396ce62012-03-30 11:15:57 -06001918 .irq_wakeup = RPM_APCC_CPU0_WAKE_UP_IRQ,
Praveen Chidambaram78499012011-11-01 17:15:17 -06001919 .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
1920 .ipc_rpm_val = 4,
1921 .target_id = {
1922 MSM_RPM_MAP(8064, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
1923 MSM_RPM_MAP(8064, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
1924 MSM_RPM_MAP(8064, INVALIDATE_0, INVALIDATE, 8),
1925 MSM_RPM_MAP(8064, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
1926 MSM_RPM_MAP(8064, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
1927 MSM_RPM_MAP(8064, RPM_CTL, RPM_CTL, 1),
1928 MSM_RPM_MAP(8064, CXO_CLK, CXO_CLK, 1),
1929 MSM_RPM_MAP(8064, PXO_CLK, PXO_CLK, 1),
1930 MSM_RPM_MAP(8064, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
1931 MSM_RPM_MAP(8064, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
1932 MSM_RPM_MAP(8064, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
1933 MSM_RPM_MAP(8064, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
1934 MSM_RPM_MAP(8064, SFPB_CLK, SFPB_CLK, 1),
1935 MSM_RPM_MAP(8064, CFPB_CLK, CFPB_CLK, 1),
1936 MSM_RPM_MAP(8064, MMFPB_CLK, MMFPB_CLK, 1),
1937 MSM_RPM_MAP(8064, EBI1_CLK, EBI1_CLK, 1),
1938 MSM_RPM_MAP(8064, APPS_FABRIC_CFG_HALT_0,
1939 APPS_FABRIC_CFG_HALT, 2),
1940 MSM_RPM_MAP(8064, APPS_FABRIC_CFG_CLKMOD_0,
1941 APPS_FABRIC_CFG_CLKMOD, 3),
1942 MSM_RPM_MAP(8064, APPS_FABRIC_CFG_IOCTL,
1943 APPS_FABRIC_CFG_IOCTL, 1),
1944 MSM_RPM_MAP(8064, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
1945 MSM_RPM_MAP(8064, SYS_FABRIC_CFG_HALT_0,
1946 SYS_FABRIC_CFG_HALT, 2),
1947 MSM_RPM_MAP(8064, SYS_FABRIC_CFG_CLKMOD_0,
1948 SYS_FABRIC_CFG_CLKMOD, 3),
1949 MSM_RPM_MAP(8064, SYS_FABRIC_CFG_IOCTL,
1950 SYS_FABRIC_CFG_IOCTL, 1),
1951 MSM_RPM_MAP(8064, SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 30),
1952 MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_HALT_0,
1953 MMSS_FABRIC_CFG_HALT, 2),
1954 MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_CLKMOD_0,
1955 MMSS_FABRIC_CFG_CLKMOD, 3),
1956 MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_IOCTL,
1957 MMSS_FABRIC_CFG_IOCTL, 1),
1958 MSM_RPM_MAP(8064, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 21),
1959 MSM_RPM_MAP(8064, PM8921_S1_0, PM8921_S1, 2),
1960 MSM_RPM_MAP(8064, PM8921_S2_0, PM8921_S2, 2),
1961 MSM_RPM_MAP(8064, PM8921_S3_0, PM8921_S3, 2),
1962 MSM_RPM_MAP(8064, PM8921_S4_0, PM8921_S4, 2),
1963 MSM_RPM_MAP(8064, PM8921_S5_0, PM8921_S5, 2),
1964 MSM_RPM_MAP(8064, PM8921_S6_0, PM8921_S6, 2),
1965 MSM_RPM_MAP(8064, PM8921_S7_0, PM8921_S7, 2),
1966 MSM_RPM_MAP(8064, PM8921_S8_0, PM8921_S8, 2),
1967 MSM_RPM_MAP(8064, PM8921_L1_0, PM8921_L1, 2),
1968 MSM_RPM_MAP(8064, PM8921_L2_0, PM8921_L2, 2),
1969 MSM_RPM_MAP(8064, PM8921_L3_0, PM8921_L3, 2),
1970 MSM_RPM_MAP(8064, PM8921_L4_0, PM8921_L4, 2),
1971 MSM_RPM_MAP(8064, PM8921_L5_0, PM8921_L5, 2),
1972 MSM_RPM_MAP(8064, PM8921_L6_0, PM8921_L6, 2),
1973 MSM_RPM_MAP(8064, PM8921_L7_0, PM8921_L7, 2),
1974 MSM_RPM_MAP(8064, PM8921_L8_0, PM8921_L8, 2),
1975 MSM_RPM_MAP(8064, PM8921_L9_0, PM8921_L9, 2),
1976 MSM_RPM_MAP(8064, PM8921_L10_0, PM8921_L10, 2),
1977 MSM_RPM_MAP(8064, PM8921_L11_0, PM8921_L11, 2),
1978 MSM_RPM_MAP(8064, PM8921_L12_0, PM8921_L12, 2),
1979 MSM_RPM_MAP(8064, PM8921_L13_0, PM8921_L13, 2),
1980 MSM_RPM_MAP(8064, PM8921_L14_0, PM8921_L14, 2),
1981 MSM_RPM_MAP(8064, PM8921_L15_0, PM8921_L15, 2),
1982 MSM_RPM_MAP(8064, PM8921_L16_0, PM8921_L16, 2),
1983 MSM_RPM_MAP(8064, PM8921_L17_0, PM8921_L17, 2),
1984 MSM_RPM_MAP(8064, PM8921_L18_0, PM8921_L18, 2),
1985 MSM_RPM_MAP(8064, PM8921_L19_0, PM8921_L19, 2),
1986 MSM_RPM_MAP(8064, PM8921_L20_0, PM8921_L20, 2),
1987 MSM_RPM_MAP(8064, PM8921_L21_0, PM8921_L21, 2),
1988 MSM_RPM_MAP(8064, PM8921_L22_0, PM8921_L22, 2),
1989 MSM_RPM_MAP(8064, PM8921_L23_0, PM8921_L23, 2),
1990 MSM_RPM_MAP(8064, PM8921_L24_0, PM8921_L24, 2),
1991 MSM_RPM_MAP(8064, PM8921_L25_0, PM8921_L25, 2),
1992 MSM_RPM_MAP(8064, PM8921_L26_0, PM8921_L26, 2),
1993 MSM_RPM_MAP(8064, PM8921_L27_0, PM8921_L27, 2),
1994 MSM_RPM_MAP(8064, PM8921_L28_0, PM8921_L28, 2),
1995 MSM_RPM_MAP(8064, PM8921_L29_0, PM8921_L29, 2),
1996 MSM_RPM_MAP(8064, PM8921_CLK1_0, PM8921_CLK1, 2),
1997 MSM_RPM_MAP(8064, PM8921_CLK2_0, PM8921_CLK2, 2),
1998 MSM_RPM_MAP(8064, PM8921_LVS1, PM8921_LVS1, 1),
1999 MSM_RPM_MAP(8064, PM8921_LVS2, PM8921_LVS2, 1),
2000 MSM_RPM_MAP(8064, PM8921_LVS3, PM8921_LVS3, 1),
2001 MSM_RPM_MAP(8064, PM8921_LVS4, PM8921_LVS4, 1),
2002 MSM_RPM_MAP(8064, PM8921_LVS5, PM8921_LVS5, 1),
2003 MSM_RPM_MAP(8064, PM8921_LVS6, PM8921_LVS6, 1),
2004 MSM_RPM_MAP(8064, PM8921_LVS7, PM8921_LVS7, 1),
2005 MSM_RPM_MAP(8064, PM8821_S1_0, PM8821_S1, 2),
2006 MSM_RPM_MAP(8064, PM8821_S2_0, PM8821_S2, 2),
2007 MSM_RPM_MAP(8064, PM8821_L1_0, PM8821_L1, 2),
2008 MSM_RPM_MAP(8064, NCP_0, NCP, 2),
2009 MSM_RPM_MAP(8064, CXO_BUFFERS, CXO_BUFFERS, 1),
2010 MSM_RPM_MAP(8064, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
2011 MSM_RPM_MAP(8064, HDMI_SWITCH, HDMI_SWITCH, 1),
2012 MSM_RPM_MAP(8064, DDR_DMM_0, DDR_DMM, 2),
2013 MSM_RPM_MAP(8064, QDSS_CLK, QDSS_CLK, 1),
Joel Kingef390842012-05-23 16:42:48 -07002014 MSM_RPM_MAP(8064, VDDMIN_GPIO, VDDMIN_GPIO, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -06002015 },
2016 .target_status = {
2017 MSM_RPM_STATUS_ID_MAP(8064, VERSION_MAJOR),
2018 MSM_RPM_STATUS_ID_MAP(8064, VERSION_MINOR),
2019 MSM_RPM_STATUS_ID_MAP(8064, VERSION_BUILD),
2020 MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_0),
2021 MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_1),
2022 MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_2),
2023 MSM_RPM_STATUS_ID_MAP(8064, RESERVED_SUPPORTED_RESOURCES_0),
2024 MSM_RPM_STATUS_ID_MAP(8064, SEQUENCE),
2025 MSM_RPM_STATUS_ID_MAP(8064, RPM_CTL),
2026 MSM_RPM_STATUS_ID_MAP(8064, CXO_CLK),
2027 MSM_RPM_STATUS_ID_MAP(8064, PXO_CLK),
2028 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CLK),
2029 MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_CLK),
2030 MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_CLK),
2031 MSM_RPM_STATUS_ID_MAP(8064, DAYTONA_FABRIC_CLK),
2032 MSM_RPM_STATUS_ID_MAP(8064, SFPB_CLK),
2033 MSM_RPM_STATUS_ID_MAP(8064, CFPB_CLK),
2034 MSM_RPM_STATUS_ID_MAP(8064, MMFPB_CLK),
2035 MSM_RPM_STATUS_ID_MAP(8064, EBI1_CLK),
2036 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_HALT),
2037 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_CLKMOD),
2038 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_IOCTL),
2039 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_ARB),
2040 MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_HALT),
2041 MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_CLKMOD),
2042 MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_IOCTL),
2043 MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_ARB),
2044 MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_HALT),
2045 MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_CLKMOD),
2046 MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_IOCTL),
2047 MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_ARB),
2048 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_0),
2049 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_1),
2050 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_0),
2051 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_1),
2052 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_0),
2053 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_1),
2054 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_0),
2055 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_1),
2056 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_0),
2057 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_1),
2058 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_0),
2059 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_1),
2060 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_0),
2061 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_1),
2062 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_0),
2063 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_1),
2064 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_0),
2065 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_1),
2066 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_0),
2067 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_1),
2068 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_0),
2069 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_1),
2070 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_0),
2071 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_1),
2072 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_0),
2073 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_1),
2074 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_0),
2075 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_1),
2076 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_0),
2077 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_1),
2078 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_0),
2079 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_1),
2080 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_0),
2081 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_1),
2082 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_0),
2083 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_1),
2084 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_0),
2085 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_1),
2086 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_0),
2087 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_1),
2088 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_0),
2089 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_1),
2090 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_0),
2091 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_1),
2092 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_0),
2093 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_1),
2094 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_0),
2095 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_1),
2096 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_0),
2097 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_1),
2098 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_0),
2099 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_1),
2100 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_0),
2101 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_1),
2102 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_0),
2103 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_1),
2104 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_0),
2105 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_1),
2106 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_0),
2107 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_1),
2108 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_0),
2109 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_1),
2110 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_0),
2111 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_1),
2112 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_0),
2113 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_1),
2114 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_0),
2115 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_1),
2116 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_0),
2117 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_1),
2118 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_0),
2119 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_1),
2120 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_0),
2121 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_1),
2122 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_0),
2123 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_1),
2124 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_0),
2125 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_1),
2126 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS1),
2127 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS2),
2128 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS3),
2129 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS4),
2130 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS5),
2131 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS6),
2132 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS7),
2133 MSM_RPM_STATUS_ID_MAP(8064, NCP_0),
2134 MSM_RPM_STATUS_ID_MAP(8064, NCP_1),
2135 MSM_RPM_STATUS_ID_MAP(8064, CXO_BUFFERS),
2136 MSM_RPM_STATUS_ID_MAP(8064, USB_OTG_SWITCH),
2137 MSM_RPM_STATUS_ID_MAP(8064, HDMI_SWITCH),
2138 MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_0),
2139 MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_1),
2140 MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH0_RANGE),
2141 MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH1_RANGE),
2142 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_0),
2143 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_1),
2144 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_0),
2145 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_1),
2146 MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_0),
2147 MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_1),
Joel Kingef390842012-05-23 16:42:48 -07002148 MSM_RPM_STATUS_ID_MAP(8064, VDDMIN_GPIO),
Praveen Chidambaram78499012011-11-01 17:15:17 -06002149 },
2150 .target_ctrl_id = {
2151 MSM_RPM_CTRL_MAP(8064, VERSION_MAJOR),
2152 MSM_RPM_CTRL_MAP(8064, VERSION_MINOR),
2153 MSM_RPM_CTRL_MAP(8064, VERSION_BUILD),
2154 MSM_RPM_CTRL_MAP(8064, REQ_CTX_0),
2155 MSM_RPM_CTRL_MAP(8064, REQ_SEL_0),
2156 MSM_RPM_CTRL_MAP(8064, ACK_CTX_0),
2157 MSM_RPM_CTRL_MAP(8064, ACK_SEL_0),
2158 },
2159 .sel_invalidate = MSM_RPM_8064_SEL_INVALIDATE,
2160 .sel_notification = MSM_RPM_8064_SEL_NOTIFICATION,
2161 .sel_last = MSM_RPM_8064_SEL_LAST,
2162 .ver = {3, 0, 0},
2163};
2164
2165struct platform_device apq8064_rpm_device = {
2166 .name = "msm_rpm",
2167 .id = -1,
2168};
2169
2170static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
2171 .phys_addr_base = 0x0010D204,
2172 .phys_size = SZ_8K,
2173};
2174
2175struct platform_device apq8064_rpm_stat_device = {
2176 .name = "msm_rpm_stat",
2177 .id = -1,
2178 .dev = {
2179 .platform_data = &msm_rpm_stat_pdata,
2180 },
2181};
2182
2183static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
2184 .phys_addr_base = 0x0010C000,
2185 .reg_offsets = {
2186 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
2187 [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
2188 },
2189 .phys_size = SZ_8K,
2190 .log_len = 4096, /* log's buffer length in bytes */
2191 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
2192};
2193
2194struct platform_device apq8064_rpm_log_device = {
2195 .name = "msm_rpm_log",
2196 .id = -1,
2197 .dev = {
2198 .platform_data = &msm_rpm_log_pdata,
2199 },
2200};
2201
Jin Hongd3024e62012-02-09 16:13:32 -08002202/* Sensors DSPS platform data */
2203
karthik karuppasamy1a1c6b02012-05-29 15:16:32 -07002204#define PPSS_DSPS_TCM_CODE_BASE 0x12000000
2205#define PPSS_DSPS_TCM_CODE_SIZE 0x28000
2206#define PPSS_DSPS_TCM_BUF_BASE 0x12040000
2207#define PPSS_DSPS_TCM_BUF_SIZE 0x4000
2208#define PPSS_DSPS_PIPE_BASE 0x12800000
2209#define PPSS_DSPS_PIPE_SIZE 0x4000
2210#define PPSS_DSPS_DDR_BASE 0x8fe00000
2211#define PPSS_DSPS_DDR_SIZE 0x100000
2212#define PPSS_SMEM_BASE 0x80000000
2213#define PPSS_SMEM_SIZE 0x200000
Jin Hongd3024e62012-02-09 16:13:32 -08002214#define PPSS_REG_PHYS_BASE 0x12080000
2215
2216static struct dsps_clk_info dsps_clks[] = {};
2217static struct dsps_regulator_info dsps_regs[] = {};
2218
2219/*
2220 * Note: GPIOs field is intialized in run-time at the function
2221 * apq8064_init_dsps().
2222 */
2223
2224struct msm_dsps_platform_data msm_dsps_pdata_8064 = {
2225 .clks = dsps_clks,
2226 .clks_num = ARRAY_SIZE(dsps_clks),
2227 .gpios = NULL,
2228 .gpios_num = 0,
2229 .regs = dsps_regs,
2230 .regs_num = ARRAY_SIZE(dsps_regs),
2231 .dsps_pwr_ctl_en = 1,
karthik karuppasamy1a1c6b02012-05-29 15:16:32 -07002232 .tcm_code_start = PPSS_DSPS_TCM_CODE_BASE,
2233 .tcm_code_size = PPSS_DSPS_TCM_CODE_SIZE,
2234 .tcm_buf_start = PPSS_DSPS_TCM_BUF_BASE,
2235 .tcm_buf_size = PPSS_DSPS_TCM_BUF_SIZE,
2236 .pipe_start = PPSS_DSPS_PIPE_BASE,
2237 .pipe_size = PPSS_DSPS_PIPE_SIZE,
2238 .ddr_start = PPSS_DSPS_DDR_BASE,
2239 .ddr_size = PPSS_DSPS_DDR_SIZE,
2240 .smem_start = PPSS_SMEM_BASE,
2241 .smem_size = PPSS_SMEM_SIZE,
Jin Hongd3024e62012-02-09 16:13:32 -08002242 .signature = DSPS_SIGNATURE,
2243};
2244
2245static struct resource msm_dsps_resources[] = {
2246 {
2247 .start = PPSS_REG_PHYS_BASE,
2248 .end = PPSS_REG_PHYS_BASE + SZ_8K - 1,
2249 .name = "ppss_reg",
2250 .flags = IORESOURCE_MEM,
2251 },
2252
2253 {
2254 .start = PPSS_WDOG_TIMER_IRQ,
2255 .end = PPSS_WDOG_TIMER_IRQ,
2256 .name = "ppss_wdog",
2257 .flags = IORESOURCE_IRQ,
2258 },
2259};
2260
2261struct platform_device msm_dsps_device_8064 = {
2262 .name = "msm_dsps",
2263 .id = 0,
2264 .num_resources = ARRAY_SIZE(msm_dsps_resources),
2265 .resource = msm_dsps_resources,
2266 .dev.platform_data = &msm_dsps_pdata_8064,
2267};
2268
Praveen Chidambaram78499012011-11-01 17:15:17 -06002269#ifdef CONFIG_MSM_MPM
2270static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
2271 [1] = MSM_GPIO_TO_INT(26),
2272 [2] = MSM_GPIO_TO_INT(88),
2273 [4] = MSM_GPIO_TO_INT(73),
2274 [5] = MSM_GPIO_TO_INT(74),
2275 [6] = MSM_GPIO_TO_INT(75),
2276 [7] = MSM_GPIO_TO_INT(76),
2277 [8] = MSM_GPIO_TO_INT(77),
2278 [9] = MSM_GPIO_TO_INT(36),
2279 [10] = MSM_GPIO_TO_INT(84),
2280 [11] = MSM_GPIO_TO_INT(7),
2281 [12] = MSM_GPIO_TO_INT(11),
2282 [13] = MSM_GPIO_TO_INT(52),
2283 [14] = MSM_GPIO_TO_INT(15),
2284 [15] = MSM_GPIO_TO_INT(83),
2285 [16] = USB3_HS_IRQ,
2286 [19] = MSM_GPIO_TO_INT(61),
2287 [20] = MSM_GPIO_TO_INT(58),
2288 [23] = MSM_GPIO_TO_INT(65),
2289 [24] = MSM_GPIO_TO_INT(63),
2290 [25] = USB1_HS_IRQ,
2291 [27] = HDMI_IRQ,
2292 [29] = MSM_GPIO_TO_INT(22),
2293 [30] = MSM_GPIO_TO_INT(72),
2294 [31] = USB4_HS_IRQ,
2295 [33] = MSM_GPIO_TO_INT(44),
2296 [34] = MSM_GPIO_TO_INT(39),
2297 [35] = MSM_GPIO_TO_INT(19),
2298 [36] = MSM_GPIO_TO_INT(23),
2299 [37] = MSM_GPIO_TO_INT(41),
2300 [38] = MSM_GPIO_TO_INT(30),
2301 [41] = MSM_GPIO_TO_INT(42),
2302 [42] = MSM_GPIO_TO_INT(56),
2303 [43] = MSM_GPIO_TO_INT(55),
2304 [44] = MSM_GPIO_TO_INT(50),
2305 [45] = MSM_GPIO_TO_INT(49),
2306 [46] = MSM_GPIO_TO_INT(47),
2307 [47] = MSM_GPIO_TO_INT(45),
2308 [48] = MSM_GPIO_TO_INT(38),
2309 [49] = MSM_GPIO_TO_INT(34),
2310 [50] = MSM_GPIO_TO_INT(32),
2311 [51] = MSM_GPIO_TO_INT(29),
2312 [52] = MSM_GPIO_TO_INT(18),
2313 [53] = MSM_GPIO_TO_INT(10),
2314 [54] = MSM_GPIO_TO_INT(81),
2315 [55] = MSM_GPIO_TO_INT(6),
2316};
2317
2318static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
2319 TLMM_MSM_SUMMARY_IRQ,
2320 RPM_APCC_CPU0_GP_HIGH_IRQ,
2321 RPM_APCC_CPU0_GP_MEDIUM_IRQ,
2322 RPM_APCC_CPU0_GP_LOW_IRQ,
2323 RPM_APCC_CPU0_WAKE_UP_IRQ,
2324 RPM_APCC_CPU1_GP_HIGH_IRQ,
2325 RPM_APCC_CPU1_GP_MEDIUM_IRQ,
2326 RPM_APCC_CPU1_GP_LOW_IRQ,
2327 RPM_APCC_CPU1_WAKE_UP_IRQ,
2328 MSS_TO_APPS_IRQ_0,
2329 MSS_TO_APPS_IRQ_1,
2330 MSS_TO_APPS_IRQ_2,
2331 MSS_TO_APPS_IRQ_3,
2332 MSS_TO_APPS_IRQ_4,
2333 MSS_TO_APPS_IRQ_5,
2334 MSS_TO_APPS_IRQ_6,
2335 MSS_TO_APPS_IRQ_7,
2336 MSS_TO_APPS_IRQ_8,
2337 MSS_TO_APPS_IRQ_9,
2338 LPASS_SCSS_GP_LOW_IRQ,
2339 LPASS_SCSS_GP_MEDIUM_IRQ,
2340 LPASS_SCSS_GP_HIGH_IRQ,
2341 SPS_MTI_30,
2342 SPS_MTI_31,
2343 RIVA_APSS_SPARE_IRQ,
2344 RIVA_APPS_WLAN_SMSM_IRQ,
2345 RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
2346 RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
Chandra Ramachandran59851722012-07-23 11:19:48 -07002347 PM8821_SEC_IRQ_N,
Praveen Chidambaram78499012011-11-01 17:15:17 -06002348};
2349
2350struct msm_mpm_device_data apq8064_mpm_dev_data __initdata = {
2351 .irqs_m2a = msm_mpm_irqs_m2a,
2352 .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
2353 .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
2354 .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
2355 .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
2356 .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
2357 .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
2358 .mpm_apps_ipc_val = BIT(1),
2359 .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
2360
2361};
2362#endif
Joel Kingdacbc822012-01-25 13:30:57 -08002363
Joel King14fe7fa2012-05-27 14:26:11 -07002364/* AP2MDM_SOFT_RESET is implemented by the PON_RESET_N gpio */
Joel Kingdacbc822012-01-25 13:30:57 -08002365#define MDM2AP_ERRFATAL 19
2366#define AP2MDM_ERRFATAL 18
2367#define MDM2AP_STATUS 49
2368#define AP2MDM_STATUS 48
Joel King14fe7fa2012-05-27 14:26:11 -07002369#define AP2MDM_SOFT_RESET 27
Vamsi Krishna9e307cd2012-04-11 13:15:36 -07002370#define AP2MDM_WAKEUP 35
Vamsi Krishnac6dcd5e2012-05-09 15:38:01 -07002371#define MDM2AP_PBLRDY 46
Joel Kingdacbc822012-01-25 13:30:57 -08002372
2373static struct resource mdm_resources[] = {
2374 {
2375 .start = MDM2AP_ERRFATAL,
2376 .end = MDM2AP_ERRFATAL,
2377 .name = "MDM2AP_ERRFATAL",
2378 .flags = IORESOURCE_IO,
2379 },
2380 {
2381 .start = AP2MDM_ERRFATAL,
2382 .end = AP2MDM_ERRFATAL,
2383 .name = "AP2MDM_ERRFATAL",
2384 .flags = IORESOURCE_IO,
2385 },
2386 {
2387 .start = MDM2AP_STATUS,
2388 .end = MDM2AP_STATUS,
2389 .name = "MDM2AP_STATUS",
2390 .flags = IORESOURCE_IO,
2391 },
2392 {
2393 .start = AP2MDM_STATUS,
2394 .end = AP2MDM_STATUS,
2395 .name = "AP2MDM_STATUS",
2396 .flags = IORESOURCE_IO,
2397 },
2398 {
Joel King14fe7fa2012-05-27 14:26:11 -07002399 .start = AP2MDM_SOFT_RESET,
2400 .end = AP2MDM_SOFT_RESET,
2401 .name = "AP2MDM_SOFT_RESET",
Joel Kingdacbc822012-01-25 13:30:57 -08002402 .flags = IORESOURCE_IO,
2403 },
Vamsi Krishna9e307cd2012-04-11 13:15:36 -07002404 {
2405 .start = AP2MDM_WAKEUP,
2406 .end = AP2MDM_WAKEUP,
2407 .name = "AP2MDM_WAKEUP",
2408 .flags = IORESOURCE_IO,
2409 },
Vamsi Krishnac6dcd5e2012-05-09 15:38:01 -07002410 {
2411 .start = MDM2AP_PBLRDY,
2412 .end = MDM2AP_PBLRDY,
2413 .name = "MDM2AP_PBLRDY",
2414 .flags = IORESOURCE_IO,
2415 },
Joel Kingdacbc822012-01-25 13:30:57 -08002416};
2417
2418struct platform_device mdm_8064_device = {
2419 .name = "mdm2_modem",
2420 .id = -1,
2421 .num_resources = ARRAY_SIZE(mdm_resources),
2422 .resource = mdm_resources,
2423};
Praveen Chidambaram8ea3dcd2011-12-07 14:46:31 -07002424
2425static int apq8064_LPM_latency = 1000; /* >100 usec for WFI */
2426
2427struct platform_device apq8064_cpu_idle_device = {
2428 .name = "msm_cpu_idle",
2429 .id = -1,
2430 .dev = {
2431 .platform_data = &apq8064_LPM_latency,
2432 },
2433};
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -07002434
2435static struct msm_dcvs_freq_entry apq8064_freq[] = {
2436 { 384000, 166981, 345600},
2437 { 702000, 213049, 632502},
2438 {1026000, 285712, 925613},
2439 {1242000, 383945, 1176550},
2440 {1458000, 419729, 1465478},
2441 {1512000, 434116, 1546674},
2442
2443};
2444
2445static struct msm_dcvs_core_info apq8064_core_info = {
2446 .freq_tbl = &apq8064_freq[0],
2447 .core_param = {
2448 .max_time_us = 100000,
2449 .num_freq = ARRAY_SIZE(apq8064_freq),
2450 },
2451 .algo_param = {
2452 .slack_time_us = 58000,
2453 .scale_slack_time = 0,
2454 .scale_slack_time_pct = 0,
2455 .disable_pc_threshold = 1458000,
2456 .em_window_size = 100000,
2457 .em_max_util_pct = 97,
2458 .ss_window_size = 1000000,
2459 .ss_util_pct = 95,
2460 .ss_iobusy_conv = 100,
2461 },
2462};
2463
2464struct platform_device apq8064_msm_gov_device = {
2465 .name = "msm_dcvs_gov",
2466 .id = -1,
2467 .dev = {
2468 .platform_data = &apq8064_core_info,
2469 },
2470};
Stepan Moskovchenko28662c52012-03-01 12:48:45 -08002471
Terence Hampson2e1705f2012-04-11 19:55:29 -04002472#ifdef CONFIG_MSM_VCAP
2473#define VCAP_HW_BASE 0x05900000
2474
2475static struct msm_bus_vectors vcap_init_vectors[] = {
2476 {
2477 .src = MSM_BUS_MASTER_VIDEO_CAP,
2478 .dst = MSM_BUS_SLAVE_EBI_CH0,
2479 .ab = 0,
2480 .ib = 0,
2481 },
2482};
2483
Terence Hampson2e1705f2012-04-11 19:55:29 -04002484static struct msm_bus_vectors vcap_480_vectors[] = {
2485 {
2486 .src = MSM_BUS_MASTER_VIDEO_CAP,
2487 .dst = MSM_BUS_SLAVE_EBI_CH0,
Terence Hampson779dc762012-06-07 15:59:27 -04002488 .ab = 480 * 720 * 3 * 60,
2489 .ib = 480 * 720 * 3 * 60 * 1.5,
2490 },
2491};
2492
2493static struct msm_bus_vectors vcap_576_vectors[] = {
2494 {
2495 .src = MSM_BUS_MASTER_VIDEO_CAP,
2496 .dst = MSM_BUS_SLAVE_EBI_CH0,
2497 .ab = 576 * 720 * 3 * 60,
2498 .ib = 576 * 720 * 3 * 60 * 1.5,
Terence Hampson2e1705f2012-04-11 19:55:29 -04002499 },
2500};
2501
2502static struct msm_bus_vectors vcap_720_vectors[] = {
2503 {
2504 .src = MSM_BUS_MASTER_VIDEO_CAP,
2505 .dst = MSM_BUS_SLAVE_EBI_CH0,
Terence Hampson35a1ff02012-04-25 17:07:18 -04002506 .ab = 1280 * 720 * 3 * 60,
2507 .ib = 1280 * 720 * 3 * 60 * 1.5,
Terence Hampson2e1705f2012-04-11 19:55:29 -04002508 },
2509};
2510
2511static struct msm_bus_vectors vcap_1080_vectors[] = {
2512 {
2513 .src = MSM_BUS_MASTER_VIDEO_CAP,
2514 .dst = MSM_BUS_SLAVE_EBI_CH0,
Terence Hampson35a1ff02012-04-25 17:07:18 -04002515 .ab = 1920 * 1080 * 3 * 60,
2516 .ib = 1920 * 1080 * 3 * 60 * 1.5,
Terence Hampson2e1705f2012-04-11 19:55:29 -04002517 },
2518};
2519
2520static struct msm_bus_paths vcap_bus_usecases[] = {
2521 {
2522 ARRAY_SIZE(vcap_init_vectors),
2523 vcap_init_vectors,
2524 },
2525 {
2526 ARRAY_SIZE(vcap_480_vectors),
2527 vcap_480_vectors,
2528 },
2529 {
Terence Hampson779dc762012-06-07 15:59:27 -04002530 ARRAY_SIZE(vcap_576_vectors),
2531 vcap_576_vectors,
2532 },
2533 {
Terence Hampson2e1705f2012-04-11 19:55:29 -04002534 ARRAY_SIZE(vcap_720_vectors),
2535 vcap_720_vectors,
2536 },
2537 {
2538 ARRAY_SIZE(vcap_1080_vectors),
2539 vcap_1080_vectors,
2540 },
2541};
2542
2543static struct msm_bus_scale_pdata vcap_axi_client_pdata = {
2544 vcap_bus_usecases,
2545 ARRAY_SIZE(vcap_bus_usecases),
2546};
2547
2548static struct resource msm_vcap_resources[] = {
2549 {
2550 .name = "vcap",
2551 .start = VCAP_HW_BASE,
2552 .end = VCAP_HW_BASE + SZ_1M - 1,
2553 .flags = IORESOURCE_MEM,
2554 },
2555 {
Terence Hampsonaeb793e2012-05-11 11:41:16 -04002556 .name = "vc_irq",
Terence Hampson2e1705f2012-04-11 19:55:29 -04002557 .start = VCAP_VC,
2558 .end = VCAP_VC,
2559 .flags = IORESOURCE_IRQ,
2560 },
Terence Hampsonaeb793e2012-05-11 11:41:16 -04002561 {
2562 .name = "vp_irq",
2563 .start = VCAP_VP,
2564 .end = VCAP_VP,
2565 .flags = IORESOURCE_IRQ,
2566 },
Terence Hampson2e1705f2012-04-11 19:55:29 -04002567};
2568
2569static unsigned vcap_gpios[] = {
2570 2, 3, 4, 5, 6, 7, 8, 9, 10,
2571 11, 12, 13, 18, 19, 20, 21,
2572 22, 23, 24, 25, 26, 80, 82,
2573 83, 84, 85, 86, 87,
2574};
2575
2576static struct vcap_platform_data vcap_pdata = {
2577 .gpios = vcap_gpios,
2578 .num_gpios = ARRAY_SIZE(vcap_gpios),
2579 .bus_client_pdata = &vcap_axi_client_pdata
2580};
2581
2582struct platform_device msm8064_device_vcap = {
2583 .name = "msm_vcap",
2584 .id = 0,
2585 .resource = msm_vcap_resources,
2586 .num_resources = ARRAY_SIZE(msm_vcap_resources),
2587 .dev = {
2588 .platform_data = &vcap_pdata,
2589 },
2590};
2591#endif
2592
Stepan Moskovchenko28662c52012-03-01 12:48:45 -08002593static struct resource msm_cache_erp_resources[] = {
2594 {
2595 .name = "l1_irq",
2596 .start = SC_SICCPUXEXTFAULTIRPTREQ,
2597 .flags = IORESOURCE_IRQ,
2598 },
2599 {
2600 .name = "l2_irq",
2601 .start = APCC_QGICL2IRPTREQ,
2602 .flags = IORESOURCE_IRQ,
2603 }
2604};
2605
2606struct platform_device apq8064_device_cache_erp = {
2607 .name = "msm_cache_erp",
2608 .id = -1,
2609 .num_resources = ARRAY_SIZE(msm_cache_erp_resources),
2610 .resource = msm_cache_erp_resources,
2611};
Pratik Patel212ab362012-03-16 12:30:07 -07002612
2613#define MSM_QDSS_PHYS_BASE 0x01A00000
2614#define MSM_ETM_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x1C000)
2615
2616#define QDSS_SOURCE(src_name, fpm) { .name = src_name, .fport_mask = fpm, }
2617
2618static struct qdss_source msm_qdss_sources[] = {
2619 QDSS_SOURCE("msm_etm", 0x33),
2620 QDSS_SOURCE("msm_oxili", 0x80),
2621};
2622
2623static struct msm_qdss_platform_data qdss_pdata = {
2624 .src_table = msm_qdss_sources,
2625 .size = ARRAY_SIZE(msm_qdss_sources),
2626 .afamily = 1,
2627};
2628
2629struct platform_device apq8064_qdss_device = {
2630 .name = "msm_qdss",
2631 .id = -1,
2632 .dev = {
2633 .platform_data = &qdss_pdata,
2634 },
2635};
2636
2637static struct resource msm_etm_resources[] = {
2638 {
2639 .start = MSM_ETM_PHYS_BASE,
2640 .end = MSM_ETM_PHYS_BASE + (SZ_4K * 4) - 1,
2641 .flags = IORESOURCE_MEM,
2642 },
2643};
2644
2645struct platform_device apq8064_etm_device = {
2646 .name = "msm_etm",
2647 .id = 0,
2648 .num_resources = ARRAY_SIZE(msm_etm_resources),
2649 .resource = msm_etm_resources,
2650};
Laura Abbott0577d7b2012-04-17 11:14:30 -07002651
2652struct msm_iommu_domain_name apq8064_iommu_ctx_names[] = {
2653 /* Camera */
2654 {
2655 .name = "vpe_src",
2656 .domain = CAMERA_DOMAIN,
2657 },
2658 /* Camera */
2659 {
2660 .name = "vpe_dst",
2661 .domain = CAMERA_DOMAIN,
2662 },
2663 /* Camera */
2664 {
2665 .name = "vfe_imgwr",
2666 .domain = CAMERA_DOMAIN,
2667 },
2668 /* Camera */
2669 {
2670 .name = "vfe_misc",
2671 .domain = CAMERA_DOMAIN,
2672 },
2673 /* Camera */
2674 {
2675 .name = "ijpeg_src",
2676 .domain = CAMERA_DOMAIN,
2677 },
2678 /* Camera */
2679 {
2680 .name = "ijpeg_dst",
2681 .domain = CAMERA_DOMAIN,
2682 },
2683 /* Camera */
2684 {
2685 .name = "jpegd_src",
2686 .domain = CAMERA_DOMAIN,
2687 },
2688 /* Camera */
2689 {
2690 .name = "jpegd_dst",
2691 .domain = CAMERA_DOMAIN,
2692 },
Olav Hauganef95ae32012-05-15 09:50:30 -07002693 /* Rotator src*/
Laura Abbott0577d7b2012-04-17 11:14:30 -07002694 {
2695 .name = "rot_src",
Olav Hauganef95ae32012-05-15 09:50:30 -07002696 .domain = ROTATOR_SRC_DOMAIN,
Laura Abbott0577d7b2012-04-17 11:14:30 -07002697 },
Olav Hauganef95ae32012-05-15 09:50:30 -07002698 /* Rotator dst */
Laura Abbott0577d7b2012-04-17 11:14:30 -07002699 {
2700 .name = "rot_dst",
Olav Hauganef95ae32012-05-15 09:50:30 -07002701 .domain = ROTATOR_DST_DOMAIN,
Laura Abbott0577d7b2012-04-17 11:14:30 -07002702 },
2703 /* Video */
2704 {
2705 .name = "vcodec_a_mm1",
2706 .domain = VIDEO_DOMAIN,
2707 },
2708 /* Video */
2709 {
2710 .name = "vcodec_b_mm2",
2711 .domain = VIDEO_DOMAIN,
2712 },
2713 /* Video */
2714 {
2715 .name = "vcodec_a_stream",
2716 .domain = VIDEO_DOMAIN,
2717 },
2718};
2719
2720static struct mem_pool apq8064_video_pools[] = {
2721 /*
2722 * Video hardware has the following requirements:
2723 * 1. All video addresses used by the video hardware must be at a higher
2724 * address than video firmware address.
2725 * 2. Video hardware can only access a range of 256MB from the base of
2726 * the video firmware.
2727 */
2728 [VIDEO_FIRMWARE_POOL] =
2729 /* Low addresses, intended for video firmware */
2730 {
2731 .paddr = SZ_128K,
2732 .size = SZ_16M - SZ_128K,
2733 },
2734 [VIDEO_MAIN_POOL] =
2735 /* Main video pool */
2736 {
2737 .paddr = SZ_16M,
2738 .size = SZ_256M - SZ_16M,
2739 },
2740 [GEN_POOL] =
2741 /* Remaining address space up to 2G */
2742 {
2743 .paddr = SZ_256M,
2744 .size = SZ_2G - SZ_256M,
2745 },
2746};
2747
2748static struct mem_pool apq8064_camera_pools[] = {
2749 [GEN_POOL] =
2750 /* One address space for camera */
2751 {
2752 .paddr = SZ_128K,
2753 .size = SZ_2G - SZ_128K,
2754 },
2755};
2756
Olav Hauganef95ae32012-05-15 09:50:30 -07002757static struct mem_pool apq8064_display_read_pools[] = {
Laura Abbott0577d7b2012-04-17 11:14:30 -07002758 [GEN_POOL] =
Olav Hauganef95ae32012-05-15 09:50:30 -07002759 /* One address space for display reads */
Laura Abbott0577d7b2012-04-17 11:14:30 -07002760 {
2761 .paddr = SZ_128K,
2762 .size = SZ_2G - SZ_128K,
2763 },
2764};
2765
Olav Hauganef95ae32012-05-15 09:50:30 -07002766static struct mem_pool apq8064_display_write_pools[] = {
Laura Abbott0577d7b2012-04-17 11:14:30 -07002767 [GEN_POOL] =
Olav Hauganef95ae32012-05-15 09:50:30 -07002768 /* One address space for display writes */
2769 {
2770 .paddr = SZ_128K,
2771 .size = SZ_2G - SZ_128K,
2772 },
2773};
2774
2775static struct mem_pool apq8064_rotator_src_pools[] = {
2776 [GEN_POOL] =
2777 /* One address space for rotator src */
2778 {
2779 .paddr = SZ_128K,
2780 .size = SZ_2G - SZ_128K,
2781 },
2782};
2783
2784static struct mem_pool apq8064_rotator_dst_pools[] = {
2785 [GEN_POOL] =
2786 /* One address space for rotator dst */
Laura Abbott0577d7b2012-04-17 11:14:30 -07002787 {
2788 .paddr = SZ_128K,
2789 .size = SZ_2G - SZ_128K,
2790 },
2791};
2792
2793static struct msm_iommu_domain apq8064_iommu_domains[] = {
2794 [VIDEO_DOMAIN] = {
2795 .iova_pools = apq8064_video_pools,
2796 .npools = ARRAY_SIZE(apq8064_video_pools),
2797 },
2798 [CAMERA_DOMAIN] = {
2799 .iova_pools = apq8064_camera_pools,
2800 .npools = ARRAY_SIZE(apq8064_camera_pools),
2801 },
Olav Hauganef95ae32012-05-15 09:50:30 -07002802 [DISPLAY_READ_DOMAIN] = {
2803 .iova_pools = apq8064_display_read_pools,
2804 .npools = ARRAY_SIZE(apq8064_display_read_pools),
Laura Abbott0577d7b2012-04-17 11:14:30 -07002805 },
Olav Hauganef95ae32012-05-15 09:50:30 -07002806 [DISPLAY_WRITE_DOMAIN] = {
2807 .iova_pools = apq8064_display_write_pools,
2808 .npools = ARRAY_SIZE(apq8064_display_write_pools),
2809 },
2810 [ROTATOR_SRC_DOMAIN] = {
2811 .iova_pools = apq8064_rotator_src_pools,
2812 .npools = ARRAY_SIZE(apq8064_rotator_src_pools),
2813 },
2814 [ROTATOR_DST_DOMAIN] = {
2815 .iova_pools = apq8064_rotator_dst_pools,
2816 .npools = ARRAY_SIZE(apq8064_rotator_dst_pools),
Laura Abbott0577d7b2012-04-17 11:14:30 -07002817 },
2818};
2819
2820struct iommu_domains_pdata apq8064_iommu_domain_pdata = {
2821 .domains = apq8064_iommu_domains,
2822 .ndomains = ARRAY_SIZE(apq8064_iommu_domains),
2823 .domain_names = apq8064_iommu_ctx_names,
2824 .nnames = ARRAY_SIZE(apq8064_iommu_ctx_names),
2825 .domain_alloc_flags = 0,
2826};
2827
2828struct platform_device apq8064_iommu_domain_device = {
2829 .name = "iommu_domains",
2830 .id = -1,
2831 .dev = {
2832 .platform_data = &apq8064_iommu_domain_pdata,
Laura Abbott532b2df2012-04-12 10:53:48 -07002833 }
2834};
2835
2836struct msm_rtb_platform_data apq8064_rtb_pdata = {
2837 .size = SZ_1M,
2838};
2839
2840static int __init msm_rtb_set_buffer_size(char *p)
2841{
2842 int s;
2843
2844 s = memparse(p, NULL);
2845 apq8064_rtb_pdata.size = ALIGN(s, SZ_4K);
2846 return 0;
2847}
2848early_param("msm_rtb_size", msm_rtb_set_buffer_size);
2849
2850struct platform_device apq8064_rtb_device = {
2851 .name = "msm_rtb",
2852 .id = -1,
2853 .dev = {
2854 .platform_data = &apq8064_rtb_pdata,
Laura Abbott0577d7b2012-04-17 11:14:30 -07002855 },
2856};
Laura Abbott93a4a352012-05-25 09:26:35 -07002857
2858#define APQ8064_L1_SIZE SZ_1M
2859/*
2860 * The actual L2 size is smaller but we need a larger buffer
2861 * size to store other dump information
2862 */
2863#define APQ8064_L2_SIZE SZ_8M
2864
2865struct msm_cache_dump_platform_data apq8064_cache_dump_pdata = {
2866 .l2_size = APQ8064_L2_SIZE,
2867 .l1_size = APQ8064_L1_SIZE,
2868};
2869
2870struct platform_device apq8064_cache_dump_device = {
2871 .name = "msm_cache_dump",
2872 .id = -1,
2873 .dev = {
2874 .platform_data = &apq8064_cache_dump_pdata,
2875 },
2876};